diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2012-07-09 12:35:41 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2012-07-09 12:35:41 -0400 |
| commit | fda338f8d3ba6f6cb271e2c10cb880ff064edb61 (patch) | |
| tree | 20a91f6acacb2cb40967ce56a539d8444b744b9e /tests/quick/se | |
| parent | b265d9925c123f0df50db98cf56dab6a3596b54b (diff) | |
| download | gem5-fda338f8d3ba6f6cb271e2c10cb880ff064edb61.tar.xz | |
Stats: Updates due to bus changes
This patch bumps all the stats to reflect the bus changes, i.e. the
introduction of the state variable, the division into a request and
response layer, and the new default bus width of 8 bytes.
Diffstat (limited to 'tests/quick/se')
69 files changed, 10003 insertions, 9996 deletions
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/config.ini index 5cc0911e9..e1fc4e09c 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/config.ini @@ -181,7 +181,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side @@ -213,7 +213,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.physmem.port[0] slave=system.system_port system.cpu.l2cache.mem_side diff --git a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/simout b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/simout index b9f1a2caf..da63093c1 100755 --- a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/simout +++ b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 11:50:11 -gem5 started Jun 4 2012 14:15:31 +gem5 compiled Jul 2 2012 08:30:56 +gem5 started Jul 2 2012 09:08:18 gem5 executing on zizzer -command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/inorder-timing -re tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/inorder-timing +command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/quick/se/00.hello/alpha/linux/inorder-timing -re tests/run.py build/ALPHA/tests/fast/quick/se/00.hello/alpha/linux/inorder-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello world! -Exiting @ tick 21234500 because target called exit() +Exiting @ tick 21985500 because target called exit() diff --git a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt index 6887d118d..b38d65b68 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000021 # Number of seconds simulated -sim_ticks 21234500 # Number of ticks simulated -final_tick 21234500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000022 # Number of seconds simulated +sim_ticks 21985500 # Number of ticks simulated +final_tick 21985500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 73768 # Simulator instruction rate (inst/s) -host_op_rate 73752 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 244499363 # Simulator tick rate (ticks/s) -host_mem_usage 214444 # Number of bytes of host memory used -host_seconds 0.09 # Real time elapsed on the host +host_inst_rate 65949 # Simulator instruction rate (inst/s) +host_op_rate 65938 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 226330541 # Simulator tick rate (ticks/s) +host_mem_usage 218192 # Number of bytes of host memory used +host_seconds 0.10 # Real time elapsed on the host sim_insts 6404 # Number of instructions simulated sim_ops 6404 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 19264 # Number of bytes read from this memory @@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 19264 # Nu system.physmem.num_reads::cpu.inst 301 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 168 # Number of read requests responded to by this memory system.physmem.num_reads::total 469 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 907202901 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 506345805 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1413548706 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 907202901 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 907202901 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 907202901 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 506345805 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1413548706 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 876213868 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 489049601 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1365263469 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 876213868 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 876213868 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 876213868 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 489049601 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1365263469 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -35,14 +35,14 @@ system.cpu.dtb.read_hits 1186 # DT system.cpu.dtb.read_misses 7 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations system.cpu.dtb.read_accesses 1193 # DTB read accesses -system.cpu.dtb.write_hits 898 # DTB write hits +system.cpu.dtb.write_hits 900 # DTB write hits system.cpu.dtb.write_misses 3 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 901 # DTB write accesses -system.cpu.dtb.data_hits 2084 # DTB hits +system.cpu.dtb.write_accesses 903 # DTB write accesses +system.cpu.dtb.data_hits 2086 # DTB hits system.cpu.dtb.data_misses 10 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 2094 # DTB accesses +system.cpu.dtb.data_accesses 2096 # DTB accesses system.cpu.itb.fetch_hits 908 # ITB hits system.cpu.itb.fetch_misses 17 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv @@ -60,26 +60,26 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 42470 # number of cpu cycles simulated +system.cpu.numCycles 43972 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.branch_predictor.lookups 1608 # Number of BP lookups -system.cpu.branch_predictor.condPredicted 1127 # Number of conditional branches predicted +system.cpu.branch_predictor.lookups 1607 # Number of BP lookups +system.cpu.branch_predictor.condPredicted 1126 # Number of conditional branches predicted system.cpu.branch_predictor.condIncorrect 712 # Number of conditional branches incorrect -system.cpu.branch_predictor.BTBLookups 1187 # Number of BTB lookups +system.cpu.branch_predictor.BTBLookups 1186 # Number of BTB lookups system.cpu.branch_predictor.BTBHits 314 # Number of BTB hits system.cpu.branch_predictor.usedRAS 126 # Number of times the RAS was used to get a target. system.cpu.branch_predictor.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.branch_predictor.BTBHitPct 26.453243 # BTB Hit Percentage +system.cpu.branch_predictor.BTBHitPct 26.475548 # BTB Hit Percentage system.cpu.branch_predictor.predictedTaken 464 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.predictedNotTaken 1144 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 5213 # Number of Reads from Int. Register File +system.cpu.branch_predictor.predictedNotTaken 1143 # Number of Branches Predicted As Not Taken (False). +system.cpu.regfile_manager.intRegFileReads 5212 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 4580 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 9793 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.intRegFileAccesses 9792 # Total Accesses (Read+Write) to the Int. Register File system.cpu.regfile_manager.floatRegFileReads 8 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 2 # Number of Writes to FP Register File system.cpu.regfile_manager.floatRegFileAccesses 10 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 2970 # Number of Registers Read Through Forwarding Logic +system.cpu.regfile_manager.regForwards 2971 # Number of Registers Read Through Forwarding Logic system.cpu.agen_unit.agens 2183 # Number of Address Generations system.cpu.execution_unit.predictedTakenIncorrect 284 # Number of Branches Incorrectly Predicted As Taken. system.cpu.execution_unit.predictedNotTakenIncorrect 367 # Number of Branches Incorrectly Predicted As Not Taken). @@ -90,12 +90,12 @@ system.cpu.execution_unit.executions 4474 # Nu system.cpu.mult_div_unit.multiplies 1 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 11434 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 12078 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 443 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 35079 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 7391 # Number of cycles cpu stages are processed. -system.cpu.activity 17.402873 # Percentage of cycles cpu is active +system.cpu.timesIdled 536 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 36557 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 7415 # Number of cycles cpu stages are processed. +system.cpu.activity 16.863004 # Percentage of cycles cpu is active system.cpu.comLoads 1185 # Number of Load instructions committed system.cpu.comStores 865 # Number of Store instructions committed system.cpu.comBranches 1051 # Number of Branches instructions committed @@ -107,72 +107,72 @@ system.cpu.committedInsts 6404 # Nu system.cpu.committedOps 6404 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 6404 # Number of Instructions committed (Total) -system.cpu.cpi 6.631793 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 6.866334 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 6.631793 # CPI: Total CPI of All Threads -system.cpu.ipc 0.150789 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 6.866334 # CPI: Total CPI of All Threads +system.cpu.ipc 0.145638 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 0.150789 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 37550 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 4920 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 11.584648 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 38585 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 3885 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 9.147634 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 38290 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 4180 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 9.842242 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 41130 # Number of cycles 0 instructions are processed. -system.cpu.stage3.runCycles 1340 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 3.155168 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 38002 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 4468 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 10.520367 # Percentage of cycles stage was utilized (processing insts). +system.cpu.ipc_total 0.145638 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 39051 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 4921 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 11.191213 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 40084 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 3888 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 8.841990 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 39791 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 4181 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 9.508323 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 42630 # Number of cycles 0 instructions are processed. +system.cpu.stage3.runCycles 1342 # Number of cycles 1+ instructions are processed. +system.cpu.stage3.utilization 3.051942 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 39502 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 4470 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 10.165560 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 138.955928 # Cycle average of tags in use -system.cpu.icache.total_refs 558 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 138.644500 # Cycle average of tags in use +system.cpu.icache.total_refs 557 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 301 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 1.853821 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 1.850498 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 138.955928 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.067850 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.067850 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 558 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 558 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 558 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 558 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 558 # number of overall hits -system.cpu.icache.overall_hits::total 558 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 350 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 350 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 350 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 350 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 350 # number of overall misses -system.cpu.icache.overall_misses::total 350 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 19343500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 19343500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 19343500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 19343500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 19343500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 19343500 # number of overall miss cycles +system.cpu.icache.occ_blocks::cpu.inst 138.644500 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.067698 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.067698 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 557 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 557 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 557 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 557 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 557 # number of overall hits +system.cpu.icache.overall_hits::total 557 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 351 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 351 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 351 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 351 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 351 # number of overall misses +system.cpu.icache.overall_misses::total 351 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 19781500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 19781500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 19781500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 19781500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 19781500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 19781500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 908 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 908 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 908 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::total 908 # number of demand (read+write) accesses system.cpu.icache.overall_accesses::cpu.inst 908 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 908 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.385463 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.385463 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.385463 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.385463 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.385463 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.385463 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55267.142857 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 55267.142857 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 55267.142857 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 55267.142857 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 55267.142857 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 55267.142857 # average overall miss latency +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.386564 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.386564 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.386564 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.386564 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.386564 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.386564 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56357.549858 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 56357.549858 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 56357.549858 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 56357.549858 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 56357.549858 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 56357.549858 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -181,70 +181,70 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 48 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 48 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 48 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 48 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 48 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 48 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 49 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 49 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 49 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 49 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 49 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 49 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 302 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 302 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 302 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 302 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 302 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 302 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 16051500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 16051500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 16051500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 16051500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 16051500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 16051500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 16493500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 16493500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 16493500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 16493500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 16493500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 16493500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.332599 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.332599 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.332599 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.332599 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.332599 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.332599 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53150.662252 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53150.662252 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53150.662252 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 53150.662252 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53150.662252 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 53150.662252 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54614.238411 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54614.238411 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54614.238411 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 54614.238411 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54614.238411 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 54614.238411 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 102.711534 # Cycle average of tags in use -system.cpu.dcache.total_refs 1703 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 102.468585 # Cycle average of tags in use +system.cpu.dcache.total_refs 1702 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 168 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 10.136905 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 10.130952 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 102.711534 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.025076 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.025076 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::cpu.data 102.468585 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.025017 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.025017 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 1088 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1088 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 615 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 615 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 1703 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 1703 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 1703 # number of overall hits -system.cpu.dcache.overall_hits::total 1703 # number of overall hits +system.cpu.dcache.WriteReq_hits::cpu.data 614 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 614 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 1702 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 1702 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 1702 # number of overall hits +system.cpu.dcache.overall_hits::total 1702 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 97 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 97 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 250 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 250 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 347 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 347 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 347 # number of overall misses -system.cpu.dcache.overall_misses::total 347 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5507500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5507500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 13555000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 13555000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 19062500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 19062500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 19062500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 19062500 # number of overall miss cycles +system.cpu.dcache.WriteReq_misses::cpu.data 251 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 251 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 348 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 348 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 348 # number of overall misses +system.cpu.dcache.overall_misses::total 348 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5918000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5918000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 15290000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 15290000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 21208000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 21208000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 21208000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 21208000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 1185 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1185 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses) @@ -255,36 +255,36 @@ system.cpu.dcache.overall_accesses::cpu.data 2050 system.cpu.dcache.overall_accesses::total 2050 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.081857 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.081857 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289017 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.289017 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.169268 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.169268 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.169268 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.169268 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56778.350515 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 56778.350515 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54220 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 54220 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 54935.158501 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 54935.158501 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 54935.158501 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 54935.158501 # average overall miss latency +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.290173 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.290173 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.169756 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.169756 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.169756 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.169756 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 61010.309278 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 61010.309278 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60916.334661 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 60916.334661 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 60942.528736 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 60942.528736 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 60942.528736 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 60942.528736 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 1656000 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 1689000 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 36 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 37 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 46000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 45648.648649 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 2 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 177 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 177 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 179 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 179 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 179 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 179 # number of overall MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 178 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 178 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 180 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 180 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 180 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 180 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 95 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 95 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 73 # number of WriteReq MSHR misses @@ -293,14 +293,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 168 system.cpu.dcache.demand_mshr_misses::total 168 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 168 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5113000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 5113000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3909500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3909500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9022500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 9022500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9022500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 9022500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5509500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 5509500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4096500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4096500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9606000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 9606000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9606000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 9606000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.080169 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.080169 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses @@ -309,26 +309,26 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.081951 system.cpu.dcache.demand_mshr_miss_rate::total 0.081951 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.081951 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.081951 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53821.052632 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53821.052632 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53554.794521 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53554.794521 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53705.357143 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 53705.357143 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53705.357143 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 53705.357143 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 57994.736842 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 57994.736842 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 56116.438356 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 56116.438356 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 57178.571429 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 57178.571429 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 57178.571429 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 57178.571429 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 195.300582 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 194.857279 # Cycle average of tags in use system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 395 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.002532 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 139.031748 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 56.268833 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.004243 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.001717 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.005960 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 138.715070 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 56.142209 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.004233 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.001713 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.005947 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits @@ -346,17 +346,17 @@ system.cpu.l2cache.demand_misses::total 469 # nu system.cpu.l2cache.overall_misses::cpu.inst 301 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 168 # number of overall misses system.cpu.l2cache.overall_misses::total 469 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 15708000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4994000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 20702000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3821500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 3821500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 15708000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 8815500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 24523500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 15708000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 8815500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 24523500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 16152000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 5390000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 21542000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4007500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 4007500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 16152000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 9397500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 25549500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 16152000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 9397500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 25549500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 302 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 95 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 397 # number of ReadReq accesses(hits+misses) @@ -379,17 +379,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.997872 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996689 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.997872 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52186.046512 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52568.421053 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52277.777778 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52349.315068 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52349.315068 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52186.046512 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52473.214286 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52288.912580 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52186.046512 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52473.214286 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52288.912580 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 53661.129568 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 56736.842105 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 54398.989899 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 54897.260274 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 54897.260274 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 53661.129568 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 55937.500000 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 54476.545842 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53661.129568 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 55937.500000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 54476.545842 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -409,17 +409,17 @@ system.cpu.l2cache.demand_mshr_misses::total 469 system.cpu.l2cache.overall_mshr_misses::cpu.inst 301 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 469 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 12038500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3838000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15876500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2942500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2942500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 12038500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6780500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 18819000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 12038500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6780500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 18819000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 12487000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4239000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 16726000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3129500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3129500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 12487000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7368500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 19855500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 12487000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7368500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 19855500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996689 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997481 # mshr miss rate for ReadReq accesses @@ -431,17 +431,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.997872 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996689 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.997872 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 39995.016611 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40400 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40092.171717 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40308.219178 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40308.219178 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 39995.016611 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40360.119048 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40125.799574 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 39995.016611 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40360.119048 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40125.799574 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41485.049834 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 44621.052632 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 42237.373737 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42869.863014 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42869.863014 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41485.049834 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 43860.119048 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42335.820896 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41485.049834 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 43860.119048 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42335.820896 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/config.ini index 280f44c05..fb11f0585 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/config.ini @@ -479,7 +479,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side @@ -511,7 +511,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.physmem.port[0] slave=system.system_port system.cpu.l2cache.mem_side diff --git a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout index da5dd186c..809102793 100755 --- a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout +++ b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 28 2012 22:05:18 -gem5 started Jun 28 2012 22:09:21 +gem5 compiled Jul 2 2012 08:30:56 +gem5 started Jul 2 2012 09:08:18 gem5 executing on zizzer command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/quick/se/00.hello/alpha/linux/o3-timing -re tests/run.py build/ALPHA/tests/fast/quick/se/00.hello/alpha/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello world! -Exiting @ tick 12146500 because target called exit() +Exiting @ tick 12811000 because target called exit() diff --git a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt index 40a9fef11..37f1f46b0 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt @@ -1,52 +1,52 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000012 # Number of seconds simulated -sim_ticks 12146500 # Number of ticks simulated -final_tick 12146500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000013 # Number of seconds simulated +sim_ticks 12811000 # Number of ticks simulated +final_tick 12811000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 109785 # Simulator instruction rate (inst/s) -host_op_rate 109750 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 208686624 # Simulator tick rate (ticks/s) -host_mem_usage 218220 # Number of bytes of host memory used -host_seconds 0.06 # Real time elapsed on the host +host_inst_rate 61639 # Simulator instruction rate (inst/s) +host_op_rate 61622 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 123585600 # Simulator tick rate (ticks/s) +host_mem_usage 219212 # Number of bytes of host memory used +host_seconds 0.10 # Real time elapsed on the host sim_insts 6386 # Number of instructions simulated sim_ops 6386 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 19968 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 11264 # Number of bytes read from this memory -system.physmem.bytes_read::total 31232 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 19968 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 19968 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 312 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 176 # Number of read requests responded to by this memory -system.physmem.num_reads::total 488 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1643930350 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 927345326 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2571275676 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1643930350 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1643930350 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1643930350 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 927345326 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2571275676 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 20096 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 11200 # Number of bytes read from this memory +system.physmem.bytes_read::total 31296 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 20096 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 20096 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 314 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 175 # Number of read requests responded to by this memory +system.physmem.num_reads::total 489 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1568651940 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 874248693 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2442900632 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1568651940 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1568651940 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1568651940 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 874248693 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2442900632 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 1978 # DTB read hits -system.cpu.dtb.read_misses 49 # DTB read misses +system.cpu.dtb.read_hits 1966 # DTB read hits +system.cpu.dtb.read_misses 45 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 2027 # DTB read accesses +system.cpu.dtb.read_accesses 2011 # DTB read accesses system.cpu.dtb.write_hits 1059 # DTB write hits -system.cpu.dtb.write_misses 31 # DTB write misses +system.cpu.dtb.write_misses 28 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 1090 # DTB write accesses -system.cpu.dtb.data_hits 3037 # DTB hits -system.cpu.dtb.data_misses 80 # DTB misses +system.cpu.dtb.write_accesses 1087 # DTB write accesses +system.cpu.dtb.data_hits 3025 # DTB hits +system.cpu.dtb.data_misses 73 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 3117 # DTB accesses -system.cpu.itb.fetch_hits 2279 # ITB hits -system.cpu.itb.fetch_misses 30 # ITB misses +system.cpu.dtb.data_accesses 3098 # DTB accesses +system.cpu.itb.fetch_hits 2254 # ITB hits +system.cpu.itb.fetch_misses 39 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 2309 # ITB accesses +system.cpu.itb.fetch_accesses 2293 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -60,246 +60,246 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 24294 # number of cpu cycles simulated +system.cpu.numCycles 25623 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 2808 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 1620 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 530 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 2127 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 736 # Number of BTB hits +system.cpu.BPredUnit.lookups 2750 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 1591 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 527 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 2077 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 748 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 421 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 67 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 7536 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 16063 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2808 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 1157 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 2867 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1787 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 912 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 23 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 639 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 2279 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 349 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 13192 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.217632 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.600569 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 402 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 69 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 8523 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 15693 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2750 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 1150 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 2817 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1761 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 996 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 25 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 745 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 2254 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 361 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 14299 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.097489 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.491166 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 10325 78.27% 78.27% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 292 2.21% 80.48% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 224 1.70% 82.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 225 1.71% 83.88% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 268 2.03% 85.92% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 190 1.44% 87.36% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 268 2.03% 89.39% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 182 1.38% 90.77% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1218 9.23% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 11482 80.30% 80.30% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 287 2.01% 82.31% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 235 1.64% 83.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 221 1.55% 85.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 257 1.80% 87.29% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 195 1.36% 88.66% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 267 1.87% 90.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 172 1.20% 91.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1183 8.27% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 13192 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.115584 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.661192 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 8379 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 934 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2684 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 63 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1132 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 256 # Number of times decode resolved a branch +system.cpu.fetch.rateDist::total 14299 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.107325 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.612458 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 9448 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 1035 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 2627 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 79 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1110 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 255 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 87 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 14824 # Number of instructions handled by decode +system.cpu.decode.DecodedInsts 14531 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 236 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1132 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 8584 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 335 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 357 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2519 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 265 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 14111 # Number of instructions processed by rename -system.cpu.rename.IQFullEvents 6 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 206 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 10590 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 17651 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 17634 # Number of integer rename lookups +system.cpu.rename.SquashCycles 1110 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 9647 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 356 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 379 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 2494 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 313 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 13871 # Number of instructions processed by rename +system.cpu.rename.IQFullEvents 7 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 268 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 10378 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 17349 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 17332 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 17 # Number of floating rename lookups system.cpu.rename.CommittedMaps 4583 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 6007 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 33 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 27 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 768 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2619 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1317 # Number of stores inserted to the mem dependence unit. +system.cpu.rename.UndoneMaps 5795 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 32 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 26 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 762 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2605 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1307 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 5 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 12558 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 31 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 10419 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 44 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 5861 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 3437 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 14 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 13192 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.789797 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.411802 # Number of insts issued each cycle +system.cpu.iq.iqInstsAdded 12446 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 30 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 10341 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 37 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 5740 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 3350 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 13 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 14299 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.723197 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.354818 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 8893 67.41% 67.41% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1482 11.23% 78.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 1143 8.66% 87.31% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 751 5.69% 93.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 453 3.43% 96.44% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 282 2.14% 98.57% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 149 1.13% 99.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 30 0.23% 99.93% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 9 0.07% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 9905 69.27% 69.27% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1622 11.34% 80.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 1176 8.22% 88.84% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 704 4.92% 93.76% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 444 3.11% 96.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 263 1.84% 98.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 141 0.99% 99.69% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 34 0.24% 99.93% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 10 0.07% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 13192 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 14299 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 8 7.41% 7.41% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 7.41% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 7.41% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 7.41% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 7.41% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 7.41% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 7.41% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 7.41% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 7.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 7.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 7.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 7.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 7.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 7.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 7.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 7.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 7.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 7.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 7.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 7.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 7.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 7.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 7.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 7.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 7.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 7.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 7.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 7.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 7.41% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 64 59.26% 66.67% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 36 33.33% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 8 7.27% 7.27% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 7.27% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 7.27% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 7.27% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 7.27% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 7.27% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 7.27% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 7.27% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 7.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 7.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 7.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 7.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 7.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 7.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 7.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 7.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 7.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 7.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 7.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 7.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 7.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 7.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 7.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 7.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 7.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 7.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 7.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 7.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 7.27% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 65 59.09% 66.36% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 37 33.64% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 7046 67.63% 67.65% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 1 0.01% 67.66% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.66% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 67.67% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.67% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.67% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.67% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.67% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.67% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.67% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.67% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.67% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.67% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.67% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.67% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.67% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.67% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.67% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.67% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.67% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.67% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.67% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.67% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.67% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.67% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.67% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.67% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.67% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.67% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2237 21.47% 89.14% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1131 10.86% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 7000 67.69% 67.71% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 1 0.01% 67.72% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.72% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 67.74% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.74% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.74% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.74% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.74% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.74% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.74% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.74% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.74% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.74% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.74% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.74% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.74% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.74% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.74% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.74% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.74% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.74% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.74% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.74% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.74% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.74% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.74% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.74% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.74% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.74% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2210 21.37% 89.11% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1126 10.89% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 10419 # Type of FU issued -system.cpu.iq.rate 0.428871 # Inst issue rate -system.cpu.iq.fu_busy_cnt 108 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.010366 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 34161 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 18458 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 9433 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 10341 # Type of FU issued +system.cpu.iq.rate 0.403583 # Inst issue rate +system.cpu.iq.fu_busy_cnt 110 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.010637 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 35107 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 18223 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 9409 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 21 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 10 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 10 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 10514 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 10438 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 11 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 65 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 70 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1434 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.squashedLoads 1420 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 4 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 19 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 452 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 442 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1132 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 41 # Number of cycles IEW is blocking +system.cpu.iew.iewSquashCycles 1110 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 39 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 1 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 12672 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 177 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2619 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1317 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 31 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispatchedInsts 12564 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 188 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2605 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1307 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 30 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 19 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 137 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 393 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 530 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 9845 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 2040 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 574 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedTakenIncorrect 139 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 385 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 524 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 9796 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 2022 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 545 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 83 # number of nop insts executed -system.cpu.iew.exec_refs 3133 # number of memory reference insts executed +system.cpu.iew.exec_nop 88 # number of nop insts executed +system.cpu.iew.exec_refs 3112 # number of memory reference insts executed system.cpu.iew.exec_branches 1595 # Number of branches executed -system.cpu.iew.exec_stores 1093 # Number of stores executed -system.cpu.iew.exec_rate 0.405244 # Inst execution rate -system.cpu.iew.wb_sent 9591 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 9443 # cumulative count of insts written-back -system.cpu.iew.wb_producers 4951 # num instructions producing a value -system.cpu.iew.wb_consumers 6720 # num instructions consuming a value +system.cpu.iew.exec_stores 1090 # Number of stores executed +system.cpu.iew.exec_rate 0.382313 # Inst execution rate +system.cpu.iew.wb_sent 9558 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 9419 # cumulative count of insts written-back +system.cpu.iew.wb_producers 4945 # num instructions producing a value +system.cpu.iew.wb_consumers 6634 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.388697 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.736756 # average fanout of values written-back +system.cpu.iew.wb_rate 0.367599 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.745402 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 6403 # The number of committed instructions system.cpu.commit.commitCommittedOps 6403 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 6261 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 6160 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 447 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 12060 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.530929 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.361741 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 444 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 13189 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.485480 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.291478 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 9314 77.23% 77.23% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1447 12.00% 89.23% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 498 4.13% 93.36% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 252 2.09% 95.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 164 1.36% 96.81% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 93 0.77% 97.58% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 106 0.88% 98.46% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 41 0.34% 98.80% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 145 1.20% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 10357 78.53% 78.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1540 11.68% 90.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 523 3.97% 94.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 223 1.69% 95.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 163 1.24% 97.10% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 109 0.83% 97.92% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 106 0.80% 98.73% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 29 0.22% 98.95% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 139 1.05% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 12060 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 13189 # Number of insts commited each cycle system.cpu.commit.committedInsts 6403 # Number of instructions committed system.cpu.commit.committedOps 6403 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -310,70 +310,70 @@ system.cpu.commit.branches 1051 # Nu system.cpu.commit.fp_insts 10 # Number of committed floating point instructions. system.cpu.commit.int_insts 6321 # Number of committed integer instructions. system.cpu.commit.function_calls 127 # Number of function calls committed. -system.cpu.commit.bw_lim_events 145 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 139 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 24228 # The number of ROB reads -system.cpu.rob.rob_writes 26471 # The number of ROB writes -system.cpu.timesIdled 224 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 11102 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 25262 # The number of ROB reads +system.cpu.rob.rob_writes 26244 # The number of ROB writes +system.cpu.timesIdled 278 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 11324 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 6386 # Number of Instructions Simulated system.cpu.committedOps 6386 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 6386 # Number of Instructions Simulated -system.cpu.cpi 3.804259 # CPI: Cycles Per Instruction -system.cpu.cpi_total 3.804259 # CPI: Total CPI of All Threads -system.cpu.ipc 0.262863 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.262863 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 12506 # number of integer regfile reads -system.cpu.int_regfile_writes 7104 # number of integer regfile writes +system.cpu.cpi 4.012371 # CPI: Cycles Per Instruction +system.cpu.cpi_total 4.012371 # CPI: Total CPI of All Threads +system.cpu.ipc 0.249229 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.249229 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 12434 # number of integer regfile reads +system.cpu.int_regfile_writes 7077 # number of integer regfile writes system.cpu.fp_regfile_reads 8 # number of floating regfile reads system.cpu.fp_regfile_writes 2 # number of floating regfile writes system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 161.646618 # Cycle average of tags in use -system.cpu.icache.total_refs 1829 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 313 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 5.843450 # Average number of references to valid blocks. +system.cpu.icache.tagsinuse 159.968477 # Cycle average of tags in use +system.cpu.icache.total_refs 1800 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 315 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 5.714286 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 161.646618 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.078929 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.078929 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 1829 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1829 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1829 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1829 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1829 # number of overall hits -system.cpu.icache.overall_hits::total 1829 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 450 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 450 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 450 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 450 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 450 # number of overall misses -system.cpu.icache.overall_misses::total 450 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 15742000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 15742000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 15742000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 15742000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 15742000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 15742000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 2279 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 2279 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 2279 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 2279 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 2279 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 2279 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.197455 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.197455 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.197455 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.197455 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.197455 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.197455 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34982.222222 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 34982.222222 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 34982.222222 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 34982.222222 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 34982.222222 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 34982.222222 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 159.968477 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.078110 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.078110 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 1800 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1800 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1800 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1800 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1800 # number of overall hits +system.cpu.icache.overall_hits::total 1800 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 454 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 454 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 454 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 454 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 454 # number of overall misses +system.cpu.icache.overall_misses::total 454 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 16294000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 16294000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 16294000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 16294000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 16294000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 16294000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 2254 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 2254 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 2254 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 2254 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 2254 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 2254 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.201420 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.201420 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.201420 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.201420 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.201420 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.201420 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35889.867841 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 35889.867841 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 35889.867841 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 35889.867841 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 35889.867841 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 35889.867841 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -382,94 +382,94 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 137 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 137 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 137 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 137 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 137 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 137 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 313 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 313 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 313 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 313 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 313 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 313 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11060000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 11060000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11060000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 11060000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11060000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 11060000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.137341 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.137341 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.137341 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.137341 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.137341 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.137341 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35335.463259 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 35335.463259 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35335.463259 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 35335.463259 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35335.463259 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 35335.463259 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 139 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 139 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 139 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 139 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 139 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 139 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 315 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 315 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 315 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 315 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 315 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 315 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11617000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 11617000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11617000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 11617000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11617000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 11617000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.139752 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.139752 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.139752 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.139752 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.139752 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.139752 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36879.365079 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 36879.365079 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36879.365079 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 36879.365079 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36879.365079 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 36879.365079 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 109.846299 # Cycle average of tags in use -system.cpu.dcache.total_refs 2275 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 176 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 12.926136 # Average number of references to valid blocks. +system.cpu.dcache.tagsinuse 107.786985 # Cycle average of tags in use +system.cpu.dcache.total_refs 2240 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 174 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 12.873563 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 109.846299 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.026818 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.026818 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 1766 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1766 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 509 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 509 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 2275 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2275 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2275 # number of overall hits -system.cpu.dcache.overall_hits::total 2275 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 146 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 146 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 356 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 356 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 502 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 502 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 502 # number of overall misses -system.cpu.dcache.overall_misses::total 502 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5337000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5337000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 12518000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 12518000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 17855000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 17855000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 17855000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 17855000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1912 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1912 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.occ_blocks::cpu.data 107.786985 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.026315 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.026315 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 1734 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1734 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 506 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 506 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 2240 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2240 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2240 # number of overall hits +system.cpu.dcache.overall_hits::total 2240 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 161 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 161 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 359 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 359 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 520 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 520 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 520 # number of overall misses +system.cpu.dcache.overall_misses::total 520 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 6422000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 6422000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 15048500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 15048500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 21470500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 21470500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 21470500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 21470500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1895 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1895 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2777 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2777 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2777 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2777 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.076360 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.076360 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.411561 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.411561 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.180771 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.180771 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.180771 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.180771 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 36554.794521 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 36554.794521 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35162.921348 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 35162.921348 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 35567.729084 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 35567.729084 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 35567.729084 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 35567.729084 # average overall miss latency +system.cpu.dcache.demand_accesses::cpu.data 2760 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2760 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2760 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2760 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.084960 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.084960 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.415029 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.415029 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.188406 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.188406 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.188406 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.188406 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 39888.198758 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 39888.198758 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41917.827298 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 41917.827298 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 41289.423077 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 41289.423077 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 41289.423077 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 41289.423077 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -478,119 +478,119 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 42 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 42 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 284 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 284 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 326 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 326 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 326 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 326 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 104 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 104 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 72 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 72 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 176 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 176 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 176 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 176 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3764000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 3764000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2575000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2575000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6339000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6339000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6339000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6339000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.054393 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.054393 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.083237 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.083237 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.063378 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.063378 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.063378 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.063378 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 36192.307692 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 36192.307692 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35763.888889 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35763.888889 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 36017.045455 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 36017.045455 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 36017.045455 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 36017.045455 # average overall mshr miss latency +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 59 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 59 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 286 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 286 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 345 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 345 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 345 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 345 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 102 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 102 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 73 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 73 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 175 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 175 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 175 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 175 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4236500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4236500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2874500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2874500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7111000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 7111000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7111000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 7111000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.053826 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.053826 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.063406 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.063406 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.063406 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.063406 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 41534.313725 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 41534.313725 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 39376.712329 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 39376.712329 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 40634.285714 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 40634.285714 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 40634.285714 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 40634.285714 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 224.380125 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 220.452556 # Cycle average of tags in use system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 416 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.002404 # Average number of references to valid blocks. +system.cpu.l2cache.sampled_refs 415 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.002410 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 161.620273 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 62.759852 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.004932 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.001915 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.006848 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 159.940532 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 60.512024 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.004881 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.001847 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.006728 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::total 1 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits system.cpu.l2cache.overall_hits::total 1 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 312 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 104 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.inst 314 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 102 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::total 416 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 72 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 72 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 312 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 176 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 488 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 312 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 176 # number of overall misses -system.cpu.l2cache.overall_misses::total 488 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 10703000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3603500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 14306500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2489000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 2489000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 10703000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 6092500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 16795500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 10703000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 6092500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 16795500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 313 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 104 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_misses::cpu.data 73 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 73 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 314 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 175 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 489 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 314 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 175 # number of overall misses +system.cpu.l2cache.overall_misses::total 489 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 11286500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4103500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 15390000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2793500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 2793500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 11286500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 6897000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 18183500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 11286500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 6897000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 18183500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 315 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 102 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 417 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 72 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 72 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 313 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 176 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 489 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 313 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 176 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 489 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996805 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_accesses::cpu.data 73 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 73 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 315 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 175 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 490 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 315 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 175 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 490 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996825 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::total 0.997602 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996805 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996825 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.997955 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996805 # miss rate for overall accesses +system.cpu.l2cache.demand_miss_rate::total 0.997959 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996825 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.997955 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34304.487179 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34649.038462 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 34390.625000 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34569.444444 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34569.444444 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34304.487179 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34616.477273 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 34417.008197 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34304.487179 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34616.477273 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 34417.008197 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::total 0.997959 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35944.267516 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 40230.392157 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 36995.192308 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 38267.123288 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 38267.123288 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35944.267516 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 39411.428571 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 37185.071575 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35944.267516 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 39411.428571 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 37185.071575 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -599,50 +599,50 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 312 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 104 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 314 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 102 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::total 416 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 72 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 72 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 312 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 176 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 488 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 312 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 176 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 488 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 9702500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3275000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 12977500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2264500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2264500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 9702500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5539500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 15242000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 9702500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5539500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 15242000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996805 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 73 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 73 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 314 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 175 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 489 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 314 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 175 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 489 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10285500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3793000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14078500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2567500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2567500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10285500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6360500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 16646000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10285500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6360500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 16646000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996825 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997602 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996805 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996825 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.997955 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996805 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.997959 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996825 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.997955 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31097.756410 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31490.384615 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31195.913462 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31451.388889 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31451.388889 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31097.756410 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31474.431818 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31233.606557 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31097.756410 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31474.431818 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31233.606557 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.997959 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32756.369427 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 37186.274510 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 33842.548077 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 35171.232877 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 35171.232877 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32756.369427 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 36345.714286 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 34040.899796 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32756.369427 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 36345.714286 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 34040.899796 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/config.ini index b0aed7d88..4b13e207f 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/config.ini @@ -148,7 +148,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side @@ -180,7 +180,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.physmem.port[0] slave=system.system_port system.cpu.l2cache.mem_side diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/simout b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/simout index 00df1b420..776a435c2 100755 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/simout +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 11:50:11 -gem5 started Jun 4 2012 13:52:31 +gem5 compiled Jul 2 2012 08:30:56 +gem5 started Jul 2 2012 09:08:22 gem5 executing on zizzer -command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing -re tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing +command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/quick/se/00.hello/alpha/linux/simple-timing -re tests/run.py build/ALPHA/tests/fast/quick/se/00.hello/alpha/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello world! -Exiting @ tick 33007000 because target called exit() +Exiting @ tick 34425000 because target called exit() diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt index 0370e845f..a9d405edb 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000033 # Number of seconds simulated -sim_ticks 33007000 # Number of ticks simulated -final_tick 33007000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000034 # Number of seconds simulated +sim_ticks 34425000 # Number of ticks simulated +final_tick 34425000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 524144 # Simulator instruction rate (inst/s) -host_op_rate 523337 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2693393609 # Simulator tick rate (ticks/s) -host_mem_usage 214140 # Number of bytes of host memory used -host_seconds 0.01 # Real time elapsed on the host +host_inst_rate 6722 # Simulator instruction rate (inst/s) +host_op_rate 6722 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 36133024 # Simulator tick rate (ticks/s) +host_mem_usage 217168 # Number of bytes of host memory used +host_seconds 0.95 # Real time elapsed on the host sim_insts 6404 # Number of instructions simulated sim_ops 6404 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 17792 # Number of bytes read from this memory @@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 17792 # Nu system.physmem.num_reads::cpu.inst 278 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 168 # Number of read requests responded to by this memory system.physmem.num_reads::total 446 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 539037174 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 325749084 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 864786257 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 539037174 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 539037174 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 539037174 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 325749084 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 864786257 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 516833696 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 312331155 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 829164851 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 516833696 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 516833696 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 516833696 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 312331155 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 829164851 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -60,7 +60,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 66014 # number of cpu cycles simulated +system.cpu.numCycles 68850 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 6404 # Number of instructions committed @@ -79,18 +79,18 @@ system.cpu.num_mem_refs 2060 # nu system.cpu.num_load_insts 1192 # Number of load instructions system.cpu.num_store_insts 868 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 66014 # Number of busy cycles +system.cpu.num_busy_cycles 68850 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 127.883393 # Cycle average of tags in use +system.cpu.icache.tagsinuse 128.155444 # Cycle average of tags in use system.cpu.icache.total_refs 6136 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 279 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 21.992832 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 127.883393 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.062443 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.062443 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::cpu.inst 128.155444 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.062576 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.062576 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 6136 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 6136 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 6136 # number of demand (read+write) hits @@ -161,14 +161,14 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52849.462366 system.cpu.icache.overall_avg_mshr_miss_latency::total 52849.462366 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 103.680615 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 103.856385 # Cycle average of tags in use system.cpu.dcache.total_refs 1882 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 168 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 11.202381 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 103.680615 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.025313 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.025313 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::cpu.data 103.856385 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.025356 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.025356 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 1090 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1090 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 792 # number of WriteReq hits @@ -259,16 +259,16 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 184.342479 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 184.699061 # Cycle average of tags in use system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 373 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.002681 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 127.900723 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 56.441756 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.003903 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.001722 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.005626 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 128.168283 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 56.530778 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.003911 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.001725 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.005637 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/config.ini index 3b6b2b818..0de3d5fa0 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/config.ini @@ -479,7 +479,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side @@ -511,7 +511,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.physmem.port[0] slave=system.system_port system.cpu.l2cache.mem_side diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simout b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simout index 2586fc610..07442c5d8 100755 --- a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simout +++ b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 28 2012 22:05:18 -gem5 started Jun 28 2012 22:09:32 +gem5 compiled Jul 2 2012 08:30:56 +gem5 started Jul 2 2012 09:08:29 gem5 executing on zizzer command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/quick/se/00.hello/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/fast/quick/se/00.hello/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello world! -Exiting @ tick 6934000 because target called exit() +Exiting @ tick 7252000 because target called exit() diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt index 729742f8d..572203942 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000007 # Number of seconds simulated -sim_ticks 6934000 # Number of ticks simulated -final_tick 6934000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 7252000 # Number of ticks simulated +final_tick 7252000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 29510 # Simulator instruction rate (inst/s) -host_op_rate 29504 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 85688409 # Simulator tick rate (ticks/s) -host_mem_usage 217944 # Number of bytes of host memory used -host_seconds 0.08 # Real time elapsed on the host +host_inst_rate 57662 # Simulator instruction rate (inst/s) +host_op_rate 57638 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 175044086 # Simulator tick rate (ticks/s) +host_mem_usage 217908 # Number of bytes of host memory used +host_seconds 0.04 # Real time elapsed on the host sim_insts 2387 # Number of instructions simulated sim_ops 2387 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 12032 # Number of bytes read from this memory @@ -19,34 +19,34 @@ system.physmem.bytes_inst_read::total 12032 # Nu system.physmem.num_reads::cpu.inst 188 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 85 # Number of read requests responded to by this memory system.physmem.num_reads::total 273 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1735217768 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 784539948 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2519757716 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1735217768 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1735217768 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1735217768 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 784539948 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2519757716 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1659128516 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 750137893 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2409266409 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1659128516 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1659128516 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1659128516 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 750137893 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2409266409 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 704 # DTB read hits -system.cpu.dtb.read_misses 36 # DTB read misses +system.cpu.dtb.read_hits 712 # DTB read hits +system.cpu.dtb.read_misses 13 # DTB read misses system.cpu.dtb.read_acv 1 # DTB read access violations -system.cpu.dtb.read_accesses 740 # DTB read accesses -system.cpu.dtb.write_hits 367 # DTB write hits -system.cpu.dtb.write_misses 22 # DTB write misses +system.cpu.dtb.read_accesses 725 # DTB read accesses +system.cpu.dtb.write_hits 368 # DTB write hits +system.cpu.dtb.write_misses 15 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 389 # DTB write accesses -system.cpu.dtb.data_hits 1071 # DTB hits -system.cpu.dtb.data_misses 58 # DTB misses +system.cpu.dtb.write_accesses 383 # DTB write accesses +system.cpu.dtb.data_hits 1080 # DTB hits +system.cpu.dtb.data_misses 28 # DTB misses system.cpu.dtb.data_acv 1 # DTB access violations -system.cpu.dtb.data_accesses 1129 # DTB accesses -system.cpu.itb.fetch_hits 999 # ITB hits +system.cpu.dtb.data_accesses 1108 # DTB accesses +system.cpu.itb.fetch_hits 1014 # ITB hits system.cpu.itb.fetch_misses 30 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 1029 # ITB accesses +system.cpu.itb.fetch_accesses 1044 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -60,246 +60,246 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4 # Number of system calls -system.cpu.numCycles 13869 # number of cpu cycles simulated +system.cpu.numCycles 14505 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 1119 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 563 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 252 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 783 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 216 # Number of BTB hits +system.cpu.BPredUnit.lookups 1131 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 573 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 253 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 782 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 218 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 210 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 34 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 3820 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 6858 # Number of instructions fetch has processed -system.cpu.fetch.Branches 1119 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 426 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 1175 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 850 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 242 # Number of cycles fetch has spent blocked +system.cpu.BPredUnit.usedRAS 211 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 37 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 4349 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 6900 # Number of instructions fetch has processed +system.cpu.fetch.Branches 1131 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 429 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 1183 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 857 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 264 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 17 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 783 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 999 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 170 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 6611 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.037362 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.461313 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.PendingTrapStallCycles 948 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 1014 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 172 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 7341 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.939926 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.361375 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 5436 82.23% 82.23% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 51 0.77% 83.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 129 1.95% 84.95% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 97 1.47% 86.42% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 136 2.06% 88.47% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 62 0.94% 89.41% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 66 1.00% 90.41% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 64 0.97% 91.38% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 570 8.62% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 6158 83.89% 83.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 50 0.68% 84.57% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 129 1.76% 86.32% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 101 1.38% 87.70% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 139 1.89% 89.59% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 62 0.84% 90.44% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 66 0.90% 91.34% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 61 0.83% 92.17% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 575 7.83% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 6611 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.080684 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.494484 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 4718 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 256 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 1133 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 10 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 494 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 166 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 83 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 6102 # Number of instructions handled by decode +system.cpu.fetch.rateDist::total 7341 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.077973 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.475698 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 5395 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 291 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 1141 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 13 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 501 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 167 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 81 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 6151 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 293 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 494 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 4814 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 67 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 147 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 1046 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 43 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 5849 # Number of instructions processed by rename -system.cpu.rename.IQFullEvents 16 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 16 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 4252 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 6619 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 6607 # Number of integer rename lookups +system.cpu.rename.SquashCycles 501 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 5491 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 66 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 174 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 1058 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 51 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 5908 # Number of instructions processed by rename +system.cpu.rename.IQFullEvents 21 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 20 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 4280 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 6676 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 6664 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 12 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1768 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 2484 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 2512 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 8 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 6 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 137 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 945 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 472 # Number of stores inserted to the mem dependence unit. +system.cpu.rename.skidInsts 145 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 960 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 476 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 3 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 3 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 4975 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.memDep0.conflictingStores 4 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 5051 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 6 # Number of non-speculative instructions added to the IQ system.cpu.iq.iqInstsIssued 4026 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 68 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 2372 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1428 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedInstsIssued 79 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 2503 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1510 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 6611 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.608985 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.321430 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 7341 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.548427 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.241979 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 4990 75.48% 75.48% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 583 8.82% 84.30% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 382 5.78% 90.08% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 267 4.04% 94.12% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 192 2.90% 97.02% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 114 1.72% 98.74% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 53 0.80% 99.55% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 18 0.27% 99.82% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 12 0.18% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 5680 77.37% 77.37% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 617 8.40% 85.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 387 5.27% 91.05% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 273 3.72% 94.77% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 198 2.70% 97.47% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 114 1.55% 99.02% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 56 0.76% 99.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 10 0.14% 99.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 6 0.08% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 6611 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 7341 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 4 9.09% 9.09% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 9.09% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 9.09% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 9.09% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 9.09% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 9.09% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 9.09% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 9.09% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 9.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 9.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 9.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 9.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 9.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 9.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 9.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 9.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 9.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 9.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 9.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 9.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 9.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 9.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 9.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 9.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 9.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 9.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 9.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.09% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 17 38.64% 47.73% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 23 52.27% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 2 4.88% 4.88% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 4.88% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 4.88% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.88% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.88% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.88% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 4.88% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.88% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 4.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 4.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.88% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 17 41.46% 46.34% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 22 53.66% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 2853 70.86% 70.86% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 1 0.02% 70.89% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.89% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.89% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.89% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 70.89% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 70.89% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 70.89% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 70.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 70.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 70.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 70.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 70.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 70.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 70.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 70.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 70.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 70.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 70.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 70.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 70.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 70.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 70.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.89% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 775 19.25% 90.14% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 397 9.86% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 2876 71.44% 71.44% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 1 0.02% 71.46% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 71.46% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 71.46% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 71.46% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 71.46% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 71.46% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 71.46% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 71.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 71.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 71.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 71.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 71.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 71.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 71.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 71.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 71.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 71.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 71.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 71.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 71.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 71.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 71.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 71.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 71.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 71.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 71.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 71.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 71.46% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 761 18.90% 90.36% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 388 9.64% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::total 4026 # Type of FU issued -system.cpu.iq.rate 0.290288 # Inst issue rate -system.cpu.iq.fu_busy_cnt 44 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.010929 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 14762 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 7351 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 3682 # Number of integer instruction queue wakeup accesses +system.cpu.iq.rate 0.277559 # Inst issue rate +system.cpu.iq.fu_busy_cnt 41 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.010184 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 15500 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 7558 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 3688 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 13 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 6 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 6 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 4063 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 4060 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 7 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 31 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 33 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 530 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 545 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 5 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 178 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 182 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 494 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 53 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 6 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 5319 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 96 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 945 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 472 # Number of dispatched store instructions +system.cpu.iew.iewSquashCycles 501 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 55 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 5 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 5407 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 98 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 960 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 476 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 6 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 6 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewIQFullEvents 4 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 5 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 54 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 153 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 57 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 150 # Number of branches that were predicted not taken incorrectly system.cpu.iew.branchMispredicts 207 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 3873 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 741 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 153 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 3874 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 726 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 152 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 338 # number of nop insts executed -system.cpu.iew.exec_refs 1130 # number of memory reference insts executed -system.cpu.iew.exec_branches 650 # Number of branches executed -system.cpu.iew.exec_stores 389 # Number of stores executed -system.cpu.iew.exec_rate 0.279256 # Inst execution rate -system.cpu.iew.wb_sent 3778 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 3688 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1732 # num instructions producing a value -system.cpu.iew.wb_consumers 2249 # num instructions consuming a value +system.cpu.iew.exec_nop 350 # number of nop insts executed +system.cpu.iew.exec_refs 1109 # number of memory reference insts executed +system.cpu.iew.exec_branches 649 # Number of branches executed +system.cpu.iew.exec_stores 383 # Number of stores executed +system.cpu.iew.exec_rate 0.267080 # Inst execution rate +system.cpu.iew.wb_sent 3756 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 3694 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1740 # num instructions producing a value +system.cpu.iew.wb_consumers 2202 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.265917 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.770120 # average fanout of values written-back +system.cpu.iew.wb_rate 0.254671 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.790191 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 2576 # The number of committed instructions system.cpu.commit.commitCommittedOps 2576 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 2738 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 2822 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 4 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 172 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 6117 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.421121 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.275697 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 174 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 6840 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.376608 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.225423 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 5226 85.43% 85.43% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 218 3.56% 89.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 319 5.21% 94.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 117 1.91% 96.13% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 69 1.13% 97.25% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 56 0.92% 98.17% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 32 0.52% 98.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 19 0.31% 99.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 61 1.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 5956 87.08% 87.08% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 217 3.17% 90.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 318 4.65% 94.90% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 115 1.68% 96.58% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 67 0.98% 97.56% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 47 0.69% 98.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 32 0.47% 98.71% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 21 0.31% 99.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 67 0.98% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 6117 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 6840 # Number of insts commited each cycle system.cpu.commit.committedInsts 2576 # Number of instructions committed system.cpu.commit.committedOps 2576 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -310,69 +310,69 @@ system.cpu.commit.branches 396 # Nu system.cpu.commit.fp_insts 6 # Number of committed floating point instructions. system.cpu.commit.int_insts 2367 # Number of committed integer instructions. system.cpu.commit.function_calls 71 # Number of function calls committed. -system.cpu.commit.bw_lim_events 61 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 67 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 11123 # The number of ROB reads -system.cpu.rob.rob_writes 11131 # The number of ROB writes -system.cpu.timesIdled 138 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 7258 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 11924 # The number of ROB reads +system.cpu.rob.rob_writes 11305 # The number of ROB writes +system.cpu.timesIdled 172 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 7164 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 2387 # Number of Instructions Simulated system.cpu.committedOps 2387 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 2387 # Number of Instructions Simulated -system.cpu.cpi 5.810222 # CPI: Cycles Per Instruction -system.cpu.cpi_total 5.810222 # CPI: Total CPI of All Threads -system.cpu.ipc 0.172110 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.172110 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 4695 # number of integer regfile reads -system.cpu.int_regfile_writes 2856 # number of integer regfile writes +system.cpu.cpi 6.076665 # CPI: Cycles Per Instruction +system.cpu.cpi_total 6.076665 # CPI: Total CPI of All Threads +system.cpu.ipc 0.164564 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.164564 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 4677 # number of integer regfile reads +system.cpu.int_regfile_writes 2861 # number of integer regfile writes system.cpu.fp_regfile_reads 6 # number of floating regfile reads system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 93.248355 # Cycle average of tags in use -system.cpu.icache.total_refs 752 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 94.201337 # Cycle average of tags in use +system.cpu.icache.total_refs 769 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 188 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 4 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 4.090426 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 93.248355 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.045531 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.045531 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 752 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 752 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 752 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 752 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 752 # number of overall hits -system.cpu.icache.overall_hits::total 752 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 247 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 247 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 247 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 247 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 247 # number of overall misses -system.cpu.icache.overall_misses::total 247 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 8946000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 8946000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 8946000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 8946000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 8946000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 8946000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 999 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 999 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 999 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 999 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 999 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 999 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.247247 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.247247 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.247247 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.247247 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.247247 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.247247 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 36218.623482 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 36218.623482 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 36218.623482 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 36218.623482 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 36218.623482 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 36218.623482 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 94.201337 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.045997 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.045997 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 769 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 769 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 769 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 769 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 769 # number of overall hits +system.cpu.icache.overall_hits::total 769 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 245 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 245 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 245 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 245 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 245 # number of overall misses +system.cpu.icache.overall_misses::total 245 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 9112500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 9112500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 9112500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 9112500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 9112500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 9112500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1014 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1014 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1014 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1014 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1014 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1014 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.241617 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.241617 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.241617 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.241617 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.241617 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.241617 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 37193.877551 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 37193.877551 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 37193.877551 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 37193.877551 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 37193.877551 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 37193.877551 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -381,94 +381,94 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 59 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 59 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 59 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 59 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 59 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 59 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 57 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 57 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 57 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 57 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 57 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 57 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 188 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 188 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 188 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 188 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 188 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 188 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 6660500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 6660500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 6660500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 6660500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 6660500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 6660500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.188188 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.188188 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.188188 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.188188 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.188188 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.188188 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35428.191489 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 35428.191489 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35428.191489 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 35428.191489 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35428.191489 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 35428.191489 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 6932500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 6932500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 6932500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 6932500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 6932500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 6932500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.185404 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.185404 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.185404 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.185404 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.185404 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.185404 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36875 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 36875 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36875 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 36875 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36875 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 36875 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 45.780075 # Cycle average of tags in use -system.cpu.dcache.total_refs 785 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 45.851495 # Cycle average of tags in use +system.cpu.dcache.total_refs 774 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 85 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 9.235294 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 9.105882 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 45.780075 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.011177 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.011177 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 563 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 563 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 222 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 222 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 785 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 785 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 785 # number of overall hits -system.cpu.dcache.overall_hits::total 785 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 110 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 110 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 72 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 72 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 182 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 182 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 182 # number of overall misses -system.cpu.dcache.overall_misses::total 182 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 3679000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 3679000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 2813500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 2813500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 6492500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 6492500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 6492500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 6492500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 673 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 673 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.occ_blocks::cpu.data 45.851495 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.011194 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.011194 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 561 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 561 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 213 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 213 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 774 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 774 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 774 # number of overall hits +system.cpu.dcache.overall_hits::total 774 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 118 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 118 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 81 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 81 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 199 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 199 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 199 # number of overall misses +system.cpu.dcache.overall_misses::total 199 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 4328500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 4328500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 3561500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 3561500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 7890000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 7890000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 7890000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 7890000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 679 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 679 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 294 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 294 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 967 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 967 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 967 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 967 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.163447 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.163447 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.244898 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.244898 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.188211 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.188211 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.188211 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.188211 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 33445.454545 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 33445.454545 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39076.388889 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 39076.388889 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 35673.076923 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 35673.076923 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 35673.076923 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 35673.076923 # average overall miss latency +system.cpu.dcache.demand_accesses::cpu.data 973 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 973 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 973 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 973 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.173785 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.173785 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.275510 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.275510 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.204522 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.204522 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.204522 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.204522 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 36682.203390 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 36682.203390 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 43969.135802 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 43969.135802 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 39648.241206 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 39648.241206 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 39648.241206 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 39648.241206 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -477,14 +477,14 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 49 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 49 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 48 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 48 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 97 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 97 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 97 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 97 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 57 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 57 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 57 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 57 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 114 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 114 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 114 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 114 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 61 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 61 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 24 # number of WriteReq MSHR misses @@ -493,42 +493,42 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 85 system.cpu.dcache.demand_mshr_misses::total 85 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 85 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 85 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2166000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2166000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 871000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 871000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 3037000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 3037000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 3037000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 3037000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.090639 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.090639 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2511500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2511500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 981000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 981000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 3492500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 3492500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 3492500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 3492500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.089838 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.089838 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.081633 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.081633 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.087901 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.087901 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.087901 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.087901 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 35508.196721 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 35508.196721 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 36291.666667 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 36291.666667 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 35729.411765 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 35729.411765 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 35729.411765 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 35729.411765 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.087359 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.087359 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.087359 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.087359 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 41172.131148 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 41172.131148 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 40875 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40875 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 41088.235294 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 41088.235294 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 41088.235294 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 41088.235294 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 122.119430 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 123.109780 # Cycle average of tags in use system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 249 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 93.334885 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 28.784545 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.002848 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.000878 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.003727 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 94.284624 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 28.825156 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.002877 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.000880 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.003757 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_misses::cpu.inst 188 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.data 61 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::total 249 # number of ReadReq misses @@ -540,17 +540,17 @@ system.cpu.l2cache.demand_misses::total 273 # nu system.cpu.l2cache.overall_misses::cpu.inst 188 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 85 # number of overall misses system.cpu.l2cache.overall_misses::total 273 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 6449000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2098500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 8547500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 830000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 830000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 6449000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 2928500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 9377500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 6449000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 2928500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 9377500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 6740500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2447000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 9187500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 950000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 950000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 6740500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 3397000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 10137500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 6740500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 3397000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 10137500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 188 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 61 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 249 # number of ReadReq accesses(hits+misses) @@ -573,17 +573,17 @@ system.cpu.l2cache.demand_miss_rate::total 1 # system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 1 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34303.191489 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34401.639344 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 34327.309237 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34583.333333 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34583.333333 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34303.191489 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34452.941176 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 34349.816850 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34303.191489 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34452.941176 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 34349.816850 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35853.723404 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 40114.754098 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 36897.590361 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 39583.333333 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 39583.333333 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35853.723404 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 39964.705882 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 37133.699634 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35853.723404 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 39964.705882 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 37133.699634 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -603,17 +603,17 @@ system.cpu.l2cache.demand_mshr_misses::total 273 system.cpu.l2cache.overall_mshr_misses::cpu.inst 188 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 85 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 273 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 5849000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1904500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 7753500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 755000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 755000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 5849000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 2659500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 8508500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 5849000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 2659500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 8508500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 6136500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2258000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 8394500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 876000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 876000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 6136500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3134000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 9270500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 6136500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3134000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 9270500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -625,17 +625,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 1 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31111.702128 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31221.311475 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31138.554217 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31458.333333 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31458.333333 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31111.702128 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31288.235294 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31166.666667 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31111.702128 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31288.235294 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31166.666667 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32640.957447 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 37016.393443 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 33712.851406 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36500 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32640.957447 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 36870.588235 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 33957.875458 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32640.957447 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 36870.588235 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 33957.875458 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/config.ini index 3d54d7382..b94afa836 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/config.ini @@ -148,7 +148,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side @@ -180,7 +180,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.physmem.port[0] slave=system.system_port system.cpu.l2cache.mem_side diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/simout b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/simout index 803a08b4e..95893429b 100755 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/simout +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 11:50:11 -gem5 started Jun 4 2012 14:39:41 +gem5 compiled Jul 2 2012 08:30:56 +gem5 started Jul 2 2012 09:08:33 gem5 executing on zizzer -command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing +command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/quick/se/00.hello/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/fast/quick/se/00.hello/alpha/tru64/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello world! -Exiting @ tick 16769000 because target called exit() +Exiting @ tick 17541000 because target called exit() diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt index fab613981..aabb78aae 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000017 # Number of seconds simulated -sim_ticks 16769000 # Number of ticks simulated -final_tick 16769000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000018 # Number of seconds simulated +sim_ticks 17541000 # Number of ticks simulated +final_tick 17541000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 308591 # Simulator instruction rate (inst/s) -host_op_rate 307918 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1999557615 # Simulator tick rate (ticks/s) -host_mem_usage 213304 # Number of bytes of host memory used +host_inst_rate 207586 # Simulator instruction rate (inst/s) +host_op_rate 207300 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1409208031 # Simulator tick rate (ticks/s) +host_mem_usage 216876 # Number of bytes of host memory used host_seconds 0.01 # Real time elapsed on the host sim_insts 2577 # Number of instructions simulated sim_ops 2577 # Number of ops (including micro ops) simulated @@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 10432 # Nu system.physmem.num_reads::cpu.inst 163 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 82 # Number of read requests responded to by this memory system.physmem.num_reads::total 245 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 622100304 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 312958435 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 935058739 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 622100304 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 622100304 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 622100304 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 312958435 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 935058739 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 594720940 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 299184767 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 893905707 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 594720940 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 594720940 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 594720940 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 299184767 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 893905707 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -60,7 +60,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4 # Number of system calls -system.cpu.numCycles 33538 # number of cpu cycles simulated +system.cpu.numCycles 35082 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 2577 # Number of instructions committed @@ -79,18 +79,18 @@ system.cpu.num_mem_refs 717 # nu system.cpu.num_load_insts 419 # Number of load instructions system.cpu.num_store_insts 298 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 33538 # Number of busy cycles +system.cpu.num_busy_cycles 35082 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 80.003762 # Cycle average of tags in use +system.cpu.icache.tagsinuse 80.027768 # Cycle average of tags in use system.cpu.icache.total_refs 2423 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 163 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 14.865031 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 80.003762 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.039064 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.039064 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::cpu.inst 80.027768 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.039076 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.039076 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 2423 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 2423 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 2423 # number of demand (read+write) hits @@ -161,14 +161,14 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53000 system.cpu.icache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 47.418751 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 47.439715 # Cycle average of tags in use system.cpu.dcache.total_refs 627 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 82 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 7.646341 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 47.418751 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.011577 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.011577 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::cpu.data 47.439715 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.011582 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.011582 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 360 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 360 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 267 # number of WriteReq hits @@ -259,16 +259,16 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 107.101205 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 107.121835 # Cycle average of tags in use system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 218 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 80.120406 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 26.980800 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.002445 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 80.139278 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 26.982557 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.002446 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.000823 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.003268 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.003269 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_misses::cpu.inst 163 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.data 55 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::total 218 # number of ReadReq misses diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini index d0f59b4b6..f2874fc12 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini @@ -556,7 +556,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.checker.itb.walker.port system.cpu.checker.dtb.walker.port @@ -588,7 +588,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.physmem.port[0] slave=system.system_port system.cpu.l2cache.mem_side diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout index c374c028c..3b3dd4083 100755 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout @@ -1,11 +1,11 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 28 2012 22:10:14 -gem5 started Jun 29 2012 00:34:53 +gem5 compiled Jul 2 2012 09:08:16 +gem5 started Jul 2 2012 15:18:47 gem5 executing on zizzer command line: build/ARM/gem5.fast -d build/ARM/tests/fast/quick/se/00.hello/arm/linux/o3-timing-checker -re tests/run.py build/ARM/tests/fast/quick/se/00.hello/arm/linux/o3-timing-checker Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 10305000 because target called exit() +Exiting @ tick 10843000 because target called exit() diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt index 9b64fc302..e9752a794 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt @@ -1,32 +1,32 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000010 # Number of seconds simulated -sim_ticks 10305000 # Number of ticks simulated -final_tick 10305000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000011 # Number of seconds simulated +sim_ticks 10843000 # Number of ticks simulated +final_tick 10843000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 40668 # Simulator instruction rate (inst/s) -host_op_rate 50741 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 91257316 # Simulator tick rate (ticks/s) -host_mem_usage 232684 # Number of bytes of host memory used -host_seconds 0.11 # Real time elapsed on the host +host_inst_rate 27388 # Simulator instruction rate (inst/s) +host_op_rate 34173 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 64670790 # Simulator tick rate (ticks/s) +host_mem_usage 232736 # Number of bytes of host memory used +host_seconds 0.17 # Real time elapsed on the host sim_insts 4591 # Number of instructions simulated sim_ops 5729 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 17664 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 17600 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 7872 # Number of bytes read from this memory -system.physmem.bytes_read::total 25536 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 17664 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 17664 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 276 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 25472 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 17600 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 17600 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 275 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 123 # Number of read requests responded to by this memory -system.physmem.num_reads::total 399 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1714119360 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 763901019 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2478020378 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1714119360 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1714119360 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1714119360 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 763901019 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2478020378 # Total bandwidth to/from this memory (bytes/s) +system.physmem.num_reads::total 398 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1623167020 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 725998340 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2349165360 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1623167020 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1623167020 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1623167020 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 725998340 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2349165360 # Total bandwidth to/from this memory (bytes/s) system.cpu.checker.dtb.inst_hits 0 # ITB inst hits system.cpu.checker.dtb.inst_misses 0 # ITB inst misses system.cpu.checker.dtb.read_hits 0 # DTB read hits @@ -115,245 +115,245 @@ system.cpu.itb.inst_accesses 0 # IT system.cpu.itb.hits 0 # DTB hits system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses -system.cpu.numCycles 20611 # number of cpu cycles simulated +system.cpu.numCycles 21687 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 2522 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 1857 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 445 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 1967 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 669 # Number of BTB hits +system.cpu.BPredUnit.lookups 2517 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 1836 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 456 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 1920 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 676 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 255 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.usedRAS 253 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 57 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 6205 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 12809 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2522 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 924 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 2802 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1712 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 1810 # Number of cycles fetch has spent blocked +system.cpu.fetch.icacheStallCycles 7080 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 12862 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2517 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 929 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 2805 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1740 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 2260 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.CacheLines 1996 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 298 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 11993 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.366631 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.761460 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 1997 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 304 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 13334 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.230988 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.652427 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 9191 76.64% 76.64% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 251 2.09% 78.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 179 1.49% 80.22% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 222 1.85% 82.07% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 215 1.79% 83.87% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 290 2.42% 86.28% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 118 0.98% 87.27% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 119 0.99% 88.26% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1408 11.74% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 10529 78.96% 78.96% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 255 1.91% 80.88% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 171 1.28% 82.16% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 221 1.66% 83.82% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 220 1.65% 85.47% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 289 2.17% 87.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 122 0.91% 88.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 119 0.89% 89.44% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1408 10.56% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 11993 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.122362 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.621464 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 6357 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 1977 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2573 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 70 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1016 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 444 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 163 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 14344 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 551 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1016 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 6632 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 279 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 1507 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2368 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 191 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 13444 # Number of instructions processed by rename -system.cpu.rename.IQFullEvents 12 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 160 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 13077 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 61779 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 60371 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 1408 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 13334 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.116060 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.593074 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 7240 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 2427 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 2551 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 88 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1028 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 446 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 164 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 14296 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 558 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1028 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 7514 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 500 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 1638 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 2347 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 307 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 13390 # Number of instructions processed by rename +system.cpu.rename.IQFullEvents 19 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 246 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 13047 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 61618 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 60098 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 1520 # Number of floating rename lookups system.cpu.rename.CommittedMaps 5673 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 7404 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 45 # count of serializing insts renamed +system.cpu.rename.UndoneMaps 7374 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 46 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 42 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 627 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2891 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1788 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 40 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 23 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 11732 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 51 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 9186 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 117 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 5655 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 16152 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 14 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 11993 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.765947 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.466891 # Number of insts issued each cycle +system.cpu.rename.skidInsts 753 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2834 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1819 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 45 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 25 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 11727 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 53 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 9087 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 132 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 5777 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 16432 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 16 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 13334 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.681491 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.365437 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 8390 69.96% 69.96% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1302 10.86% 80.81% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 789 6.58% 87.39% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 542 4.52% 91.91% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 463 3.86% 95.77% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 295 2.46% 98.23% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 149 1.24% 99.47% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 45 0.38% 99.85% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 18 0.15% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 9565 71.73% 71.73% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1503 11.27% 83.01% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 815 6.11% 89.12% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 548 4.11% 93.23% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 447 3.35% 96.58% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 275 2.06% 98.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 130 0.97% 99.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 41 0.31% 99.93% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 10 0.07% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 11993 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 13334 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 3 1.38% 1.38% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 1.38% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 1.38% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.38% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.38% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.38% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 1.38% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.38% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 1.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 1.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.38% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 150 69.12% 70.51% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 64 29.49% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 6 2.86% 2.86% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 2.86% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 2.86% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.86% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.86% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.86% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 2.86% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.86% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 2.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 2.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.86% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 142 67.62% 70.48% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 62 29.52% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 5505 59.93% 59.93% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 7 0.08% 60.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.00% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.00% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.00% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.00% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.00% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.00% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.04% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.04% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.04% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.04% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2406 26.19% 86.23% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1265 13.77% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 5478 60.28% 60.28% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 8 0.09% 60.37% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.37% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.37% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.37% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.37% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.37% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.37% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.40% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.40% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.40% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.40% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2349 25.85% 86.26% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1249 13.74% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 9186 # Type of FU issued -system.cpu.iq.rate 0.445684 # Inst issue rate -system.cpu.iq.fu_busy_cnt 217 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.023623 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 30663 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 17408 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 8220 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 9087 # Type of FU issued +system.cpu.iq.rate 0.419007 # Inst issue rate +system.cpu.iq.fu_busy_cnt 210 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.023110 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 31814 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 17497 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 8174 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 46 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_writes 76 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 9383 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 9277 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 64 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 57 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1691 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.squashedLoads 1634 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 19 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 850 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 881 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1016 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 175 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 21 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 11783 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 140 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2891 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1788 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 39 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 13 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 1028 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 203 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 24 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 11780 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 137 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2834 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1819 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 41 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 14 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 1 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 19 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 88 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 319 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 407 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 8719 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 2169 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 467 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedTakenIncorrect 89 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 334 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 423 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 8660 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 2140 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 427 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 3377 # number of memory reference insts executed -system.cpu.iew.exec_branches 1400 # Number of branches executed -system.cpu.iew.exec_stores 1208 # Number of stores executed -system.cpu.iew.exec_rate 0.423027 # Inst execution rate -system.cpu.iew.wb_sent 8403 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 8236 # cumulative count of insts written-back -system.cpu.iew.wb_producers 3901 # num instructions producing a value -system.cpu.iew.wb_consumers 7899 # num instructions consuming a value +system.cpu.iew.exec_refs 3344 # number of memory reference insts executed +system.cpu.iew.exec_branches 1407 # Number of branches executed +system.cpu.iew.exec_stores 1204 # Number of stores executed +system.cpu.iew.exec_rate 0.399318 # Inst execution rate +system.cpu.iew.wb_sent 8336 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 8190 # cumulative count of insts written-back +system.cpu.iew.wb_producers 3858 # num instructions producing a value +system.cpu.iew.wb_consumers 7806 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.399592 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.493860 # average fanout of values written-back +system.cpu.iew.wb_rate 0.377646 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.494235 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 4591 # The number of committed instructions system.cpu.commit.commitCommittedOps 5729 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 6053 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 6051 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 355 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 10978 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.521862 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.331986 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 369 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 12307 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.465507 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.263835 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 8629 78.60% 78.60% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1108 10.09% 88.70% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 430 3.92% 92.61% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 264 2.40% 95.02% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 184 1.68% 96.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 173 1.58% 98.27% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 56 0.51% 98.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 40 0.36% 99.14% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 94 0.86% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 9888 80.34% 80.34% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1205 9.79% 90.14% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 432 3.51% 93.65% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 264 2.15% 95.79% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 159 1.29% 97.08% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 164 1.33% 98.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 55 0.45% 98.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 38 0.31% 99.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 102 0.83% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 10978 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 12307 # Number of insts commited each cycle system.cpu.commit.committedInsts 4591 # Number of instructions committed system.cpu.commit.committedOps 5729 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -364,69 +364,69 @@ system.cpu.commit.branches 944 # Nu system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. system.cpu.commit.int_insts 4976 # Number of committed integer instructions. system.cpu.commit.function_calls 82 # Number of function calls committed. -system.cpu.commit.bw_lim_events 94 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 102 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 22509 # The number of ROB reads -system.cpu.rob.rob_writes 24591 # The number of ROB writes -system.cpu.timesIdled 178 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 8618 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 23828 # The number of ROB reads +system.cpu.rob.rob_writes 24602 # The number of ROB writes +system.cpu.timesIdled 202 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 8353 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 4591 # Number of Instructions Simulated system.cpu.committedOps 5729 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 4591 # Number of Instructions Simulated -system.cpu.cpi 4.489436 # CPI: Cycles Per Instruction -system.cpu.cpi_total 4.489436 # CPI: Total CPI of All Threads -system.cpu.ipc 0.222745 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.222745 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 40006 # number of integer regfile reads -system.cpu.int_regfile_writes 8113 # number of integer regfile writes +system.cpu.cpi 4.723807 # CPI: Cycles Per Instruction +system.cpu.cpi_total 4.723807 # CPI: Total CPI of All Threads +system.cpu.ipc 0.211694 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.211694 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 39657 # number of integer regfile reads +system.cpu.int_regfile_writes 8076 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.misc_regfile_reads 15846 # number of misc regfile reads +system.cpu.misc_regfile_reads 15863 # number of misc regfile reads system.cpu.misc_regfile_writes 24 # number of misc regfile writes system.cpu.icache.replacements 5 # number of replacements -system.cpu.icache.tagsinuse 150.103653 # Cycle average of tags in use -system.cpu.icache.total_refs 1637 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 149.186170 # Cycle average of tags in use +system.cpu.icache.total_refs 1630 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 296 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 5.530405 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 5.506757 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 150.103653 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.073293 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.073293 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 1637 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1637 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1637 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1637 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1637 # number of overall hits -system.cpu.icache.overall_hits::total 1637 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 359 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 359 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 359 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 359 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 359 # number of overall misses -system.cpu.icache.overall_misses::total 359 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 12452500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 12452500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 12452500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 12452500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 12452500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 12452500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1996 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1996 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1996 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1996 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1996 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1996 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.179860 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.179860 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.179860 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.179860 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.179860 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.179860 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34686.629526 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 34686.629526 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 34686.629526 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 34686.629526 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 34686.629526 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 34686.629526 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 149.186170 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.072845 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.072845 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 1630 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1630 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1630 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1630 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1630 # number of overall hits +system.cpu.icache.overall_hits::total 1630 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 367 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 367 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 367 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 367 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 367 # number of overall misses +system.cpu.icache.overall_misses::total 367 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 13154000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 13154000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 13154000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 13154000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 13154000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 13154000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1997 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1997 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1997 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1997 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1997 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1997 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.183776 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.183776 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.183776 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.183776 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.183776 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.183776 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35841.961853 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 35841.961853 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 35841.961853 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 35841.961853 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 35841.961853 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 35841.961853 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -435,110 +435,110 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 63 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 63 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 63 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 63 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 63 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 63 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 71 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 71 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 71 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 71 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 71 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 71 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 296 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 296 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 296 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 296 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 296 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 296 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9831500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 9831500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9831500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 9831500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9831500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 9831500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.148297 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.148297 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.148297 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.148297 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.148297 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.148297 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 33214.527027 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 33214.527027 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 33214.527027 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 33214.527027 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 33214.527027 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 33214.527027 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 10405500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 10405500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 10405500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 10405500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 10405500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 10405500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.148222 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.148222 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.148222 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.148222 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.148222 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.148222 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35153.716216 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 35153.716216 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35153.716216 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 35153.716216 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35153.716216 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 35153.716216 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 87.680549 # Cycle average of tags in use -system.cpu.dcache.total_refs 2445 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 86.628845 # Cycle average of tags in use +system.cpu.dcache.total_refs 2404 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 149 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 16.409396 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 16.134228 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 87.680549 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.021406 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.021406 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 1816 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1816 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 609 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 609 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 9 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 9 # number of LoadLockedReq hits +system.cpu.dcache.occ_blocks::cpu.data 86.628845 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.021150 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.021150 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 1780 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1780 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 602 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 602 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 11 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 11 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 2425 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2425 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2425 # number of overall hits -system.cpu.dcache.overall_hits::total 2425 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 173 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 173 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 304 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 304 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 2382 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2382 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2382 # number of overall hits +system.cpu.dcache.overall_hits::total 2382 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 190 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 190 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 311 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 311 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 477 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 477 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 477 # number of overall misses -system.cpu.dcache.overall_misses::total 477 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5540500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5540500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 10913500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 10913500 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 501 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 501 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 501 # number of overall misses +system.cpu.dcache.overall_misses::total 501 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 6900500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 6900500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 12710500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 12710500 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 76500 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 76500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 16454000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 16454000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 16454000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 16454000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1989 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1989 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 19611000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 19611000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 19611000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 19611000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1970 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1970 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 11 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 13 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 13 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2902 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2902 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2902 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2902 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.086978 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.086978 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.332968 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.332968 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.181818 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.181818 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.164369 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.164369 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.164369 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.164369 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32026.011561 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 32026.011561 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35899.671053 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 35899.671053 # average WriteReq miss latency +system.cpu.dcache.demand_accesses::cpu.data 2883 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2883 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2883 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2883 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.096447 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.096447 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.340635 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.340635 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.153846 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.153846 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.173777 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.173777 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.173777 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.173777 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 36318.421053 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 36318.421053 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 40869.774920 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 40869.774920 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 38250 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 38250 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 34494.758910 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 34494.758910 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 34494.758910 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 34494.758910 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 39143.712575 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 39143.712575 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 39143.712575 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 39143.712575 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -547,16 +547,16 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 66 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 66 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 262 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 262 # number of WriteReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 83 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 83 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 269 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 269 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 328 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 328 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 328 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 328 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 352 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 352 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 352 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 352 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 107 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 107 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 42 # number of WriteReq MSHR misses @@ -565,73 +565,73 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 149 system.cpu.dcache.demand_mshr_misses::total 149 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 149 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 149 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3133500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 3133500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1505500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1505500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 4639000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 4639000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 4639000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 4639000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.053796 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.053796 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3667500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 3667500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1713000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1713000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5380500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 5380500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5380500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 5380500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.054315 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.054315 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.046002 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.046002 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.051344 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.051344 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.051344 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.051344 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 29285.046729 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 29285.046729 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35845.238095 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35845.238095 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 31134.228188 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 31134.228188 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 31134.228188 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 31134.228188 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.051682 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.051682 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.051682 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.051682 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 34275.700935 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 34275.700935 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 40785.714286 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40785.714286 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 36110.738255 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 36110.738255 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 36110.738255 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 36110.738255 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 188.762510 # Cycle average of tags in use -system.cpu.l2cache.total_refs 42 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 357 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.117647 # Average number of references to valid blocks. +system.cpu.l2cache.tagsinuse 186.552400 # Cycle average of tags in use +system.cpu.l2cache.total_refs 41 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 356 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.115169 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 142.243584 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 46.518926 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.004341 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.001420 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.005761 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 20 # number of ReadReq hits +system.cpu.l2cache.occ_blocks::cpu.inst 140.494709 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 46.057690 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.004288 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.001406 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.005693 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 19 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 22 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 42 # number of ReadReq hits -system.cpu.l2cache.demand_hits::cpu.inst 20 # number of demand (read+write) hits +system.cpu.l2cache.ReadReq_hits::total 41 # number of ReadReq hits +system.cpu.l2cache.demand_hits::cpu.inst 19 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.data 22 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 42 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 20 # number of overall hits +system.cpu.l2cache.demand_hits::total 41 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 19 # number of overall hits system.cpu.l2cache.overall_hits::cpu.data 22 # number of overall hits -system.cpu.l2cache.overall_hits::total 42 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 276 # number of ReadReq misses +system.cpu.l2cache.overall_hits::total 41 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 277 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.data 85 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 361 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 362 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 42 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 42 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 276 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 277 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.data 127 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 403 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 276 # number of overall misses +system.cpu.l2cache.demand_misses::total 404 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 277 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 127 # number of overall misses -system.cpu.l2cache.overall_misses::total 403 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 9473000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2933000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 12406000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1449000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 1449000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 9473000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 4382000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 13855000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 9473000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 4382000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 13855000 # number of overall miss cycles +system.cpu.l2cache.overall_misses::total 404 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 9973000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3362000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 13335000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1665500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 1665500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 9973000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 5027500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 15000500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 9973000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 5027500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 15000500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 296 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 107 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 403 # number of ReadReq accesses(hits+misses) @@ -643,28 +643,28 @@ system.cpu.l2cache.demand_accesses::total 445 # n system.cpu.l2cache.overall_accesses::cpu.inst 296 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 149 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 445 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.932432 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.935811 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.794393 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.895782 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.898263 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.932432 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.935811 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.852349 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.905618 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.932432 # miss rate for overall accesses +system.cpu.l2cache.demand_miss_rate::total 0.907865 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.935811 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.852349 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.905618 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34322.463768 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34505.882353 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 34365.650970 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34500 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34500 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34322.463768 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34503.937008 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 34379.652605 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34322.463768 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34503.937008 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 34379.652605 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::total 0.907865 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 36003.610108 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 39552.941176 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 36837.016575 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 39654.761905 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 39654.761905 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 36003.610108 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 39586.614173 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 37129.950495 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 36003.610108 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 39586.614173 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 37129.950495 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -673,56 +673,59 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 2 # number of ReadReq MSHR hits system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 4 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 4 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 6 # number of ReadReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.data 4 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 4 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 6 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.data 4 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 4 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 276 # number of ReadReq MSHR misses +system.cpu.l2cache.overall_mshr_hits::total 6 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 275 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 81 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 357 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 356 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 42 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 42 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 276 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 275 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 123 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 399 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 276 # number of overall MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 398 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 275 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 123 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 399 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 8590000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2552500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 11142500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1317000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1317000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 8590000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3869500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 12459500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 8590000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3869500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 12459500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.932432 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.overall_mshr_misses::total 398 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 9090000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2983000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 12073000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1532500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1532500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 9090000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4515500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 13605500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 9090000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4515500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 13605500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.929054 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.757009 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.885856 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.883375 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.932432 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.929054 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.825503 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.896629 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.932432 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.894382 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.929054 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.825503 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.896629 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31123.188406 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31512.345679 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31211.484594 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31357.142857 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31357.142857 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31123.188406 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31459.349593 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31226.817043 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31123.188406 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31459.349593 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31226.817043 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.894382 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 33054.545455 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 36827.160494 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 33912.921348 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36488.095238 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36488.095238 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 33054.545455 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 36711.382114 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 34184.673367 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 33054.545455 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 36711.382114 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 34184.673367 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini index 693c71c0c..9e38ceef5 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini @@ -497,7 +497,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port @@ -529,7 +529,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.physmem.port[0] slave=system.system_port system.cpu.l2cache.mem_side diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout index 8b9162b5e..b7b5be837 100755 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout @@ -1,11 +1,11 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 28 2012 22:10:14 -gem5 started Jun 29 2012 00:34:42 +gem5 compiled Jul 2 2012 09:08:16 +gem5 started Jul 2 2012 15:18:36 gem5 executing on zizzer command line: build/ARM/gem5.fast -d build/ARM/tests/fast/quick/se/00.hello/arm/linux/o3-timing -re tests/run.py build/ARM/tests/fast/quick/se/00.hello/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 10305000 because target called exit() +Exiting @ tick 10843000 because target called exit() diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt index e182dd250..260f325f8 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt @@ -1,32 +1,32 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000010 # Number of seconds simulated -sim_ticks 10305000 # Number of ticks simulated -final_tick 10305000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000011 # Number of seconds simulated +sim_ticks 10843000 # Number of ticks simulated +final_tick 10843000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 29768 # Simulator instruction rate (inst/s) -host_op_rate 37142 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 66801597 # Simulator tick rate (ticks/s) -host_mem_usage 232684 # Number of bytes of host memory used -host_seconds 0.15 # Real time elapsed on the host +host_inst_rate 17631 # Simulator instruction rate (inst/s) +host_op_rate 22000 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 41635778 # Simulator tick rate (ticks/s) +host_mem_usage 232604 # Number of bytes of host memory used +host_seconds 0.26 # Real time elapsed on the host sim_insts 4591 # Number of instructions simulated sim_ops 5729 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 17664 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 17600 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 7872 # Number of bytes read from this memory -system.physmem.bytes_read::total 25536 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 17664 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 17664 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 276 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 25472 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 17600 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 17600 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 275 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 123 # Number of read requests responded to by this memory -system.physmem.num_reads::total 399 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1714119360 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 763901019 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2478020378 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1714119360 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1714119360 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1714119360 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 763901019 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2478020378 # Total bandwidth to/from this memory (bytes/s) +system.physmem.num_reads::total 398 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1623167020 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 725998340 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2349165360 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1623167020 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1623167020 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1623167020 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 725998340 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2349165360 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -70,245 +70,245 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 13 # Number of system calls -system.cpu.numCycles 20611 # number of cpu cycles simulated +system.cpu.numCycles 21687 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 2522 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 1857 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 445 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 1967 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 669 # Number of BTB hits +system.cpu.BPredUnit.lookups 2517 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 1836 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 456 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 1920 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 676 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 255 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.usedRAS 253 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 57 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 6205 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 12809 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2522 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 924 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 2802 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1712 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 1810 # Number of cycles fetch has spent blocked +system.cpu.fetch.icacheStallCycles 7080 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 12862 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2517 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 929 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 2805 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1740 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 2260 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.CacheLines 1996 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 298 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 11993 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.366631 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.761460 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 1997 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 304 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 13334 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.230988 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.652427 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 9191 76.64% 76.64% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 251 2.09% 78.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 179 1.49% 80.22% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 222 1.85% 82.07% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 215 1.79% 83.87% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 290 2.42% 86.28% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 118 0.98% 87.27% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 119 0.99% 88.26% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1408 11.74% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 10529 78.96% 78.96% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 255 1.91% 80.88% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 171 1.28% 82.16% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 221 1.66% 83.82% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 220 1.65% 85.47% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 289 2.17% 87.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 122 0.91% 88.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 119 0.89% 89.44% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1408 10.56% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 11993 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.122362 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.621464 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 6357 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 1977 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2573 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 70 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1016 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 444 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 163 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 14344 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 551 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1016 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 6632 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 279 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 1507 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2368 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 191 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 13444 # Number of instructions processed by rename -system.cpu.rename.IQFullEvents 12 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 160 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 13077 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 61779 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 60371 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 1408 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 13334 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.116060 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.593074 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 7240 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 2427 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 2551 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 88 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1028 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 446 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 164 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 14296 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 558 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1028 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 7514 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 500 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 1638 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 2347 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 307 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 13390 # Number of instructions processed by rename +system.cpu.rename.IQFullEvents 19 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 246 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 13047 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 61618 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 60098 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 1520 # Number of floating rename lookups system.cpu.rename.CommittedMaps 5673 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 7404 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 45 # count of serializing insts renamed +system.cpu.rename.UndoneMaps 7374 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 46 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 42 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 627 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2891 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1788 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 40 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 23 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 11732 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 51 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 9186 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 117 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 5655 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 16152 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 14 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 11993 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.765947 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.466891 # Number of insts issued each cycle +system.cpu.rename.skidInsts 753 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2834 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1819 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 45 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 25 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 11727 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 53 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 9087 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 132 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 5777 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 16432 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 16 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 13334 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.681491 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.365437 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 8390 69.96% 69.96% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1302 10.86% 80.81% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 789 6.58% 87.39% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 542 4.52% 91.91% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 463 3.86% 95.77% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 295 2.46% 98.23% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 149 1.24% 99.47% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 45 0.38% 99.85% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 18 0.15% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 9565 71.73% 71.73% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1503 11.27% 83.01% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 815 6.11% 89.12% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 548 4.11% 93.23% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 447 3.35% 96.58% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 275 2.06% 98.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 130 0.97% 99.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 41 0.31% 99.93% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 10 0.07% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 11993 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 13334 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 3 1.38% 1.38% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 1.38% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 1.38% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.38% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.38% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.38% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 1.38% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.38% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 1.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 1.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.38% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 150 69.12% 70.51% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 64 29.49% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 6 2.86% 2.86% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 2.86% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 2.86% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.86% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.86% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.86% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 2.86% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.86% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 2.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 2.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.86% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 142 67.62% 70.48% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 62 29.52% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 5505 59.93% 59.93% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 7 0.08% 60.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.00% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.00% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.00% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.00% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.00% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.00% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.04% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.04% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.04% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.04% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2406 26.19% 86.23% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1265 13.77% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 5478 60.28% 60.28% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 8 0.09% 60.37% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.37% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.37% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.37% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.37% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.37% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.37% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.40% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.40% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.40% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.40% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2349 25.85% 86.26% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1249 13.74% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 9186 # Type of FU issued -system.cpu.iq.rate 0.445684 # Inst issue rate -system.cpu.iq.fu_busy_cnt 217 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.023623 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 30663 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 17408 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 8220 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 9087 # Type of FU issued +system.cpu.iq.rate 0.419007 # Inst issue rate +system.cpu.iq.fu_busy_cnt 210 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.023110 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 31814 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 17497 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 8174 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 46 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_writes 76 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 9383 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 9277 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 64 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 57 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1691 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.squashedLoads 1634 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 19 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 850 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 881 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1016 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 175 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 21 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 11783 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 140 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2891 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1788 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 39 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 13 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 1028 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 203 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 24 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 11780 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 137 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2834 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1819 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 41 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 14 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 1 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 19 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 88 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 319 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 407 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 8719 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 2169 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 467 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedTakenIncorrect 89 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 334 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 423 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 8660 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 2140 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 427 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 3377 # number of memory reference insts executed -system.cpu.iew.exec_branches 1400 # Number of branches executed -system.cpu.iew.exec_stores 1208 # Number of stores executed -system.cpu.iew.exec_rate 0.423027 # Inst execution rate -system.cpu.iew.wb_sent 8403 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 8236 # cumulative count of insts written-back -system.cpu.iew.wb_producers 3901 # num instructions producing a value -system.cpu.iew.wb_consumers 7899 # num instructions consuming a value +system.cpu.iew.exec_refs 3344 # number of memory reference insts executed +system.cpu.iew.exec_branches 1407 # Number of branches executed +system.cpu.iew.exec_stores 1204 # Number of stores executed +system.cpu.iew.exec_rate 0.399318 # Inst execution rate +system.cpu.iew.wb_sent 8336 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 8190 # cumulative count of insts written-back +system.cpu.iew.wb_producers 3858 # num instructions producing a value +system.cpu.iew.wb_consumers 7806 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.399592 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.493860 # average fanout of values written-back +system.cpu.iew.wb_rate 0.377646 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.494235 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 4591 # The number of committed instructions system.cpu.commit.commitCommittedOps 5729 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 6053 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 6051 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 355 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 10978 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.521862 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.331986 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 369 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 12307 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.465507 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.263835 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 8629 78.60% 78.60% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1108 10.09% 88.70% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 430 3.92% 92.61% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 264 2.40% 95.02% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 184 1.68% 96.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 173 1.58% 98.27% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 56 0.51% 98.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 40 0.36% 99.14% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 94 0.86% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 9888 80.34% 80.34% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1205 9.79% 90.14% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 432 3.51% 93.65% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 264 2.15% 95.79% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 159 1.29% 97.08% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 164 1.33% 98.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 55 0.45% 98.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 38 0.31% 99.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 102 0.83% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 10978 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 12307 # Number of insts commited each cycle system.cpu.commit.committedInsts 4591 # Number of instructions committed system.cpu.commit.committedOps 5729 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -319,69 +319,69 @@ system.cpu.commit.branches 944 # Nu system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. system.cpu.commit.int_insts 4976 # Number of committed integer instructions. system.cpu.commit.function_calls 82 # Number of function calls committed. -system.cpu.commit.bw_lim_events 94 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 102 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 22509 # The number of ROB reads -system.cpu.rob.rob_writes 24591 # The number of ROB writes -system.cpu.timesIdled 178 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 8618 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 23828 # The number of ROB reads +system.cpu.rob.rob_writes 24602 # The number of ROB writes +system.cpu.timesIdled 202 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 8353 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 4591 # Number of Instructions Simulated system.cpu.committedOps 5729 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 4591 # Number of Instructions Simulated -system.cpu.cpi 4.489436 # CPI: Cycles Per Instruction -system.cpu.cpi_total 4.489436 # CPI: Total CPI of All Threads -system.cpu.ipc 0.222745 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.222745 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 40006 # number of integer regfile reads -system.cpu.int_regfile_writes 8113 # number of integer regfile writes +system.cpu.cpi 4.723807 # CPI: Cycles Per Instruction +system.cpu.cpi_total 4.723807 # CPI: Total CPI of All Threads +system.cpu.ipc 0.211694 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.211694 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 39657 # number of integer regfile reads +system.cpu.int_regfile_writes 8076 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.misc_regfile_reads 15846 # number of misc regfile reads +system.cpu.misc_regfile_reads 15863 # number of misc regfile reads system.cpu.misc_regfile_writes 24 # number of misc regfile writes system.cpu.icache.replacements 5 # number of replacements -system.cpu.icache.tagsinuse 150.103653 # Cycle average of tags in use -system.cpu.icache.total_refs 1637 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 149.186170 # Cycle average of tags in use +system.cpu.icache.total_refs 1630 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 296 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 5.530405 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 5.506757 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 150.103653 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.073293 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.073293 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 1637 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1637 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1637 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1637 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1637 # number of overall hits -system.cpu.icache.overall_hits::total 1637 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 359 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 359 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 359 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 359 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 359 # number of overall misses -system.cpu.icache.overall_misses::total 359 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 12452500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 12452500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 12452500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 12452500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 12452500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 12452500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1996 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1996 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1996 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1996 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1996 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1996 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.179860 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.179860 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.179860 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.179860 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.179860 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.179860 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34686.629526 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 34686.629526 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 34686.629526 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 34686.629526 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 34686.629526 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 34686.629526 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 149.186170 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.072845 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.072845 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 1630 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1630 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1630 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1630 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1630 # number of overall hits +system.cpu.icache.overall_hits::total 1630 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 367 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 367 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 367 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 367 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 367 # number of overall misses +system.cpu.icache.overall_misses::total 367 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 13154000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 13154000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 13154000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 13154000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 13154000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 13154000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1997 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1997 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1997 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1997 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1997 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1997 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.183776 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.183776 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.183776 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.183776 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.183776 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.183776 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35841.961853 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 35841.961853 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 35841.961853 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 35841.961853 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 35841.961853 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 35841.961853 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -390,110 +390,110 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 63 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 63 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 63 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 63 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 63 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 63 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 71 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 71 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 71 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 71 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 71 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 71 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 296 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 296 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 296 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 296 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 296 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 296 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9831500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 9831500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9831500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 9831500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9831500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 9831500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.148297 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.148297 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.148297 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.148297 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.148297 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.148297 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 33214.527027 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 33214.527027 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 33214.527027 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 33214.527027 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 33214.527027 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 33214.527027 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 10405500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 10405500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 10405500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 10405500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 10405500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 10405500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.148222 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.148222 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.148222 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.148222 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.148222 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.148222 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35153.716216 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 35153.716216 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35153.716216 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 35153.716216 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35153.716216 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 35153.716216 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 87.680549 # Cycle average of tags in use -system.cpu.dcache.total_refs 2445 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 86.628845 # Cycle average of tags in use +system.cpu.dcache.total_refs 2404 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 149 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 16.409396 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 16.134228 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 87.680549 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.021406 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.021406 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 1816 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1816 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 609 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 609 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 9 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 9 # number of LoadLockedReq hits +system.cpu.dcache.occ_blocks::cpu.data 86.628845 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.021150 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.021150 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 1780 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1780 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 602 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 602 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 11 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 11 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 2425 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2425 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2425 # number of overall hits -system.cpu.dcache.overall_hits::total 2425 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 173 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 173 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 304 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 304 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 2382 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2382 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2382 # number of overall hits +system.cpu.dcache.overall_hits::total 2382 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 190 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 190 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 311 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 311 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 477 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 477 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 477 # number of overall misses -system.cpu.dcache.overall_misses::total 477 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5540500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5540500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 10913500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 10913500 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 501 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 501 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 501 # number of overall misses +system.cpu.dcache.overall_misses::total 501 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 6900500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 6900500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 12710500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 12710500 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 76500 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 76500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 16454000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 16454000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 16454000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 16454000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1989 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1989 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 19611000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 19611000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 19611000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 19611000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1970 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1970 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 11 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 13 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 13 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2902 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2902 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2902 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2902 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.086978 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.086978 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.332968 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.332968 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.181818 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.181818 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.164369 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.164369 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.164369 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.164369 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32026.011561 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 32026.011561 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35899.671053 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 35899.671053 # average WriteReq miss latency +system.cpu.dcache.demand_accesses::cpu.data 2883 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2883 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2883 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2883 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.096447 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.096447 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.340635 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.340635 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.153846 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.153846 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.173777 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.173777 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.173777 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.173777 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 36318.421053 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 36318.421053 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 40869.774920 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 40869.774920 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 38250 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 38250 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 34494.758910 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 34494.758910 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 34494.758910 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 34494.758910 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 39143.712575 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 39143.712575 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 39143.712575 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 39143.712575 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -502,16 +502,16 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 66 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 66 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 262 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 262 # number of WriteReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 83 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 83 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 269 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 269 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 328 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 328 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 328 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 328 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 352 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 352 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 352 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 352 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 107 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 107 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 42 # number of WriteReq MSHR misses @@ -520,73 +520,73 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 149 system.cpu.dcache.demand_mshr_misses::total 149 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 149 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 149 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3133500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 3133500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1505500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1505500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 4639000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 4639000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 4639000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 4639000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.053796 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.053796 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3667500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 3667500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1713000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1713000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5380500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 5380500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5380500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 5380500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.054315 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.054315 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.046002 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.046002 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.051344 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.051344 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.051344 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.051344 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 29285.046729 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 29285.046729 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35845.238095 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35845.238095 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 31134.228188 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 31134.228188 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 31134.228188 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 31134.228188 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.051682 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.051682 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.051682 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.051682 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 34275.700935 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 34275.700935 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 40785.714286 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40785.714286 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 36110.738255 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 36110.738255 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 36110.738255 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 36110.738255 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 188.762510 # Cycle average of tags in use -system.cpu.l2cache.total_refs 42 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 357 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.117647 # Average number of references to valid blocks. +system.cpu.l2cache.tagsinuse 186.552400 # Cycle average of tags in use +system.cpu.l2cache.total_refs 41 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 356 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.115169 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 142.243584 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 46.518926 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.004341 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.001420 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.005761 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 20 # number of ReadReq hits +system.cpu.l2cache.occ_blocks::cpu.inst 140.494709 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 46.057690 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.004288 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.001406 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.005693 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 19 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 22 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 42 # number of ReadReq hits -system.cpu.l2cache.demand_hits::cpu.inst 20 # number of demand (read+write) hits +system.cpu.l2cache.ReadReq_hits::total 41 # number of ReadReq hits +system.cpu.l2cache.demand_hits::cpu.inst 19 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.data 22 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 42 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 20 # number of overall hits +system.cpu.l2cache.demand_hits::total 41 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 19 # number of overall hits system.cpu.l2cache.overall_hits::cpu.data 22 # number of overall hits -system.cpu.l2cache.overall_hits::total 42 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 276 # number of ReadReq misses +system.cpu.l2cache.overall_hits::total 41 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 277 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.data 85 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 361 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 362 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 42 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 42 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 276 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 277 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.data 127 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 403 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 276 # number of overall misses +system.cpu.l2cache.demand_misses::total 404 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 277 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 127 # number of overall misses -system.cpu.l2cache.overall_misses::total 403 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 9473000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2933000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 12406000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1449000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 1449000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 9473000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 4382000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 13855000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 9473000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 4382000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 13855000 # number of overall miss cycles +system.cpu.l2cache.overall_misses::total 404 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 9973000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3362000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 13335000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1665500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 1665500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 9973000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 5027500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 15000500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 9973000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 5027500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 15000500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 296 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 107 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 403 # number of ReadReq accesses(hits+misses) @@ -598,28 +598,28 @@ system.cpu.l2cache.demand_accesses::total 445 # n system.cpu.l2cache.overall_accesses::cpu.inst 296 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 149 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 445 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.932432 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.935811 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.794393 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.895782 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.898263 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.932432 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.935811 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.852349 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.905618 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.932432 # miss rate for overall accesses +system.cpu.l2cache.demand_miss_rate::total 0.907865 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.935811 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.852349 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.905618 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34322.463768 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34505.882353 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 34365.650970 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34500 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34500 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34322.463768 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34503.937008 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 34379.652605 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34322.463768 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34503.937008 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 34379.652605 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::total 0.907865 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 36003.610108 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 39552.941176 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 36837.016575 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 39654.761905 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 39654.761905 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 36003.610108 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 39586.614173 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 37129.950495 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 36003.610108 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 39586.614173 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 37129.950495 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -628,56 +628,59 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 2 # number of ReadReq MSHR hits system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 4 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 4 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 6 # number of ReadReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.data 4 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 4 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 6 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.data 4 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 4 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 276 # number of ReadReq MSHR misses +system.cpu.l2cache.overall_mshr_hits::total 6 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 275 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 81 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 357 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 356 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 42 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 42 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 276 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 275 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 123 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 399 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 276 # number of overall MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 398 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 275 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 123 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 399 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 8590000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2552500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 11142500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1317000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1317000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 8590000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3869500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 12459500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 8590000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3869500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 12459500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.932432 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.overall_mshr_misses::total 398 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 9090000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2983000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 12073000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1532500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1532500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 9090000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4515500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 13605500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 9090000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4515500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 13605500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.929054 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.757009 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.885856 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.883375 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.932432 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.929054 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.825503 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.896629 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.932432 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.894382 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.929054 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.825503 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.896629 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31123.188406 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31512.345679 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31211.484594 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31357.142857 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31357.142857 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31123.188406 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31459.349593 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31226.817043 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31123.188406 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31459.349593 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31226.817043 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.894382 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 33054.545455 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 36827.160494 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 33912.921348 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36488.095238 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36488.095238 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 33054.545455 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 36711.382114 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 34184.673367 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 33054.545455 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 36711.382114 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 34184.673367 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/config.ini b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/config.ini index 89402c0d8..e19a07626 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/config.ini +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/config.ini @@ -166,7 +166,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port @@ -198,7 +198,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.physmem.port[0] slave=system.system_port system.cpu.l2cache.mem_side diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/simout b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/simout index d4a066c4f..16fea9a8f 100755 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/simout +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/simout @@ -1,11 +1,11 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 28 2012 22:10:14 -gem5 started Jun 29 2012 00:35:26 +gem5 compiled Jul 2 2012 09:08:16 +gem5 started Jul 2 2012 15:19:21 gem5 executing on zizzer command line: build/ARM/gem5.fast -d build/ARM/tests/fast/quick/se/00.hello/arm/linux/simple-timing -re tests/run.py build/ARM/tests/fast/quick/se/00.hello/arm/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 26351000 because target called exit() +Exiting @ tick 27316000 because target called exit() diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt index bac15b503..0ed449cb9 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000026 # Number of seconds simulated -sim_ticks 26351000 # Number of ticks simulated -final_tick 26351000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000027 # Number of seconds simulated +sim_ticks 27316000 # Number of ticks simulated +final_tick 27316000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 50718 # Simulator instruction rate (inst/s) -host_op_rate 63005 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 292657577 # Simulator tick rate (ticks/s) -host_mem_usage 231660 # Number of bytes of host memory used +host_inst_rate 53670 # Simulator instruction rate (inst/s) +host_op_rate 66671 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 321019881 # Simulator tick rate (ticks/s) +host_mem_usage 231588 # Number of bytes of host memory used host_seconds 0.09 # Real time elapsed on the host sim_insts 4565 # Number of instructions simulated sim_ops 5672 # Number of ops (including micro ops) simulated @@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 14400 # Nu system.physmem.num_reads::cpu.inst 225 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 125 # Number of read requests responded to by this memory system.physmem.num_reads::total 350 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 546468825 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 303593792 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 850062616 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 546468825 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 546468825 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 546468825 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 303593792 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 850062616 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 527163567 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 292868648 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 820032216 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 527163567 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 527163567 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 527163567 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 292868648 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 820032216 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -70,7 +70,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 13 # Number of system calls -system.cpu.numCycles 52702 # number of cpu cycles simulated +system.cpu.numCycles 54632 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 4565 # Number of instructions committed @@ -89,18 +89,18 @@ system.cpu.num_mem_refs 2138 # nu system.cpu.num_load_insts 1200 # Number of load instructions system.cpu.num_store_insts 938 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 52702 # Number of busy cycles +system.cpu.num_busy_cycles 54632 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 1 # number of replacements -system.cpu.icache.tagsinuse 114.562374 # Cycle average of tags in use +system.cpu.icache.tagsinuse 114.832264 # Cycle average of tags in use system.cpu.icache.total_refs 4364 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 241 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 18.107884 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 114.562374 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.055939 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.055939 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::cpu.inst 114.832264 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.056070 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.056070 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 4364 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 4364 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 4364 # number of demand (read+write) hits @@ -171,14 +171,14 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50211.618257 system.cpu.icache.overall_avg_mshr_miss_latency::total 50211.618257 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 82.961484 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 83.122861 # Cycle average of tags in use system.cpu.dcache.total_refs 1940 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 141 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 13.758865 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 82.961484 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.020254 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.020254 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::cpu.data 83.122861 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.020294 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.020294 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 1048 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1048 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 870 # number of WriteReq hits @@ -277,16 +277,16 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 48234.042553 system.cpu.dcache.overall_avg_mshr_miss_latency::total 48234.042553 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 154.001524 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 154.336658 # Cycle average of tags in use system.cpu.l2cache.total_refs 32 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 307 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.104235 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 105.840466 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 48.161058 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.003230 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.001470 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.004700 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 106.089659 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 48.246999 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.003238 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.001472 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.004710 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 16 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 16 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 32 # number of ReadReq hits diff --git a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/config.ini b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/config.ini index ee123d638..3f1b44728 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/config.ini +++ b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/config.ini @@ -181,7 +181,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side @@ -213,7 +213,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.physmem.port[0] slave=system.system_port system.cpu.l2cache.mem_side diff --git a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/simout b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/simout index 40197f717..3e33cecf6 100755 --- a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/simout +++ b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 11:58:11 -gem5 started Jun 4 2012 14:43:16 +gem5 compiled Jul 2 2012 08:47:33 +gem5 started Jul 2 2012 11:28:42 gem5 executing on zizzer -command line: build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/00.hello/mips/linux/inorder-timing -re tests/run.py build/MIPS/tests/opt/quick/se/00.hello/mips/linux/inorder-timing +command line: build/MIPS/gem5.fast -d build/MIPS/tests/fast/quick/se/00.hello/mips/linux/inorder-timing -re tests/run.py build/MIPS/tests/fast/quick/se/00.hello/mips/linux/inorder-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello World! -Exiting @ tick 19775000 because target called exit() +Exiting @ tick 20520000 because target called exit() diff --git a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt index 705e8dbde..615d61bce 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000020 # Number of seconds simulated -sim_ticks 19775000 # Number of ticks simulated -final_tick 19775000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000021 # Number of seconds simulated +sim_ticks 20520000 # Number of ticks simulated +final_tick 20520000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 79967 # Simulator instruction rate (inst/s) -host_op_rate 79947 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 271245925 # Simulator tick rate (ticks/s) -host_mem_usage 215348 # Number of bytes of host memory used -host_seconds 0.07 # Real time elapsed on the host +host_inst_rate 67788 # Simulator instruction rate (inst/s) +host_op_rate 67774 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 238625492 # Simulator tick rate (ticks/s) +host_mem_usage 219036 # Number of bytes of host memory used +host_seconds 0.09 # Real time elapsed on the host sim_insts 5827 # Number of instructions simulated sim_ops 5827 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 20288 # Number of bytes read from this memory @@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 20288 # Nu system.physmem.num_reads::cpu.inst 317 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 138 # Number of read requests responded to by this memory system.physmem.num_reads::total 455 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1025941846 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 446624526 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1472566372 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1025941846 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1025941846 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1025941846 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 446624526 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1472566372 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 988693957 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 430409357 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1419103314 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 988693957 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 988693957 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 988693957 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 430409357 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1419103314 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses system.cpu.dtb.read_accesses 0 # DTB read accesses @@ -46,27 +46,27 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 8 # Number of system calls -system.cpu.numCycles 39551 # number of cpu cycles simulated +system.cpu.numCycles 41041 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.branch_predictor.lookups 1152 # Number of BP lookups -system.cpu.branch_predictor.condPredicted 851 # Number of conditional branches predicted +system.cpu.branch_predictor.lookups 1151 # Number of BP lookups +system.cpu.branch_predictor.condPredicted 850 # Number of conditional branches predicted system.cpu.branch_predictor.condIncorrect 605 # Number of conditional branches incorrect -system.cpu.branch_predictor.BTBLookups 867 # Number of BTB lookups -system.cpu.branch_predictor.BTBHits 309 # Number of BTB hits +system.cpu.branch_predictor.BTBLookups 866 # Number of BTB lookups +system.cpu.branch_predictor.BTBHits 310 # Number of BTB hits system.cpu.branch_predictor.usedRAS 86 # Number of times the RAS was used to get a target. system.cpu.branch_predictor.RASInCorrect 32 # Number of incorrect RAS predictions. -system.cpu.branch_predictor.BTBHitPct 35.640138 # BTB Hit Percentage -system.cpu.branch_predictor.predictedTaken 402 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.predictedNotTaken 750 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 5104 # Number of Reads from Int. Register File +system.cpu.branch_predictor.BTBHitPct 35.796767 # BTB Hit Percentage +system.cpu.branch_predictor.predictedTaken 403 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.predictedNotTaken 748 # Number of Branches Predicted As Not Taken (False). +system.cpu.regfile_manager.intRegFileReads 5102 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 3408 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 8512 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.intRegFileAccesses 8510 # Total Accesses (Read+Write) to the Int. Register File system.cpu.regfile_manager.floatRegFileReads 3 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 1 # Number of Writes to FP Register File system.cpu.regfile_manager.floatRegFileAccesses 4 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 1330 # Number of Registers Read Through Forwarding Logic -system.cpu.agen_unit.agens 2238 # Number of Address Generations +system.cpu.regfile_manager.regForwards 1331 # Number of Registers Read Through Forwarding Logic +system.cpu.agen_unit.agens 2237 # Number of Address Generations system.cpu.execution_unit.predictedTakenIncorrect 262 # Number of Branches Incorrectly Predicted As Taken. system.cpu.execution_unit.predictedNotTakenIncorrect 334 # Number of Branches Incorrectly Predicted As Not Taken). system.cpu.execution_unit.mispredicted 596 # Number of Branches Incorrectly Predicted @@ -76,12 +76,12 @@ system.cpu.execution_unit.executions 3155 # Nu system.cpu.mult_div_unit.multiplies 3 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 1 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 9142 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 9765 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 404 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 34183 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 5368 # Number of cycles cpu stages are processed. -system.cpu.activity 13.572350 # Percentage of cycles cpu is active +system.cpu.timesIdled 505 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 35643 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 5398 # Number of cycles cpu stages are processed. +system.cpu.activity 13.152701 # Percentage of cycles cpu is active system.cpu.comLoads 1164 # Number of Load instructions committed system.cpu.comStores 925 # Number of Store instructions committed system.cpu.comBranches 916 # Number of Branches instructions committed @@ -93,72 +93,72 @@ system.cpu.committedInsts 5827 # Nu system.cpu.committedOps 5827 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 5827 # Number of Instructions committed (Total) -system.cpu.cpi 6.787541 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 7.043247 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 6.787541 # CPI: Total CPI of All Threads -system.cpu.ipc 0.147329 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 7.043247 # CPI: Total CPI of All Threads +system.cpu.ipc 0.141980 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 0.147329 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 35911 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 3640 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 9.203307 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 36722 # Number of cycles 0 instructions are processed. +system.cpu.ipc_total 0.141980 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 37403 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 3638 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 8.864306 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 38212 # Number of cycles 0 instructions are processed. system.cpu.stage1.runCycles 2829 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 7.152790 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 36760 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 2791 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 7.056712 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 38308 # Number of cycles 0 instructions are processed. +system.cpu.stage1.utilization 6.893107 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 38251 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 2790 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 6.798080 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 39798 # Number of cycles 0 instructions are processed. system.cpu.stage3.runCycles 1243 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 3.142778 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 36647 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 2904 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 7.342419 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.utilization 3.028679 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 38136 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 2905 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 7.078288 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.replacements 13 # number of replacements -system.cpu.icache.tagsinuse 148.175887 # Cycle average of tags in use +system.cpu.icache.tagsinuse 147.235290 # Cycle average of tags in use system.cpu.icache.total_refs 411 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 319 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 1.288401 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 148.175887 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.072352 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.072352 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::cpu.inst 147.235290 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.071892 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.071892 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 411 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 411 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 411 # number of demand (read+write) hits system.cpu.icache.demand_hits::total 411 # number of demand (read+write) hits system.cpu.icache.overall_hits::cpu.inst 411 # number of overall hits system.cpu.icache.overall_hits::total 411 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 343 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 343 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 343 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 343 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 343 # number of overall misses -system.cpu.icache.overall_misses::total 343 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 19128500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 19128500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 19128500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 19128500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 19128500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 19128500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 754 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 754 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 754 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 754 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 754 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 754 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.454907 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.454907 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.454907 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.454907 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.454907 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.454907 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55768.221574 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 55768.221574 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 55768.221574 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 55768.221574 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 55768.221574 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 55768.221574 # average overall miss latency +system.cpu.icache.ReadReq_misses::cpu.inst 344 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 344 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 344 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 344 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 344 # number of overall misses +system.cpu.icache.overall_misses::total 344 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 19612500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 19612500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 19612500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 19612500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 19612500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 19612500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 755 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 755 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 755 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 755 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 755 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 755 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.455629 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.455629 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.455629 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.455629 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.455629 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.455629 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 57013.081395 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 57013.081395 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 57013.081395 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 57013.081395 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 57013.081395 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 57013.081395 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 29000 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -167,70 +167,70 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets 29000 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 24 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 24 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 24 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 24 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 24 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 24 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 25 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 25 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 25 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 25 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 25 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 25 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 319 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 319 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 319 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 319 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 319 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 319 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 16951500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 16951500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 16951500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 16951500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 16951500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 16951500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.423077 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.423077 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.423077 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.423077 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.423077 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.423077 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53139.498433 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53139.498433 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53139.498433 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 53139.498433 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53139.498433 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 53139.498433 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 17428000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 17428000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 17428000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 17428000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 17428000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 17428000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.422517 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.422517 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.422517 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.422517 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.422517 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.422517 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54633.228840 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54633.228840 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54633.228840 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 54633.228840 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54633.228840 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 54633.228840 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 89.746602 # Cycle average of tags in use -system.cpu.dcache.total_refs 1838 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 89.278998 # Cycle average of tags in use +system.cpu.dcache.total_refs 1835 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 138 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 13.318841 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 13.297101 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 89.746602 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.021911 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.021911 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 1075 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1075 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 763 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 763 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 1838 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 1838 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 1838 # number of overall hits -system.cpu.dcache.overall_hits::total 1838 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 89 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 89 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 162 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 162 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 251 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 251 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 251 # number of overall misses -system.cpu.dcache.overall_misses::total 251 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5072500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5072500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 8910500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 8910500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 13983000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 13983000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 13983000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 13983000 # number of overall miss cycles +system.cpu.dcache.occ_blocks::cpu.data 89.278998 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.021797 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.021797 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 1073 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1073 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 762 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 762 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 1835 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 1835 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 1835 # number of overall hits +system.cpu.dcache.overall_hits::total 1835 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 91 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 91 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 163 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 163 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 254 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 254 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 254 # number of overall misses +system.cpu.dcache.overall_misses::total 254 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5537000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5537000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 10150000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 10150000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 15687000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 15687000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 15687000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 15687000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 1164 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1164 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 925 # number of WriteReq accesses(hits+misses) @@ -239,38 +239,38 @@ system.cpu.dcache.demand_accesses::cpu.data 2089 # system.cpu.dcache.demand_accesses::total 2089 # number of demand (read+write) accesses system.cpu.dcache.overall_accesses::cpu.data 2089 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 2089 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.076460 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.076460 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.175135 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.175135 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.120153 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.120153 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.120153 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.120153 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56994.382022 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 56994.382022 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55003.086420 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 55003.086420 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 55709.163347 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 55709.163347 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 55709.163347 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 55709.163347 # average overall miss latency +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.078179 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.078179 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.176216 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.176216 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.121589 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.121589 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.121589 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.121589 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 60846.153846 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 60846.153846 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62269.938650 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 62269.938650 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 61759.842520 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 61759.842520 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 61759.842520 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 61759.842520 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 1153500 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 1194500 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 23 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 50152.173913 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 51934.782609 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 2 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 111 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 111 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 113 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 113 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 113 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 113 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 4 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 112 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 112 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 116 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 116 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 116 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 116 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 87 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 87 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 51 # number of WriteReq MSHR misses @@ -279,14 +279,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 138 system.cpu.dcache.demand_mshr_misses::total 138 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 138 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4702500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4702500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2745500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2745500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7448000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 7448000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7448000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 7448000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5138000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 5138000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2913500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2913500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8051500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 8051500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8051500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 8051500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.074742 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.074742 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055135 # mshr miss rate for WriteReq accesses @@ -295,26 +295,26 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.066060 system.cpu.dcache.demand_mshr_miss_rate::total 0.066060 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.066060 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.066060 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 54051.724138 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 54051.724138 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53833.333333 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53833.333333 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53971.014493 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 53971.014493 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53971.014493 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 53971.014493 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 59057.471264 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 59057.471264 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 57127.450980 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 57127.450980 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 58344.202899 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 58344.202899 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 58344.202899 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 58344.202899 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 205.517886 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 204.292602 # Cycle average of tags in use system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 404 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.004950 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 149.817885 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 55.700002 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.004572 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.001700 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.006272 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 148.846889 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 55.445713 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.004542 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.001692 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.006235 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits @@ -332,17 +332,17 @@ system.cpu.l2cache.demand_misses::total 455 # nu system.cpu.l2cache.overall_misses::cpu.inst 317 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 138 # number of overall misses system.cpu.l2cache.overall_misses::total 455 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 16585000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4585000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 21170000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2682000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 2682000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 16585000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 7267000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 23852000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 16585000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 7267000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 23852000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 17060000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 5021500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 22081500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2843500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 2843500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 17060000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 7865000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 24925000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 17060000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 7865000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 24925000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 319 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 87 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 406 # number of ReadReq accesses(hits+misses) @@ -365,17 +365,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.995624 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993730 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.995624 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52318.611987 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52701.149425 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52400.990099 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52588.235294 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52588.235294 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52318.611987 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52659.420290 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52421.978022 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52318.611987 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52659.420290 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52421.978022 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 53817.034700 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 57718.390805 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 54657.178218 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 55754.901961 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 55754.901961 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 53817.034700 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 56992.753623 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 54780.219780 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53817.034700 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 56992.753623 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 54780.219780 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -395,17 +395,17 @@ system.cpu.l2cache.demand_mshr_misses::total 455 system.cpu.l2cache.overall_mshr_misses::cpu.inst 317 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 455 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 12717500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3529500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 16247000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2058000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2058000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 12717500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5587500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 18305000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 12717500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5587500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 18305000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 13201000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3966500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 17167500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2221000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2221000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 13201000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6187500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 19388500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 13201000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6187500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 19388500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993730 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.995074 # mshr miss rate for ReadReq accesses @@ -417,17 +417,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.995624 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993730 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.995624 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40118.296530 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40568.965517 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40215.346535 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40352.941176 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40352.941176 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40118.296530 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40489.130435 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40230.769231 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40118.296530 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40489.130435 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40230.769231 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41643.533123 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 45591.954023 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 42493.811881 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 43549.019608 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 43549.019608 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41643.533123 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 44836.956522 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42612.087912 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41643.533123 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 44836.956522 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42612.087912 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/config.ini index a70bd3d3a..f6f1675ea 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/config.ini +++ b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/config.ini @@ -479,7 +479,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side @@ -511,7 +511,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.physmem.port[0] slave=system.system_port system.cpu.l2cache.mem_side diff --git a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/simout index d99f33506..d96fc7f5c 100755 --- a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/simout +++ b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 28 2012 22:05:18 -gem5 started Jun 28 2012 22:52:53 +gem5 compiled Jul 2 2012 08:47:33 +gem5 started Jul 2 2012 11:28:53 gem5 executing on zizzer command line: build/MIPS/gem5.fast -d build/MIPS/tests/fast/quick/se/00.hello/mips/linux/o3-timing -re tests/run.py build/MIPS/tests/fast/quick/se/00.hello/mips/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello World! -Exiting @ tick 12478500 because target called exit() +Exiting @ tick 13016500 because target called exit() diff --git a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt index 7981b4fdb..4a3a21e6c 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt @@ -1,32 +1,32 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000012 # Number of seconds simulated -sim_ticks 12478500 # Number of ticks simulated -final_tick 12478500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000013 # Number of seconds simulated +sim_ticks 13016500 # Number of ticks simulated +final_tick 13016500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 84509 # Simulator instruction rate (inst/s) -host_op_rate 84485 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 203899861 # Simulator tick rate (ticks/s) -host_mem_usage 220092 # Number of bytes of host memory used -host_seconds 0.06 # Real time elapsed on the host +host_inst_rate 54505 # Simulator instruction rate (inst/s) +host_op_rate 54495 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 137205108 # Simulator tick rate (ticks/s) +host_mem_usage 220060 # Number of bytes of host memory used +host_seconds 0.10 # Real time elapsed on the host sim_insts 5169 # Number of instructions simulated sim_ops 5169 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 21632 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9152 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 21760 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9024 # Number of bytes read from this memory system.physmem.bytes_read::total 30784 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 21632 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 21632 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 338 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 143 # Number of read requests responded to by this memory +system.physmem.bytes_inst_read::cpu.inst 21760 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 21760 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 340 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 141 # Number of read requests responded to by this memory system.physmem.num_reads::total 481 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1733541692 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 733421485 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2466963177 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1733541692 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1733541692 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1733541692 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 733421485 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2466963177 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1671724350 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 693273922 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2364998271 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1671724350 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1671724350 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1671724350 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 693273922 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2364998271 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses system.cpu.dtb.read_accesses 0 # DTB read accesses @@ -46,245 +46,245 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 8 # Number of system calls -system.cpu.numCycles 24958 # number of cpu cycles simulated +system.cpu.numCycles 26034 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 2172 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 1452 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 447 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 1660 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 457 # Number of BTB hits +system.cpu.BPredUnit.lookups 2148 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 1448 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 450 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 1662 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 462 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 278 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 71 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 8142 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 13207 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2172 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 735 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 3199 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1325 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 670 # Number of cycles fetch has spent blocked +system.cpu.BPredUnit.usedRAS 263 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 67 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 8866 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 13061 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2148 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 725 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 3176 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1340 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 826 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 143 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 1938 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 262 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 13025 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.013973 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.329859 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 1948 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 270 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 13893 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.940114 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.257377 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 9826 75.44% 75.44% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1298 9.97% 85.40% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 113 0.87% 86.27% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 139 1.07% 87.34% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 293 2.25% 89.59% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 102 0.78% 90.37% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 157 1.21% 91.58% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 134 1.03% 92.61% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 963 7.39% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 10717 77.14% 77.14% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1298 9.34% 86.48% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 110 0.79% 87.27% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 134 0.96% 88.24% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 300 2.16% 90.40% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 103 0.74% 91.14% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 148 1.07% 92.20% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 126 0.91% 93.11% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 957 6.89% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 13025 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.087026 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.529169 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 8327 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 818 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 3014 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 41 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 825 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 136 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 46 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 12256 # Number of instructions handled by decode +system.cpu.fetch.rateDist::total 13893 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.082507 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.501690 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 9037 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 974 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 2996 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 51 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 835 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 145 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 47 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 12168 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 188 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 825 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 8509 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 222 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 499 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2873 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 97 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 11712 # Number of instructions processed by rename -system.cpu.rename.LSQFullEvents 88 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 7146 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 13901 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 13897 # Number of integer rename lookups +system.cpu.rename.SquashCycles 835 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 9227 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 288 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 540 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 2860 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 143 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 11638 # Number of instructions processed by rename +system.cpu.rename.LSQFullEvents 129 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 7046 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 13805 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 13801 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 4 # Number of floating rename lookups system.cpu.rename.CommittedMaps 3410 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 3736 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 18 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 11 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 266 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2476 # Number of loads inserted to the mem dependence unit. +system.cpu.rename.UndoneMaps 3636 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 16 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 10 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 308 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2447 # Number of loads inserted to the mem dependence unit. system.cpu.memDep0.insertedStores 1180 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 1 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 1 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 9032 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 13 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 8121 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 52 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 3346 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 2009 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 3 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 13025 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.623493 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.295831 # Number of insts issued each cycle +system.cpu.iq.iqInstsAdded 9050 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 12 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 8137 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 46 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 3435 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1984 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 13893 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.585691 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.249798 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 9566 73.44% 73.44% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1360 10.44% 83.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 840 6.45% 90.33% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 535 4.11% 94.44% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 357 2.74% 97.18% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 221 1.70% 98.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 96 0.74% 99.62% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 33 0.25% 99.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 17 0.13% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 10352 74.51% 74.51% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1446 10.41% 84.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 850 6.12% 91.04% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 537 3.87% 94.90% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 350 2.52% 97.42% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 226 1.63% 99.05% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 89 0.64% 99.69% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 28 0.20% 99.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 15 0.11% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 13025 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 13893 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 4 2.63% 2.63% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 2.63% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 2.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 2.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 2.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 2.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.63% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 96 63.16% 65.79% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 3 1.97% 1.97% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 1.97% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 1.97% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.97% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.97% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.97% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 1.97% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.97% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 1.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 1.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.97% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 97 63.82% 65.79% # attempts to use FU when none available system.cpu.iq.fu_full::MemWrite 52 34.21% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 4783 58.90% 58.90% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 4 0.05% 58.95% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 2 0.02% 58.97% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 59.00% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 59.00% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 59.00% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 59.00% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.00% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.00% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2243 27.62% 86.61% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1087 13.39% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 4825 59.30% 59.30% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 5 0.06% 59.36% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 2 0.02% 59.38% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 59.41% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 59.41% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 59.41% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 59.41% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.41% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.41% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2212 27.18% 86.59% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1091 13.41% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 8121 # Type of FU issued -system.cpu.iq.rate 0.325387 # Inst issue rate +system.cpu.iq.FU_type_0::total 8137 # Type of FU issued +system.cpu.iq.rate 0.312553 # Inst issue rate system.cpu.iq.fu_busy_cnt 152 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.018717 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 29467 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 12396 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 7292 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fu_busy_rate 0.018680 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 30361 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 12504 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 7339 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 4 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 2 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 2 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 8271 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 8287 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 2 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 61 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 60 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1312 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 4 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 7 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedLoads 1283 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 9 # Number of memory ordering violations system.cpu.iew.lsq.thread0.squashedStores 255 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 825 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 149 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 10 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 10514 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 112 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2476 # Number of dispatched load instructions +system.cpu.iew.iewSquashCycles 835 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 148 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 16 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 10551 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 78 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2447 # Number of dispatched load instructions system.cpu.iew.iewDispStoreInsts 1180 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 13 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispNonSpecInsts 12 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 2 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 1 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 7 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 107 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 373 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 480 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 7766 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 2126 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 355 # Number of squashed instructions skipped in execute +system.cpu.iew.memOrderViolationEvents 9 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 101 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 378 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 479 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 7784 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 2096 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 353 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1469 # number of nop insts executed -system.cpu.iew.exec_refs 3191 # number of memory reference insts executed -system.cpu.iew.exec_branches 1304 # Number of branches executed -system.cpu.iew.exec_stores 1065 # Number of stores executed -system.cpu.iew.exec_rate 0.311163 # Inst execution rate -system.cpu.iew.wb_sent 7392 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 7294 # cumulative count of insts written-back -system.cpu.iew.wb_producers 2836 # num instructions producing a value -system.cpu.iew.wb_consumers 4075 # num instructions consuming a value +system.cpu.iew.exec_nop 1489 # number of nop insts executed +system.cpu.iew.exec_refs 3163 # number of memory reference insts executed +system.cpu.iew.exec_branches 1325 # Number of branches executed +system.cpu.iew.exec_stores 1067 # Number of stores executed +system.cpu.iew.exec_rate 0.298994 # Inst execution rate +system.cpu.iew.wb_sent 7431 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 7341 # cumulative count of insts written-back +system.cpu.iew.wb_producers 2840 # num instructions producing a value +system.cpu.iew.wb_consumers 4066 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.292251 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.695951 # average fanout of values written-back +system.cpu.iew.wb_rate 0.281977 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.698475 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 5826 # The number of committed instructions system.cpu.commit.commitCommittedOps 5826 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 4683 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 4721 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 10 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 402 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 12200 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.477541 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.256570 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 404 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 13058 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.446163 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.225344 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 9781 80.17% 80.17% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1000 8.20% 88.37% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 629 5.16% 93.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 333 2.73% 96.25% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 158 1.30% 97.55% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 93 0.76% 98.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 67 0.55% 98.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 42 0.34% 99.20% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 97 0.80% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 10619 81.32% 81.32% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1036 7.93% 89.26% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 643 4.92% 94.18% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 305 2.34% 96.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 154 1.18% 97.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 84 0.64% 98.34% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 72 0.55% 98.89% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 39 0.30% 99.19% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 106 0.81% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 12200 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 13058 # Number of insts commited each cycle system.cpu.commit.committedInsts 5826 # Number of instructions committed system.cpu.commit.committedOps 5826 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -295,69 +295,69 @@ system.cpu.commit.branches 916 # Nu system.cpu.commit.fp_insts 2 # Number of committed floating point instructions. system.cpu.commit.int_insts 5124 # Number of committed integer instructions. system.cpu.commit.function_calls 87 # Number of function calls committed. -system.cpu.commit.bw_lim_events 97 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 106 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 22599 # The number of ROB reads -system.cpu.rob.rob_writes 21853 # The number of ROB writes -system.cpu.timesIdled 249 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 11933 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 23486 # The number of ROB reads +system.cpu.rob.rob_writes 21936 # The number of ROB writes +system.cpu.timesIdled 270 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 12141 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 5169 # Number of Instructions Simulated system.cpu.committedOps 5169 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 5169 # Number of Instructions Simulated -system.cpu.cpi 4.828400 # CPI: Cycles Per Instruction -system.cpu.cpi_total 4.828400 # CPI: Total CPI of All Threads -system.cpu.ipc 0.207108 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.207108 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 10560 # number of integer regfile reads -system.cpu.int_regfile_writes 5130 # number of integer regfile writes +system.cpu.cpi 5.036564 # CPI: Cycles Per Instruction +system.cpu.cpi_total 5.036564 # CPI: Total CPI of All Threads +system.cpu.ipc 0.198548 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.198548 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 10600 # number of integer regfile reads +system.cpu.int_regfile_writes 5152 # number of integer regfile writes system.cpu.fp_regfile_reads 3 # number of floating regfile reads system.cpu.fp_regfile_writes 1 # number of floating regfile writes -system.cpu.misc_regfile_reads 150 # number of misc regfile reads +system.cpu.misc_regfile_reads 155 # number of misc regfile reads system.cpu.icache.replacements 17 # number of replacements -system.cpu.icache.tagsinuse 163.784522 # Cycle average of tags in use -system.cpu.icache.total_refs 1503 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 341 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 4.407625 # Average number of references to valid blocks. +system.cpu.icache.tagsinuse 163.172601 # Cycle average of tags in use +system.cpu.icache.total_refs 1511 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 343 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 4.405248 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 163.784522 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.079973 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.079973 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 1503 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1503 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1503 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1503 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1503 # number of overall hits -system.cpu.icache.overall_hits::total 1503 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 435 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 435 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 435 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 435 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 435 # number of overall misses -system.cpu.icache.overall_misses::total 435 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 15599500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 15599500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 15599500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 15599500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 15599500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 15599500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1938 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1938 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1938 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1938 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1938 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1938 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.224458 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.224458 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.224458 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.224458 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.224458 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.224458 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35860.919540 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 35860.919540 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 35860.919540 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 35860.919540 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 35860.919540 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 35860.919540 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 163.172601 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.079674 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.079674 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 1511 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1511 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1511 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1511 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1511 # number of overall hits +system.cpu.icache.overall_hits::total 1511 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 437 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 437 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 437 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 437 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 437 # number of overall misses +system.cpu.icache.overall_misses::total 437 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 15987000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 15987000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 15987000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 15987000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 15987000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 15987000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1948 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1948 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1948 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1948 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1948 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1948 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.224333 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.224333 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.224333 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.224333 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.224333 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.224333 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 36583.524027 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 36583.524027 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 36583.524027 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 36583.524027 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 36583.524027 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 36583.524027 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -372,88 +372,88 @@ system.cpu.icache.demand_mshr_hits::cpu.inst 94 system.cpu.icache.demand_mshr_hits::total 94 # number of demand (read+write) MSHR hits system.cpu.icache.overall_mshr_hits::cpu.inst 94 # number of overall MSHR hits system.cpu.icache.overall_mshr_hits::total 94 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 341 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 341 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 341 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 341 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 341 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 341 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11963500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 11963500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11963500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 11963500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11963500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 11963500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.175955 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.175955 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.175955 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.175955 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.175955 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.175955 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35083.577713 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 35083.577713 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35083.577713 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 35083.577713 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35083.577713 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 35083.577713 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 343 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 343 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 343 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 343 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 343 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 343 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12452000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 12452000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12452000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 12452000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12452000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 12452000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.176078 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.176078 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.176078 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.176078 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.176078 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.176078 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36303.206997 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 36303.206997 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36303.206997 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 36303.206997 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36303.206997 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 36303.206997 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 92.268506 # Cycle average of tags in use -system.cpu.dcache.total_refs 2489 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 143 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 17.405594 # Average number of references to valid blocks. +system.cpu.dcache.tagsinuse 91.140441 # Cycle average of tags in use +system.cpu.dcache.total_refs 2441 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 141 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 17.312057 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 92.268506 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.022526 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.022526 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 1903 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1903 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 586 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 586 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 2489 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2489 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2489 # number of overall hits -system.cpu.dcache.overall_hits::total 2489 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 133 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 133 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 339 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 339 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 472 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 472 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 472 # number of overall misses -system.cpu.dcache.overall_misses::total 472 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 4784500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 4784500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 11421000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 11421000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 16205500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 16205500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 16205500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 16205500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 2036 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 2036 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.occ_blocks::cpu.data 91.140441 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.022251 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.022251 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 1863 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1863 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 578 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 578 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 2441 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2441 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2441 # number of overall hits +system.cpu.dcache.overall_hits::total 2441 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 148 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 148 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 347 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 347 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 495 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 495 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 495 # number of overall misses +system.cpu.dcache.overall_misses::total 495 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5658500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5658500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 13040000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 13040000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 18698500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 18698500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 18698500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 18698500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 2011 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 2011 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 925 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 925 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2961 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2961 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2961 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2961 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.065324 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.065324 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.366486 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.366486 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.159406 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.159406 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.159406 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.159406 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 35973.684211 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 35973.684211 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33690.265487 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 33690.265487 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 34333.686441 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 34333.686441 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 34333.686441 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 34333.686441 # average overall miss latency +system.cpu.dcache.demand_accesses::cpu.data 2936 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2936 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2936 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2936 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.073595 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.073595 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.375135 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.375135 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.168597 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.168597 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.168597 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.168597 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 38233.108108 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 38233.108108 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37579.250720 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 37579.250720 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 37774.747475 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 37774.747475 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 37774.747475 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 37774.747475 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -462,119 +462,119 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 41 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 41 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 288 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 288 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 329 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 329 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 329 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 329 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 92 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 92 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 58 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 58 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 296 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 296 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 354 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 354 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 354 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 354 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 90 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 90 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 51 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 51 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 143 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 143 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 143 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 143 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3306000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 3306000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1845000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1845000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5151000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 5151000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5151000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 5151000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.045187 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.045187 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_misses::cpu.data 141 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 141 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 141 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 141 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3847000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 3847000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2081000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2081000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5928000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 5928000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5928000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 5928000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.044754 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.044754 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055135 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.055135 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.048294 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.048294 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.048294 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.048294 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 35934.782609 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 35934.782609 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 36176.470588 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 36176.470588 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 36020.979021 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 36020.979021 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 36020.979021 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 36020.979021 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.048025 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.048025 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.048025 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.048025 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 42744.444444 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 42744.444444 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 40803.921569 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40803.921569 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 42042.553191 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 42042.553191 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 42042.553191 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 42042.553191 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 224.190745 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 222.725864 # Cycle average of tags in use system.cpu.l2cache.total_refs 3 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 430 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.006977 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 165.976213 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 58.214532 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.005065 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.001777 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.006842 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 165.335127 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 57.390737 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.005046 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.001751 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.006797 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 3 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 3 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 3 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::total 3 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.inst 3 # number of overall hits system.cpu.l2cache.overall_hits::total 3 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 338 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 92 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.inst 340 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 90 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::total 430 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 51 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 51 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 338 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 143 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 340 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 141 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::total 481 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 338 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 143 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.inst 340 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 141 # number of overall misses system.cpu.l2cache.overall_misses::total 481 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 11593500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3178500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 14772000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1768500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 1768500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 11593500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 4947000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 16540500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 11593500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 4947000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 16540500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 341 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 92 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 12086500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3738500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 15825000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1998000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 1998000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 12086500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 5736500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 17823000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 12086500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 5736500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 17823000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 343 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 90 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 433 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 51 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 51 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 341 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 143 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 343 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 141 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::total 484 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 341 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 143 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 343 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 141 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 484 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.991202 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.991254 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::total 0.993072 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.991202 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.991254 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::total 0.993802 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.991202 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.991254 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.993802 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34300.295858 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34548.913043 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 34353.488372 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34676.470588 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34676.470588 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34300.295858 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34594.405594 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 34387.733888 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34300.295858 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34594.405594 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 34387.733888 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35548.529412 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 41538.888889 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 36802.325581 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 39176.470588 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 39176.470588 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35548.529412 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 40684.397163 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 37054.054054 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35548.529412 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 40684.397163 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 37054.054054 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -583,50 +583,50 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 338 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 92 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 340 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 90 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::total 430 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 51 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 51 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 338 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 143 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 340 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 141 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::total 481 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 338 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 143 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 340 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 141 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 481 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10498500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2890500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13389000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1604000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1604000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10498500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4494500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 14993000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10498500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4494500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 14993000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.991202 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10999000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3463000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14462000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1839500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1839500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10999000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5302500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 16301500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10999000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5302500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 16301500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.991254 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.993072 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.991202 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.991254 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::total 0.993802 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.991202 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.991254 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.993802 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31060.650888 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31418.478261 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31137.209302 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31450.980392 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31450.980392 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31060.650888 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31430.069930 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31170.478170 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31060.650888 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31430.069930 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31170.478170 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32350 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 38477.777778 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 33632.558140 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36068.627451 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36068.627451 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32350 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 37606.382979 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 33890.852391 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32350 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 37606.382979 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 33890.852391 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/config.ini b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/config.ini index f7cc4efef..1e54677ab 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/config.ini +++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/config.ini @@ -148,7 +148,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side @@ -180,7 +180,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.physmem.port[0] slave=system.system_port system.cpu.l2cache.mem_side diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/simout b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/simout index ac53df969..3ee3fb923 100755 --- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/simout +++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 11:58:11 -gem5 started Jun 4 2012 14:43:48 +gem5 compiled Jul 2 2012 08:47:33 +gem5 started Jul 2 2012 11:29:16 gem5 executing on zizzer -command line: build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing -re tests/run.py build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing +command line: build/MIPS/gem5.fast -d build/MIPS/tests/fast/quick/se/00.hello/mips/linux/simple-timing -re tests/run.py build/MIPS/tests/fast/quick/se/00.hello/mips/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello World! -Exiting @ tick 32088000 because target called exit() +Exiting @ tick 33413000 because target called exit() diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt index 8f49928a9..eb8915cb4 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000032 # Number of seconds simulated -sim_ticks 32088000 # Number of ticks simulated -final_tick 32088000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000033 # Number of seconds simulated +sim_ticks 33413000 # Number of ticks simulated +final_tick 33413000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 540307 # Simulator instruction rate (inst/s) -host_op_rate 539410 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2965678153 # Simulator tick rate (ticks/s) -host_mem_usage 215020 # Number of bytes of host memory used -host_seconds 0.01 # Real time elapsed on the host +host_inst_rate 168189 # Simulator instruction rate (inst/s) +host_op_rate 168105 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 963489284 # Simulator tick rate (ticks/s) +host_mem_usage 219036 # Number of bytes of host memory used +host_seconds 0.03 # Real time elapsed on the host sim_insts 5827 # Number of instructions simulated sim_ops 5827 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 19264 # Number of bytes read from this memory @@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 19264 # Nu system.physmem.num_reads::cpu.inst 301 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 138 # Number of read requests responded to by this memory system.physmem.num_reads::total 439 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 600349040 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 275243082 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 875592122 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 600349040 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 600349040 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 600349040 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 275243082 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 875592122 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 576542064 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 264328255 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 840870320 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 576542064 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 576542064 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 576542064 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 264328255 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 840870320 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses system.cpu.dtb.read_accesses 0 # DTB read accesses @@ -46,7 +46,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 8 # Number of system calls -system.cpu.numCycles 64176 # number of cpu cycles simulated +system.cpu.numCycles 66826 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 5827 # Number of instructions committed @@ -65,18 +65,18 @@ system.cpu.num_mem_refs 2090 # nu system.cpu.num_load_insts 1164 # Number of load instructions system.cpu.num_store_insts 926 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 64176 # Number of busy cycles +system.cpu.num_busy_cycles 66826 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 13 # number of replacements -system.cpu.icache.tagsinuse 132.493866 # Cycle average of tags in use +system.cpu.icache.tagsinuse 133.092783 # Cycle average of tags in use system.cpu.icache.total_refs 5526 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 303 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 18.237624 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 132.493866 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.064694 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.064694 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::cpu.inst 133.092783 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.064987 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.064987 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 5526 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 5526 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 5526 # number of demand (read+write) hits @@ -147,14 +147,14 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52722.772277 system.cpu.icache.overall_avg_mshr_miss_latency::total 52722.772277 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 87.458397 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 87.717237 # Cycle average of tags in use system.cpu.dcache.total_refs 1951 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 138 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 14.137681 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 87.458397 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.021352 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.021352 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::cpu.data 87.717237 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.021415 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.021415 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 1077 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1077 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 874 # number of WriteReq hits @@ -245,16 +245,16 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 188.045319 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 188.818071 # Cycle average of tags in use system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 388 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.005155 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 133.837577 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 54.207742 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.004084 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.001654 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.005739 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 134.446837 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 54.371234 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.004103 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.001659 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.005762 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits diff --git a/tests/quick/se/00.hello/ref/power/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/power/linux/o3-timing/config.ini index 928f0469f..fe01ee3c1 100644 --- a/tests/quick/se/00.hello/ref/power/linux/o3-timing/config.ini +++ b/tests/quick/se/00.hello/ref/power/linux/o3-timing/config.ini @@ -480,7 +480,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side @@ -512,7 +512,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.physmem.port[0] slave=system.system_port system.cpu.l2cache.mem_side diff --git a/tests/quick/se/00.hello/ref/power/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/power/linux/o3-timing/simout index 584102e9c..4c16f50ba 100755 --- a/tests/quick/se/00.hello/ref/power/linux/o3-timing/simout +++ b/tests/quick/se/00.hello/ref/power/linux/o3-timing/simout @@ -1,11 +1,11 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 28 2012 22:05:18 -gem5 started Jun 28 2012 22:53:15 +gem5 compiled Jul 2 2012 08:50:36 +gem5 started Jul 2 2012 11:29:39 gem5 executing on zizzer command line: build/POWER/gem5.fast -d build/POWER/tests/fast/quick/se/00.hello/power/linux/o3-timing -re tests/run.py build/POWER/tests/fast/quick/se/00.hello/power/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 11179000 because target called exit() +Exiting @ tick 11812000 because target called exit() diff --git a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt index f8f7991bd..0b8cd16ea 100644 --- a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt @@ -1,32 +1,32 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000011 # Number of seconds simulated -sim_ticks 11179000 # Number of ticks simulated -final_tick 11179000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000012 # Number of seconds simulated +sim_ticks 11812000 # Number of ticks simulated +final_tick 11812000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 61972 # Simulator instruction rate (inst/s) -host_op_rate 61960 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 119400246 # Simulator tick rate (ticks/s) -host_mem_usage 216052 # Number of bytes of host memory used -host_seconds 0.09 # Real time elapsed on the host +host_inst_rate 59914 # Simulator instruction rate (inst/s) +host_op_rate 59903 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 121974515 # Simulator tick rate (ticks/s) +host_mem_usage 216016 # Number of bytes of host memory used +host_seconds 0.10 # Real time elapsed on the host sim_insts 5800 # Number of instructions simulated sim_ops 5800 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 22400 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 6464 # Number of bytes read from this memory -system.physmem.bytes_read::total 28864 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 22400 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 22400 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 350 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 101 # Number of read requests responded to by this memory -system.physmem.num_reads::total 451 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 2003757044 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 578227033 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2581984077 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 2003757044 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 2003757044 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 2003757044 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 578227033 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2581984077 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 22528 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 6400 # Number of bytes read from this memory +system.physmem.bytes_read::total 28928 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 22528 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 22528 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 352 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 100 # Number of read requests responded to by this memory +system.physmem.num_reads::total 452 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1907213004 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 541821876 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2449034880 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1907213004 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1907213004 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1907213004 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 541821876 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2449034880 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses system.cpu.dtb.read_accesses 0 # DTB read accesses @@ -46,245 +46,245 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 9 # Number of system calls -system.cpu.numCycles 22359 # number of cpu cycles simulated +system.cpu.numCycles 23625 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 2487 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 2038 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 457 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 2063 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 631 # Number of BTB hits +system.cpu.BPredUnit.lookups 2490 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 2041 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 460 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 2061 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 629 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 157 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 28 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 6834 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 14542 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2487 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 788 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 2415 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1412 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 813 # Number of cycles fetch has spent blocked +system.cpu.BPredUnit.usedRAS 162 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 30 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 7441 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 14561 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2490 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 791 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 2421 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1432 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 932 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.CacheLines 1887 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 310 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 11013 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.320439 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.737355 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 1897 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 321 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 11761 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.238075 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.668941 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 8598 78.07% 78.07% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 170 1.54% 79.62% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 167 1.52% 81.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 144 1.31% 82.44% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 198 1.80% 84.24% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 151 1.37% 85.61% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 257 2.33% 87.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 107 0.97% 88.91% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1221 11.09% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 9340 79.42% 79.42% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 172 1.46% 80.88% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 167 1.42% 82.30% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 146 1.24% 83.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 197 1.68% 85.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 155 1.32% 86.53% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 255 2.17% 88.70% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 108 0.92% 89.62% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1221 10.38% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 11013 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.111230 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.650387 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 7023 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 884 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2239 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 74 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 793 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 359 # Number of times decode resolved a branch +system.cpu.fetch.rateDist::total 11761 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.105397 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.616339 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 7565 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 1069 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 2256 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 64 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 807 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 361 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 160 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 12898 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 445 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 793 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 7240 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 304 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 345 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2086 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 245 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 12206 # Number of instructions processed by rename -system.cpu.rename.IQFullEvents 3 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 201 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 10543 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 19911 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 19856 # Number of integer rename lookups +system.cpu.decode.DecodedInsts 12930 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 452 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 807 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 7781 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 440 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 384 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 2100 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 249 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 12283 # Number of instructions processed by rename +system.cpu.rename.IQFullEvents 13 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 203 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 10602 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 20025 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 19970 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 55 # Number of floating rename lookups system.cpu.rename.CommittedMaps 5007 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 5536 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 25 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 25 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 518 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2072 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1895 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 60 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 30 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 10882 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 61 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 9264 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 154 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 4859 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 4160 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 45 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 11013 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.841188 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.574613 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 5595 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 26 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 26 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 552 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2098 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1917 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 63 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 31 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 11001 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 65 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 9282 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 167 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 4968 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 4343 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 49 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 11761 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.789219 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.523023 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 7627 69.25% 69.25% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1067 9.69% 78.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 747 6.78% 85.73% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 527 4.79% 90.51% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 479 4.35% 94.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 323 2.93% 97.79% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 151 1.37% 99.16% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 51 0.46% 99.63% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 41 0.37% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 8303 70.60% 70.60% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1127 9.58% 80.18% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 767 6.52% 86.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 536 4.56% 91.26% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 478 4.06% 95.32% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 324 2.75% 98.08% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 139 1.18% 99.26% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 49 0.42% 99.68% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 38 0.32% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 11013 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 11761 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 6 3.35% 3.35% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 3.35% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 3.35% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.35% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.35% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.35% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 3.35% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.35% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 3.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 3.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.35% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 80 44.69% 48.04% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 93 51.96% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 5 2.87% 2.87% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 2.87% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 2.87% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.87% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.87% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.87% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 2.87% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.87% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 2.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 2.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.87% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 78 44.83% 47.70% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 91 52.30% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 5707 61.60% 61.60% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 61.60% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.60% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 61.63% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.63% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.63% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.63% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.63% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.63% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.63% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.63% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.63% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.63% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.63% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.63% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.63% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.63% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.63% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.63% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.63% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.63% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.63% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.63% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 61.63% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.63% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 61.63% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.63% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.63% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.63% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 1853 20.00% 81.63% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1702 18.37% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 5709 61.51% 61.51% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 61.51% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.51% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 61.53% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.53% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.53% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.53% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.53% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 61.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 61.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.53% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 1861 20.05% 81.58% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1710 18.42% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 9264 # Type of FU issued -system.cpu.iq.rate 0.414330 # Inst issue rate -system.cpu.iq.fu_busy_cnt 179 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.019322 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 29812 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 15773 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 8347 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 9282 # Type of FU issued +system.cpu.iq.rate 0.392889 # Inst issue rate +system.cpu.iq.fu_busy_cnt 174 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.018746 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 30604 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 16005 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 8374 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 62 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 36 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 27 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 9409 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 9422 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 34 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 65 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 70 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1110 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1136 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 7 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 849 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 871 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 793 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 112 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 15 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 10943 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 107 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2072 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1895 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 51 # Number of dispatched non-speculative instructions +system.cpu.iew.iewSquashCycles 807 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 227 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 22 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 11066 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 108 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2098 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1917 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 54 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 9 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 2 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 3 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 7 # Number of memory order violations system.cpu.iew.predictedTakenIncorrect 78 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 311 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 389 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 8757 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 1710 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 507 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedNotTakenIncorrect 309 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 387 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 8779 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 1716 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 503 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 3276 # number of memory reference insts executed +system.cpu.iew.exec_refs 3289 # number of memory reference insts executed system.cpu.iew.exec_branches 1382 # Number of branches executed -system.cpu.iew.exec_stores 1566 # Number of stores executed -system.cpu.iew.exec_rate 0.391654 # Inst execution rate -system.cpu.iew.wb_sent 8550 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 8374 # cumulative count of insts written-back -system.cpu.iew.wb_producers 4334 # num instructions producing a value -system.cpu.iew.wb_consumers 6981 # num instructions consuming a value +system.cpu.iew.exec_stores 1573 # Number of stores executed +system.cpu.iew.exec_rate 0.371598 # Inst execution rate +system.cpu.iew.wb_sent 8575 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 8401 # cumulative count of insts written-back +system.cpu.iew.wb_producers 4358 # num instructions producing a value +system.cpu.iew.wb_consumers 6997 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.374525 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.620828 # average fanout of values written-back +system.cpu.iew.wb_rate 0.355598 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.622838 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 5800 # The number of committed instructions system.cpu.commit.commitCommittedOps 5800 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 5152 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 5275 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 16 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 300 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 10220 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.567515 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.347907 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 301 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 10954 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.529487 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.308345 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 7783 76.15% 76.15% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1041 10.19% 86.34% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 649 6.35% 92.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 256 2.50% 95.20% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 188 1.84% 97.04% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 108 1.06% 98.09% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 57 0.56% 98.65% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 45 0.44% 99.09% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 93 0.91% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 8509 77.68% 77.68% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1052 9.60% 87.28% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 645 5.89% 93.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 263 2.40% 95.57% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 183 1.67% 97.24% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 104 0.95% 98.19% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 63 0.58% 98.77% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 41 0.37% 99.14% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 94 0.86% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 10220 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 10954 # Number of insts commited each cycle system.cpu.commit.committedInsts 5800 # Number of instructions committed system.cpu.commit.committedOps 5800 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -295,68 +295,68 @@ system.cpu.commit.branches 1038 # Nu system.cpu.commit.fp_insts 22 # Number of committed floating point instructions. system.cpu.commit.int_insts 5706 # Number of committed integer instructions. system.cpu.commit.function_calls 103 # Number of function calls committed. -system.cpu.commit.bw_lim_events 93 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 94 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 21079 # The number of ROB reads -system.cpu.rob.rob_writes 22698 # The number of ROB writes -system.cpu.timesIdled 215 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 11346 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 21935 # The number of ROB reads +system.cpu.rob.rob_writes 22958 # The number of ROB writes +system.cpu.timesIdled 232 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 11864 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 5800 # Number of Instructions Simulated system.cpu.committedOps 5800 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 5800 # Number of Instructions Simulated -system.cpu.cpi 3.855000 # CPI: Cycles Per Instruction -system.cpu.cpi_total 3.855000 # CPI: Total CPI of All Threads -system.cpu.ipc 0.259403 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.259403 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 13891 # number of integer regfile reads -system.cpu.int_regfile_writes 7248 # number of integer regfile writes +system.cpu.cpi 4.073276 # CPI: Cycles Per Instruction +system.cpu.cpi_total 4.073276 # CPI: Total CPI of All Threads +system.cpu.ipc 0.245503 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.245503 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 13900 # number of integer regfile reads +system.cpu.int_regfile_writes 7266 # number of integer regfile writes system.cpu.fp_regfile_reads 25 # number of floating regfile reads system.cpu.fp_regfile_writes 2 # number of floating regfile writes system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 172.424294 # Cycle average of tags in use -system.cpu.icache.total_refs 1455 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 355 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 4.098592 # Average number of references to valid blocks. +system.cpu.icache.tagsinuse 172.776641 # Cycle average of tags in use +system.cpu.icache.total_refs 1462 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 357 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 4.095238 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 172.424294 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.084192 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.084192 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 1455 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1455 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1455 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1455 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1455 # number of overall hits -system.cpu.icache.overall_hits::total 1455 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 432 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 432 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 432 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 432 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 432 # number of overall misses -system.cpu.icache.overall_misses::total 432 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 15599000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 15599000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 15599000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 15599000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 15599000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 15599000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1887 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1887 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1887 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1887 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1887 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1887 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.228935 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.228935 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.228935 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.228935 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.228935 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.228935 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 36108.796296 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 36108.796296 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 36108.796296 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 36108.796296 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 36108.796296 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 36108.796296 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 172.776641 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.084364 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.084364 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 1462 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1462 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1462 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1462 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1462 # number of overall hits +system.cpu.icache.overall_hits::total 1462 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 435 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 435 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 435 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 435 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 435 # number of overall misses +system.cpu.icache.overall_misses::total 435 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 16386000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 16386000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 16386000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 16386000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 16386000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 16386000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1897 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1897 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1897 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1897 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1897 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1897 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.229309 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.229309 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.229309 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.229309 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.229309 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.229309 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 37668.965517 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 37668.965517 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 37668.965517 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 37668.965517 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 37668.965517 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 37668.965517 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -365,70 +365,70 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 77 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 77 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 77 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 77 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 77 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 77 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 355 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 355 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 355 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 355 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 355 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 355 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12417500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 12417500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12417500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 12417500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12417500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 12417500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.188129 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.188129 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.188129 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.188129 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.188129 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.188129 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 34978.873239 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 34978.873239 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 34978.873239 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 34978.873239 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34978.873239 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 34978.873239 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 78 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 78 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 78 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 78 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 78 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 78 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 357 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 357 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 357 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 357 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 357 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 357 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 13154500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 13154500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 13154500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 13154500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 13154500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 13154500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.188192 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.188192 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.188192 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.188192 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.188192 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.188192 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36847.338936 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 36847.338936 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36847.338936 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 36847.338936 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36847.338936 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 36847.338936 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 63.023619 # Cycle average of tags in use -system.cpu.dcache.total_refs 2216 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 101 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 21.940594 # Average number of references to valid blocks. +system.cpu.dcache.tagsinuse 63.298936 # Cycle average of tags in use +system.cpu.dcache.total_refs 2197 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 100 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 21.970000 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 63.023619 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.015387 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.015387 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 1486 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1486 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 730 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 730 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 2216 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2216 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2216 # number of overall hits -system.cpu.dcache.overall_hits::total 2216 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 86 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 86 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 316 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 316 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 402 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 402 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 402 # number of overall misses -system.cpu.dcache.overall_misses::total 402 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 3106000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 3106000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 10571500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 10571500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 13677500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 13677500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 13677500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 13677500 # number of overall miss cycles +system.cpu.dcache.occ_blocks::cpu.data 63.298936 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.015454 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.015454 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 1480 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1480 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 717 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 717 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 2197 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2197 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2197 # number of overall hits +system.cpu.dcache.overall_hits::total 2197 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 92 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 92 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 329 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 329 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 421 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 421 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 421 # number of overall misses +system.cpu.dcache.overall_misses::total 421 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 3732500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 3732500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 12822500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 12822500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 16555000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 16555000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 16555000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 16555000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 1572 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1572 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 1046 # number of WriteReq accesses(hits+misses) @@ -437,22 +437,22 @@ system.cpu.dcache.demand_accesses::cpu.data 2618 # system.cpu.dcache.demand_accesses::total 2618 # number of demand (read+write) accesses system.cpu.dcache.overall_accesses::cpu.data 2618 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 2618 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.054707 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.054707 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.302103 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.302103 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.153552 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.153552 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.153552 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.153552 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 36116.279070 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 36116.279070 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33454.113924 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 33454.113924 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 34023.631841 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 34023.631841 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 34023.631841 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 34023.631841 # average overall miss latency +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.058524 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.058524 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.314532 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.314532 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.160810 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.160810 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.160810 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.160810 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 40570.652174 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 40570.652174 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38974.164134 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 38974.164134 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 39323.040380 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 39323.040380 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 39323.040380 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 39323.040380 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -461,119 +461,119 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 33 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 33 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 268 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 268 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 301 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 301 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 301 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 301 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 39 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 39 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 282 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 282 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 321 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 321 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 321 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 321 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 53 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 53 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 48 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 48 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 101 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 101 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 101 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 101 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1890500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 1890500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1748500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1748500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 3639000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 3639000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 3639000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 3639000 # number of overall MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 47 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 47 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 100 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 100 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 100 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 100 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2119000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2119000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2085000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2085000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 4204000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 4204000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 4204000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 4204000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.033715 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.033715 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.045889 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.045889 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.038579 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.038579 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.038579 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.038579 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 35669.811321 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 35669.811321 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 36427.083333 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 36427.083333 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 36029.702970 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 36029.702970 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 36029.702970 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 36029.702970 # average overall mshr miss latency +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044933 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.044933 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.038197 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.038197 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.038197 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.038197 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 39981.132075 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 39981.132075 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44361.702128 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44361.702128 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 42040 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 42040 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 42040 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 42040 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 202.260551 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 203.410235 # Cycle average of tags in use system.cpu.l2cache.total_refs 5 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 403 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.012407 # Average number of references to valid blocks. +system.cpu.l2cache.sampled_refs 405 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.012346 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 171.544564 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 30.715987 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.005235 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.000937 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.006173 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 171.891736 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 31.518500 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.005246 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.000962 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.006208 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 5 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 5 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 5 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::total 5 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.inst 5 # number of overall hits system.cpu.l2cache.overall_hits::total 5 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 350 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.inst 352 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.data 53 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 403 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 48 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 48 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 350 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 101 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 451 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 350 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 101 # number of overall misses -system.cpu.l2cache.overall_misses::total 451 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 12033000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1829000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 13862000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1674500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 1674500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 12033000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 3503500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 15536500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 12033000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 3503500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 15536500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 355 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_misses::total 405 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 47 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 47 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 352 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 100 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 452 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 352 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 100 # number of overall misses +system.cpu.l2cache.overall_misses::total 452 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 12780500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2060500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 14841000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2028000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 2028000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 12780500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 4088500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 16869000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 12780500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 4088500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 16869000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 357 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 53 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 408 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 48 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 48 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 355 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 101 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 456 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 355 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 101 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 456 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.985915 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_accesses::total 410 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 47 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 47 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 357 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 100 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 457 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 357 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 100 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 457 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.985994 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.987745 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.987805 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.985915 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.985994 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.989035 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.985915 # miss rate for overall accesses +system.cpu.l2cache.demand_miss_rate::total 0.989059 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.985994 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.989035 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34380 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34509.433962 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 34397.022333 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34885.416667 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34885.416667 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34380 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34688.118812 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 34449.002217 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34380 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34688.118812 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 34449.002217 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::total 0.989059 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 36308.238636 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 38877.358491 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 36644.444444 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 43148.936170 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 43148.936170 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 36308.238636 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 40885 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 37320.796460 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 36308.238636 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 40885 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 37320.796460 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -582,50 +582,50 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 350 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 352 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 53 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 403 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 48 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 48 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 350 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 101 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 451 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 350 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 101 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 451 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10908500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1662000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 12570500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1521500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1521500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10908500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3183500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 14092000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10908500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3183500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 14092000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.985915 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses::total 405 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 47 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 47 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 352 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 100 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 452 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 352 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 100 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 452 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11653500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1896000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13549500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1881500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1881500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11653500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3777500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 15431000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11653500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3777500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 15431000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.985994 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.987745 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.987805 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.985915 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.985994 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.989035 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.985915 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.989059 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.985994 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.989035 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31167.142857 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31358.490566 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31192.307692 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31697.916667 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31697.916667 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31167.142857 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31519.801980 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31246.119734 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31167.142857 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31519.801980 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31246.119734 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.989059 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 33106.534091 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 35773.584906 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 33455.555556 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40031.914894 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40031.914894 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 33106.534091 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 37775 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 34139.380531 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 33106.534091 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 37775 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 34139.380531 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/config.ini b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/config.ini index d62e06b17..dd53d4220 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/config.ini +++ b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/config.ini @@ -181,7 +181,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side @@ -213,7 +213,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.physmem.port[0] slave=system.system_port system.cpu.l2cache.mem_side diff --git a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/simout b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/simout index 76c88733e..a234b881d 100755 --- a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/simout +++ b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 12:01:47 -gem5 started Jun 4 2012 14:44:31 +gem5 compiled Jul 2 2012 08:54:18 +gem5 started Jul 2 2012 11:30:03 gem5 executing on zizzer -command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/inorder-timing -re tests/run.py build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/inorder-timing +command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/quick/se/00.hello/sparc/linux/inorder-timing -re tests/run.py build/SPARC/tests/fast/quick/se/00.hello/sparc/linux/inorder-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... -Hello World!Exiting @ tick 18196500 because target called exit() +Hello World!Exiting @ tick 18885500 because target called exit() diff --git a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt index b45b5b881..fa8b51b5a 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000018 # Number of seconds simulated -sim_ticks 18196500 # Number of ticks simulated -final_tick 18196500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000019 # Number of seconds simulated +sim_ticks 18885500 # Number of ticks simulated +final_tick 18885500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 58781 # Simulator instruction rate (inst/s) -host_op_rate 58769 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 200221364 # Simulator tick rate (ticks/s) -host_mem_usage 221628 # Number of bytes of host memory used -host_seconds 0.09 # Real time elapsed on the host +host_inst_rate 37135 # Simulator instruction rate (inst/s) +host_op_rate 37131 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 131302803 # Simulator tick rate (ticks/s) +host_mem_usage 220012 # Number of bytes of host memory used +host_seconds 0.14 # Real time elapsed on the host sim_insts 5340 # Number of instructions simulated sim_ops 5340 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 18496 # Number of bytes read from this memory @@ -19,28 +19,28 @@ system.physmem.bytes_inst_read::total 18496 # Nu system.physmem.num_reads::cpu.inst 289 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 134 # Number of read requests responded to by this memory system.physmem.num_reads::total 423 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1016459209 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 471299426 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1487758635 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1016459209 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1016459209 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1016459209 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 471299426 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1487758635 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 979375712 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 454105001 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1433480713 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 979375712 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 979375712 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 979375712 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 454105001 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1433480713 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 11 # Number of system calls -system.cpu.numCycles 36394 # number of cpu cycles simulated +system.cpu.numCycles 37772 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.branch_predictor.lookups 1617 # Number of BP lookups +system.cpu.branch_predictor.lookups 1615 # Number of BP lookups system.cpu.branch_predictor.condPredicted 1022 # Number of conditional branches predicted system.cpu.branch_predictor.condIncorrect 899 # Number of conditional branches incorrect -system.cpu.branch_predictor.BTBLookups 1172 # Number of BTB lookups +system.cpu.branch_predictor.BTBLookups 1170 # Number of BTB lookups system.cpu.branch_predictor.BTBHits 435 # Number of BTB hits system.cpu.branch_predictor.usedRAS 67 # Number of times the RAS was used to get a target. system.cpu.branch_predictor.RASInCorrect 4 # Number of incorrect RAS predictions. -system.cpu.branch_predictor.BTBHitPct 37.116041 # BTB Hit Percentage +system.cpu.branch_predictor.BTBHitPct 37.179487 # BTB Hit Percentage system.cpu.branch_predictor.predictedTaken 502 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.predictedNotTaken 1115 # Number of Branches Predicted As Not Taken (False). +system.cpu.branch_predictor.predictedNotTaken 1113 # Number of Branches Predicted As Not Taken (False). system.cpu.regfile_manager.intRegFileReads 5634 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 4000 # Number of Writes to Int. Register File system.cpu.regfile_manager.intRegFileAccesses 9634 # Total Accesses (Read+Write) to the Int. Register File @@ -58,12 +58,12 @@ system.cpu.execution_unit.executions 3979 # Nu system.cpu.mult_div_unit.multiplies 0 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 9708 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 10178 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 421 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 30167 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 6227 # Number of cycles cpu stages are processed. -system.cpu.activity 17.109963 # Percentage of cycles cpu is active +system.cpu.timesIdled 501 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 31527 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 6245 # Number of cycles cpu stages are processed. +system.cpu.activity 16.533411 # Percentage of cycles cpu is active system.cpu.comLoads 716 # Number of Load instructions committed system.cpu.comStores 673 # Number of Store instructions committed system.cpu.comBranches 1116 # Number of Branches instructions committed @@ -75,72 +75,72 @@ system.cpu.committedInsts 5340 # Nu system.cpu.committedOps 5340 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 5340 # Number of Instructions committed (Total) -system.cpu.cpi 6.815356 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 7.073408 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 6.815356 # CPI: Total CPI of All Threads -system.cpu.ipc 0.146727 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 7.073408 # CPI: Total CPI of All Threads +system.cpu.ipc 0.141375 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 0.146727 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 31821 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 4573 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 12.565258 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 33191 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 3203 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 8.800901 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 33344 # Number of cycles 0 instructions are processed. +system.cpu.ipc_total 0.141375 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 33203 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 4569 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 12.096262 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 34575 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 3197 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 8.463942 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 34722 # Number of cycles 0 instructions are processed. system.cpu.stage2.runCycles 3050 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 8.380502 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 35411 # Number of cycles 0 instructions are processed. +system.cpu.stage2.utilization 8.074764 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 36789 # Number of cycles 0 instructions are processed. system.cpu.stage3.runCycles 983 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 2.700995 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 33220 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 3174 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 8.721218 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.utilization 2.602457 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 34600 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 3172 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 8.397755 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 136.672418 # Cycle average of tags in use -system.cpu.icache.total_refs 827 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 136.494329 # Cycle average of tags in use +system.cpu.icache.total_refs 825 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 291 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 2.841924 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 2.835052 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 136.672418 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.066735 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.066735 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 827 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 827 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 827 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 827 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 827 # number of overall hits -system.cpu.icache.overall_hits::total 827 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 347 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 347 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 347 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 347 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 347 # number of overall misses -system.cpu.icache.overall_misses::total 347 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 19107000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 19107000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 19107000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 19107000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 19107000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 19107000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1174 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1174 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1174 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1174 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1174 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1174 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.295571 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.295571 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.295571 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.295571 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.295571 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.295571 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55063.400576 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 55063.400576 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 55063.400576 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 55063.400576 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 55063.400576 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 55063.400576 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 136.494329 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.066648 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.066648 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 825 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 825 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 825 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 825 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 825 # number of overall hits +system.cpu.icache.overall_hits::total 825 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 350 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 350 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 350 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 350 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 350 # number of overall misses +system.cpu.icache.overall_misses::total 350 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 19647000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 19647000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 19647000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 19647000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 19647000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 19647000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1175 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1175 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1175 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1175 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1175 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1175 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.297872 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.297872 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.297872 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.297872 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.297872 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.297872 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56134.285714 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 56134.285714 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 56134.285714 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 56134.285714 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 56134.285714 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 56134.285714 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 106000 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -149,70 +149,70 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets 35333.333333 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 56 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 56 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 56 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 56 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 56 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 56 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 59 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 59 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 59 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 59 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 59 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 59 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 291 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 291 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 291 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 291 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 291 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 291 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15468000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 15468000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15468000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 15468000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15468000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 15468000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.247871 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.247871 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.247871 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.247871 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.247871 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.247871 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53154.639175 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53154.639175 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53154.639175 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 53154.639175 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53154.639175 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 53154.639175 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15992500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 15992500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15992500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 15992500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15992500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 15992500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.247660 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.247660 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.247660 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.247660 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.247660 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.247660 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54957.044674 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54957.044674 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54957.044674 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 54957.044674 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54957.044674 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 54957.044674 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 82.864730 # Cycle average of tags in use -system.cpu.dcache.total_refs 1049 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 82.670041 # Cycle average of tags in use +system.cpu.dcache.total_refs 1046 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 135 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 7.770370 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 7.748148 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 82.864730 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.020231 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.020231 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 657 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 657 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 392 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 392 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 1049 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 1049 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 1049 # number of overall hits -system.cpu.dcache.overall_hits::total 1049 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 59 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 59 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 281 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 281 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 340 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 340 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 340 # number of overall misses -system.cpu.dcache.overall_misses::total 340 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 3291500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 3291500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 15458000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 15458000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 18749500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 18749500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 18749500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 18749500 # number of overall miss cycles +system.cpu.dcache.occ_blocks::cpu.data 82.670041 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.020183 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.020183 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 655 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 655 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 391 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 391 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 1046 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 1046 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 1046 # number of overall hits +system.cpu.dcache.overall_hits::total 1046 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 61 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 61 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 282 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 282 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 343 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 343 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 343 # number of overall misses +system.cpu.dcache.overall_misses::total 343 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 3569500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 3569500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 17306500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 17306500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 20876000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 20876000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 20876000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 20876000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 716 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 716 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 673 # number of WriteReq accesses(hits+misses) @@ -221,38 +221,38 @@ system.cpu.dcache.demand_accesses::cpu.data 1389 # system.cpu.dcache.demand_accesses::total 1389 # number of demand (read+write) accesses system.cpu.dcache.overall_accesses::cpu.data 1389 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 1389 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.082402 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.082402 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.417533 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.417533 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.244780 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.244780 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.244780 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.244780 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55788.135593 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 55788.135593 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55010.676157 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 55010.676157 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 55145.588235 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 55145.588235 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 55145.588235 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 55145.588235 # average overall miss latency +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.085196 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.085196 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.419019 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.419019 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.246940 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.246940 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.246940 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.246940 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 58516.393443 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 58516.393443 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61370.567376 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 61370.567376 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 60862.973761 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 60862.973761 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 60862.973761 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 60862.973761 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 2259500 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 2306500 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 45 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 50211.111111 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 51255.555556 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 5 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 5 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 200 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 200 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 205 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 205 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 205 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 205 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 7 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 7 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 201 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 201 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 208 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 208 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 208 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 208 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 54 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 54 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 81 # number of WriteReq MSHR misses @@ -261,14 +261,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 135 system.cpu.dcache.demand_mshr_misses::total 135 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 135 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 135 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2866000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2866000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4327500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4327500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7193500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 7193500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7193500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 7193500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3065000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 3065000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4526000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4526000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7591000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 7591000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7591000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 7591000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.075419 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.075419 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.120357 # mshr miss rate for WriteReq accesses @@ -277,26 +277,26 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.097192 system.cpu.dcache.demand_mshr_miss_rate::total 0.097192 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.097192 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.097192 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53074.074074 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53074.074074 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53425.925926 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53425.925926 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53285.185185 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 53285.185185 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53285.185185 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 53285.185185 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 56759.259259 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 56759.259259 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 55876.543210 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 55876.543210 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 56229.629630 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 56229.629630 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 56229.629630 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 56229.629630 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 162.299655 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 162.084916 # Cycle average of tags in use system.cpu.l2cache.total_refs 3 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 342 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.008772 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 136.188396 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 26.111259 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.004156 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.000797 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.004953 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 136.002391 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 26.082525 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.004150 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.000796 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.004946 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 1 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 3 # number of ReadReq hits @@ -317,17 +317,17 @@ system.cpu.l2cache.demand_misses::total 423 # nu system.cpu.l2cache.overall_misses::cpu.inst 289 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 134 # number of overall misses system.cpu.l2cache.overall_misses::total 423 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 15131000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2786500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 17917500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4230500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 4230500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 15131000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 7017000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 22148000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 15131000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 7017000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 22148000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 15656000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2985500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 18641500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4434500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 4434500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 15656000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 7420000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 23076000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 15656000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 7420000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 23076000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 291 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 54 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 345 # number of ReadReq accesses(hits+misses) @@ -350,17 +350,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.992958 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993127 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.992593 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.992958 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52356.401384 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52575.471698 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52390.350877 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52228.395062 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52228.395062 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52356.401384 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52365.671642 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52359.338061 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52356.401384 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52365.671642 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52359.338061 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 54173.010381 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 56330.188679 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 54507.309942 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 54746.913580 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 54746.913580 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 54173.010381 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 55373.134328 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 54553.191489 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 54173.010381 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 55373.134328 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 54553.191489 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -380,17 +380,17 @@ system.cpu.l2cache.demand_mshr_misses::total 423 system.cpu.l2cache.overall_mshr_misses::cpu.inst 289 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 134 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 423 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11603500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2143500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13747000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3255500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3255500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11603500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5399000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 17002500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11603500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5399000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 17002500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 12139500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2343500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14483000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3454500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3454500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 12139500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5798000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 17937500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 12139500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5798000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 17937500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993127 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.981481 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.991304 # mshr miss rate for ReadReq accesses @@ -402,17 +402,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.992958 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993127 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.992593 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.992958 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40150.519031 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40443.396226 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40195.906433 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40191.358025 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40191.358025 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40150.519031 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40291.044776 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40195.035461 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40150.519031 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40291.044776 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40195.035461 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 42005.190311 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 44216.981132 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 42347.953216 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42648.148148 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42648.148148 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42005.190311 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 43268.656716 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42405.437352 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42005.190311 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 43268.656716 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42405.437352 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/config.ini b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/config.ini index 232d3350e..53f402a63 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/config.ini +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/config.ini @@ -148,7 +148,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side @@ -180,7 +180,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.physmem.port[0] slave=system.system_port system.cpu.l2cache.mem_side diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/simout b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/simout index e4af58bc7..81bff15c4 100755 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/simout +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 12:01:47 -gem5 started Jun 4 2012 14:44:42 +gem5 compiled Jul 2 2012 08:54:18 +gem5 started Jul 2 2012 11:30:26 gem5 executing on zizzer -command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing +command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/quick/se/00.hello/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/fast/quick/se/00.hello/sparc/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... -Hello World!Exiting @ tick 28206000 because target called exit() +Hello World!Exiting @ tick 29541000 because target called exit() diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt index 3580b75db..d0e2c9d97 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000028 # Number of seconds simulated -sim_ticks 28206000 # Number of ticks simulated -final_tick 28206000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000030 # Number of seconds simulated +sim_ticks 29541000 # Number of ticks simulated +final_tick 29541000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 427855 # Simulator instruction rate (inst/s) -host_op_rate 427237 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2253599179 # Simulator tick rate (ticks/s) -host_mem_usage 221156 # Number of bytes of host memory used -host_seconds 0.01 # Real time elapsed on the host +host_inst_rate 73924 # Simulator instruction rate (inst/s) +host_op_rate 73907 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 408761366 # Simulator tick rate (ticks/s) +host_mem_usage 220016 # Number of bytes of host memory used +host_seconds 0.07 # Real time elapsed on the host sim_insts 5340 # Number of instructions simulated sim_ops 5340 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 16320 # Number of bytes read from this memory @@ -19,16 +19,16 @@ system.physmem.bytes_inst_read::total 16320 # Nu system.physmem.num_reads::cpu.inst 255 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 134 # Number of read requests responded to by this memory system.physmem.num_reads::total 389 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 578600298 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 304048784 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 882649082 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 578600298 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 578600298 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 578600298 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 304048784 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 882649082 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 552452524 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 290308385 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 842760909 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 552452524 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 552452524 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 552452524 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 290308385 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 842760909 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 11 # Number of system calls -system.cpu.numCycles 56412 # number of cpu cycles simulated +system.cpu.numCycles 59082 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 5340 # Number of instructions committed @@ -47,18 +47,18 @@ system.cpu.num_mem_refs 1402 # nu system.cpu.num_load_insts 724 # Number of load instructions system.cpu.num_store_insts 678 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 56412 # Number of busy cycles +system.cpu.num_busy_cycles 59082 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 116.975932 # Cycle average of tags in use +system.cpu.icache.tagsinuse 117.079183 # Cycle average of tags in use system.cpu.icache.total_refs 5127 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 257 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 19.949416 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 116.975932 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.057117 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.057117 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::cpu.inst 117.079183 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.057168 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.057168 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 5127 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 5127 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 5127 # number of demand (read+write) hits @@ -129,14 +129,14 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52673.151751 system.cpu.icache.overall_avg_mshr_miss_latency::total 52673.151751 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 82.065697 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 82.107175 # Cycle average of tags in use system.cpu.dcache.total_refs 1254 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 135 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 9.288889 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 82.065697 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.020036 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.020036 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::cpu.data 82.107175 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.020046 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.020046 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 662 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 662 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 592 # number of WriteReq hits @@ -227,16 +227,16 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52688.888889 system.cpu.dcache.overall_avg_mshr_miss_latency::total 52688.888889 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 142.102892 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 142.223187 # Cycle average of tags in use system.cpu.l2cache.total_refs 3 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 308 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.009740 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 116.450335 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 25.652557 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.003554 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.000783 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.004337 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 116.548564 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 25.674623 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.003557 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.000784 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.004340 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 1 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 3 # number of ReadReq hits diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/config.ini index f4e4acba8..73bd70079 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/config.ini +++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/config.ini @@ -500,7 +500,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port @@ -532,7 +532,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.physmem.port[0] system.cpu.interrupts.pio system.cpu.interrupts.int_slave slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simout index 19d634444..3bef840f7 100755 --- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simout +++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simout @@ -1,11 +1,11 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 13:44:28 -gem5 started Jun 4 2012 15:03:58 +gem5 compiled Jul 2 2012 08:58:39 +gem5 started Jul 2 2012 12:38:36 gem5 executing on zizzer -command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/se/00.hello/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/quick/se/00.hello/x86/linux/o3-timing +command line: build/X86/gem5.fast -d build/X86/tests/fast/quick/se/00.hello/x86/linux/o3-timing -re tests/run.py build/X86/tests/fast/quick/se/00.hello/x86/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 12198000 because target called exit() +Exiting @ tick 12803000 because target called exit() diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt index b16a10afa..d0e4f2a16 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt @@ -1,272 +1,272 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000012 # Number of seconds simulated -sim_ticks 12198000 # Number of ticks simulated -final_tick 12198000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000013 # Number of seconds simulated +sim_ticks 12803000 # Number of ticks simulated +final_tick 12803000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 39950 # Simulator instruction rate (inst/s) -host_op_rate 72345 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 89952499 # Simulator tick rate (ticks/s) -host_mem_usage 224288 # Number of bytes of host memory used -host_seconds 0.14 # Real time elapsed on the host +host_inst_rate 24032 # Simulator instruction rate (inst/s) +host_op_rate 43521 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 56800152 # Simulator tick rate (ticks/s) +host_mem_usage 227452 # Number of bytes of host memory used +host_seconds 0.23 # Real time elapsed on the host sim_insts 5416 # Number of instructions simulated sim_ops 9809 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 19328 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9536 # Number of bytes read from this memory -system.physmem.bytes_read::total 28864 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 19328 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 19328 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 302 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 149 # Number of read requests responded to by this memory -system.physmem.num_reads::total 451 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1584522053 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 781767503 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2366289556 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1584522053 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1584522053 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1584522053 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 781767503 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2366289556 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 19264 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9280 # Number of bytes read from this memory +system.physmem.bytes_read::total 28544 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 19264 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 19264 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 301 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 145 # Number of read requests responded to by this memory +system.physmem.num_reads::total 446 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1504647348 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 724830118 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2229477466 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1504647348 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1504647348 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1504647348 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 724830118 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2229477466 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 11 # Number of system calls -system.cpu.numCycles 24397 # number of cpu cycles simulated +system.cpu.numCycles 25607 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 3206 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 3206 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 560 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 2627 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 792 # Number of BTB hits +system.cpu.BPredUnit.lookups 3125 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 3125 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 558 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 2605 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 830 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 7375 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 15410 # Number of instructions fetch has processed -system.cpu.fetch.Branches 3206 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 792 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 4170 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 2487 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 3163 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 16 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 98 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 1951 # Number of cache lines fetched +system.cpu.fetch.icacheStallCycles 8034 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 14981 # Number of instructions fetch has processed +system.cpu.fetch.Branches 3125 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 830 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 4070 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 2483 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 3408 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 41 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 244 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 1957 # Number of cache lines fetched system.cpu.fetch.IcacheSquashes 281 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 16727 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.635918 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.075272 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::samples 17679 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.502687 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.975668 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 12659 75.68% 75.68% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 177 1.06% 76.74% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 166 0.99% 77.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 214 1.28% 79.01% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 171 1.02% 80.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 175 1.05% 81.08% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 250 1.49% 82.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 166 0.99% 83.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 2749 16.43% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 13710 77.55% 77.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 177 1.00% 78.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 164 0.93% 79.48% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 211 1.19% 80.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 170 0.96% 81.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 182 1.03% 82.66% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 260 1.47% 84.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 162 0.92% 85.05% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 2643 14.95% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 16727 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.131410 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.631635 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 7836 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 3109 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 3749 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 128 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1905 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 26025 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 1905 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 8180 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 1960 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 442 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 3522 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 718 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 24463 # Number of instructions processed by rename +system.cpu.fetch.rateDist::total 17679 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.122037 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.585035 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 8588 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 3390 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 3692 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 127 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1882 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 25327 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 1882 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 8910 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 2031 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 505 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 3461 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 890 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 23802 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 3 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 50 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 591 # Number of times rename has blocked due to LSQ full +system.cpu.rename.IQFullEvents 47 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 747 # Number of times rename has blocked due to LSQ full system.cpu.rename.FullRegisterEvents 1 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 35223 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 70488 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 70472 # Number of integer rename lookups +system.cpu.rename.RenamedOperands 34224 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 68607 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 68591 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 16 # Number of floating rename lookups system.cpu.rename.CommittedMaps 14707 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 20516 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 33 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 33 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 1918 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2376 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1791 # Number of stores inserted to the mem dependence unit. +system.cpu.rename.UndoneMaps 19517 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 35 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 35 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 1875 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2306 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1775 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 11 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 4 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 21692 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 38 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 17854 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 82 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 11255 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 20549 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 25 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 16727 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.067376 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.893384 # Number of insts issued each cycle +system.cpu.iq.iqInstsAdded 21232 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 40 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 17582 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 92 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 10865 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 19620 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 27 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 17679 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.994513 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.826049 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 11276 67.41% 67.41% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1383 8.27% 75.68% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 1035 6.19% 81.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 667 3.99% 85.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 692 4.14% 89.99% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 723 4.32% 94.31% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 673 4.02% 98.34% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 245 1.46% 99.80% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 33 0.20% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 12114 68.52% 68.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1582 8.95% 77.47% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 1012 5.72% 83.19% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 689 3.90% 87.09% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 696 3.94% 91.03% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 692 3.91% 94.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 627 3.55% 98.49% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 233 1.32% 99.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 34 0.19% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 16727 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 17679 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 140 73.30% 73.30% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 73.30% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 73.30% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 73.30% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 73.30% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 73.30% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 73.30% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 73.30% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 73.30% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 73.30% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 73.30% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 73.30% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 73.30% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 73.30% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 73.30% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 73.30% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 73.30% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 73.30% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 73.30% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 73.30% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 73.30% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 73.30% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 73.30% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 73.30% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 73.30% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 73.30% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 73.30% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 73.30% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 73.30% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 30 15.71% 89.01% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 21 10.99% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 133 73.08% 73.08% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 73.08% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 73.08% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 73.08% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 73.08% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 73.08% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 73.08% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 73.08% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 73.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 73.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 73.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 73.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 73.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 73.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 73.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 73.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 73.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 73.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 73.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 73.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 73.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 73.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 73.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 73.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 73.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 73.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 73.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 73.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 73.08% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 29 15.93% 89.01% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 20 10.99% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 4 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 14397 80.64% 80.66% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 80.66% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 80.66% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 80.66% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 80.66% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 80.66% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 80.66% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 80.66% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 80.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 80.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 80.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 80.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 80.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 80.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 80.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 80.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 80.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 80.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 80.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 80.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 80.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 80.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 80.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 80.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 80.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 80.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 80.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 80.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 80.66% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 1982 11.10% 91.76% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1471 8.24% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 14185 80.68% 80.70% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 80.70% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 80.70% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 80.70% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 80.70% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 80.70% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 80.70% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 80.70% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 80.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 80.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 80.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 80.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 80.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 80.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 80.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 80.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 80.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 80.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 80.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 80.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 80.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 80.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 80.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 80.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 80.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 80.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 80.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 80.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 80.70% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 1924 10.94% 91.64% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1469 8.36% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 17854 # Type of FU issued -system.cpu.iq.rate 0.731811 # Inst issue rate -system.cpu.iq.fu_busy_cnt 191 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.010698 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 52700 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 32991 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 16402 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 17582 # Type of FU issued +system.cpu.iq.rate 0.686609 # Inst issue rate +system.cpu.iq.fu_busy_cnt 182 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.010351 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 53109 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 32144 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 16183 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 8 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 4 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 4 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 18037 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 17756 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 4 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 151 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 148 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1320 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 20 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.squashedLoads 1250 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 14 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 11 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 857 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 841 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1905 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1329 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 39 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 21730 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 24 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2376 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1791 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 34 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 10 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 1882 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1425 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 33 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 21272 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 46 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2306 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1775 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 36 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 4 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 11 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 59 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 631 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 690 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 16824 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 1844 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1030 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedTakenIncorrect 65 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 640 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 705 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 16602 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 1794 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 980 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 3203 # number of memory reference insts executed -system.cpu.iew.exec_branches 1645 # Number of branches executed -system.cpu.iew.exec_stores 1359 # Number of stores executed -system.cpu.iew.exec_rate 0.689593 # Inst execution rate -system.cpu.iew.wb_sent 16593 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 16406 # cumulative count of insts written-back -system.cpu.iew.wb_producers 10679 # num instructions producing a value -system.cpu.iew.wb_consumers 24448 # num instructions consuming a value +system.cpu.iew.exec_refs 3144 # number of memory reference insts executed +system.cpu.iew.exec_branches 1642 # Number of branches executed +system.cpu.iew.exec_stores 1350 # Number of stores executed +system.cpu.iew.exec_rate 0.648338 # Inst execution rate +system.cpu.iew.wb_sent 16384 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 16187 # cumulative count of insts written-back +system.cpu.iew.wb_producers 10480 # num instructions producing a value +system.cpu.iew.wb_consumers 24095 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.672460 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.436805 # average fanout of values written-back +system.cpu.iew.wb_rate 0.632132 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.434945 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 5416 # The number of committed instructions system.cpu.commit.commitCommittedOps 9809 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 11920 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 11462 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 13 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 571 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 14822 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.661787 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.507902 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 589 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 15797 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.620941 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.463366 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 11181 75.44% 75.44% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1365 9.21% 84.64% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 653 4.41% 89.05% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 730 4.93% 93.98% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 365 2.46% 96.44% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 129 0.87% 97.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 139 0.94% 98.25% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 71 0.48% 98.72% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 189 1.28% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 12065 76.38% 76.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1534 9.71% 86.09% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 576 3.65% 89.73% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 731 4.63% 94.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 367 2.32% 96.68% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 129 0.82% 97.50% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 134 0.85% 98.35% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 75 0.47% 98.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 186 1.18% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 14822 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 15797 # Number of insts commited each cycle system.cpu.commit.committedInsts 5416 # Number of instructions committed system.cpu.commit.committedOps 9809 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -277,68 +277,68 @@ system.cpu.commit.branches 1214 # Nu system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. system.cpu.commit.int_insts 9714 # Number of committed integer instructions. system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 189 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 186 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 36362 # The number of ROB reads -system.cpu.rob.rob_writes 45397 # The number of ROB writes -system.cpu.timesIdled 150 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 7670 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 36882 # The number of ROB reads +system.cpu.rob.rob_writes 44457 # The number of ROB writes +system.cpu.timesIdled 153 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 7928 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 5416 # Number of Instructions Simulated system.cpu.committedOps 9809 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 5416 # Number of Instructions Simulated -system.cpu.cpi 4.504616 # CPI: Cycles Per Instruction -system.cpu.cpi_total 4.504616 # CPI: Total CPI of All Threads -system.cpu.ipc 0.221995 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.221995 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 35460 # number of integer regfile reads -system.cpu.int_regfile_writes 22063 # number of integer regfile writes +system.cpu.cpi 4.728028 # CPI: Cycles Per Instruction +system.cpu.cpi_total 4.728028 # CPI: Total CPI of All Threads +system.cpu.ipc 0.211505 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.211505 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 35136 # number of integer regfile reads +system.cpu.int_regfile_writes 21832 # number of integer regfile writes system.cpu.fp_regfile_reads 4 # number of floating regfile reads -system.cpu.misc_regfile_reads 7402 # number of misc regfile reads +system.cpu.misc_regfile_reads 7303 # number of misc regfile reads system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 145.636183 # Cycle average of tags in use -system.cpu.icache.total_refs 1561 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 304 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 5.134868 # Average number of references to valid blocks. +system.cpu.icache.tagsinuse 144.987593 # Cycle average of tags in use +system.cpu.icache.total_refs 1569 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 302 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 5.195364 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 145.636183 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.071111 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.071111 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 1561 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1561 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1561 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1561 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1561 # number of overall hits -system.cpu.icache.overall_hits::total 1561 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 390 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 390 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 390 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 390 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 390 # number of overall misses -system.cpu.icache.overall_misses::total 390 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 13866500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 13866500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 13866500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 13866500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 13866500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 13866500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1951 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1951 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1951 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1951 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1951 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1951 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.199897 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.199897 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.199897 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.199897 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.199897 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.199897 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35555.128205 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 35555.128205 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 35555.128205 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 35555.128205 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 35555.128205 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 35555.128205 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 144.987593 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.070795 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.070795 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 1569 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1569 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1569 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1569 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1569 # number of overall hits +system.cpu.icache.overall_hits::total 1569 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 388 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 388 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 388 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 388 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 388 # number of overall misses +system.cpu.icache.overall_misses::total 388 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 14367500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 14367500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 14367500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 14367500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 14367500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 14367500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1957 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1957 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1957 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1957 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1957 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1957 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.198263 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.198263 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.198263 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.198263 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.198263 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.198263 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 37029.639175 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 37029.639175 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 37029.639175 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 37029.639175 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 37029.639175 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 37029.639175 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -353,88 +353,88 @@ system.cpu.icache.demand_mshr_hits::cpu.inst 86 system.cpu.icache.demand_mshr_hits::total 86 # number of demand (read+write) MSHR hits system.cpu.icache.overall_mshr_hits::cpu.inst 86 # number of overall MSHR hits system.cpu.icache.overall_mshr_hits::total 86 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 304 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 304 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 304 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 304 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 304 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 304 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 10687000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 10687000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 10687000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 10687000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 10687000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 10687000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.155818 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.155818 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.155818 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.155818 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.155818 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.155818 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35154.605263 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 35154.605263 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35154.605263 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 35154.605263 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35154.605263 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 35154.605263 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 302 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 302 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 302 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 302 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 302 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 302 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11138000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 11138000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11138000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 11138000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11138000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 11138000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.154318 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.154318 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.154318 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.154318 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.154318 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.154318 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36880.794702 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 36880.794702 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36880.794702 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 36880.794702 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36880.794702 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 36880.794702 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 84.751522 # Cycle average of tags in use -system.cpu.dcache.total_refs 2365 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 148 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 15.979730 # Average number of references to valid blocks. +system.cpu.dcache.tagsinuse 83.196834 # Cycle average of tags in use +system.cpu.dcache.total_refs 2330 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 144 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 16.180556 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 84.751522 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.020691 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.020691 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 1507 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1507 # number of ReadReq hits +system.cpu.dcache.occ_blocks::cpu.data 83.196834 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.020312 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.020312 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 1472 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1472 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 858 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 858 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 2365 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2365 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2365 # number of overall hits -system.cpu.dcache.overall_hits::total 2365 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 115 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 115 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 2330 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2330 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2330 # number of overall hits +system.cpu.dcache.overall_hits::total 2330 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 112 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 112 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 76 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 76 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 191 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 191 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 191 # number of overall misses -system.cpu.dcache.overall_misses::total 191 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 4030500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 4030500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 2917500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 2917500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 6948000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 6948000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 6948000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 6948000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1622 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1622 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 188 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 188 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 188 # number of overall misses +system.cpu.dcache.overall_misses::total 188 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 4401500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 4401500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 3078500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 3078500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 7480000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 7480000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 7480000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 7480000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1584 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1584 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 934 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 934 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2556 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2556 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2556 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2556 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.070900 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.070900 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 2518 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2518 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2518 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2518 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.070707 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.070707 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.081370 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.081370 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.074726 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.074726 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.074726 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.074726 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 35047.826087 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 35047.826087 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38388.157895 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 38388.157895 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 36376.963351 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 36376.963351 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 36376.963351 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 36376.963351 # average overall miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.074662 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.074662 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.074662 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.074662 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 39299.107143 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 39299.107143 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 40506.578947 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 40506.578947 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 39787.234043 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 39787.234043 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 39787.234043 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 39787.234043 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -443,117 +443,117 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 42 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 42 # number of ReadReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 42 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 42 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 42 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 42 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 73 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 73 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 43 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 43 # number of ReadReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 43 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 43 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 43 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 43 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 69 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 69 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 76 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 76 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 149 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 149 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 149 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 149 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2574000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2574000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2689500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2689500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5263500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 5263500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5263500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 5263500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.045006 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.045006 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_misses::cpu.data 145 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 145 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 145 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 145 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2699500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2699500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2850500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2850500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5550000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 5550000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5550000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 5550000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.043561 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.043561 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.081370 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.081370 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.058294 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.058294 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.058294 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.058294 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 35260.273973 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 35260.273973 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35388.157895 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35388.157895 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 35325.503356 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 35325.503356 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 35325.503356 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 35325.503356 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.057585 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.057585 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.057585 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.057585 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 39123.188406 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 39123.188406 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 37506.578947 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 37506.578947 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 38275.862069 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 38275.862069 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 38275.862069 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 38275.862069 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 179.622577 # Cycle average of tags in use -system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 374 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.005348 # Average number of references to valid blocks. +system.cpu.l2cache.tagsinuse 177.887385 # Cycle average of tags in use +system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 369 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.002710 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 145.234150 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 34.388427 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.004432 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.001049 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.005482 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits -system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 2 # number of overall hits -system.cpu.l2cache.overall_hits::total 2 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 302 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 73 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 375 # number of ReadReq misses +system.cpu.l2cache.occ_blocks::cpu.inst 144.949907 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 32.937478 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.004424 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.001005 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.005429 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits +system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 1 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits +system.cpu.l2cache.overall_hits::total 1 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 301 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 69 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 370 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 76 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 76 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 302 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 149 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 451 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 302 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 149 # number of overall misses -system.cpu.l2cache.overall_misses::total 451 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 10368000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2486500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 12854500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2603000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 2603000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 10368000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 5089500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 15457500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 10368000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 5089500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 15457500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 304 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 73 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 377 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.demand_misses::cpu.inst 301 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 145 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 446 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 301 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 145 # number of overall misses +system.cpu.l2cache.overall_misses::total 446 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 10831500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2627000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 13458500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2772000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 2772000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 10831500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 5399000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 16230500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 10831500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 5399000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 16230500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 302 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 69 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 371 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 76 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 76 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 304 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 149 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 453 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 304 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 149 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 453 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.993421 # miss rate for ReadReq accesses +system.cpu.l2cache.demand_accesses::cpu.inst 302 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 145 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 447 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 302 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 145 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 447 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996689 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.994695 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.997305 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.993421 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996689 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.995585 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993421 # miss rate for overall accesses +system.cpu.l2cache.demand_miss_rate::total 0.997763 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996689 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.995585 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34331.125828 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34061.643836 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 34278.666667 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34250 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34250 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34331.125828 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34157.718121 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 34273.835920 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34331.125828 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34157.718121 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 34273.835920 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::total 0.997763 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35985.049834 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 38072.463768 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 36374.324324 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 36473.684211 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 36473.684211 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35985.049834 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 37234.482759 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 36391.255605 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35985.049834 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 37234.482759 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 36391.255605 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -562,50 +562,50 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 302 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 73 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 375 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 301 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 69 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 370 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 76 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 76 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 302 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 149 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 451 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 302 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 149 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 451 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 9394000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2263500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 11657500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2369500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2369500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 9394000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4633000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 14027000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 9394000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4633000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 14027000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993421 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 301 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 145 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 446 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 301 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 145 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 446 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 9877000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2416500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 12293500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2541500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2541500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 9877000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4958000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 14835000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 9877000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4958000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 14835000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996689 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.994695 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997305 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.993421 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996689 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.995585 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993421 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.997763 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996689 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.995585 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31105.960265 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31006.849315 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31086.666667 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31177.631579 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31177.631579 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31105.960265 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31093.959732 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31101.995565 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31105.960265 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31093.959732 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31101.995565 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.997763 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32813.953488 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 35021.739130 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 33225.675676 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 33440.789474 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 33440.789474 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32813.953488 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 34193.103448 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 33262.331839 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32813.953488 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 34193.103448 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 33262.331839 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/config.ini b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/config.ini index 3ced8b832..75df56c4d 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/config.ini +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/config.ini @@ -169,7 +169,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port @@ -201,7 +201,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.physmem.port[0] system.cpu.interrupts.pio system.cpu.interrupts.int_slave slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/simout b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/simout index 62a044b81..c1b9925b1 100755 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/simout +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/simout @@ -1,11 +1,11 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 13:44:28 -gem5 started Jun 4 2012 15:04:19 +gem5 compiled Jul 2 2012 08:58:39 +gem5 started Jul 2 2012 12:38:59 gem5 executing on zizzer -command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing -re tests/run.py build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing +command line: build/X86/gem5.fast -d build/X86/tests/fast/quick/se/00.hello/x86/linux/simple-timing -re tests/run.py build/X86/tests/fast/quick/se/00.hello/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 28768000 because target called exit() +Exiting @ tick 29726000 because target called exit() diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt index 1e89d36d4..4b1ad61d2 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000029 # Number of seconds simulated -sim_ticks 28768000 # Number of ticks simulated -final_tick 28768000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000030 # Number of seconds simulated +sim_ticks 29726000 # Number of ticks simulated +final_tick 29726000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 318234 # Simulator instruction rate (inst/s) -host_op_rate 575684 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1686451163 # Simulator tick rate (ticks/s) -host_mem_usage 223048 # Number of bytes of host memory used -host_seconds 0.02 # Real time elapsed on the host +host_inst_rate 107097 # Simulator instruction rate (inst/s) +host_op_rate 193883 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 587308683 # Simulator tick rate (ticks/s) +host_mem_usage 226300 # Number of bytes of host memory used +host_seconds 0.05 # Real time elapsed on the host sim_insts 5417 # Number of instructions simulated sim_ops 9810 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 14528 # Number of bytes read from this memory @@ -19,16 +19,16 @@ system.physmem.bytes_inst_read::total 14528 # Nu system.physmem.num_reads::cpu.inst 227 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 134 # Number of read requests responded to by this memory system.physmem.num_reads::total 361 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 505005562 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 298109010 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 803114572 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 505005562 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 505005562 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 505005562 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 298109010 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 803114572 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 488730404 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 288501648 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 777232053 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 488730404 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 488730404 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 488730404 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 288501648 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 777232053 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 11 # Number of system calls -system.cpu.numCycles 57536 # number of cpu cycles simulated +system.cpu.numCycles 59452 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 5417 # Number of instructions committed @@ -47,18 +47,18 @@ system.cpu.num_mem_refs 1990 # nu system.cpu.num_load_insts 1056 # Number of load instructions system.cpu.num_store_insts 934 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 57536 # Number of busy cycles +system.cpu.num_busy_cycles 59452 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 105.363985 # Cycle average of tags in use +system.cpu.icache.tagsinuse 105.590396 # Cycle average of tags in use system.cpu.icache.total_refs 6683 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 228 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 29.311404 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 105.363985 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.051447 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.051447 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::cpu.inst 105.590396 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.051558 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.051558 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 6683 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 6683 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 6683 # number of demand (read+write) hits @@ -129,14 +129,14 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52815.789474 system.cpu.icache.overall_avg_mshr_miss_latency::total 52815.789474 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 80.668870 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 80.767478 # Cycle average of tags in use system.cpu.dcache.total_refs 1856 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 134 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 13.850746 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 80.668870 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.019695 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.019695 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::cpu.data 80.767478 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.019719 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.019719 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 1001 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1001 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 855 # number of WriteReq hits @@ -227,16 +227,16 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 133.809342 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 134.079161 # Cycle average of tags in use system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 282 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.003546 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 105.370729 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 28.438613 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.003216 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.000868 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.004084 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 105.593760 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 28.485401 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.003222 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.000869 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.004092 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits diff --git a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini index 01d2e4278..856b4f64d 100644 --- a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini +++ b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini @@ -479,7 +479,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side @@ -530,7 +530,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.physmem.port[0] slave=system.system_port system.cpu.l2cache.mem_side diff --git a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout index 8da405b24..94c9ff95a 100755 --- a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout +++ b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout @@ -1,8 +1,8 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 28 2012 22:05:18 -gem5 started Jun 28 2012 22:09:52 +gem5 compiled Jul 2 2012 08:30:56 +gem5 started Jul 2 2012 09:08:40 gem5 executing on zizzer command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/quick/se/01.hello-2T-smt/alpha/linux/o3-timing -re tests/run.py build/ALPHA/tests/fast/quick/se/01.hello-2T-smt/alpha/linux/o3-timing Global frequency set at 1000000000000 ticks per second @@ -11,4 +11,4 @@ info: Increasing stack size by one page. info: Increasing stack size by one page. Hello world! Hello world! -Exiting @ tick 13801000 because target called exit() +Exiting @ tick 15041500 because target called exit() diff --git a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt index 3bebb79ad..a5109fa39 100644 --- a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt +++ b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt @@ -1,52 +1,52 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000014 # Number of seconds simulated -sim_ticks 13801000 # Number of ticks simulated -final_tick 13801000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000015 # Number of seconds simulated +sim_ticks 15041500 # Number of ticks simulated +final_tick 15041500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 32086 # Simulator instruction rate (inst/s) -host_op_rate 32085 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 34665771 # Simulator tick rate (ticks/s) -host_mem_usage 218816 # Number of bytes of host memory used -host_seconds 0.40 # Real time elapsed on the host +host_inst_rate 102152 # Simulator instruction rate (inst/s) +host_op_rate 102138 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 120262580 # Simulator tick rate (ticks/s) +host_mem_usage 219804 # Number of bytes of host memory used +host_seconds 0.13 # Real time elapsed on the host sim_insts 12773 # Number of instructions simulated sim_ops 12773 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 40000 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 22720 # Number of bytes read from this memory -system.physmem.bytes_read::total 62720 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 40000 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 40000 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 625 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 355 # Number of read requests responded to by this memory -system.physmem.num_reads::total 980 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 2898340700 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1646257518 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4544598218 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 2898340700 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 2898340700 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 2898340700 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1646257518 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4544598218 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 39936 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 22400 # Number of bytes read from this memory +system.physmem.bytes_read::total 62336 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 39936 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 39936 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 624 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 350 # Number of read requests responded to by this memory +system.physmem.num_reads::total 974 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 2655054350 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1489213177 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4144267527 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 2655054350 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 2655054350 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 2655054350 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1489213177 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4144267527 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 4109 # DTB read hits -system.cpu.dtb.read_misses 91 # DTB read misses +system.cpu.dtb.read_hits 4063 # DTB read hits +system.cpu.dtb.read_misses 99 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 4200 # DTB read accesses -system.cpu.dtb.write_hits 2070 # DTB write hits -system.cpu.dtb.write_misses 61 # DTB write misses +system.cpu.dtb.read_accesses 4162 # DTB read accesses +system.cpu.dtb.write_hits 2079 # DTB write hits +system.cpu.dtb.write_misses 66 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 2131 # DTB write accesses -system.cpu.dtb.data_hits 6179 # DTB hits -system.cpu.dtb.data_misses 152 # DTB misses +system.cpu.dtb.write_accesses 2145 # DTB write accesses +system.cpu.dtb.data_hits 6142 # DTB hits +system.cpu.dtb.data_misses 165 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 6331 # DTB accesses -system.cpu.itb.fetch_hits 5033 # ITB hits -system.cpu.itb.fetch_misses 52 # ITB misses +system.cpu.dtb.data_accesses 6307 # DTB accesses +system.cpu.itb.fetch_hits 4998 # ITB hits +system.cpu.itb.fetch_misses 64 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 5085 # ITB accesses +system.cpu.itb.fetch_accesses 5062 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -61,360 +61,361 @@ system.cpu.itb.data_acv 0 # DT system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload0.num_syscalls 17 # Number of system calls system.cpu.workload1.num_syscalls 17 # Number of system calls -system.cpu.numCycles 27603 # number of cpu cycles simulated +system.cpu.numCycles 30084 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 6273 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 3546 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 1676 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 4641 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 749 # Number of BTB hits +system.cpu.BPredUnit.lookups 6210 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 3535 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 1700 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 4700 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 759 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 905 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 178 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 1498 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 35104 # Number of instructions fetch has processed -system.cpu.fetch.Branches 6273 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 1654 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 5870 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1752 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 45 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.CacheLines 5033 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 742 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 21582 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.626541 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.950246 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 825 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 175 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 1535 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 34626 # Number of instructions fetch has processed +system.cpu.fetch.Branches 6210 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 1584 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 5789 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1776 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 48 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.CacheLines 4998 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 745 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 24259 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.427347 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.816880 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 15712 72.80% 72.80% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 465 2.15% 74.96% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 353 1.64% 76.59% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 445 2.06% 78.65% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 412 1.91% 80.56% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 367 1.70% 82.26% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 466 2.16% 84.42% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 577 2.67% 87.10% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 2785 12.90% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 18470 76.14% 76.14% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 464 1.91% 78.05% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 348 1.43% 79.48% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 447 1.84% 81.33% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 403 1.66% 82.99% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 343 1.41% 84.40% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 469 1.93% 86.33% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 536 2.21% 88.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 2779 11.46% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 21582 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.227258 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.271746 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 29958 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 5047 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 5024 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 472 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 2407 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 618 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 398 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 30693 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 650 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 2407 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 30628 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 2400 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 805 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 4751 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 1917 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 28414 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 8 # Number of times rename has blocked due to ROB full -system.cpu.rename.LSQFullEvents 1949 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 21384 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 35492 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 35458 # Number of integer rename lookups +system.cpu.fetch.rateDist::total 24259 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.206422 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.150977 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 34703 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 5701 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 4994 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 517 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 2387 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 655 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 440 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 30483 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 727 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 2387 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 35405 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 2859 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 908 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 4714 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 2029 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 28166 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 11 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 2057 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 21169 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 35183 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 35149 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 34 # Number of floating rename lookups system.cpu.rename.CommittedMaps 9166 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 12218 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 55 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 43 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 5512 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2647 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1284 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 3 # Number of conflicting loads. +system.cpu.rename.UndoneMaps 12003 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 54 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 42 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 5549 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2568 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1287 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 11 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. -system.cpu.memDep1.insertedLoads 2635 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep1.insertedStores 1309 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep1.conflictingLoads 14 # Number of conflicting loads. +system.cpu.memDep1.insertedLoads 2598 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep1.insertedStores 1301 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep1.conflictingLoads 17 # Number of conflicting loads. system.cpu.memDep1.conflictingStores 0 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 25261 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 50 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 21461 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 117 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 11327 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 6314 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 16 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 21582 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.994393 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.507504 # Number of insts issued each cycle +system.cpu.iq.iqInstsAdded 25020 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 51 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 21261 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 104 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 11085 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 6273 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 17 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 24259 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.876417 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.449361 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 12693 58.81% 58.81% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 3009 13.94% 72.76% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 2444 11.32% 84.08% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 1529 7.08% 91.16% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 1011 4.68% 95.85% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 561 2.60% 98.45% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 239 1.11% 99.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 74 0.34% 99.90% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 22 0.10% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 15324 63.17% 63.17% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 3188 13.14% 76.31% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 2404 9.91% 86.22% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 1484 6.12% 92.34% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 963 3.97% 96.31% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 553 2.28% 98.59% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 233 0.96% 99.55% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 82 0.34% 99.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 28 0.12% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 21582 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 24259 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 7 3.76% 3.76% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 3.76% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 3.76% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.76% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.76% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.76% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 3.76% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.76% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 3.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 3.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.76% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 115 61.83% 65.59% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 64 34.41% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 5 2.69% 2.69% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 2.69% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 2.69% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.69% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.69% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.69% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 2.69% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.69% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 2.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 2.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.69% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 116 62.37% 65.05% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 65 34.95% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 7347 68.12% 68.13% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 1 0.01% 68.14% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.14% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 68.16% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.16% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.16% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.16% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 68.16% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.16% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.16% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.16% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.16% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.16% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.16% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.16% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.16% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.16% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.16% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.16% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.16% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.16% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.16% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.16% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.16% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.16% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.16% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.16% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.16% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.16% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2315 21.46% 89.63% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1119 10.37% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 7259 68.24% 68.26% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 1 0.01% 68.27% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.27% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 68.29% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.29% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.29% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.29% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 68.29% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.29% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2247 21.12% 89.41% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1126 10.59% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 10786 # Type of FU issued +system.cpu.iq.FU_type_0::total 10637 # Type of FU issued system.cpu.iq.FU_type_1::No_OpClass 2 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type_1::IntAlu 7235 67.78% 67.79% # Type of FU issued -system.cpu.iq.FU_type_1::IntMult 1 0.01% 67.80% # Type of FU issued -system.cpu.iq.FU_type_1::IntDiv 0 0.00% 67.80% # Type of FU issued -system.cpu.iq.FU_type_1::FloatAdd 2 0.02% 67.82% # Type of FU issued -system.cpu.iq.FU_type_1::FloatCmp 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_1::FloatCvt 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_1::FloatMult 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_1::FloatDiv 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_1::FloatSqrt 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_1::SimdAdd 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_1::SimdAddAcc 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_1::SimdAlu 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_1::SimdCmp 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_1::SimdCvt 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_1::SimdMisc 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_1::SimdMult 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_1::SimdMultAcc 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_1::SimdShift 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_1::SimdShiftAcc 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_1::SimdSqrt 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatAdd 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatAlu 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatCmp 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatCvt 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatDiv 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatMisc 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatMult 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatMultAcc 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatSqrt 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_1::MemRead 2307 21.61% 89.43% # Type of FU issued -system.cpu.iq.FU_type_1::MemWrite 1128 10.57% 100.00% # Type of FU issued +system.cpu.iq.FU_type_1::IntAlu 7177 67.55% 67.57% # Type of FU issued +system.cpu.iq.FU_type_1::IntMult 1 0.01% 67.58% # Type of FU issued +system.cpu.iq.FU_type_1::IntDiv 0 0.00% 67.58% # Type of FU issued +system.cpu.iq.FU_type_1::FloatAdd 2 0.02% 67.60% # Type of FU issued +system.cpu.iq.FU_type_1::FloatCmp 0 0.00% 67.60% # Type of FU issued +system.cpu.iq.FU_type_1::FloatCvt 0 0.00% 67.60% # Type of FU issued +system.cpu.iq.FU_type_1::FloatMult 0 0.00% 67.60% # Type of FU issued +system.cpu.iq.FU_type_1::FloatDiv 0 0.00% 67.60% # Type of FU issued +system.cpu.iq.FU_type_1::FloatSqrt 0 0.00% 67.60% # Type of FU issued +system.cpu.iq.FU_type_1::SimdAdd 0 0.00% 67.60% # Type of FU issued +system.cpu.iq.FU_type_1::SimdAddAcc 0 0.00% 67.60% # Type of FU issued +system.cpu.iq.FU_type_1::SimdAlu 0 0.00% 67.60% # Type of FU issued +system.cpu.iq.FU_type_1::SimdCmp 0 0.00% 67.60% # Type of FU issued +system.cpu.iq.FU_type_1::SimdCvt 0 0.00% 67.60% # Type of FU issued +system.cpu.iq.FU_type_1::SimdMisc 0 0.00% 67.60% # Type of FU issued +system.cpu.iq.FU_type_1::SimdMult 0 0.00% 67.60% # Type of FU issued +system.cpu.iq.FU_type_1::SimdMultAcc 0 0.00% 67.60% # Type of FU issued +system.cpu.iq.FU_type_1::SimdShift 0 0.00% 67.60% # Type of FU issued +system.cpu.iq.FU_type_1::SimdShiftAcc 0 0.00% 67.60% # Type of FU issued +system.cpu.iq.FU_type_1::SimdSqrt 0 0.00% 67.60% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatAdd 0 0.00% 67.60% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatAlu 0 0.00% 67.60% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatCmp 0 0.00% 67.60% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatCvt 0 0.00% 67.60% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatDiv 0 0.00% 67.60% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatMisc 0 0.00% 67.60% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatMult 0 0.00% 67.60% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatMultAcc 0 0.00% 67.60% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatSqrt 0 0.00% 67.60% # Type of FU issued +system.cpu.iq.FU_type_1::MemRead 2282 21.48% 89.08% # Type of FU issued +system.cpu.iq.FU_type_1::MemWrite 1160 10.92% 100.00% # Type of FU issued system.cpu.iq.FU_type_1::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_1::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_1::total 10675 # Type of FU issued +system.cpu.iq.FU_type_1::total 10624 # Type of FU issued system.cpu.iq.FU_type::No_OpClass 4 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type::IntAlu 14582 67.95% 67.97% # Type of FU issued -system.cpu.iq.FU_type::IntMult 2 0.01% 67.97% # Type of FU issued -system.cpu.iq.FU_type::IntDiv 0 0.00% 67.97% # Type of FU issued -system.cpu.iq.FU_type::FloatAdd 4 0.02% 67.99% # Type of FU issued -system.cpu.iq.FU_type::FloatCmp 0 0.00% 67.99% # Type of FU issued -system.cpu.iq.FU_type::FloatCvt 0 0.00% 67.99% # Type of FU issued -system.cpu.iq.FU_type::FloatMult 0 0.00% 67.99% # Type of FU issued -system.cpu.iq.FU_type::FloatDiv 0 0.00% 67.99% # Type of FU issued -system.cpu.iq.FU_type::FloatSqrt 0 0.00% 67.99% # Type of FU issued -system.cpu.iq.FU_type::SimdAdd 0 0.00% 67.99% # Type of FU issued -system.cpu.iq.FU_type::SimdAddAcc 0 0.00% 67.99% # Type of FU issued -system.cpu.iq.FU_type::SimdAlu 0 0.00% 67.99% # Type of FU issued -system.cpu.iq.FU_type::SimdCmp 0 0.00% 67.99% # Type of FU issued -system.cpu.iq.FU_type::SimdCvt 0 0.00% 67.99% # Type of FU issued -system.cpu.iq.FU_type::SimdMisc 0 0.00% 67.99% # Type of FU issued -system.cpu.iq.FU_type::SimdMult 0 0.00% 67.99% # Type of FU issued -system.cpu.iq.FU_type::SimdMultAcc 0 0.00% 67.99% # Type of FU issued -system.cpu.iq.FU_type::SimdShift 0 0.00% 67.99% # Type of FU issued -system.cpu.iq.FU_type::SimdShiftAcc 0 0.00% 67.99% # Type of FU issued -system.cpu.iq.FU_type::SimdSqrt 0 0.00% 67.99% # Type of FU issued -system.cpu.iq.FU_type::SimdFloatAdd 0 0.00% 67.99% # Type of FU issued -system.cpu.iq.FU_type::SimdFloatAlu 0 0.00% 67.99% # Type of FU issued -system.cpu.iq.FU_type::SimdFloatCmp 0 0.00% 67.99% # Type of FU issued -system.cpu.iq.FU_type::SimdFloatCvt 0 0.00% 67.99% # Type of FU issued -system.cpu.iq.FU_type::SimdFloatDiv 0 0.00% 67.99% # Type of FU issued -system.cpu.iq.FU_type::SimdFloatMisc 0 0.00% 67.99% # Type of FU issued -system.cpu.iq.FU_type::SimdFloatMult 0 0.00% 67.99% # Type of FU issued -system.cpu.iq.FU_type::SimdFloatMultAcc 0 0.00% 67.99% # Type of FU issued -system.cpu.iq.FU_type::SimdFloatSqrt 0 0.00% 67.99% # Type of FU issued -system.cpu.iq.FU_type::MemRead 4622 21.54% 89.53% # Type of FU issued -system.cpu.iq.FU_type::MemWrite 2247 10.47% 100.00% # Type of FU issued +system.cpu.iq.FU_type::IntAlu 14436 67.90% 67.92% # Type of FU issued +system.cpu.iq.FU_type::IntMult 2 0.01% 67.93% # Type of FU issued +system.cpu.iq.FU_type::IntDiv 0 0.00% 67.93% # Type of FU issued +system.cpu.iq.FU_type::FloatAdd 4 0.02% 67.95% # Type of FU issued +system.cpu.iq.FU_type::FloatCmp 0 0.00% 67.95% # Type of FU issued +system.cpu.iq.FU_type::FloatCvt 0 0.00% 67.95% # Type of FU issued +system.cpu.iq.FU_type::FloatMult 0 0.00% 67.95% # Type of FU issued +system.cpu.iq.FU_type::FloatDiv 0 0.00% 67.95% # Type of FU issued +system.cpu.iq.FU_type::FloatSqrt 0 0.00% 67.95% # Type of FU issued +system.cpu.iq.FU_type::SimdAdd 0 0.00% 67.95% # Type of FU issued +system.cpu.iq.FU_type::SimdAddAcc 0 0.00% 67.95% # Type of FU issued +system.cpu.iq.FU_type::SimdAlu 0 0.00% 67.95% # Type of FU issued +system.cpu.iq.FU_type::SimdCmp 0 0.00% 67.95% # Type of FU issued +system.cpu.iq.FU_type::SimdCvt 0 0.00% 67.95% # Type of FU issued +system.cpu.iq.FU_type::SimdMisc 0 0.00% 67.95% # Type of FU issued +system.cpu.iq.FU_type::SimdMult 0 0.00% 67.95% # Type of FU issued +system.cpu.iq.FU_type::SimdMultAcc 0 0.00% 67.95% # Type of FU issued +system.cpu.iq.FU_type::SimdShift 0 0.00% 67.95% # Type of FU issued +system.cpu.iq.FU_type::SimdShiftAcc 0 0.00% 67.95% # Type of FU issued +system.cpu.iq.FU_type::SimdSqrt 0 0.00% 67.95% # Type of FU issued +system.cpu.iq.FU_type::SimdFloatAdd 0 0.00% 67.95% # Type of FU issued +system.cpu.iq.FU_type::SimdFloatAlu 0 0.00% 67.95% # Type of FU issued +system.cpu.iq.FU_type::SimdFloatCmp 0 0.00% 67.95% # Type of FU issued +system.cpu.iq.FU_type::SimdFloatCvt 0 0.00% 67.95% # Type of FU issued +system.cpu.iq.FU_type::SimdFloatDiv 0 0.00% 67.95% # Type of FU issued +system.cpu.iq.FU_type::SimdFloatMisc 0 0.00% 67.95% # Type of FU issued +system.cpu.iq.FU_type::SimdFloatMult 0 0.00% 67.95% # Type of FU issued +system.cpu.iq.FU_type::SimdFloatMultAcc 0 0.00% 67.95% # Type of FU issued +system.cpu.iq.FU_type::SimdFloatSqrt 0 0.00% 67.95% # Type of FU issued +system.cpu.iq.FU_type::MemRead 4529 21.30% 89.25% # Type of FU issued +system.cpu.iq.FU_type::MemWrite 2286 10.75% 100.00% # Type of FU issued system.cpu.iq.FU_type::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type::total 21461 # Type of FU issued -system.cpu.iq.rate 0.777488 # Inst issue rate -system.cpu.iq.fu_busy_cnt::0 93 # FU busy when requested -system.cpu.iq.fu_busy_cnt::1 93 # FU busy when requested +system.cpu.iq.FU_type::total 21261 # Type of FU issued +system.cpu.iq.rate 0.706721 # Inst issue rate +system.cpu.iq.fu_busy_cnt::0 86 # FU busy when requested +system.cpu.iq.fu_busy_cnt::1 100 # FU busy when requested system.cpu.iq.fu_busy_cnt::total 186 # FU busy when requested -system.cpu.iq.fu_busy_rate::0 0.004333 # FU busy rate (busy events/executed inst) -system.cpu.iq.fu_busy_rate::1 0.004333 # FU busy rate (busy events/executed inst) -system.cpu.iq.fu_busy_rate::total 0.008667 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 64765 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 36642 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 19216 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fu_busy_rate::0 0.004045 # FU busy rate (busy events/executed inst) +system.cpu.iq.fu_busy_rate::1 0.004703 # FU busy rate (busy events/executed inst) +system.cpu.iq.fu_busy_rate::total 0.008748 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 67029 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 36163 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 19051 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 42 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 20 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 20 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 21621 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 21421 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 22 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 55 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 47 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1462 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 4 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 16 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 419 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 1383 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 14 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 422 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread1.forwLoads 61 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread1.forwLoads 65 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread1.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread1.squashedLoads 1450 # Number of loads squashed -system.cpu.iew.lsq.thread1.ignoredResponses 1 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread1.memOrderViolation 17 # Number of memory ordering violations -system.cpu.iew.lsq.thread1.squashedStores 444 # Number of stores squashed +system.cpu.iew.lsq.thread1.squashedLoads 1413 # Number of loads squashed +system.cpu.iew.lsq.thread1.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread1.memOrderViolation 16 # Number of memory ordering violations +system.cpu.iew.lsq.thread1.squashedStores 436 # Number of stores squashed system.cpu.iew.lsq.thread1.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread1.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread1.rescheduledLoads 1 # Number of loads that were rescheduled system.cpu.iew.lsq.thread1.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 2407 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 503 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 41 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 25446 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 693 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 5282 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 2593 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 50 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 33 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 2 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 33 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 259 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 1247 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1506 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 20047 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts::0 2108 # Number of load instructions executed -system.cpu.iew.iewExecLoadInsts::1 2105 # Number of load instructions executed -system.cpu.iew.iewExecLoadInsts::total 4213 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1414 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 2387 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 608 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 48 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 25214 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 623 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 5166 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 2588 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 51 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 40 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 1 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 30 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 252 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 1229 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1481 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 19905 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts::0 2053 # Number of load instructions executed +system.cpu.iew.iewExecLoadInsts::1 2121 # Number of load instructions executed +system.cpu.iew.iewExecLoadInsts::total 4174 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1356 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp::0 0 # number of swp insts executed system.cpu.iew.exec_swp::1 0 # number of swp insts executed system.cpu.iew.exec_swp::total 0 # number of swp insts executed -system.cpu.iew.exec_nop::0 69 # number of nop insts executed -system.cpu.iew.exec_nop::1 66 # number of nop insts executed -system.cpu.iew.exec_nop::total 135 # number of nop insts executed -system.cpu.iew.exec_refs::0 3190 # number of memory reference insts executed -system.cpu.iew.exec_refs::1 3171 # number of memory reference insts executed -system.cpu.iew.exec_refs::total 6361 # number of memory reference insts executed -system.cpu.iew.exec_branches::0 1643 # Number of branches executed -system.cpu.iew.exec_branches::1 1639 # Number of branches executed -system.cpu.iew.exec_branches::total 3282 # Number of branches executed -system.cpu.iew.exec_stores::0 1082 # Number of stores executed -system.cpu.iew.exec_stores::1 1066 # Number of stores executed -system.cpu.iew.exec_stores::total 2148 # Number of stores executed -system.cpu.iew.exec_rate 0.726262 # Inst execution rate -system.cpu.iew.wb_sent::0 9814 # cumulative count of insts sent to commit -system.cpu.iew.wb_sent::1 9693 # cumulative count of insts sent to commit -system.cpu.iew.wb_sent::total 19507 # cumulative count of insts sent to commit -system.cpu.iew.wb_count::0 9690 # cumulative count of insts written-back -system.cpu.iew.wb_count::1 9546 # cumulative count of insts written-back -system.cpu.iew.wb_count::total 19236 # cumulative count of insts written-back -system.cpu.iew.wb_producers::0 5036 # num instructions producing a value -system.cpu.iew.wb_producers::1 4985 # num instructions producing a value -system.cpu.iew.wb_producers::total 10021 # num instructions producing a value -system.cpu.iew.wb_consumers::0 6558 # num instructions consuming a value -system.cpu.iew.wb_consumers::1 6494 # num instructions consuming a value -system.cpu.iew.wb_consumers::total 13052 # num instructions consuming a value +system.cpu.iew.exec_nop::0 70 # number of nop insts executed +system.cpu.iew.exec_nop::1 73 # number of nop insts executed +system.cpu.iew.exec_nop::total 143 # number of nop insts executed +system.cpu.iew.exec_refs::0 3144 # number of memory reference insts executed +system.cpu.iew.exec_refs::1 3199 # number of memory reference insts executed +system.cpu.iew.exec_refs::total 6343 # number of memory reference insts executed +system.cpu.iew.exec_branches::0 1633 # Number of branches executed +system.cpu.iew.exec_branches::1 1644 # Number of branches executed +system.cpu.iew.exec_branches::total 3277 # Number of branches executed +system.cpu.iew.exec_stores::0 1091 # Number of stores executed +system.cpu.iew.exec_stores::1 1078 # Number of stores executed +system.cpu.iew.exec_stores::total 2169 # Number of stores executed +system.cpu.iew.exec_rate 0.661647 # Inst execution rate +system.cpu.iew.wb_sent::0 9696 # cumulative count of insts sent to commit +system.cpu.iew.wb_sent::1 9663 # cumulative count of insts sent to commit +system.cpu.iew.wb_sent::total 19359 # cumulative count of insts sent to commit +system.cpu.iew.wb_count::0 9565 # cumulative count of insts written-back +system.cpu.iew.wb_count::1 9506 # cumulative count of insts written-back +system.cpu.iew.wb_count::total 19071 # cumulative count of insts written-back +system.cpu.iew.wb_producers::0 4909 # num instructions producing a value +system.cpu.iew.wb_producers::1 4894 # num instructions producing a value +system.cpu.iew.wb_producers::total 9803 # num instructions producing a value +system.cpu.iew.wb_consumers::0 6387 # num instructions consuming a value +system.cpu.iew.wb_consumers::1 6353 # num instructions consuming a value +system.cpu.iew.wb_consumers::total 12740 # num instructions consuming a value system.cpu.iew.wb_penalized::0 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.wb_penalized::1 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.wb_penalized::total 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate::0 0.351049 # insts written-back per cycle -system.cpu.iew.wb_rate::1 0.345832 # insts written-back per cycle -system.cpu.iew.wb_rate::total 0.696881 # insts written-back per cycle -system.cpu.iew.wb_fanout::0 0.767917 # average fanout of values written-back -system.cpu.iew.wb_fanout::1 0.767632 # average fanout of values written-back -system.cpu.iew.wb_fanout::total 0.767775 # average fanout of values written-back +system.cpu.iew.wb_rate::0 0.317943 # insts written-back per cycle +system.cpu.iew.wb_rate::1 0.315982 # insts written-back per cycle +system.cpu.iew.wb_rate::total 0.633925 # insts written-back per cycle +system.cpu.iew.wb_fanout::0 0.768592 # average fanout of values written-back +system.cpu.iew.wb_fanout::1 0.770345 # average fanout of values written-back +system.cpu.iew.wb_fanout::total 0.769466 # average fanout of values written-back system.cpu.iew.wb_penalized_rate::0 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.iew.wb_penalized_rate::1 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.iew.wb_penalized_rate::total 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 12807 # The number of committed instructions system.cpu.commit.commitCommittedOps 12807 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 12581 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 12383 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 34 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1295 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 21524 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.595010 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.388263 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 1285 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 24193 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.529368 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.313270 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 15949 74.10% 74.10% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 2814 13.07% 87.17% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 1173 5.45% 92.62% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 493 2.29% 94.91% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 336 1.56% 96.47% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 260 1.21% 97.68% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 183 0.85% 98.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 102 0.47% 99.01% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 214 0.99% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 18560 76.72% 76.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 2866 11.85% 88.56% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 1184 4.89% 93.46% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 489 2.02% 95.48% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 363 1.50% 96.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 239 0.99% 97.97% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 192 0.79% 98.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 93 0.38% 99.14% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 207 0.86% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 21524 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 24193 # Number of insts commited each cycle system.cpu.commit.committedInsts::0 6403 # Number of instructions committed system.cpu.commit.committedInsts::1 6404 # Number of instructions committed system.cpu.commit.committedInsts::total 12807 # Number of instructions committed @@ -445,27 +446,27 @@ system.cpu.commit.int_insts::total 12642 # Nu system.cpu.commit.function_calls::0 127 # Number of function calls committed. system.cpu.commit.function_calls::1 127 # Number of function calls committed. system.cpu.commit.function_calls::total 254 # Number of function calls committed. -system.cpu.commit.bw_lim_events 214 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 207 # number cycles where commit BW limit reached system.cpu.commit.bw_limited::0 0 # number of insts not committed due to BW limits system.cpu.commit.bw_limited::1 0 # number of insts not committed due to BW limits system.cpu.commit.bw_limited::total 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 111695 # The number of ROB reads -system.cpu.rob.rob_writes 53212 # The number of ROB writes -system.cpu.timesIdled 218 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 6021 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 116646 # The number of ROB reads +system.cpu.rob.rob_writes 52783 # The number of ROB writes +system.cpu.timesIdled 298 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 5825 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts::0 6386 # Number of Instructions Simulated system.cpu.committedInsts::1 6387 # Number of Instructions Simulated system.cpu.committedOps::0 6386 # Number of Ops (including micro ops) Simulated system.cpu.committedOps::1 6387 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 12773 # Number of Instructions Simulated -system.cpu.cpi::0 4.322424 # CPI: Cycles Per Instruction -system.cpu.cpi::1 4.321747 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.161043 # CPI: Total CPI of All Threads -system.cpu.ipc::0 0.231352 # IPC: Instructions Per Cycle -system.cpu.ipc::1 0.231388 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.462740 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 25345 # number of integer regfile reads -system.cpu.int_regfile_writes 14554 # number of integer regfile writes +system.cpu.cpi::0 4.710930 # CPI: Cycles Per Instruction +system.cpu.cpi::1 4.710193 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.355281 # CPI: Total CPI of All Threads +system.cpu.ipc::0 0.212272 # IPC: Instructions Per Cycle +system.cpu.ipc::1 0.212306 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.424578 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 25165 # number of integer regfile reads +system.cpu.int_regfile_writes 14392 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads system.cpu.fp_regfile_writes 4 # number of floating regfile writes system.cpu.misc_regfile_reads 2 # number of misc regfile reads @@ -473,50 +474,50 @@ system.cpu.misc_regfile_writes 2 # nu system.cpu.icache.replacements::0 6 # number of replacements system.cpu.icache.replacements::1 0 # number of replacements system.cpu.icache.replacements::total 6 # number of replacements -system.cpu.icache.tagsinuse 321.631643 # Cycle average of tags in use -system.cpu.icache.total_refs 4144 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 627 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 6.609250 # Average number of references to valid blocks. +system.cpu.icache.tagsinuse 315.592215 # Cycle average of tags in use +system.cpu.icache.total_refs 4122 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 626 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 6.584665 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 321.631643 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.157047 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.157047 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 4144 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 4144 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 4144 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 4144 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 4144 # number of overall hits -system.cpu.icache.overall_hits::total 4144 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 889 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 889 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 889 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 889 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 889 # number of overall misses -system.cpu.icache.overall_misses::total 889 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 31471500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 31471500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 31471500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 31471500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 31471500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 31471500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 5033 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 5033 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 5033 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 5033 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 5033 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 5033 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.176634 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.176634 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.176634 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.176634 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.176634 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.176634 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35401.012373 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 35401.012373 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 35401.012373 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 35401.012373 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 35401.012373 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 35401.012373 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 315.592215 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.154098 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.154098 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 4122 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 4122 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 4122 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 4122 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 4122 # number of overall hits +system.cpu.icache.overall_hits::total 4122 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 876 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 876 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 876 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 876 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 876 # number of overall misses +system.cpu.icache.overall_misses::total 876 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 34427000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 34427000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 34427000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 34427000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 34427000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 34427000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 4998 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 4998 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 4998 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 4998 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 4998 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 4998 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.175270 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.175270 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.175270 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.175270 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.175270 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.175270 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 39300.228311 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 39300.228311 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 39300.228311 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 39300.228311 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 39300.228311 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 39300.228311 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -525,96 +526,96 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 262 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 262 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 262 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 262 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 262 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 262 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 627 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 627 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 627 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 627 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 627 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 627 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22341500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 22341500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22341500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 22341500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22341500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 22341500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.124578 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.124578 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.124578 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.124578 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.124578 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.124578 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35632.376396 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 35632.376396 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35632.376396 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 35632.376396 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35632.376396 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 35632.376396 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 250 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 250 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 250 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 250 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 250 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 250 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 626 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 626 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 626 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 626 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 626 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 626 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 25017500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 25017500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 25017500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 25017500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 25017500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 25017500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.125250 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.125250 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.125250 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.125250 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.125250 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.125250 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 39964.057508 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 39964.057508 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 39964.057508 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 39964.057508 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 39964.057508 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 39964.057508 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements::0 0 # number of replacements system.cpu.dcache.replacements::1 0 # number of replacements system.cpu.dcache.replacements::total 0 # number of replacements -system.cpu.dcache.tagsinuse 221.639601 # Cycle average of tags in use -system.cpu.dcache.total_refs 4700 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 355 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 13.239437 # Average number of references to valid blocks. +system.cpu.dcache.tagsinuse 216.324578 # Cycle average of tags in use +system.cpu.dcache.total_refs 4646 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 350 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 13.274286 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 221.639601 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.054111 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.054111 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 3679 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 3679 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 1021 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 1021 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 4700 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 4700 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 4700 # number of overall hits -system.cpu.dcache.overall_hits::total 4700 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 312 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 312 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 709 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 709 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 1021 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1021 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1021 # number of overall misses -system.cpu.dcache.overall_misses::total 1021 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 11353000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 11353000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 22399000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 22399000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 33752000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 33752000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 33752000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 33752000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 3991 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 3991 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.occ_blocks::cpu.data 216.324578 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.052814 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.052814 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 3634 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 3634 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 1012 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 1012 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 4646 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 4646 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 4646 # number of overall hits +system.cpu.dcache.overall_hits::total 4646 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 315 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 315 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 718 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 718 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 1033 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1033 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1033 # number of overall misses +system.cpu.dcache.overall_misses::total 1033 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 14081500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 14081500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 28681000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 28681000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 42762500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 42762500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 42762500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 42762500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 3949 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 3949 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 1730 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 1730 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 5721 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 5721 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 5721 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 5721 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.078176 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.078176 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.409827 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.409827 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.178465 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.178465 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.178465 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.178465 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 36387.820513 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 36387.820513 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31592.383639 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 31592.383639 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 33057.786484 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 33057.786484 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 33057.786484 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 33057.786484 # average overall miss latency +system.cpu.dcache.demand_accesses::cpu.data 5679 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 5679 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 5679 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 5679 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.079767 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.079767 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.415029 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.415029 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.181898 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.181898 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.181898 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.181898 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 44703.174603 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 44703.174603 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39945.682451 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 39945.682451 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 41396.418199 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 41396.418199 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 41396.418199 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 41396.418199 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -623,173 +624,173 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 102 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 102 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 564 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 564 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 666 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 666 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 666 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 666 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 210 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 210 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 145 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 145 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 355 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 355 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 355 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 355 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7724000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 7724000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5248500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5248500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12972500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 12972500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12972500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 12972500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.052618 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.052618 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.083815 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.083815 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.062052 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.062052 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.062052 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.062052 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 36780.952381 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 36780.952381 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 36196.551724 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 36196.551724 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 36542.253521 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 36542.253521 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 36542.253521 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 36542.253521 # average overall mshr miss latency +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 111 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 111 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 572 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 572 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 683 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 683 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 683 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 683 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 204 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 204 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 146 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 146 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 350 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 350 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 350 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 350 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9596500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 9596500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6268000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 6268000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 15864500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 15864500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 15864500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 15864500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.051659 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.051659 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.061631 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.061631 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.061631 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.061631 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 47041.666667 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 47041.666667 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42931.506849 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42931.506849 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 45327.142857 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 45327.142857 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 45327.142857 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 45327.142857 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements::0 0 # number of replacements system.cpu.l2cache.replacements::1 0 # number of replacements system.cpu.l2cache.replacements::total 0 # number of replacements -system.cpu.l2cache.tagsinuse 447.061292 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 437.003550 # Cycle average of tags in use system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 835 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.002395 # Average number of references to valid blocks. +system.cpu.l2cache.sampled_refs 828 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.002415 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 321.947671 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 125.113621 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.009825 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.003818 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.013643 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 315.880086 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 121.123464 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.009640 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.003696 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.013336 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::total 2 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.inst 2 # number of overall hits system.cpu.l2cache.overall_hits::total 2 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 625 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 210 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 835 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 145 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 145 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 625 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 355 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 980 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 625 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 355 # number of overall misses -system.cpu.l2cache.overall_misses::total 980 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 21523000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 7330000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 28853000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5026500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 5026500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 21523000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 12356500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 33879500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 21523000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 12356500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 33879500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 627 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 210 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 837 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 145 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 145 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 627 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 355 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 982 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 627 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 355 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 982 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996810 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses::cpu.inst 624 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 204 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 828 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 146 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 146 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 624 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 350 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 974 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 624 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 350 # number of overall misses +system.cpu.l2cache.overall_misses::total 974 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 24336000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 9337500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 33673500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6106000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 6106000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 24336000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 15443500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 39779500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 24336000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 15443500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 39779500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 626 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 204 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 830 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 146 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 146 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 626 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 350 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 976 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 626 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 350 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 976 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996805 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.997611 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.997590 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996810 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996805 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.997963 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996810 # miss rate for overall accesses +system.cpu.l2cache.demand_miss_rate::total 0.997951 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996805 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.997963 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34436.800000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34904.761905 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 34554.491018 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34665.517241 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34665.517241 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34436.800000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34807.042254 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 34570.918367 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34436.800000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34807.042254 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 34570.918367 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 21000 # number of cycles access was blocked +system.cpu.l2cache.overall_miss_rate::total 0.997951 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 39000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 45772.058824 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 40668.478261 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 41821.917808 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 41821.917808 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 39000 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 44124.285714 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 40841.375770 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 39000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 44124.285714 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 40841.375770 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 37500 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 4 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 9 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs 5250 # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs 4166.666667 # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 625 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 210 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 835 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 145 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 145 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 625 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 355 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 980 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 625 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 355 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 980 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 19555500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 6675000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 26230500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4577500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4577500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19555500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11252500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 30808000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19555500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11252500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 30808000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996810 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 624 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 204 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 828 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 146 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 146 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 624 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 350 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 974 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 624 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 350 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 974 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 22375000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 8716000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 31091000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5649500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5649500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 22375000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 14365500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 36740500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 22375000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 14365500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 36740500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996805 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997611 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997590 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996810 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996805 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.997963 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996810 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.997951 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996805 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.997963 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31288.800000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31785.714286 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31413.772455 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31568.965517 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31568.965517 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31288.800000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31697.183099 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31436.734694 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31288.800000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31697.183099 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31436.734694 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.997951 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 35857.371795 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42725.490196 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 37549.516908 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 38695.205479 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 38695.205479 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 35857.371795 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 41044.285714 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 37721.252567 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 35857.371795 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 41044.285714 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 37721.252567 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/config.ini b/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/config.ini index b15f5671c..09d24317c 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/config.ini +++ b/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/config.ini @@ -181,7 +181,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side @@ -213,7 +213,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.physmem.port[0] slave=system.system_port system.cpu.l2cache.mem_side diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/simout b/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/simout index 30eeb514f..6fbf990e1 100755 --- a/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/simout +++ b/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 12:01:47 -gem5 started Jun 4 2012 14:44:53 +gem5 compiled Jul 2 2012 08:54:18 +gem5 started Jul 2 2012 11:30:48 gem5 executing on zizzer -command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/inorder-timing -re tests/run.py build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/inorder-timing +command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/quick/se/02.insttest/sparc/linux/inorder-timing -re tests/run.py build/SPARC/tests/fast/quick/se/02.insttest/sparc/linux/inorder-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Begining test of difficult SPARC instructions... @@ -18,4 +18,4 @@ LDTX: Passed LDTW: Passed STTW: Passed Done -Exiting @ tick 25007500 because target called exit() +Exiting @ tick 25615500 because target called exit() diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt index 73324a4d5..c2589ee2d 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt +++ b/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000025 # Number of seconds simulated -sim_ticks 25007500 # Number of ticks simulated -final_tick 25007500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000026 # Number of seconds simulated +sim_ticks 25615500 # Number of ticks simulated +final_tick 25615500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 72389 # Simulator instruction rate (inst/s) -host_op_rate 72383 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 119272701 # Simulator tick rate (ticks/s) -host_mem_usage 221376 # Number of bytes of host memory used -host_seconds 0.21 # Real time elapsed on the host +host_inst_rate 51797 # Simulator instruction rate (inst/s) +host_op_rate 51795 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 87424707 # Simulator tick rate (ticks/s) +host_mem_usage 219936 # Number of bytes of host memory used +host_seconds 0.29 # Real time elapsed on the host sim_insts 15175 # Number of instructions simulated sim_ops 15175 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 19072 # Number of bytes read from this memory @@ -19,36 +19,36 @@ system.physmem.bytes_inst_read::total 19072 # Nu system.physmem.num_reads::cpu.inst 298 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 138 # Number of read requests responded to by this memory system.physmem.num_reads::total 436 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 762651205 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 353174048 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1115825252 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 762651205 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 762651205 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 762651205 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 353174048 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1115825252 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 744549199 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 344791240 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1089340438 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 744549199 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 744549199 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 744549199 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 344791240 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1089340438 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 18 # Number of system calls -system.cpu.numCycles 50016 # number of cpu cycles simulated +system.cpu.numCycles 51232 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.branch_predictor.lookups 5015 # Number of BP lookups +system.cpu.branch_predictor.lookups 5014 # Number of BP lookups system.cpu.branch_predictor.condPredicted 3353 # Number of conditional branches predicted system.cpu.branch_predictor.condIncorrect 2379 # Number of conditional branches incorrect -system.cpu.branch_predictor.BTBLookups 3332 # Number of BTB lookups +system.cpu.branch_predictor.BTBLookups 3331 # Number of BTB lookups system.cpu.branch_predictor.BTBHits 2040 # Number of BTB hits system.cpu.branch_predictor.usedRAS 174 # Number of times the RAS was used to get a target. system.cpu.branch_predictor.RASInCorrect 5 # Number of incorrect RAS predictions. -system.cpu.branch_predictor.BTBHitPct 61.224490 # BTB Hit Percentage +system.cpu.branch_predictor.BTBHitPct 61.242870 # BTB Hit Percentage system.cpu.branch_predictor.predictedTaken 2214 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.predictedNotTaken 2801 # Number of Branches Predicted As Not Taken (False). +system.cpu.branch_predictor.predictedNotTaken 2800 # Number of Branches Predicted As Not Taken (False). system.cpu.regfile_manager.intRegFileReads 14401 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 11111 # Number of Writes to Int. Register File system.cpu.regfile_manager.intRegFileAccesses 25512 # Total Accesses (Read+Write) to the Int. Register File system.cpu.regfile_manager.floatRegFileReads 0 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 0 # Number of Writes to FP Register File system.cpu.regfile_manager.floatRegFileAccesses 0 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 4993 # Number of Registers Read Through Forwarding Logic -system.cpu.agen_unit.agens 3952 # Number of Address Generations +system.cpu.regfile_manager.regForwards 4991 # Number of Registers Read Through Forwarding Logic +system.cpu.agen_unit.agens 3950 # Number of Address Generations system.cpu.execution_unit.predictedTakenIncorrect 1316 # Number of Branches Incorrectly Predicted As Taken. system.cpu.execution_unit.predictedNotTakenIncorrect 1000 # Number of Branches Incorrectly Predicted As Not Taken). system.cpu.execution_unit.mispredicted 2316 # Number of Branches Incorrectly Predicted @@ -58,12 +58,12 @@ system.cpu.execution_unit.executions 11084 # Nu system.cpu.mult_div_unit.multiplies 0 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 21887 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 22262 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 453 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 32683 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 17333 # Number of cycles cpu stages are processed. -system.cpu.activity 34.654910 # Percentage of cycles cpu is active +system.cpu.timesIdled 525 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 33883 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 17349 # Number of cycles cpu stages are processed. +system.cpu.activity 33.863601 # Percentage of cycles cpu is active system.cpu.comLoads 2226 # Number of Load instructions committed system.cpu.comStores 1448 # Number of Store instructions committed system.cpu.comBranches 3359 # Number of Branches instructions committed @@ -75,72 +75,72 @@ system.cpu.committedInsts 15175 # Nu system.cpu.committedOps 15175 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 15175 # Number of Instructions committed (Total) -system.cpu.cpi 3.295947 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 3.376079 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 3.295947 # CPI: Total CPI of All Threads -system.cpu.ipc 0.303403 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 3.376079 # CPI: Total CPI of All Threads +system.cpu.ipc 0.296202 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 0.303403 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 36923 # Number of cycles 0 instructions are processed. +system.cpu.ipc_total 0.296202 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 38139 # Number of cycles 0 instructions are processed. system.cpu.stage0.runCycles 13093 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 26.177623 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 40814 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 9202 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 18.398113 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 41191 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 8825 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 17.644354 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 47132 # Number of cycles 0 instructions are processed. -system.cpu.stage3.runCycles 2884 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 5.766155 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 40690 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 9326 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 18.646033 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage0.utilization 25.556293 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 42033 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 9199 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 17.955575 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 42406 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 8826 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 17.227514 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 48347 # Number of cycles 0 instructions are processed. +system.cpu.stage3.runCycles 2885 # Number of cycles 1+ instructions are processed. +system.cpu.stage3.utilization 5.631246 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 41905 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 9327 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 18.205418 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 165.557258 # Cycle average of tags in use -system.cpu.icache.total_refs 2602 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 164.555255 # Cycle average of tags in use +system.cpu.icache.total_refs 2600 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 299 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 8.702341 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 8.695652 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 165.557258 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.080839 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.080839 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 2602 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 2602 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 2602 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 2602 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 2602 # number of overall hits -system.cpu.icache.overall_hits::total 2602 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 368 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 368 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 368 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 368 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 368 # number of overall misses -system.cpu.icache.overall_misses::total 368 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 20203500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 20203500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 20203500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 20203500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 20203500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 20203500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 2970 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 2970 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 2970 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 2970 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 2970 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 2970 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.123906 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.123906 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.123906 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.123906 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.123906 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.123906 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54900.815217 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 54900.815217 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 54900.815217 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 54900.815217 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 54900.815217 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 54900.815217 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 164.555255 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.080349 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.080349 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 2600 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 2600 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 2600 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 2600 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 2600 # number of overall hits +system.cpu.icache.overall_hits::total 2600 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 371 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 371 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 371 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 371 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 371 # number of overall misses +system.cpu.icache.overall_misses::total 371 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 20687000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 20687000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 20687000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 20687000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 20687000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 20687000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 2971 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 2971 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 2971 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 2971 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 2971 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 2971 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.124874 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.124874 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.124874 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.124874 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.124874 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.124874 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55760.107817 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 55760.107817 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 55760.107817 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 55760.107817 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 55760.107817 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 55760.107817 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 65500 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -149,72 +149,72 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets 32750 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 67 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 67 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 67 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 67 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 67 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 67 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 70 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 70 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 70 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 70 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 70 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 70 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 301 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 301 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 301 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 301 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 301 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 301 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15872000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 15872000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15872000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 15872000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15872000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 15872000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.101347 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.101347 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.101347 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.101347 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.101347 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.101347 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52730.897010 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52730.897010 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52730.897010 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 52730.897010 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52730.897010 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 52730.897010 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 16327000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 16327000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 16327000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 16327000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 16327000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 16327000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.101313 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.101313 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.101313 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.101313 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.101313 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.101313 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54242.524917 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54242.524917 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54242.524917 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 54242.524917 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54242.524917 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 54242.524917 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 97.041769 # Cycle average of tags in use -system.cpu.dcache.total_refs 3316 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 96.551113 # Cycle average of tags in use +system.cpu.dcache.total_refs 3315 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 138 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 24.028986 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 24.021739 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 97.041769 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.023692 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.023692 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::cpu.data 96.551113 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.023572 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.023572 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 2168 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 2168 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 1142 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 1142 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 1141 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 1141 # number of WriteReq hits system.cpu.dcache.SwapReq_hits::cpu.data 6 # number of SwapReq hits system.cpu.dcache.SwapReq_hits::total 6 # number of SwapReq hits -system.cpu.dcache.demand_hits::cpu.data 3310 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 3310 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 3310 # number of overall hits -system.cpu.dcache.overall_hits::total 3310 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 3309 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 3309 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 3309 # number of overall hits +system.cpu.dcache.overall_hits::total 3309 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 58 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 58 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 300 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 300 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 358 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 358 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 358 # number of overall misses -system.cpu.dcache.overall_misses::total 358 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 3281500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 3281500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 16397000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 16397000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 19678500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 19678500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 19678500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 19678500 # number of overall miss cycles +system.cpu.dcache.WriteReq_misses::cpu.data 301 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 301 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 359 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 359 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 359 # number of overall misses +system.cpu.dcache.overall_misses::total 359 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 3488000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 3488000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 18458000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 18458000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 21946000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 21946000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 21946000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 21946000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 2226 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 2226 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 1442 # number of WriteReq accesses(hits+misses) @@ -227,36 +227,36 @@ system.cpu.dcache.overall_accesses::cpu.data 3668 system.cpu.dcache.overall_accesses::total 3668 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.026056 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.026056 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.208044 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.208044 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.097601 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.097601 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.097601 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.097601 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56577.586207 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 56577.586207 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54656.666667 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 54656.666667 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 54967.877095 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 54967.877095 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 54967.877095 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 54967.877095 # average overall miss latency +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.208738 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.208738 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.097874 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.097874 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.097874 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.097874 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 60137.931034 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 60137.931034 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61322.259136 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 61322.259136 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 61130.919220 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 61130.919220 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 61130.919220 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 61130.919220 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 2208000 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 2258500 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 44 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 45 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 50181.818182 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 50188.888889 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.ReadReq_mshr_hits::cpu.data 5 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 5 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 215 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 215 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 220 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 220 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 220 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 220 # number of overall MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 216 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 216 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 221 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 221 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 221 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 221 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 53 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 53 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 85 # number of WriteReq MSHR misses @@ -265,14 +265,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 138 system.cpu.dcache.demand_mshr_misses::total 138 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 138 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2837000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2837000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4545000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4545000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7382000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 7382000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7382000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 7382000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2987500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2987500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4730000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4730000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7717500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 7717500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7717500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 7717500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.023810 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.023810 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.058946 # mshr miss rate for WriteReq accesses @@ -281,26 +281,26 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.037623 system.cpu.dcache.demand_mshr_miss_rate::total 0.037623 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.037623 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.037623 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53528.301887 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53528.301887 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53470.588235 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53470.588235 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53492.753623 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 53492.753623 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53492.753623 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 53492.753623 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 56367.924528 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 56367.924528 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 55647.058824 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 55647.058824 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 55923.913043 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 55923.913043 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 55923.913043 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 55923.913043 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 196.205624 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 195.062761 # Cycle average of tags in use system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 350 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.005714 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 164.948941 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 31.256684 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.005034 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.000954 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.005988 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 163.946873 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 31.115888 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.005003 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.000950 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.005953 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits @@ -318,17 +318,17 @@ system.cpu.l2cache.demand_misses::total 437 # nu system.cpu.l2cache.overall_misses::cpu.inst 299 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 138 # number of overall misses system.cpu.l2cache.overall_misses::total 437 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 15533000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2776500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 18309500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4442500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 4442500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 15533000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 7219000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 22752000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 15533000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 7219000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 22752000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 15990000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2926500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 18916500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4635000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 4635000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 15990000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 7561500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 23551500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 15990000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 7561500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 23551500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 301 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 53 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 354 # number of ReadReq accesses(hits+misses) @@ -351,17 +351,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.995444 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993355 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.995444 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 51949.832776 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52386.792453 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52015.625000 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52264.705882 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52264.705882 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 51949.832776 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52311.594203 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52064.073227 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 51949.832776 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52311.594203 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52064.073227 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 53478.260870 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 55216.981132 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 53740.056818 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 54529.411765 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 54529.411765 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 53478.260870 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 54793.478261 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 53893.592677 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53478.260870 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 54793.478261 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 53893.592677 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -381,17 +381,17 @@ system.cpu.l2cache.demand_mshr_misses::total 437 system.cpu.l2cache.overall_mshr_misses::cpu.inst 299 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 437 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11916000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2132500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14048500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3416000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3416000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11916000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5548500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 17464500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11916000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5548500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 17464500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 12379500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2285000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14664500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3604000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3604000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 12379500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5889000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 18268500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 12379500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5889000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 18268500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993355 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.994350 # mshr miss rate for ReadReq accesses @@ -403,17 +403,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.995444 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993355 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.995444 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 39852.842809 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40235.849057 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 39910.511364 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40188.235294 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40188.235294 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 39852.842809 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40206.521739 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39964.530892 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 39852.842809 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40206.521739 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39964.530892 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41403.010033 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 43113.207547 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 41660.511364 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42400 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42400 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41403.010033 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42673.913043 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 41804.347826 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41403.010033 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42673.913043 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 41804.347826 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/config.ini b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/config.ini index e306accf8..f6619bb03 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/config.ini +++ b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/config.ini @@ -479,7 +479,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side @@ -511,7 +511,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.physmem.port[0] slave=system.system_port system.cpu.l2cache.mem_side diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simout b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simout index c81e9ca95..47b15000f 100755 --- a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simout +++ b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simout @@ -1,8 +1,8 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 28 2012 22:06:58 -gem5 started Jun 28 2012 22:53:48 +gem5 compiled Jul 2 2012 08:54:18 +gem5 started Jul 2 2012 11:30:59 gem5 executing on zizzer command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/quick/se/02.insttest/sparc/linux/o3-timing -re tests/run.py build/SPARC/tests/fast/quick/se/02.insttest/sparc/linux/o3-timing Global frequency set at 1000000000000 ticks per second @@ -18,4 +18,4 @@ LDTX: Passed LDTW: Passed STTW: Passed Done -Exiting @ tick 19806500 because target called exit() +Exiting @ tick 20274500 because target called exit() diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt index 52156950f..49a67051b 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt +++ b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt @@ -1,269 +1,269 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000020 # Number of seconds simulated -sim_ticks 19806500 # Number of ticks simulated -final_tick 19806500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 20274500 # Number of ticks simulated +final_tick 20274500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 96556 # Simulator instruction rate (inst/s) -host_op_rate 96545 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 132327745 # Simulator tick rate (ticks/s) -host_mem_usage 221008 # Number of bytes of host memory used -host_seconds 0.15 # Real time elapsed on the host +host_inst_rate 55162 # Simulator instruction rate (inst/s) +host_op_rate 55159 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 77392529 # Simulator tick rate (ticks/s) +host_mem_usage 220968 # Number of bytes of host memory used +host_seconds 0.26 # Real time elapsed on the host sim_insts 14449 # Number of instructions simulated sim_ops 14449 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 21632 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 21568 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 9344 # Number of bytes read from this memory -system.physmem.bytes_read::total 30976 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 21632 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 21632 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 338 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 30912 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 21568 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 21568 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 337 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 146 # Number of read requests responded to by this memory -system.physmem.num_reads::total 484 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1092166713 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 471764320 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1563931033 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1092166713 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1092166713 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1092166713 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 471764320 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1563931033 # Total bandwidth to/from this memory (bytes/s) +system.physmem.num_reads::total 483 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1063799354 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 460874498 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1524673851 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1063799354 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1063799354 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1063799354 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 460874498 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1524673851 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 18 # Number of system calls -system.cpu.numCycles 39614 # number of cpu cycles simulated +system.cpu.numCycles 40550 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 6890 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 4576 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 1121 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 5201 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 2595 # Number of BTB hits +system.cpu.BPredUnit.lookups 6892 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 4586 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 1120 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 5125 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 2600 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 459 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.usedRAS 458 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 168 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 11869 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 32300 # Number of instructions fetch has processed -system.cpu.fetch.Branches 6890 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 3054 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 9560 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 3188 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 6935 # Number of cycles fetch has spent blocked +system.cpu.fetch.icacheStallCycles 12259 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 32259 # Number of instructions fetch has processed +system.cpu.fetch.Branches 6892 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 3058 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 9557 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 3181 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 7365 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 726 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 5516 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 469 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 31065 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.039755 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.210803 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.PendingTrapStallCycles 767 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 5500 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 472 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 31917 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.010715 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.185460 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 21505 69.23% 69.23% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 4746 15.28% 84.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 494 1.59% 86.09% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 444 1.43% 87.52% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 682 2.20% 89.72% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 763 2.46% 92.17% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 240 0.77% 92.95% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 277 0.89% 93.84% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1914 6.16% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 22360 70.06% 70.06% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 4750 14.88% 84.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 493 1.54% 86.48% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 436 1.37% 87.85% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 686 2.15% 90.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 773 2.42% 92.42% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 235 0.74% 93.16% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 276 0.86% 94.02% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1908 5.98% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 31065 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.173928 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.815368 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 12513 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 7669 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 8722 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 190 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1971 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 30088 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 1971 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 13189 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 248 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 6922 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 8283 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 452 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 27408 # Number of instructions processed by rename -system.cpu.rename.IQFullEvents 5 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 125 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 24445 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 50953 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 50953 # Number of integer rename lookups +system.cpu.fetch.rateDist::total 31917 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.169963 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.795536 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 12903 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 8133 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 8719 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 197 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1965 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 30080 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 1965 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 13582 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 285 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 7298 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 8277 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 510 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 27385 # Number of instructions processed by rename +system.cpu.rename.IQFullEvents 11 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 172 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 24421 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 50913 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 50913 # Number of integer rename lookups system.cpu.rename.CommittedMaps 13832 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 10613 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 705 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 708 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 2841 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 3647 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 2469 # Number of stores inserted to the mem dependence unit. +system.cpu.rename.UndoneMaps 10589 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 704 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 706 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 2903 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 3640 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 2472 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 4 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 23180 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 670 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 21761 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 105 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 8457 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 5919 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 195 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 31065 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.700499 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.316624 # Number of insts issued each cycle +system.cpu.iq.iqInstsAdded 23148 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 669 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 21730 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 108 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 8364 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 5915 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 194 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 31917 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.680828 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.297413 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 21619 69.59% 69.59% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 3603 11.60% 81.19% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 2384 7.67% 88.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 1730 5.57% 94.43% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 898 2.89% 97.32% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 488 1.57% 98.90% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 252 0.81% 99.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 72 0.23% 99.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 19 0.06% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 22417 70.24% 70.24% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 3682 11.54% 81.77% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 2373 7.43% 89.21% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 1722 5.40% 94.60% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 904 2.83% 97.43% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 493 1.54% 98.98% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 244 0.76% 99.74% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 65 0.20% 99.95% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 17 0.05% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 31065 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 31917 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 54 29.19% 29.19% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 29.19% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 29.19% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 29.19% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 29.19% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 29.19% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 29.19% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 29.19% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 29.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 29.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 29.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 29.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 29.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 29.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 29.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 29.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 29.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 29.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 29.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 29.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 29.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 29.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 29.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 29.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 29.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 29.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 29.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 29.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 29.19% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 26 14.05% 43.24% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 105 56.76% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 46 26.59% 26.59% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 26.59% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 26.59% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 26.59% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 26.59% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 26.59% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 26.59% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 26.59% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 26.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 26.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 26.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 26.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 26.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 26.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 26.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 26.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 26.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 26.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 26.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 26.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 26.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 26.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 26.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 26.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 26.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 26.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 26.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 26.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 26.59% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 24 13.87% 40.46% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 103 59.54% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 16056 73.78% 73.78% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 73.78% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 73.78% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 73.78% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 73.78% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 73.78% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 73.78% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 73.78% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 73.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 73.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 73.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 73.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 73.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 73.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 73.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 73.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 73.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 73.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 73.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 73.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 73.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 73.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 73.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 73.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 73.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 73.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 73.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 73.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 73.78% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 3441 15.81% 89.60% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 2264 10.40% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 16031 73.77% 73.77% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 73.77% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 73.77% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 73.77% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 73.77% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 73.77% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 73.77% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 73.77% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 73.77% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 73.77% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 73.77% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 73.77% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 73.77% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 73.77% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 73.77% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 73.77% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 73.77% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 73.77% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 73.77% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 73.77% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 73.77% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 73.77% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 73.77% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 73.77% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 73.77% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 73.77% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 73.77% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 73.77% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 73.77% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 3433 15.80% 89.57% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 2266 10.43% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 21761 # Type of FU issued -system.cpu.iq.rate 0.549326 # Inst issue rate -system.cpu.iq.fu_busy_cnt 185 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.008501 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 74877 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 32333 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 19979 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 21730 # Type of FU issued +system.cpu.iq.rate 0.535882 # Inst issue rate +system.cpu.iq.fu_busy_cnt 173 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.007961 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 75658 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 32207 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 19957 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 21946 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 21903 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 26 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1421 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1414 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 27 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1021 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 1024 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1971 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 144 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 11 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 25018 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 406 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 3647 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 2469 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 670 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 3 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 1965 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 99 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 5 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 24982 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 417 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 3640 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 2472 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 669 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 2 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 27 # Number of memory order violations system.cpu.iew.predictedTakenIncorrect 291 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 962 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1253 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 20571 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 3278 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1190 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedNotTakenIncorrect 958 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1249 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 20553 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 3273 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1177 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1168 # number of nop insts executed -system.cpu.iew.exec_refs 5421 # number of memory reference insts executed -system.cpu.iew.exec_branches 4301 # Number of branches executed -system.cpu.iew.exec_stores 2143 # Number of stores executed -system.cpu.iew.exec_rate 0.519286 # Inst execution rate -system.cpu.iew.wb_sent 20246 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 19979 # cumulative count of insts written-back -system.cpu.iew.wb_producers 9281 # num instructions producing a value -system.cpu.iew.wb_consumers 11411 # num instructions consuming a value +system.cpu.iew.exec_nop 1165 # number of nop insts executed +system.cpu.iew.exec_refs 5419 # number of memory reference insts executed +system.cpu.iew.exec_branches 4294 # Number of branches executed +system.cpu.iew.exec_stores 2146 # Number of stores executed +system.cpu.iew.exec_rate 0.506856 # Inst execution rate +system.cpu.iew.wb_sent 20221 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 19957 # cumulative count of insts written-back +system.cpu.iew.wb_producers 9257 # num instructions producing a value +system.cpu.iew.wb_consumers 11359 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.504342 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.813338 # average fanout of values written-back +system.cpu.iew.wb_rate 0.492158 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.814948 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 15175 # The number of committed instructions system.cpu.commit.commitCommittedOps 15175 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 9761 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 9725 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 475 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1121 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 29111 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.521281 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.203804 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 1120 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 29969 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.506357 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.189037 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 21721 74.61% 74.61% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 4069 13.98% 88.59% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 1444 4.96% 93.55% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 793 2.72% 96.28% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 337 1.16% 97.43% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 258 0.89% 98.32% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 320 1.10% 99.42% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 71 0.24% 99.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 98 0.34% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 22543 75.22% 75.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 4136 13.80% 89.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 1421 4.74% 93.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 789 2.63% 96.40% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 331 1.10% 97.50% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 259 0.86% 98.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 318 1.06% 99.43% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 73 0.24% 99.67% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 99 0.33% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 29111 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 29969 # Number of insts commited each cycle system.cpu.commit.committedInsts 15175 # Number of instructions committed system.cpu.commit.committedOps 15175 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -274,68 +274,68 @@ system.cpu.commit.branches 3359 # Nu system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. system.cpu.commit.int_insts 12186 # Number of committed integer instructions. system.cpu.commit.function_calls 187 # Number of function calls committed. -system.cpu.commit.bw_lim_events 98 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 99 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 53126 # The number of ROB reads -system.cpu.rob.rob_writes 51851 # The number of ROB writes -system.cpu.timesIdled 186 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 8549 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 53947 # The number of ROB reads +system.cpu.rob.rob_writes 51773 # The number of ROB writes +system.cpu.timesIdled 196 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 8633 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 14449 # Number of Instructions Simulated system.cpu.committedOps 14449 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 14449 # Number of Instructions Simulated -system.cpu.cpi 2.741643 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.741643 # CPI: Total CPI of All Threads -system.cpu.ipc 0.364745 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.364745 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 32757 # number of integer regfile reads -system.cpu.int_regfile_writes 18209 # number of integer regfile writes -system.cpu.misc_regfile_reads 7073 # number of misc regfile reads +system.cpu.cpi 2.806423 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.806423 # CPI: Total CPI of All Threads +system.cpu.ipc 0.356326 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.356326 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 32739 # number of integer regfile reads +system.cpu.int_regfile_writes 18191 # number of integer regfile writes +system.cpu.misc_regfile_reads 7070 # number of misc regfile reads system.cpu.misc_regfile_writes 569 # number of misc regfile writes system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 201.055469 # Cycle average of tags in use -system.cpu.icache.total_refs 5034 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 340 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 14.805882 # Average number of references to valid blocks. +system.cpu.icache.tagsinuse 199.218311 # Cycle average of tags in use +system.cpu.icache.total_refs 5020 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 339 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 14.808260 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 201.055469 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.098172 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.098172 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 5034 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 5034 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 5034 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 5034 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 5034 # number of overall hits -system.cpu.icache.overall_hits::total 5034 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 482 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 482 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 482 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 482 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 482 # number of overall misses -system.cpu.icache.overall_misses::total 482 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 16634500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 16634500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 16634500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 16634500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 16634500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 16634500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 5516 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 5516 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 5516 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 5516 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 5516 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 5516 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.087382 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.087382 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.087382 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.087382 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.087382 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.087382 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34511.410788 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 34511.410788 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 34511.410788 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 34511.410788 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 34511.410788 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 34511.410788 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 199.218311 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.097275 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.097275 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 5020 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 5020 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 5020 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 5020 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 5020 # number of overall hits +system.cpu.icache.overall_hits::total 5020 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 480 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 480 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 480 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 480 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 480 # number of overall misses +system.cpu.icache.overall_misses::total 480 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 16877500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 16877500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 16877500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 16877500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 16877500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 16877500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 5500 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 5500 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 5500 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 5500 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 5500 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 5500 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.087273 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.087273 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.087273 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.087273 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.087273 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.087273 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35161.458333 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 35161.458333 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 35161.458333 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 35161.458333 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 35161.458333 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 35161.458333 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -344,98 +344,98 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 142 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 142 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 142 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 142 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 142 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 142 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 340 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 340 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 340 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 340 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 340 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 340 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11937500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 11937500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11937500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 11937500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11937500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 11937500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.061639 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.061639 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.061639 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.061639 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.061639 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.061639 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35110.294118 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 35110.294118 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35110.294118 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 35110.294118 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35110.294118 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 35110.294118 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 141 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 141 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 141 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 141 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 141 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 141 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 339 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 339 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 339 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 339 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 339 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 339 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12213000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 12213000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12213000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 12213000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12213000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 12213000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.061636 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.061636 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.061636 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.061636 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.061636 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.061636 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36026.548673 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 36026.548673 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36026.548673 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 36026.548673 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36026.548673 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 36026.548673 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 103.574586 # Cycle average of tags in use -system.cpu.dcache.total_refs 4084 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 102.764065 # Cycle average of tags in use +system.cpu.dcache.total_refs 4075 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 146 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 27.972603 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 27.910959 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 103.574586 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.025287 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.025287 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 3044 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 3044 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 1034 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 1034 # number of WriteReq hits +system.cpu.dcache.occ_blocks::cpu.data 102.764065 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.025089 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.025089 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 3036 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 3036 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 1033 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 1033 # number of WriteReq hits system.cpu.dcache.SwapReq_hits::cpu.data 6 # number of SwapReq hits system.cpu.dcache.SwapReq_hits::total 6 # number of SwapReq hits -system.cpu.dcache.demand_hits::cpu.data 4078 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 4078 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 4078 # number of overall hits -system.cpu.dcache.overall_hits::total 4078 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 116 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 116 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 408 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 408 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 524 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 524 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 524 # number of overall misses -system.cpu.dcache.overall_misses::total 524 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 4022000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 4022000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 14592500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 14592500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 18614500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 18614500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 18614500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 18614500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 3160 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 3160 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.data 4069 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 4069 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 4069 # number of overall hits +system.cpu.dcache.overall_hits::total 4069 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 121 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 121 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 409 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 409 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 530 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 530 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 530 # number of overall misses +system.cpu.dcache.overall_misses::total 530 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 4649500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 4649500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 17651000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 17651000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 22300500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 22300500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 22300500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 22300500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 3157 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 3157 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 1442 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 1442 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SwapReq_accesses::cpu.data 6 # number of SwapReq accesses(hits+misses) system.cpu.dcache.SwapReq_accesses::total 6 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 4602 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 4602 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 4602 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 4602 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.036709 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.036709 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.282940 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.282940 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.113864 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.113864 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.113864 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.113864 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34672.413793 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 34672.413793 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35765.931373 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 35765.931373 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 35523.854962 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 35523.854962 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 35523.854962 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 35523.854962 # average overall miss latency +system.cpu.dcache.demand_accesses::cpu.data 4599 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 4599 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 4599 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 4599 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.038328 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.038328 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.283634 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.283634 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.115242 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.115242 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.115242 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.115242 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 38425.619835 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 38425.619835 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 43156.479218 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 43156.479218 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 42076.415094 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 42076.415094 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 42076.415094 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 42076.415094 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -444,14 +444,14 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 53 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 53 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 325 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 325 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 378 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 378 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 378 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 378 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 58 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 58 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 326 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 326 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 384 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 384 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 384 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 384 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 63 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 63 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 83 # number of WriteReq MSHR misses @@ -460,103 +460,103 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 146 system.cpu.dcache.demand_mshr_misses::total 146 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 146 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 146 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2243500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2243500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2978500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2978500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5222000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 5222000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5222000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 5222000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.019937 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.019937 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2518000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2518000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3293000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3293000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5811000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 5811000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5811000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 5811000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.019956 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.019956 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.057559 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.057559 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.031725 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.031725 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.031725 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.031725 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 35611.111111 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 35611.111111 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35885.542169 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35885.542169 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 35767.123288 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 35767.123288 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 35767.123288 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 35767.123288 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.031746 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.031746 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.031746 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.031746 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 39968.253968 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 39968.253968 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 39674.698795 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 39674.698795 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 39801.369863 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 39801.369863 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 39801.369863 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 39801.369863 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 236.586962 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 234.467813 # Cycle average of tags in use system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 401 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.004988 # Average number of references to valid blocks. +system.cpu.l2cache.sampled_refs 400 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.005000 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 200.308921 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 36.278041 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.006113 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.001107 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.007220 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 198.479082 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 35.988731 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.006057 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.001098 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.007155 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::total 2 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.inst 2 # number of overall hits system.cpu.l2cache.overall_hits::total 2 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 338 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.inst 337 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.data 63 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 401 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 400 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 83 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 83 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 338 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 337 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.data 146 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 484 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 338 # number of overall misses +system.cpu.l2cache.demand_misses::total 483 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 337 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 146 # number of overall misses -system.cpu.l2cache.overall_misses::total 484 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 11581500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2169000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 13750500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2869000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 2869000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 11581500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 5038000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 16619500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 11581500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 5038000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 16619500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 340 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.overall_misses::total 483 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 11867000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2431500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 14298500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3194500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 3194500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 11867000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 5626000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 17493000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 11867000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 5626000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 17493000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 339 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 63 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 403 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 402 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 83 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 83 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 340 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 339 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 146 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 486 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 340 # number of overall (read+write) accesses +system.cpu.l2cache.demand_accesses::total 485 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 339 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 146 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 486 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.994118 # miss rate for ReadReq accesses +system.cpu.l2cache.overall_accesses::total 485 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.994100 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.995037 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.995025 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.994118 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.994100 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.995885 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.994118 # miss rate for overall accesses +system.cpu.l2cache.demand_miss_rate::total 0.995876 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.994100 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.995885 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34264.792899 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34428.571429 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 34290.523691 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34566.265060 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34566.265060 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34264.792899 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34506.849315 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 34337.809917 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34264.792899 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34506.849315 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 34337.809917 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::total 0.995876 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35213.649852 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 38595.238095 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 35746.250000 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 38487.951807 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 38487.951807 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35213.649852 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 38534.246575 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 36217.391304 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35213.649852 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 38534.246575 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 36217.391304 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -565,50 +565,50 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 338 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 337 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 63 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 401 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 400 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 83 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 83 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 338 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 337 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 146 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 484 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 338 # number of overall MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 483 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 337 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 146 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 484 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10495000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1969500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 12464500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2607500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2607500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10495000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4577000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 15072000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10495000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4577000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 15072000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.994118 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.overall_mshr_misses::total 483 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10794500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2238500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13033000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2937500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2937500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10794500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5176000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 15970500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10794500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5176000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 15970500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.994100 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.995037 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.995025 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.994118 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.994100 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.995885 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.994118 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.995876 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.994100 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.995885 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31050.295858 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31261.904762 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31083.541147 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31415.662651 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31415.662651 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31050.295858 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31349.315068 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31140.495868 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31050.295858 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31349.315068 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31140.495868 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.995876 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32031.157270 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 35531.746032 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 32582.500000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 35391.566265 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 35391.566265 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32031.157270 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 35452.054795 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 33065.217391 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32031.157270 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 35452.054795 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 33065.217391 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/config.ini b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/config.ini index cfbf65944..10c1546b5 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/config.ini +++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/config.ini @@ -148,7 +148,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side @@ -180,7 +180,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.physmem.port[0] slave=system.system_port system.cpu.l2cache.mem_side diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/simout b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/simout index 423d84a63..71ca2d641 100755 --- a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/simout +++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 12:01:47 -gem5 started Jun 4 2012 14:45:13 +gem5 compiled Jul 2 2012 08:54:18 +gem5 started Jul 2 2012 11:31:22 gem5 executing on zizzer -command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/simple-timing +command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/quick/se/02.insttest/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/fast/quick/se/02.insttest/sparc/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Begining test of difficult SPARC instructions... @@ -18,4 +18,4 @@ LDTX: Passed LDTW: Passed STTW: Passed Done -Exiting @ tick 41800000 because target called exit() +Exiting @ tick 43120000 because target called exit() diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt index f6532c6ee..54833842f 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000042 # Number of seconds simulated -sim_ticks 41800000 # Number of ticks simulated -final_tick 41800000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000043 # Number of seconds simulated +sim_ticks 43120000 # Number of ticks simulated +final_tick 43120000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 488993 # Simulator instruction rate (inst/s) -host_op_rate 488707 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1345414902 # Simulator tick rate (ticks/s) -host_mem_usage 221064 # Number of bytes of host memory used -host_seconds 0.03 # Real time elapsed on the host +host_inst_rate 107758 # Simulator instruction rate (inst/s) +host_op_rate 107745 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 306125993 # Simulator tick rate (ticks/s) +host_mem_usage 219936 # Number of bytes of host memory used +host_seconds 0.14 # Real time elapsed on the host sim_insts 15175 # Number of instructions simulated sim_ops 15175 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 17792 # Number of bytes read from this memory @@ -19,16 +19,16 @@ system.physmem.bytes_inst_read::total 17792 # Nu system.physmem.num_reads::cpu.inst 278 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 138 # Number of read requests responded to by this memory system.physmem.num_reads::total 416 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 425645933 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 211291866 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 636937799 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 425645933 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 425645933 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 425645933 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 211291866 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 636937799 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 412615955 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 204823748 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 617439703 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 412615955 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 412615955 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 412615955 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 204823748 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 617439703 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 18 # Number of system calls -system.cpu.numCycles 83600 # number of cpu cycles simulated +system.cpu.numCycles 86240 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 15175 # Number of instructions committed @@ -47,18 +47,18 @@ system.cpu.num_mem_refs 3684 # nu system.cpu.num_load_insts 2232 # Number of load instructions system.cpu.num_store_insts 1452 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 83600 # Number of busy cycles +system.cpu.num_busy_cycles 86240 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 153.436702 # Cycle average of tags in use +system.cpu.icache.tagsinuse 152.912665 # Cycle average of tags in use system.cpu.icache.total_refs 14941 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 280 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 53.360714 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 153.436702 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.074920 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.074920 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::cpu.inst 152.912665 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.074664 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.074664 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 14941 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 14941 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 14941 # number of demand (read+write) hits @@ -129,14 +129,14 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52700 system.cpu.icache.overall_avg_mshr_miss_latency::total 52700 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 97.842991 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 97.642881 # Cycle average of tags in use system.cpu.dcache.total_refs 3536 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 138 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 25.623188 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 97.842991 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.023887 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.023887 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::cpu.data 97.642881 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.023839 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.023839 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 2173 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 2173 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 1357 # number of WriteReq hits @@ -231,16 +231,16 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 184.236128 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 183.636297 # Cycle average of tags in use system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 331 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.006042 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 152.765242 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 31.470886 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.004662 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.000960 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.005622 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 152.238639 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 31.397658 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.004646 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.000958 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.005604 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini index 08b3f6997..e18da5544 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini @@ -1773,7 +1773,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.physmem.port[0] slave=system.l2c.mem_side system.system_port @@ -1795,7 +1795,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.l2c.cpu_side slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu2.icache.mem_side system.cpu2.dcache.mem_side system.cpu3.icache.mem_side system.cpu3.dcache.mem_side diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout index b2cdd54e1..2447cd00c 100755 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout @@ -1,8 +1,8 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 28 2012 22:06:58 -gem5 started Jun 28 2012 22:54:10 +gem5 compiled Jul 2 2012 08:54:18 +gem5 started Jul 2 2012 11:31:33 gem5 executing on zizzer command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp -re tests/run.py build/SPARC/tests/fast/quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp Global frequency set at 1000000000000 ticks per second @@ -17,66 +17,66 @@ Init done Iteration 1 completed [Iteration 2, Thread 3] Got lock [Iteration 2, Thread 3] Critical section done, previously next=0, now next=3 -[Iteration 2, Thread 1] Got lock -[Iteration 2, Thread 1] Critical section done, previously next=3, now next=1 [Iteration 2, Thread 2] Got lock -[Iteration 2, Thread 2] Critical section done, previously next=1, now next=2 +[Iteration 2, Thread 2] Critical section done, previously next=3, now next=2 +[Iteration 2, Thread 1] Got lock +[Iteration 2, Thread 1] Critical section done, previously next=2, now next=1 Iteration 2 completed -[Iteration 3, Thread 3] Got lock -[Iteration 3, Thread 3] Critical section done, previously next=0, now next=3 [Iteration 3, Thread 2] Got lock -[Iteration 3, Thread 2] Critical section done, previously next=3, now next=2 +[Iteration 3, Thread 2] Critical section done, previously next=0, now next=2 [Iteration 3, Thread 1] Got lock [Iteration 3, Thread 1] Critical section done, previously next=2, now next=1 +[Iteration 3, Thread 3] Got lock +[Iteration 3, Thread 3] Critical section done, previously next=1, now next=3 Iteration 3 completed -[Iteration 4, Thread 3] Got lock -[Iteration 4, Thread 3] Critical section done, previously next=0, now next=3 -[Iteration 4, Thread 1] Got lock -[Iteration 4, Thread 1] Critical section done, previously next=3, now next=1 [Iteration 4, Thread 2] Got lock -[Iteration 4, Thread 2] Critical section done, previously next=1, now next=2 +[Iteration 4, Thread 2] Critical section done, previously next=0, now next=2 +[Iteration 4, Thread 1] Got lock +[Iteration 4, Thread 1] Critical section done, previously next=2, now next=1 +[Iteration 4, Thread 3] Got lock +[Iteration 4, Thread 3] Critical section done, previously next=1, now next=3 Iteration 4 completed -[Iteration 5, Thread 3] Got lock -[Iteration 5, Thread 3] Critical section done, previously next=0, now next=3 [Iteration 5, Thread 2] Got lock -[Iteration 5, Thread 2] Critical section done, previously next=3, now next=2 +[Iteration 5, Thread 2] Critical section done, previously next=0, now next=2 +[Iteration 5, Thread 3] Got lock +[Iteration 5, Thread 3] Critical section done, previously next=2, now next=3 [Iteration 5, Thread 1] Got lock -[Iteration 5, Thread 1] Critical section done, previously next=2, now next=1 +[Iteration 5, Thread 1] Critical section done, previously next=3, now next=1 Iteration 5 completed +[Iteration 6, Thread 3] Got lock +[Iteration 6, Thread 3] Critical section done, previously next=0, now next=3 [Iteration 6, Thread 2] Got lock -[Iteration 6, Thread 2] Critical section done, previously next=0, now next=2 +[Iteration 6, Thread 2] Critical section done, previously next=3, now next=2 [Iteration 6, Thread 1] Got lock [Iteration 6, Thread 1] Critical section done, previously next=2, now next=1 -[Iteration 6, Thread 3] Got lock -[Iteration 6, Thread 3] Critical section done, previously next=1, now next=3 Iteration 6 completed -[Iteration 7, Thread 1] Got lock -[Iteration 7, Thread 1] Critical section done, previously next=0, now next=1 -[Iteration 7, Thread 3] Got lock -[Iteration 7, Thread 3] Critical section done, previously next=1, now next=3 [Iteration 7, Thread 2] Got lock -[Iteration 7, Thread 2] Critical section done, previously next=3, now next=2 +[Iteration 7, Thread 2] Critical section done, previously next=0, now next=2 +[Iteration 7, Thread 3] Got lock +[Iteration 7, Thread 3] Critical section done, previously next=2, now next=3 +[Iteration 7, Thread 1] Got lock +[Iteration 7, Thread 1] Critical section done, previously next=3, now next=1 Iteration 7 completed +[Iteration 8, Thread 1] Got lock +[Iteration 8, Thread 1] Critical section done, previously next=0, now next=1 [Iteration 8, Thread 2] Got lock -[Iteration 8, Thread 2] Critical section done, previously next=0, now next=2 +[Iteration 8, Thread 2] Critical section done, previously next=1, now next=2 [Iteration 8, Thread 3] Got lock [Iteration 8, Thread 3] Critical section done, previously next=2, now next=3 -[Iteration 8, Thread 1] Got lock -[Iteration 8, Thread 1] Critical section done, previously next=3, now next=1 Iteration 8 completed -[Iteration 9, Thread 2] Got lock -[Iteration 9, Thread 2] Critical section done, previously next=0, now next=2 -[Iteration 9, Thread 1] Got lock -[Iteration 9, Thread 1] Critical section done, previously next=2, now next=1 [Iteration 9, Thread 3] Got lock -[Iteration 9, Thread 3] Critical section done, previously next=1, now next=3 +[Iteration 9, Thread 3] Critical section done, previously next=0, now next=3 +[Iteration 9, Thread 1] Got lock +[Iteration 9, Thread 1] Critical section done, previously next=3, now next=1 +[Iteration 9, Thread 2] Got lock +[Iteration 9, Thread 2] Critical section done, previously next=1, now next=2 Iteration 9 completed -[Iteration 10, Thread 3] Got lock -[Iteration 10, Thread 3] Critical section done, previously next=0, now next=3 [Iteration 10, Thread 2] Got lock -[Iteration 10, Thread 2] Critical section done, previously next=3, now next=2 +[Iteration 10, Thread 2] Critical section done, previously next=0, now next=2 +[Iteration 10, Thread 3] Got lock +[Iteration 10, Thread 3] Critical section done, previously next=2, now next=3 [Iteration 10, Thread 1] Got lock -[Iteration 10, Thread 1] Critical section done, previously next=2, now next=1 +[Iteration 10, Thread 1] Critical section done, previously next=3, now next=1 Iteration 10 completed PASSED :-) -Exiting @ tick 111594500 because target called exit() +Exiting @ tick 113941500 because target called exit() diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt index ea1876230..08b3d0977 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt @@ -1,958 +1,958 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000112 # Number of seconds simulated -sim_ticks 111594500 # Number of ticks simulated -final_tick 111594500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000114 # Number of seconds simulated +sim_ticks 113941500 # Number of ticks simulated +final_tick 113941500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 200629 # Simulator instruction rate (inst/s) -host_op_rate 200629 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 20568067 # Simulator tick rate (ticks/s) -host_mem_usage 235024 # Number of bytes of host memory used -host_seconds 5.43 # Real time elapsed on the host -sim_insts 1088531 # Number of instructions simulated -sim_ops 1088531 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu0.inst 23104 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 10816 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 5632 # Number of bytes read from this memory +host_inst_rate 130117 # Simulator instruction rate (inst/s) +host_op_rate 130117 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 13474596 # Simulator tick rate (ticks/s) +host_mem_usage 234988 # Number of bytes of host memory used +host_seconds 8.46 # Real time elapsed on the host +sim_insts 1100269 # Number of instructions simulated +sim_ops 1100269 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu0.inst 23232 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 10752 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 5376 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.data 1280 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 128 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 320 # Number of bytes read from this memory system.physmem.bytes_read::cpu2.data 832 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3.inst 256 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3.inst 384 # Number of bytes read from this memory system.physmem.bytes_read::cpu3.data 832 # Number of bytes read from this memory -system.physmem.bytes_read::total 42880 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 23104 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 5632 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 128 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu3.inst 256 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 29120 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu0.inst 361 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 169 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 88 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 43008 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 23232 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 5376 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 320 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu3.inst 384 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 29312 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu0.inst 363 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 168 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 84 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.data 20 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 2 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 5 # Number of read requests responded to by this memory system.physmem.num_reads::cpu2.data 13 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3.inst 4 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3.inst 6 # Number of read requests responded to by this memory system.physmem.num_reads::cpu3.data 13 # Number of read requests responded to by this memory -system.physmem.num_reads::total 670 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu0.inst 207035293 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 96922339 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 50468437 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 11470099 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 1147010 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 7455565 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.inst 2294020 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.data 7455565 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 384248328 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 207035293 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 50468437 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 1147010 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu3.inst 2294020 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 260944760 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 207035293 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 96922339 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 50468437 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 11470099 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 1147010 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 7455565 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.inst 2294020 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.data 7455565 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 384248328 # Total bandwidth to/from this memory (bytes/s) +system.physmem.num_reads::total 672 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu0.inst 203894104 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 94364213 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 47182107 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 11233835 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 2808459 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 7301993 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.inst 3370150 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.data 7301993 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 377456853 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 203894104 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 47182107 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 2808459 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu3.inst 3370150 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 257254819 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 203894104 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 94364213 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 47182107 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 11233835 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 2808459 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 7301993 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.inst 3370150 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.data 7301993 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 377456853 # Total bandwidth to/from this memory (bytes/s) system.cpu0.workload.num_syscalls 89 # Number of system calls -system.cpu0.numCycles 223190 # number of cpu cycles simulated +system.cpu0.numCycles 227884 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.BPredUnit.lookups 87370 # Number of BP lookups -system.cpu0.BPredUnit.condPredicted 85036 # Number of conditional branches predicted -system.cpu0.BPredUnit.condIncorrect 1313 # Number of conditional branches incorrect -system.cpu0.BPredUnit.BTBLookups 84895 # Number of BTB lookups -system.cpu0.BPredUnit.BTBHits 82517 # Number of BTB hits +system.cpu0.BPredUnit.lookups 88195 # Number of BP lookups +system.cpu0.BPredUnit.condPredicted 85894 # Number of conditional branches predicted +system.cpu0.BPredUnit.condIncorrect 1314 # Number of conditional branches incorrect +system.cpu0.BPredUnit.BTBLookups 85741 # Number of BTB lookups +system.cpu0.BPredUnit.BTBHits 83416 # Number of BTB hits system.cpu0.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.BPredUnit.usedRAS 514 # Number of times the RAS was used to get a target. +system.cpu0.BPredUnit.usedRAS 517 # Number of times the RAS was used to get a target. system.cpu0.BPredUnit.RASInCorrect 132 # Number of incorrect RAS predictions. -system.cpu0.fetch.icacheStallCycles 17415 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 518858 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 87370 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 83031 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 170328 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 4037 # Number of cycles fetch has spent squashing -system.cpu0.fetch.BlockedCycles 13330 # Number of cycles fetch has spent blocked +system.cpu0.fetch.icacheStallCycles 17885 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 523742 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 88195 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 83933 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 172058 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 4069 # Number of cycles fetch has spent squashing +system.cpu0.fetch.BlockedCycles 15014 # Number of cycles fetch has spent blocked system.cpu0.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 1404 # Number of stall cycles due to pending traps -system.cpu0.fetch.CacheLines 6152 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 508 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.rateDist::samples 205057 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 2.530311 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.210840 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.PendingTrapStallCycles 1439 # Number of stall cycles due to pending traps +system.cpu0.fetch.CacheLines 6122 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 517 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.rateDist::samples 209007 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 2.505859 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.211450 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 34729 16.94% 16.94% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 84380 41.15% 58.09% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 595 0.29% 58.38% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 973 0.47% 58.85% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 523 0.26% 59.11% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 80298 39.16% 98.26% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 656 0.32% 98.58% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 373 0.18% 98.77% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 2530 1.23% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 36949 17.68% 17.68% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 85270 40.80% 58.48% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 593 0.28% 58.76% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 1005 0.48% 59.24% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 500 0.24% 59.48% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 81190 38.85% 98.33% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 659 0.32% 98.64% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 361 0.17% 98.81% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 2480 1.19% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 205057 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.391460 # Number of branch fetches per cycle -system.cpu0.fetch.rate 2.324737 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 18107 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 14779 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 169274 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 322 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 2575 # Number of cycles decode is squashing -system.cpu0.decode.DecodedInsts 515764 # Number of instructions handled by decode -system.cpu0.rename.SquashCycles 2575 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 18814 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 1415 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 12654 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 168925 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 674 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 512400 # Number of instructions processed by rename -system.cpu0.rename.IQFullEvents 5 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LSQFullEvents 252 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.RenamedOperands 350257 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 1022076 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 1022076 # Number of integer rename lookups -system.cpu0.rename.CommittedMaps 336320 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 13937 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 921 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 951 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 4116 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 164196 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 82879 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 80125 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 79869 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 428350 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 958 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 425359 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 176 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 11411 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 10569 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 399 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 205057 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 2.074345 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.084750 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 209007 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.387017 # Number of branch fetches per cycle +system.cpu0.fetch.rate 2.298283 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 18552 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 16516 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 170985 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 348 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 2606 # Number of cycles decode is squashing +system.cpu0.decode.DecodedInsts 520718 # Number of instructions handled by decode +system.cpu0.rename.SquashCycles 2606 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 19281 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 2206 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 13583 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 170639 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 692 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 517471 # Number of instructions processed by rename +system.cpu0.rename.IQFullEvents 4 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LSQFullEvents 300 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.RenamedOperands 353567 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 1032190 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 1032190 # Number of integer rename lookups +system.cpu0.rename.CommittedMaps 339600 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 13967 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 909 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 933 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 4082 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 165924 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 83735 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 81055 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 80764 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 432543 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 950 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 429278 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 221 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 11501 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 11387 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 391 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 209007 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 2.053893 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.097042 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 33897 16.53% 16.53% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 5266 2.57% 19.10% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 81920 39.95% 59.05% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 81274 39.63% 98.68% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 1599 0.78% 99.46% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 693 0.34% 99.80% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 302 0.15% 99.95% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 90 0.04% 99.99% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 16 0.01% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 36203 17.32% 17.32% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 5360 2.56% 19.89% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 82686 39.56% 59.45% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 82056 39.26% 98.71% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 1635 0.78% 99.49% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 680 0.33% 99.81% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 282 0.13% 99.95% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 94 0.04% 99.99% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 11 0.01% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 205057 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 209007 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 54 22.69% 22.69% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 0 0.00% 22.69% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 22.69% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 22.69% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 22.69% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 22.69% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 22.69% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 22.69% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 22.69% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 22.69% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 22.69% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 22.69% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 22.69% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 22.69% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 22.69% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 22.69% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 22.69% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 22.69% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 22.69% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 22.69% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 22.69% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 22.69% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 22.69% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 22.69% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 22.69% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 22.69% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 22.69% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 22.69% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 22.69% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 72 30.25% 52.94% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 112 47.06% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 43 16.23% 16.23% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 0 0.00% 16.23% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 16.23% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 16.23% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 16.23% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 16.23% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 16.23% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 16.23% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 16.23% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 16.23% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 16.23% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 16.23% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 16.23% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 16.23% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 16.23% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 16.23% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 16.23% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 16.23% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 16.23% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 16.23% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 16.23% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 16.23% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 16.23% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 16.23% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 16.23% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 16.23% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 16.23% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 16.23% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 16.23% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 110 41.51% 57.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 112 42.26% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 179447 42.19% 42.19% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 0 0.00% 42.19% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 42.19% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 42.19% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 42.19% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 42.19% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 42.19% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 42.19% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 42.19% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 42.19% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 42.19% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 42.19% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 42.19% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 42.19% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 42.19% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 42.19% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 42.19% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 42.19% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 42.19% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 42.19% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.19% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.19% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.19% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.19% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.19% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 42.19% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 42.19% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 42.19% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.19% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 163633 38.47% 80.66% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 82279 19.34% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 180966 42.16% 42.16% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 0 0.00% 42.16% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 42.16% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 42.16% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 42.16% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 42.16% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 42.16% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 42.16% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 42.16% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 42.16% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 42.16% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 42.16% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 42.16% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 42.16% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 42.16% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 42.16% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 42.16% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 42.16% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 42.16% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 42.16% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.16% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.16% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.16% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.16% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.16% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 42.16% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 42.16% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 42.16% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.16% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 165240 38.49% 80.65% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 83072 19.35% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 425359 # Type of FU issued -system.cpu0.iq.rate 1.905816 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 238 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.000560 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 1056189 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 440777 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 423418 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.FU_type_0::total 429278 # Type of FU issued +system.cpu0.iq.rate 1.883757 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 265 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.000617 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 1068049 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 445050 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 427325 # Number of integer instruction queue wakeup accesses system.cpu0.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu0.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu0.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 425597 # Number of integer alu accesses +system.cpu0.iq.int_alu_accesses 429543 # Number of integer alu accesses system.cpu0.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 79599 # Number of loads that had data forwarded from stores +system.cpu0.iew.lsq.thread0.forwLoads 80408 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 2452 # Number of loads squashed +system.cpu0.iew.lsq.thread0.squashedLoads 2540 # Number of loads squashed system.cpu0.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 58 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 1501 # Number of stores squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 56 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 1537 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu0.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 16 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.cacheBlocked 8 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 2575 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 1020 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 41 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 509980 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 329 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 164196 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 82879 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 846 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 43 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewSquashCycles 2606 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 1701 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 86 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 515038 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 368 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 165924 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 83735 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 837 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 90 # Number of times the IQ has become full, causing a stall system.cpu0.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 58 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 368 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 1157 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 1525 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 424238 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 163317 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 1121 # Number of squashed instructions skipped in execute +system.cpu0.iew.memOrderViolationEvents 56 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 370 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 1149 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 1519 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 428170 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 164921 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 1108 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 80672 # number of nop insts executed -system.cpu0.iew.exec_refs 245449 # number of memory reference insts executed -system.cpu0.iew.exec_branches 84313 # Number of branches executed -system.cpu0.iew.exec_stores 82132 # Number of stores executed -system.cpu0.iew.exec_rate 1.900793 # Inst execution rate -system.cpu0.iew.wb_sent 423777 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 423418 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 250898 # num instructions producing a value -system.cpu0.iew.wb_consumers 253433 # num instructions consuming a value +system.cpu0.iew.exec_nop 81545 # number of nop insts executed +system.cpu0.iew.exec_refs 247840 # number of memory reference insts executed +system.cpu0.iew.exec_branches 85100 # Number of branches executed +system.cpu0.iew.exec_stores 82919 # Number of stores executed +system.cpu0.iew.exec_rate 1.878895 # Inst execution rate +system.cpu0.iew.wb_sent 427676 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 427325 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 253224 # num instructions producing a value +system.cpu0.iew.wb_consumers 255650 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 1.897119 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.989997 # average fanout of values written-back +system.cpu0.iew.wb_rate 1.875186 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.990510 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitCommittedInsts 496825 # The number of committed instructions -system.cpu0.commit.commitCommittedOps 496825 # The number of committed instructions -system.cpu0.commit.commitSquashedInsts 13135 # The number of squashed insts skipped by commit +system.cpu0.commit.commitCommittedInsts 501745 # The number of committed instructions +system.cpu0.commit.commitCommittedOps 501745 # The number of committed instructions +system.cpu0.commit.commitSquashedInsts 13260 # The number of squashed insts skipped by commit system.cpu0.commit.commitNonSpecStalls 559 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 1313 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 202499 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 2.453469 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 2.133222 # Number of insts commited each cycle +system.cpu0.commit.branchMispredicts 1314 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 206418 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 2.430723 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 2.136815 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 34446 17.01% 17.01% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 84010 41.49% 58.50% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 2422 1.20% 59.69% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 711 0.35% 60.04% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 562 0.28% 60.32% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 79343 39.18% 99.50% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 465 0.23% 99.73% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 235 0.12% 99.85% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 305 0.15% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 36760 17.81% 17.81% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 84779 41.07% 58.88% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 2446 1.18% 60.07% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 715 0.35% 60.41% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 578 0.28% 60.69% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 80055 38.78% 99.47% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 554 0.27% 99.74% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 230 0.11% 99.85% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 301 0.15% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 202499 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 496825 # Number of instructions committed -system.cpu0.commit.committedOps 496825 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 206418 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 501745 # Number of instructions committed +system.cpu0.commit.committedOps 501745 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 243122 # Number of memory references committed -system.cpu0.commit.loads 161744 # Number of loads committed +system.cpu0.commit.refs 245582 # Number of memory references committed +system.cpu0.commit.loads 163384 # Number of loads committed system.cpu0.commit.membars 84 # Number of memory barriers committed -system.cpu0.commit.branches 83266 # Number of branches committed +system.cpu0.commit.branches 84086 # Number of branches committed system.cpu0.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 334650 # Number of committed integer instructions. +system.cpu0.commit.int_insts 337930 # Number of committed integer instructions. system.cpu0.commit.function_calls 223 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 305 # number cycles where commit BW limit reached +system.cpu0.commit.bw_lim_events 301 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 710993 # The number of ROB reads -system.cpu0.rob.rob_writes 1022511 # The number of ROB writes -system.cpu0.timesIdled 324 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 18133 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.committedInsts 416744 # Number of Instructions Simulated -system.cpu0.committedOps 416744 # Number of Ops (including micro ops) Simulated -system.cpu0.committedInsts_total 416744 # Number of Instructions Simulated -system.cpu0.cpi 0.535557 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 0.535557 # CPI: Total CPI of All Threads -system.cpu0.ipc 1.867216 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 1.867216 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 758967 # number of integer regfile reads -system.cpu0.int_regfile_writes 341941 # number of integer regfile writes +system.cpu0.rob.rob_reads 719961 # The number of ROB reads +system.cpu0.rob.rob_writes 1032633 # The number of ROB writes +system.cpu0.timesIdled 343 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 18877 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.committedInsts 420844 # Number of Instructions Simulated +system.cpu0.committedOps 420844 # Number of Ops (including micro ops) Simulated +system.cpu0.committedInsts_total 420844 # Number of Instructions Simulated +system.cpu0.cpi 0.541493 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 0.541493 # CPI: Total CPI of All Threads +system.cpu0.ipc 1.846747 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 1.846747 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 766075 # number of integer regfile reads +system.cpu0.int_regfile_writes 345063 # number of integer regfile writes system.cpu0.fp_regfile_reads 192 # number of floating regfile reads -system.cpu0.misc_regfile_reads 247293 # number of misc regfile reads +system.cpu0.misc_regfile_reads 249668 # number of misc regfile reads system.cpu0.misc_regfile_writes 564 # number of misc regfile writes -system.cpu0.icache.replacements 307 # number of replacements -system.cpu0.icache.tagsinuse 248.147409 # Cycle average of tags in use -system.cpu0.icache.total_refs 5393 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 598 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 9.018395 # Average number of references to valid blocks. +system.cpu0.icache.replacements 308 # number of replacements +system.cpu0.icache.tagsinuse 248.197747 # Cycle average of tags in use +system.cpu0.icache.total_refs 5361 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 601 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 8.920133 # Average number of references to valid blocks. system.cpu0.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 248.147409 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.484663 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.484663 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 5393 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 5393 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 5393 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 5393 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 5393 # number of overall hits -system.cpu0.icache.overall_hits::total 5393 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 759 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 759 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 759 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 759 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 759 # number of overall misses -system.cpu0.icache.overall_misses::total 759 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 28913000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 28913000 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 28913000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 28913000 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 28913000 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 28913000 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 6152 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 6152 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 6152 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 6152 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 6152 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 6152 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.123375 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.123375 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.123375 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.123375 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.123375 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.123375 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 38093.544137 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 38093.544137 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 38093.544137 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 38093.544137 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 38093.544137 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 38093.544137 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 15500 # number of cycles access was blocked +system.cpu0.icache.occ_blocks::cpu0.inst 248.197747 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.484761 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.484761 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 5361 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 5361 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 5361 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 5361 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 5361 # number of overall hits +system.cpu0.icache.overall_hits::total 5361 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 761 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 761 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 761 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 761 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 761 # number of overall misses +system.cpu0.icache.overall_misses::total 761 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 29540500 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 29540500 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 29540500 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 29540500 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 29540500 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 29540500 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 6122 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 6122 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 6122 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 6122 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 6122 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 6122 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.124306 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.124306 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.124306 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.124306 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.124306 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.124306 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 38818.002628 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 38818.002628 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 38818.002628 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 38818.002628 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 38818.002628 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 38818.002628 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 13500 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 1 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 15500 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 13500 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 160 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 160 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 160 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 160 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 160 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 160 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 599 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 599 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 599 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 599 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 599 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 599 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 21855500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 21855500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 21855500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 21855500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 21855500 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 21855500 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.097367 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.097367 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.097367 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.097367 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.097367 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.097367 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 36486.644407 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 36486.644407 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 36486.644407 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 36486.644407 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 36486.644407 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 36486.644407 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 159 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 159 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 159 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 159 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 159 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 159 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 602 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 602 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 602 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 602 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 602 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 602 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 22436000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 22436000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 22436000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 22436000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 22436000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 22436000 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.098334 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.098334 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.098334 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.098334 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.098334 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.098334 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 37269.102990 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 37269.102990 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 37269.102990 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 37269.102990 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 37269.102990 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 37269.102990 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.dcache.replacements 2 # number of replacements -system.cpu0.dcache.tagsinuse 144.541703 # Cycle average of tags in use -system.cpu0.dcache.total_refs 163878 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 171 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 958.350877 # Average number of references to valid blocks. +system.cpu0.dcache.tagsinuse 144.386808 # Cycle average of tags in use +system.cpu0.dcache.total_refs 165433 # Total number of references to valid blocks. +system.cpu0.dcache.sampled_refs 170 # Sample count of references to valid blocks. +system.cpu0.dcache.avg_refs 973.135294 # Average number of references to valid blocks. system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 144.541703 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.282308 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.282308 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 83150 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 83150 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 80790 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 80790 # number of WriteReq hits -system.cpu0.dcache.SwapReq_hits::cpu0.data 21 # number of SwapReq hits -system.cpu0.dcache.SwapReq_hits::total 21 # number of SwapReq hits -system.cpu0.dcache.demand_hits::cpu0.data 163940 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 163940 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 163940 # number of overall hits -system.cpu0.dcache.overall_hits::total 163940 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 500 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 500 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 546 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 546 # number of WriteReq misses -system.cpu0.dcache.SwapReq_misses::cpu0.data 21 # number of SwapReq misses -system.cpu0.dcache.SwapReq_misses::total 21 # number of SwapReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1046 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1046 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1046 # number of overall misses -system.cpu0.dcache.overall_misses::total 1046 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 13780500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 13780500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 24368986 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 24368986 # number of WriteReq miss cycles -system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 390500 # number of SwapReq miss cycles -system.cpu0.dcache.SwapReq_miss_latency::total 390500 # number of SwapReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 38149486 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 38149486 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 38149486 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 38149486 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 83650 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 83650 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 81336 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 81336 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.occ_blocks::cpu0.data 144.386808 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.282005 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::total 0.282005 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 83919 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 83919 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 81593 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 81593 # number of WriteReq hits +system.cpu0.dcache.SwapReq_hits::cpu0.data 18 # number of SwapReq hits +system.cpu0.dcache.SwapReq_hits::total 18 # number of SwapReq hits +system.cpu0.dcache.demand_hits::cpu0.data 165512 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 165512 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 165512 # number of overall hits +system.cpu0.dcache.overall_hits::total 165512 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 525 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 525 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 563 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 563 # number of WriteReq misses +system.cpu0.dcache.SwapReq_misses::cpu0.data 24 # number of SwapReq misses +system.cpu0.dcache.SwapReq_misses::total 24 # number of SwapReq misses +system.cpu0.dcache.demand_misses::cpu0.data 1088 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1088 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1088 # number of overall misses +system.cpu0.dcache.overall_misses::total 1088 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 16325500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 16325500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 28838494 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 28838494 # number of WriteReq miss cycles +system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 480000 # number of SwapReq miss cycles +system.cpu0.dcache.SwapReq_miss_latency::total 480000 # number of SwapReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 45163994 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 45163994 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 45163994 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 45163994 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 84444 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 84444 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 82156 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 82156 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses) system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 164986 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 164986 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 164986 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 164986 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.005977 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.005977 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.006713 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.006713 # miss rate for WriteReq accesses -system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.500000 # miss rate for SwapReq accesses -system.cpu0.dcache.SwapReq_miss_rate::total 0.500000 # miss rate for SwapReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.006340 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.006340 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.006340 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.006340 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 27561 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 27561 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 44631.842491 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 44631.842491 # average WriteReq miss latency -system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 18595.238095 # average SwapReq miss latency -system.cpu0.dcache.SwapReq_avg_miss_latency::total 18595.238095 # average SwapReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 36471.783939 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 36471.783939 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 36471.783939 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 36471.783939 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 194000 # number of cycles access was blocked +system.cpu0.dcache.demand_accesses::cpu0.data 166600 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 166600 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 166600 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 166600 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.006217 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.006217 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.006853 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.006853 # miss rate for WriteReq accesses +system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.571429 # miss rate for SwapReq accesses +system.cpu0.dcache.SwapReq_miss_rate::total 0.571429 # miss rate for SwapReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.006531 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.006531 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.006531 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.006531 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 31096.190476 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 31096.190476 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 51222.902309 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 51222.902309 # average WriteReq miss latency +system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 20000 # average SwapReq miss latency +system.cpu0.dcache.SwapReq_avg_miss_latency::total 20000 # average SwapReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 41511.023897 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 41511.023897 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 41511.023897 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 41511.023897 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 119500 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 19 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 18 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 10210.526316 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 6638.888889 # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed system.cpu0.dcache.writebacks::writebacks 1 # number of writebacks system.cpu0.dcache.writebacks::total 1 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 320 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 320 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 371 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 371 # number of WriteReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 691 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 691 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 691 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 691 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 345 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 345 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 392 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 392 # number of WriteReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 737 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 737 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 737 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 737 # number of overall MSHR hits system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 180 # number of ReadReq MSHR misses system.cpu0.dcache.ReadReq_mshr_misses::total 180 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 175 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 175 # number of WriteReq MSHR misses -system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data 21 # number of SwapReq MSHR misses -system.cpu0.dcache.SwapReq_mshr_misses::total 21 # number of SwapReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 355 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 355 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 355 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 355 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4933000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4933000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6275500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6275500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 327500 # number of SwapReq MSHR miss cycles -system.cpu0.dcache.SwapReq_mshr_miss_latency::total 327500 # number of SwapReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 11208500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 11208500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 11208500 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 11208500 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.002152 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.002152 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.002152 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.002152 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.500000 # mshr miss rate for SwapReq accesses -system.cpu0.dcache.SwapReq_mshr_miss_rate::total 0.500000 # mshr miss rate for SwapReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.002152 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.002152 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.002152 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.002152 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 27405.555556 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 27405.555556 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 35860 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 35860 # average WriteReq mshr miss latency -system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 15595.238095 # average SwapReq mshr miss latency -system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 15595.238095 # average SwapReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 31573.239437 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 31573.239437 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 31573.239437 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 31573.239437 # average overall mshr miss latency +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 171 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 171 # number of WriteReq MSHR misses +system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data 24 # number of SwapReq MSHR misses +system.cpu0.dcache.SwapReq_mshr_misses::total 24 # number of SwapReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 351 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 351 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 351 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 351 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 5693511 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5693511 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6731000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6731000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 405000 # number of SwapReq MSHR miss cycles +system.cpu0.dcache.SwapReq_mshr_miss_latency::total 405000 # number of SwapReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 12424511 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 12424511 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 12424511 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 12424511 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.002132 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.002132 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.002081 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.002081 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.571429 # mshr miss rate for SwapReq accesses +system.cpu0.dcache.SwapReq_mshr_miss_rate::total 0.571429 # mshr miss rate for SwapReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.002107 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.002107 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.002107 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.002107 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 31630.616667 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 31630.616667 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 39362.573099 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 39362.573099 # average WriteReq mshr miss latency +system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 16875 # average SwapReq mshr miss latency +system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 16875 # average SwapReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 35397.467236 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 35397.467236 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 35397.467236 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 35397.467236 # average overall mshr miss latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.numCycles 187839 # number of cpu cycles simulated +system.cpu1.numCycles 191339 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.BPredUnit.lookups 50940 # Number of BP lookups -system.cpu1.BPredUnit.condPredicted 47890 # Number of conditional branches predicted -system.cpu1.BPredUnit.condIncorrect 1510 # Number of conditional branches incorrect -system.cpu1.BPredUnit.BTBLookups 44289 # Number of BTB lookups -system.cpu1.BPredUnit.BTBHits 43310 # Number of BTB hits +system.cpu1.BPredUnit.lookups 49631 # Number of BP lookups +system.cpu1.BPredUnit.condPredicted 46572 # Number of conditional branches predicted +system.cpu1.BPredUnit.condIncorrect 1528 # Number of conditional branches incorrect +system.cpu1.BPredUnit.BTBLookups 42950 # Number of BTB lookups +system.cpu1.BPredUnit.BTBHits 41997 # Number of BTB hits system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.BPredUnit.usedRAS 829 # Number of times the RAS was used to get a target. +system.cpu1.BPredUnit.usedRAS 805 # Number of times the RAS was used to get a target. system.cpu1.BPredUnit.RASInCorrect 232 # Number of incorrect RAS predictions. -system.cpu1.fetch.icacheStallCycles 31688 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 280910 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 50940 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 44139 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 100869 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 4392 # Number of cycles fetch has spent squashing -system.cpu1.fetch.BlockedCycles 39081 # Number of cycles fetch has spent blocked +system.cpu1.fetch.icacheStallCycles 33375 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 271825 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 49631 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 42802 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 98758 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 4453 # Number of cycles fetch has spent squashing +system.cpu1.fetch.BlockedCycles 42292 # Number of cycles fetch has spent blocked system.cpu1.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.NoActiveThreadStallCycles 6575 # Number of stall cycles due to no active thread to fetch from -system.cpu1.fetch.PendingTrapStallCycles 1045 # Number of stall cycles due to pending traps -system.cpu1.fetch.CacheLines 22757 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 318 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.rateDist::samples 182067 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 1.542894 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.098462 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.NoActiveThreadStallCycles 6725 # Number of stall cycles due to no active thread to fetch from +system.cpu1.fetch.PendingTrapStallCycles 1070 # Number of stall cycles due to pending traps +system.cpu1.fetch.CacheLines 23889 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 317 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.rateDist::samples 185079 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 1.468697 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.066601 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 81198 44.60% 44.60% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 51887 28.50% 73.10% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 7438 4.09% 77.18% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 3280 1.80% 78.98% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 684 0.38% 79.36% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 31924 17.53% 96.89% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 1209 0.66% 97.56% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 879 0.48% 98.04% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 3568 1.96% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 86321 46.64% 46.64% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 51121 27.62% 74.26% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 7925 4.28% 78.54% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 3336 1.80% 80.35% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 734 0.40% 80.74% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 30013 16.22% 96.96% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 1151 0.62% 97.58% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 885 0.48% 98.06% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 3593 1.94% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 182067 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.271190 # Number of branch fetches per cycle -system.cpu1.fetch.rate 1.495483 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 38413 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 34373 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 93637 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 6265 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 2804 # Number of cycles decode is squashing -system.cpu1.decode.DecodedInsts 276803 # Number of instructions handled by decode -system.cpu1.rename.SquashCycles 2804 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 39183 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 19194 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 14318 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 87661 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 12332 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 274424 # Number of instructions processed by rename -system.cpu1.rename.IQFullEvents 18 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 52 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.RenamedOperands 191179 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 520245 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 520245 # Number of integer rename lookups -system.cpu1.rename.CommittedMaps 175779 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 15400 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 1221 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 1348 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 15085 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 76182 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 35431 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 36807 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 30214 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 225638 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 7711 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 228522 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 80 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 12774 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 11561 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 762 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 182067 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 1.255153 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.306407 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 185079 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.259388 # Number of branch fetches per cycle +system.cpu1.fetch.rate 1.420646 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 40472 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 37211 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 91012 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 6805 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 2854 # Number of cycles decode is squashing +system.cpu1.decode.DecodedInsts 267804 # Number of instructions handled by decode +system.cpu1.rename.SquashCycles 2854 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 41302 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 21637 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 14674 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 84497 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 13390 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 265308 # Number of instructions processed by rename +system.cpu1.rename.IQFullEvents 16 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LSQFullEvents 60 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.RenamedOperands 184298 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 499771 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 499771 # Number of integer rename lookups +system.cpu1.rename.CommittedMaps 168579 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 15719 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 1236 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 1367 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 16177 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 72909 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 33507 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 35450 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 28267 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 217311 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 8226 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 220400 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 173 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 13138 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 12222 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 799 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 185079 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 1.190843 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.296813 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 78861 43.31% 43.31% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 26436 14.52% 57.83% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 35607 19.56% 77.39% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 36159 19.86% 97.25% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 3279 1.80% 99.05% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 1252 0.69% 99.74% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 353 0.19% 99.93% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 59 0.03% 99.97% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 84217 45.50% 45.50% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 27917 15.08% 60.59% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 33688 18.20% 78.79% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 34243 18.50% 97.29% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 3324 1.80% 99.09% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 1232 0.67% 99.75% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 345 0.19% 99.94% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 52 0.03% 99.97% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::8 61 0.03% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 182067 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 185079 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 20 6.62% 6.62% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 0 0.00% 6.62% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 6.62% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 6.62% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 6.62% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 6.62% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 6.62% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 6.62% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 6.62% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 6.62% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 6.62% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 6.62% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 6.62% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 6.62% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 6.62% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 6.62% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 6.62% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 6.62% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 6.62% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 6.62% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 6.62% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 6.62% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 6.62% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 6.62% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 6.62% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 6.62% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 6.62% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.62% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 6.62% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 72 23.84% 30.46% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 210 69.54% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 21 6.60% 6.60% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 0 0.00% 6.60% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 6.60% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 6.60% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 6.60% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 6.60% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 6.60% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 6.60% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 6.60% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 6.60% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 6.60% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 6.60% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 6.60% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 6.60% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 6.60% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 6.60% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 6.60% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 6.60% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 6.60% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 6.60% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 6.60% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 6.60% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 6.60% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 6.60% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 6.60% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 6.60% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 6.60% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.60% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 6.60% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 87 27.36% 33.96% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 210 66.04% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 112122 49.06% 49.06% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 0 0.00% 49.06% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 49.06% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 49.06% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 49.06% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 49.06% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 49.06% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 49.06% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 49.06% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 49.06% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 49.06% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 49.06% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 49.06% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 49.06% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 49.06% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 49.06% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 49.06% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 49.06% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.06% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 49.06% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.06% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.06% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.06% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.06% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.06% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.06% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 49.06% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.06% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.06% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 81642 35.73% 84.79% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 34758 15.21% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 108844 49.38% 49.38% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 0 0.00% 49.38% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 49.38% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 49.38% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 49.38% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 49.38% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 49.38% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 49.38% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 49.38% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 49.38% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 49.38% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 49.38% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 49.38% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 49.38% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 49.38% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 49.38% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 49.38% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 49.38% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.38% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 49.38% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.38% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.38% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.38% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.38% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.38% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.38% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 49.38% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.38% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.38% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 78735 35.72% 85.11% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 32821 14.89% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 228522 # Type of FU issued -system.cpu1.iq.rate 1.216584 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 302 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.001322 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 639493 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 246163 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 226488 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.FU_type_0::total 220400 # Type of FU issued +system.cpu1.iq.rate 1.151882 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 318 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.001443 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 626370 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 238714 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 218326 # Number of integer instruction queue wakeup accesses system.cpu1.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu1.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu1.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 228824 # Number of integer alu accesses +system.cpu1.iq.int_alu_accesses 220718 # Number of integer alu accesses system.cpu1.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 30049 # Number of loads that had data forwarded from stores +system.cpu1.iew.lsq.thread0.forwLoads 28122 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 2733 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 6 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 40 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 1566 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 2824 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 8 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 39 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 1558 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu1.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu1.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 2804 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 1582 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 60 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 271136 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 377 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 76182 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 35431 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 1144 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 55 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewSquashCycles 2854 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 2376 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 88 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 261974 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 434 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 72909 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 33507 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 1131 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 89 # Number of times the IQ has become full, causing a stall system.cpu1.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 40 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 494 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 1182 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 1676 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 227186 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 75112 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 1336 # Number of squashed instructions skipped in execute +system.cpu1.iew.memOrderViolationEvents 39 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 510 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 1187 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 1697 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 219051 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 71704 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 1349 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 37787 # number of nop insts executed -system.cpu1.iew.exec_refs 109780 # number of memory reference insts executed -system.cpu1.iew.exec_branches 47145 # Number of branches executed -system.cpu1.iew.exec_stores 34668 # Number of stores executed -system.cpu1.iew.exec_rate 1.209472 # Inst execution rate -system.cpu1.iew.wb_sent 226789 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 226488 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 126631 # num instructions producing a value -system.cpu1.iew.wb_consumers 131515 # num instructions consuming a value +system.cpu1.iew.exec_nop 36437 # number of nop insts executed +system.cpu1.iew.exec_refs 104435 # number of memory reference insts executed +system.cpu1.iew.exec_branches 45735 # Number of branches executed +system.cpu1.iew.exec_stores 32731 # Number of stores executed +system.cpu1.iew.exec_rate 1.144832 # Inst execution rate +system.cpu1.iew.wb_sent 218612 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 218326 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 121254 # num instructions producing a value +system.cpu1.iew.wb_consumers 126110 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 1.205756 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.962864 # average fanout of values written-back +system.cpu1.iew.wb_rate 1.141043 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.961494 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitCommittedInsts 256347 # The number of committed instructions -system.cpu1.commit.commitCommittedOps 256347 # The number of committed instructions -system.cpu1.commit.commitSquashedInsts 14788 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 6949 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 1510 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 172689 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 1.484443 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.966336 # Number of insts commited each cycle +system.cpu1.commit.commitCommittedInsts 246738 # The number of committed instructions +system.cpu1.commit.commitCommittedOps 246738 # The number of committed instructions +system.cpu1.commit.commitSquashedInsts 15223 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 7427 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 1528 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 175501 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 1.405907 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.932846 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 79222 45.88% 45.88% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 45065 26.10% 71.97% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 6173 3.57% 75.55% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 7849 4.55% 80.09% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 1517 0.88% 80.97% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 30495 17.66% 98.63% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 550 0.32% 98.95% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 998 0.58% 99.53% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 820 0.47% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 84843 48.34% 48.34% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 43671 24.88% 73.23% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 6232 3.55% 76.78% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 8331 4.75% 81.52% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 1551 0.88% 82.41% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 28453 16.21% 98.62% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 613 0.35% 98.97% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 993 0.57% 99.54% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 814 0.46% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 172689 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 256347 # Number of instructions committed -system.cpu1.commit.committedOps 256347 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 175501 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 246738 # Number of instructions committed +system.cpu1.commit.committedOps 246738 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 107314 # Number of memory references committed -system.cpu1.commit.loads 73449 # Number of loads committed -system.cpu1.commit.membars 6235 # Number of memory barriers committed -system.cpu1.commit.branches 46061 # Number of branches committed +system.cpu1.commit.refs 102034 # Number of memory references committed +system.cpu1.commit.loads 70085 # Number of loads committed +system.cpu1.commit.membars 6711 # Number of memory barriers committed +system.cpu1.commit.branches 44619 # Number of branches committed system.cpu1.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 175498 # Number of committed integer instructions. +system.cpu1.commit.int_insts 168775 # Number of committed integer instructions. system.cpu1.commit.function_calls 322 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 820 # number cycles where commit BW limit reached +system.cpu1.commit.bw_lim_events 814 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 442417 # The number of ROB reads -system.cpu1.rob.rob_writes 545088 # The number of ROB writes -system.cpu1.timesIdled 232 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 5772 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 35349 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 213261 # Number of Instructions Simulated -system.cpu1.committedOps 213261 # Number of Ops (including micro ops) Simulated -system.cpu1.committedInsts_total 213261 # Number of Instructions Simulated -system.cpu1.cpi 0.880794 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 0.880794 # CPI: Total CPI of All Threads -system.cpu1.ipc 1.135339 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 1.135339 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 389025 # number of integer regfile reads -system.cpu1.int_regfile_writes 181950 # number of integer regfile writes +system.cpu1.rob.rob_reads 436061 # The number of ROB reads +system.cpu1.rob.rob_writes 526790 # The number of ROB writes +system.cpu1.timesIdled 250 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 6260 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 36543 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 204620 # Number of Instructions Simulated +system.cpu1.committedOps 204620 # Number of Ops (including micro ops) Simulated +system.cpu1.committedInsts_total 204620 # Number of Instructions Simulated +system.cpu1.cpi 0.935094 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 0.935094 # CPI: Total CPI of All Threads +system.cpu1.ipc 1.069411 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 1.069411 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 373202 # number of integer regfile reads +system.cpu1.int_regfile_writes 174771 # number of integer regfile writes system.cpu1.fp_regfile_writes 64 # number of floating regfile writes -system.cpu1.misc_regfile_reads 111436 # number of misc regfile reads +system.cpu1.misc_regfile_reads 106146 # number of misc regfile reads system.cpu1.misc_regfile_writes 646 # number of misc regfile writes -system.cpu1.icache.replacements 321 # number of replacements -system.cpu1.icache.tagsinuse 92.166456 # Cycle average of tags in use -system.cpu1.icache.total_refs 22247 # Total number of references to valid blocks. +system.cpu1.icache.replacements 322 # number of replacements +system.cpu1.icache.tagsinuse 90.902674 # Cycle average of tags in use +system.cpu1.icache.total_refs 23372 # Total number of references to valid blocks. system.cpu1.icache.sampled_refs 436 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 51.025229 # Average number of references to valid blocks. +system.cpu1.icache.avg_refs 53.605505 # Average number of references to valid blocks. system.cpu1.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 92.166456 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.180013 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.180013 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 22247 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 22247 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 22247 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 22247 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 22247 # number of overall hits -system.cpu1.icache.overall_hits::total 22247 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 510 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 510 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 510 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 510 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 510 # number of overall misses -system.cpu1.icache.overall_misses::total 510 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 11347500 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 11347500 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 11347500 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 11347500 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 11347500 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 11347500 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 22757 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 22757 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 22757 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 22757 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 22757 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 22757 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.022411 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.022411 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.022411 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.022411 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.022411 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.022411 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 22250 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 22250 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 22250 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 22250 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 22250 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 22250 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 33000 # number of cycles access was blocked +system.cpu1.icache.occ_blocks::cpu1.inst 90.902674 # Average occupied blocks per requestor +system.cpu1.icache.occ_percent::cpu1.inst 0.177544 # Average percentage of cache occupancy +system.cpu1.icache.occ_percent::total 0.177544 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 23372 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 23372 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 23372 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 23372 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 23372 # number of overall hits +system.cpu1.icache.overall_hits::total 23372 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 517 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 517 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 517 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 517 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 517 # number of overall misses +system.cpu1.icache.overall_misses::total 517 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 11874500 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 11874500 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 11874500 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 11874500 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 11874500 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 11874500 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 23889 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 23889 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 23889 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 23889 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 23889 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 23889 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.021642 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.021642 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.021642 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.021642 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.021642 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.021642 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 22968.085106 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 22968.085106 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 22968.085106 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 22968.085106 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 22968.085106 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 22968.085106 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 32000 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 1 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 33000 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 32000 # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 74 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 74 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 74 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 74 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 74 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 74 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 81 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 81 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 81 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 81 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 81 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 81 # number of overall MSHR hits system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 436 # number of ReadReq MSHR misses system.cpu1.icache.ReadReq_mshr_misses::total 436 # number of ReadReq MSHR misses system.cpu1.icache.demand_mshr_misses::cpu1.inst 436 # number of demand (read+write) MSHR misses system.cpu1.icache.demand_mshr_misses::total 436 # number of demand (read+write) MSHR misses system.cpu1.icache.overall_mshr_misses::cpu1.inst 436 # number of overall MSHR misses system.cpu1.icache.overall_mshr_misses::total 436 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 8591500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 8591500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 8591500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 8591500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 8591500 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 8591500 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.019159 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.019159 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.019159 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.019159 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.019159 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.019159 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 19705.275229 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 19705.275229 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 19705.275229 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 19705.275229 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 19705.275229 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 19705.275229 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 8863000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 8863000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 8863000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 8863000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 8863000 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 8863000 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.018251 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.018251 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.018251 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.018251 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.018251 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.018251 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 20327.981651 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 20327.981651 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 20327.981651 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 20327.981651 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 20327.981651 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 20327.981651 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dcache.replacements 0 # number of replacements -system.cpu1.dcache.tagsinuse 27.650583 # Cycle average of tags in use -system.cpu1.dcache.total_refs 40148 # Total number of references to valid blocks. +system.cpu1.dcache.tagsinuse 27.508331 # Cycle average of tags in use +system.cpu1.dcache.total_refs 38240 # Total number of references to valid blocks. system.cpu1.dcache.sampled_refs 29 # Sample count of references to valid blocks. -system.cpu1.dcache.avg_refs 1384.413793 # Average number of references to valid blocks. +system.cpu1.dcache.avg_refs 1318.620690 # Average number of references to valid blocks. system.cpu1.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::cpu1.data 27.650583 # Average occupied blocks per requestor -system.cpu1.dcache.occ_percent::cpu1.data 0.054005 # Average percentage of cache occupancy -system.cpu1.dcache.occ_percent::total 0.054005 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::cpu1.data 44622 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 44622 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 33643 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 33643 # number of WriteReq hits -system.cpu1.dcache.SwapReq_hits::cpu1.data 16 # number of SwapReq hits -system.cpu1.dcache.SwapReq_hits::total 16 # number of SwapReq hits -system.cpu1.dcache.demand_hits::cpu1.data 78265 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 78265 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 78265 # number of overall hits -system.cpu1.dcache.overall_hits::total 78265 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 425 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 425 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 154 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 154 # number of WriteReq misses -system.cpu1.dcache.SwapReq_misses::cpu1.data 52 # number of SwapReq misses -system.cpu1.dcache.SwapReq_misses::total 52 # number of SwapReq misses -system.cpu1.dcache.demand_misses::cpu1.data 579 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 579 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 579 # number of overall misses -system.cpu1.dcache.overall_misses::total 579 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 9294500 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 9294500 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 3142500 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 3142500 # number of WriteReq miss cycles -system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 1219000 # number of SwapReq miss cycles -system.cpu1.dcache.SwapReq_miss_latency::total 1219000 # number of SwapReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 12437000 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 12437000 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 12437000 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 12437000 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 45047 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 45047 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 33797 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 33797 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SwapReq_accesses::cpu1.data 68 # number of SwapReq accesses(hits+misses) -system.cpu1.dcache.SwapReq_accesses::total 68 # number of SwapReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 78844 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 78844 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 78844 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 78844 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.009435 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.009435 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.004557 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.004557 # miss rate for WriteReq accesses -system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.764706 # miss rate for SwapReq accesses -system.cpu1.dcache.SwapReq_miss_rate::total 0.764706 # miss rate for SwapReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.007344 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.007344 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.007344 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.007344 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 21869.411765 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 21869.411765 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 20405.844156 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 20405.844156 # average WriteReq miss latency -system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 23442.307692 # average SwapReq miss latency -system.cpu1.dcache.SwapReq_avg_miss_latency::total 23442.307692 # average SwapReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 21480.138169 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 21480.138169 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 21480.138169 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 21480.138169 # average overall miss latency +system.cpu1.dcache.occ_blocks::cpu1.data 27.508331 # Average occupied blocks per requestor +system.cpu1.dcache.occ_percent::cpu1.data 0.053727 # Average percentage of cache occupancy +system.cpu1.dcache.occ_percent::total 0.053727 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::cpu1.data 43171 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 43171 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 31745 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 31745 # number of WriteReq hits +system.cpu1.dcache.SwapReq_hits::cpu1.data 15 # number of SwapReq hits +system.cpu1.dcache.SwapReq_hits::total 15 # number of SwapReq hits +system.cpu1.dcache.demand_hits::cpu1.data 74916 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 74916 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 74916 # number of overall hits +system.cpu1.dcache.overall_hits::total 74916 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 395 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 395 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 134 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 134 # number of WriteReq misses +system.cpu1.dcache.SwapReq_misses::cpu1.data 55 # number of SwapReq misses +system.cpu1.dcache.SwapReq_misses::total 55 # number of SwapReq misses +system.cpu1.dcache.demand_misses::cpu1.data 529 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 529 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 529 # number of overall misses +system.cpu1.dcache.overall_misses::total 529 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 11922500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 11922500 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 3308000 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 3308000 # number of WriteReq miss cycles +system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 1319000 # number of SwapReq miss cycles +system.cpu1.dcache.SwapReq_miss_latency::total 1319000 # number of SwapReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 15230500 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 15230500 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 15230500 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 15230500 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 43566 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 43566 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 31879 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 31879 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SwapReq_accesses::cpu1.data 70 # number of SwapReq accesses(hits+misses) +system.cpu1.dcache.SwapReq_accesses::total 70 # number of SwapReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 75445 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 75445 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 75445 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 75445 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.009067 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.009067 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.004203 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.004203 # miss rate for WriteReq accesses +system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.785714 # miss rate for SwapReq accesses +system.cpu1.dcache.SwapReq_miss_rate::total 0.785714 # miss rate for SwapReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.007012 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.007012 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.007012 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.007012 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 30183.544304 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 30183.544304 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 24686.567164 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 24686.567164 # average WriteReq miss latency +system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 23981.818182 # average SwapReq miss latency +system.cpu1.dcache.SwapReq_avg_miss_latency::total 23981.818182 # average SwapReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 28791.115312 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 28791.115312 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 28791.115312 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 28791.115312 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -961,366 +961,366 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 266 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 266 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 47 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 47 # number of WriteReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 313 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 313 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 313 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 313 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 159 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 159 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 107 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 107 # number of WriteReq MSHR misses -system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 52 # number of SwapReq MSHR misses -system.cpu1.dcache.SwapReq_mshr_misses::total 52 # number of SwapReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 229 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 229 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 34 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 34 # number of WriteReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 263 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 263 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 263 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 263 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 166 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 166 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 100 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 100 # number of WriteReq MSHR misses +system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 55 # number of SwapReq MSHR misses +system.cpu1.dcache.SwapReq_mshr_misses::total 55 # number of SwapReq MSHR misses system.cpu1.dcache.demand_mshr_misses::cpu1.data 266 # number of demand (read+write) MSHR misses system.cpu1.dcache.demand_mshr_misses::total 266 # number of demand (read+write) MSHR misses system.cpu1.dcache.overall_mshr_misses::cpu1.data 266 # number of overall MSHR misses system.cpu1.dcache.overall_mshr_misses::total 266 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2405000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2405000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1693500 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1693500 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 1063000 # number of SwapReq MSHR miss cycles -system.cpu1.dcache.SwapReq_mshr_miss_latency::total 1063000 # number of SwapReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4098500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 4098500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4098500 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 4098500 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.003530 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.003530 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.003166 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.003166 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.764706 # mshr miss rate for SwapReq accesses -system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.764706 # mshr miss rate for SwapReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.003374 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.003374 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.003374 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.003374 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15125.786164 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 15125.786164 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 15827.102804 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 15827.102804 # average WriteReq mshr miss latency -system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 20442.307692 # average SwapReq mshr miss latency -system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 20442.307692 # average SwapReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15407.894737 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 15407.894737 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15407.894737 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 15407.894737 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 3273504 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 3273504 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1639000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1639000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 1148500 # number of SwapReq MSHR miss cycles +system.cpu1.dcache.SwapReq_mshr_miss_latency::total 1148500 # number of SwapReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4912504 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 4912504 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4912504 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 4912504 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.003810 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.003810 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.003137 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.003137 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.785714 # mshr miss rate for SwapReq accesses +system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.785714 # mshr miss rate for SwapReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.003526 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.003526 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.003526 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.003526 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 19719.903614 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 19719.903614 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16390 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16390 # average WriteReq mshr miss latency +system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 20881.818182 # average SwapReq mshr miss latency +system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 20881.818182 # average SwapReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18468.060150 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18468.060150 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18468.060150 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18468.060150 # average overall mshr miss latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.numCycles 187552 # number of cpu cycles simulated +system.cpu2.numCycles 191032 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.BPredUnit.lookups 49236 # Number of BP lookups -system.cpu2.BPredUnit.condPredicted 46105 # Number of conditional branches predicted -system.cpu2.BPredUnit.condIncorrect 1532 # Number of conditional branches incorrect -system.cpu2.BPredUnit.BTBLookups 42466 # Number of BTB lookups -system.cpu2.BPredUnit.BTBHits 41429 # Number of BTB hits +system.cpu2.BPredUnit.lookups 57390 # Number of BP lookups +system.cpu2.BPredUnit.condPredicted 54193 # Number of conditional branches predicted +system.cpu2.BPredUnit.condIncorrect 1550 # Number of conditional branches incorrect +system.cpu2.BPredUnit.BTBLookups 50681 # Number of BTB lookups +system.cpu2.BPredUnit.BTBHits 49645 # Number of BTB hits system.cpu2.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.BPredUnit.usedRAS 825 # Number of times the RAS was used to get a target. +system.cpu2.BPredUnit.usedRAS 804 # Number of times the RAS was used to get a target. system.cpu2.BPredUnit.RASInCorrect 232 # Number of incorrect RAS predictions. -system.cpu2.fetch.icacheStallCycles 33274 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 268508 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 49236 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 42254 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 98143 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 4464 # Number of cycles fetch has spent squashing -system.cpu2.fetch.BlockedCycles 42536 # Number of cycles fetch has spent blocked +system.cpu2.fetch.icacheStallCycles 29539 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 321276 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 57390 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 50449 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 112230 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 4473 # Number of cycles fetch has spent squashing +system.cpu2.fetch.BlockedCycles 35583 # Number of cycles fetch has spent blocked system.cpu2.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu2.fetch.NoActiveThreadStallCycles 6571 # Number of stall cycles due to no active thread to fetch from -system.cpu2.fetch.PendingTrapStallCycles 1082 # Number of stall cycles due to pending traps -system.cpu2.fetch.CacheLines 24716 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 294 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.rateDist::samples 184466 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.455596 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 2.059567 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.NoActiveThreadStallCycles 6761 # Number of stall cycles due to no active thread to fetch from +system.cpu2.fetch.PendingTrapStallCycles 1077 # Number of stall cycles due to pending traps +system.cpu2.fetch.CacheLines 20533 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 334 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.rateDist::samples 188044 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.708515 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 2.158633 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 86323 46.80% 46.80% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 50944 27.62% 74.41% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 8337 4.52% 78.93% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 3301 1.79% 80.72% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 755 0.41% 81.13% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 29086 15.77% 96.90% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 1170 0.63% 97.53% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 883 0.48% 98.01% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 3667 1.99% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 75814 40.32% 40.32% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 56962 30.29% 70.61% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 6138 3.26% 73.87% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 3348 1.78% 75.65% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 769 0.41% 76.06% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 39287 20.89% 96.95% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 1207 0.64% 97.60% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 911 0.48% 98.08% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 3608 1.92% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 184466 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.262519 # Number of branch fetches per cycle -system.cpu2.fetch.rate 1.431646 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 41063 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 36807 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 89946 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 7224 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 2855 # Number of cycles decode is squashing -system.cpu2.decode.DecodedInsts 264281 # Number of instructions handled by decode -system.cpu2.rename.SquashCycles 2855 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 41843 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 22202 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 13743 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 82992 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 14260 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 261668 # Number of instructions processed by rename -system.cpu2.rename.IQFullEvents 19 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LSQFullEvents 57 # Number of times rename has blocked due to LSQ full -system.cpu2.rename.RenamedOperands 181221 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 490993 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 490993 # Number of integer rename lookups -system.cpu2.rename.CommittedMaps 165322 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 15899 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 1233 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 1350 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 17036 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 71489 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 32632 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 34884 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 27362 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 213682 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 8649 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 217360 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 54 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 13263 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 11908 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 765 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 184466 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 1.178320 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 1.292872 # Number of insts issued each cycle +system.cpu2.fetch.rateDist::total 188044 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.300421 # Number of branch fetches per cycle +system.cpu2.fetch.rate 1.681792 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 35225 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 31967 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 106013 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 5229 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 2849 # Number of cycles decode is squashing +system.cpu2.decode.DecodedInsts 316907 # Number of instructions handled by decode +system.cpu2.rename.SquashCycles 2849 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 36004 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 16323 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 14784 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 101094 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 10229 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 314547 # Number of instructions processed by rename +system.cpu2.rename.IQFullEvents 23 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LSQFullEvents 56 # Number of times rename has blocked due to LSQ full +system.cpu2.rename.RenamedOperands 220052 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 605102 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 605102 # Number of integer rename lookups +system.cpu2.rename.CommittedMaps 204228 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 15824 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 1236 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 1356 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 12873 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 89800 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 42907 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 42940 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 37601 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 260749 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 6485 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 262481 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 146 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 13131 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 11780 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 687 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 188044 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 1.395849 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 1.314415 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 84063 45.57% 45.57% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 29277 15.87% 61.44% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 32764 17.76% 79.20% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 33297 18.05% 97.25% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 3312 1.80% 99.05% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 1277 0.69% 99.74% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 362 0.20% 99.94% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 53 0.03% 99.97% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 61 0.03% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 73292 38.98% 38.98% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 23055 12.26% 51.24% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 43065 22.90% 74.14% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 43582 23.18% 97.31% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 3340 1.78% 99.09% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 1248 0.66% 99.75% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 346 0.18% 99.94% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 54 0.03% 99.97% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 62 0.03% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 184466 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 188044 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 20 6.64% 6.64% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 0 0.00% 6.64% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 0 0.00% 6.64% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 6.64% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 6.64% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 6.64% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 6.64% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 6.64% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 6.64% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 6.64% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 6.64% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 6.64% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 6.64% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 6.64% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 6.64% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 6.64% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 6.64% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 6.64% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 6.64% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 6.64% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 6.64% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 6.64% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 6.64% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 6.64% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 6.64% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 6.64% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 6.64% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.64% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 6.64% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 71 23.59% 30.23% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 210 69.77% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 21 6.65% 6.65% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 0 0.00% 6.65% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 0 0.00% 6.65% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 6.65% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 6.65% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 6.65% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 6.65% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 6.65% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 6.65% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 6.65% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 6.65% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 6.65% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 6.65% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 6.65% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 6.65% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 6.65% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 6.65% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 6.65% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 6.65% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 6.65% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 6.65% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 6.65% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 6.65% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 6.65% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 6.65% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 6.65% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 6.65% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.65% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 6.65% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 85 26.90% 33.54% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 210 66.46% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 107542 49.48% 49.48% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 0 0.00% 49.48% # Type of FU issued -system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 49.48% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 49.48% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 49.48% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 49.48% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 49.48% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 49.48% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 49.48% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 49.48% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 49.48% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 49.48% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 49.48% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 49.48% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 49.48% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 49.48% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 49.48% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 49.48% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.48% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 49.48% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.48% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.48% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.48% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.48% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.48% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.48% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 49.48% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.48% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.48% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 77871 35.83% 85.30% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 31947 14.70% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 126143 48.06% 48.06% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 0 0.00% 48.06% # Type of FU issued +system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 48.06% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 48.06% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 48.06% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 48.06% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 48.06% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 48.06% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 48.06% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 48.06% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 48.06% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 48.06% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 48.06% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 48.06% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 48.06% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 48.06% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 48.06% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 48.06% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.06% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 48.06% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 48.06% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.06% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 48.06% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 48.06% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 48.06% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.06% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 48.06% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.06% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.06% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 94161 35.87% 83.93% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 42177 16.07% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 217360 # Type of FU issued -system.cpu2.iq.rate 1.158932 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 301 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.001385 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 619541 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 235636 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 215243 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.FU_type_0::total 262481 # Type of FU issued +system.cpu2.iq.rate 1.374016 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 316 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.001204 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 713468 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 280402 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 260315 # Number of integer instruction queue wakeup accesses system.cpu2.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu2.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu2.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 217661 # Number of integer alu accesses +system.cpu2.iq.int_alu_accesses 262797 # Number of integer alu accesses system.cpu2.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 27206 # Number of loads that had data forwarded from stores +system.cpu2.iew.lsq.thread0.forwLoads 37443 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 2801 # Number of loads squashed -system.cpu2.iew.lsq.thread0.ignoredResponses 8 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 42 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 1615 # Number of stores squashed +system.cpu2.iew.lsq.thread0.squashedLoads 2702 # Number of loads squashed +system.cpu2.iew.lsq.thread0.ignoredResponses 6 # Number of memory responses ignored because the instruction is squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 37 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 1644 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu2.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu2.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 2855 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 1726 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 52 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 258195 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 386 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 71489 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 32632 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 1140 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 46 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewSquashCycles 2849 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 1860 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 77 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 311245 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 407 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 89800 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 42907 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 1163 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 74 # Number of times the IQ has become full, causing a stall system.cpu2.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 42 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 513 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 1199 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 1712 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 215982 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 70400 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 1378 # Number of squashed instructions skipped in execute +system.cpu2.iew.memOrderViolationEvents 37 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 516 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 1201 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 1717 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 261072 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 88760 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 1409 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed -system.cpu2.iew.exec_nop 35864 # number of nop insts executed -system.cpu2.iew.exec_refs 102255 # number of memory reference insts executed -system.cpu2.iew.exec_branches 45260 # Number of branches executed -system.cpu2.iew.exec_stores 31855 # Number of stores executed -system.cpu2.iew.exec_rate 1.151585 # Inst execution rate -system.cpu2.iew.wb_sent 215555 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 215243 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 119078 # num instructions producing a value -system.cpu2.iew.wb_consumers 124002 # num instructions consuming a value +system.cpu2.iew.exec_nop 44011 # number of nop insts executed +system.cpu2.iew.exec_refs 130847 # number of memory reference insts executed +system.cpu2.iew.exec_branches 53503 # Number of branches executed +system.cpu2.iew.exec_stores 42087 # Number of stores executed +system.cpu2.iew.exec_rate 1.366640 # Inst execution rate +system.cpu2.iew.wb_sent 260613 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 260315 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 147697 # num instructions producing a value +system.cpu2.iew.wb_consumers 152590 # num instructions consuming a value system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_rate 1.147644 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.960291 # average fanout of values written-back +system.cpu2.iew.wb_rate 1.362677 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.967934 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.commit.commitCommittedInsts 242999 # The number of committed instructions -system.cpu2.commit.commitCommittedOps 242999 # The number of committed instructions -system.cpu2.commit.commitSquashedInsts 15188 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 7884 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 1532 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 175041 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 1.388240 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 1.921152 # Number of insts commited each cycle +system.cpu2.commit.commitCommittedInsts 296145 # The number of committed instructions +system.cpu2.commit.commitCommittedOps 296145 # The number of committed instructions +system.cpu2.commit.commitSquashedInsts 15092 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 5798 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 1550 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 178435 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 1.659680 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 2.032759 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 85384 48.78% 48.78% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 43145 24.65% 73.43% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 6226 3.56% 76.98% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 8763 5.01% 81.99% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 1523 0.87% 82.86% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 27601 15.77% 98.63% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 589 0.34% 98.97% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 998 0.57% 99.54% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 812 0.46% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 72400 40.57% 40.57% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 51371 28.79% 69.36% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 6245 3.50% 72.86% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 6660 3.73% 76.60% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 1539 0.86% 77.46% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 37793 21.18% 98.64% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 621 0.35% 98.99% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 991 0.56% 99.54% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 815 0.46% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 175041 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 242999 # Number of instructions committed -system.cpu2.commit.committedOps 242999 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 178435 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 296145 # Number of instructions committed +system.cpu2.commit.committedOps 296145 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 99705 # Number of memory references committed -system.cpu2.commit.loads 68688 # Number of loads committed -system.cpu2.commit.membars 7170 # Number of memory barriers committed -system.cpu2.commit.branches 44148 # Number of branches committed +system.cpu2.commit.refs 128361 # Number of memory references committed +system.cpu2.commit.loads 87098 # Number of loads committed +system.cpu2.commit.membars 5084 # Number of memory barriers committed +system.cpu2.commit.branches 52312 # Number of branches committed system.cpu2.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 165976 # Number of committed integer instructions. +system.cpu2.commit.int_insts 202794 # Number of committed integer instructions. system.cpu2.commit.function_calls 322 # Number of function calls committed. -system.cpu2.commit.bw_lim_events 812 # number cycles where commit BW limit reached +system.cpu2.commit.bw_lim_events 815 # number cycles where commit BW limit reached system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu2.rob.rob_reads 431829 # The number of ROB reads -system.cpu2.rob.rob_writes 519243 # The number of ROB writes -system.cpu2.timesIdled 226 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 3086 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 35636 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 200891 # Number of Instructions Simulated -system.cpu2.committedOps 200891 # Number of Ops (including micro ops) Simulated -system.cpu2.committedInsts_total 200891 # Number of Instructions Simulated -system.cpu2.cpi 0.933601 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 0.933601 # CPI: Total CPI of All Threads -system.cpu2.ipc 1.071122 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 1.071122 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 366578 # number of integer regfile reads -system.cpu2.int_regfile_writes 171642 # number of integer regfile writes +system.cpu2.rob.rob_reads 488270 # The number of ROB reads +system.cpu2.rob.rob_writes 625337 # The number of ROB writes +system.cpu2.timesIdled 230 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 2988 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 36850 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 247959 # Number of Instructions Simulated +system.cpu2.committedOps 247959 # Number of Ops (including micro ops) Simulated +system.cpu2.committedInsts_total 247959 # Number of Instructions Simulated +system.cpu2.cpi 0.770418 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 0.770418 # CPI: Total CPI of All Threads +system.cpu2.ipc 1.297997 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 1.297997 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 452595 # number of integer regfile reads +system.cpu2.int_regfile_writes 210629 # number of integer regfile writes system.cpu2.fp_regfile_writes 64 # number of floating regfile writes -system.cpu2.misc_regfile_reads 103931 # number of misc regfile reads +system.cpu2.misc_regfile_reads 132559 # number of misc regfile reads system.cpu2.misc_regfile_writes 646 # number of misc regfile writes -system.cpu2.icache.replacements 324 # number of replacements -system.cpu2.icache.tagsinuse 83.306019 # Cycle average of tags in use -system.cpu2.icache.total_refs 24210 # Total number of references to valid blocks. +system.cpu2.icache.replacements 322 # number of replacements +system.cpu2.icache.tagsinuse 84.182173 # Cycle average of tags in use +system.cpu2.icache.total_refs 20037 # Total number of references to valid blocks. system.cpu2.icache.sampled_refs 438 # Sample count of references to valid blocks. -system.cpu2.icache.avg_refs 55.273973 # Average number of references to valid blocks. +system.cpu2.icache.avg_refs 45.746575 # Average number of references to valid blocks. system.cpu2.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.icache.occ_blocks::cpu2.inst 83.306019 # Average occupied blocks per requestor -system.cpu2.icache.occ_percent::cpu2.inst 0.162707 # Average percentage of cache occupancy -system.cpu2.icache.occ_percent::total 0.162707 # Average percentage of cache occupancy -system.cpu2.icache.ReadReq_hits::cpu2.inst 24210 # number of ReadReq hits -system.cpu2.icache.ReadReq_hits::total 24210 # number of ReadReq hits -system.cpu2.icache.demand_hits::cpu2.inst 24210 # number of demand (read+write) hits -system.cpu2.icache.demand_hits::total 24210 # number of demand (read+write) hits -system.cpu2.icache.overall_hits::cpu2.inst 24210 # number of overall hits -system.cpu2.icache.overall_hits::total 24210 # number of overall hits -system.cpu2.icache.ReadReq_misses::cpu2.inst 506 # number of ReadReq misses -system.cpu2.icache.ReadReq_misses::total 506 # number of ReadReq misses -system.cpu2.icache.demand_misses::cpu2.inst 506 # number of demand (read+write) misses -system.cpu2.icache.demand_misses::total 506 # number of demand (read+write) misses -system.cpu2.icache.overall_misses::cpu2.inst 506 # number of overall misses -system.cpu2.icache.overall_misses::total 506 # number of overall misses -system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 7060500 # number of ReadReq miss cycles -system.cpu2.icache.ReadReq_miss_latency::total 7060500 # number of ReadReq miss cycles -system.cpu2.icache.demand_miss_latency::cpu2.inst 7060500 # number of demand (read+write) miss cycles -system.cpu2.icache.demand_miss_latency::total 7060500 # number of demand (read+write) miss cycles -system.cpu2.icache.overall_miss_latency::cpu2.inst 7060500 # number of overall miss cycles -system.cpu2.icache.overall_miss_latency::total 7060500 # number of overall miss cycles -system.cpu2.icache.ReadReq_accesses::cpu2.inst 24716 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.ReadReq_accesses::total 24716 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.demand_accesses::cpu2.inst 24716 # number of demand (read+write) accesses -system.cpu2.icache.demand_accesses::total 24716 # number of demand (read+write) accesses -system.cpu2.icache.overall_accesses::cpu2.inst 24716 # number of overall (read+write) accesses -system.cpu2.icache.overall_accesses::total 24716 # number of overall (read+write) accesses -system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.020473 # miss rate for ReadReq accesses -system.cpu2.icache.ReadReq_miss_rate::total 0.020473 # miss rate for ReadReq accesses -system.cpu2.icache.demand_miss_rate::cpu2.inst 0.020473 # miss rate for demand accesses -system.cpu2.icache.demand_miss_rate::total 0.020473 # miss rate for demand accesses -system.cpu2.icache.overall_miss_rate::cpu2.inst 0.020473 # miss rate for overall accesses -system.cpu2.icache.overall_miss_rate::total 0.020473 # miss rate for overall accesses -system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 13953.557312 # average ReadReq miss latency -system.cpu2.icache.ReadReq_avg_miss_latency::total 13953.557312 # average ReadReq miss latency -system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 13953.557312 # average overall miss latency -system.cpu2.icache.demand_avg_miss_latency::total 13953.557312 # average overall miss latency -system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 13953.557312 # average overall miss latency -system.cpu2.icache.overall_avg_miss_latency::total 13953.557312 # average overall miss latency +system.cpu2.icache.occ_blocks::cpu2.inst 84.182173 # Average occupied blocks per requestor +system.cpu2.icache.occ_percent::cpu2.inst 0.164418 # Average percentage of cache occupancy +system.cpu2.icache.occ_percent::total 0.164418 # Average percentage of cache occupancy +system.cpu2.icache.ReadReq_hits::cpu2.inst 20037 # number of ReadReq hits +system.cpu2.icache.ReadReq_hits::total 20037 # number of ReadReq hits +system.cpu2.icache.demand_hits::cpu2.inst 20037 # number of demand (read+write) hits +system.cpu2.icache.demand_hits::total 20037 # number of demand (read+write) hits +system.cpu2.icache.overall_hits::cpu2.inst 20037 # number of overall hits +system.cpu2.icache.overall_hits::total 20037 # number of overall hits +system.cpu2.icache.ReadReq_misses::cpu2.inst 496 # number of ReadReq misses +system.cpu2.icache.ReadReq_misses::total 496 # number of ReadReq misses +system.cpu2.icache.demand_misses::cpu2.inst 496 # number of demand (read+write) misses +system.cpu2.icache.demand_misses::total 496 # number of demand (read+write) misses +system.cpu2.icache.overall_misses::cpu2.inst 496 # number of overall misses +system.cpu2.icache.overall_misses::total 496 # number of overall misses +system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 7608500 # number of ReadReq miss cycles +system.cpu2.icache.ReadReq_miss_latency::total 7608500 # number of ReadReq miss cycles +system.cpu2.icache.demand_miss_latency::cpu2.inst 7608500 # number of demand (read+write) miss cycles +system.cpu2.icache.demand_miss_latency::total 7608500 # number of demand (read+write) miss cycles +system.cpu2.icache.overall_miss_latency::cpu2.inst 7608500 # number of overall miss cycles +system.cpu2.icache.overall_miss_latency::total 7608500 # number of overall miss cycles +system.cpu2.icache.ReadReq_accesses::cpu2.inst 20533 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.ReadReq_accesses::total 20533 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.demand_accesses::cpu2.inst 20533 # number of demand (read+write) accesses +system.cpu2.icache.demand_accesses::total 20533 # number of demand (read+write) accesses +system.cpu2.icache.overall_accesses::cpu2.inst 20533 # number of overall (read+write) accesses +system.cpu2.icache.overall_accesses::total 20533 # number of overall (read+write) accesses +system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.024156 # miss rate for ReadReq accesses +system.cpu2.icache.ReadReq_miss_rate::total 0.024156 # miss rate for ReadReq accesses +system.cpu2.icache.demand_miss_rate::cpu2.inst 0.024156 # miss rate for demand accesses +system.cpu2.icache.demand_miss_rate::total 0.024156 # miss rate for demand accesses +system.cpu2.icache.overall_miss_rate::cpu2.inst 0.024156 # miss rate for overall accesses +system.cpu2.icache.overall_miss_rate::total 0.024156 # miss rate for overall accesses +system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 15339.717742 # average ReadReq miss latency +system.cpu2.icache.ReadReq_avg_miss_latency::total 15339.717742 # average ReadReq miss latency +system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 15339.717742 # average overall miss latency +system.cpu2.icache.demand_avg_miss_latency::total 15339.717742 # average overall miss latency +system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 15339.717742 # average overall miss latency +system.cpu2.icache.overall_avg_miss_latency::total 15339.717742 # average overall miss latency system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1329,106 +1329,106 @@ system.cpu2.icache.avg_blocked_cycles::no_mshrs nan system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu2.icache.fast_writes 0 # number of fast writes performed system.cpu2.icache.cache_copies 0 # number of cache copies performed -system.cpu2.icache.ReadReq_mshr_hits::cpu2.inst 68 # number of ReadReq MSHR hits -system.cpu2.icache.ReadReq_mshr_hits::total 68 # number of ReadReq MSHR hits -system.cpu2.icache.demand_mshr_hits::cpu2.inst 68 # number of demand (read+write) MSHR hits -system.cpu2.icache.demand_mshr_hits::total 68 # number of demand (read+write) MSHR hits -system.cpu2.icache.overall_mshr_hits::cpu2.inst 68 # number of overall MSHR hits -system.cpu2.icache.overall_mshr_hits::total 68 # number of overall MSHR hits +system.cpu2.icache.ReadReq_mshr_hits::cpu2.inst 58 # number of ReadReq MSHR hits +system.cpu2.icache.ReadReq_mshr_hits::total 58 # number of ReadReq MSHR hits +system.cpu2.icache.demand_mshr_hits::cpu2.inst 58 # number of demand (read+write) MSHR hits +system.cpu2.icache.demand_mshr_hits::total 58 # number of demand (read+write) MSHR hits +system.cpu2.icache.overall_mshr_hits::cpu2.inst 58 # number of overall MSHR hits +system.cpu2.icache.overall_mshr_hits::total 58 # number of overall MSHR hits system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst 438 # number of ReadReq MSHR misses system.cpu2.icache.ReadReq_mshr_misses::total 438 # number of ReadReq MSHR misses system.cpu2.icache.demand_mshr_misses::cpu2.inst 438 # number of demand (read+write) MSHR misses system.cpu2.icache.demand_mshr_misses::total 438 # number of demand (read+write) MSHR misses system.cpu2.icache.overall_mshr_misses::cpu2.inst 438 # number of overall MSHR misses system.cpu2.icache.overall_mshr_misses::total 438 # number of overall MSHR misses -system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 5136000 # number of ReadReq MSHR miss cycles -system.cpu2.icache.ReadReq_mshr_miss_latency::total 5136000 # number of ReadReq MSHR miss cycles -system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 5136000 # number of demand (read+write) MSHR miss cycles -system.cpu2.icache.demand_mshr_miss_latency::total 5136000 # number of demand (read+write) MSHR miss cycles -system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 5136000 # number of overall MSHR miss cycles -system.cpu2.icache.overall_mshr_miss_latency::total 5136000 # number of overall MSHR miss cycles -system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.017721 # mshr miss rate for ReadReq accesses -system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.017721 # mshr miss rate for ReadReq accesses -system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.017721 # mshr miss rate for demand accesses -system.cpu2.icache.demand_mshr_miss_rate::total 0.017721 # mshr miss rate for demand accesses -system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.017721 # mshr miss rate for overall accesses -system.cpu2.icache.overall_mshr_miss_rate::total 0.017721 # mshr miss rate for overall accesses -system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 11726.027397 # average ReadReq mshr miss latency -system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 11726.027397 # average ReadReq mshr miss latency -system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 11726.027397 # average overall mshr miss latency -system.cpu2.icache.demand_avg_mshr_miss_latency::total 11726.027397 # average overall mshr miss latency -system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 11726.027397 # average overall mshr miss latency -system.cpu2.icache.overall_avg_mshr_miss_latency::total 11726.027397 # average overall mshr miss latency +system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 5673500 # number of ReadReq MSHR miss cycles +system.cpu2.icache.ReadReq_mshr_miss_latency::total 5673500 # number of ReadReq MSHR miss cycles +system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 5673500 # number of demand (read+write) MSHR miss cycles +system.cpu2.icache.demand_mshr_miss_latency::total 5673500 # number of demand (read+write) MSHR miss cycles +system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 5673500 # number of overall MSHR miss cycles +system.cpu2.icache.overall_mshr_miss_latency::total 5673500 # number of overall MSHR miss cycles +system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.021332 # mshr miss rate for ReadReq accesses +system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.021332 # mshr miss rate for ReadReq accesses +system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.021332 # mshr miss rate for demand accesses +system.cpu2.icache.demand_mshr_miss_rate::total 0.021332 # mshr miss rate for demand accesses +system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.021332 # mshr miss rate for overall accesses +system.cpu2.icache.overall_mshr_miss_rate::total 0.021332 # mshr miss rate for overall accesses +system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12953.196347 # average ReadReq mshr miss latency +system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 12953.196347 # average ReadReq mshr miss latency +system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 12953.196347 # average overall mshr miss latency +system.cpu2.icache.demand_avg_mshr_miss_latency::total 12953.196347 # average overall mshr miss latency +system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 12953.196347 # average overall mshr miss latency +system.cpu2.icache.overall_avg_mshr_miss_latency::total 12953.196347 # average overall mshr miss latency system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu2.dcache.replacements 0 # number of replacements -system.cpu2.dcache.tagsinuse 24.973314 # Cycle average of tags in use -system.cpu2.dcache.total_refs 37203 # Total number of references to valid blocks. +system.cpu2.dcache.tagsinuse 24.868946 # Cycle average of tags in use +system.cpu2.dcache.total_refs 47444 # Total number of references to valid blocks. system.cpu2.dcache.sampled_refs 28 # Sample count of references to valid blocks. -system.cpu2.dcache.avg_refs 1328.678571 # Average number of references to valid blocks. +system.cpu2.dcache.avg_refs 1694.428571 # Average number of references to valid blocks. system.cpu2.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.dcache.occ_blocks::cpu2.data 24.973314 # Average occupied blocks per requestor -system.cpu2.dcache.occ_percent::cpu2.data 0.048776 # Average percentage of cache occupancy -system.cpu2.dcache.occ_percent::total 0.048776 # Average percentage of cache occupancy -system.cpu2.dcache.ReadReq_hits::cpu2.data 42731 # number of ReadReq hits -system.cpu2.dcache.ReadReq_hits::total 42731 # number of ReadReq hits -system.cpu2.dcache.WriteReq_hits::cpu2.data 30798 # number of WriteReq hits -system.cpu2.dcache.WriteReq_hits::total 30798 # number of WriteReq hits -system.cpu2.dcache.SwapReq_hits::cpu2.data 14 # number of SwapReq hits -system.cpu2.dcache.SwapReq_hits::total 14 # number of SwapReq hits -system.cpu2.dcache.demand_hits::cpu2.data 73529 # number of demand (read+write) hits -system.cpu2.dcache.demand_hits::total 73529 # number of demand (read+write) hits -system.cpu2.dcache.overall_hits::cpu2.data 73529 # number of overall hits -system.cpu2.dcache.overall_hits::total 73529 # number of overall hits -system.cpu2.dcache.ReadReq_misses::cpu2.data 443 # number of ReadReq misses -system.cpu2.dcache.ReadReq_misses::total 443 # number of ReadReq misses -system.cpu2.dcache.WriteReq_misses::cpu2.data 151 # number of WriteReq misses -system.cpu2.dcache.WriteReq_misses::total 151 # number of WriteReq misses -system.cpu2.dcache.SwapReq_misses::cpu2.data 54 # number of SwapReq misses -system.cpu2.dcache.SwapReq_misses::total 54 # number of SwapReq misses -system.cpu2.dcache.demand_misses::cpu2.data 594 # number of demand (read+write) misses -system.cpu2.dcache.demand_misses::total 594 # number of demand (read+write) misses -system.cpu2.dcache.overall_misses::cpu2.data 594 # number of overall misses -system.cpu2.dcache.overall_misses::total 594 # number of overall misses -system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 9862000 # number of ReadReq miss cycles -system.cpu2.dcache.ReadReq_miss_latency::total 9862000 # number of ReadReq miss cycles -system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 2806000 # number of WriteReq miss cycles -system.cpu2.dcache.WriteReq_miss_latency::total 2806000 # number of WriteReq miss cycles -system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 1173500 # number of SwapReq miss cycles -system.cpu2.dcache.SwapReq_miss_latency::total 1173500 # number of SwapReq miss cycles -system.cpu2.dcache.demand_miss_latency::cpu2.data 12668000 # number of demand (read+write) miss cycles -system.cpu2.dcache.demand_miss_latency::total 12668000 # number of demand (read+write) miss cycles -system.cpu2.dcache.overall_miss_latency::cpu2.data 12668000 # number of overall miss cycles -system.cpu2.dcache.overall_miss_latency::total 12668000 # number of overall miss cycles -system.cpu2.dcache.ReadReq_accesses::cpu2.data 43174 # number of ReadReq accesses(hits+misses) -system.cpu2.dcache.ReadReq_accesses::total 43174 # number of ReadReq accesses(hits+misses) -system.cpu2.dcache.WriteReq_accesses::cpu2.data 30949 # number of WriteReq accesses(hits+misses) -system.cpu2.dcache.WriteReq_accesses::total 30949 # number of WriteReq accesses(hits+misses) +system.cpu2.dcache.occ_blocks::cpu2.data 24.868946 # Average occupied blocks per requestor +system.cpu2.dcache.occ_percent::cpu2.data 0.048572 # Average percentage of cache occupancy +system.cpu2.dcache.occ_percent::total 0.048572 # Average percentage of cache occupancy +system.cpu2.dcache.ReadReq_hits::cpu2.data 50906 # number of ReadReq hits +system.cpu2.dcache.ReadReq_hits::total 50906 # number of ReadReq hits +system.cpu2.dcache.WriteReq_hits::cpu2.data 41055 # number of WriteReq hits +system.cpu2.dcache.WriteReq_hits::total 41055 # number of WriteReq hits +system.cpu2.dcache.SwapReq_hits::cpu2.data 12 # number of SwapReq hits +system.cpu2.dcache.SwapReq_hits::total 12 # number of SwapReq hits +system.cpu2.dcache.demand_hits::cpu2.data 91961 # number of demand (read+write) hits +system.cpu2.dcache.demand_hits::total 91961 # number of demand (read+write) hits +system.cpu2.dcache.overall_hits::cpu2.data 91961 # number of overall hits +system.cpu2.dcache.overall_hits::total 91961 # number of overall hits +system.cpu2.dcache.ReadReq_misses::cpu2.data 392 # number of ReadReq misses +system.cpu2.dcache.ReadReq_misses::total 392 # number of ReadReq misses +system.cpu2.dcache.WriteReq_misses::cpu2.data 140 # number of WriteReq misses +system.cpu2.dcache.WriteReq_misses::total 140 # number of WriteReq misses +system.cpu2.dcache.SwapReq_misses::cpu2.data 56 # number of SwapReq misses +system.cpu2.dcache.SwapReq_misses::total 56 # number of SwapReq misses +system.cpu2.dcache.demand_misses::cpu2.data 532 # number of demand (read+write) misses +system.cpu2.dcache.demand_misses::total 532 # number of demand (read+write) misses +system.cpu2.dcache.overall_misses::cpu2.data 532 # number of overall misses +system.cpu2.dcache.overall_misses::total 532 # number of overall misses +system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 10132000 # number of ReadReq miss cycles +system.cpu2.dcache.ReadReq_miss_latency::total 10132000 # number of ReadReq miss cycles +system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 3391500 # number of WriteReq miss cycles +system.cpu2.dcache.WriteReq_miss_latency::total 3391500 # number of WriteReq miss cycles +system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 1227500 # number of SwapReq miss cycles +system.cpu2.dcache.SwapReq_miss_latency::total 1227500 # number of SwapReq miss cycles +system.cpu2.dcache.demand_miss_latency::cpu2.data 13523500 # number of demand (read+write) miss cycles +system.cpu2.dcache.demand_miss_latency::total 13523500 # number of demand (read+write) miss cycles +system.cpu2.dcache.overall_miss_latency::cpu2.data 13523500 # number of overall miss cycles +system.cpu2.dcache.overall_miss_latency::total 13523500 # number of overall miss cycles +system.cpu2.dcache.ReadReq_accesses::cpu2.data 51298 # number of ReadReq accesses(hits+misses) +system.cpu2.dcache.ReadReq_accesses::total 51298 # number of ReadReq accesses(hits+misses) +system.cpu2.dcache.WriteReq_accesses::cpu2.data 41195 # number of WriteReq accesses(hits+misses) +system.cpu2.dcache.WriteReq_accesses::total 41195 # number of WriteReq accesses(hits+misses) system.cpu2.dcache.SwapReq_accesses::cpu2.data 68 # number of SwapReq accesses(hits+misses) system.cpu2.dcache.SwapReq_accesses::total 68 # number of SwapReq accesses(hits+misses) -system.cpu2.dcache.demand_accesses::cpu2.data 74123 # number of demand (read+write) accesses -system.cpu2.dcache.demand_accesses::total 74123 # number of demand (read+write) accesses -system.cpu2.dcache.overall_accesses::cpu2.data 74123 # number of overall (read+write) accesses -system.cpu2.dcache.overall_accesses::total 74123 # number of overall (read+write) accesses -system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.010261 # miss rate for ReadReq accesses -system.cpu2.dcache.ReadReq_miss_rate::total 0.010261 # miss rate for ReadReq accesses -system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.004879 # miss rate for WriteReq accesses -system.cpu2.dcache.WriteReq_miss_rate::total 0.004879 # miss rate for WriteReq accesses -system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.794118 # miss rate for SwapReq accesses -system.cpu2.dcache.SwapReq_miss_rate::total 0.794118 # miss rate for SwapReq accesses -system.cpu2.dcache.demand_miss_rate::cpu2.data 0.008014 # miss rate for demand accesses -system.cpu2.dcache.demand_miss_rate::total 0.008014 # miss rate for demand accesses -system.cpu2.dcache.overall_miss_rate::cpu2.data 0.008014 # miss rate for overall accesses -system.cpu2.dcache.overall_miss_rate::total 0.008014 # miss rate for overall accesses -system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 22261.851016 # average ReadReq miss latency -system.cpu2.dcache.ReadReq_avg_miss_latency::total 22261.851016 # average ReadReq miss latency -system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 18582.781457 # average WriteReq miss latency -system.cpu2.dcache.WriteReq_avg_miss_latency::total 18582.781457 # average WriteReq miss latency -system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 21731.481481 # average SwapReq miss latency -system.cpu2.dcache.SwapReq_avg_miss_latency::total 21731.481481 # average SwapReq miss latency -system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 21326.599327 # average overall miss latency -system.cpu2.dcache.demand_avg_miss_latency::total 21326.599327 # average overall miss latency -system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 21326.599327 # average overall miss latency -system.cpu2.dcache.overall_avg_miss_latency::total 21326.599327 # average overall miss latency +system.cpu2.dcache.demand_accesses::cpu2.data 92493 # number of demand (read+write) accesses +system.cpu2.dcache.demand_accesses::total 92493 # number of demand (read+write) accesses +system.cpu2.dcache.overall_accesses::cpu2.data 92493 # number of overall (read+write) accesses +system.cpu2.dcache.overall_accesses::total 92493 # number of overall (read+write) accesses +system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.007642 # miss rate for ReadReq accesses +system.cpu2.dcache.ReadReq_miss_rate::total 0.007642 # miss rate for ReadReq accesses +system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.003398 # miss rate for WriteReq accesses +system.cpu2.dcache.WriteReq_miss_rate::total 0.003398 # miss rate for WriteReq accesses +system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.823529 # miss rate for SwapReq accesses +system.cpu2.dcache.SwapReq_miss_rate::total 0.823529 # miss rate for SwapReq accesses +system.cpu2.dcache.demand_miss_rate::cpu2.data 0.005752 # miss rate for demand accesses +system.cpu2.dcache.demand_miss_rate::total 0.005752 # miss rate for demand accesses +system.cpu2.dcache.overall_miss_rate::cpu2.data 0.005752 # miss rate for overall accesses +system.cpu2.dcache.overall_miss_rate::total 0.005752 # miss rate for overall accesses +system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 25846.938776 # average ReadReq miss latency +system.cpu2.dcache.ReadReq_avg_miss_latency::total 25846.938776 # average ReadReq miss latency +system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 24225 # average WriteReq miss latency +system.cpu2.dcache.WriteReq_avg_miss_latency::total 24225 # average WriteReq miss latency +system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 21919.642857 # average SwapReq miss latency +system.cpu2.dcache.SwapReq_avg_miss_latency::total 21919.642857 # average SwapReq miss latency +system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 25420.112782 # average overall miss latency +system.cpu2.dcache.demand_avg_miss_latency::total 25420.112782 # average overall miss latency +system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 25420.112782 # average overall miss latency +system.cpu2.dcache.overall_avg_miss_latency::total 25420.112782 # average overall miss latency system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1437,366 +1437,366 @@ system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu2.dcache.fast_writes 0 # number of fast writes performed system.cpu2.dcache.cache_copies 0 # number of cache copies performed -system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data 279 # number of ReadReq MSHR hits -system.cpu2.dcache.ReadReq_mshr_hits::total 279 # number of ReadReq MSHR hits -system.cpu2.dcache.WriteReq_mshr_hits::cpu2.data 47 # number of WriteReq MSHR hits -system.cpu2.dcache.WriteReq_mshr_hits::total 47 # number of WriteReq MSHR hits -system.cpu2.dcache.demand_mshr_hits::cpu2.data 326 # number of demand (read+write) MSHR hits -system.cpu2.dcache.demand_mshr_hits::total 326 # number of demand (read+write) MSHR hits -system.cpu2.dcache.overall_mshr_hits::cpu2.data 326 # number of overall MSHR hits -system.cpu2.dcache.overall_mshr_hits::total 326 # number of overall MSHR hits -system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 164 # number of ReadReq MSHR misses -system.cpu2.dcache.ReadReq_mshr_misses::total 164 # number of ReadReq MSHR misses -system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 104 # number of WriteReq MSHR misses -system.cpu2.dcache.WriteReq_mshr_misses::total 104 # number of WriteReq MSHR misses -system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 54 # number of SwapReq MSHR misses -system.cpu2.dcache.SwapReq_mshr_misses::total 54 # number of SwapReq MSHR misses -system.cpu2.dcache.demand_mshr_misses::cpu2.data 268 # number of demand (read+write) MSHR misses -system.cpu2.dcache.demand_mshr_misses::total 268 # number of demand (read+write) MSHR misses -system.cpu2.dcache.overall_mshr_misses::cpu2.data 268 # number of overall MSHR misses -system.cpu2.dcache.overall_mshr_misses::total 268 # number of overall MSHR misses -system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 2336000 # number of ReadReq MSHR miss cycles -system.cpu2.dcache.ReadReq_mshr_miss_latency::total 2336000 # number of ReadReq MSHR miss cycles -system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1419000 # number of WriteReq MSHR miss cycles -system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1419000 # number of WriteReq MSHR miss cycles -system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 1011500 # number of SwapReq MSHR miss cycles -system.cpu2.dcache.SwapReq_mshr_miss_latency::total 1011500 # number of SwapReq MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 3755000 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_latency::total 3755000 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 3755000 # number of overall MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_latency::total 3755000 # number of overall MSHR miss cycles -system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003799 # mshr miss rate for ReadReq accesses -system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003799 # mshr miss rate for ReadReq accesses -system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.003360 # mshr miss rate for WriteReq accesses -system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.003360 # mshr miss rate for WriteReq accesses -system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.794118 # mshr miss rate for SwapReq accesses -system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.794118 # mshr miss rate for SwapReq accesses -system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.003616 # mshr miss rate for demand accesses -system.cpu2.dcache.demand_mshr_miss_rate::total 0.003616 # mshr miss rate for demand accesses -system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.003616 # mshr miss rate for overall accesses -system.cpu2.dcache.overall_mshr_miss_rate::total 0.003616 # mshr miss rate for overall accesses -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 14243.902439 # average ReadReq mshr miss latency -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 14243.902439 # average ReadReq mshr miss latency -system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 13644.230769 # average WriteReq mshr miss latency -system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 13644.230769 # average WriteReq mshr miss latency -system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 18731.481481 # average SwapReq mshr miss latency -system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 18731.481481 # average SwapReq mshr miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 14011.194030 # average overall mshr miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency::total 14011.194030 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 14011.194030 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency::total 14011.194030 # average overall mshr miss latency +system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data 241 # number of ReadReq MSHR hits +system.cpu2.dcache.ReadReq_mshr_hits::total 241 # number of ReadReq MSHR hits +system.cpu2.dcache.WriteReq_mshr_hits::cpu2.data 35 # number of WriteReq MSHR hits +system.cpu2.dcache.WriteReq_mshr_hits::total 35 # number of WriteReq MSHR hits +system.cpu2.dcache.demand_mshr_hits::cpu2.data 276 # number of demand (read+write) MSHR hits +system.cpu2.dcache.demand_mshr_hits::total 276 # number of demand (read+write) MSHR hits +system.cpu2.dcache.overall_mshr_hits::cpu2.data 276 # number of overall MSHR hits +system.cpu2.dcache.overall_mshr_hits::total 276 # number of overall MSHR hits +system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 151 # number of ReadReq MSHR misses +system.cpu2.dcache.ReadReq_mshr_misses::total 151 # number of ReadReq MSHR misses +system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 105 # number of WriteReq MSHR misses +system.cpu2.dcache.WriteReq_mshr_misses::total 105 # number of WriteReq MSHR misses +system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 56 # number of SwapReq MSHR misses +system.cpu2.dcache.SwapReq_mshr_misses::total 56 # number of SwapReq MSHR misses +system.cpu2.dcache.demand_mshr_misses::cpu2.data 256 # number of demand (read+write) MSHR misses +system.cpu2.dcache.demand_mshr_misses::total 256 # number of demand (read+write) MSHR misses +system.cpu2.dcache.overall_mshr_misses::cpu2.data 256 # number of overall MSHR misses +system.cpu2.dcache.overall_mshr_misses::total 256 # number of overall MSHR misses +system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 2456507 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_latency::total 2456507 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1732500 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1732500 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 1052000 # number of SwapReq MSHR miss cycles +system.cpu2.dcache.SwapReq_mshr_miss_latency::total 1052000 # number of SwapReq MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 4189007 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_latency::total 4189007 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 4189007 # number of overall MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_latency::total 4189007 # number of overall MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.002944 # mshr miss rate for ReadReq accesses +system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.002944 # mshr miss rate for ReadReq accesses +system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.002549 # mshr miss rate for WriteReq accesses +system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.002549 # mshr miss rate for WriteReq accesses +system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.823529 # mshr miss rate for SwapReq accesses +system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.823529 # mshr miss rate for SwapReq accesses +system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.002768 # mshr miss rate for demand accesses +system.cpu2.dcache.demand_mshr_miss_rate::total 0.002768 # mshr miss rate for demand accesses +system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.002768 # mshr miss rate for overall accesses +system.cpu2.dcache.overall_mshr_miss_rate::total 0.002768 # mshr miss rate for overall accesses +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 16268.258278 # average ReadReq mshr miss latency +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 16268.258278 # average ReadReq mshr miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 16500 # average WriteReq mshr miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 16500 # average WriteReq mshr miss latency +system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 18785.714286 # average SwapReq mshr miss latency +system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 18785.714286 # average SwapReq mshr miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 16363.308594 # average overall mshr miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency::total 16363.308594 # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 16363.308594 # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency::total 16363.308594 # average overall mshr miss latency system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.numCycles 187286 # number of cpu cycles simulated +system.cpu3.numCycles 190752 # number of cpu cycles simulated system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu3.BPredUnit.lookups 59110 # Number of BP lookups -system.cpu3.BPredUnit.condPredicted 55955 # Number of conditional branches predicted -system.cpu3.BPredUnit.condIncorrect 1573 # Number of conditional branches incorrect -system.cpu3.BPredUnit.BTBLookups 52456 # Number of BTB lookups -system.cpu3.BPredUnit.BTBHits 51388 # Number of BTB hits +system.cpu3.BPredUnit.lookups 53643 # Number of BP lookups +system.cpu3.BPredUnit.condPredicted 50394 # Number of conditional branches predicted +system.cpu3.BPredUnit.condIncorrect 1547 # Number of conditional branches incorrect +system.cpu3.BPredUnit.BTBLookups 46912 # Number of BTB lookups +system.cpu3.BPredUnit.BTBHits 45897 # Number of BTB hits system.cpu3.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu3.BPredUnit.usedRAS 831 # Number of times the RAS was used to get a target. +system.cpu3.BPredUnit.usedRAS 838 # Number of times the RAS was used to get a target. system.cpu3.BPredUnit.RASInCorrect 232 # Number of incorrect RAS predictions. -system.cpu3.fetch.icacheStallCycles 27555 # Number of cycles fetch is stalled on an Icache miss -system.cpu3.fetch.Insts 332776 # Number of instructions fetch has processed -system.cpu3.fetch.Branches 59110 # Number of branches that fetch encountered -system.cpu3.fetch.predictedBranches 52219 # Number of branches that fetch has predicted taken -system.cpu3.fetch.Cycles 115081 # Number of cycles fetch has run and was not squashing or blocked -system.cpu3.fetch.SquashCycles 4575 # Number of cycles fetch has spent squashing -system.cpu3.fetch.BlockedCycles 31846 # Number of cycles fetch has spent blocked +system.cpu3.fetch.icacheStallCycles 31381 # Number of cycles fetch is stalled on an Icache miss +system.cpu3.fetch.Insts 296607 # Number of instructions fetch has processed +system.cpu3.fetch.Branches 53643 # Number of branches that fetch encountered +system.cpu3.fetch.predictedBranches 46735 # Number of branches that fetch has predicted taken +system.cpu3.fetch.Cycles 105748 # Number of cycles fetch has run and was not squashing or blocked +system.cpu3.fetch.SquashCycles 4379 # Number of cycles fetch has spent squashing +system.cpu3.fetch.BlockedCycles 39758 # Number of cycles fetch has spent blocked system.cpu3.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu3.fetch.NoActiveThreadStallCycles 6567 # Number of stall cycles due to no active thread to fetch from -system.cpu3.fetch.PendingTrapStallCycles 1060 # Number of stall cycles due to pending traps -system.cpu3.fetch.CacheLines 19062 # Number of cache lines fetched -system.cpu3.fetch.IcacheSquashes 312 # Number of outstanding Icache misses that were squashed -system.cpu3.fetch.rateDist::samples 185045 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::mean 1.798352 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::stdev 2.183167 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.NoActiveThreadStallCycles 6743 # Number of stall cycles due to no active thread to fetch from +system.cpu3.fetch.PendingTrapStallCycles 1058 # Number of stall cycles due to pending traps +system.cpu3.fetch.CacheLines 22503 # Number of cache lines fetched +system.cpu3.fetch.IcacheSquashes 317 # Number of outstanding Icache misses that were squashed +system.cpu3.fetch.rateDist::samples 187456 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::mean 1.582275 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::stdev 2.112091 # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::0 69964 37.81% 37.81% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::1 58012 31.35% 69.16% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::2 5498 2.97% 72.13% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::3 3553 1.92% 74.05% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::4 717 0.39% 74.44% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::5 41629 22.50% 96.93% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::6 1211 0.65% 97.59% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::7 858 0.46% 98.05% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::8 3603 1.95% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::0 81708 43.59% 43.59% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::1 54260 28.95% 72.53% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::2 7170 3.82% 76.36% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::3 3258 1.74% 78.10% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::4 706 0.38% 78.47% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::5 34710 18.52% 96.99% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::6 1204 0.64% 97.63% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::7 885 0.47% 98.10% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::8 3555 1.90% 100.00% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::total 185045 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.branchRate 0.315614 # Number of branch fetches per cycle -system.cpu3.fetch.rate 1.776833 # Number of inst fetches per cycle -system.cpu3.decode.IdleCycles 32638 # Number of cycles decode is idle -system.cpu3.decode.BlockedCycles 28853 # Number of cycles decode is blocked -system.cpu3.decode.RunCycles 109537 # Number of cycles decode is running -system.cpu3.decode.UnblockCycles 4519 # Number of cycles decode is unblocking -system.cpu3.decode.SquashCycles 2931 # Number of cycles decode is squashing -system.cpu3.decode.DecodedInsts 328437 # Number of instructions handled by decode -system.cpu3.rename.SquashCycles 2931 # Number of cycles rename is squashing -system.cpu3.rename.IdleCycles 33475 # Number of cycles rename is idle -system.cpu3.rename.BlockCycles 14026 # Number of cycles rename is blocking -system.cpu3.rename.serializeStallCycles 13970 # count of cycles rename stalled for serializing inst -system.cpu3.rename.RunCycles 105232 # Number of cycles rename is running -system.cpu3.rename.UnblockCycles 8844 # Number of cycles rename is unblocking -system.cpu3.rename.RenamedInsts 325744 # Number of instructions processed by rename -system.cpu3.rename.IQFullEvents 27 # Number of times rename has blocked due to IQ full -system.cpu3.rename.LSQFullEvents 59 # Number of times rename has blocked due to LSQ full -system.cpu3.rename.RenamedOperands 228226 # Number of destination operands rename has renamed -system.cpu3.rename.RenameLookups 629601 # Number of register rename lookups that rename has made -system.cpu3.rename.int_rename_lookups 629601 # Number of integer rename lookups -system.cpu3.rename.CommittedMaps 212325 # Number of HB maps that are committed -system.cpu3.rename.UndoneMaps 15901 # Number of HB maps that are undone due to squashing -system.cpu3.rename.serializingInsts 1261 # count of serializing insts renamed -system.cpu3.rename.tempSerializingInsts 1383 # count of temporary serializing insts renamed -system.cpu3.rename.skidInsts 11670 # count of insts added to the skid buffer -system.cpu3.memDep0.insertedLoads 93735 # Number of loads inserted to the mem dependence unit. -system.cpu3.memDep0.insertedStores 45116 # Number of stores inserted to the mem dependence unit. -system.cpu3.memDep0.conflictingLoads 44692 # Number of conflicting loads. -system.cpu3.memDep0.conflictingStores 39822 # Number of conflicting stores. -system.cpu3.iq.iqInstsAdded 270564 # Number of instructions added to the IQ (excludes non-spec) -system.cpu3.iq.iqNonSpecInstsAdded 6038 # Number of non-speculative instructions added to the IQ -system.cpu3.iq.iqInstsIssued 271349 # Number of instructions issued +system.cpu3.fetch.rateDist::total 187456 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.branchRate 0.281219 # Number of branch fetches per cycle +system.cpu3.fetch.rate 1.554935 # Number of inst fetches per cycle +system.cpu3.decode.IdleCycles 37941 # Number of cycles decode is idle +system.cpu3.decode.BlockedCycles 35250 # Number of cycles decode is blocked +system.cpu3.decode.RunCycles 98653 # Number of cycles decode is running +system.cpu3.decode.UnblockCycles 6106 # Number of cycles decode is unblocking +system.cpu3.decode.SquashCycles 2763 # Number of cycles decode is squashing +system.cpu3.decode.DecodedInsts 292333 # Number of instructions handled by decode +system.cpu3.rename.SquashCycles 2763 # Number of cycles rename is squashing +system.cpu3.rename.IdleCycles 38724 # Number of cycles rename is idle +system.cpu3.rename.BlockCycles 18900 # Number of cycles rename is blocking +system.cpu3.rename.serializeStallCycles 15518 # count of cycles rename stalled for serializing inst +system.cpu3.rename.RunCycles 92845 # Number of cycles rename is running +system.cpu3.rename.UnblockCycles 11963 # Number of cycles rename is unblocking +system.cpu3.rename.RenamedInsts 289904 # Number of instructions processed by rename +system.cpu3.rename.IQFullEvents 5 # Number of times rename has blocked due to IQ full +system.cpu3.rename.LSQFullEvents 41 # Number of times rename has blocked due to LSQ full +system.cpu3.rename.RenamedOperands 201915 # Number of destination operands rename has renamed +system.cpu3.rename.RenameLookups 552179 # Number of register rename lookups that rename has made +system.cpu3.rename.int_rename_lookups 552179 # Number of integer rename lookups +system.cpu3.rename.CommittedMaps 186764 # Number of HB maps that are committed +system.cpu3.rename.UndoneMaps 15151 # Number of HB maps that are undone due to squashing +system.cpu3.rename.serializingInsts 1285 # count of serializing insts renamed +system.cpu3.rename.tempSerializingInsts 1418 # count of temporary serializing insts renamed +system.cpu3.rename.skidInsts 14719 # count of insts added to the skid buffer +system.cpu3.memDep0.insertedLoads 81367 # Number of loads inserted to the mem dependence unit. +system.cpu3.memDep0.insertedStores 38245 # Number of stores inserted to the mem dependence unit. +system.cpu3.memDep0.conflictingLoads 39205 # Number of conflicting loads. +system.cpu3.memDep0.conflictingStores 32957 # Number of conflicting stores. +system.cpu3.iq.iqInstsAdded 238924 # Number of instructions added to the IQ (excludes non-spec) +system.cpu3.iq.iqNonSpecInstsAdded 7473 # Number of non-speculative instructions added to the IQ +system.cpu3.iq.iqInstsIssued 241868 # Number of instructions issued system.cpu3.iq.iqSquashedInstsIssued 117 # Number of squashed instructions issued -system.cpu3.iq.iqSquashedInstsExamined 13410 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu3.iq.iqSquashedOperandsExamined 12382 # Number of squashed operands that are examined and possibly removed from graph -system.cpu3.iq.iqSquashedNonSpecRemoved 838 # Number of squashed non-spec instructions that were removed -system.cpu3.iq.issued_per_cycle::samples 185045 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::mean 1.466395 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::stdev 1.313251 # Number of insts issued each cycle +system.cpu3.iq.iqSquashedInstsExamined 12521 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu3.iq.iqSquashedOperandsExamined 10991 # Number of squashed operands that are examined and possibly removed from graph +system.cpu3.iq.iqSquashedNonSpecRemoved 722 # Number of squashed non-spec instructions that were removed +system.cpu3.iq.issued_per_cycle::samples 187456 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::mean 1.290265 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::stdev 1.307286 # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::0 67828 36.65% 36.65% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::1 21223 11.47% 48.12% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::2 45218 24.44% 72.56% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::3 45760 24.73% 97.29% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::4 3300 1.78% 99.07% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::5 1261 0.68% 99.75% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::6 341 0.18% 99.94% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::0 79218 42.26% 42.26% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::1 25849 13.79% 56.05% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::2 38415 20.49% 76.54% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::3 38999 20.80% 97.35% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::4 3297 1.76% 99.10% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::5 1241 0.66% 99.77% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::6 322 0.17% 99.94% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::7 53 0.03% 99.97% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::8 61 0.03% 100.00% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::8 62 0.03% 100.00% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::total 185045 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::total 187456 # Number of insts issued each cycle system.cpu3.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntAlu 21 6.80% 6.80% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntMult 0 0.00% 6.80% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntDiv 0 0.00% 6.80% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatAdd 0 0.00% 6.80% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatCmp 0 0.00% 6.80% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatCvt 0 0.00% 6.80% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatMult 0 0.00% 6.80% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatDiv 0 0.00% 6.80% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 6.80% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAdd 0 0.00% 6.80% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 6.80% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAlu 0 0.00% 6.80% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdCmp 0 0.00% 6.80% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdCvt 0 0.00% 6.80% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMisc 0 0.00% 6.80% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMult 0 0.00% 6.80% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 6.80% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdShift 0 0.00% 6.80% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 6.80% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 6.80% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 6.80% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 6.80% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 6.80% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 6.80% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 6.80% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 6.80% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 6.80% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.80% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 6.80% # attempts to use FU when none available -system.cpu3.iq.fu_full::MemRead 78 25.24% 32.04% # attempts to use FU when none available -system.cpu3.iq.fu_full::MemWrite 210 67.96% 100.00% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntAlu 22 7.19% 7.19% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntMult 0 0.00% 7.19% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntDiv 0 0.00% 7.19% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatAdd 0 0.00% 7.19% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatCmp 0 0.00% 7.19% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatCvt 0 0.00% 7.19% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatMult 0 0.00% 7.19% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatDiv 0 0.00% 7.19% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 7.19% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAdd 0 0.00% 7.19% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 7.19% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAlu 0 0.00% 7.19% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdCmp 0 0.00% 7.19% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdCvt 0 0.00% 7.19% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMisc 0 0.00% 7.19% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMult 0 0.00% 7.19% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 7.19% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdShift 0 0.00% 7.19% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 7.19% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 7.19% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 7.19% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 7.19% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 7.19% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 7.19% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 7.19% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 7.19% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 7.19% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 7.19% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 7.19% # attempts to use FU when none available +system.cpu3.iq.fu_full::MemRead 74 24.18% 31.37% # attempts to use FU when none available +system.cpu3.iq.fu_full::MemWrite 210 68.63% 100.00% # attempts to use FU when none available system.cpu3.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu3.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu3.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu3.iq.FU_type_0::IntAlu 129621 47.77% 47.77% # Type of FU issued -system.cpu3.iq.FU_type_0::IntMult 0 0.00% 47.77% # Type of FU issued -system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 47.77% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 47.77% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 47.77% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 47.77% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 47.77% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 47.77% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 47.77% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 47.77% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 47.77% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 47.77% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 47.77% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 47.77% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 47.77% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 47.77% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 47.77% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 47.77% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 47.77% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 47.77% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.77% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.77% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.77% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.77% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.77% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMisc 0 0.00% 47.77% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 47.77% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.77% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.77% # Type of FU issued -system.cpu3.iq.FU_type_0::MemRead 97351 35.88% 83.65% # Type of FU issued -system.cpu3.iq.FU_type_0::MemWrite 44377 16.35% 100.00% # Type of FU issued +system.cpu3.iq.FU_type_0::IntAlu 117603 48.62% 48.62% # Type of FU issued +system.cpu3.iq.FU_type_0::IntMult 0 0.00% 48.62% # Type of FU issued +system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 48.62% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 48.62% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 48.62% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 48.62% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 48.62% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 48.62% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 48.62% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 48.62% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 48.62% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 48.62% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 48.62% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 48.62% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 48.62% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 48.62% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 48.62% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 48.62% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.62% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 48.62% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 48.62% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.62% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 48.62% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 48.62% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 48.62% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.62% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 48.62% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.62% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.62% # Type of FU issued +system.cpu3.iq.FU_type_0::MemRead 86736 35.86% 84.48% # Type of FU issued +system.cpu3.iq.FU_type_0::MemWrite 37529 15.52% 100.00% # Type of FU issued system.cpu3.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu3.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu3.iq.FU_type_0::total 271349 # Type of FU issued -system.cpu3.iq.rate 1.448848 # Inst issue rate -system.cpu3.iq.fu_busy_cnt 309 # FU busy when requested -system.cpu3.iq.fu_busy_rate 0.001139 # FU busy rate (busy events/executed inst) -system.cpu3.iq.int_inst_queue_reads 728169 # Number of integer instruction queue reads -system.cpu3.iq.int_inst_queue_writes 290051 # Number of integer instruction queue writes -system.cpu3.iq.int_inst_queue_wakeup_accesses 269261 # Number of integer instruction queue wakeup accesses +system.cpu3.iq.FU_type_0::total 241868 # Type of FU issued +system.cpu3.iq.rate 1.267971 # Inst issue rate +system.cpu3.iq.fu_busy_cnt 306 # FU busy when requested +system.cpu3.iq.fu_busy_rate 0.001265 # FU busy rate (busy events/executed inst) +system.cpu3.iq.int_inst_queue_reads 671615 # Number of integer instruction queue reads +system.cpu3.iq.int_inst_queue_writes 258950 # Number of integer instruction queue writes +system.cpu3.iq.int_inst_queue_wakeup_accesses 239863 # Number of integer instruction queue wakeup accesses system.cpu3.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu3.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu3.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu3.iq.int_alu_accesses 271658 # Number of integer alu accesses +system.cpu3.iq.int_alu_accesses 242174 # Number of integer alu accesses system.cpu3.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu3.iew.lsq.thread0.forwLoads 39639 # Number of loads that had data forwarded from stores +system.cpu3.iew.lsq.thread0.forwLoads 32833 # Number of loads that had data forwarded from stores system.cpu3.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu3.iew.lsq.thread0.squashedLoads 2895 # Number of loads squashed -system.cpu3.iew.lsq.thread0.ignoredResponses 6 # Number of memory responses ignored because the instruction is squashed -system.cpu3.iew.lsq.thread0.memOrderViolation 39 # Number of memory ordering violations -system.cpu3.iew.lsq.thread0.squashedStores 1672 # Number of stores squashed +system.cpu3.iew.lsq.thread0.squashedLoads 2526 # Number of loads squashed +system.cpu3.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed +system.cpu3.iew.lsq.thread0.memOrderViolation 32 # Number of memory ordering violations +system.cpu3.iew.lsq.thread0.squashedStores 1583 # Number of stores squashed system.cpu3.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu3.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu3.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu3.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu3.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu3.iew.iewSquashCycles 2931 # Number of cycles IEW is squashing -system.cpu3.iew.iewBlockCycles 1690 # Number of cycles IEW is blocking +system.cpu3.iew.iewSquashCycles 2763 # Number of cycles IEW is squashing +system.cpu3.iew.iewBlockCycles 1788 # Number of cycles IEW is blocking system.cpu3.iew.iewUnblockCycles 60 # Number of cycles IEW is unblocking -system.cpu3.iew.iewDispatchedInsts 322365 # Number of instructions dispatched to IQ -system.cpu3.iew.iewDispSquashedInsts 383 # Number of squashed instructions skipped by dispatch -system.cpu3.iew.iewDispLoadInsts 93735 # Number of dispatched load instructions -system.cpu3.iew.iewDispStoreInsts 45116 # Number of dispatched store instructions -system.cpu3.iew.iewDispNonSpecInsts 1181 # Number of dispatched non-speculative instructions -system.cpu3.iew.iewIQFullEvents 62 # Number of times the IQ has become full, causing a stall +system.cpu3.iew.iewDispatchedInsts 286739 # Number of instructions dispatched to IQ +system.cpu3.iew.iewDispSquashedInsts 413 # Number of squashed instructions skipped by dispatch +system.cpu3.iew.iewDispLoadInsts 81367 # Number of dispatched load instructions +system.cpu3.iew.iewDispStoreInsts 38245 # Number of dispatched store instructions +system.cpu3.iew.iewDispNonSpecInsts 1210 # Number of dispatched non-speculative instructions +system.cpu3.iew.iewIQFullEvents 58 # Number of times the IQ has become full, causing a stall system.cpu3.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu3.iew.memOrderViolationEvents 39 # Number of memory order violations -system.cpu3.iew.predictedTakenIncorrect 528 # Number of branches that were predicted taken incorrectly -system.cpu3.iew.predictedNotTakenIncorrect 1218 # Number of branches that were predicted not taken incorrectly -system.cpu3.iew.branchMispredicts 1746 # Number of branch mispredicts detected at execute -system.cpu3.iew.iewExecutedInsts 269989 # Number of executed instructions -system.cpu3.iew.iewExecLoadInsts 92559 # Number of load instructions executed -system.cpu3.iew.iewExecSquashedInsts 1360 # Number of squashed instructions skipped in execute +system.cpu3.iew.memOrderViolationEvents 32 # Number of memory order violations +system.cpu3.iew.predictedTakenIncorrect 503 # Number of branches that were predicted taken incorrectly +system.cpu3.iew.predictedNotTakenIncorrect 1210 # Number of branches that were predicted not taken incorrectly +system.cpu3.iew.branchMispredicts 1713 # Number of branch mispredicts detected at execute +system.cpu3.iew.iewExecutedInsts 240581 # Number of executed instructions +system.cpu3.iew.iewExecLoadInsts 80413 # Number of load instructions executed +system.cpu3.iew.iewExecSquashedInsts 1287 # Number of squashed instructions skipped in execute system.cpu3.iew.exec_swp 0 # number of swp insts executed -system.cpu3.iew.exec_nop 45763 # number of nop insts executed -system.cpu3.iew.exec_refs 136843 # number of memory reference insts executed -system.cpu3.iew.exec_branches 55022 # Number of branches executed -system.cpu3.iew.exec_stores 44284 # Number of stores executed -system.cpu3.iew.exec_rate 1.441587 # Inst execution rate -system.cpu3.iew.wb_sent 269584 # cumulative count of insts sent to commit -system.cpu3.iew.wb_count 269261 # cumulative count of insts written-back -system.cpu3.iew.wb_producers 153664 # num instructions producing a value -system.cpu3.iew.wb_consumers 158539 # num instructions consuming a value +system.cpu3.iew.exec_nop 40342 # number of nop insts executed +system.cpu3.iew.exec_refs 117868 # number of memory reference insts executed +system.cpu3.iew.exec_branches 49825 # Number of branches executed +system.cpu3.iew.exec_stores 37455 # Number of stores executed +system.cpu3.iew.exec_rate 1.261224 # Inst execution rate +system.cpu3.iew.wb_sent 240146 # cumulative count of insts sent to commit +system.cpu3.iew.wb_count 239863 # cumulative count of insts written-back +system.cpu3.iew.wb_producers 134653 # num instructions producing a value +system.cpu3.iew.wb_consumers 139524 # num instructions consuming a value system.cpu3.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu3.iew.wb_rate 1.437700 # insts written-back per cycle -system.cpu3.iew.wb_fanout 0.969250 # average fanout of values written-back +system.cpu3.iew.wb_rate 1.257460 # insts written-back per cycle +system.cpu3.iew.wb_fanout 0.965088 # average fanout of values written-back system.cpu3.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu3.commit.commitCommittedInsts 306791 # The number of committed instructions -system.cpu3.commit.commitCommittedOps 306791 # The number of committed instructions -system.cpu3.commit.commitSquashedInsts 15574 # The number of squashed insts skipped by commit -system.cpu3.commit.commitNonSpecStalls 5200 # The number of times commit has been forced to stall to communicate backwards -system.cpu3.commit.branchMispredicts 1573 # The number of times a branch was mispredicted -system.cpu3.commit.committed_per_cycle::samples 175548 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::mean 1.747619 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::stdev 2.056560 # Number of insts commited each cycle +system.cpu3.commit.commitCommittedInsts 272332 # The number of committed instructions +system.cpu3.commit.commitCommittedOps 272332 # The number of committed instructions +system.cpu3.commit.commitSquashedInsts 14381 # The number of squashed insts skipped by commit +system.cpu3.commit.commitNonSpecStalls 6751 # The number of times commit has been forced to stall to communicate backwards +system.cpu3.commit.branchMispredicts 1547 # The number of times a branch was mispredicted +system.cpu3.commit.committed_per_cycle::samples 177951 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::mean 1.530376 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::stdev 1.985731 # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::0 66312 37.77% 37.77% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::1 53003 30.19% 67.97% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::2 6220 3.54% 71.51% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::3 6065 3.45% 74.97% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::4 1526 0.87% 75.83% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::5 40098 22.84% 98.68% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::6 522 0.30% 98.97% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::7 989 0.56% 99.54% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::0 79207 44.51% 44.51% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::1 47739 26.83% 71.34% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::2 6222 3.50% 74.83% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::3 7617 4.28% 79.11% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::4 1549 0.87% 79.98% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::5 33224 18.67% 98.66% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::6 582 0.33% 98.98% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::7 998 0.56% 99.54% # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::8 813 0.46% 100.00% # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::total 175548 # Number of insts commited each cycle -system.cpu3.commit.committedInsts 306791 # Number of instructions committed -system.cpu3.commit.committedOps 306791 # Number of ops (including micro ops) committed +system.cpu3.commit.committed_per_cycle::total 177951 # Number of insts commited each cycle +system.cpu3.commit.committedInsts 272332 # Number of instructions committed +system.cpu3.commit.committedOps 272332 # Number of ops (including micro ops) committed system.cpu3.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu3.commit.refs 134284 # Number of memory references committed -system.cpu3.commit.loads 90840 # Number of loads committed -system.cpu3.commit.membars 4481 # Number of memory barriers committed -system.cpu3.commit.branches 53890 # Number of branches committed +system.cpu3.commit.refs 115503 # Number of memory references committed +system.cpu3.commit.loads 78841 # Number of loads committed +system.cpu3.commit.membars 6036 # Number of memory barriers committed +system.cpu3.commit.branches 48661 # Number of branches committed system.cpu3.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu3.commit.int_insts 210289 # Number of committed integer instructions. +system.cpu3.commit.int_insts 186284 # Number of committed integer instructions. system.cpu3.commit.function_calls 322 # Number of function calls committed. system.cpu3.commit.bw_lim_events 813 # number cycles where commit BW limit reached system.cpu3.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu3.rob.rob_reads 496513 # The number of ROB reads -system.cpu3.rob.rob_writes 647676 # The number of ROB writes -system.cpu3.timesIdled 218 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu3.idleCycles 2241 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu3.quiesceCycles 35902 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu3.committedInsts 257635 # Number of Instructions Simulated -system.cpu3.committedOps 257635 # Number of Ops (including micro ops) Simulated -system.cpu3.committedInsts_total 257635 # Number of Instructions Simulated -system.cpu3.cpi 0.726943 # CPI: Cycles Per Instruction -system.cpu3.cpi_total 0.726943 # CPI: Total CPI of All Threads -system.cpu3.ipc 1.375623 # IPC: Instructions Per Cycle -system.cpu3.ipc_total 1.375623 # IPC: Total IPC of All Threads -system.cpu3.int_regfile_reads 470214 # number of integer regfile reads -system.cpu3.int_regfile_writes 218594 # number of integer regfile writes +system.cpu3.rob.rob_reads 463264 # The number of ROB reads +system.cpu3.rob.rob_writes 576197 # The number of ROB writes +system.cpu3.timesIdled 226 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu3.idleCycles 3296 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu3.quiesceCycles 37130 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu3.committedInsts 226846 # Number of Instructions Simulated +system.cpu3.committedOps 226846 # Number of Ops (including micro ops) Simulated +system.cpu3.committedInsts_total 226846 # Number of Instructions Simulated +system.cpu3.cpi 0.840888 # CPI: Cycles Per Instruction +system.cpu3.cpi_total 0.840888 # CPI: Total CPI of All Threads +system.cpu3.ipc 1.189220 # IPC: Instructions Per Cycle +system.cpu3.ipc_total 1.189220 # IPC: Total IPC of All Threads +system.cpu3.int_regfile_reads 413495 # number of integer regfile reads +system.cpu3.int_regfile_writes 192863 # number of integer regfile writes system.cpu3.fp_regfile_writes 64 # number of floating regfile writes -system.cpu3.misc_regfile_reads 138505 # number of misc regfile reads +system.cpu3.misc_regfile_reads 119579 # number of misc regfile reads system.cpu3.misc_regfile_writes 646 # number of misc regfile writes -system.cpu3.icache.replacements 322 # number of replacements -system.cpu3.icache.tagsinuse 87.207959 # Cycle average of tags in use -system.cpu3.icache.total_refs 18566 # Total number of references to valid blocks. -system.cpu3.icache.sampled_refs 436 # Sample count of references to valid blocks. -system.cpu3.icache.avg_refs 42.582569 # Average number of references to valid blocks. +system.cpu3.icache.replacements 323 # number of replacements +system.cpu3.icache.tagsinuse 88.254899 # Cycle average of tags in use +system.cpu3.icache.total_refs 21999 # Total number of references to valid blocks. +system.cpu3.icache.sampled_refs 439 # Sample count of references to valid blocks. +system.cpu3.icache.avg_refs 50.111617 # Average number of references to valid blocks. system.cpu3.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.icache.occ_blocks::cpu3.inst 87.207959 # Average occupied blocks per requestor -system.cpu3.icache.occ_percent::cpu3.inst 0.170328 # Average percentage of cache occupancy -system.cpu3.icache.occ_percent::total 0.170328 # Average percentage of cache occupancy -system.cpu3.icache.ReadReq_hits::cpu3.inst 18566 # number of ReadReq hits -system.cpu3.icache.ReadReq_hits::total 18566 # number of ReadReq hits -system.cpu3.icache.demand_hits::cpu3.inst 18566 # number of demand (read+write) hits -system.cpu3.icache.demand_hits::total 18566 # number of demand (read+write) hits -system.cpu3.icache.overall_hits::cpu3.inst 18566 # number of overall hits -system.cpu3.icache.overall_hits::total 18566 # number of overall hits -system.cpu3.icache.ReadReq_misses::cpu3.inst 496 # number of ReadReq misses -system.cpu3.icache.ReadReq_misses::total 496 # number of ReadReq misses -system.cpu3.icache.demand_misses::cpu3.inst 496 # number of demand (read+write) misses -system.cpu3.icache.demand_misses::total 496 # number of demand (read+write) misses -system.cpu3.icache.overall_misses::cpu3.inst 496 # number of overall misses -system.cpu3.icache.overall_misses::total 496 # number of overall misses -system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 6966500 # number of ReadReq miss cycles -system.cpu3.icache.ReadReq_miss_latency::total 6966500 # number of ReadReq miss cycles -system.cpu3.icache.demand_miss_latency::cpu3.inst 6966500 # number of demand (read+write) miss cycles -system.cpu3.icache.demand_miss_latency::total 6966500 # number of demand (read+write) miss cycles -system.cpu3.icache.overall_miss_latency::cpu3.inst 6966500 # number of overall miss cycles -system.cpu3.icache.overall_miss_latency::total 6966500 # number of overall miss cycles -system.cpu3.icache.ReadReq_accesses::cpu3.inst 19062 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.ReadReq_accesses::total 19062 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.demand_accesses::cpu3.inst 19062 # number of demand (read+write) accesses -system.cpu3.icache.demand_accesses::total 19062 # number of demand (read+write) accesses -system.cpu3.icache.overall_accesses::cpu3.inst 19062 # number of overall (read+write) accesses -system.cpu3.icache.overall_accesses::total 19062 # number of overall (read+write) accesses -system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.026020 # miss rate for ReadReq accesses -system.cpu3.icache.ReadReq_miss_rate::total 0.026020 # miss rate for ReadReq accesses -system.cpu3.icache.demand_miss_rate::cpu3.inst 0.026020 # miss rate for demand accesses -system.cpu3.icache.demand_miss_rate::total 0.026020 # miss rate for demand accesses -system.cpu3.icache.overall_miss_rate::cpu3.inst 0.026020 # miss rate for overall accesses -system.cpu3.icache.overall_miss_rate::total 0.026020 # miss rate for overall accesses -system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 14045.362903 # average ReadReq miss latency -system.cpu3.icache.ReadReq_avg_miss_latency::total 14045.362903 # average ReadReq miss latency -system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 14045.362903 # average overall miss latency -system.cpu3.icache.demand_avg_miss_latency::total 14045.362903 # average overall miss latency -system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 14045.362903 # average overall miss latency -system.cpu3.icache.overall_avg_miss_latency::total 14045.362903 # average overall miss latency +system.cpu3.icache.occ_blocks::cpu3.inst 88.254899 # Average occupied blocks per requestor +system.cpu3.icache.occ_percent::cpu3.inst 0.172373 # Average percentage of cache occupancy +system.cpu3.icache.occ_percent::total 0.172373 # Average percentage of cache occupancy +system.cpu3.icache.ReadReq_hits::cpu3.inst 21999 # number of ReadReq hits +system.cpu3.icache.ReadReq_hits::total 21999 # number of ReadReq hits +system.cpu3.icache.demand_hits::cpu3.inst 21999 # number of demand (read+write) hits +system.cpu3.icache.demand_hits::total 21999 # number of demand (read+write) hits +system.cpu3.icache.overall_hits::cpu3.inst 21999 # number of overall hits +system.cpu3.icache.overall_hits::total 21999 # number of overall hits +system.cpu3.icache.ReadReq_misses::cpu3.inst 504 # number of ReadReq misses +system.cpu3.icache.ReadReq_misses::total 504 # number of ReadReq misses +system.cpu3.icache.demand_misses::cpu3.inst 504 # number of demand (read+write) misses +system.cpu3.icache.demand_misses::total 504 # number of demand (read+write) misses +system.cpu3.icache.overall_misses::cpu3.inst 504 # number of overall misses +system.cpu3.icache.overall_misses::total 504 # number of overall misses +system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 7701000 # number of ReadReq miss cycles +system.cpu3.icache.ReadReq_miss_latency::total 7701000 # number of ReadReq miss cycles +system.cpu3.icache.demand_miss_latency::cpu3.inst 7701000 # number of demand (read+write) miss cycles +system.cpu3.icache.demand_miss_latency::total 7701000 # number of demand (read+write) miss cycles +system.cpu3.icache.overall_miss_latency::cpu3.inst 7701000 # number of overall miss cycles +system.cpu3.icache.overall_miss_latency::total 7701000 # number of overall miss cycles +system.cpu3.icache.ReadReq_accesses::cpu3.inst 22503 # number of ReadReq accesses(hits+misses) +system.cpu3.icache.ReadReq_accesses::total 22503 # number of ReadReq accesses(hits+misses) +system.cpu3.icache.demand_accesses::cpu3.inst 22503 # number of demand (read+write) accesses +system.cpu3.icache.demand_accesses::total 22503 # number of demand (read+write) accesses +system.cpu3.icache.overall_accesses::cpu3.inst 22503 # number of overall (read+write) accesses +system.cpu3.icache.overall_accesses::total 22503 # number of overall (read+write) accesses +system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.022397 # miss rate for ReadReq accesses +system.cpu3.icache.ReadReq_miss_rate::total 0.022397 # miss rate for ReadReq accesses +system.cpu3.icache.demand_miss_rate::cpu3.inst 0.022397 # miss rate for demand accesses +system.cpu3.icache.demand_miss_rate::total 0.022397 # miss rate for demand accesses +system.cpu3.icache.overall_miss_rate::cpu3.inst 0.022397 # miss rate for overall accesses +system.cpu3.icache.overall_miss_rate::total 0.022397 # miss rate for overall accesses +system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 15279.761905 # average ReadReq miss latency +system.cpu3.icache.ReadReq_avg_miss_latency::total 15279.761905 # average ReadReq miss latency +system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 15279.761905 # average overall miss latency +system.cpu3.icache.demand_avg_miss_latency::total 15279.761905 # average overall miss latency +system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 15279.761905 # average overall miss latency +system.cpu3.icache.overall_avg_miss_latency::total 15279.761905 # average overall miss latency system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1805,106 +1805,106 @@ system.cpu3.icache.avg_blocked_cycles::no_mshrs nan system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu3.icache.fast_writes 0 # number of fast writes performed system.cpu3.icache.cache_copies 0 # number of cache copies performed -system.cpu3.icache.ReadReq_mshr_hits::cpu3.inst 60 # number of ReadReq MSHR hits -system.cpu3.icache.ReadReq_mshr_hits::total 60 # number of ReadReq MSHR hits -system.cpu3.icache.demand_mshr_hits::cpu3.inst 60 # number of demand (read+write) MSHR hits -system.cpu3.icache.demand_mshr_hits::total 60 # number of demand (read+write) MSHR hits -system.cpu3.icache.overall_mshr_hits::cpu3.inst 60 # number of overall MSHR hits -system.cpu3.icache.overall_mshr_hits::total 60 # number of overall MSHR hits -system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst 436 # number of ReadReq MSHR misses -system.cpu3.icache.ReadReq_mshr_misses::total 436 # number of ReadReq MSHR misses -system.cpu3.icache.demand_mshr_misses::cpu3.inst 436 # number of demand (read+write) MSHR misses -system.cpu3.icache.demand_mshr_misses::total 436 # number of demand (read+write) MSHR misses -system.cpu3.icache.overall_mshr_misses::cpu3.inst 436 # number of overall MSHR misses -system.cpu3.icache.overall_mshr_misses::total 436 # number of overall MSHR misses -system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 5084500 # number of ReadReq MSHR miss cycles -system.cpu3.icache.ReadReq_mshr_miss_latency::total 5084500 # number of ReadReq MSHR miss cycles -system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 5084500 # number of demand (read+write) MSHR miss cycles -system.cpu3.icache.demand_mshr_miss_latency::total 5084500 # number of demand (read+write) MSHR miss cycles -system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 5084500 # number of overall MSHR miss cycles -system.cpu3.icache.overall_mshr_miss_latency::total 5084500 # number of overall MSHR miss cycles -system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.022873 # mshr miss rate for ReadReq accesses -system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.022873 # mshr miss rate for ReadReq accesses -system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.022873 # mshr miss rate for demand accesses -system.cpu3.icache.demand_mshr_miss_rate::total 0.022873 # mshr miss rate for demand accesses -system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.022873 # mshr miss rate for overall accesses -system.cpu3.icache.overall_mshr_miss_rate::total 0.022873 # mshr miss rate for overall accesses -system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 11661.697248 # average ReadReq mshr miss latency -system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 11661.697248 # average ReadReq mshr miss latency -system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 11661.697248 # average overall mshr miss latency -system.cpu3.icache.demand_avg_mshr_miss_latency::total 11661.697248 # average overall mshr miss latency -system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 11661.697248 # average overall mshr miss latency -system.cpu3.icache.overall_avg_mshr_miss_latency::total 11661.697248 # average overall mshr miss latency +system.cpu3.icache.ReadReq_mshr_hits::cpu3.inst 65 # number of ReadReq MSHR hits +system.cpu3.icache.ReadReq_mshr_hits::total 65 # number of ReadReq MSHR hits +system.cpu3.icache.demand_mshr_hits::cpu3.inst 65 # number of demand (read+write) MSHR hits +system.cpu3.icache.demand_mshr_hits::total 65 # number of demand (read+write) MSHR hits +system.cpu3.icache.overall_mshr_hits::cpu3.inst 65 # number of overall MSHR hits +system.cpu3.icache.overall_mshr_hits::total 65 # number of overall MSHR hits +system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst 439 # number of ReadReq MSHR misses +system.cpu3.icache.ReadReq_mshr_misses::total 439 # number of ReadReq MSHR misses +system.cpu3.icache.demand_mshr_misses::cpu3.inst 439 # number of demand (read+write) MSHR misses +system.cpu3.icache.demand_mshr_misses::total 439 # number of demand (read+write) MSHR misses +system.cpu3.icache.overall_mshr_misses::cpu3.inst 439 # number of overall MSHR misses +system.cpu3.icache.overall_mshr_misses::total 439 # number of overall MSHR misses +system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 5678000 # number of ReadReq MSHR miss cycles +system.cpu3.icache.ReadReq_mshr_miss_latency::total 5678000 # number of ReadReq MSHR miss cycles +system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 5678000 # number of demand (read+write) MSHR miss cycles +system.cpu3.icache.demand_mshr_miss_latency::total 5678000 # number of demand (read+write) MSHR miss cycles +system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 5678000 # number of overall MSHR miss cycles +system.cpu3.icache.overall_mshr_miss_latency::total 5678000 # number of overall MSHR miss cycles +system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.019509 # mshr miss rate for ReadReq accesses +system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.019509 # mshr miss rate for ReadReq accesses +system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.019509 # mshr miss rate for demand accesses +system.cpu3.icache.demand_mshr_miss_rate::total 0.019509 # mshr miss rate for demand accesses +system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.019509 # mshr miss rate for overall accesses +system.cpu3.icache.overall_mshr_miss_rate::total 0.019509 # mshr miss rate for overall accesses +system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12933.940774 # average ReadReq mshr miss latency +system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 12933.940774 # average ReadReq mshr miss latency +system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 12933.940774 # average overall mshr miss latency +system.cpu3.icache.demand_avg_mshr_miss_latency::total 12933.940774 # average overall mshr miss latency +system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 12933.940774 # average overall mshr miss latency +system.cpu3.icache.overall_avg_mshr_miss_latency::total 12933.940774 # average overall mshr miss latency system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu3.dcache.replacements 0 # number of replacements -system.cpu3.dcache.tagsinuse 26.205436 # Cycle average of tags in use -system.cpu3.dcache.total_refs 49620 # Total number of references to valid blocks. +system.cpu3.dcache.tagsinuse 26.059158 # Cycle average of tags in use +system.cpu3.dcache.total_refs 42792 # Total number of references to valid blocks. system.cpu3.dcache.sampled_refs 28 # Sample count of references to valid blocks. -system.cpu3.dcache.avg_refs 1772.142857 # Average number of references to valid blocks. +system.cpu3.dcache.avg_refs 1528.285714 # Average number of references to valid blocks. system.cpu3.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.dcache.occ_blocks::cpu3.data 26.205436 # Average occupied blocks per requestor -system.cpu3.dcache.occ_percent::cpu3.data 0.051182 # Average percentage of cache occupancy -system.cpu3.dcache.occ_percent::total 0.051182 # Average percentage of cache occupancy -system.cpu3.dcache.ReadReq_hits::cpu3.data 52477 # number of ReadReq hits -system.cpu3.dcache.ReadReq_hits::total 52477 # number of ReadReq hits -system.cpu3.dcache.WriteReq_hits::cpu3.data 43221 # number of WriteReq hits -system.cpu3.dcache.WriteReq_hits::total 43221 # number of WriteReq hits -system.cpu3.dcache.SwapReq_hits::cpu3.data 12 # number of SwapReq hits -system.cpu3.dcache.SwapReq_hits::total 12 # number of SwapReq hits -system.cpu3.dcache.demand_hits::cpu3.data 95698 # number of demand (read+write) hits -system.cpu3.dcache.demand_hits::total 95698 # number of demand (read+write) hits -system.cpu3.dcache.overall_hits::cpu3.data 95698 # number of overall hits -system.cpu3.dcache.overall_hits::total 95698 # number of overall hits -system.cpu3.dcache.ReadReq_misses::cpu3.data 424 # number of ReadReq misses -system.cpu3.dcache.ReadReq_misses::total 424 # number of ReadReq misses -system.cpu3.dcache.WriteReq_misses::cpu3.data 150 # number of WriteReq misses -system.cpu3.dcache.WriteReq_misses::total 150 # number of WriteReq misses -system.cpu3.dcache.SwapReq_misses::cpu3.data 61 # number of SwapReq misses -system.cpu3.dcache.SwapReq_misses::total 61 # number of SwapReq misses -system.cpu3.dcache.demand_misses::cpu3.data 574 # number of demand (read+write) misses -system.cpu3.dcache.demand_misses::total 574 # number of demand (read+write) misses -system.cpu3.dcache.overall_misses::cpu3.data 574 # number of overall misses -system.cpu3.dcache.overall_misses::total 574 # number of overall misses -system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 8617000 # number of ReadReq miss cycles -system.cpu3.dcache.ReadReq_miss_latency::total 8617000 # number of ReadReq miss cycles -system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 2850000 # number of WriteReq miss cycles -system.cpu3.dcache.WriteReq_miss_latency::total 2850000 # number of WriteReq miss cycles -system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 1161500 # number of SwapReq miss cycles -system.cpu3.dcache.SwapReq_miss_latency::total 1161500 # number of SwapReq miss cycles -system.cpu3.dcache.demand_miss_latency::cpu3.data 11467000 # number of demand (read+write) miss cycles -system.cpu3.dcache.demand_miss_latency::total 11467000 # number of demand (read+write) miss cycles -system.cpu3.dcache.overall_miss_latency::cpu3.data 11467000 # number of overall miss cycles -system.cpu3.dcache.overall_miss_latency::total 11467000 # number of overall miss cycles -system.cpu3.dcache.ReadReq_accesses::cpu3.data 52901 # number of ReadReq accesses(hits+misses) -system.cpu3.dcache.ReadReq_accesses::total 52901 # number of ReadReq accesses(hits+misses) -system.cpu3.dcache.WriteReq_accesses::cpu3.data 43371 # number of WriteReq accesses(hits+misses) -system.cpu3.dcache.WriteReq_accesses::total 43371 # number of WriteReq accesses(hits+misses) -system.cpu3.dcache.SwapReq_accesses::cpu3.data 73 # number of SwapReq accesses(hits+misses) -system.cpu3.dcache.SwapReq_accesses::total 73 # number of SwapReq accesses(hits+misses) -system.cpu3.dcache.demand_accesses::cpu3.data 96272 # number of demand (read+write) accesses -system.cpu3.dcache.demand_accesses::total 96272 # number of demand (read+write) accesses -system.cpu3.dcache.overall_accesses::cpu3.data 96272 # number of overall (read+write) accesses -system.cpu3.dcache.overall_accesses::total 96272 # number of overall (read+write) accesses -system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.008015 # miss rate for ReadReq accesses -system.cpu3.dcache.ReadReq_miss_rate::total 0.008015 # miss rate for ReadReq accesses -system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.003459 # miss rate for WriteReq accesses -system.cpu3.dcache.WriteReq_miss_rate::total 0.003459 # miss rate for WriteReq accesses -system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.835616 # miss rate for SwapReq accesses -system.cpu3.dcache.SwapReq_miss_rate::total 0.835616 # miss rate for SwapReq accesses -system.cpu3.dcache.demand_miss_rate::cpu3.data 0.005962 # miss rate for demand accesses -system.cpu3.dcache.demand_miss_rate::total 0.005962 # miss rate for demand accesses -system.cpu3.dcache.overall_miss_rate::cpu3.data 0.005962 # miss rate for overall accesses -system.cpu3.dcache.overall_miss_rate::total 0.005962 # miss rate for overall accesses -system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 20323.113208 # average ReadReq miss latency -system.cpu3.dcache.ReadReq_avg_miss_latency::total 20323.113208 # average ReadReq miss latency -system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 19000 # average WriteReq miss latency -system.cpu3.dcache.WriteReq_avg_miss_latency::total 19000 # average WriteReq miss latency -system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 19040.983607 # average SwapReq miss latency -system.cpu3.dcache.SwapReq_avg_miss_latency::total 19040.983607 # average SwapReq miss latency -system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 19977.351916 # average overall miss latency -system.cpu3.dcache.demand_avg_miss_latency::total 19977.351916 # average overall miss latency -system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 19977.351916 # average overall miss latency -system.cpu3.dcache.overall_avg_miss_latency::total 19977.351916 # average overall miss latency +system.cpu3.dcache.occ_blocks::cpu3.data 26.059158 # Average occupied blocks per requestor +system.cpu3.dcache.occ_percent::cpu3.data 0.050897 # Average percentage of cache occupancy +system.cpu3.dcache.occ_percent::total 0.050897 # Average percentage of cache occupancy +system.cpu3.dcache.ReadReq_hits::cpu3.data 47204 # number of ReadReq hits +system.cpu3.dcache.ReadReq_hits::total 47204 # number of ReadReq hits +system.cpu3.dcache.WriteReq_hits::cpu3.data 36453 # number of WriteReq hits +system.cpu3.dcache.WriteReq_hits::total 36453 # number of WriteReq hits +system.cpu3.dcache.SwapReq_hits::cpu3.data 14 # number of SwapReq hits +system.cpu3.dcache.SwapReq_hits::total 14 # number of SwapReq hits +system.cpu3.dcache.demand_hits::cpu3.data 83657 # number of demand (read+write) hits +system.cpu3.dcache.demand_hits::total 83657 # number of demand (read+write) hits +system.cpu3.dcache.overall_hits::cpu3.data 83657 # number of overall hits +system.cpu3.dcache.overall_hits::total 83657 # number of overall hits +system.cpu3.dcache.ReadReq_misses::cpu3.data 361 # number of ReadReq misses +system.cpu3.dcache.ReadReq_misses::total 361 # number of ReadReq misses +system.cpu3.dcache.WriteReq_misses::cpu3.data 140 # number of WriteReq misses +system.cpu3.dcache.WriteReq_misses::total 140 # number of WriteReq misses +system.cpu3.dcache.SwapReq_misses::cpu3.data 55 # number of SwapReq misses +system.cpu3.dcache.SwapReq_misses::total 55 # number of SwapReq misses +system.cpu3.dcache.demand_misses::cpu3.data 501 # number of demand (read+write) misses +system.cpu3.dcache.demand_misses::total 501 # number of demand (read+write) misses +system.cpu3.dcache.overall_misses::cpu3.data 501 # number of overall misses +system.cpu3.dcache.overall_misses::total 501 # number of overall misses +system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 9450000 # number of ReadReq miss cycles +system.cpu3.dcache.ReadReq_miss_latency::total 9450000 # number of ReadReq miss cycles +system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 3328500 # number of WriteReq miss cycles +system.cpu3.dcache.WriteReq_miss_latency::total 3328500 # number of WriteReq miss cycles +system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 1305500 # number of SwapReq miss cycles +system.cpu3.dcache.SwapReq_miss_latency::total 1305500 # number of SwapReq miss cycles +system.cpu3.dcache.demand_miss_latency::cpu3.data 12778500 # number of demand (read+write) miss cycles +system.cpu3.dcache.demand_miss_latency::total 12778500 # number of demand (read+write) miss cycles +system.cpu3.dcache.overall_miss_latency::cpu3.data 12778500 # number of overall miss cycles +system.cpu3.dcache.overall_miss_latency::total 12778500 # number of overall miss cycles +system.cpu3.dcache.ReadReq_accesses::cpu3.data 47565 # number of ReadReq accesses(hits+misses) +system.cpu3.dcache.ReadReq_accesses::total 47565 # number of ReadReq accesses(hits+misses) +system.cpu3.dcache.WriteReq_accesses::cpu3.data 36593 # number of WriteReq accesses(hits+misses) +system.cpu3.dcache.WriteReq_accesses::total 36593 # number of WriteReq accesses(hits+misses) +system.cpu3.dcache.SwapReq_accesses::cpu3.data 69 # number of SwapReq accesses(hits+misses) +system.cpu3.dcache.SwapReq_accesses::total 69 # number of SwapReq accesses(hits+misses) +system.cpu3.dcache.demand_accesses::cpu3.data 84158 # number of demand (read+write) accesses +system.cpu3.dcache.demand_accesses::total 84158 # number of demand (read+write) accesses +system.cpu3.dcache.overall_accesses::cpu3.data 84158 # number of overall (read+write) accesses +system.cpu3.dcache.overall_accesses::total 84158 # number of overall (read+write) accesses +system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.007590 # miss rate for ReadReq accesses +system.cpu3.dcache.ReadReq_miss_rate::total 0.007590 # miss rate for ReadReq accesses +system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.003826 # miss rate for WriteReq accesses +system.cpu3.dcache.WriteReq_miss_rate::total 0.003826 # miss rate for WriteReq accesses +system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.797101 # miss rate for SwapReq accesses +system.cpu3.dcache.SwapReq_miss_rate::total 0.797101 # miss rate for SwapReq accesses +system.cpu3.dcache.demand_miss_rate::cpu3.data 0.005953 # miss rate for demand accesses +system.cpu3.dcache.demand_miss_rate::total 0.005953 # miss rate for demand accesses +system.cpu3.dcache.overall_miss_rate::cpu3.data 0.005953 # miss rate for overall accesses +system.cpu3.dcache.overall_miss_rate::total 0.005953 # miss rate for overall accesses +system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 26177.285319 # average ReadReq miss latency +system.cpu3.dcache.ReadReq_avg_miss_latency::total 26177.285319 # average ReadReq miss latency +system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 23775 # average WriteReq miss latency +system.cpu3.dcache.WriteReq_avg_miss_latency::total 23775 # average WriteReq miss latency +system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 23736.363636 # average SwapReq miss latency +system.cpu3.dcache.SwapReq_avg_miss_latency::total 23736.363636 # average SwapReq miss latency +system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 25505.988024 # average overall miss latency +system.cpu3.dcache.demand_avg_miss_latency::total 25505.988024 # average overall miss latency +system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 25505.988024 # average overall miss latency +system.cpu3.dcache.overall_avg_miss_latency::total 25505.988024 # average overall miss latency system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1913,288 +1913,288 @@ system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu3.dcache.fast_writes 0 # number of fast writes performed system.cpu3.dcache.cache_copies 0 # number of cache copies performed -system.cpu3.dcache.ReadReq_mshr_hits::cpu3.data 264 # number of ReadReq MSHR hits -system.cpu3.dcache.ReadReq_mshr_hits::total 264 # number of ReadReq MSHR hits -system.cpu3.dcache.WriteReq_mshr_hits::cpu3.data 46 # number of WriteReq MSHR hits -system.cpu3.dcache.WriteReq_mshr_hits::total 46 # number of WriteReq MSHR hits -system.cpu3.dcache.demand_mshr_hits::cpu3.data 310 # number of demand (read+write) MSHR hits -system.cpu3.dcache.demand_mshr_hits::total 310 # number of demand (read+write) MSHR hits -system.cpu3.dcache.overall_mshr_hits::cpu3.data 310 # number of overall MSHR hits -system.cpu3.dcache.overall_mshr_hits::total 310 # number of overall MSHR hits -system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 160 # number of ReadReq MSHR misses -system.cpu3.dcache.ReadReq_mshr_misses::total 160 # number of ReadReq MSHR misses -system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 104 # number of WriteReq MSHR misses -system.cpu3.dcache.WriteReq_mshr_misses::total 104 # number of WriteReq MSHR misses -system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 61 # number of SwapReq MSHR misses -system.cpu3.dcache.SwapReq_mshr_misses::total 61 # number of SwapReq MSHR misses -system.cpu3.dcache.demand_mshr_misses::cpu3.data 264 # number of demand (read+write) MSHR misses -system.cpu3.dcache.demand_mshr_misses::total 264 # number of demand (read+write) MSHR misses -system.cpu3.dcache.overall_mshr_misses::cpu3.data 264 # number of overall MSHR misses -system.cpu3.dcache.overall_mshr_misses::total 264 # number of overall MSHR misses -system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 1797000 # number of ReadReq MSHR miss cycles -system.cpu3.dcache.ReadReq_mshr_miss_latency::total 1797000 # number of ReadReq MSHR miss cycles -system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1508500 # number of WriteReq MSHR miss cycles -system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1508500 # number of WriteReq MSHR miss cycles -system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 978500 # number of SwapReq MSHR miss cycles -system.cpu3.dcache.SwapReq_mshr_miss_latency::total 978500 # number of SwapReq MSHR miss cycles -system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 3305500 # number of demand (read+write) MSHR miss cycles -system.cpu3.dcache.demand_mshr_miss_latency::total 3305500 # number of demand (read+write) MSHR miss cycles -system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 3305500 # number of overall MSHR miss cycles -system.cpu3.dcache.overall_mshr_miss_latency::total 3305500 # number of overall MSHR miss cycles -system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.003025 # mshr miss rate for ReadReq accesses -system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.003025 # mshr miss rate for ReadReq accesses -system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.002398 # mshr miss rate for WriteReq accesses -system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.002398 # mshr miss rate for WriteReq accesses -system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.835616 # mshr miss rate for SwapReq accesses -system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.835616 # mshr miss rate for SwapReq accesses -system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.002742 # mshr miss rate for demand accesses -system.cpu3.dcache.demand_mshr_miss_rate::total 0.002742 # mshr miss rate for demand accesses -system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.002742 # mshr miss rate for overall accesses -system.cpu3.dcache.overall_mshr_miss_rate::total 0.002742 # mshr miss rate for overall accesses -system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 11231.250000 # average ReadReq mshr miss latency -system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 11231.250000 # average ReadReq mshr miss latency -system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 14504.807692 # average WriteReq mshr miss latency -system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 14504.807692 # average WriteReq mshr miss latency -system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 16040.983607 # average SwapReq mshr miss latency -system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 16040.983607 # average SwapReq mshr miss latency -system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 12520.833333 # average overall mshr miss latency -system.cpu3.dcache.demand_avg_mshr_miss_latency::total 12520.833333 # average overall mshr miss latency -system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 12520.833333 # average overall mshr miss latency -system.cpu3.dcache.overall_avg_mshr_miss_latency::total 12520.833333 # average overall mshr miss latency +system.cpu3.dcache.ReadReq_mshr_hits::cpu3.data 206 # number of ReadReq MSHR hits +system.cpu3.dcache.ReadReq_mshr_hits::total 206 # number of ReadReq MSHR hits +system.cpu3.dcache.WriteReq_mshr_hits::cpu3.data 33 # number of WriteReq MSHR hits +system.cpu3.dcache.WriteReq_mshr_hits::total 33 # number of WriteReq MSHR hits +system.cpu3.dcache.demand_mshr_hits::cpu3.data 239 # number of demand (read+write) MSHR hits +system.cpu3.dcache.demand_mshr_hits::total 239 # number of demand (read+write) MSHR hits +system.cpu3.dcache.overall_mshr_hits::cpu3.data 239 # number of overall MSHR hits +system.cpu3.dcache.overall_mshr_hits::total 239 # number of overall MSHR hits +system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 155 # number of ReadReq MSHR misses +system.cpu3.dcache.ReadReq_mshr_misses::total 155 # number of ReadReq MSHR misses +system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 107 # number of WriteReq MSHR misses +system.cpu3.dcache.WriteReq_mshr_misses::total 107 # number of WriteReq MSHR misses +system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 55 # number of SwapReq MSHR misses +system.cpu3.dcache.SwapReq_mshr_misses::total 55 # number of SwapReq MSHR misses +system.cpu3.dcache.demand_mshr_misses::cpu3.data 262 # number of demand (read+write) MSHR misses +system.cpu3.dcache.demand_mshr_misses::total 262 # number of demand (read+write) MSHR misses +system.cpu3.dcache.overall_mshr_misses::cpu3.data 262 # number of overall MSHR misses +system.cpu3.dcache.overall_mshr_misses::total 262 # number of overall MSHR misses +system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 2585504 # number of ReadReq MSHR miss cycles +system.cpu3.dcache.ReadReq_mshr_miss_latency::total 2585504 # number of ReadReq MSHR miss cycles +system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1735000 # number of WriteReq MSHR miss cycles +system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1735000 # number of WriteReq MSHR miss cycles +system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 1134500 # number of SwapReq MSHR miss cycles +system.cpu3.dcache.SwapReq_mshr_miss_latency::total 1134500 # number of SwapReq MSHR miss cycles +system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 4320504 # number of demand (read+write) MSHR miss cycles +system.cpu3.dcache.demand_mshr_miss_latency::total 4320504 # number of demand (read+write) MSHR miss cycles +system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 4320504 # number of overall MSHR miss cycles +system.cpu3.dcache.overall_mshr_miss_latency::total 4320504 # number of overall MSHR miss cycles +system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.003259 # mshr miss rate for ReadReq accesses +system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.003259 # mshr miss rate for ReadReq accesses +system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.002924 # mshr miss rate for WriteReq accesses +system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.002924 # mshr miss rate for WriteReq accesses +system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.797101 # mshr miss rate for SwapReq accesses +system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.797101 # mshr miss rate for SwapReq accesses +system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.003113 # mshr miss rate for demand accesses +system.cpu3.dcache.demand_mshr_miss_rate::total 0.003113 # mshr miss rate for demand accesses +system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.003113 # mshr miss rate for overall accesses +system.cpu3.dcache.overall_mshr_miss_rate::total 0.003113 # mshr miss rate for overall accesses +system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 16680.670968 # average ReadReq mshr miss latency +system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 16680.670968 # average ReadReq mshr miss latency +system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 16214.953271 # average WriteReq mshr miss latency +system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 16214.953271 # average WriteReq mshr miss latency +system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 20627.272727 # average SwapReq mshr miss latency +system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 20627.272727 # average SwapReq mshr miss latency +system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 16490.473282 # average overall mshr miss latency +system.cpu3.dcache.demand_avg_mshr_miss_latency::total 16490.473282 # average overall mshr miss latency +system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 16490.473282 # average overall mshr miss latency +system.cpu3.dcache.overall_avg_mshr_miss_latency::total 16490.473282 # average overall mshr miss latency system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.l2c.replacements 0 # number of replacements -system.l2c.tagsinuse 436.530480 # Cycle average of tags in use -system.l2c.total_refs 1479 # Total number of references to valid blocks. -system.l2c.sampled_refs 536 # Sample count of references to valid blocks. -system.l2c.avg_refs 2.759328 # Average number of references to valid blocks. +system.l2c.tagsinuse 436.890326 # Cycle average of tags in use +system.l2c.total_refs 1480 # Total number of references to valid blocks. +system.l2c.sampled_refs 538 # Sample count of references to valid blocks. +system.l2c.avg_refs 2.750929 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 0.840422 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 294.533073 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 59.606311 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 70.480803 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 5.728880 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu2.inst 1.673039 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu2.data 0.734409 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu3.inst 2.156423 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu3.data 0.777117 # Average occupied blocks per requestor +system.l2c.occ_blocks::writebacks 0.838452 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.inst 294.676580 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.data 59.534459 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.inst 68.181124 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.data 5.702984 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu2.inst 2.344879 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu2.data 0.730463 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu3.inst 4.107761 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu3.data 0.773625 # Average occupied blocks per requestor system.l2c.occ_percent::writebacks 0.000013 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.004494 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.000910 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.001075 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.inst 0.004496 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.data 0.000908 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.inst 0.001040 # Average percentage of cache occupancy system.l2c.occ_percent::cpu1.data 0.000087 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu2.inst 0.000026 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu2.inst 0.000036 # Average percentage of cache occupancy system.l2c.occ_percent::cpu2.data 0.000011 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu3.inst 0.000033 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu3.inst 0.000063 # Average percentage of cache occupancy system.l2c.occ_percent::cpu3.data 0.000012 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.006661 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.inst 238 # number of ReadReq hits +system.l2c.occ_percent::total 0.006666 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0.inst 239 # number of ReadReq hits system.l2c.ReadReq_hits::cpu0.data 5 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 347 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 350 # number of ReadReq hits system.l2c.ReadReq_hits::cpu1.data 5 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.inst 431 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.inst 428 # number of ReadReq hits system.l2c.ReadReq_hits::cpu2.data 11 # number of ReadReq hits system.l2c.ReadReq_hits::cpu3.inst 431 # number of ReadReq hits system.l2c.ReadReq_hits::cpu3.data 11 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1479 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1480 # number of ReadReq hits system.l2c.Writeback_hits::writebacks 1 # number of Writeback hits system.l2c.Writeback_hits::total 1 # number of Writeback hits system.l2c.UpgradeReq_hits::cpu0.data 3 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 3 # number of UpgradeReq hits -system.l2c.demand_hits::cpu0.inst 238 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 239 # number of demand (read+write) hits system.l2c.demand_hits::cpu0.data 5 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 347 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 350 # number of demand (read+write) hits system.l2c.demand_hits::cpu1.data 5 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.inst 431 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.inst 428 # number of demand (read+write) hits system.l2c.demand_hits::cpu2.data 11 # number of demand (read+write) hits system.l2c.demand_hits::cpu3.inst 431 # number of demand (read+write) hits system.l2c.demand_hits::cpu3.data 11 # number of demand (read+write) hits -system.l2c.demand_hits::total 1479 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.inst 238 # number of overall hits +system.l2c.demand_hits::total 1480 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.inst 239 # number of overall hits system.l2c.overall_hits::cpu0.data 5 # number of overall hits -system.l2c.overall_hits::cpu1.inst 347 # number of overall hits +system.l2c.overall_hits::cpu1.inst 350 # number of overall hits system.l2c.overall_hits::cpu1.data 5 # number of overall hits -system.l2c.overall_hits::cpu2.inst 431 # number of overall hits +system.l2c.overall_hits::cpu2.inst 428 # number of overall hits system.l2c.overall_hits::cpu2.data 11 # number of overall hits system.l2c.overall_hits::cpu3.inst 431 # number of overall hits system.l2c.overall_hits::cpu3.data 11 # number of overall hits -system.l2c.overall_hits::total 1479 # number of overall hits -system.l2c.ReadReq_misses::cpu0.inst 361 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 75 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 89 # number of ReadReq misses +system.l2c.overall_hits::total 1480 # number of overall hits +system.l2c.ReadReq_misses::cpu0.inst 363 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 74 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 86 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.data 7 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.inst 7 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu2.inst 10 # number of ReadReq misses system.l2c.ReadReq_misses::cpu2.data 1 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu3.inst 5 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu3.inst 8 # number of ReadReq misses system.l2c.ReadReq_misses::cpu3.data 1 # number of ReadReq misses -system.l2c.ReadReq_misses::total 546 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 23 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 20 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu2.data 19 # number of UpgradeReq misses +system.l2c.ReadReq_misses::total 550 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 20 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 15 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu2.data 21 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::cpu3.data 19 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 81 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 75 # number of UpgradeReq misses system.l2c.ReadExReq_misses::cpu0.data 94 # number of ReadExReq misses system.l2c.ReadExReq_misses::cpu1.data 13 # number of ReadExReq misses system.l2c.ReadExReq_misses::cpu2.data 12 # number of ReadExReq misses system.l2c.ReadExReq_misses::cpu3.data 12 # number of ReadExReq misses system.l2c.ReadExReq_misses::total 131 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.inst 361 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 169 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 89 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 363 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 168 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 86 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.data 20 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.inst 7 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2.inst 10 # number of demand (read+write) misses system.l2c.demand_misses::cpu2.data 13 # number of demand (read+write) misses -system.l2c.demand_misses::cpu3.inst 5 # number of demand (read+write) misses +system.l2c.demand_misses::cpu3.inst 8 # number of demand (read+write) misses system.l2c.demand_misses::cpu3.data 13 # number of demand (read+write) misses -system.l2c.demand_misses::total 677 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.inst 361 # number of overall misses -system.l2c.overall_misses::cpu0.data 169 # number of overall misses -system.l2c.overall_misses::cpu1.inst 89 # number of overall misses +system.l2c.demand_misses::total 681 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.inst 363 # number of overall misses +system.l2c.overall_misses::cpu0.data 168 # number of overall misses +system.l2c.overall_misses::cpu1.inst 86 # number of overall misses system.l2c.overall_misses::cpu1.data 20 # number of overall misses -system.l2c.overall_misses::cpu2.inst 7 # number of overall misses +system.l2c.overall_misses::cpu2.inst 10 # number of overall misses system.l2c.overall_misses::cpu2.data 13 # number of overall misses -system.l2c.overall_misses::cpu3.inst 5 # number of overall misses +system.l2c.overall_misses::cpu3.inst 8 # number of overall misses system.l2c.overall_misses::cpu3.data 13 # number of overall misses -system.l2c.overall_misses::total 677 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.inst 18817000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 3930500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 4612000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 366000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2.inst 304000 # number of ReadReq miss cycles +system.l2c.overall_misses::total 681 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu0.inst 19255500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.data 4177000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.inst 4495500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 377500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu2.inst 449500 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu2.data 52500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu3.inst 254000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu3.inst 388000 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu3.data 52500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 28388500 # number of ReadReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 4938500 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 681500 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu2.data 629500 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu3.data 628000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 6877500 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.inst 18817000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 8869000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 4612000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 1047500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.inst 304000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.data 682000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu3.inst 254000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu3.data 680500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 35266000 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.inst 18817000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 8869000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 4612000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 1047500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.inst 304000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.data 682000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu3.inst 254000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu3.data 680500 # number of overall miss cycles -system.l2c.overall_miss_latency::total 35266000 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.inst 599 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 80 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_miss_latency::total 29248000 # number of ReadReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 5163500 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 751000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu2.data 663000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu3.data 658499 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 7235999 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu0.inst 19255500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 9340500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 4495500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 1128500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.inst 449500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.data 715500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu3.inst 388000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu3.data 710999 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 36483999 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.inst 19255500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 9340500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 4495500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 1128500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.inst 449500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.data 715500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu3.inst 388000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu3.data 710999 # number of overall miss cycles +system.l2c.overall_miss_latency::total 36483999 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.inst 602 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 79 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu1.inst 436 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu1.data 12 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu2.inst 438 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu2.data 12 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu3.inst 436 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu3.inst 439 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu3.data 12 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2025 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2030 # number of ReadReq accesses(hits+misses) system.l2c.Writeback_accesses::writebacks 1 # number of Writeback accesses(hits+misses) system.l2c.Writeback_accesses::total 1 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 26 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 20 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu2.data 19 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 23 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 15 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu2.data 21 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu3.data 19 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 84 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 78 # number of UpgradeReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu0.data 94 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu1.data 13 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu2.data 12 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu3.data 12 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::total 131 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.inst 599 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 174 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 602 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 173 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu1.inst 436 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu1.data 25 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu2.inst 438 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu2.data 24 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu3.inst 436 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu3.inst 439 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu3.data 24 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2156 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 599 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 174 # number of overall (read+write) accesses +system.l2c.demand_accesses::total 2161 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 602 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 173 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu1.inst 436 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu1.data 25 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu2.inst 438 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu2.data 24 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu3.inst 436 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu3.inst 439 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu3.data 24 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2156 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.602671 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.937500 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.204128 # miss rate for ReadReq accesses +system.l2c.overall_accesses::total 2161 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.602990 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.936709 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.197248 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu1.data 0.583333 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2.inst 0.015982 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2.inst 0.022831 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu2.data 0.083333 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu3.inst 0.011468 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu3.inst 0.018223 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu3.data 0.083333 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.269630 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.884615 # miss rate for UpgradeReq accesses +system.l2c.ReadReq_miss_rate::total 0.270936 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.869565 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::cpu2.data 1 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::cpu3.data 1 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.964286 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.961538 # miss rate for UpgradeReq accesses system.l2c.ReadExReq_miss_rate::cpu0.data 1 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::cpu1.data 1 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::cpu3.data 1 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.inst 0.602671 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.971264 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.204128 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.602990 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.971098 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.197248 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu1.data 0.800000 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.inst 0.015982 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.inst 0.022831 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu2.data 0.541667 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu3.inst 0.011468 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu3.inst 0.018223 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu3.data 0.541667 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.314007 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.inst 0.602671 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.971264 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.204128 # miss rate for overall accesses +system.l2c.demand_miss_rate::total 0.315132 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.inst 0.602990 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.971098 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.197248 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu1.data 0.800000 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.inst 0.015982 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.inst 0.022831 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu2.data 0.541667 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu3.inst 0.011468 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu3.inst 0.018223 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu3.data 0.541667 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.314007 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52124.653740 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.data 52406.666667 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 51820.224719 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 52285.714286 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2.inst 43428.571429 # average ReadReq miss latency +system.l2c.overall_miss_rate::total 0.315132 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu0.inst 53045.454545 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.data 56445.945946 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 52273.255814 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 53928.571429 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2.inst 44950 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu2.data 52500 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu3.inst 50800 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu3.inst 48500 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu3.data 52500 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 51993.589744 # average ReadReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52537.234043 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 52423.076923 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu2.data 52458.333333 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu3.data 52333.333333 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 52500 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 52124.653740 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 52479.289941 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 51820.224719 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 52375 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.inst 43428.571429 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.data 52461.538462 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu3.inst 50800 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu3.data 52346.153846 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 52091.580502 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 52124.653740 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 52479.289941 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 51820.224719 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 52375 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.inst 43428.571429 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.data 52461.538462 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu3.inst 50800 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu3.data 52346.153846 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 52091.580502 # average overall miss latency +system.l2c.ReadReq_avg_miss_latency::total 53178.181818 # average ReadReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 54930.851064 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 57769.230769 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu2.data 55250 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu3.data 54874.916667 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 55236.633588 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 53045.454545 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 55598.214286 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 52273.255814 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 56425 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.inst 44950 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.data 55038.461538 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu3.inst 48500 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu3.data 54692.230769 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 53574.154185 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 53045.454545 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 55598.214286 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 52273.255814 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 56425 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.inst 44950 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.data 55038.461538 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu3.inst 48500 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu3.data 54692.230769 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 53574.154185 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -2203,166 +2203,166 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.ReadReq_mshr_hits::cpu1.inst 1 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu1.inst 2 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::cpu2.inst 5 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu3.inst 1 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::total 7 # number of ReadReq MSHR hits -system.l2c.demand_mshr_hits::cpu1.inst 1 # number of demand (read+write) MSHR hits +system.l2c.ReadReq_mshr_hits::cpu3.inst 2 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::total 9 # number of ReadReq MSHR hits +system.l2c.demand_mshr_hits::cpu1.inst 2 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_hits::cpu2.inst 5 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu3.inst 1 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::total 7 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits::cpu1.inst 1 # number of overall MSHR hits +system.l2c.demand_mshr_hits::cpu3.inst 2 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::total 9 # number of demand (read+write) MSHR hits +system.l2c.overall_mshr_hits::cpu1.inst 2 # number of overall MSHR hits system.l2c.overall_mshr_hits::cpu2.inst 5 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu3.inst 1 # number of overall MSHR hits -system.l2c.overall_mshr_hits::total 7 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses::cpu0.inst 361 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.data 75 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.inst 88 # number of ReadReq MSHR misses +system.l2c.overall_mshr_hits::cpu3.inst 2 # number of overall MSHR hits +system.l2c.overall_mshr_hits::total 9 # number of overall MSHR hits +system.l2c.ReadReq_mshr_misses::cpu0.inst 363 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.data 74 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.inst 84 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu1.data 7 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu2.inst 2 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu2.inst 5 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu2.data 1 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu3.inst 4 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu3.inst 6 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu3.data 1 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 539 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.data 23 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 20 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu2.data 19 # number of UpgradeReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 541 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0.data 20 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 15 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu2.data 21 # number of UpgradeReq MSHR misses system.l2c.UpgradeReq_mshr_misses::cpu3.data 19 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 81 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 75 # number of UpgradeReq MSHR misses system.l2c.ReadExReq_mshr_misses::cpu0.data 94 # number of ReadExReq MSHR misses system.l2c.ReadExReq_mshr_misses::cpu1.data 13 # number of ReadExReq MSHR misses system.l2c.ReadExReq_mshr_misses::cpu2.data 12 # number of ReadExReq MSHR misses system.l2c.ReadExReq_mshr_misses::cpu3.data 12 # number of ReadExReq MSHR misses system.l2c.ReadExReq_mshr_misses::total 131 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 361 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.data 169 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 88 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 363 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.data 168 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 84 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu1.data 20 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2.inst 2 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2.inst 5 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu2.data 13 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu3.inst 4 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu3.inst 6 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu3.data 13 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 670 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 361 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.data 169 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 88 # number of overall MSHR misses +system.l2c.demand_mshr_misses::total 672 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0.inst 363 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.data 168 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 84 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu1.data 20 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2.inst 2 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2.inst 5 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu2.data 13 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu3.inst 4 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu3.inst 6 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu3.data 13 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 670 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 14412000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.data 3017000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 3521000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 280000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 80000 # number of ReadReq MSHR miss cycles +system.l2c.overall_mshr_misses::total 672 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 14840000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.data 3282500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 3420000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.data 291500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 200000 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::cpu2.data 40000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu3.inst 160000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu3.inst 240000 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::cpu3.data 40000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 21550000 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 920000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 800000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 760000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data 760500 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 3240500 # number of UpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 3791500 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 522500 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 483500 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu3.data 481500 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 5279000 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 14412000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 6808500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 3521000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 802500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2.inst 80000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2.data 523500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu3.inst 160000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu3.data 521500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 26829000 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 14412000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 6808500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 3521000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 802500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.inst 80000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.data 523500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu3.inst 160000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu3.data 521500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 26829000 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.602671 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.937500 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.201835 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_latency::total 22354000 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 800000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 600000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 844000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data 765000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 3009000 # number of UpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 4019000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 593500 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 516500 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu3.data 511500 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 5640500 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 14840000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 7301500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 3420000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 885000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.inst 200000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.data 556500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu3.inst 240000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu3.data 551500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 27994500 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 14840000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 7301500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 3420000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 885000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.inst 200000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.data 556500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu3.inst 240000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu3.data 551500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 27994500 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.602990 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.936709 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.192661 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.583333 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.004566 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.011416 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.083333 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu3.inst 0.009174 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu3.inst 0.013667 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu3.data 0.083333 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.266173 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.884615 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.266502 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.869565 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.964286 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.961538 # mshr miss rate for UpgradeReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.602671 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.971264 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.201835 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.602990 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.971098 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.192661 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu1.data 0.800000 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.inst 0.004566 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.inst 0.011416 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu2.data 0.541667 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu3.inst 0.009174 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3.inst 0.013667 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu3.data 0.541667 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.310761 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.602671 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.971264 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.201835 # mshr miss rate for overall accesses +system.l2c.demand_mshr_miss_rate::total 0.310967 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.602990 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.971098 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.192661 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu1.data 0.800000 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.inst 0.004566 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.inst 0.011416 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu2.data 0.541667 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu3.inst 0.009174 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3.inst 0.013667 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu3.data 0.541667 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.310761 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 39922.437673 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40226.666667 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40011.363636 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40000 # average ReadReq mshr miss latency +system.l2c.overall_mshr_miss_rate::total 0.310967 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40881.542700 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 44358.108108 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40714.285714 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 41642.857143 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 40000 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 40000 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst 40000 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.data 40000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 39981.447124 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 41319.778189 # average ReadReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40000 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40000 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 40000 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 40026.315789 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40006.172840 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40335.106383 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40192.307692 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 40291.666667 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 40125 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 40297.709924 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 39922.437673 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40286.982249 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40011.363636 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40125 # average overall mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 40190.476190 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 40263.157895 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40120 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 42755.319149 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 45653.846154 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 43041.666667 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 42625 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 43057.251908 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40881.542700 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 43461.309524 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40714.285714 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 44250 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 40000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.data 40269.230769 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 42807.692308 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 40000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3.data 40115.384615 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 40043.283582 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 39922.437673 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40286.982249 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40011.363636 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40125 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.data 42423.076923 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 41658.482143 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40881.542700 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 43461.309524 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40714.285714 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 44250 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 40000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.data 40269.230769 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 42807.692308 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 40000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3.data 40115.384615 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 40043.283582 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.data 42423.076923 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 41658.482143 # average overall mshr miss latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini index cf4b383de..55888365a 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini @@ -449,7 +449,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.physmem.port[0] slave=system.l2c.mem_side system.system_port @@ -471,7 +471,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.l2c.cpu_side slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu2.icache.mem_side system.cpu2.dcache.mem_side system.cpu3.icache.mem_side system.cpu3.dcache.mem_side diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout index 145ab230c..900805018 100755 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout @@ -1,8 +1,8 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 28 2012 22:06:58 -gem5 started Jun 28 2012 22:54:12 +gem5 compiled Jul 2 2012 08:54:18 +gem5 started Jul 2 2012 11:32:06 gem5 executing on zizzer command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/quick/se/40.m5threads-test-atomic/sparc/linux/simple-timing-mp -re tests/run.py build/SPARC/tests/fast/quick/se/40.m5threads-test-atomic/sparc/linux/simple-timing-mp Global frequency set at 1000000000000 ticks per second @@ -10,73 +10,73 @@ info: Entering event queue @ 0. Starting simulation... Init done [Iteration 1, Thread 1] Got lock [Iteration 1, Thread 1] Critical section done, previously next=0, now next=1 -[Iteration 1, Thread 3] Got lock -[Iteration 1, Thread 3] Critical section done, previously next=1, now next=3 [Iteration 1, Thread 2] Got lock -[Iteration 1, Thread 2] Critical section done, previously next=3, now next=2 +[Iteration 1, Thread 2] Critical section done, previously next=1, now next=2 +[Iteration 1, Thread 3] Got lock +[Iteration 1, Thread 3] Critical section done, previously next=2, now next=3 Iteration 1 completed -[Iteration 2, Thread 2] Got lock -[Iteration 2, Thread 2] Critical section done, previously next=0, now next=2 -[Iteration 2, Thread 3] Got lock -[Iteration 2, Thread 3] Critical section done, previously next=2, now next=3 [Iteration 2, Thread 1] Got lock -[Iteration 2, Thread 1] Critical section done, previously next=3, now next=1 +[Iteration 2, Thread 1] Critical section done, previously next=0, now next=1 +[Iteration 2, Thread 3] Got lock +[Iteration 2, Thread 3] Critical section done, previously next=1, now next=3 +[Iteration 2, Thread 2] Got lock +[Iteration 2, Thread 2] Critical section done, previously next=3, now next=2 Iteration 2 completed +[Iteration 3, Thread 1] Got lock +[Iteration 3, Thread 1] Critical section done, previously next=0, now next=1 [Iteration 3, Thread 3] Got lock -[Iteration 3, Thread 3] Critical section done, previously next=0, now next=3 +[Iteration 3, Thread 3] Critical section done, previously next=1, now next=3 [Iteration 3, Thread 2] Got lock [Iteration 3, Thread 2] Critical section done, previously next=3, now next=2 -[Iteration 3, Thread 1] Got lock -[Iteration 3, Thread 1] Critical section done, previously next=2, now next=1 Iteration 3 completed -[Iteration 4, Thread 2] Got lock -[Iteration 4, Thread 2] Critical section done, previously next=0, now next=2 -[Iteration 4, Thread 3] Got lock -[Iteration 4, Thread 3] Critical section done, previously next=2, now next=3 [Iteration 4, Thread 1] Got lock -[Iteration 4, Thread 1] Critical section done, previously next=3, now next=1 +[Iteration 4, Thread 1] Critical section done, previously next=0, now next=1 +[Iteration 4, Thread 3] Got lock +[Iteration 4, Thread 3] Critical section done, previously next=1, now next=3 +[Iteration 4, Thread 2] Got lock +[Iteration 4, Thread 2] Critical section done, previously next=3, now next=2 Iteration 4 completed +[Iteration 5, Thread 1] Got lock +[Iteration 5, Thread 1] Critical section done, previously next=0, now next=1 [Iteration 5, Thread 3] Got lock -[Iteration 5, Thread 3] Critical section done, previously next=0, now next=3 +[Iteration 5, Thread 3] Critical section done, previously next=1, now next=3 [Iteration 5, Thread 2] Got lock [Iteration 5, Thread 2] Critical section done, previously next=3, now next=2 -[Iteration 5, Thread 1] Got lock -[Iteration 5, Thread 1] Critical section done, previously next=2, now next=1 Iteration 5 completed -[Iteration 6, Thread 2] Got lock -[Iteration 6, Thread 2] Critical section done, previously next=0, now next=2 -[Iteration 6, Thread 3] Got lock -[Iteration 6, Thread 3] Critical section done, previously next=2, now next=3 [Iteration 6, Thread 1] Got lock -[Iteration 6, Thread 1] Critical section done, previously next=3, now next=1 +[Iteration 6, Thread 1] Critical section done, previously next=0, now next=1 +[Iteration 6, Thread 3] Got lock +[Iteration 6, Thread 3] Critical section done, previously next=1, now next=3 +[Iteration 6, Thread 2] Got lock +[Iteration 6, Thread 2] Critical section done, previously next=3, now next=2 Iteration 6 completed +[Iteration 7, Thread 1] Got lock +[Iteration 7, Thread 1] Critical section done, previously next=0, now next=1 [Iteration 7, Thread 3] Got lock -[Iteration 7, Thread 3] Critical section done, previously next=0, now next=3 +[Iteration 7, Thread 3] Critical section done, previously next=1, now next=3 [Iteration 7, Thread 2] Got lock [Iteration 7, Thread 2] Critical section done, previously next=3, now next=2 -[Iteration 7, Thread 1] Got lock -[Iteration 7, Thread 1] Critical section done, previously next=2, now next=1 Iteration 7 completed -[Iteration 8, Thread 2] Got lock -[Iteration 8, Thread 2] Critical section done, previously next=0, now next=2 -[Iteration 8, Thread 3] Got lock -[Iteration 8, Thread 3] Critical section done, previously next=2, now next=3 [Iteration 8, Thread 1] Got lock -[Iteration 8, Thread 1] Critical section done, previously next=3, now next=1 +[Iteration 8, Thread 1] Critical section done, previously next=0, now next=1 +[Iteration 8, Thread 3] Got lock +[Iteration 8, Thread 3] Critical section done, previously next=1, now next=3 +[Iteration 8, Thread 2] Got lock +[Iteration 8, Thread 2] Critical section done, previously next=3, now next=2 Iteration 8 completed +[Iteration 9, Thread 1] Got lock +[Iteration 9, Thread 1] Critical section done, previously next=0, now next=1 [Iteration 9, Thread 3] Got lock -[Iteration 9, Thread 3] Critical section done, previously next=0, now next=3 +[Iteration 9, Thread 3] Critical section done, previously next=1, now next=3 [Iteration 9, Thread 2] Got lock [Iteration 9, Thread 2] Critical section done, previously next=3, now next=2 -[Iteration 9, Thread 1] Got lock -[Iteration 9, Thread 1] Critical section done, previously next=2, now next=1 Iteration 9 completed -[Iteration 10, Thread 2] Got lock -[Iteration 10, Thread 2] Critical section done, previously next=0, now next=2 [Iteration 10, Thread 1] Got lock -[Iteration 10, Thread 1] Critical section done, previously next=2, now next=1 +[Iteration 10, Thread 1] Critical section done, previously next=0, now next=1 +[Iteration 10, Thread 2] Got lock +[Iteration 10, Thread 2] Critical section done, previously next=1, now next=2 [Iteration 10, Thread 3] Got lock -[Iteration 10, Thread 3] Critical section done, previously next=1, now next=3 +[Iteration 10, Thread 3] Critical section done, previously next=2, now next=3 Iteration 10 completed PASSED :-) -Exiting @ tick 262299000 because target called exit() +Exiting @ tick 268912000 because target called exit() diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt index c654a221f..ea05c2e9c 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt @@ -1,130 +1,130 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000262 # Number of seconds simulated -sim_ticks 262299000 # Number of ticks simulated -final_tick 262299000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000269 # Number of seconds simulated +sim_ticks 268912000 # Number of ticks simulated +final_tick 268912000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1271827 # Simulator instruction rate (inst/s) -host_op_rate 1271784 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 503510999 # Simulator tick rate (ticks/s) -host_mem_usage 230932 # Number of bytes of host memory used -host_seconds 0.52 # Real time elapsed on the host -sim_insts 662502 # Number of instructions simulated -sim_ops 662502 # Number of ops (including micro ops) simulated +host_inst_rate 548575 # Simulator instruction rate (inst/s) +host_op_rate 548567 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 220132321 # Simulator tick rate (ticks/s) +host_mem_usage 230896 # Number of bytes of host memory used +host_seconds 1.22 # Real time elapsed on the host +sim_insts 670117 # Number of instructions simulated +sim_ops 670117 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu0.inst 18240 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.data 10560 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.inst 3776 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.data 1408 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 576 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 1024 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3.inst 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3.data 960 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 128 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 960 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3.inst 512 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3.data 1024 # Number of bytes read from this memory system.physmem.bytes_read::total 36608 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu0.inst 18240 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::cpu1.inst 3776 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 576 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu3.inst 64 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 128 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu3.inst 512 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 22656 # Number of instructions bytes read from this memory system.physmem.num_reads::cpu0.inst 285 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.data 165 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.inst 59 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.data 22 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 9 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 16 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3.inst 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3.data 15 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 2 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 15 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3.inst 8 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3.data 16 # Number of read requests responded to by this memory system.physmem.num_reads::total 572 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu0.inst 69538961 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 40259399 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 14395785 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 5367920 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 2195967 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 3903942 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.inst 243996 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.data 3659945 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 139565915 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 69538961 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 14395785 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 2195967 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu3.inst 243996 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 86374710 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 69538961 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 40259399 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 14395785 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 5367920 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 2195967 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 3903942 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.inst 243996 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.data 3659945 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 139565915 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 67828881 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 39269352 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 14041768 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 5235914 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 475992 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 3569941 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.inst 1903969 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.data 3807937 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 136133754 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 67828881 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 14041768 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 475992 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu3.inst 1903969 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 84250610 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 67828881 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 39269352 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 14041768 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 5235914 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 475992 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 3569941 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.inst 1903969 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.data 3807937 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 136133754 # Total bandwidth to/from this memory (bytes/s) system.cpu0.workload.num_syscalls 89 # Number of system calls -system.cpu0.numCycles 524598 # number of cpu cycles simulated +system.cpu0.numCycles 537824 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 158353 # Number of instructions committed -system.cpu0.committedOps 158353 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 109064 # Number of integer alu accesses +system.cpu0.committedInsts 160927 # Number of instructions committed +system.cpu0.committedOps 160927 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 110780 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu0.num_func_calls 390 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 25994 # number of instructions that are conditional controls -system.cpu0.num_int_insts 109064 # number of integer instructions +system.cpu0.num_conditional_control_insts 26423 # number of instructions that are conditional controls +system.cpu0.num_int_insts 110780 # number of integer instructions system.cpu0.num_fp_insts 0 # number of float instructions -system.cpu0.num_int_register_reads 315336 # number of times the integer registers were read -system.cpu0.num_int_register_writes 110671 # number of times the integer registers were written +system.cpu0.num_int_register_reads 320484 # number of times the integer registers were read +system.cpu0.num_int_register_writes 112387 # number of times the integer registers were written system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu0.num_mem_refs 73905 # number of memory refs -system.cpu0.num_load_insts 48930 # Number of load instructions -system.cpu0.num_store_insts 24975 # Number of store instructions +system.cpu0.num_mem_refs 75192 # number of memory refs +system.cpu0.num_load_insts 49788 # Number of load instructions +system.cpu0.num_store_insts 25404 # Number of store instructions system.cpu0.num_idle_cycles 0 # Number of idle cycles -system.cpu0.num_busy_cycles 524598 # Number of busy cycles +system.cpu0.num_busy_cycles 537824 # Number of busy cycles system.cpu0.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu0.idle_fraction 0 # Percentage of idle cycles system.cpu0.icache.replacements 215 # number of replacements -system.cpu0.icache.tagsinuse 212.479251 # Cycle average of tags in use -system.cpu0.icache.total_refs 157949 # Total number of references to valid blocks. +system.cpu0.icache.tagsinuse 212.253377 # Cycle average of tags in use +system.cpu0.icache.total_refs 160523 # Total number of references to valid blocks. system.cpu0.icache.sampled_refs 467 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 338.220557 # Average number of references to valid blocks. +system.cpu0.icache.avg_refs 343.732334 # Average number of references to valid blocks. system.cpu0.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 212.479251 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.414999 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.414999 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 157949 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 157949 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 157949 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 157949 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 157949 # number of overall hits -system.cpu0.icache.overall_hits::total 157949 # number of overall hits +system.cpu0.icache.occ_blocks::cpu0.inst 212.253377 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.414557 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.414557 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 160523 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 160523 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 160523 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 160523 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 160523 # number of overall hits +system.cpu0.icache.overall_hits::total 160523 # number of overall hits system.cpu0.icache.ReadReq_misses::cpu0.inst 467 # number of ReadReq misses system.cpu0.icache.ReadReq_misses::total 467 # number of ReadReq misses system.cpu0.icache.demand_misses::cpu0.inst 467 # number of demand (read+write) misses system.cpu0.icache.demand_misses::total 467 # number of demand (read+write) misses system.cpu0.icache.overall_misses::cpu0.inst 467 # number of overall misses system.cpu0.icache.overall_misses::total 467 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 18524000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 18524000 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 18524000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 18524000 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 18524000 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 18524000 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 158416 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 158416 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 158416 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 158416 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 158416 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 158416 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.002948 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.002948 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.002948 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.002948 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.002948 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.002948 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 39665.952891 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 39665.952891 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 39665.952891 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 39665.952891 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 39665.952891 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 39665.952891 # average overall miss latency +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 18554000 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 18554000 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 18554000 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 18554000 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 18554000 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 18554000 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 160990 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 160990 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 160990 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 160990 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 160990 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 160990 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.002901 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.002901 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.002901 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.002901 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.002901 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.002901 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 39730.192719 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 39730.192719 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 39730.192719 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 39730.192719 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 39730.192719 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 39730.192719 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -139,44 +139,44 @@ system.cpu0.icache.demand_mshr_misses::cpu0.inst 467 system.cpu0.icache.demand_mshr_misses::total 467 # number of demand (read+write) MSHR misses system.cpu0.icache.overall_mshr_misses::cpu0.inst 467 # number of overall MSHR misses system.cpu0.icache.overall_mshr_misses::total 467 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 17123000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 17123000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 17123000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 17123000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 17123000 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 17123000 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.002948 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.002948 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.002948 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.002948 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.002948 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.002948 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 36665.952891 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 36665.952891 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 36665.952891 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 36665.952891 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 36665.952891 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 36665.952891 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 17153000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 17153000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 17153000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 17153000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 17153000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 17153000 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.002901 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.002901 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.002901 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.002901 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.002901 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.002901 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 36730.192719 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 36730.192719 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 36730.192719 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 36730.192719 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 36730.192719 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 36730.192719 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.dcache.replacements 2 # number of replacements -system.cpu0.dcache.tagsinuse 145.603716 # Cycle average of tags in use -system.cpu0.dcache.total_refs 73381 # Total number of references to valid blocks. +system.cpu0.dcache.tagsinuse 145.513886 # Cycle average of tags in use +system.cpu0.dcache.total_refs 74668 # Total number of references to valid blocks. system.cpu0.dcache.sampled_refs 167 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 439.407186 # Average number of references to valid blocks. +system.cpu0.dcache.avg_refs 447.113772 # Average number of references to valid blocks. system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 145.603716 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.284382 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.284382 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 48758 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 48758 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 24741 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 24741 # number of WriteReq hits +system.cpu0.dcache.occ_blocks::cpu0.data 145.513886 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.284207 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::total 0.284207 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 49616 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 49616 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 25170 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 25170 # number of WriteReq hits system.cpu0.dcache.SwapReq_hits::cpu0.data 16 # number of SwapReq hits system.cpu0.dcache.SwapReq_hits::total 16 # number of SwapReq hits -system.cpu0.dcache.demand_hits::cpu0.data 73499 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 73499 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 73499 # number of overall hits -system.cpu0.dcache.overall_hits::total 73499 # number of overall hits +system.cpu0.dcache.demand_hits::cpu0.data 74786 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 74786 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 74786 # number of overall hits +system.cpu0.dcache.overall_hits::total 74786 # number of overall hits system.cpu0.dcache.ReadReq_misses::cpu0.data 162 # number of ReadReq misses system.cpu0.dcache.ReadReq_misses::total 162 # number of ReadReq misses system.cpu0.dcache.WriteReq_misses::cpu0.data 183 # number of WriteReq misses @@ -187,46 +187,46 @@ system.cpu0.dcache.demand_misses::cpu0.data 345 # system.cpu0.dcache.demand_misses::total 345 # number of demand (read+write) misses system.cpu0.dcache.overall_misses::cpu0.data 345 # number of overall misses system.cpu0.dcache.overall_misses::total 345 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 4747000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 4747000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 7176000 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 7176000 # number of WriteReq miss cycles -system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 389000 # number of SwapReq miss cycles -system.cpu0.dcache.SwapReq_miss_latency::total 389000 # number of SwapReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 11923000 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 11923000 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 11923000 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 11923000 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 48920 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 48920 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 24924 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 24924 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5171000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 5171000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 7310000 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 7310000 # number of WriteReq miss cycles +system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 522000 # number of SwapReq miss cycles +system.cpu0.dcache.SwapReq_miss_latency::total 522000 # number of SwapReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 12481000 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 12481000 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 12481000 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 12481000 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 49778 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 49778 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 25353 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 25353 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses) system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 73844 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 73844 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 73844 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 73844 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.003312 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.003312 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007342 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.007342 # miss rate for WriteReq accesses +system.cpu0.dcache.demand_accesses::cpu0.data 75131 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 75131 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 75131 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 75131 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.003254 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.003254 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007218 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.007218 # miss rate for WriteReq accesses system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.619048 # miss rate for SwapReq accesses system.cpu0.dcache.SwapReq_miss_rate::total 0.619048 # miss rate for SwapReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.004672 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.004672 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.004672 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.004672 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 29302.469136 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 29302.469136 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 39213.114754 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 39213.114754 # average WriteReq miss latency -system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 14961.538462 # average SwapReq miss latency -system.cpu0.dcache.SwapReq_avg_miss_latency::total 14961.538462 # average SwapReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 34559.420290 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 34559.420290 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 34559.420290 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 34559.420290 # average overall miss latency +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.004592 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.004592 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.004592 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.004592 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 31919.753086 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 31919.753086 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 39945.355191 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 39945.355191 # average WriteReq miss latency +system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 20076.923077 # average SwapReq miss latency +system.cpu0.dcache.SwapReq_avg_miss_latency::total 20076.923077 # average SwapReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 36176.811594 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 36176.811594 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 36176.811594 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 36176.811594 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -247,104 +247,104 @@ system.cpu0.dcache.demand_mshr_misses::cpu0.data 345 system.cpu0.dcache.demand_mshr_misses::total 345 # number of demand (read+write) MSHR misses system.cpu0.dcache.overall_mshr_misses::cpu0.data 345 # number of overall MSHR misses system.cpu0.dcache.overall_mshr_misses::total 345 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4261000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4261000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6627000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6627000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 311000 # number of SwapReq MSHR miss cycles -system.cpu0.dcache.SwapReq_mshr_miss_latency::total 311000 # number of SwapReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 10888000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 10888000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10888000 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 10888000 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.003312 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.003312 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.007342 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.007342 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4684001 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4684001 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6761000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6761000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 444000 # number of SwapReq MSHR miss cycles +system.cpu0.dcache.SwapReq_mshr_miss_latency::total 444000 # number of SwapReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 11445001 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 11445001 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 11445001 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 11445001 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.003254 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.003254 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.007218 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.007218 # mshr miss rate for WriteReq accesses system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.619048 # mshr miss rate for SwapReq accesses system.cpu0.dcache.SwapReq_mshr_miss_rate::total 0.619048 # mshr miss rate for SwapReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.004672 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.004672 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.004672 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.004672 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 26302.469136 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 26302.469136 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 36213.114754 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 36213.114754 # average WriteReq mshr miss latency -system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 11961.538462 # average SwapReq mshr miss latency -system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 11961.538462 # average SwapReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 31559.420290 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 31559.420290 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 31559.420290 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 31559.420290 # average overall mshr miss latency +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.004592 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.004592 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.004592 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.004592 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 28913.586420 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 28913.586420 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 36945.355191 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 36945.355191 # average WriteReq mshr miss latency +system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 17076.923077 # average SwapReq mshr miss latency +system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 17076.923077 # average SwapReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 33173.915942 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 33173.915942 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 33173.915942 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 33173.915942 # average overall mshr miss latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.numCycles 524598 # number of cpu cycles simulated +system.cpu1.numCycles 537824 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 172389 # Number of instructions committed -system.cpu1.committedOps 172389 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 107964 # Number of integer alu accesses +system.cpu1.committedInsts 159902 # Number of instructions committed +system.cpu1.committedOps 159902 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 114536 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu1.num_func_calls 637 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 36219 # number of instructions that are conditional controls -system.cpu1.num_int_insts 107964 # number of integer instructions +system.cpu1.num_conditional_control_insts 26689 # number of instructions that are conditional controls +system.cpu1.num_int_insts 114536 # number of integer instructions system.cpu1.num_fp_insts 0 # number of float instructions -system.cpu1.num_int_register_reads 249169 # number of times the integer registers were read -system.cpu1.num_int_register_writes 92792 # number of times the integer registers were written +system.cpu1.num_int_register_reads 313629 # number of times the integer registers were read +system.cpu1.num_int_register_writes 121810 # number of times the integer registers were written system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu1.num_mem_refs 47914 # number of memory refs -system.cpu1.num_load_insts 39632 # Number of load instructions -system.cpu1.num_store_insts 8282 # Number of store instructions -system.cpu1.num_idle_cycles 68732.001738 # Number of idle cycles -system.cpu1.num_busy_cycles 455865.998262 # Number of busy cycles -system.cpu1.not_idle_fraction 0.868982 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.131018 # Percentage of idle cycles +system.cpu1.num_mem_refs 64016 # number of memory refs +system.cpu1.num_load_insts 42937 # Number of load instructions +system.cpu1.num_store_insts 21079 # Number of store instructions +system.cpu1.num_idle_cycles 71606.001734 # Number of idle cycles +system.cpu1.num_busy_cycles 466217.998266 # Number of busy cycles +system.cpu1.not_idle_fraction 0.866860 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.133140 # Percentage of idle cycles system.cpu1.icache.replacements 280 # number of replacements -system.cpu1.icache.tagsinuse 70.077944 # Cycle average of tags in use -system.cpu1.icache.total_refs 172056 # Total number of references to valid blocks. +system.cpu1.icache.tagsinuse 69.902178 # Cycle average of tags in use +system.cpu1.icache.total_refs 159569 # Total number of references to valid blocks. system.cpu1.icache.sampled_refs 366 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 470.098361 # Average number of references to valid blocks. +system.cpu1.icache.avg_refs 435.980874 # Average number of references to valid blocks. system.cpu1.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 70.077944 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.136871 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.136871 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 172056 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 172056 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 172056 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 172056 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 172056 # number of overall hits -system.cpu1.icache.overall_hits::total 172056 # number of overall hits +system.cpu1.icache.occ_blocks::cpu1.inst 69.902178 # Average occupied blocks per requestor +system.cpu1.icache.occ_percent::cpu1.inst 0.136528 # Average percentage of cache occupancy +system.cpu1.icache.occ_percent::total 0.136528 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 159569 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 159569 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 159569 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 159569 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 159569 # number of overall hits +system.cpu1.icache.overall_hits::total 159569 # number of overall hits system.cpu1.icache.ReadReq_misses::cpu1.inst 366 # number of ReadReq misses system.cpu1.icache.ReadReq_misses::total 366 # number of ReadReq misses system.cpu1.icache.demand_misses::cpu1.inst 366 # number of demand (read+write) misses system.cpu1.icache.demand_misses::total 366 # number of demand (read+write) misses system.cpu1.icache.overall_misses::cpu1.inst 366 # number of overall misses system.cpu1.icache.overall_misses::total 366 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7921500 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 7921500 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 7921500 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 7921500 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 7921500 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 7921500 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 172422 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 172422 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 172422 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 172422 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 172422 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 172422 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.002123 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.002123 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.002123 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.002123 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.002123 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.002123 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 21643.442623 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 21643.442623 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 21643.442623 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 21643.442623 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 21643.442623 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 21643.442623 # average overall miss latency +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7984500 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 7984500 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 7984500 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 7984500 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 7984500 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 7984500 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 159935 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 159935 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 159935 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 159935 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 159935 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 159935 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.002288 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.002288 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.002288 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.002288 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.002288 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.002288 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 21815.573770 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 21815.573770 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 21815.573770 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 21815.573770 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 21815.573770 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 21815.573770 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -359,94 +359,94 @@ system.cpu1.icache.demand_mshr_misses::cpu1.inst 366 system.cpu1.icache.demand_mshr_misses::total 366 # number of demand (read+write) MSHR misses system.cpu1.icache.overall_mshr_misses::cpu1.inst 366 # number of overall MSHR misses system.cpu1.icache.overall_mshr_misses::total 366 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 6823000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 6823000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 6823000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 6823000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 6823000 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 6823000 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.002123 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.002123 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.002123 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.002123 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.002123 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.002123 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 18642.076503 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 18642.076503 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 18642.076503 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 18642.076503 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 18642.076503 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 18642.076503 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 6886000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 6886000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 6886000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 6886000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 6886000 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 6886000 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.002288 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.002288 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.002288 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.002288 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.002288 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.002288 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 18814.207650 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 18814.207650 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 18814.207650 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 18814.207650 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 18814.207650 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 18814.207650 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dcache.replacements 0 # number of replacements -system.cpu1.dcache.tagsinuse 27.731444 # Cycle average of tags in use -system.cpu1.dcache.total_refs 18765 # Total number of references to valid blocks. +system.cpu1.dcache.tagsinuse 27.730072 # Cycle average of tags in use +system.cpu1.dcache.total_refs 44449 # Total number of references to valid blocks. system.cpu1.dcache.sampled_refs 29 # Sample count of references to valid blocks. -system.cpu1.dcache.avg_refs 647.068966 # Average number of references to valid blocks. +system.cpu1.dcache.avg_refs 1532.724138 # Average number of references to valid blocks. system.cpu1.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::cpu1.data 27.731444 # Average occupied blocks per requestor -system.cpu1.dcache.occ_percent::cpu1.data 0.054163 # Average percentage of cache occupancy -system.cpu1.dcache.occ_percent::total 0.054163 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::cpu1.data 39445 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 39445 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 8099 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 8099 # number of WriteReq hits -system.cpu1.dcache.SwapReq_hits::cpu1.data 18 # number of SwapReq hits -system.cpu1.dcache.SwapReq_hits::total 18 # number of SwapReq hits -system.cpu1.dcache.demand_hits::cpu1.data 47544 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 47544 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 47544 # number of overall hits -system.cpu1.dcache.overall_hits::total 47544 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 179 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 179 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 98 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 98 # number of WriteReq misses -system.cpu1.dcache.SwapReq_misses::cpu1.data 65 # number of SwapReq misses -system.cpu1.dcache.SwapReq_misses::total 65 # number of SwapReq misses -system.cpu1.dcache.demand_misses::cpu1.data 277 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 277 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 277 # number of overall misses -system.cpu1.dcache.overall_misses::total 277 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 3683000 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 3683000 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 1838000 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 1838000 # number of WriteReq miss cycles -system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 415000 # number of SwapReq miss cycles -system.cpu1.dcache.SwapReq_miss_latency::total 415000 # number of SwapReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 5521000 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 5521000 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 5521000 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 5521000 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 39624 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 39624 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 8197 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 8197 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SwapReq_accesses::cpu1.data 83 # number of SwapReq accesses(hits+misses) -system.cpu1.dcache.SwapReq_accesses::total 83 # number of SwapReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 47821 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 47821 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 47821 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 47821 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.004517 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.004517 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.011956 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.011956 # miss rate for WriteReq accesses -system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.783133 # miss rate for SwapReq accesses -system.cpu1.dcache.SwapReq_miss_rate::total 0.783133 # miss rate for SwapReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.005792 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.005792 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.005792 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.005792 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 20575.418994 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 20575.418994 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18755.102041 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 18755.102041 # average WriteReq miss latency -system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 6384.615385 # average SwapReq miss latency -system.cpu1.dcache.SwapReq_avg_miss_latency::total 6384.615385 # average SwapReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 19931.407942 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 19931.407942 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 19931.407942 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 19931.407942 # average overall miss latency +system.cpu1.dcache.occ_blocks::cpu1.data 27.730072 # Average occupied blocks per requestor +system.cpu1.dcache.occ_percent::cpu1.data 0.054160 # Average percentage of cache occupancy +system.cpu1.dcache.occ_percent::total 0.054160 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::cpu1.data 42776 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 42776 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 20903 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 20903 # number of WriteReq hits +system.cpu1.dcache.SwapReq_hits::cpu1.data 10 # number of SwapReq hits +system.cpu1.dcache.SwapReq_hits::total 10 # number of SwapReq hits +system.cpu1.dcache.demand_hits::cpu1.data 63679 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 63679 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 63679 # number of overall hits +system.cpu1.dcache.overall_hits::total 63679 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 153 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 153 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 106 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 106 # number of WriteReq misses +system.cpu1.dcache.SwapReq_misses::cpu1.data 58 # number of SwapReq misses +system.cpu1.dcache.SwapReq_misses::total 58 # number of SwapReq misses +system.cpu1.dcache.demand_misses::cpu1.data 259 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 259 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 259 # number of overall misses +system.cpu1.dcache.overall_misses::total 259 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 3030000 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 3030000 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2410000 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 2410000 # number of WriteReq miss cycles +system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 772000 # number of SwapReq miss cycles +system.cpu1.dcache.SwapReq_miss_latency::total 772000 # number of SwapReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 5440000 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 5440000 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 5440000 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 5440000 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 42929 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 42929 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 21009 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 21009 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SwapReq_accesses::cpu1.data 68 # number of SwapReq accesses(hits+misses) +system.cpu1.dcache.SwapReq_accesses::total 68 # number of SwapReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 63938 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 63938 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 63938 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 63938 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.003564 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.003564 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.005045 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.005045 # miss rate for WriteReq accesses +system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.852941 # miss rate for SwapReq accesses +system.cpu1.dcache.SwapReq_miss_rate::total 0.852941 # miss rate for SwapReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.004051 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.004051 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.004051 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.004051 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 19803.921569 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 19803.921569 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 22735.849057 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 22735.849057 # average WriteReq miss latency +system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 13310.344828 # average SwapReq miss latency +system.cpu1.dcache.SwapReq_avg_miss_latency::total 13310.344828 # average SwapReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 21003.861004 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 21003.861004 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 21003.861004 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 21003.861004 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -455,114 +455,114 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 179 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 179 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 98 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 98 # number of WriteReq MSHR misses -system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 65 # number of SwapReq MSHR misses -system.cpu1.dcache.SwapReq_mshr_misses::total 65 # number of SwapReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 277 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 277 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 277 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 277 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 3146000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 3146000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1544000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1544000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 220000 # number of SwapReq MSHR miss cycles -system.cpu1.dcache.SwapReq_mshr_miss_latency::total 220000 # number of SwapReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4690000 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 4690000 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4690000 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 4690000 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.004517 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.004517 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.011956 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.011956 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.783133 # mshr miss rate for SwapReq accesses -system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.783133 # mshr miss rate for SwapReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.005792 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.005792 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.005792 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.005792 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 17575.418994 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 17575.418994 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 15755.102041 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 15755.102041 # average WriteReq mshr miss latency -system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 3384.615385 # average SwapReq mshr miss latency -system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 3384.615385 # average SwapReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16931.407942 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16931.407942 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16931.407942 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16931.407942 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 153 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 153 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 106 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 106 # number of WriteReq MSHR misses +system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 58 # number of SwapReq MSHR misses +system.cpu1.dcache.SwapReq_mshr_misses::total 58 # number of SwapReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 259 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 259 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 259 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 259 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2570001 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2570001 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2092000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2092000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 598000 # number of SwapReq MSHR miss cycles +system.cpu1.dcache.SwapReq_mshr_miss_latency::total 598000 # number of SwapReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4662001 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 4662001 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4662001 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 4662001 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.003564 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.003564 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.005045 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.005045 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.852941 # mshr miss rate for SwapReq accesses +system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.852941 # mshr miss rate for SwapReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.004051 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.004051 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.004051 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.004051 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 16797.392157 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 16797.392157 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 19735.849057 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 19735.849057 # average WriteReq mshr miss latency +system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 10310.344828 # average SwapReq mshr miss latency +system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 10310.344828 # average SwapReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18000.003861 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18000.003861 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18000.003861 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18000.003861 # average overall mshr miss latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.numCycles 524598 # number of cpu cycles simulated +system.cpu2.numCycles 537824 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.committedInsts 165564 # Number of instructions committed -system.cpu2.committedOps 165564 # Number of ops (including micro ops) committed -system.cpu2.num_int_alu_accesses 112387 # Number of integer alu accesses +system.cpu2.committedInsts 177221 # Number of instructions committed +system.cpu2.committedOps 177221 # Number of ops (including micro ops) committed +system.cpu2.num_int_alu_accesses 109567 # Number of integer alu accesses system.cpu2.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu2.num_func_calls 637 # number of times a function call or return occured -system.cpu2.num_conditional_control_insts 30599 # number of instructions that are conditional controls -system.cpu2.num_int_insts 112387 # number of integer instructions +system.cpu2.num_conditional_control_insts 37840 # number of instructions that are conditional controls +system.cpu2.num_int_insts 109567 # number of integer instructions system.cpu2.num_fp_insts 0 # number of float instructions -system.cpu2.num_int_register_reads 289349 # number of times the integer registers were read -system.cpu2.num_int_register_writes 110679 # number of times the integer registers were written +system.cpu2.num_int_register_reads 249142 # number of times the integer registers were read +system.cpu2.num_int_register_writes 92045 # number of times the integer registers were written system.cpu2.num_fp_register_reads 0 # number of times the floating registers were read system.cpu2.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu2.num_mem_refs 57957 # number of memory refs -system.cpu2.num_load_insts 41868 # Number of load instructions -system.cpu2.num_store_insts 16089 # Number of store instructions -system.cpu2.num_idle_cycles 68998.001737 # Number of idle cycles -system.cpu2.num_busy_cycles 455599.998263 # Number of busy cycles -system.cpu2.not_idle_fraction 0.868475 # Percentage of non-idle cycles -system.cpu2.idle_fraction 0.131525 # Percentage of idle cycles -system.cpu2.icache.replacements 280 # number of replacements -system.cpu2.icache.tagsinuse 65.602896 # Cycle average of tags in use -system.cpu2.icache.total_refs 165231 # Total number of references to valid blocks. -system.cpu2.icache.sampled_refs 366 # Sample count of references to valid blocks. -system.cpu2.icache.avg_refs 451.450820 # Average number of references to valid blocks. +system.cpu2.num_mem_refs 47896 # number of memory refs +system.cpu2.num_load_insts 40447 # Number of load instructions +system.cpu2.num_store_insts 7449 # Number of store instructions +system.cpu2.num_idle_cycles 71882.001733 # Number of idle cycles +system.cpu2.num_busy_cycles 465941.998267 # Number of busy cycles +system.cpu2.not_idle_fraction 0.866347 # Percentage of non-idle cycles +system.cpu2.idle_fraction 0.133653 # Percentage of idle cycles +system.cpu2.icache.replacements 281 # number of replacements +system.cpu2.icache.tagsinuse 67.531468 # Cycle average of tags in use +system.cpu2.icache.total_refs 176887 # Total number of references to valid blocks. +system.cpu2.icache.sampled_refs 367 # Sample count of references to valid blocks. +system.cpu2.icache.avg_refs 481.980926 # Average number of references to valid blocks. system.cpu2.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.icache.occ_blocks::cpu2.inst 65.602896 # Average occupied blocks per requestor -system.cpu2.icache.occ_percent::cpu2.inst 0.128131 # Average percentage of cache occupancy -system.cpu2.icache.occ_percent::total 0.128131 # Average percentage of cache occupancy -system.cpu2.icache.ReadReq_hits::cpu2.inst 165231 # number of ReadReq hits -system.cpu2.icache.ReadReq_hits::total 165231 # number of ReadReq hits -system.cpu2.icache.demand_hits::cpu2.inst 165231 # number of demand (read+write) hits -system.cpu2.icache.demand_hits::total 165231 # number of demand (read+write) hits -system.cpu2.icache.overall_hits::cpu2.inst 165231 # number of overall hits -system.cpu2.icache.overall_hits::total 165231 # number of overall hits -system.cpu2.icache.ReadReq_misses::cpu2.inst 366 # number of ReadReq misses -system.cpu2.icache.ReadReq_misses::total 366 # number of ReadReq misses -system.cpu2.icache.demand_misses::cpu2.inst 366 # number of demand (read+write) misses -system.cpu2.icache.demand_misses::total 366 # number of demand (read+write) misses -system.cpu2.icache.overall_misses::cpu2.inst 366 # number of overall misses -system.cpu2.icache.overall_misses::total 366 # number of overall misses -system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 5648500 # number of ReadReq miss cycles -system.cpu2.icache.ReadReq_miss_latency::total 5648500 # number of ReadReq miss cycles -system.cpu2.icache.demand_miss_latency::cpu2.inst 5648500 # number of demand (read+write) miss cycles -system.cpu2.icache.demand_miss_latency::total 5648500 # number of demand (read+write) miss cycles -system.cpu2.icache.overall_miss_latency::cpu2.inst 5648500 # number of overall miss cycles -system.cpu2.icache.overall_miss_latency::total 5648500 # number of overall miss cycles -system.cpu2.icache.ReadReq_accesses::cpu2.inst 165597 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.ReadReq_accesses::total 165597 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.demand_accesses::cpu2.inst 165597 # number of demand (read+write) accesses -system.cpu2.icache.demand_accesses::total 165597 # number of demand (read+write) accesses -system.cpu2.icache.overall_accesses::cpu2.inst 165597 # number of overall (read+write) accesses -system.cpu2.icache.overall_accesses::total 165597 # number of overall (read+write) accesses -system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.002210 # miss rate for ReadReq accesses -system.cpu2.icache.ReadReq_miss_rate::total 0.002210 # miss rate for ReadReq accesses -system.cpu2.icache.demand_miss_rate::cpu2.inst 0.002210 # miss rate for demand accesses -system.cpu2.icache.demand_miss_rate::total 0.002210 # miss rate for demand accesses -system.cpu2.icache.overall_miss_rate::cpu2.inst 0.002210 # miss rate for overall accesses -system.cpu2.icache.overall_miss_rate::total 0.002210 # miss rate for overall accesses -system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 15433.060109 # average ReadReq miss latency -system.cpu2.icache.ReadReq_avg_miss_latency::total 15433.060109 # average ReadReq miss latency -system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 15433.060109 # average overall miss latency -system.cpu2.icache.demand_avg_miss_latency::total 15433.060109 # average overall miss latency -system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 15433.060109 # average overall miss latency -system.cpu2.icache.overall_avg_miss_latency::total 15433.060109 # average overall miss latency +system.cpu2.icache.occ_blocks::cpu2.inst 67.531468 # Average occupied blocks per requestor +system.cpu2.icache.occ_percent::cpu2.inst 0.131897 # Average percentage of cache occupancy +system.cpu2.icache.occ_percent::total 0.131897 # Average percentage of cache occupancy +system.cpu2.icache.ReadReq_hits::cpu2.inst 176887 # number of ReadReq hits +system.cpu2.icache.ReadReq_hits::total 176887 # number of ReadReq hits +system.cpu2.icache.demand_hits::cpu2.inst 176887 # number of demand (read+write) hits +system.cpu2.icache.demand_hits::total 176887 # number of demand (read+write) hits +system.cpu2.icache.overall_hits::cpu2.inst 176887 # number of overall hits +system.cpu2.icache.overall_hits::total 176887 # number of overall hits +system.cpu2.icache.ReadReq_misses::cpu2.inst 367 # number of ReadReq misses +system.cpu2.icache.ReadReq_misses::total 367 # number of ReadReq misses +system.cpu2.icache.demand_misses::cpu2.inst 367 # number of demand (read+write) misses +system.cpu2.icache.demand_misses::total 367 # number of demand (read+write) misses +system.cpu2.icache.overall_misses::cpu2.inst 367 # number of overall misses +system.cpu2.icache.overall_misses::total 367 # number of overall misses +system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 5709500 # number of ReadReq miss cycles +system.cpu2.icache.ReadReq_miss_latency::total 5709500 # number of ReadReq miss cycles +system.cpu2.icache.demand_miss_latency::cpu2.inst 5709500 # number of demand (read+write) miss cycles +system.cpu2.icache.demand_miss_latency::total 5709500 # number of demand (read+write) miss cycles +system.cpu2.icache.overall_miss_latency::cpu2.inst 5709500 # number of overall miss cycles +system.cpu2.icache.overall_miss_latency::total 5709500 # number of overall miss cycles +system.cpu2.icache.ReadReq_accesses::cpu2.inst 177254 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.ReadReq_accesses::total 177254 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.demand_accesses::cpu2.inst 177254 # number of demand (read+write) accesses +system.cpu2.icache.demand_accesses::total 177254 # number of demand (read+write) accesses +system.cpu2.icache.overall_accesses::cpu2.inst 177254 # number of overall (read+write) accesses +system.cpu2.icache.overall_accesses::total 177254 # number of overall (read+write) accesses +system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.002070 # miss rate for ReadReq accesses +system.cpu2.icache.ReadReq_miss_rate::total 0.002070 # miss rate for ReadReq accesses +system.cpu2.icache.demand_miss_rate::cpu2.inst 0.002070 # miss rate for demand accesses +system.cpu2.icache.demand_miss_rate::total 0.002070 # miss rate for demand accesses +system.cpu2.icache.overall_miss_rate::cpu2.inst 0.002070 # miss rate for overall accesses +system.cpu2.icache.overall_miss_rate::total 0.002070 # miss rate for overall accesses +system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 15557.220708 # average ReadReq miss latency +system.cpu2.icache.ReadReq_avg_miss_latency::total 15557.220708 # average ReadReq miss latency +system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 15557.220708 # average overall miss latency +system.cpu2.icache.demand_avg_miss_latency::total 15557.220708 # average overall miss latency +system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 15557.220708 # average overall miss latency +system.cpu2.icache.overall_avg_miss_latency::total 15557.220708 # average overall miss latency system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -571,100 +571,100 @@ system.cpu2.icache.avg_blocked_cycles::no_mshrs nan system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu2.icache.fast_writes 0 # number of fast writes performed system.cpu2.icache.cache_copies 0 # number of cache copies performed -system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst 366 # number of ReadReq MSHR misses -system.cpu2.icache.ReadReq_mshr_misses::total 366 # number of ReadReq MSHR misses -system.cpu2.icache.demand_mshr_misses::cpu2.inst 366 # number of demand (read+write) MSHR misses -system.cpu2.icache.demand_mshr_misses::total 366 # number of demand (read+write) MSHR misses -system.cpu2.icache.overall_mshr_misses::cpu2.inst 366 # number of overall MSHR misses -system.cpu2.icache.overall_mshr_misses::total 366 # number of overall MSHR misses -system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 4550500 # number of ReadReq MSHR miss cycles -system.cpu2.icache.ReadReq_mshr_miss_latency::total 4550500 # number of ReadReq MSHR miss cycles -system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 4550500 # number of demand (read+write) MSHR miss cycles -system.cpu2.icache.demand_mshr_miss_latency::total 4550500 # number of demand (read+write) MSHR miss cycles -system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 4550500 # number of overall MSHR miss cycles -system.cpu2.icache.overall_mshr_miss_latency::total 4550500 # number of overall MSHR miss cycles -system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.002210 # mshr miss rate for ReadReq accesses -system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.002210 # mshr miss rate for ReadReq accesses -system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.002210 # mshr miss rate for demand accesses -system.cpu2.icache.demand_mshr_miss_rate::total 0.002210 # mshr miss rate for demand accesses -system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.002210 # mshr miss rate for overall accesses -system.cpu2.icache.overall_mshr_miss_rate::total 0.002210 # mshr miss rate for overall accesses -system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12433.060109 # average ReadReq mshr miss latency -system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 12433.060109 # average ReadReq mshr miss latency -system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 12433.060109 # average overall mshr miss latency -system.cpu2.icache.demand_avg_mshr_miss_latency::total 12433.060109 # average overall mshr miss latency -system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 12433.060109 # average overall mshr miss latency -system.cpu2.icache.overall_avg_mshr_miss_latency::total 12433.060109 # average overall mshr miss latency +system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst 367 # number of ReadReq MSHR misses +system.cpu2.icache.ReadReq_mshr_misses::total 367 # number of ReadReq MSHR misses +system.cpu2.icache.demand_mshr_misses::cpu2.inst 367 # number of demand (read+write) MSHR misses +system.cpu2.icache.demand_mshr_misses::total 367 # number of demand (read+write) MSHR misses +system.cpu2.icache.overall_mshr_misses::cpu2.inst 367 # number of overall MSHR misses +system.cpu2.icache.overall_mshr_misses::total 367 # number of overall MSHR misses +system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 4608500 # number of ReadReq MSHR miss cycles +system.cpu2.icache.ReadReq_mshr_miss_latency::total 4608500 # number of ReadReq MSHR miss cycles +system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 4608500 # number of demand (read+write) MSHR miss cycles +system.cpu2.icache.demand_mshr_miss_latency::total 4608500 # number of demand (read+write) MSHR miss cycles +system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 4608500 # number of overall MSHR miss cycles +system.cpu2.icache.overall_mshr_miss_latency::total 4608500 # number of overall MSHR miss cycles +system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.002070 # mshr miss rate for ReadReq accesses +system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.002070 # mshr miss rate for ReadReq accesses +system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.002070 # mshr miss rate for demand accesses +system.cpu2.icache.demand_mshr_miss_rate::total 0.002070 # mshr miss rate for demand accesses +system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.002070 # mshr miss rate for overall accesses +system.cpu2.icache.overall_mshr_miss_rate::total 0.002070 # mshr miss rate for overall accesses +system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12557.220708 # average ReadReq mshr miss latency +system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 12557.220708 # average ReadReq mshr miss latency +system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 12557.220708 # average overall mshr miss latency +system.cpu2.icache.demand_avg_mshr_miss_latency::total 12557.220708 # average overall mshr miss latency +system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 12557.220708 # average overall mshr miss latency +system.cpu2.icache.overall_avg_mshr_miss_latency::total 12557.220708 # average overall mshr miss latency system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu2.dcache.replacements 0 # number of replacements -system.cpu2.dcache.tagsinuse 25.974144 # Cycle average of tags in use -system.cpu2.dcache.total_refs 34436 # Total number of references to valid blocks. +system.cpu2.dcache.tagsinuse 26.637011 # Cycle average of tags in use +system.cpu2.dcache.total_refs 17171 # Total number of references to valid blocks. system.cpu2.dcache.sampled_refs 29 # Sample count of references to valid blocks. -system.cpu2.dcache.avg_refs 1187.448276 # Average number of references to valid blocks. +system.cpu2.dcache.avg_refs 592.103448 # Average number of references to valid blocks. system.cpu2.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.dcache.occ_blocks::cpu2.data 25.974144 # Average occupied blocks per requestor -system.cpu2.dcache.occ_percent::cpu2.data 0.050731 # Average percentage of cache occupancy -system.cpu2.dcache.occ_percent::total 0.050731 # Average percentage of cache occupancy -system.cpu2.dcache.ReadReq_hits::cpu2.data 41706 # number of ReadReq hits -system.cpu2.dcache.ReadReq_hits::total 41706 # number of ReadReq hits -system.cpu2.dcache.WriteReq_hits::cpu2.data 15916 # number of WriteReq hits -system.cpu2.dcache.WriteReq_hits::total 15916 # number of WriteReq hits -system.cpu2.dcache.SwapReq_hits::cpu2.data 11 # number of SwapReq hits -system.cpu2.dcache.SwapReq_hits::total 11 # number of SwapReq hits -system.cpu2.dcache.demand_hits::cpu2.data 57622 # number of demand (read+write) hits -system.cpu2.dcache.demand_hits::total 57622 # number of demand (read+write) hits -system.cpu2.dcache.overall_hits::cpu2.data 57622 # number of overall hits -system.cpu2.dcache.overall_hits::total 57622 # number of overall hits -system.cpu2.dcache.ReadReq_misses::cpu2.data 154 # number of ReadReq misses -system.cpu2.dcache.ReadReq_misses::total 154 # number of ReadReq misses -system.cpu2.dcache.WriteReq_misses::cpu2.data 109 # number of WriteReq misses -system.cpu2.dcache.WriteReq_misses::total 109 # number of WriteReq misses +system.cpu2.dcache.occ_blocks::cpu2.data 26.637011 # Average occupied blocks per requestor +system.cpu2.dcache.occ_percent::cpu2.data 0.052025 # Average percentage of cache occupancy +system.cpu2.dcache.occ_percent::total 0.052025 # Average percentage of cache occupancy +system.cpu2.dcache.ReadReq_hits::cpu2.data 40266 # number of ReadReq hits +system.cpu2.dcache.ReadReq_hits::total 40266 # number of ReadReq hits +system.cpu2.dcache.WriteReq_hits::cpu2.data 7273 # number of WriteReq hits +system.cpu2.dcache.WriteReq_hits::total 7273 # number of WriteReq hits +system.cpu2.dcache.SwapReq_hits::cpu2.data 18 # number of SwapReq hits +system.cpu2.dcache.SwapReq_hits::total 18 # number of SwapReq hits +system.cpu2.dcache.demand_hits::cpu2.data 47539 # number of demand (read+write) hits +system.cpu2.dcache.demand_hits::total 47539 # number of demand (read+write) hits +system.cpu2.dcache.overall_hits::cpu2.data 47539 # number of overall hits +system.cpu2.dcache.overall_hits::total 47539 # number of overall hits +system.cpu2.dcache.ReadReq_misses::cpu2.data 173 # number of ReadReq misses +system.cpu2.dcache.ReadReq_misses::total 173 # number of ReadReq misses +system.cpu2.dcache.WriteReq_misses::cpu2.data 105 # number of WriteReq misses +system.cpu2.dcache.WriteReq_misses::total 105 # number of WriteReq misses system.cpu2.dcache.SwapReq_misses::cpu2.data 51 # number of SwapReq misses system.cpu2.dcache.SwapReq_misses::total 51 # number of SwapReq misses -system.cpu2.dcache.demand_misses::cpu2.data 263 # number of demand (read+write) misses -system.cpu2.dcache.demand_misses::total 263 # number of demand (read+write) misses -system.cpu2.dcache.overall_misses::cpu2.data 263 # number of overall misses -system.cpu2.dcache.overall_misses::total 263 # number of overall misses -system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 2498000 # number of ReadReq miss cycles -system.cpu2.dcache.ReadReq_miss_latency::total 2498000 # number of ReadReq miss cycles -system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 2031000 # number of WriteReq miss cycles -system.cpu2.dcache.WriteReq_miss_latency::total 2031000 # number of WriteReq miss cycles -system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 305000 # number of SwapReq miss cycles -system.cpu2.dcache.SwapReq_miss_latency::total 305000 # number of SwapReq miss cycles -system.cpu2.dcache.demand_miss_latency::cpu2.data 4529000 # number of demand (read+write) miss cycles -system.cpu2.dcache.demand_miss_latency::total 4529000 # number of demand (read+write) miss cycles -system.cpu2.dcache.overall_miss_latency::cpu2.data 4529000 # number of overall miss cycles -system.cpu2.dcache.overall_miss_latency::total 4529000 # number of overall miss cycles -system.cpu2.dcache.ReadReq_accesses::cpu2.data 41860 # number of ReadReq accesses(hits+misses) -system.cpu2.dcache.ReadReq_accesses::total 41860 # number of ReadReq accesses(hits+misses) -system.cpu2.dcache.WriteReq_accesses::cpu2.data 16025 # number of WriteReq accesses(hits+misses) -system.cpu2.dcache.WriteReq_accesses::total 16025 # number of WriteReq accesses(hits+misses) -system.cpu2.dcache.SwapReq_accesses::cpu2.data 62 # number of SwapReq accesses(hits+misses) -system.cpu2.dcache.SwapReq_accesses::total 62 # number of SwapReq accesses(hits+misses) -system.cpu2.dcache.demand_accesses::cpu2.data 57885 # number of demand (read+write) accesses -system.cpu2.dcache.demand_accesses::total 57885 # number of demand (read+write) accesses -system.cpu2.dcache.overall_accesses::cpu2.data 57885 # number of overall (read+write) accesses -system.cpu2.dcache.overall_accesses::total 57885 # number of overall (read+write) accesses -system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.003679 # miss rate for ReadReq accesses -system.cpu2.dcache.ReadReq_miss_rate::total 0.003679 # miss rate for ReadReq accesses -system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.006802 # miss rate for WriteReq accesses -system.cpu2.dcache.WriteReq_miss_rate::total 0.006802 # miss rate for WriteReq accesses -system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.822581 # miss rate for SwapReq accesses -system.cpu2.dcache.SwapReq_miss_rate::total 0.822581 # miss rate for SwapReq accesses -system.cpu2.dcache.demand_miss_rate::cpu2.data 0.004543 # miss rate for demand accesses -system.cpu2.dcache.demand_miss_rate::total 0.004543 # miss rate for demand accesses -system.cpu2.dcache.overall_miss_rate::cpu2.data 0.004543 # miss rate for overall accesses -system.cpu2.dcache.overall_miss_rate::total 0.004543 # miss rate for overall accesses -system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 16220.779221 # average ReadReq miss latency -system.cpu2.dcache.ReadReq_avg_miss_latency::total 16220.779221 # average ReadReq miss latency -system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 18633.027523 # average WriteReq miss latency -system.cpu2.dcache.WriteReq_avg_miss_latency::total 18633.027523 # average WriteReq miss latency -system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 5980.392157 # average SwapReq miss latency -system.cpu2.dcache.SwapReq_avg_miss_latency::total 5980.392157 # average SwapReq miss latency -system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 17220.532319 # average overall miss latency -system.cpu2.dcache.demand_avg_miss_latency::total 17220.532319 # average overall miss latency -system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 17220.532319 # average overall miss latency -system.cpu2.dcache.overall_avg_miss_latency::total 17220.532319 # average overall miss latency +system.cpu2.dcache.demand_misses::cpu2.data 278 # number of demand (read+write) misses +system.cpu2.dcache.demand_misses::total 278 # number of demand (read+write) misses +system.cpu2.dcache.overall_misses::cpu2.data 278 # number of overall misses +system.cpu2.dcache.overall_misses::total 278 # number of overall misses +system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 3995000 # number of ReadReq miss cycles +system.cpu2.dcache.ReadReq_miss_latency::total 3995000 # number of ReadReq miss cycles +system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 2318000 # number of WriteReq miss cycles +system.cpu2.dcache.WriteReq_miss_latency::total 2318000 # number of WriteReq miss cycles +system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 814000 # number of SwapReq miss cycles +system.cpu2.dcache.SwapReq_miss_latency::total 814000 # number of SwapReq miss cycles +system.cpu2.dcache.demand_miss_latency::cpu2.data 6313000 # number of demand (read+write) miss cycles +system.cpu2.dcache.demand_miss_latency::total 6313000 # number of demand (read+write) miss cycles +system.cpu2.dcache.overall_miss_latency::cpu2.data 6313000 # number of overall miss cycles +system.cpu2.dcache.overall_miss_latency::total 6313000 # number of overall miss cycles +system.cpu2.dcache.ReadReq_accesses::cpu2.data 40439 # number of ReadReq accesses(hits+misses) +system.cpu2.dcache.ReadReq_accesses::total 40439 # number of ReadReq accesses(hits+misses) +system.cpu2.dcache.WriteReq_accesses::cpu2.data 7378 # number of WriteReq accesses(hits+misses) +system.cpu2.dcache.WriteReq_accesses::total 7378 # number of WriteReq accesses(hits+misses) +system.cpu2.dcache.SwapReq_accesses::cpu2.data 69 # number of SwapReq accesses(hits+misses) +system.cpu2.dcache.SwapReq_accesses::total 69 # number of SwapReq accesses(hits+misses) +system.cpu2.dcache.demand_accesses::cpu2.data 47817 # number of demand (read+write) accesses +system.cpu2.dcache.demand_accesses::total 47817 # number of demand (read+write) accesses +system.cpu2.dcache.overall_accesses::cpu2.data 47817 # number of overall (read+write) accesses +system.cpu2.dcache.overall_accesses::total 47817 # number of overall (read+write) accesses +system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.004278 # miss rate for ReadReq accesses +system.cpu2.dcache.ReadReq_miss_rate::total 0.004278 # miss rate for ReadReq accesses +system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.014231 # miss rate for WriteReq accesses +system.cpu2.dcache.WriteReq_miss_rate::total 0.014231 # miss rate for WriteReq accesses +system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.739130 # miss rate for SwapReq accesses +system.cpu2.dcache.SwapReq_miss_rate::total 0.739130 # miss rate for SwapReq accesses +system.cpu2.dcache.demand_miss_rate::cpu2.data 0.005814 # miss rate for demand accesses +system.cpu2.dcache.demand_miss_rate::total 0.005814 # miss rate for demand accesses +system.cpu2.dcache.overall_miss_rate::cpu2.data 0.005814 # miss rate for overall accesses +system.cpu2.dcache.overall_miss_rate::total 0.005814 # miss rate for overall accesses +system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 23092.485549 # average ReadReq miss latency +system.cpu2.dcache.ReadReq_avg_miss_latency::total 23092.485549 # average ReadReq miss latency +system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 22076.190476 # average WriteReq miss latency +system.cpu2.dcache.WriteReq_avg_miss_latency::total 22076.190476 # average WriteReq miss latency +system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 15960.784314 # average SwapReq miss latency +system.cpu2.dcache.SwapReq_avg_miss_latency::total 15960.784314 # average SwapReq miss latency +system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 22708.633094 # average overall miss latency +system.cpu2.dcache.demand_avg_miss_latency::total 22708.633094 # average overall miss latency +system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 22708.633094 # average overall miss latency +system.cpu2.dcache.overall_avg_miss_latency::total 22708.633094 # average overall miss latency system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -673,114 +673,114 @@ system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu2.dcache.fast_writes 0 # number of fast writes performed system.cpu2.dcache.cache_copies 0 # number of cache copies performed -system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 154 # number of ReadReq MSHR misses -system.cpu2.dcache.ReadReq_mshr_misses::total 154 # number of ReadReq MSHR misses -system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 109 # number of WriteReq MSHR misses -system.cpu2.dcache.WriteReq_mshr_misses::total 109 # number of WriteReq MSHR misses +system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 173 # number of ReadReq MSHR misses +system.cpu2.dcache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses +system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 105 # number of WriteReq MSHR misses +system.cpu2.dcache.WriteReq_mshr_misses::total 105 # number of WriteReq MSHR misses system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 51 # number of SwapReq MSHR misses system.cpu2.dcache.SwapReq_mshr_misses::total 51 # number of SwapReq MSHR misses -system.cpu2.dcache.demand_mshr_misses::cpu2.data 263 # number of demand (read+write) MSHR misses -system.cpu2.dcache.demand_mshr_misses::total 263 # number of demand (read+write) MSHR misses -system.cpu2.dcache.overall_mshr_misses::cpu2.data 263 # number of overall MSHR misses -system.cpu2.dcache.overall_mshr_misses::total 263 # number of overall MSHR misses -system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 2036000 # number of ReadReq MSHR miss cycles -system.cpu2.dcache.ReadReq_mshr_miss_latency::total 2036000 # number of ReadReq MSHR miss cycles -system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1704000 # number of WriteReq MSHR miss cycles -system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1704000 # number of WriteReq MSHR miss cycles -system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 152000 # number of SwapReq MSHR miss cycles -system.cpu2.dcache.SwapReq_mshr_miss_latency::total 152000 # number of SwapReq MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 3740000 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_latency::total 3740000 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 3740000 # number of overall MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_latency::total 3740000 # number of overall MSHR miss cycles -system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003679 # mshr miss rate for ReadReq accesses -system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003679 # mshr miss rate for ReadReq accesses -system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.006802 # mshr miss rate for WriteReq accesses -system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.006802 # mshr miss rate for WriteReq accesses -system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.822581 # mshr miss rate for SwapReq accesses -system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.822581 # mshr miss rate for SwapReq accesses -system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.004543 # mshr miss rate for demand accesses -system.cpu2.dcache.demand_mshr_miss_rate::total 0.004543 # mshr miss rate for demand accesses -system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.004543 # mshr miss rate for overall accesses -system.cpu2.dcache.overall_mshr_miss_rate::total 0.004543 # mshr miss rate for overall accesses -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 13220.779221 # average ReadReq mshr miss latency -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 13220.779221 # average ReadReq mshr miss latency -system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 15633.027523 # average WriteReq mshr miss latency -system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 15633.027523 # average WriteReq mshr miss latency -system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 2980.392157 # average SwapReq mshr miss latency -system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 2980.392157 # average SwapReq mshr miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 14220.532319 # average overall mshr miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency::total 14220.532319 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 14220.532319 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency::total 14220.532319 # average overall mshr miss latency +system.cpu2.dcache.demand_mshr_misses::cpu2.data 278 # number of demand (read+write) MSHR misses +system.cpu2.dcache.demand_mshr_misses::total 278 # number of demand (read+write) MSHR misses +system.cpu2.dcache.overall_mshr_misses::cpu2.data 278 # number of overall MSHR misses +system.cpu2.dcache.overall_mshr_misses::total 278 # number of overall MSHR misses +system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 3476000 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_latency::total 3476000 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 2003000 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_latency::total 2003000 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 661000 # number of SwapReq MSHR miss cycles +system.cpu2.dcache.SwapReq_mshr_miss_latency::total 661000 # number of SwapReq MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 5479000 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_latency::total 5479000 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 5479000 # number of overall MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_latency::total 5479000 # number of overall MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.004278 # mshr miss rate for ReadReq accesses +system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.004278 # mshr miss rate for ReadReq accesses +system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.014231 # mshr miss rate for WriteReq accesses +system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.014231 # mshr miss rate for WriteReq accesses +system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.739130 # mshr miss rate for SwapReq accesses +system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.739130 # mshr miss rate for SwapReq accesses +system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.005814 # mshr miss rate for demand accesses +system.cpu2.dcache.demand_mshr_miss_rate::total 0.005814 # mshr miss rate for demand accesses +system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.005814 # mshr miss rate for overall accesses +system.cpu2.dcache.overall_mshr_miss_rate::total 0.005814 # mshr miss rate for overall accesses +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 20092.485549 # average ReadReq mshr miss latency +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 20092.485549 # average ReadReq mshr miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 19076.190476 # average WriteReq mshr miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 19076.190476 # average WriteReq mshr miss latency +system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 12960.784314 # average SwapReq mshr miss latency +system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 12960.784314 # average SwapReq mshr miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 19708.633094 # average overall mshr miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency::total 19708.633094 # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 19708.633094 # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency::total 19708.633094 # average overall mshr miss latency system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.numCycles 524598 # number of cpu cycles simulated +system.cpu3.numCycles 537824 # number of cpu cycles simulated system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu3.committedInsts 166196 # Number of instructions committed -system.cpu3.committedOps 166196 # Number of ops (including micro ops) committed -system.cpu3.num_int_alu_accesses 112131 # Number of integer alu accesses +system.cpu3.committedInsts 172067 # Number of instructions committed +system.cpu3.committedOps 172067 # Number of ops (including micro ops) committed +system.cpu3.num_int_alu_accesses 111206 # Number of integer alu accesses system.cpu3.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu3.num_func_calls 637 # number of times a function call or return occured -system.cpu3.num_conditional_control_insts 31040 # number of instructions that are conditional controls -system.cpu3.num_int_insts 112131 # number of integer instructions +system.cpu3.num_conditional_control_insts 34437 # number of instructions that are conditional controls +system.cpu3.num_int_insts 111206 # number of integer instructions system.cpu3.num_fp_insts 0 # number of float instructions -system.cpu3.num_int_register_reads 286557 # number of times the integer registers were read -system.cpu3.num_int_register_writes 109409 # number of times the integer registers were written +system.cpu3.num_int_register_reads 269314 # number of times the integer registers were read +system.cpu3.num_int_register_writes 101322 # number of times the integer registers were written system.cpu3.num_fp_register_reads 0 # number of times the floating registers were read system.cpu3.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu3.num_mem_refs 57260 # number of memory refs -system.cpu3.num_load_insts 41737 # Number of load instructions -system.cpu3.num_store_insts 15523 # Number of store instructions -system.cpu3.num_idle_cycles 69252.001736 # Number of idle cycles -system.cpu3.num_busy_cycles 455345.998264 # Number of busy cycles -system.cpu3.not_idle_fraction 0.867990 # Percentage of non-idle cycles -system.cpu3.idle_fraction 0.132010 # Percentage of idle cycles -system.cpu3.icache.replacements 281 # number of replacements -system.cpu3.icache.tagsinuse 67.739564 # Cycle average of tags in use -system.cpu3.icache.total_refs 165862 # Total number of references to valid blocks. -system.cpu3.icache.sampled_refs 367 # Sample count of references to valid blocks. -system.cpu3.icache.avg_refs 451.940054 # Average number of references to valid blocks. +system.cpu3.num_mem_refs 52937 # number of memory refs +system.cpu3.num_load_insts 41268 # Number of load instructions +system.cpu3.num_store_insts 11669 # Number of store instructions +system.cpu3.num_idle_cycles 72158.001732 # Number of idle cycles +system.cpu3.num_busy_cycles 465665.998268 # Number of busy cycles +system.cpu3.not_idle_fraction 0.865833 # Percentage of non-idle cycles +system.cpu3.idle_fraction 0.134167 # Percentage of idle cycles +system.cpu3.icache.replacements 280 # number of replacements +system.cpu3.icache.tagsinuse 65.342080 # Cycle average of tags in use +system.cpu3.icache.total_refs 171734 # Total number of references to valid blocks. +system.cpu3.icache.sampled_refs 366 # Sample count of references to valid blocks. +system.cpu3.icache.avg_refs 469.218579 # Average number of references to valid blocks. system.cpu3.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.icache.occ_blocks::cpu3.inst 67.739564 # Average occupied blocks per requestor -system.cpu3.icache.occ_percent::cpu3.inst 0.132304 # Average percentage of cache occupancy -system.cpu3.icache.occ_percent::total 0.132304 # Average percentage of cache occupancy -system.cpu3.icache.ReadReq_hits::cpu3.inst 165862 # number of ReadReq hits -system.cpu3.icache.ReadReq_hits::total 165862 # number of ReadReq hits -system.cpu3.icache.demand_hits::cpu3.inst 165862 # number of demand (read+write) hits -system.cpu3.icache.demand_hits::total 165862 # number of demand (read+write) hits -system.cpu3.icache.overall_hits::cpu3.inst 165862 # number of overall hits -system.cpu3.icache.overall_hits::total 165862 # number of overall hits -system.cpu3.icache.ReadReq_misses::cpu3.inst 367 # number of ReadReq misses -system.cpu3.icache.ReadReq_misses::total 367 # number of ReadReq misses -system.cpu3.icache.demand_misses::cpu3.inst 367 # number of demand (read+write) misses -system.cpu3.icache.demand_misses::total 367 # number of demand (read+write) misses -system.cpu3.icache.overall_misses::cpu3.inst 367 # number of overall misses -system.cpu3.icache.overall_misses::total 367 # number of overall misses -system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 5533500 # number of ReadReq miss cycles -system.cpu3.icache.ReadReq_miss_latency::total 5533500 # number of ReadReq miss cycles -system.cpu3.icache.demand_miss_latency::cpu3.inst 5533500 # number of demand (read+write) miss cycles -system.cpu3.icache.demand_miss_latency::total 5533500 # number of demand (read+write) miss cycles -system.cpu3.icache.overall_miss_latency::cpu3.inst 5533500 # number of overall miss cycles -system.cpu3.icache.overall_miss_latency::total 5533500 # number of overall miss cycles -system.cpu3.icache.ReadReq_accesses::cpu3.inst 166229 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.ReadReq_accesses::total 166229 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.demand_accesses::cpu3.inst 166229 # number of demand (read+write) accesses -system.cpu3.icache.demand_accesses::total 166229 # number of demand (read+write) accesses -system.cpu3.icache.overall_accesses::cpu3.inst 166229 # number of overall (read+write) accesses -system.cpu3.icache.overall_accesses::total 166229 # number of overall (read+write) accesses -system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.002208 # miss rate for ReadReq accesses -system.cpu3.icache.ReadReq_miss_rate::total 0.002208 # miss rate for ReadReq accesses -system.cpu3.icache.demand_miss_rate::cpu3.inst 0.002208 # miss rate for demand accesses -system.cpu3.icache.demand_miss_rate::total 0.002208 # miss rate for demand accesses -system.cpu3.icache.overall_miss_rate::cpu3.inst 0.002208 # miss rate for overall accesses -system.cpu3.icache.overall_miss_rate::total 0.002208 # miss rate for overall accesses -system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 15077.656676 # average ReadReq miss latency -system.cpu3.icache.ReadReq_avg_miss_latency::total 15077.656676 # average ReadReq miss latency -system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 15077.656676 # average overall miss latency -system.cpu3.icache.demand_avg_miss_latency::total 15077.656676 # average overall miss latency -system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 15077.656676 # average overall miss latency -system.cpu3.icache.overall_avg_miss_latency::total 15077.656676 # average overall miss latency +system.cpu3.icache.occ_blocks::cpu3.inst 65.342080 # Average occupied blocks per requestor +system.cpu3.icache.occ_percent::cpu3.inst 0.127621 # Average percentage of cache occupancy +system.cpu3.icache.occ_percent::total 0.127621 # Average percentage of cache occupancy +system.cpu3.icache.ReadReq_hits::cpu3.inst 171734 # number of ReadReq hits +system.cpu3.icache.ReadReq_hits::total 171734 # number of ReadReq hits +system.cpu3.icache.demand_hits::cpu3.inst 171734 # number of demand (read+write) hits +system.cpu3.icache.demand_hits::total 171734 # number of demand (read+write) hits +system.cpu3.icache.overall_hits::cpu3.inst 171734 # number of overall hits +system.cpu3.icache.overall_hits::total 171734 # number of overall hits +system.cpu3.icache.ReadReq_misses::cpu3.inst 366 # number of ReadReq misses +system.cpu3.icache.ReadReq_misses::total 366 # number of ReadReq misses +system.cpu3.icache.demand_misses::cpu3.inst 366 # number of demand (read+write) misses +system.cpu3.icache.demand_misses::total 366 # number of demand (read+write) misses +system.cpu3.icache.overall_misses::cpu3.inst 366 # number of overall misses +system.cpu3.icache.overall_misses::total 366 # number of overall misses +system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 5645500 # number of ReadReq miss cycles +system.cpu3.icache.ReadReq_miss_latency::total 5645500 # number of ReadReq miss cycles +system.cpu3.icache.demand_miss_latency::cpu3.inst 5645500 # number of demand (read+write) miss cycles +system.cpu3.icache.demand_miss_latency::total 5645500 # number of demand (read+write) miss cycles +system.cpu3.icache.overall_miss_latency::cpu3.inst 5645500 # number of overall miss cycles +system.cpu3.icache.overall_miss_latency::total 5645500 # number of overall miss cycles +system.cpu3.icache.ReadReq_accesses::cpu3.inst 172100 # number of ReadReq accesses(hits+misses) +system.cpu3.icache.ReadReq_accesses::total 172100 # number of ReadReq accesses(hits+misses) +system.cpu3.icache.demand_accesses::cpu3.inst 172100 # number of demand (read+write) accesses +system.cpu3.icache.demand_accesses::total 172100 # number of demand (read+write) accesses +system.cpu3.icache.overall_accesses::cpu3.inst 172100 # number of overall (read+write) accesses +system.cpu3.icache.overall_accesses::total 172100 # number of overall (read+write) accesses +system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.002127 # miss rate for ReadReq accesses +system.cpu3.icache.ReadReq_miss_rate::total 0.002127 # miss rate for ReadReq accesses +system.cpu3.icache.demand_miss_rate::cpu3.inst 0.002127 # miss rate for demand accesses +system.cpu3.icache.demand_miss_rate::total 0.002127 # miss rate for demand accesses +system.cpu3.icache.overall_miss_rate::cpu3.inst 0.002127 # miss rate for overall accesses +system.cpu3.icache.overall_miss_rate::total 0.002127 # miss rate for overall accesses +system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 15424.863388 # average ReadReq miss latency +system.cpu3.icache.ReadReq_avg_miss_latency::total 15424.863388 # average ReadReq miss latency +system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 15424.863388 # average overall miss latency +system.cpu3.icache.demand_avg_miss_latency::total 15424.863388 # average overall miss latency +system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 15424.863388 # average overall miss latency +system.cpu3.icache.overall_avg_miss_latency::total 15424.863388 # average overall miss latency system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -789,100 +789,100 @@ system.cpu3.icache.avg_blocked_cycles::no_mshrs nan system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu3.icache.fast_writes 0 # number of fast writes performed system.cpu3.icache.cache_copies 0 # number of cache copies performed -system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst 367 # number of ReadReq MSHR misses -system.cpu3.icache.ReadReq_mshr_misses::total 367 # number of ReadReq MSHR misses -system.cpu3.icache.demand_mshr_misses::cpu3.inst 367 # number of demand (read+write) MSHR misses -system.cpu3.icache.demand_mshr_misses::total 367 # number of demand (read+write) MSHR misses -system.cpu3.icache.overall_mshr_misses::cpu3.inst 367 # number of overall MSHR misses -system.cpu3.icache.overall_mshr_misses::total 367 # number of overall MSHR misses -system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 4432500 # number of ReadReq MSHR miss cycles -system.cpu3.icache.ReadReq_mshr_miss_latency::total 4432500 # number of ReadReq MSHR miss cycles -system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 4432500 # number of demand (read+write) MSHR miss cycles -system.cpu3.icache.demand_mshr_miss_latency::total 4432500 # number of demand (read+write) MSHR miss cycles -system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 4432500 # number of overall MSHR miss cycles -system.cpu3.icache.overall_mshr_miss_latency::total 4432500 # number of overall MSHR miss cycles -system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.002208 # mshr miss rate for ReadReq accesses -system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.002208 # mshr miss rate for ReadReq accesses -system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.002208 # mshr miss rate for demand accesses -system.cpu3.icache.demand_mshr_miss_rate::total 0.002208 # mshr miss rate for demand accesses -system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.002208 # mshr miss rate for overall accesses -system.cpu3.icache.overall_mshr_miss_rate::total 0.002208 # mshr miss rate for overall accesses -system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12077.656676 # average ReadReq mshr miss latency -system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 12077.656676 # average ReadReq mshr miss latency -system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 12077.656676 # average overall mshr miss latency -system.cpu3.icache.demand_avg_mshr_miss_latency::total 12077.656676 # average overall mshr miss latency -system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 12077.656676 # average overall mshr miss latency -system.cpu3.icache.overall_avg_mshr_miss_latency::total 12077.656676 # average overall mshr miss latency +system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst 366 # number of ReadReq MSHR misses +system.cpu3.icache.ReadReq_mshr_misses::total 366 # number of ReadReq MSHR misses +system.cpu3.icache.demand_mshr_misses::cpu3.inst 366 # number of demand (read+write) MSHR misses +system.cpu3.icache.demand_mshr_misses::total 366 # number of demand (read+write) MSHR misses +system.cpu3.icache.overall_mshr_misses::cpu3.inst 366 # number of overall MSHR misses +system.cpu3.icache.overall_mshr_misses::total 366 # number of overall MSHR misses +system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 4547000 # number of ReadReq MSHR miss cycles +system.cpu3.icache.ReadReq_mshr_miss_latency::total 4547000 # number of ReadReq MSHR miss cycles +system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 4547000 # number of demand (read+write) MSHR miss cycles +system.cpu3.icache.demand_mshr_miss_latency::total 4547000 # number of demand (read+write) MSHR miss cycles +system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 4547000 # number of overall MSHR miss cycles +system.cpu3.icache.overall_mshr_miss_latency::total 4547000 # number of overall MSHR miss cycles +system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.002127 # mshr miss rate for ReadReq accesses +system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.002127 # mshr miss rate for ReadReq accesses +system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.002127 # mshr miss rate for demand accesses +system.cpu3.icache.demand_mshr_miss_rate::total 0.002127 # mshr miss rate for demand accesses +system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.002127 # mshr miss rate for overall accesses +system.cpu3.icache.overall_mshr_miss_rate::total 0.002127 # mshr miss rate for overall accesses +system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12423.497268 # average ReadReq mshr miss latency +system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 12423.497268 # average ReadReq mshr miss latency +system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 12423.497268 # average overall mshr miss latency +system.cpu3.icache.demand_avg_mshr_miss_latency::total 12423.497268 # average overall mshr miss latency +system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 12423.497268 # average overall mshr miss latency +system.cpu3.icache.overall_avg_mshr_miss_latency::total 12423.497268 # average overall mshr miss latency system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu3.dcache.replacements 0 # number of replacements -system.cpu3.dcache.tagsinuse 26.774212 # Cycle average of tags in use -system.cpu3.dcache.total_refs 33417 # Total number of references to valid blocks. +system.cpu3.dcache.tagsinuse 25.848817 # Cycle average of tags in use +system.cpu3.dcache.total_refs 25744 # Total number of references to valid blocks. system.cpu3.dcache.sampled_refs 30 # Sample count of references to valid blocks. -system.cpu3.dcache.avg_refs 1113.900000 # Average number of references to valid blocks. +system.cpu3.dcache.avg_refs 858.133333 # Average number of references to valid blocks. system.cpu3.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.dcache.occ_blocks::cpu3.data 26.774212 # Average occupied blocks per requestor -system.cpu3.dcache.occ_percent::cpu3.data 0.052293 # Average percentage of cache occupancy -system.cpu3.dcache.occ_percent::total 0.052293 # Average percentage of cache occupancy -system.cpu3.dcache.ReadReq_hits::cpu3.data 41574 # number of ReadReq hits -system.cpu3.dcache.ReadReq_hits::total 41574 # number of ReadReq hits -system.cpu3.dcache.WriteReq_hits::cpu3.data 15348 # number of WriteReq hits -system.cpu3.dcache.WriteReq_hits::total 15348 # number of WriteReq hits -system.cpu3.dcache.SwapReq_hits::cpu3.data 11 # number of SwapReq hits -system.cpu3.dcache.SwapReq_hits::total 11 # number of SwapReq hits -system.cpu3.dcache.demand_hits::cpu3.data 56922 # number of demand (read+write) hits -system.cpu3.dcache.demand_hits::total 56922 # number of demand (read+write) hits -system.cpu3.dcache.overall_hits::cpu3.data 56922 # number of overall hits -system.cpu3.dcache.overall_hits::total 56922 # number of overall hits -system.cpu3.dcache.ReadReq_misses::cpu3.data 155 # number of ReadReq misses -system.cpu3.dcache.ReadReq_misses::total 155 # number of ReadReq misses -system.cpu3.dcache.WriteReq_misses::cpu3.data 108 # number of WriteReq misses -system.cpu3.dcache.WriteReq_misses::total 108 # number of WriteReq misses -system.cpu3.dcache.SwapReq_misses::cpu3.data 54 # number of SwapReq misses -system.cpu3.dcache.SwapReq_misses::total 54 # number of SwapReq misses -system.cpu3.dcache.demand_misses::cpu3.data 263 # number of demand (read+write) misses -system.cpu3.dcache.demand_misses::total 263 # number of demand (read+write) misses -system.cpu3.dcache.overall_misses::cpu3.data 263 # number of overall misses -system.cpu3.dcache.overall_misses::total 263 # number of overall misses -system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 2537000 # number of ReadReq miss cycles -system.cpu3.dcache.ReadReq_miss_latency::total 2537000 # number of ReadReq miss cycles -system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 2026000 # number of WriteReq miss cycles -system.cpu3.dcache.WriteReq_miss_latency::total 2026000 # number of WriteReq miss cycles -system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 326000 # number of SwapReq miss cycles -system.cpu3.dcache.SwapReq_miss_latency::total 326000 # number of SwapReq miss cycles -system.cpu3.dcache.demand_miss_latency::cpu3.data 4563000 # number of demand (read+write) miss cycles -system.cpu3.dcache.demand_miss_latency::total 4563000 # number of demand (read+write) miss cycles -system.cpu3.dcache.overall_miss_latency::cpu3.data 4563000 # number of overall miss cycles -system.cpu3.dcache.overall_miss_latency::total 4563000 # number of overall miss cycles -system.cpu3.dcache.ReadReq_accesses::cpu3.data 41729 # number of ReadReq accesses(hits+misses) -system.cpu3.dcache.ReadReq_accesses::total 41729 # number of ReadReq accesses(hits+misses) -system.cpu3.dcache.WriteReq_accesses::cpu3.data 15456 # number of WriteReq accesses(hits+misses) -system.cpu3.dcache.WriteReq_accesses::total 15456 # number of WriteReq accesses(hits+misses) -system.cpu3.dcache.SwapReq_accesses::cpu3.data 65 # number of SwapReq accesses(hits+misses) -system.cpu3.dcache.SwapReq_accesses::total 65 # number of SwapReq accesses(hits+misses) -system.cpu3.dcache.demand_accesses::cpu3.data 57185 # number of demand (read+write) accesses -system.cpu3.dcache.demand_accesses::total 57185 # number of demand (read+write) accesses -system.cpu3.dcache.overall_accesses::cpu3.data 57185 # number of overall (read+write) accesses -system.cpu3.dcache.overall_accesses::total 57185 # number of overall (read+write) accesses -system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.003714 # miss rate for ReadReq accesses -system.cpu3.dcache.ReadReq_miss_rate::total 0.003714 # miss rate for ReadReq accesses -system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.006988 # miss rate for WriteReq accesses -system.cpu3.dcache.WriteReq_miss_rate::total 0.006988 # miss rate for WriteReq accesses -system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.830769 # miss rate for SwapReq accesses -system.cpu3.dcache.SwapReq_miss_rate::total 0.830769 # miss rate for SwapReq accesses -system.cpu3.dcache.demand_miss_rate::cpu3.data 0.004599 # miss rate for demand accesses -system.cpu3.dcache.demand_miss_rate::total 0.004599 # miss rate for demand accesses -system.cpu3.dcache.overall_miss_rate::cpu3.data 0.004599 # miss rate for overall accesses -system.cpu3.dcache.overall_miss_rate::total 0.004599 # miss rate for overall accesses -system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 16367.741935 # average ReadReq miss latency -system.cpu3.dcache.ReadReq_avg_miss_latency::total 16367.741935 # average ReadReq miss latency -system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 18759.259259 # average WriteReq miss latency -system.cpu3.dcache.WriteReq_avg_miss_latency::total 18759.259259 # average WriteReq miss latency -system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 6037.037037 # average SwapReq miss latency -system.cpu3.dcache.SwapReq_avg_miss_latency::total 6037.037037 # average SwapReq miss latency -system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 17349.809886 # average overall miss latency -system.cpu3.dcache.demand_avg_miss_latency::total 17349.809886 # average overall miss latency -system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 17349.809886 # average overall miss latency -system.cpu3.dcache.overall_avg_miss_latency::total 17349.809886 # average overall miss latency +system.cpu3.dcache.occ_blocks::cpu3.data 25.848817 # Average occupied blocks per requestor +system.cpu3.dcache.occ_percent::cpu3.data 0.050486 # Average percentage of cache occupancy +system.cpu3.dcache.occ_percent::total 0.050486 # Average percentage of cache occupancy +system.cpu3.dcache.ReadReq_hits::cpu3.data 41084 # number of ReadReq hits +system.cpu3.dcache.ReadReq_hits::total 41084 # number of ReadReq hits +system.cpu3.dcache.WriteReq_hits::cpu3.data 11491 # number of WriteReq hits +system.cpu3.dcache.WriteReq_hits::total 11491 # number of WriteReq hits +system.cpu3.dcache.SwapReq_hits::cpu3.data 12 # number of SwapReq hits +system.cpu3.dcache.SwapReq_hits::total 12 # number of SwapReq hits +system.cpu3.dcache.demand_hits::cpu3.data 52575 # number of demand (read+write) hits +system.cpu3.dcache.demand_hits::total 52575 # number of demand (read+write) hits +system.cpu3.dcache.overall_hits::cpu3.data 52575 # number of overall hits +system.cpu3.dcache.overall_hits::total 52575 # number of overall hits +system.cpu3.dcache.ReadReq_misses::cpu3.data 176 # number of ReadReq misses +system.cpu3.dcache.ReadReq_misses::total 176 # number of ReadReq misses +system.cpu3.dcache.WriteReq_misses::cpu3.data 105 # number of WriteReq misses +system.cpu3.dcache.WriteReq_misses::total 105 # number of WriteReq misses +system.cpu3.dcache.SwapReq_misses::cpu3.data 59 # number of SwapReq misses +system.cpu3.dcache.SwapReq_misses::total 59 # number of SwapReq misses +system.cpu3.dcache.demand_misses::cpu3.data 281 # number of demand (read+write) misses +system.cpu3.dcache.demand_misses::total 281 # number of demand (read+write) misses +system.cpu3.dcache.overall_misses::cpu3.data 281 # number of overall misses +system.cpu3.dcache.overall_misses::total 281 # number of overall misses +system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 4401000 # number of ReadReq miss cycles +system.cpu3.dcache.ReadReq_miss_latency::total 4401000 # number of ReadReq miss cycles +system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 1861000 # number of WriteReq miss cycles +system.cpu3.dcache.WriteReq_miss_latency::total 1861000 # number of WriteReq miss cycles +system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 928000 # number of SwapReq miss cycles +system.cpu3.dcache.SwapReq_miss_latency::total 928000 # number of SwapReq miss cycles +system.cpu3.dcache.demand_miss_latency::cpu3.data 6262000 # number of demand (read+write) miss cycles +system.cpu3.dcache.demand_miss_latency::total 6262000 # number of demand (read+write) miss cycles +system.cpu3.dcache.overall_miss_latency::cpu3.data 6262000 # number of overall miss cycles +system.cpu3.dcache.overall_miss_latency::total 6262000 # number of overall miss cycles +system.cpu3.dcache.ReadReq_accesses::cpu3.data 41260 # number of ReadReq accesses(hits+misses) +system.cpu3.dcache.ReadReq_accesses::total 41260 # number of ReadReq accesses(hits+misses) +system.cpu3.dcache.WriteReq_accesses::cpu3.data 11596 # number of WriteReq accesses(hits+misses) +system.cpu3.dcache.WriteReq_accesses::total 11596 # number of WriteReq accesses(hits+misses) +system.cpu3.dcache.SwapReq_accesses::cpu3.data 71 # number of SwapReq accesses(hits+misses) +system.cpu3.dcache.SwapReq_accesses::total 71 # number of SwapReq accesses(hits+misses) +system.cpu3.dcache.demand_accesses::cpu3.data 52856 # number of demand (read+write) accesses +system.cpu3.dcache.demand_accesses::total 52856 # number of demand (read+write) accesses +system.cpu3.dcache.overall_accesses::cpu3.data 52856 # number of overall (read+write) accesses +system.cpu3.dcache.overall_accesses::total 52856 # number of overall (read+write) accesses +system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.004266 # miss rate for ReadReq accesses +system.cpu3.dcache.ReadReq_miss_rate::total 0.004266 # miss rate for ReadReq accesses +system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.009055 # miss rate for WriteReq accesses +system.cpu3.dcache.WriteReq_miss_rate::total 0.009055 # miss rate for WriteReq accesses +system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.830986 # miss rate for SwapReq accesses +system.cpu3.dcache.SwapReq_miss_rate::total 0.830986 # miss rate for SwapReq accesses +system.cpu3.dcache.demand_miss_rate::cpu3.data 0.005316 # miss rate for demand accesses +system.cpu3.dcache.demand_miss_rate::total 0.005316 # miss rate for demand accesses +system.cpu3.dcache.overall_miss_rate::cpu3.data 0.005316 # miss rate for overall accesses +system.cpu3.dcache.overall_miss_rate::total 0.005316 # miss rate for overall accesses +system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 25005.681818 # average ReadReq miss latency +system.cpu3.dcache.ReadReq_avg_miss_latency::total 25005.681818 # average ReadReq miss latency +system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 17723.809524 # average WriteReq miss latency +system.cpu3.dcache.WriteReq_avg_miss_latency::total 17723.809524 # average WriteReq miss latency +system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 15728.813559 # average SwapReq miss latency +system.cpu3.dcache.SwapReq_avg_miss_latency::total 15728.813559 # average SwapReq miss latency +system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 22284.697509 # average overall miss latency +system.cpu3.dcache.demand_avg_miss_latency::total 22284.697509 # average overall miss latency +system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 22284.697509 # average overall miss latency +system.cpu3.dcache.overall_avg_miss_latency::total 22284.697509 # average overall miss latency system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -891,81 +891,81 @@ system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu3.dcache.fast_writes 0 # number of fast writes performed system.cpu3.dcache.cache_copies 0 # number of cache copies performed -system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 155 # number of ReadReq MSHR misses -system.cpu3.dcache.ReadReq_mshr_misses::total 155 # number of ReadReq MSHR misses -system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 108 # number of WriteReq MSHR misses -system.cpu3.dcache.WriteReq_mshr_misses::total 108 # number of WriteReq MSHR misses -system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 54 # number of SwapReq MSHR misses -system.cpu3.dcache.SwapReq_mshr_misses::total 54 # number of SwapReq MSHR misses -system.cpu3.dcache.demand_mshr_misses::cpu3.data 263 # number of demand (read+write) MSHR misses -system.cpu3.dcache.demand_mshr_misses::total 263 # number of demand (read+write) MSHR misses -system.cpu3.dcache.overall_mshr_misses::cpu3.data 263 # number of overall MSHR misses -system.cpu3.dcache.overall_mshr_misses::total 263 # number of overall MSHR misses -system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 2072000 # number of ReadReq MSHR miss cycles -system.cpu3.dcache.ReadReq_mshr_miss_latency::total 2072000 # number of ReadReq MSHR miss cycles -system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1702000 # number of WriteReq MSHR miss cycles -system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1702000 # number of WriteReq MSHR miss cycles -system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 164000 # number of SwapReq MSHR miss cycles -system.cpu3.dcache.SwapReq_mshr_miss_latency::total 164000 # number of SwapReq MSHR miss cycles -system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 3774000 # number of demand (read+write) MSHR miss cycles -system.cpu3.dcache.demand_mshr_miss_latency::total 3774000 # number of demand (read+write) MSHR miss cycles -system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 3774000 # number of overall MSHR miss cycles -system.cpu3.dcache.overall_mshr_miss_latency::total 3774000 # number of overall MSHR miss cycles -system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.003714 # mshr miss rate for ReadReq accesses -system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.003714 # mshr miss rate for ReadReq accesses -system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.006988 # mshr miss rate for WriteReq accesses -system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.006988 # mshr miss rate for WriteReq accesses -system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.830769 # mshr miss rate for SwapReq accesses -system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.830769 # mshr miss rate for SwapReq accesses -system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.004599 # mshr miss rate for demand accesses -system.cpu3.dcache.demand_mshr_miss_rate::total 0.004599 # mshr miss rate for demand accesses -system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.004599 # mshr miss rate for overall accesses -system.cpu3.dcache.overall_mshr_miss_rate::total 0.004599 # mshr miss rate for overall accesses -system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 13367.741935 # average ReadReq mshr miss latency -system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 13367.741935 # average ReadReq mshr miss latency -system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 15759.259259 # average WriteReq mshr miss latency -system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 15759.259259 # average WriteReq mshr miss latency -system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 3037.037037 # average SwapReq mshr miss latency -system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 3037.037037 # average SwapReq mshr miss latency -system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 14349.809886 # average overall mshr miss latency -system.cpu3.dcache.demand_avg_mshr_miss_latency::total 14349.809886 # average overall mshr miss latency -system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 14349.809886 # average overall mshr miss latency -system.cpu3.dcache.overall_avg_mshr_miss_latency::total 14349.809886 # average overall mshr miss latency +system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 176 # number of ReadReq MSHR misses +system.cpu3.dcache.ReadReq_mshr_misses::total 176 # number of ReadReq MSHR misses +system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 105 # number of WriteReq MSHR misses +system.cpu3.dcache.WriteReq_mshr_misses::total 105 # number of WriteReq MSHR misses +system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 59 # number of SwapReq MSHR misses +system.cpu3.dcache.SwapReq_mshr_misses::total 59 # number of SwapReq MSHR misses +system.cpu3.dcache.demand_mshr_misses::cpu3.data 281 # number of demand (read+write) MSHR misses +system.cpu3.dcache.demand_mshr_misses::total 281 # number of demand (read+write) MSHR misses +system.cpu3.dcache.overall_mshr_misses::cpu3.data 281 # number of overall MSHR misses +system.cpu3.dcache.overall_mshr_misses::total 281 # number of overall MSHR misses +system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 3873000 # number of ReadReq MSHR miss cycles +system.cpu3.dcache.ReadReq_mshr_miss_latency::total 3873000 # number of ReadReq MSHR miss cycles +system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1546000 # number of WriteReq MSHR miss cycles +system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1546000 # number of WriteReq MSHR miss cycles +system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 751000 # number of SwapReq MSHR miss cycles +system.cpu3.dcache.SwapReq_mshr_miss_latency::total 751000 # number of SwapReq MSHR miss cycles +system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 5419000 # number of demand (read+write) MSHR miss cycles +system.cpu3.dcache.demand_mshr_miss_latency::total 5419000 # number of demand (read+write) MSHR miss cycles +system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 5419000 # number of overall MSHR miss cycles +system.cpu3.dcache.overall_mshr_miss_latency::total 5419000 # number of overall MSHR miss cycles +system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.004266 # mshr miss rate for ReadReq accesses +system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.004266 # mshr miss rate for ReadReq accesses +system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.009055 # mshr miss rate for WriteReq accesses +system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.009055 # mshr miss rate for WriteReq accesses +system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.830986 # mshr miss rate for SwapReq accesses +system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.830986 # mshr miss rate for SwapReq accesses +system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.005316 # mshr miss rate for demand accesses +system.cpu3.dcache.demand_mshr_miss_rate::total 0.005316 # mshr miss rate for demand accesses +system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.005316 # mshr miss rate for overall accesses +system.cpu3.dcache.overall_mshr_miss_rate::total 0.005316 # mshr miss rate for overall accesses +system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 22005.681818 # average ReadReq mshr miss latency +system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 22005.681818 # average ReadReq mshr miss latency +system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 14723.809524 # average WriteReq mshr miss latency +system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 14723.809524 # average WriteReq mshr miss latency +system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 12728.813559 # average SwapReq mshr miss latency +system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 12728.813559 # average SwapReq mshr miss latency +system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 19284.697509 # average overall mshr miss latency +system.cpu3.dcache.demand_avg_mshr_miss_latency::total 19284.697509 # average overall mshr miss latency +system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 19284.697509 # average overall mshr miss latency +system.cpu3.dcache.overall_avg_mshr_miss_latency::total 19284.697509 # average overall mshr miss latency system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.l2c.replacements 0 # number of replacements -system.l2c.tagsinuse 349.180649 # Cycle average of tags in use -system.l2c.total_refs 1220 # Total number of references to valid blocks. +system.l2c.tagsinuse 348.808930 # Cycle average of tags in use +system.l2c.total_refs 1221 # Total number of references to valid blocks. system.l2c.sampled_refs 429 # Sample count of references to valid blocks. -system.l2c.avg_refs 2.843823 # Average number of references to valid blocks. +system.l2c.avg_refs 2.846154 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 0.889759 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 231.859241 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 54.220371 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 51.601321 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 6.129070 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu2.inst 1.917102 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu2.data 0.831909 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu3.inst 0.887228 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu3.data 0.844647 # Average occupied blocks per requestor +system.l2c.occ_blocks::writebacks 0.888060 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.inst 231.678051 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.data 54.187452 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.inst 51.469392 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.data 6.113383 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu2.inst 1.770981 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu2.data 0.842116 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu3.inst 1.030371 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu3.data 0.829126 # Average occupied blocks per requestor system.l2c.occ_percent::writebacks 0.000014 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.003538 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.inst 0.003535 # Average percentage of cache occupancy system.l2c.occ_percent::cpu0.data 0.000827 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.000787 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.data 0.000094 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu2.inst 0.000029 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.inst 0.000785 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.data 0.000093 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu2.inst 0.000027 # Average percentage of cache occupancy system.l2c.occ_percent::cpu2.data 0.000013 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu3.inst 0.000014 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu3.inst 0.000016 # Average percentage of cache occupancy system.l2c.occ_percent::cpu3.data 0.000013 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.005328 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.005322 # Average percentage of cache occupancy system.l2c.ReadReq_hits::cpu0.inst 182 # number of ReadReq hits system.l2c.ReadReq_hits::cpu0.data 5 # number of ReadReq hits system.l2c.ReadReq_hits::cpu1.inst 300 # number of ReadReq hits system.l2c.ReadReq_hits::cpu1.data 3 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.inst 354 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.inst 355 # number of ReadReq hits system.l2c.ReadReq_hits::cpu2.data 9 # number of ReadReq hits system.l2c.ReadReq_hits::cpu3.inst 358 # number of ReadReq hits system.l2c.ReadReq_hits::cpu3.data 9 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1220 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1221 # number of ReadReq hits system.l2c.Writeback_hits::writebacks 1 # number of Writeback hits system.l2c.Writeback_hits::total 1 # number of Writeback hits system.l2c.UpgradeReq_hits::cpu0.data 2 # number of UpgradeReq hits @@ -974,34 +974,34 @@ system.l2c.demand_hits::cpu0.inst 182 # nu system.l2c.demand_hits::cpu0.data 5 # number of demand (read+write) hits system.l2c.demand_hits::cpu1.inst 300 # number of demand (read+write) hits system.l2c.demand_hits::cpu1.data 3 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.inst 354 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.inst 355 # number of demand (read+write) hits system.l2c.demand_hits::cpu2.data 9 # number of demand (read+write) hits system.l2c.demand_hits::cpu3.inst 358 # number of demand (read+write) hits system.l2c.demand_hits::cpu3.data 9 # number of demand (read+write) hits -system.l2c.demand_hits::total 1220 # number of demand (read+write) hits +system.l2c.demand_hits::total 1221 # number of demand (read+write) hits system.l2c.overall_hits::cpu0.inst 182 # number of overall hits system.l2c.overall_hits::cpu0.data 5 # number of overall hits system.l2c.overall_hits::cpu1.inst 300 # number of overall hits system.l2c.overall_hits::cpu1.data 3 # number of overall hits -system.l2c.overall_hits::cpu2.inst 354 # number of overall hits +system.l2c.overall_hits::cpu2.inst 355 # number of overall hits system.l2c.overall_hits::cpu2.data 9 # number of overall hits system.l2c.overall_hits::cpu3.inst 358 # number of overall hits system.l2c.overall_hits::cpu3.data 9 # number of overall hits -system.l2c.overall_hits::total 1220 # number of overall hits +system.l2c.overall_hits::total 1221 # number of overall hits system.l2c.ReadReq_misses::cpu0.inst 285 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.data 66 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.inst 66 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.data 8 # number of ReadReq misses system.l2c.ReadReq_misses::cpu2.inst 12 # number of ReadReq misses system.l2c.ReadReq_misses::cpu2.data 2 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu3.inst 9 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu3.inst 8 # number of ReadReq misses system.l2c.ReadReq_misses::cpu3.data 2 # number of ReadReq misses -system.l2c.ReadReq_misses::total 450 # number of ReadReq misses +system.l2c.ReadReq_misses::total 449 # number of ReadReq misses system.l2c.UpgradeReq_misses::cpu0.data 28 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 11 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu2.data 15 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu3.data 15 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 69 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 20 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu2.data 27 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu3.data 11 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 86 # number of UpgradeReq misses system.l2c.ReadExReq_misses::cpu0.data 99 # number of ReadExReq misses system.l2c.ReadExReq_misses::cpu1.data 15 # number of ReadExReq misses system.l2c.ReadExReq_misses::cpu2.data 14 # number of ReadExReq misses @@ -1013,66 +1013,66 @@ system.l2c.demand_misses::cpu1.inst 66 # nu system.l2c.demand_misses::cpu1.data 23 # number of demand (read+write) misses system.l2c.demand_misses::cpu2.inst 12 # number of demand (read+write) misses system.l2c.demand_misses::cpu2.data 16 # number of demand (read+write) misses -system.l2c.demand_misses::cpu3.inst 9 # number of demand (read+write) misses +system.l2c.demand_misses::cpu3.inst 8 # number of demand (read+write) misses system.l2c.demand_misses::cpu3.data 16 # number of demand (read+write) misses -system.l2c.demand_misses::total 592 # number of demand (read+write) misses +system.l2c.demand_misses::total 591 # number of demand (read+write) misses system.l2c.overall_misses::cpu0.inst 285 # number of overall misses system.l2c.overall_misses::cpu0.data 165 # number of overall misses system.l2c.overall_misses::cpu1.inst 66 # number of overall misses system.l2c.overall_misses::cpu1.data 23 # number of overall misses system.l2c.overall_misses::cpu2.inst 12 # number of overall misses system.l2c.overall_misses::cpu2.data 16 # number of overall misses -system.l2c.overall_misses::cpu3.inst 9 # number of overall misses +system.l2c.overall_misses::cpu3.inst 8 # number of overall misses system.l2c.overall_misses::cpu3.data 16 # number of overall misses -system.l2c.overall_misses::total 592 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.inst 14822000 # number of ReadReq miss cycles +system.l2c.overall_misses::total 591 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu0.inst 14828000 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu0.data 3432000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 3402000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 411000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2.inst 615000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2.data 104000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu3.inst 446000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu3.data 101000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 23333000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.inst 3308000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 398000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu2.inst 529000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu2.data 95000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu3.inst 418000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu3.data 104000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 23112000 # number of ReadReq miss cycles system.l2c.ReadExReq_miss_latency::cpu0.data 5148000 # number of ReadExReq miss cycles system.l2c.ReadExReq_miss_latency::cpu1.data 780000 # number of ReadExReq miss cycles system.l2c.ReadExReq_miss_latency::cpu2.data 728000 # number of ReadExReq miss cycles system.l2c.ReadExReq_miss_latency::cpu3.data 728000 # number of ReadExReq miss cycles system.l2c.ReadExReq_miss_latency::total 7384000 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.inst 14822000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.inst 14828000 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu0.data 8580000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 3402000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 1191000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.inst 615000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.data 832000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu3.inst 446000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu3.data 829000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 30717000 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.inst 14822000 # number of overall miss cycles +system.l2c.demand_miss_latency::cpu1.inst 3308000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 1178000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.inst 529000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.data 823000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu3.inst 418000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu3.data 832000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 30496000 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.inst 14828000 # number of overall miss cycles system.l2c.overall_miss_latency::cpu0.data 8580000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 3402000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 1191000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.inst 615000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.data 832000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu3.inst 446000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu3.data 829000 # number of overall miss cycles -system.l2c.overall_miss_latency::total 30717000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 3308000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 1178000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.inst 529000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.data 823000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu3.inst 418000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu3.data 832000 # number of overall miss cycles +system.l2c.overall_miss_latency::total 30496000 # number of overall miss cycles system.l2c.ReadReq_accesses::cpu0.inst 467 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu0.data 71 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu1.inst 366 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu1.data 11 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.inst 366 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2.inst 367 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu2.data 11 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu3.inst 367 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu3.inst 366 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu3.data 11 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::total 1670 # number of ReadReq accesses(hits+misses) system.l2c.Writeback_accesses::writebacks 1 # number of Writeback accesses(hits+misses) system.l2c.Writeback_accesses::total 1 # number of Writeback accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu0.data 30 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 11 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu2.data 15 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu3.data 15 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 71 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 20 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu2.data 27 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu3.data 11 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 88 # number of UpgradeReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu0.data 99 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu1.data 15 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu2.data 14 # number of ReadExReq accesses(hits+misses) @@ -1082,34 +1082,34 @@ system.l2c.demand_accesses::cpu0.inst 467 # nu system.l2c.demand_accesses::cpu0.data 170 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu1.inst 366 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu1.data 26 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.inst 366 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.inst 367 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu2.data 25 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu3.inst 367 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu3.inst 366 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu3.data 25 # number of demand (read+write) accesses system.l2c.demand_accesses::total 1812 # number of demand (read+write) accesses system.l2c.overall_accesses::cpu0.inst 467 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu0.data 170 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu1.inst 366 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu1.data 26 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.inst 366 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.inst 367 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu2.data 25 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu3.inst 367 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu3.inst 366 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu3.data 25 # number of overall (read+write) accesses system.l2c.overall_accesses::total 1812 # number of overall (read+write) accesses system.l2c.ReadReq_miss_rate::cpu0.inst 0.610278 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu0.data 0.929577 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu1.inst 0.180328 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu1.data 0.727273 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2.inst 0.032787 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2.inst 0.032698 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu2.data 0.181818 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu3.inst 0.024523 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu3.inst 0.021858 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu3.data 0.181818 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.269461 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.268862 # miss rate for ReadReq accesses system.l2c.UpgradeReq_miss_rate::cpu0.data 0.933333 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::cpu2.data 1 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::cpu3.data 1 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.971831 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.977273 # miss rate for UpgradeReq accesses system.l2c.ReadExReq_miss_rate::cpu0.data 1 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::cpu1.data 1 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses @@ -1119,52 +1119,52 @@ system.l2c.demand_miss_rate::cpu0.inst 0.610278 # mi system.l2c.demand_miss_rate::cpu0.data 0.970588 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu1.inst 0.180328 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu1.data 0.884615 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.inst 0.032787 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.inst 0.032698 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu2.data 0.640000 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu3.inst 0.024523 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu3.inst 0.021858 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu3.data 0.640000 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.326711 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.326159 # miss rate for demand accesses system.l2c.overall_miss_rate::cpu0.inst 0.610278 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu0.data 0.970588 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu1.inst 0.180328 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu1.data 0.884615 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.inst 0.032787 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.inst 0.032698 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu2.data 0.640000 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu3.inst 0.024523 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu3.inst 0.021858 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu3.data 0.640000 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.326711 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52007.017544 # average ReadReq miss latency +system.l2c.overall_miss_rate::total 0.326159 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52028.070175 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu0.data 52000 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 51545.454545 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 51375 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2.inst 51250 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2.data 52000 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu3.inst 49555.555556 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu3.data 50500 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 51851.111111 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 50121.212121 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 49750 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2.inst 44083.333333 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2.data 47500 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu3.inst 52250 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu3.data 52000 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 51474.387528 # average ReadReq miss latency system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52000 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::cpu1.data 52000 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::cpu2.data 52000 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::cpu3.data 52000 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 52007.017544 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 52028.070175 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu0.data 52000 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 51545.454545 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 51782.608696 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.inst 51250 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.data 52000 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu3.inst 49555.555556 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu3.data 51812.500000 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 51886.824324 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 52007.017544 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 50121.212121 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 51217.391304 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.inst 44083.333333 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.data 51437.500000 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu3.inst 52250 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu3.data 52000 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 51600.676819 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 52028.070175 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu0.data 52000 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 51545.454545 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 51782.608696 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.inst 51250 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.data 52000 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu3.inst 49555.555556 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu3.data 51812.500000 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 51886.824324 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 50121.212121 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 51217.391304 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.inst 44083.333333 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.data 51437.500000 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu3.inst 52250 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu3.data 52000 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 51600.676819 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1175,36 +1175,33 @@ system.l2c.fast_writes 0 # nu system.l2c.cache_copies 0 # number of cache copies performed system.l2c.ReadReq_mshr_hits::cpu1.inst 7 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::cpu1.data 1 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu2.inst 3 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu3.inst 8 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu3.data 1 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::total 20 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu2.inst 10 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu2.data 1 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::total 19 # number of ReadReq MSHR hits system.l2c.demand_mshr_hits::cpu1.inst 7 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_hits::cpu1.data 1 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu2.inst 3 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu3.inst 8 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu3.data 1 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::total 20 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu2.inst 10 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu2.data 1 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::total 19 # number of demand (read+write) MSHR hits system.l2c.overall_mshr_hits::cpu1.inst 7 # number of overall MSHR hits system.l2c.overall_mshr_hits::cpu1.data 1 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu2.inst 3 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu3.inst 8 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu3.data 1 # number of overall MSHR hits -system.l2c.overall_mshr_hits::total 20 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu2.inst 10 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu2.data 1 # number of overall MSHR hits +system.l2c.overall_mshr_hits::total 19 # number of overall MSHR hits system.l2c.ReadReq_mshr_misses::cpu0.inst 285 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu0.data 66 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu1.inst 59 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu1.data 7 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu2.inst 9 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu2.data 2 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu3.inst 1 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu3.data 1 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu2.inst 2 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu2.data 1 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu3.inst 8 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu3.data 2 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::total 430 # number of ReadReq MSHR misses system.l2c.UpgradeReq_mshr_misses::cpu0.data 28 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 11 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu2.data 15 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu3.data 15 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 69 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 20 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu2.data 27 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu3.data 11 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 86 # number of UpgradeReq MSHR misses system.l2c.ReadExReq_mshr_misses::cpu0.data 99 # number of ReadExReq MSHR misses system.l2c.ReadExReq_mshr_misses::cpu1.data 15 # number of ReadExReq MSHR misses system.l2c.ReadExReq_mshr_misses::cpu2.data 14 # number of ReadExReq MSHR misses @@ -1214,71 +1211,71 @@ system.l2c.demand_mshr_misses::cpu0.inst 285 # nu system.l2c.demand_mshr_misses::cpu0.data 165 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu1.inst 59 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu1.data 22 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2.inst 9 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2.data 16 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu3.inst 1 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu3.data 15 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2.inst 2 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2.data 15 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu3.inst 8 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu3.data 16 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::total 572 # number of demand (read+write) MSHR misses system.l2c.overall_mshr_misses::cpu0.inst 285 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu0.data 165 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu1.inst 59 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu1.data 22 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2.inst 9 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2.data 16 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu3.inst 1 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu3.data 15 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2.inst 2 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2.data 15 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu3.inst 8 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu3.data 16 # number of overall MSHR misses system.l2c.overall_mshr_misses::total 572 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 11402000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 11408000 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::cpu0.data 2640000 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 2360000 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::cpu1.data 280000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 361000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2.data 80000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu3.inst 40000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu3.data 40000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 17203000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 80000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2.data 40000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu3.inst 322000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu3.data 80000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 17210000 # number of ReadReq MSHR miss cycles system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 1120000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 440000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 600000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data 600000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 2760000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 800000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 1080000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data 440000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 3440000 # number of UpgradeReq MSHR miss cycles system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 3960000 # number of ReadExReq MSHR miss cycles system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 600000 # number of ReadExReq MSHR miss cycles system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 560000 # number of ReadExReq MSHR miss cycles system.l2c.ReadExReq_mshr_miss_latency::cpu3.data 560000 # number of ReadExReq MSHR miss cycles system.l2c.ReadExReq_mshr_miss_latency::total 5680000 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 11402000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 11408000 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu0.data 6600000 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu1.inst 2360000 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu1.data 880000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2.inst 361000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2.data 640000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu3.inst 40000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu3.data 600000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 22883000 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 11402000 # number of overall MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.inst 80000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.data 600000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu3.inst 322000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu3.data 640000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 22890000 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 11408000 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu0.data 6600000 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu1.inst 2360000 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu1.data 880000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.inst 361000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.data 640000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu3.inst 40000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu3.data 600000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 22883000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.inst 80000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.data 600000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu3.inst 322000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu3.data 640000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 22890000 # number of overall MSHR miss cycles system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.610278 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.929577 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.161202 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.636364 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.024590 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.181818 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu3.inst 0.002725 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu3.data 0.090909 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.005450 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.090909 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu3.inst 0.021858 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu3.data 0.181818 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::total 0.257485 # mshr miss rate for ReadReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.933333 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.971831 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.977273 # mshr miss rate for UpgradeReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for ReadExReq accesses @@ -1288,29 +1285,29 @@ system.l2c.demand_mshr_miss_rate::cpu0.inst 0.610278 # system.l2c.demand_mshr_miss_rate::cpu0.data 0.970588 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu1.inst 0.161202 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu1.data 0.846154 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.inst 0.024590 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.data 0.640000 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu3.inst 0.002725 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu3.data 0.600000 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.inst 0.005450 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.data 0.600000 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3.inst 0.021858 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3.data 0.640000 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::total 0.315673 # mshr miss rate for demand accesses system.l2c.overall_mshr_miss_rate::cpu0.inst 0.610278 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu0.data 0.970588 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu1.inst 0.161202 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu1.data 0.846154 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.inst 0.024590 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.data 0.640000 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu3.inst 0.002725 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu3.data 0.600000 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.inst 0.005450 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.data 0.600000 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3.inst 0.021858 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3.data 0.640000 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::total 0.315673 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40007.017544 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40028.070175 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40000 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40000 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 40111.111111 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 40000 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 40000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst 40000 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst 40250 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.data 40000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 40006.976744 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 40023.255814 # average ReadReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40000 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40000 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 40000 # average UpgradeReq mshr miss latency @@ -1321,24 +1318,24 @@ system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40000 system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 40000 # average ReadExReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 40000 # average ReadExReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40007.017544 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40028.070175 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40000 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40000 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 40111.111111 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 40000 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu2.data 40000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 40000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 40250 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu3.data 40000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 40005.244755 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40007.017544 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40017.482517 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40028.070175 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40000 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40000 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 40111.111111 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 40000 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu2.data 40000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 40000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 40250 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu3.data 40000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 40005.244755 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40017.482517 # average overall mshr miss latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest/simerr b/tests/quick/se/50.memtest/ref/alpha/linux/memtest/simerr index a874a3f37..b8bd8a115 100755 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest/simerr +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest/simerr @@ -1,74 +1,74 @@ -system.cpu4: completed 10000 read, 5380 write accesses @22344646 -system.cpu6: completed 10000 read, 5214 write accesses @22747629 -system.cpu7: completed 10000 read, 5415 write accesses @22929508 -system.cpu2: completed 10000 read, 5407 write accesses @23019836 -system.cpu5: completed 10000 read, 5331 write accesses @23061044 -system.cpu0: completed 10000 read, 5432 write accesses @23140146 -system.cpu3: completed 10000 read, 5376 write accesses @23188049 -system.cpu1: completed 10000 read, 5387 write accesses @23350185 -system.cpu4: completed 20000 read, 10814 write accesses @44761691 -system.cpu7: completed 20000 read, 10827 write accesses @45213444 -system.cpu1: completed 20000 read, 10711 write accesses @45275122 -system.cpu6: completed 20000 read, 10548 write accesses @45324102 -system.cpu3: completed 20000 read, 10701 write accesses @45506880 -system.cpu2: completed 20000 read, 10922 write accesses @45734056 -system.cpu5: completed 20000 read, 10686 write accesses @45942373 -system.cpu0: completed 20000 read, 10937 write accesses @46044746 -system.cpu7: completed 30000 read, 16167 write accesses @66979485 -system.cpu4: completed 30000 read, 16361 write accesses @67223162 -system.cpu6: completed 30000 read, 15931 write accesses @67873351 -system.cpu3: completed 30000 read, 16353 write accesses @68348826 -system.cpu5: completed 30000 read, 16080 write accesses @68377482 -system.cpu1: completed 30000 read, 16196 write accesses @68419268 -system.cpu0: completed 30000 read, 16219 write accesses @68619325 -system.cpu2: completed 30000 read, 16526 write accesses @68648506 -system.cpu4: completed 40000 read, 21581 write accesses @88592659 -system.cpu7: completed 40000 read, 21651 write accesses @88863809 -system.cpu6: completed 40000 read, 21187 write accesses @89230569 -system.cpu1: completed 40000 read, 21556 write accesses @89813083 -system.cpu2: completed 40000 read, 21771 write accesses @90046604 -system.cpu3: completed 40000 read, 21725 write accesses @90210729 -system.cpu5: completed 40000 read, 21435 write accesses @90283858 -system.cpu0: completed 40000 read, 21836 write accesses @90947960 -system.cpu4: completed 50000 read, 27034 write accesses @111338978 -system.cpu6: completed 50000 read, 26346 write accesses @111492478 -system.cpu1: completed 50000 read, 26820 write accesses @112199634 -system.cpu7: completed 50000 read, 27390 write accesses @112358430 -system.cpu5: completed 50000 read, 26711 write accesses @112747804 -system.cpu3: completed 50000 read, 27030 write accesses @113062631 -system.cpu2: completed 50000 read, 27246 write accesses @113387493 -system.cpu0: completed 50000 read, 27088 write accesses @113621350 -system.cpu4: completed 60000 read, 32322 write accesses @134108306 -system.cpu6: completed 60000 read, 31811 write accesses @134700049 -system.cpu2: completed 60000 read, 32452 write accesses @135470855 -system.cpu1: completed 60000 read, 32239 write accesses @135474213 -system.cpu7: completed 60000 read, 32783 write accesses @135487924 -system.cpu5: completed 60000 read, 32297 write accesses @135551091 -system.cpu3: completed 60000 read, 32475 write accesses @135953364 -system.cpu0: completed 60000 read, 32594 write accesses @136506452 -system.cpu4: completed 70000 read, 37624 write accesses @156509147 -system.cpu6: completed 70000 read, 37191 write accesses @157507230 -system.cpu2: completed 70000 read, 37791 write accesses @158024045 -system.cpu7: completed 70000 read, 38252 write accesses @158415918 -system.cpu1: completed 70000 read, 37644 write accesses @158423190 -system.cpu5: completed 70000 read, 37691 write accesses @158678523 -system.cpu3: completed 70000 read, 38021 write accesses @158813067 -system.cpu0: completed 70000 read, 37965 write accesses @159679646 -system.cpu4: completed 80000 read, 42948 write accesses @178855235 -system.cpu6: completed 80000 read, 42510 write accesses @180069540 -system.cpu2: completed 80000 read, 43201 write accesses @180702038 -system.cpu1: completed 80000 read, 43267 write accesses @181114200 -system.cpu7: completed 80000 read, 43705 write accesses @181378010 -system.cpu3: completed 80000 read, 43552 write accesses @181443642 -system.cpu5: completed 80000 read, 43080 write accesses @181574154 -system.cpu0: completed 80000 read, 43418 write accesses @182451715 -system.cpu4: completed 90000 read, 48279 write accesses @201435873 -system.cpu6: completed 90000 read, 47918 write accesses @202390012 -system.cpu2: completed 90000 read, 48513 write accesses @203087400 -system.cpu1: completed 90000 read, 48611 write accesses @203141768 -system.cpu7: completed 90000 read, 48973 write accesses @204050544 -system.cpu5: completed 90000 read, 48423 write accesses @204299514 -system.cpu0: completed 90000 read, 48663 write accesses @204396348 -system.cpu3: completed 90000 read, 48999 write accesses @204475748 -system.cpu4: completed 100000 read, 53697 write accesses @224044586 +system.cpu3: completed 10000 read, 5269 write accesses @22241329 +system.cpu6: completed 10000 read, 5339 write accesses @22510874 +system.cpu4: completed 10000 read, 5452 write accesses @22618520 +system.cpu2: completed 10000 read, 5274 write accesses @22652245 +system.cpu5: completed 10000 read, 5225 write accesses @22698654 +system.cpu0: completed 10000 read, 5313 write accesses @22972460 +system.cpu1: completed 10000 read, 5425 write accesses @23112052 +system.cpu7: completed 10000 read, 5664 write accesses @23303588 +system.cpu3: completed 20000 read, 10591 write accesses @44494817 +system.cpu6: completed 20000 read, 10810 write accesses @44620430 +system.cpu2: completed 20000 read, 10802 write accesses @45009184 +system.cpu0: completed 20000 read, 10643 write accesses @45009224 +system.cpu5: completed 20000 read, 10647 write accesses @45039314 +system.cpu1: completed 20000 read, 10757 write accesses @45068735 +system.cpu4: completed 20000 read, 10808 write accesses @45199458 +system.cpu7: completed 20000 read, 11080 write accesses @45757070 +system.cpu2: completed 30000 read, 16115 write accesses @67069204 +system.cpu3: completed 30000 read, 16110 write accesses @67286000 +system.cpu5: completed 30000 read, 16163 write accesses @67388496 +system.cpu4: completed 30000 read, 16262 write accesses @67495238 +system.cpu6: completed 30000 read, 16234 write accesses @67566368 +system.cpu0: completed 30000 read, 16102 write accesses @67625583 +system.cpu1: completed 30000 read, 16288 write accesses @67665372 +system.cpu7: completed 30000 read, 16608 write accesses @68406261 +system.cpu4: completed 40000 read, 21521 write accesses @88522458 +system.cpu2: completed 40000 read, 21461 write accesses @88760475 +system.cpu5: completed 40000 read, 21540 write accesses @88851958 +system.cpu3: completed 40000 read, 21536 write accesses @88901742 +system.cpu6: completed 40000 read, 21498 write accesses @88910943 +system.cpu1: completed 40000 read, 21730 write accesses @89071047 +system.cpu0: completed 40000 read, 21414 write accesses @89232143 +system.cpu7: completed 40000 read, 22063 write accesses @90453997 +system.cpu4: completed 50000 read, 26910 write accesses @111349230 +system.cpu1: completed 50000 read, 26996 write accesses @111399385 +system.cpu2: completed 50000 read, 26807 write accesses @111571994 +system.cpu6: completed 50000 read, 26876 write accesses @111619105 +system.cpu3: completed 50000 read, 27009 write accesses @111789131 +system.cpu0: completed 50000 read, 26777 write accesses @111829265 +system.cpu5: completed 50000 read, 26952 write accesses @111861140 +system.cpu7: completed 50000 read, 27397 write accesses @112901639 +system.cpu1: completed 60000 read, 32331 write accesses @134016224 +system.cpu2: completed 60000 read, 32246 write accesses @134236668 +system.cpu4: completed 60000 read, 32290 write accesses @134236929 +system.cpu5: completed 60000 read, 32370 write accesses @134256674 +system.cpu6: completed 60000 read, 32444 write accesses @134707450 +system.cpu0: completed 60000 read, 32183 write accesses @134767456 +system.cpu3: completed 60000 read, 32423 write accesses @134996472 +system.cpu7: completed 60000 read, 32735 write accesses @135678114 +system.cpu2: completed 70000 read, 37600 write accesses @156516476 +system.cpu1: completed 70000 read, 37730 write accesses @156721328 +system.cpu5: completed 70000 read, 37748 write accesses @156805205 +system.cpu6: completed 70000 read, 37760 write accesses @156910635 +system.cpu4: completed 70000 read, 37725 write accesses @156961462 +system.cpu0: completed 70000 read, 37635 write accesses @158012668 +system.cpu3: completed 70000 read, 37942 write accesses @158279756 +system.cpu7: completed 70000 read, 38031 write accesses @158283192 +system.cpu5: completed 80000 read, 43255 write accesses @179067469 +system.cpu2: completed 80000 read, 43125 write accesses @179091672 +system.cpu1: completed 80000 read, 43134 write accesses @179182044 +system.cpu6: completed 80000 read, 43119 write accesses @179350821 +system.cpu4: completed 80000 read, 43054 write accesses @179621308 +system.cpu7: completed 80000 read, 43393 write accesses @180749386 +system.cpu0: completed 80000 read, 43229 write accesses @180793374 +system.cpu3: completed 80000 read, 43339 write accesses @180920432 +system.cpu6: completed 90000 read, 48363 write accesses @201441693 +system.cpu2: completed 90000 read, 48516 write accesses @201463344 +system.cpu5: completed 90000 read, 48731 write accesses @201471872 +system.cpu1: completed 90000 read, 48576 write accesses @201752753 +system.cpu4: completed 90000 read, 48432 write accesses @201853284 +system.cpu7: completed 90000 read, 48666 write accesses @202980078 +system.cpu3: completed 90000 read, 48647 write accesses @203163876 +system.cpu0: completed 90000 read, 48482 write accesses @203365064 +system.cpu6: completed 100000 read, 53510 write accesses @223713460 hack: be nice to actually delete the event here diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest/simout b/tests/quick/se/50.memtest/ref/alpha/linux/memtest/simout index 2045d5848..ed860ddcf 100755 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest/simout +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 28 2012 22:05:18 -gem5 started Jun 28 2012 22:09:54 +gem5 compiled Jul 2 2012 08:30:56 +gem5 started Jul 2 2012 09:08:41 gem5 executing on zizzer command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/quick/se/50.memtest/alpha/linux/memtest -re tests/run.py build/ALPHA/tests/fast/quick/se/50.memtest/alpha/linux/memtest Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 224044586 because maximum number of loads reached +Exiting @ tick 223713460 because maximum number of loads reached diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest/stats.txt b/tests/quick/se/50.memtest/ref/alpha/linux/memtest/stats.txt index 9c1b7f7cc..1fe48d0c8 100644 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest/stats.txt +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest/stats.txt @@ -1,637 +1,640 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000224 # Number of seconds simulated -sim_ticks 224044586 # Number of ticks simulated -final_tick 224044586 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 223713460 # Number of ticks simulated +final_tick 223713460 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_tick_rate 1786168 # Simulator tick rate (ticks/s) -host_mem_usage 347548 # Number of bytes of host memory used -host_seconds 125.43 # Real time elapsed on the host -system.physmem.bytes_read::cpu0 89715 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1 89291 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2 88175 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3 85667 # Number of bytes read from this memory -system.physmem.bytes_read::cpu4 87042 # Number of bytes read from this memory -system.physmem.bytes_read::cpu5 87583 # Number of bytes read from this memory -system.physmem.bytes_read::cpu6 89679 # Number of bytes read from this memory -system.physmem.bytes_read::cpu7 83220 # Number of bytes read from this memory -system.physmem.bytes_read::total 700372 # Number of bytes read from this memory -system.physmem.bytes_written::writebacks 455360 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0 5322 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1 5377 # Number of bytes written to this memory -system.physmem.bytes_written::cpu2 5241 # Number of bytes written to this memory -system.physmem.bytes_written::cpu3 5325 # Number of bytes written to this memory -system.physmem.bytes_written::cpu4 5339 # Number of bytes written to this memory -system.physmem.bytes_written::cpu5 5367 # Number of bytes written to this memory -system.physmem.bytes_written::cpu6 5444 # Number of bytes written to this memory -system.physmem.bytes_written::cpu7 5417 # Number of bytes written to this memory -system.physmem.bytes_written::total 498192 # Number of bytes written to this memory -system.physmem.num_reads::cpu0 11091 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1 11171 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2 11126 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3 11075 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu4 11127 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu5 11038 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu6 11244 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu7 11085 # Number of read requests responded to by this memory -system.physmem.num_reads::total 88957 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 7115 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0 5322 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1 5377 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu2 5241 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu3 5325 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu4 5339 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu5 5367 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu6 5444 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu7 5417 # Number of write requests responded to by this memory -system.physmem.num_writes::total 49947 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0 400433689 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1 398541208 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2 393560057 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3 382365856 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu4 388503028 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu5 390917726 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu6 400273006 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu7 371443923 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3126038493 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2032452594 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0 23754200 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1 23999687 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu2 23392665 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu3 23767591 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu4 23830078 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu5 23955053 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu6 24298735 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu7 24178223 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2223628827 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2032452594 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0 424187889 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1 422540895 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2 416952722 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3 406133447 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu4 412333106 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu5 414872779 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu6 424571741 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu7 395622146 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 5349667320 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 14607 # number of replacements -system.l2c.tagsinuse 798.832185 # Cycle average of tags in use -system.l2c.total_refs 150557 # Total number of references to valid blocks. -system.l2c.sampled_refs 15432 # Sample count of references to valid blocks. -system.l2c.avg_refs 9.756156 # Average number of references to valid blocks. +host_tick_rate 1721618 # Simulator tick rate (ticks/s) +host_mem_usage 347508 # Number of bytes of host memory used +host_seconds 129.94 # Real time elapsed on the host +system.physmem.bytes_read::cpu0 81065 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1 82807 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2 84800 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3 80115 # Number of bytes read from this memory +system.physmem.bytes_read::cpu4 83878 # Number of bytes read from this memory +system.physmem.bytes_read::cpu5 83050 # Number of bytes read from this memory +system.physmem.bytes_read::cpu6 84723 # Number of bytes read from this memory +system.physmem.bytes_read::cpu7 83101 # Number of bytes read from this memory +system.physmem.bytes_read::total 663539 # Number of bytes read from this memory +system.physmem.bytes_written::writebacks 423360 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0 5290 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1 5393 # Number of bytes written to this memory +system.physmem.bytes_written::cpu2 5404 # Number of bytes written to this memory +system.physmem.bytes_written::cpu3 5324 # Number of bytes written to this memory +system.physmem.bytes_written::cpu4 5344 # Number of bytes written to this memory +system.physmem.bytes_written::cpu5 5398 # Number of bytes written to this memory +system.physmem.bytes_written::cpu6 5445 # Number of bytes written to this memory +system.physmem.bytes_written::cpu7 5412 # Number of bytes written to this memory +system.physmem.bytes_written::total 466370 # Number of bytes written to this memory +system.physmem.num_reads::cpu0 11135 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1 11050 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2 11090 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3 11067 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu4 11176 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu5 11041 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu6 11139 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu7 11029 # Number of read requests responded to by this memory +system.physmem.num_reads::total 88727 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 6615 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0 5290 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1 5393 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu2 5404 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu3 5324 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu4 5344 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu5 5398 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu6 5445 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu7 5412 # Number of write requests responded to by this memory +system.physmem.num_writes::total 49625 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0 362360852 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1 370147599 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2 379056316 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3 358114349 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu4 374934973 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu5 371233810 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu6 378712126 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu7 371461780 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2966021803 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1892420778 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0 23646320 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1 24106730 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu2 24155900 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu3 23798300 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu4 23887700 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu5 24129080 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu6 24339170 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu7 24191660 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2084675638 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1892420778 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0 386007172 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1 394254329 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2 403212216 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3 381912648 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu4 398822673 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu5 395362890 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu6 403051296 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu7 395653440 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 5050697441 # Total bandwidth to/from this memory (bytes/s) +system.l2c.replacements 13635 # number of replacements +system.l2c.tagsinuse 790.382632 # Cycle average of tags in use +system.l2c.total_refs 148986 # Total number of references to valid blocks. +system.l2c.sampled_refs 14447 # Sample count of references to valid blocks. +system.l2c.avg_refs 10.312591 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 740.812109 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0 7.661361 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1 7.247095 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu2 7.177515 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu3 6.855610 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu4 7.321397 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu5 7.120032 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu6 7.753138 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu7 6.883928 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.723449 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0 0.007482 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1 0.007077 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu2 0.007009 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu3 0.006695 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu4 0.007150 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu5 0.006953 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu6 0.007571 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu7 0.006723 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.780110 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0 10638 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1 10673 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2 10871 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu3 10613 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu4 10754 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu5 10954 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu6 10851 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu7 10889 # number of ReadReq hits -system.l2c.ReadReq_hits::total 86243 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 75632 # number of Writeback hits -system.l2c.Writeback_hits::total 75632 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0 330 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1 349 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu2 360 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu3 350 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu4 332 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu5 339 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu6 326 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu7 357 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 2743 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu0 1980 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1 1883 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu2 1924 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu3 2003 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu4 1977 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu5 1920 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu6 1982 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu7 1896 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 15565 # number of ReadExReq hits -system.l2c.demand_hits::cpu0 12618 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1 12556 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2 12795 # number of demand (read+write) hits -system.l2c.demand_hits::cpu3 12616 # number of demand (read+write) hits -system.l2c.demand_hits::cpu4 12731 # number of demand (read+write) hits -system.l2c.demand_hits::cpu5 12874 # number of demand (read+write) hits -system.l2c.demand_hits::cpu6 12833 # number of demand (read+write) hits -system.l2c.demand_hits::cpu7 12785 # number of demand (read+write) hits -system.l2c.demand_hits::total 101808 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0 12618 # number of overall hits -system.l2c.overall_hits::cpu1 12556 # number of overall hits -system.l2c.overall_hits::cpu2 12795 # number of overall hits -system.l2c.overall_hits::cpu3 12616 # number of overall hits -system.l2c.overall_hits::cpu4 12731 # number of overall hits -system.l2c.overall_hits::cpu5 12874 # number of overall hits -system.l2c.overall_hits::cpu6 12833 # number of overall hits -system.l2c.overall_hits::cpu7 12785 # number of overall hits -system.l2c.overall_hits::total 101808 # number of overall hits -system.l2c.ReadReq_misses::cpu0 834 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1 832 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2 822 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu3 780 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu4 790 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu5 794 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu6 838 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu7 736 # number of ReadReq misses -system.l2c.ReadReq_misses::total 6426 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0 1913 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1 1876 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu2 1922 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu3 2012 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu4 1999 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu5 1918 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu6 1887 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu7 1932 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 15459 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::cpu0 4394 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1 4308 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu2 4316 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu3 4354 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu4 4292 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu5 4292 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu6 4233 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu7 4328 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 34517 # number of ReadExReq misses -system.l2c.demand_misses::cpu0 5228 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1 5140 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2 5138 # number of demand (read+write) misses -system.l2c.demand_misses::cpu3 5134 # number of demand (read+write) misses -system.l2c.demand_misses::cpu4 5082 # number of demand (read+write) misses -system.l2c.demand_misses::cpu5 5086 # number of demand (read+write) misses -system.l2c.demand_misses::cpu6 5071 # number of demand (read+write) misses -system.l2c.demand_misses::cpu7 5064 # number of demand (read+write) misses -system.l2c.demand_misses::total 40943 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0 5228 # number of overall misses -system.l2c.overall_misses::cpu1 5140 # number of overall misses -system.l2c.overall_misses::cpu2 5138 # number of overall misses -system.l2c.overall_misses::cpu3 5134 # number of overall misses -system.l2c.overall_misses::cpu4 5082 # number of overall misses -system.l2c.overall_misses::cpu5 5086 # number of overall misses -system.l2c.overall_misses::cpu6 5071 # number of overall misses -system.l2c.overall_misses::cpu7 5064 # number of overall misses -system.l2c.overall_misses::total 40943 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0 41350032 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1 41129977 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2 40786420 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu3 38596362 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu4 39278271 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu5 39541044 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu6 41568753 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu7 36525760 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 318776619 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0 49804280 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1 51885731 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu2 53676097 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu3 52486307 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu4 52437029 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu5 51272005 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu6 52254582 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu7 52654576 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 416470607 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0 219461654 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1 215283667 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu2 215604529 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu3 217440085 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu4 214512687 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu5 214479862 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu6 211622352 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu7 216182446 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 1724587282 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0 260811686 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1 256413644 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2 256390949 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu3 256036447 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu4 253790958 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu5 254020906 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu6 253191105 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu7 252708206 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 2043363901 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0 260811686 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1 256413644 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2 256390949 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu3 256036447 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu4 253790958 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu5 254020906 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu6 253191105 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu7 252708206 # number of overall miss cycles -system.l2c.overall_miss_latency::total 2043363901 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0 11472 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1 11505 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2 11693 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu3 11393 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu4 11544 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu5 11748 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu6 11689 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu7 11625 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 92669 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 75632 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 75632 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0 2243 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1 2225 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu2 2282 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu3 2362 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu4 2331 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu5 2257 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu6 2213 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu7 2289 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 18202 # number of UpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0 6374 # number of ReadExReq accesses(hits+misses) +system.l2c.occ_blocks::writebacks 735.582494 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0 6.455373 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1 6.652747 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu2 6.865494 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu3 6.639169 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu4 7.152690 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu5 7.266868 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu6 7.044725 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu7 6.723074 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.718342 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0 0.006304 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1 0.006497 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu2 0.006705 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu3 0.006484 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu4 0.006985 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu5 0.007097 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu6 0.006880 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu7 0.006566 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.771858 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0 10736 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1 10614 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2 10598 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu3 10656 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu4 10639 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu5 10502 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu6 10784 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu7 10768 # number of ReadReq hits +system.l2c.ReadReq_hits::total 85297 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 74602 # number of Writeback hits +system.l2c.Writeback_hits::total 74602 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0 364 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1 332 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu2 337 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu3 343 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu4 366 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu5 372 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu6 359 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu7 320 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 2793 # number of UpgradeReq hits +system.l2c.ReadExReq_hits::cpu0 1921 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1 1802 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu2 1826 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu3 1918 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu4 1884 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu5 1935 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu6 1883 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu7 1847 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 15016 # number of ReadExReq hits +system.l2c.demand_hits::cpu0 12657 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1 12416 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2 12424 # number of demand (read+write) hits +system.l2c.demand_hits::cpu3 12574 # number of demand (read+write) hits +system.l2c.demand_hits::cpu4 12523 # number of demand (read+write) hits +system.l2c.demand_hits::cpu5 12437 # number of demand (read+write) hits +system.l2c.demand_hits::cpu6 12667 # number of demand (read+write) hits +system.l2c.demand_hits::cpu7 12615 # number of demand (read+write) hits +system.l2c.demand_hits::total 100313 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0 12657 # number of overall hits +system.l2c.overall_hits::cpu1 12416 # number of overall hits +system.l2c.overall_hits::cpu2 12424 # number of overall hits +system.l2c.overall_hits::cpu3 12574 # number of overall hits +system.l2c.overall_hits::cpu4 12523 # number of overall hits +system.l2c.overall_hits::cpu5 12437 # number of overall hits +system.l2c.overall_hits::cpu6 12667 # number of overall hits +system.l2c.overall_hits::cpu7 12615 # number of overall hits +system.l2c.overall_hits::total 100313 # number of overall hits +system.l2c.ReadReq_misses::cpu0 732 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1 746 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu2 787 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu3 736 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu4 779 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu5 768 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu6 802 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu7 756 # number of ReadReq misses +system.l2c.ReadReq_misses::total 6106 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0 1954 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1 1934 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu2 2007 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu3 1961 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu4 1921 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu5 2008 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu6 1917 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu7 1898 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 15600 # number of UpgradeReq misses +system.l2c.ReadExReq_misses::cpu0 4348 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1 4389 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu2 4257 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu3 4320 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu4 4350 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu5 4337 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu6 4234 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu7 4290 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 34525 # number of ReadExReq misses +system.l2c.demand_misses::cpu0 5080 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1 5135 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2 5044 # number of demand (read+write) misses +system.l2c.demand_misses::cpu3 5056 # number of demand (read+write) misses +system.l2c.demand_misses::cpu4 5129 # number of demand (read+write) misses +system.l2c.demand_misses::cpu5 5105 # number of demand (read+write) misses +system.l2c.demand_misses::cpu6 5036 # number of demand (read+write) misses +system.l2c.demand_misses::cpu7 5046 # number of demand (read+write) misses +system.l2c.demand_misses::total 40631 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0 5080 # number of overall misses +system.l2c.overall_misses::cpu1 5135 # number of overall misses +system.l2c.overall_misses::cpu2 5044 # number of overall misses +system.l2c.overall_misses::cpu3 5056 # number of overall misses +system.l2c.overall_misses::cpu4 5129 # number of overall misses +system.l2c.overall_misses::cpu5 5105 # number of overall misses +system.l2c.overall_misses::cpu6 5036 # number of overall misses +system.l2c.overall_misses::cpu7 5046 # number of overall misses +system.l2c.overall_misses::total 40631 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu0 36182301 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1 37095182 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu2 38839912 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu3 36320452 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu4 38654457 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu5 37981477 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu6 39913673 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu7 37420167 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 302407621 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu0 51570624 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1 52824724 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu2 55089368 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu3 54044648 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu4 51434616 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu5 55447032 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu6 51075446 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu7 51050152 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 422536610 # number of UpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0 217343370 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1 219324999 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu2 212745239 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu3 215838098 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu4 217293309 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu5 216702467 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu6 211504918 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu7 214216755 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 1724969155 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu0 253525671 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1 256420181 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2 251585151 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu3 252158550 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu4 255947766 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu5 254683944 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu6 251418591 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu7 251636922 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 2027376776 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0 253525671 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1 256420181 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2 251585151 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu3 252158550 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu4 255947766 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu5 254683944 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu6 251418591 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu7 251636922 # number of overall miss cycles +system.l2c.overall_miss_latency::total 2027376776 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0 11468 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1 11360 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2 11385 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu3 11392 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu4 11418 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu5 11270 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu6 11586 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu7 11524 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 91403 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 74602 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 74602 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0 2318 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1 2266 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu2 2344 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu3 2304 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu4 2287 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu5 2380 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu6 2276 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu7 2218 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 18393 # number of UpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0 6269 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu1 6191 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu2 6240 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu3 6357 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu4 6269 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu5 6212 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu6 6215 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu7 6224 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 50082 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0 17846 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1 17696 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2 17933 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu3 17750 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu4 17813 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu5 17960 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu6 17904 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu7 17849 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 142751 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0 17846 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1 17696 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2 17933 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu3 17750 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu4 17813 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu5 17960 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu6 17904 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu7 17849 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 142751 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0 0.072699 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1 0.072316 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2 0.070298 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu3 0.068463 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu4 0.068434 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu5 0.067586 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu6 0.071691 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu7 0.063312 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.069344 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0 0.852876 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1 0.843146 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu2 0.842244 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu3 0.851820 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu4 0.857572 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu5 0.849801 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu6 0.852689 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu7 0.844037 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.849302 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0 0.689363 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1 0.695849 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu2 0.691667 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu3 0.684914 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu4 0.684639 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu5 0.690921 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu6 0.681094 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu7 0.695373 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.689210 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0 0.292951 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1 0.290461 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2 0.286511 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu3 0.289239 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu4 0.285297 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu5 0.283185 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu6 0.283233 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu7 0.283713 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.286814 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0 0.292951 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1 0.290461 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2 0.286511 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu3 0.289239 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu4 0.285297 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu5 0.283185 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu6 0.283233 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu7 0.283713 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.286814 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0 49580.374101 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1 49435.068510 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2 49618.515815 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu3 49482.515385 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu4 49719.330380 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu5 49799.803526 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu6 49604.717184 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu7 49627.391304 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 49607.316993 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0 26034.647151 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1 27657.639126 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu2 27927.209677 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu3 26086.633698 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu4 26231.630315 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu5 26732.015120 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu6 27691.882353 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu7 27253.921325 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 26940.332945 # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0 49945.756486 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1 49972.996054 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu2 49954.710148 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu3 49940.304318 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu4 49979.656803 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu5 49972.008854 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu6 49993.468462 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu7 49949.733364 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 49963.417504 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0 49887.468630 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1 49885.922957 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2 49900.924290 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu3 49870.753214 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu4 49939.188902 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu5 49945.125049 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu6 49929.225991 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu7 49902.884281 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 49907.527563 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0 49887.468630 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1 49885.922957 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2 49900.924290 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu3 49870.753214 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu4 49939.188902 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu5 49945.125049 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu6 49929.225991 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu7 49902.884281 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 49907.527563 # average overall miss latency -system.l2c.blocked_cycles::no_mshrs 97509 # number of cycles access was blocked +system.l2c.ReadExReq_accesses::cpu2 6083 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu3 6238 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu4 6234 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu5 6272 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu6 6117 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu7 6137 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 49541 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0 17737 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1 17551 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2 17468 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu3 17630 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu4 17652 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu5 17542 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu6 17703 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu7 17661 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 140944 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0 17737 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1 17551 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2 17468 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu3 17630 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu4 17652 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu5 17542 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu6 17703 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu7 17661 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 140944 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0 0.063830 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1 0.065669 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2 0.069126 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu3 0.064607 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu4 0.068226 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu5 0.068146 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu6 0.069221 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu7 0.065602 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.066803 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0 0.842968 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1 0.853486 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu2 0.856229 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu3 0.851128 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu4 0.839965 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu5 0.843697 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu6 0.842267 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu7 0.855726 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.848149 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0 0.693572 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1 0.708932 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu2 0.699819 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu3 0.692530 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu4 0.697786 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu5 0.691486 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu6 0.692169 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu7 0.699039 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.696898 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0 0.286407 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1 0.292576 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2 0.288757 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu3 0.286784 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu4 0.290562 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu5 0.291016 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu6 0.284472 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu7 0.285714 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.288278 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0 0.286407 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1 0.292576 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2 0.288757 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu3 0.286784 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu4 0.290562 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu5 0.291016 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu6 0.284472 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu7 0.285714 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.288278 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu0 49429.372951 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1 49725.445040 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2 49351.857687 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu3 49348.440217 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu4 49620.612323 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu5 49455.048177 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu6 49767.672070 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu7 49497.575397 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 49526.305437 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu0 26392.335722 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1 27313.714581 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu2 27448.613852 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu3 27559.738909 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu4 26774.917231 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu5 27613.063745 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu6 26643.425143 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu7 26896.813488 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 27085.680128 # average UpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0 49986.975621 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1 49971.519481 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu2 49975.390886 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu3 49962.522685 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu4 49952.484828 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu5 49965.982707 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu6 49953.924894 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu7 49933.975524 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 49962.900941 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu0 49906.628150 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1 49935.770399 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2 49878.102895 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu3 49873.130934 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu4 49902.079548 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu5 49889.117336 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu6 49924.263503 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu7 49868.593341 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 49897.289656 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0 49906.628150 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1 49935.770399 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2 49878.102895 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu3 49873.130934 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu4 49902.079548 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu5 49889.117336 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu6 49924.263503 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu7 49868.593341 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 49897.289656 # average overall miss latency +system.l2c.blocked_cycles::no_mshrs 96627 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.l2c.blocked::no_mshrs 14 # number of cycles access was blocked +system.l2c.blocked::no_mshrs 19 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked -system.l2c.avg_blocked_cycles::no_mshrs 6964.928571 # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles::no_mshrs 5085.631579 # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 7115 # number of writebacks -system.l2c.writebacks::total 7115 # number of writebacks -system.l2c.ReadReq_mshr_hits::cpu0 22 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu1 23 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu2 22 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu3 24 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu4 13 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu5 15 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu6 19 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu7 17 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::total 155 # number of ReadReq MSHR hits -system.l2c.UpgradeReq_mshr_hits::cpu1 4 # number of UpgradeReq MSHR hits +system.l2c.writebacks::writebacks 6616 # number of writebacks +system.l2c.writebacks::total 6616 # number of writebacks +system.l2c.ReadReq_mshr_hits::cpu0 18 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu1 10 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu2 24 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu3 23 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu4 22 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu5 19 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu6 17 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu7 24 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::total 157 # number of ReadReq MSHR hits +system.l2c.UpgradeReq_mshr_hits::cpu0 2 # number of UpgradeReq MSHR hits +system.l2c.UpgradeReq_mshr_hits::cpu1 1 # number of UpgradeReq MSHR hits system.l2c.UpgradeReq_mshr_hits::cpu2 1 # number of UpgradeReq MSHR hits system.l2c.UpgradeReq_mshr_hits::cpu3 1 # number of UpgradeReq MSHR hits system.l2c.UpgradeReq_mshr_hits::cpu4 1 # number of UpgradeReq MSHR hits -system.l2c.UpgradeReq_mshr_hits::cpu5 2 # number of UpgradeReq MSHR hits -system.l2c.UpgradeReq_mshr_hits::total 9 # number of UpgradeReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu0 13 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu1 8 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu2 13 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu3 15 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu4 15 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu5 9 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu6 4 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu7 12 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::total 89 # number of ReadExReq MSHR hits -system.l2c.demand_mshr_hits::cpu0 35 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1 31 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu2 35 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu3 39 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu4 28 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu5 24 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu6 23 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu7 29 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::total 244 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits::cpu0 35 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1 31 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu2 35 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu3 39 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu4 28 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu5 24 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu6 23 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu7 29 # number of overall MSHR hits -system.l2c.overall_mshr_hits::total 244 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses::cpu0 812 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1 809 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu2 800 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu3 756 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu4 777 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu5 779 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu6 819 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu7 719 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 6271 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0 1913 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1 1872 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu2 1921 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu3 2011 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu4 1998 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu5 1916 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu6 1887 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu7 1932 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 15450 # number of UpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0 4381 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1 4300 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu2 4303 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu3 4339 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu4 4277 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu5 4283 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu6 4229 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu7 4316 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 34428 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu0 5193 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1 5109 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2 5103 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu3 5095 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu4 5054 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu5 5062 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu6 5048 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu7 5035 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 40699 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0 5193 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1 5109 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2 5103 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu3 5095 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu4 5054 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu5 5062 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu6 5048 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu7 5035 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 40699 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu0 32483716 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1 32363556 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2 32004501 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu3 30243000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu4 31083178 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu5 31162243 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu6 32763319 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu7 28723011 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 250826524 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0 76520708 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1 74880632 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu2 76840756 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu3 80440711 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu4 79880909 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu5 76600687 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu6 75440727 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu7 77280682 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 617885812 # number of UpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0 175203645 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1 171923291 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu2 172082750 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu3 173484044 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu4 171083248 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu5 171323717 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu6 169163499 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu7 172603062 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 1376867256 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0 207687361 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1 204286847 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2 204087251 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu3 203727044 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu4 202166426 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu5 202485960 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu6 201926818 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu7 201326073 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 1627693780 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0 207687361 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1 204286847 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2 204087251 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu3 203727044 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu4 202166426 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu5 202485960 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu6 201926818 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu7 201326073 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 1627693780 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0 393605068 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1 397164440 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu2 396084825 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu3 395564887 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu4 396845191 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu5 392884701 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu6 399924937 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu7 397605829 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 3169679878 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0 212842079 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1 215082041 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu2 209602015 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu3 213002165 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu4 213521784 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu5 214681989 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu6 217761849 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu7 216562185 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 1713056107 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0 606447147 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1 612246481 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu2 605686840 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu3 608567052 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu4 610366975 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu5 607566690 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu6 617686786 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu7 614168014 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 4882735985 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0 0.070781 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1 0.070317 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2 0.068417 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu3 0.066357 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu4 0.067308 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu5 0.066309 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu6 0.070066 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu7 0.061849 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.067671 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0 0.852876 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1 0.841348 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu2 0.841805 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu3 0.851397 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu4 0.857143 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu5 0.848914 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu6 0.852689 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu7 0.844037 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.848808 # mshr miss rate for UpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0 0.687324 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1 0.694557 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu2 0.689583 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu3 0.682555 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu4 0.682246 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu5 0.689472 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu6 0.680451 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu7 0.693445 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.687433 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0 0.290990 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1 0.288709 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2 0.284559 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu3 0.287042 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu4 0.283725 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu5 0.281849 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu6 0.281948 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu7 0.282089 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.285105 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0 0.290990 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1 0.288709 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2 0.284559 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu3 0.287042 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu4 0.283725 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu5 0.281849 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu6 0.281948 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu7 0.282089 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.285105 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0 40004.576355 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1 40004.395550 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2 40005.626250 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu3 40003.968254 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu4 40004.090090 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu5 40002.879332 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu6 40004.052503 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu7 39948.554937 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 39997.851060 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0 40000.370099 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1 40000.337607 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2 40000.393545 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3 40000.353555 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu4 39980.434935 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu5 39979.481733 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu6 39979.187599 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu7 40000.353002 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 39992.609191 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0 39991.701666 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1 39982.160698 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2 39991.343249 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3 39982.494584 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu4 40000.759411 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu5 40000.867850 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu6 40000.827382 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu7 39991.441613 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 39992.658766 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0 39993.714808 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1 39985.681542 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2 39993.582403 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3 39985.680864 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu4 40001.271468 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu5 40001.177400 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu6 40001.350634 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu7 39985.317378 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 39993.458807 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0 39993.714808 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1 39985.681542 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2 39993.582403 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3 39985.680864 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu4 40001.271468 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu5 40001.177400 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu6 40001.350634 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu7 39985.317378 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 39993.458807 # average overall mshr miss latency +system.l2c.UpgradeReq_mshr_hits::cpu5 1 # number of UpgradeReq MSHR hits +system.l2c.UpgradeReq_mshr_hits::cpu6 1 # number of UpgradeReq MSHR hits +system.l2c.UpgradeReq_mshr_hits::cpu7 4 # number of UpgradeReq MSHR hits +system.l2c.UpgradeReq_mshr_hits::total 12 # number of UpgradeReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu0 6 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu1 13 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu2 9 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu3 9 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu4 12 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu5 11 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu6 10 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu7 15 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::total 85 # number of ReadExReq MSHR hits +system.l2c.demand_mshr_hits::cpu0 24 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1 23 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu2 33 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu3 32 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu4 34 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu5 30 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu6 27 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu7 39 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::total 242 # number of demand (read+write) MSHR hits +system.l2c.overall_mshr_hits::cpu0 24 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu1 23 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu2 33 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu3 32 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu4 34 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu5 30 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu6 27 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu7 39 # number of overall MSHR hits +system.l2c.overall_mshr_hits::total 242 # number of overall MSHR hits +system.l2c.ReadReq_mshr_misses::cpu0 714 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1 736 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu2 763 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu3 713 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu4 757 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu5 749 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu6 785 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu7 732 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 5949 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0 1952 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1 1933 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu2 2006 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu3 1960 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu4 1920 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu5 2007 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu6 1916 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu7 1894 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 15588 # number of UpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0 4342 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1 4376 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu2 4248 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu3 4311 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu4 4338 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu5 4326 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu6 4224 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu7 4275 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 34440 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu0 5056 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1 5112 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2 5011 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu3 5024 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu4 5095 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu5 5075 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu6 5009 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu7 5007 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 40389 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0 5056 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1 5112 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2 5011 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu3 5024 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu4 5095 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu5 5075 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu6 5009 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu7 5007 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 40389 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu0 28564754 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1 29444935 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2 30526423 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu3 28524830 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu4 30284517 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu5 29963728 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu6 31404851 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu7 29284664 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 237998702 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0 78081132 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1 77281042 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu2 80241204 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu3 78401138 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu4 76801198 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu5 80241160 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu6 76640992 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu7 75761030 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 623448896 # number of UpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0 173685720 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1 175005460 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu2 169924253 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu3 172445652 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu4 173444745 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu5 173045540 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu6 168925276 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu7 170965174 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 1377441820 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0 202250474 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1 204450395 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2 200450676 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu3 200970482 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu4 203729262 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu5 203009268 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu6 200330127 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu7 200249838 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 1615440522 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0 202250474 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1 204450395 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2 200450676 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu3 200970482 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu4 203729262 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu5 203009268 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu6 200330127 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu7 200249838 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 1615440522 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0 400927744 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1 396406972 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu2 396807484 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu3 398767759 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu4 400808423 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu5 395927220 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu6 398767355 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu7 395367613 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 3183780570 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0 211603917 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1 215684252 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu2 216163665 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu3 212923402 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu4 213723846 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu5 215924115 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu6 217803639 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu7 216444289 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 1720271125 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0 612531661 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1 612091224 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu2 612971149 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu3 611691161 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu4 614532269 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu5 611851335 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu6 616570994 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu7 611811902 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 4904051695 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0 0.062260 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1 0.064789 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2 0.067018 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu3 0.062588 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu4 0.066299 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu5 0.066460 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu6 0.067754 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu7 0.063520 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.065085 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0 0.842105 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1 0.853045 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu2 0.855802 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu3 0.850694 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu4 0.839528 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu5 0.843277 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu6 0.841828 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu7 0.853922 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.847496 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0 0.692614 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1 0.706832 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu2 0.698340 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu3 0.691087 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu4 0.695861 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu5 0.689732 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu6 0.690535 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu7 0.696594 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.695182 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0 0.285054 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1 0.291265 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2 0.286867 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3 0.284969 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu4 0.288636 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu5 0.289306 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu6 0.282946 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu7 0.283506 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.286561 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0 0.285054 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1 0.291265 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2 0.286867 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3 0.284969 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu4 0.288636 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu5 0.289306 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu6 0.282946 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu7 0.283506 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.286561 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0 40006.658263 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1 40006.705163 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2 40008.418087 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu3 40006.774194 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu4 40005.966975 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu5 40004.977303 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu6 40006.179618 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu7 40006.371585 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 40006.505631 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0 40000.579918 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1 39979.845835 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2 40000.600199 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3 40000.580612 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu4 40000.623958 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu5 39980.647733 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu6 40000.517745 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu7 40000.543823 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 39995.438542 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0 40001.317365 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1 39992.106947 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2 40001.001177 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3 40001.311065 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu4 39982.652144 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu5 40001.280629 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu6 39991.779356 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu7 39991.853567 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 39995.407085 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0 40002.071598 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1 39994.208725 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2 40002.130513 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3 40002.086385 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu4 39986.116192 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu5 40001.826207 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu6 39994.036135 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu7 39993.976034 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 39997.041818 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0 40002.071598 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1 39994.208725 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2 40002.130513 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3 40002.086385 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu4 39986.116192 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu5 40001.826207 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu6 39994.036135 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu7 39993.976034 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 39997.041818 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0 inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1 inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2 inf # average ReadReq mshr uncacheable latency @@ -660,114 +663,114 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu6 inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu7 inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.num_reads 98637 # number of read accesses completed -system.cpu0.num_writes 53345 # number of write accesses completed +system.cpu0.num_reads 99016 # number of read accesses completed +system.cpu0.num_writes 53340 # number of write accesses completed system.cpu0.num_copies 0 # number of copy accesses completed -system.cpu0.l1c.replacements 22018 # number of replacements -system.cpu0.l1c.tagsinuse 396.710521 # Cycle average of tags in use -system.cpu0.l1c.total_refs 13223 # Total number of references to valid blocks. -system.cpu0.l1c.sampled_refs 22420 # Sample count of references to valid blocks. -system.cpu0.l1c.avg_refs 0.589786 # Average number of references to valid blocks. +system.cpu0.l1c.replacements 21906 # number of replacements +system.cpu0.l1c.tagsinuse 396.590239 # Cycle average of tags in use +system.cpu0.l1c.total_refs 13140 # Total number of references to valid blocks. +system.cpu0.l1c.sampled_refs 22312 # Sample count of references to valid blocks. +system.cpu0.l1c.avg_refs 0.588921 # Average number of references to valid blocks. system.cpu0.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.l1c.occ_blocks::cpu0 396.710521 # Average occupied blocks per requestor -system.cpu0.l1c.occ_percent::cpu0 0.774825 # Average percentage of cache occupancy -system.cpu0.l1c.occ_percent::total 0.774825 # Average percentage of cache occupancy -system.cpu0.l1c.ReadReq_hits::cpu0 8580 # number of ReadReq hits -system.cpu0.l1c.ReadReq_hits::total 8580 # number of ReadReq hits -system.cpu0.l1c.WriteReq_hits::cpu0 1119 # number of WriteReq hits -system.cpu0.l1c.WriteReq_hits::total 1119 # number of WriteReq hits -system.cpu0.l1c.demand_hits::cpu0 9699 # number of demand (read+write) hits -system.cpu0.l1c.demand_hits::total 9699 # number of demand (read+write) hits -system.cpu0.l1c.overall_hits::cpu0 9699 # number of overall hits -system.cpu0.l1c.overall_hits::total 9699 # number of overall hits -system.cpu0.l1c.ReadReq_misses::cpu0 35932 # number of ReadReq misses -system.cpu0.l1c.ReadReq_misses::total 35932 # number of ReadReq misses -system.cpu0.l1c.WriteReq_misses::cpu0 23215 # number of WriteReq misses -system.cpu0.l1c.WriteReq_misses::total 23215 # number of WriteReq misses -system.cpu0.l1c.demand_misses::cpu0 59147 # number of demand (read+write) misses -system.cpu0.l1c.demand_misses::total 59147 # number of demand (read+write) misses -system.cpu0.l1c.overall_misses::cpu0 59147 # number of overall misses -system.cpu0.l1c.overall_misses::total 59147 # number of overall misses -system.cpu0.l1c.ReadReq_miss_latency::cpu0 928213854 # number of ReadReq miss cycles -system.cpu0.l1c.ReadReq_miss_latency::total 928213854 # number of ReadReq miss cycles -system.cpu0.l1c.WriteReq_miss_latency::cpu0 888665457 # number of WriteReq miss cycles -system.cpu0.l1c.WriteReq_miss_latency::total 888665457 # number of WriteReq miss cycles -system.cpu0.l1c.demand_miss_latency::cpu0 1816879311 # number of demand (read+write) miss cycles -system.cpu0.l1c.demand_miss_latency::total 1816879311 # number of demand (read+write) miss cycles -system.cpu0.l1c.overall_miss_latency::cpu0 1816879311 # number of overall miss cycles -system.cpu0.l1c.overall_miss_latency::total 1816879311 # number of overall miss cycles -system.cpu0.l1c.ReadReq_accesses::cpu0 44512 # number of ReadReq accesses(hits+misses) -system.cpu0.l1c.ReadReq_accesses::total 44512 # number of ReadReq accesses(hits+misses) -system.cpu0.l1c.WriteReq_accesses::cpu0 24334 # number of WriteReq accesses(hits+misses) -system.cpu0.l1c.WriteReq_accesses::total 24334 # number of WriteReq accesses(hits+misses) -system.cpu0.l1c.demand_accesses::cpu0 68846 # number of demand (read+write) accesses -system.cpu0.l1c.demand_accesses::total 68846 # number of demand (read+write) accesses -system.cpu0.l1c.overall_accesses::cpu0 68846 # number of overall (read+write) accesses -system.cpu0.l1c.overall_accesses::total 68846 # number of overall (read+write) accesses -system.cpu0.l1c.ReadReq_miss_rate::cpu0 0.807243 # miss rate for ReadReq accesses -system.cpu0.l1c.ReadReq_miss_rate::total 0.807243 # miss rate for ReadReq accesses -system.cpu0.l1c.WriteReq_miss_rate::cpu0 0.954015 # miss rate for WriteReq accesses -system.cpu0.l1c.WriteReq_miss_rate::total 0.954015 # miss rate for WriteReq accesses -system.cpu0.l1c.demand_miss_rate::cpu0 0.859120 # miss rate for demand accesses -system.cpu0.l1c.demand_miss_rate::total 0.859120 # miss rate for demand accesses -system.cpu0.l1c.overall_miss_rate::cpu0 0.859120 # miss rate for overall accesses -system.cpu0.l1c.overall_miss_rate::total 0.859120 # miss rate for overall accesses -system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 25832.512913 # average ReadReq miss latency -system.cpu0.l1c.ReadReq_avg_miss_latency::total 25832.512913 # average ReadReq miss latency -system.cpu0.l1c.WriteReq_avg_miss_latency::cpu0 38279.795692 # average WriteReq miss latency -system.cpu0.l1c.WriteReq_avg_miss_latency::total 38279.795692 # average WriteReq miss latency -system.cpu0.l1c.demand_avg_miss_latency::cpu0 30718.029841 # average overall miss latency -system.cpu0.l1c.demand_avg_miss_latency::total 30718.029841 # average overall miss latency -system.cpu0.l1c.overall_avg_miss_latency::cpu0 30718.029841 # average overall miss latency -system.cpu0.l1c.overall_avg_miss_latency::total 30718.029841 # average overall miss latency -system.cpu0.l1c.blocked_cycles::no_mshrs 213519076 # number of cycles access was blocked +system.cpu0.l1c.occ_blocks::cpu0 396.590239 # Average occupied blocks per requestor +system.cpu0.l1c.occ_percent::cpu0 0.774590 # Average percentage of cache occupancy +system.cpu0.l1c.occ_percent::total 0.774590 # Average percentage of cache occupancy +system.cpu0.l1c.ReadReq_hits::cpu0 8561 # number of ReadReq hits +system.cpu0.l1c.ReadReq_hits::total 8561 # number of ReadReq hits +system.cpu0.l1c.WriteReq_hits::cpu0 1051 # number of WriteReq hits +system.cpu0.l1c.WriteReq_hits::total 1051 # number of WriteReq hits +system.cpu0.l1c.demand_hits::cpu0 9612 # number of demand (read+write) hits +system.cpu0.l1c.demand_hits::total 9612 # number of demand (read+write) hits +system.cpu0.l1c.overall_hits::cpu0 9612 # number of overall hits +system.cpu0.l1c.overall_hits::total 9612 # number of overall hits +system.cpu0.l1c.ReadReq_misses::cpu0 35875 # number of ReadReq misses +system.cpu0.l1c.ReadReq_misses::total 35875 # number of ReadReq misses +system.cpu0.l1c.WriteReq_misses::cpu0 23186 # number of WriteReq misses +system.cpu0.l1c.WriteReq_misses::total 23186 # number of WriteReq misses +system.cpu0.l1c.demand_misses::cpu0 59061 # number of demand (read+write) misses +system.cpu0.l1c.demand_misses::total 59061 # number of demand (read+write) misses +system.cpu0.l1c.overall_misses::cpu0 59061 # number of overall misses +system.cpu0.l1c.overall_misses::total 59061 # number of overall misses +system.cpu0.l1c.ReadReq_miss_latency::cpu0 894906998 # number of ReadReq miss cycles +system.cpu0.l1c.ReadReq_miss_latency::total 894906998 # number of ReadReq miss cycles +system.cpu0.l1c.WriteReq_miss_latency::cpu0 820039819 # number of WriteReq miss cycles +system.cpu0.l1c.WriteReq_miss_latency::total 820039819 # number of WriteReq miss cycles +system.cpu0.l1c.demand_miss_latency::cpu0 1714946817 # number of demand (read+write) miss cycles +system.cpu0.l1c.demand_miss_latency::total 1714946817 # number of demand (read+write) miss cycles +system.cpu0.l1c.overall_miss_latency::cpu0 1714946817 # number of overall miss cycles +system.cpu0.l1c.overall_miss_latency::total 1714946817 # number of overall miss cycles +system.cpu0.l1c.ReadReq_accesses::cpu0 44436 # number of ReadReq accesses(hits+misses) +system.cpu0.l1c.ReadReq_accesses::total 44436 # number of ReadReq accesses(hits+misses) +system.cpu0.l1c.WriteReq_accesses::cpu0 24237 # number of WriteReq accesses(hits+misses) +system.cpu0.l1c.WriteReq_accesses::total 24237 # number of WriteReq accesses(hits+misses) +system.cpu0.l1c.demand_accesses::cpu0 68673 # number of demand (read+write) accesses +system.cpu0.l1c.demand_accesses::total 68673 # number of demand (read+write) accesses +system.cpu0.l1c.overall_accesses::cpu0 68673 # number of overall (read+write) accesses +system.cpu0.l1c.overall_accesses::total 68673 # number of overall (read+write) accesses +system.cpu0.l1c.ReadReq_miss_rate::cpu0 0.807341 # miss rate for ReadReq accesses +system.cpu0.l1c.ReadReq_miss_rate::total 0.807341 # miss rate for ReadReq accesses +system.cpu0.l1c.WriteReq_miss_rate::cpu0 0.956637 # miss rate for WriteReq accesses +system.cpu0.l1c.WriteReq_miss_rate::total 0.956637 # miss rate for WriteReq accesses +system.cpu0.l1c.demand_miss_rate::cpu0 0.860032 # miss rate for demand accesses +system.cpu0.l1c.demand_miss_rate::total 0.860032 # miss rate for demand accesses +system.cpu0.l1c.overall_miss_rate::cpu0 0.860032 # miss rate for overall accesses +system.cpu0.l1c.overall_miss_rate::total 0.860032 # miss rate for overall accesses +system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 24945.142801 # average ReadReq miss latency +system.cpu0.l1c.ReadReq_avg_miss_latency::total 24945.142801 # average ReadReq miss latency +system.cpu0.l1c.WriteReq_avg_miss_latency::cpu0 35367.886613 # average WriteReq miss latency +system.cpu0.l1c.WriteReq_avg_miss_latency::total 35367.886613 # average WriteReq miss latency +system.cpu0.l1c.demand_avg_miss_latency::cpu0 29036.874029 # average overall miss latency +system.cpu0.l1c.demand_avg_miss_latency::total 29036.874029 # average overall miss latency +system.cpu0.l1c.overall_avg_miss_latency::cpu0 29036.874029 # average overall miss latency +system.cpu0.l1c.overall_avg_miss_latency::total 29036.874029 # average overall miss latency +system.cpu0.l1c.blocked_cycles::no_mshrs 154642800 # number of cycles access was blocked system.cpu0.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.l1c.blocked::no_mshrs 67191 # number of cycles access was blocked +system.cpu0.l1c.blocked::no_mshrs 53124 # number of cycles access was blocked system.cpu0.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.l1c.avg_blocked_cycles::no_mshrs 3177.792800 # average number of cycles each access was blocked +system.cpu0.l1c.avg_blocked_cycles::no_mshrs 2910.978089 # average number of cycles each access was blocked system.cpu0.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.l1c.fast_writes 0 # number of fast writes performed system.cpu0.l1c.cache_copies 0 # number of cache copies performed -system.cpu0.l1c.writebacks::writebacks 9668 # number of writebacks -system.cpu0.l1c.writebacks::total 9668 # number of writebacks -system.cpu0.l1c.ReadReq_mshr_misses::cpu0 35932 # number of ReadReq MSHR misses -system.cpu0.l1c.ReadReq_mshr_misses::total 35932 # number of ReadReq MSHR misses -system.cpu0.l1c.WriteReq_mshr_misses::cpu0 23215 # number of WriteReq MSHR misses -system.cpu0.l1c.WriteReq_mshr_misses::total 23215 # number of WriteReq MSHR misses -system.cpu0.l1c.demand_mshr_misses::cpu0 59147 # number of demand (read+write) MSHR misses -system.cpu0.l1c.demand_mshr_misses::total 59147 # number of demand (read+write) MSHR misses -system.cpu0.l1c.overall_mshr_misses::cpu0 59147 # number of overall MSHR misses -system.cpu0.l1c.overall_mshr_misses::total 59147 # number of overall MSHR misses -system.cpu0.l1c.ReadReq_mshr_miss_latency::cpu0 892144080 # number of ReadReq MSHR miss cycles -system.cpu0.l1c.ReadReq_mshr_miss_latency::total 892144080 # number of ReadReq MSHR miss cycles -system.cpu0.l1c.WriteReq_mshr_miss_latency::cpu0 865359572 # number of WriteReq MSHR miss cycles -system.cpu0.l1c.WriteReq_mshr_miss_latency::total 865359572 # number of WriteReq MSHR miss cycles -system.cpu0.l1c.demand_mshr_miss_latency::cpu0 1757503652 # number of demand (read+write) MSHR miss cycles -system.cpu0.l1c.demand_mshr_miss_latency::total 1757503652 # number of demand (read+write) MSHR miss cycles -system.cpu0.l1c.overall_mshr_miss_latency::cpu0 1757503652 # number of overall MSHR miss cycles -system.cpu0.l1c.overall_mshr_miss_latency::total 1757503652 # number of overall MSHR miss cycles -system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::cpu0 897451639 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::total 897451639 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::cpu0 561857596 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::total 561857596 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l1c.overall_mshr_uncacheable_latency::cpu0 1459309235 # number of overall MSHR uncacheable cycles -system.cpu0.l1c.overall_mshr_uncacheable_latency::total 1459309235 # number of overall MSHR uncacheable cycles -system.cpu0.l1c.ReadReq_mshr_miss_rate::cpu0 0.807243 # mshr miss rate for ReadReq accesses -system.cpu0.l1c.ReadReq_mshr_miss_rate::total 0.807243 # mshr miss rate for ReadReq accesses -system.cpu0.l1c.WriteReq_mshr_miss_rate::cpu0 0.954015 # mshr miss rate for WriteReq accesses -system.cpu0.l1c.WriteReq_mshr_miss_rate::total 0.954015 # mshr miss rate for WriteReq accesses -system.cpu0.l1c.demand_mshr_miss_rate::cpu0 0.859120 # mshr miss rate for demand accesses -system.cpu0.l1c.demand_mshr_miss_rate::total 0.859120 # mshr miss rate for demand accesses -system.cpu0.l1c.overall_mshr_miss_rate::cpu0 0.859120 # mshr miss rate for overall accesses -system.cpu0.l1c.overall_mshr_miss_rate::total 0.859120 # mshr miss rate for overall accesses -system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::cpu0 24828.678615 # average ReadReq mshr miss latency -system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::total 24828.678615 # average ReadReq mshr miss latency -system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::cpu0 37275.880767 # average WriteReq mshr miss latency -system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::total 37275.880767 # average WriteReq mshr miss latency -system.cpu0.l1c.demand_avg_mshr_miss_latency::cpu0 29714.163897 # average overall mshr miss latency -system.cpu0.l1c.demand_avg_mshr_miss_latency::total 29714.163897 # average overall mshr miss latency -system.cpu0.l1c.overall_avg_mshr_miss_latency::cpu0 29714.163897 # average overall mshr miss latency -system.cpu0.l1c.overall_avg_mshr_miss_latency::total 29714.163897 # average overall mshr miss latency +system.cpu0.l1c.writebacks::writebacks 9551 # number of writebacks +system.cpu0.l1c.writebacks::total 9551 # number of writebacks +system.cpu0.l1c.ReadReq_mshr_misses::cpu0 35875 # number of ReadReq MSHR misses +system.cpu0.l1c.ReadReq_mshr_misses::total 35875 # number of ReadReq MSHR misses +system.cpu0.l1c.WriteReq_mshr_misses::cpu0 23186 # number of WriteReq MSHR misses +system.cpu0.l1c.WriteReq_mshr_misses::total 23186 # number of WriteReq MSHR misses +system.cpu0.l1c.demand_mshr_misses::cpu0 59061 # number of demand (read+write) MSHR misses +system.cpu0.l1c.demand_mshr_misses::total 59061 # number of demand (read+write) MSHR misses +system.cpu0.l1c.overall_mshr_misses::cpu0 59061 # number of overall MSHR misses +system.cpu0.l1c.overall_mshr_misses::total 59061 # number of overall MSHR misses +system.cpu0.l1c.ReadReq_mshr_miss_latency::cpu0 858892486 # number of ReadReq MSHR miss cycles +system.cpu0.l1c.ReadReq_mshr_miss_latency::total 858892486 # number of ReadReq MSHR miss cycles +system.cpu0.l1c.WriteReq_mshr_miss_latency::cpu0 796764078 # number of WriteReq MSHR miss cycles +system.cpu0.l1c.WriteReq_mshr_miss_latency::total 796764078 # number of WriteReq MSHR miss cycles +system.cpu0.l1c.demand_mshr_miss_latency::cpu0 1655656564 # number of demand (read+write) MSHR miss cycles +system.cpu0.l1c.demand_mshr_miss_latency::total 1655656564 # number of demand (read+write) MSHR miss cycles +system.cpu0.l1c.overall_mshr_miss_latency::cpu0 1655656564 # number of overall MSHR miss cycles +system.cpu0.l1c.overall_mshr_miss_latency::total 1655656564 # number of overall MSHR miss cycles +system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::cpu0 681029068 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::total 681029068 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::cpu0 670499371 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::total 670499371 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l1c.overall_mshr_uncacheable_latency::cpu0 1351528439 # number of overall MSHR uncacheable cycles +system.cpu0.l1c.overall_mshr_uncacheable_latency::total 1351528439 # number of overall MSHR uncacheable cycles +system.cpu0.l1c.ReadReq_mshr_miss_rate::cpu0 0.807341 # mshr miss rate for ReadReq accesses +system.cpu0.l1c.ReadReq_mshr_miss_rate::total 0.807341 # mshr miss rate for ReadReq accesses +system.cpu0.l1c.WriteReq_mshr_miss_rate::cpu0 0.956637 # mshr miss rate for WriteReq accesses +system.cpu0.l1c.WriteReq_mshr_miss_rate::total 0.956637 # mshr miss rate for WriteReq accesses +system.cpu0.l1c.demand_mshr_miss_rate::cpu0 0.860032 # mshr miss rate for demand accesses +system.cpu0.l1c.demand_mshr_miss_rate::total 0.860032 # mshr miss rate for demand accesses +system.cpu0.l1c.overall_mshr_miss_rate::cpu0 0.860032 # mshr miss rate for overall accesses +system.cpu0.l1c.overall_mshr_miss_rate::total 0.860032 # mshr miss rate for overall accesses +system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::cpu0 23941.253965 # average ReadReq mshr miss latency +system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::total 23941.253965 # average ReadReq mshr miss latency +system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::cpu0 34364.016130 # average WriteReq mshr miss latency +system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::total 34364.016130 # average WriteReq mshr miss latency +system.cpu0.l1c.demand_avg_mshr_miss_latency::cpu0 28032.992398 # average overall mshr miss latency +system.cpu0.l1c.demand_avg_mshr_miss_latency::total 28032.992398 # average overall mshr miss latency +system.cpu0.l1c.overall_avg_mshr_miss_latency::cpu0 28032.992398 # average overall mshr miss latency +system.cpu0.l1c.overall_avg_mshr_miss_latency::total 28032.992398 # average overall mshr miss latency system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu0 inf # average ReadReq mshr uncacheable latency system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu0 inf # average WriteReq mshr uncacheable latency @@ -775,114 +778,114 @@ system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::cpu0 inf # average overall mshr uncacheable latency system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.num_reads 99346 # number of read accesses completed -system.cpu1.num_writes 53405 # number of write accesses completed +system.cpu1.num_reads 99689 # number of read accesses completed +system.cpu1.num_writes 53832 # number of write accesses completed system.cpu1.num_copies 0 # number of copy accesses completed -system.cpu1.l1c.replacements 21836 # number of replacements -system.cpu1.l1c.tagsinuse 395.252412 # Cycle average of tags in use -system.cpu1.l1c.total_refs 13010 # Total number of references to valid blocks. -system.cpu1.l1c.sampled_refs 22258 # Sample count of references to valid blocks. -system.cpu1.l1c.avg_refs 0.584509 # Average number of references to valid blocks. +system.cpu1.l1c.replacements 21971 # number of replacements +system.cpu1.l1c.tagsinuse 397.434568 # Cycle average of tags in use +system.cpu1.l1c.total_refs 13255 # Total number of references to valid blocks. +system.cpu1.l1c.sampled_refs 22377 # Sample count of references to valid blocks. +system.cpu1.l1c.avg_refs 0.592349 # Average number of references to valid blocks. system.cpu1.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.l1c.occ_blocks::cpu1 395.252412 # Average occupied blocks per requestor -system.cpu1.l1c.occ_percent::cpu1 0.771977 # Average percentage of cache occupancy -system.cpu1.l1c.occ_percent::total 0.771977 # Average percentage of cache occupancy -system.cpu1.l1c.ReadReq_hits::cpu1 8468 # number of ReadReq hits -system.cpu1.l1c.ReadReq_hits::total 8468 # number of ReadReq hits -system.cpu1.l1c.WriteReq_hits::cpu1 1045 # number of WriteReq hits -system.cpu1.l1c.WriteReq_hits::total 1045 # number of WriteReq hits -system.cpu1.l1c.demand_hits::cpu1 9513 # number of demand (read+write) hits -system.cpu1.l1c.demand_hits::total 9513 # number of demand (read+write) hits -system.cpu1.l1c.overall_hits::cpu1 9513 # number of overall hits -system.cpu1.l1c.overall_hits::total 9513 # number of overall hits -system.cpu1.l1c.ReadReq_misses::cpu1 36170 # number of ReadReq misses -system.cpu1.l1c.ReadReq_misses::total 36170 # number of ReadReq misses -system.cpu1.l1c.WriteReq_misses::cpu1 22843 # number of WriteReq misses -system.cpu1.l1c.WriteReq_misses::total 22843 # number of WriteReq misses -system.cpu1.l1c.demand_misses::cpu1 59013 # number of demand (read+write) misses -system.cpu1.l1c.demand_misses::total 59013 # number of demand (read+write) misses -system.cpu1.l1c.overall_misses::cpu1 59013 # number of overall misses -system.cpu1.l1c.overall_misses::total 59013 # number of overall misses -system.cpu1.l1c.ReadReq_miss_latency::cpu1 930956991 # number of ReadReq miss cycles -system.cpu1.l1c.ReadReq_miss_latency::total 930956991 # number of ReadReq miss cycles -system.cpu1.l1c.WriteReq_miss_latency::cpu1 873445374 # number of WriteReq miss cycles -system.cpu1.l1c.WriteReq_miss_latency::total 873445374 # number of WriteReq miss cycles -system.cpu1.l1c.demand_miss_latency::cpu1 1804402365 # number of demand (read+write) miss cycles -system.cpu1.l1c.demand_miss_latency::total 1804402365 # number of demand (read+write) miss cycles -system.cpu1.l1c.overall_miss_latency::cpu1 1804402365 # number of overall miss cycles -system.cpu1.l1c.overall_miss_latency::total 1804402365 # number of overall miss cycles -system.cpu1.l1c.ReadReq_accesses::cpu1 44638 # number of ReadReq accesses(hits+misses) -system.cpu1.l1c.ReadReq_accesses::total 44638 # number of ReadReq accesses(hits+misses) -system.cpu1.l1c.WriteReq_accesses::cpu1 23888 # number of WriteReq accesses(hits+misses) -system.cpu1.l1c.WriteReq_accesses::total 23888 # number of WriteReq accesses(hits+misses) -system.cpu1.l1c.demand_accesses::cpu1 68526 # number of demand (read+write) accesses -system.cpu1.l1c.demand_accesses::total 68526 # number of demand (read+write) accesses -system.cpu1.l1c.overall_accesses::cpu1 68526 # number of overall (read+write) accesses -system.cpu1.l1c.overall_accesses::total 68526 # number of overall (read+write) accesses -system.cpu1.l1c.ReadReq_miss_rate::cpu1 0.810296 # miss rate for ReadReq accesses -system.cpu1.l1c.ReadReq_miss_rate::total 0.810296 # miss rate for ReadReq accesses -system.cpu1.l1c.WriteReq_miss_rate::cpu1 0.956254 # miss rate for WriteReq accesses -system.cpu1.l1c.WriteReq_miss_rate::total 0.956254 # miss rate for WriteReq accesses -system.cpu1.l1c.demand_miss_rate::cpu1 0.861177 # miss rate for demand accesses -system.cpu1.l1c.demand_miss_rate::total 0.861177 # miss rate for demand accesses -system.cpu1.l1c.overall_miss_rate::cpu1 0.861177 # miss rate for overall accesses -system.cpu1.l1c.overall_miss_rate::total 0.861177 # miss rate for overall accesses -system.cpu1.l1c.ReadReq_avg_miss_latency::cpu1 25738.374095 # average ReadReq miss latency -system.cpu1.l1c.ReadReq_avg_miss_latency::total 25738.374095 # average ReadReq miss latency -system.cpu1.l1c.WriteReq_avg_miss_latency::cpu1 38236.894191 # average WriteReq miss latency -system.cpu1.l1c.WriteReq_avg_miss_latency::total 38236.894191 # average WriteReq miss latency -system.cpu1.l1c.demand_avg_miss_latency::cpu1 30576.353770 # average overall miss latency -system.cpu1.l1c.demand_avg_miss_latency::total 30576.353770 # average overall miss latency -system.cpu1.l1c.overall_avg_miss_latency::cpu1 30576.353770 # average overall miss latency -system.cpu1.l1c.overall_avg_miss_latency::total 30576.353770 # average overall miss latency -system.cpu1.l1c.blocked_cycles::no_mshrs 212850460 # number of cycles access was blocked +system.cpu1.l1c.occ_blocks::cpu1 397.434568 # Average occupied blocks per requestor +system.cpu1.l1c.occ_percent::cpu1 0.776239 # Average percentage of cache occupancy +system.cpu1.l1c.occ_percent::total 0.776239 # Average percentage of cache occupancy +system.cpu1.l1c.ReadReq_hits::cpu1 8630 # number of ReadReq hits +system.cpu1.l1c.ReadReq_hits::total 8630 # number of ReadReq hits +system.cpu1.l1c.WriteReq_hits::cpu1 1103 # number of WriteReq hits +system.cpu1.l1c.WriteReq_hits::total 1103 # number of WriteReq hits +system.cpu1.l1c.demand_hits::cpu1 9733 # number of demand (read+write) hits +system.cpu1.l1c.demand_hits::total 9733 # number of demand (read+write) hits +system.cpu1.l1c.overall_hits::cpu1 9733 # number of overall hits +system.cpu1.l1c.overall_hits::total 9733 # number of overall hits +system.cpu1.l1c.ReadReq_misses::cpu1 36139 # number of ReadReq misses +system.cpu1.l1c.ReadReq_misses::total 36139 # number of ReadReq misses +system.cpu1.l1c.WriteReq_misses::cpu1 23155 # number of WriteReq misses +system.cpu1.l1c.WriteReq_misses::total 23155 # number of WriteReq misses +system.cpu1.l1c.demand_misses::cpu1 59294 # number of demand (read+write) misses +system.cpu1.l1c.demand_misses::total 59294 # number of demand (read+write) misses +system.cpu1.l1c.overall_misses::cpu1 59294 # number of overall misses +system.cpu1.l1c.overall_misses::total 59294 # number of overall misses +system.cpu1.l1c.ReadReq_miss_latency::cpu1 902705787 # number of ReadReq miss cycles +system.cpu1.l1c.ReadReq_miss_latency::total 902705787 # number of ReadReq miss cycles +system.cpu1.l1c.WriteReq_miss_latency::cpu1 819450505 # number of WriteReq miss cycles +system.cpu1.l1c.WriteReq_miss_latency::total 819450505 # number of WriteReq miss cycles +system.cpu1.l1c.demand_miss_latency::cpu1 1722156292 # number of demand (read+write) miss cycles +system.cpu1.l1c.demand_miss_latency::total 1722156292 # number of demand (read+write) miss cycles +system.cpu1.l1c.overall_miss_latency::cpu1 1722156292 # number of overall miss cycles +system.cpu1.l1c.overall_miss_latency::total 1722156292 # number of overall miss cycles +system.cpu1.l1c.ReadReq_accesses::cpu1 44769 # number of ReadReq accesses(hits+misses) +system.cpu1.l1c.ReadReq_accesses::total 44769 # number of ReadReq accesses(hits+misses) +system.cpu1.l1c.WriteReq_accesses::cpu1 24258 # number of WriteReq accesses(hits+misses) +system.cpu1.l1c.WriteReq_accesses::total 24258 # number of WriteReq accesses(hits+misses) +system.cpu1.l1c.demand_accesses::cpu1 69027 # number of demand (read+write) accesses +system.cpu1.l1c.demand_accesses::total 69027 # number of demand (read+write) accesses +system.cpu1.l1c.overall_accesses::cpu1 69027 # number of overall (read+write) accesses +system.cpu1.l1c.overall_accesses::total 69027 # number of overall (read+write) accesses +system.cpu1.l1c.ReadReq_miss_rate::cpu1 0.807233 # miss rate for ReadReq accesses +system.cpu1.l1c.ReadReq_miss_rate::total 0.807233 # miss rate for ReadReq accesses +system.cpu1.l1c.WriteReq_miss_rate::cpu1 0.954530 # miss rate for WriteReq accesses +system.cpu1.l1c.WriteReq_miss_rate::total 0.954530 # miss rate for WriteReq accesses +system.cpu1.l1c.demand_miss_rate::cpu1 0.858997 # miss rate for demand accesses +system.cpu1.l1c.demand_miss_rate::total 0.858997 # miss rate for demand accesses +system.cpu1.l1c.overall_miss_rate::cpu1 0.858997 # miss rate for overall accesses +system.cpu1.l1c.overall_miss_rate::total 0.858997 # miss rate for overall accesses +system.cpu1.l1c.ReadReq_avg_miss_latency::cpu1 24978.715155 # average ReadReq miss latency +system.cpu1.l1c.ReadReq_avg_miss_latency::total 24978.715155 # average ReadReq miss latency +system.cpu1.l1c.WriteReq_avg_miss_latency::cpu1 35389.786439 # average WriteReq miss latency +system.cpu1.l1c.WriteReq_avg_miss_latency::total 35389.786439 # average WriteReq miss latency +system.cpu1.l1c.demand_avg_miss_latency::cpu1 29044.360171 # average overall miss latency +system.cpu1.l1c.demand_avg_miss_latency::total 29044.360171 # average overall miss latency +system.cpu1.l1c.overall_avg_miss_latency::cpu1 29044.360171 # average overall miss latency +system.cpu1.l1c.overall_avg_miss_latency::total 29044.360171 # average overall miss latency +system.cpu1.l1c.blocked_cycles::no_mshrs 155390130 # number of cycles access was blocked system.cpu1.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.l1c.blocked::no_mshrs 67062 # number of cycles access was blocked +system.cpu1.l1c.blocked::no_mshrs 53247 # number of cycles access was blocked system.cpu1.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.l1c.avg_blocked_cycles::no_mshrs 3173.935463 # average number of cycles each access was blocked +system.cpu1.l1c.avg_blocked_cycles::no_mshrs 2918.288918 # average number of cycles each access was blocked system.cpu1.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.l1c.fast_writes 0 # number of fast writes performed system.cpu1.l1c.cache_copies 0 # number of cache copies performed -system.cpu1.l1c.writebacks::writebacks 9414 # number of writebacks -system.cpu1.l1c.writebacks::total 9414 # number of writebacks -system.cpu1.l1c.ReadReq_mshr_misses::cpu1 36170 # number of ReadReq MSHR misses -system.cpu1.l1c.ReadReq_mshr_misses::total 36170 # number of ReadReq MSHR misses -system.cpu1.l1c.WriteReq_mshr_misses::cpu1 22843 # number of WriteReq MSHR misses -system.cpu1.l1c.WriteReq_mshr_misses::total 22843 # number of WriteReq MSHR misses -system.cpu1.l1c.demand_mshr_misses::cpu1 59013 # number of demand (read+write) MSHR misses -system.cpu1.l1c.demand_mshr_misses::total 59013 # number of demand (read+write) MSHR misses -system.cpu1.l1c.overall_mshr_misses::cpu1 59013 # number of overall MSHR misses -system.cpu1.l1c.overall_mshr_misses::total 59013 # number of overall MSHR misses -system.cpu1.l1c.ReadReq_mshr_miss_latency::cpu1 894646237 # number of ReadReq MSHR miss cycles -system.cpu1.l1c.ReadReq_mshr_miss_latency::total 894646237 # number of ReadReq MSHR miss cycles -system.cpu1.l1c.WriteReq_mshr_miss_latency::cpu1 850514976 # number of WriteReq MSHR miss cycles -system.cpu1.l1c.WriteReq_mshr_miss_latency::total 850514976 # number of WriteReq MSHR miss cycles -system.cpu1.l1c.demand_mshr_miss_latency::cpu1 1745161213 # number of demand (read+write) MSHR miss cycles -system.cpu1.l1c.demand_mshr_miss_latency::total 1745161213 # number of demand (read+write) MSHR miss cycles -system.cpu1.l1c.overall_mshr_miss_latency::cpu1 1745161213 # number of overall MSHR miss cycles -system.cpu1.l1c.overall_mshr_miss_latency::total 1745161213 # number of overall MSHR miss cycles -system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::cpu1 906808922 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::total 906808922 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::cpu1 573615954 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::total 573615954 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l1c.overall_mshr_uncacheable_latency::cpu1 1480424876 # number of overall MSHR uncacheable cycles -system.cpu1.l1c.overall_mshr_uncacheable_latency::total 1480424876 # number of overall MSHR uncacheable cycles -system.cpu1.l1c.ReadReq_mshr_miss_rate::cpu1 0.810296 # mshr miss rate for ReadReq accesses -system.cpu1.l1c.ReadReq_mshr_miss_rate::total 0.810296 # mshr miss rate for ReadReq accesses -system.cpu1.l1c.WriteReq_mshr_miss_rate::cpu1 0.956254 # mshr miss rate for WriteReq accesses -system.cpu1.l1c.WriteReq_mshr_miss_rate::total 0.956254 # mshr miss rate for WriteReq accesses -system.cpu1.l1c.demand_mshr_miss_rate::cpu1 0.861177 # mshr miss rate for demand accesses -system.cpu1.l1c.demand_mshr_miss_rate::total 0.861177 # mshr miss rate for demand accesses -system.cpu1.l1c.overall_mshr_miss_rate::cpu1 0.861177 # mshr miss rate for overall accesses -system.cpu1.l1c.overall_mshr_miss_rate::total 0.861177 # mshr miss rate for overall accesses -system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 24734.482638 # average ReadReq mshr miss latency -system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::total 24734.482638 # average ReadReq mshr miss latency -system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 37233.068161 # average WriteReq mshr miss latency -system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::total 37233.068161 # average WriteReq mshr miss latency -system.cpu1.l1c.demand_avg_mshr_miss_latency::cpu1 29572.487638 # average overall mshr miss latency -system.cpu1.l1c.demand_avg_mshr_miss_latency::total 29572.487638 # average overall mshr miss latency -system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 29572.487638 # average overall mshr miss latency -system.cpu1.l1c.overall_avg_mshr_miss_latency::total 29572.487638 # average overall mshr miss latency +system.cpu1.l1c.writebacks::writebacks 9603 # number of writebacks +system.cpu1.l1c.writebacks::total 9603 # number of writebacks +system.cpu1.l1c.ReadReq_mshr_misses::cpu1 36139 # number of ReadReq MSHR misses +system.cpu1.l1c.ReadReq_mshr_misses::total 36139 # number of ReadReq MSHR misses +system.cpu1.l1c.WriteReq_mshr_misses::cpu1 23155 # number of WriteReq MSHR misses +system.cpu1.l1c.WriteReq_mshr_misses::total 23155 # number of WriteReq MSHR misses +system.cpu1.l1c.demand_mshr_misses::cpu1 59294 # number of demand (read+write) MSHR misses +system.cpu1.l1c.demand_mshr_misses::total 59294 # number of demand (read+write) MSHR misses +system.cpu1.l1c.overall_mshr_misses::cpu1 59294 # number of overall MSHR misses +system.cpu1.l1c.overall_mshr_misses::total 59294 # number of overall MSHR misses +system.cpu1.l1c.ReadReq_mshr_miss_latency::cpu1 866427236 # number of ReadReq MSHR miss cycles +system.cpu1.l1c.ReadReq_mshr_miss_latency::total 866427236 # number of ReadReq MSHR miss cycles +system.cpu1.l1c.WriteReq_mshr_miss_latency::cpu1 796207895 # number of WriteReq MSHR miss cycles +system.cpu1.l1c.WriteReq_mshr_miss_latency::total 796207895 # number of WriteReq MSHR miss cycles +system.cpu1.l1c.demand_mshr_miss_latency::cpu1 1662635131 # number of demand (read+write) MSHR miss cycles +system.cpu1.l1c.demand_mshr_miss_latency::total 1662635131 # number of demand (read+write) MSHR miss cycles +system.cpu1.l1c.overall_mshr_miss_latency::cpu1 1662635131 # number of overall MSHR miss cycles +system.cpu1.l1c.overall_mshr_miss_latency::total 1662635131 # number of overall MSHR miss cycles +system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::cpu1 674093801 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::total 674093801 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::cpu1 675943433 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::total 675943433 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l1c.overall_mshr_uncacheable_latency::cpu1 1350037234 # number of overall MSHR uncacheable cycles +system.cpu1.l1c.overall_mshr_uncacheable_latency::total 1350037234 # number of overall MSHR uncacheable cycles +system.cpu1.l1c.ReadReq_mshr_miss_rate::cpu1 0.807233 # mshr miss rate for ReadReq accesses +system.cpu1.l1c.ReadReq_mshr_miss_rate::total 0.807233 # mshr miss rate for ReadReq accesses +system.cpu1.l1c.WriteReq_mshr_miss_rate::cpu1 0.954530 # mshr miss rate for WriteReq accesses +system.cpu1.l1c.WriteReq_mshr_miss_rate::total 0.954530 # mshr miss rate for WriteReq accesses +system.cpu1.l1c.demand_mshr_miss_rate::cpu1 0.858997 # mshr miss rate for demand accesses +system.cpu1.l1c.demand_mshr_miss_rate::total 0.858997 # mshr miss rate for demand accesses +system.cpu1.l1c.overall_mshr_miss_rate::cpu1 0.858997 # mshr miss rate for overall accesses +system.cpu1.l1c.overall_mshr_miss_rate::total 0.858997 # mshr miss rate for overall accesses +system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 23974.853648 # average ReadReq mshr miss latency +system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::total 23974.853648 # average ReadReq mshr miss latency +system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 34386.002807 # average WriteReq mshr miss latency +system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::total 34386.002807 # average WriteReq mshr miss latency +system.cpu1.l1c.demand_avg_mshr_miss_latency::cpu1 28040.529075 # average overall mshr miss latency +system.cpu1.l1c.demand_avg_mshr_miss_latency::total 28040.529075 # average overall mshr miss latency +system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 28040.529075 # average overall mshr miss latency +system.cpu1.l1c.overall_avg_mshr_miss_latency::total 28040.529075 # average overall mshr miss latency system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu1 inf # average ReadReq mshr uncacheable latency system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu1 inf # average WriteReq mshr uncacheable latency @@ -890,114 +893,114 @@ system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::cpu1 inf # average overall mshr uncacheable latency system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.num_reads 99179 # number of read accesses completed -system.cpu2.num_writes 53408 # number of write accesses completed +system.cpu2.num_reads 99864 # number of read accesses completed +system.cpu2.num_writes 53679 # number of write accesses completed system.cpu2.num_copies 0 # number of copy accesses completed -system.cpu2.l1c.replacements 21970 # number of replacements -system.cpu2.l1c.tagsinuse 396.422513 # Cycle average of tags in use -system.cpu2.l1c.total_refs 13458 # Total number of references to valid blocks. -system.cpu2.l1c.sampled_refs 22394 # Sample count of references to valid blocks. -system.cpu2.l1c.avg_refs 0.600965 # Average number of references to valid blocks. +system.cpu2.l1c.replacements 22117 # number of replacements +system.cpu2.l1c.tagsinuse 397.846327 # Cycle average of tags in use +system.cpu2.l1c.total_refs 13470 # Total number of references to valid blocks. +system.cpu2.l1c.sampled_refs 22518 # Sample count of references to valid blocks. +system.cpu2.l1c.avg_refs 0.598188 # Average number of references to valid blocks. system.cpu2.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.l1c.occ_blocks::cpu2 396.422513 # Average occupied blocks per requestor -system.cpu2.l1c.occ_percent::cpu2 0.774263 # Average percentage of cache occupancy -system.cpu2.l1c.occ_percent::total 0.774263 # Average percentage of cache occupancy -system.cpu2.l1c.ReadReq_hits::cpu2 8875 # number of ReadReq hits -system.cpu2.l1c.ReadReq_hits::total 8875 # number of ReadReq hits -system.cpu2.l1c.WriteReq_hits::cpu2 1083 # number of WriteReq hits -system.cpu2.l1c.WriteReq_hits::total 1083 # number of WriteReq hits -system.cpu2.l1c.demand_hits::cpu2 9958 # number of demand (read+write) hits -system.cpu2.l1c.demand_hits::total 9958 # number of demand (read+write) hits -system.cpu2.l1c.overall_hits::cpu2 9958 # number of overall hits -system.cpu2.l1c.overall_hits::total 9958 # number of overall hits -system.cpu2.l1c.ReadReq_misses::cpu2 35921 # number of ReadReq misses -system.cpu2.l1c.ReadReq_misses::total 35921 # number of ReadReq misses -system.cpu2.l1c.WriteReq_misses::cpu2 23014 # number of WriteReq misses -system.cpu2.l1c.WriteReq_misses::total 23014 # number of WriteReq misses -system.cpu2.l1c.demand_misses::cpu2 58935 # number of demand (read+write) misses -system.cpu2.l1c.demand_misses::total 58935 # number of demand (read+write) misses -system.cpu2.l1c.overall_misses::cpu2 58935 # number of overall misses -system.cpu2.l1c.overall_misses::total 58935 # number of overall misses -system.cpu2.l1c.ReadReq_miss_latency::cpu2 936514854 # number of ReadReq miss cycles -system.cpu2.l1c.ReadReq_miss_latency::total 936514854 # number of ReadReq miss cycles -system.cpu2.l1c.WriteReq_miss_latency::cpu2 882688372 # number of WriteReq miss cycles -system.cpu2.l1c.WriteReq_miss_latency::total 882688372 # number of WriteReq miss cycles -system.cpu2.l1c.demand_miss_latency::cpu2 1819203226 # number of demand (read+write) miss cycles -system.cpu2.l1c.demand_miss_latency::total 1819203226 # number of demand (read+write) miss cycles -system.cpu2.l1c.overall_miss_latency::cpu2 1819203226 # number of overall miss cycles -system.cpu2.l1c.overall_miss_latency::total 1819203226 # number of overall miss cycles -system.cpu2.l1c.ReadReq_accesses::cpu2 44796 # number of ReadReq accesses(hits+misses) -system.cpu2.l1c.ReadReq_accesses::total 44796 # number of ReadReq accesses(hits+misses) -system.cpu2.l1c.WriteReq_accesses::cpu2 24097 # number of WriteReq accesses(hits+misses) -system.cpu2.l1c.WriteReq_accesses::total 24097 # number of WriteReq accesses(hits+misses) -system.cpu2.l1c.demand_accesses::cpu2 68893 # number of demand (read+write) accesses -system.cpu2.l1c.demand_accesses::total 68893 # number of demand (read+write) accesses -system.cpu2.l1c.overall_accesses::cpu2 68893 # number of overall (read+write) accesses -system.cpu2.l1c.overall_accesses::total 68893 # number of overall (read+write) accesses -system.cpu2.l1c.ReadReq_miss_rate::cpu2 0.801880 # miss rate for ReadReq accesses -system.cpu2.l1c.ReadReq_miss_rate::total 0.801880 # miss rate for ReadReq accesses -system.cpu2.l1c.WriteReq_miss_rate::cpu2 0.955057 # miss rate for WriteReq accesses -system.cpu2.l1c.WriteReq_miss_rate::total 0.955057 # miss rate for WriteReq accesses -system.cpu2.l1c.demand_miss_rate::cpu2 0.855457 # miss rate for demand accesses -system.cpu2.l1c.demand_miss_rate::total 0.855457 # miss rate for demand accesses -system.cpu2.l1c.overall_miss_rate::cpu2 0.855457 # miss rate for overall accesses -system.cpu2.l1c.overall_miss_rate::total 0.855457 # miss rate for overall accesses -system.cpu2.l1c.ReadReq_avg_miss_latency::cpu2 26071.513989 # average ReadReq miss latency -system.cpu2.l1c.ReadReq_avg_miss_latency::total 26071.513989 # average ReadReq miss latency -system.cpu2.l1c.WriteReq_avg_miss_latency::cpu2 38354.409142 # average WriteReq miss latency -system.cpu2.l1c.WriteReq_avg_miss_latency::total 38354.409142 # average WriteReq miss latency -system.cpu2.l1c.demand_avg_miss_latency::cpu2 30867.960058 # average overall miss latency -system.cpu2.l1c.demand_avg_miss_latency::total 30867.960058 # average overall miss latency -system.cpu2.l1c.overall_avg_miss_latency::cpu2 30867.960058 # average overall miss latency -system.cpu2.l1c.overall_avg_miss_latency::total 30867.960058 # average overall miss latency -system.cpu2.l1c.blocked_cycles::no_mshrs 215347558 # number of cycles access was blocked +system.cpu2.l1c.occ_blocks::cpu2 397.846327 # Average occupied blocks per requestor +system.cpu2.l1c.occ_percent::cpu2 0.777044 # Average percentage of cache occupancy +system.cpu2.l1c.occ_percent::total 0.777044 # Average percentage of cache occupancy +system.cpu2.l1c.ReadReq_hits::cpu2 8720 # number of ReadReq hits +system.cpu2.l1c.ReadReq_hits::total 8720 # number of ReadReq hits +system.cpu2.l1c.WriteReq_hits::cpu2 1090 # number of WriteReq hits +system.cpu2.l1c.WriteReq_hits::total 1090 # number of WriteReq hits +system.cpu2.l1c.demand_hits::cpu2 9810 # number of demand (read+write) hits +system.cpu2.l1c.demand_hits::total 9810 # number of demand (read+write) hits +system.cpu2.l1c.overall_hits::cpu2 9810 # number of overall hits +system.cpu2.l1c.overall_hits::total 9810 # number of overall hits +system.cpu2.l1c.ReadReq_misses::cpu2 36026 # number of ReadReq misses +system.cpu2.l1c.ReadReq_misses::total 36026 # number of ReadReq misses +system.cpu2.l1c.WriteReq_misses::cpu2 23186 # number of WriteReq misses +system.cpu2.l1c.WriteReq_misses::total 23186 # number of WriteReq misses +system.cpu2.l1c.demand_misses::cpu2 59212 # number of demand (read+write) misses +system.cpu2.l1c.demand_misses::total 59212 # number of demand (read+write) misses +system.cpu2.l1c.overall_misses::cpu2 59212 # number of overall misses +system.cpu2.l1c.overall_misses::total 59212 # number of overall misses +system.cpu2.l1c.ReadReq_miss_latency::cpu2 899117648 # number of ReadReq miss cycles +system.cpu2.l1c.ReadReq_miss_latency::total 899117648 # number of ReadReq miss cycles +system.cpu2.l1c.WriteReq_miss_latency::cpu2 813653609 # number of WriteReq miss cycles +system.cpu2.l1c.WriteReq_miss_latency::total 813653609 # number of WriteReq miss cycles +system.cpu2.l1c.demand_miss_latency::cpu2 1712771257 # number of demand (read+write) miss cycles +system.cpu2.l1c.demand_miss_latency::total 1712771257 # number of demand (read+write) miss cycles +system.cpu2.l1c.overall_miss_latency::cpu2 1712771257 # number of overall miss cycles +system.cpu2.l1c.overall_miss_latency::total 1712771257 # number of overall miss cycles +system.cpu2.l1c.ReadReq_accesses::cpu2 44746 # number of ReadReq accesses(hits+misses) +system.cpu2.l1c.ReadReq_accesses::total 44746 # number of ReadReq accesses(hits+misses) +system.cpu2.l1c.WriteReq_accesses::cpu2 24276 # number of WriteReq accesses(hits+misses) +system.cpu2.l1c.WriteReq_accesses::total 24276 # number of WriteReq accesses(hits+misses) +system.cpu2.l1c.demand_accesses::cpu2 69022 # number of demand (read+write) accesses +system.cpu2.l1c.demand_accesses::total 69022 # number of demand (read+write) accesses +system.cpu2.l1c.overall_accesses::cpu2 69022 # number of overall (read+write) accesses +system.cpu2.l1c.overall_accesses::total 69022 # number of overall (read+write) accesses +system.cpu2.l1c.ReadReq_miss_rate::cpu2 0.805122 # miss rate for ReadReq accesses +system.cpu2.l1c.ReadReq_miss_rate::total 0.805122 # miss rate for ReadReq accesses +system.cpu2.l1c.WriteReq_miss_rate::cpu2 0.955100 # miss rate for WriteReq accesses +system.cpu2.l1c.WriteReq_miss_rate::total 0.955100 # miss rate for WriteReq accesses +system.cpu2.l1c.demand_miss_rate::cpu2 0.857871 # miss rate for demand accesses +system.cpu2.l1c.demand_miss_rate::total 0.857871 # miss rate for demand accesses +system.cpu2.l1c.overall_miss_rate::cpu2 0.857871 # miss rate for overall accesses +system.cpu2.l1c.overall_miss_rate::total 0.857871 # miss rate for overall accesses +system.cpu2.l1c.ReadReq_avg_miss_latency::cpu2 24957.465386 # average ReadReq miss latency +system.cpu2.l1c.ReadReq_avg_miss_latency::total 24957.465386 # average ReadReq miss latency +system.cpu2.l1c.WriteReq_avg_miss_latency::cpu2 35092.452730 # average WriteReq miss latency +system.cpu2.l1c.WriteReq_avg_miss_latency::total 35092.452730 # average WriteReq miss latency +system.cpu2.l1c.demand_avg_miss_latency::cpu2 28926.083513 # average overall miss latency +system.cpu2.l1c.demand_avg_miss_latency::total 28926.083513 # average overall miss latency +system.cpu2.l1c.overall_avg_miss_latency::cpu2 28926.083513 # average overall miss latency +system.cpu2.l1c.overall_avg_miss_latency::total 28926.083513 # average overall miss latency +system.cpu2.l1c.blocked_cycles::no_mshrs 153072251 # number of cycles access was blocked system.cpu2.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu2.l1c.blocked::no_mshrs 67274 # number of cycles access was blocked +system.cpu2.l1c.blocked::no_mshrs 52648 # number of cycles access was blocked system.cpu2.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu2.l1c.avg_blocked_cycles::no_mshrs 3201.051788 # average number of cycles each access was blocked +system.cpu2.l1c.avg_blocked_cycles::no_mshrs 2907.465640 # average number of cycles each access was blocked system.cpu2.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu2.l1c.fast_writes 0 # number of fast writes performed system.cpu2.l1c.cache_copies 0 # number of cache copies performed -system.cpu2.l1c.writebacks::writebacks 9572 # number of writebacks -system.cpu2.l1c.writebacks::total 9572 # number of writebacks -system.cpu2.l1c.ReadReq_mshr_misses::cpu2 35921 # number of ReadReq MSHR misses -system.cpu2.l1c.ReadReq_mshr_misses::total 35921 # number of ReadReq MSHR misses -system.cpu2.l1c.WriteReq_mshr_misses::cpu2 23014 # number of WriteReq MSHR misses -system.cpu2.l1c.WriteReq_mshr_misses::total 23014 # number of WriteReq MSHR misses -system.cpu2.l1c.demand_mshr_misses::cpu2 58935 # number of demand (read+write) MSHR misses -system.cpu2.l1c.demand_mshr_misses::total 58935 # number of demand (read+write) MSHR misses -system.cpu2.l1c.overall_mshr_misses::cpu2 58935 # number of overall MSHR misses -system.cpu2.l1c.overall_mshr_misses::total 58935 # number of overall MSHR misses -system.cpu2.l1c.ReadReq_mshr_miss_latency::cpu2 900454097 # number of ReadReq MSHR miss cycles -system.cpu2.l1c.ReadReq_mshr_miss_latency::total 900454097 # number of ReadReq MSHR miss cycles -system.cpu2.l1c.WriteReq_mshr_miss_latency::cpu2 859588304 # number of WriteReq MSHR miss cycles -system.cpu2.l1c.WriteReq_mshr_miss_latency::total 859588304 # number of WriteReq MSHR miss cycles -system.cpu2.l1c.demand_mshr_miss_latency::cpu2 1760042401 # number of demand (read+write) MSHR miss cycles -system.cpu2.l1c.demand_mshr_miss_latency::total 1760042401 # number of demand (read+write) MSHR miss cycles -system.cpu2.l1c.overall_mshr_miss_latency::cpu2 1760042401 # number of overall MSHR miss cycles -system.cpu2.l1c.overall_mshr_miss_latency::total 1760042401 # number of overall MSHR miss cycles -system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::cpu2 903394412 # number of ReadReq MSHR uncacheable cycles -system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::total 903394412 # number of ReadReq MSHR uncacheable cycles -system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::cpu2 551786925 # number of WriteReq MSHR uncacheable cycles -system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::total 551786925 # number of WriteReq MSHR uncacheable cycles -system.cpu2.l1c.overall_mshr_uncacheable_latency::cpu2 1455181337 # number of overall MSHR uncacheable cycles -system.cpu2.l1c.overall_mshr_uncacheable_latency::total 1455181337 # number of overall MSHR uncacheable cycles -system.cpu2.l1c.ReadReq_mshr_miss_rate::cpu2 0.801880 # mshr miss rate for ReadReq accesses -system.cpu2.l1c.ReadReq_mshr_miss_rate::total 0.801880 # mshr miss rate for ReadReq accesses -system.cpu2.l1c.WriteReq_mshr_miss_rate::cpu2 0.955057 # mshr miss rate for WriteReq accesses -system.cpu2.l1c.WriteReq_mshr_miss_rate::total 0.955057 # mshr miss rate for WriteReq accesses -system.cpu2.l1c.demand_mshr_miss_rate::cpu2 0.855457 # mshr miss rate for demand accesses -system.cpu2.l1c.demand_mshr_miss_rate::total 0.855457 # mshr miss rate for demand accesses -system.cpu2.l1c.overall_mshr_miss_rate::cpu2 0.855457 # mshr miss rate for overall accesses -system.cpu2.l1c.overall_mshr_miss_rate::total 0.855457 # mshr miss rate for overall accesses -system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::cpu2 25067.623312 # average ReadReq mshr miss latency -system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::total 25067.623312 # average ReadReq mshr miss latency -system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::cpu2 37350.669332 # average WriteReq mshr miss latency -system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::total 37350.669332 # average WriteReq mshr miss latency -system.cpu2.l1c.demand_avg_mshr_miss_latency::cpu2 29864.128294 # average overall mshr miss latency -system.cpu2.l1c.demand_avg_mshr_miss_latency::total 29864.128294 # average overall mshr miss latency -system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 29864.128294 # average overall mshr miss latency -system.cpu2.l1c.overall_avg_mshr_miss_latency::total 29864.128294 # average overall mshr miss latency +system.cpu2.l1c.writebacks::writebacks 9600 # number of writebacks +system.cpu2.l1c.writebacks::total 9600 # number of writebacks +system.cpu2.l1c.ReadReq_mshr_misses::cpu2 36026 # number of ReadReq MSHR misses +system.cpu2.l1c.ReadReq_mshr_misses::total 36026 # number of ReadReq MSHR misses +system.cpu2.l1c.WriteReq_mshr_misses::cpu2 23186 # number of WriteReq MSHR misses +system.cpu2.l1c.WriteReq_mshr_misses::total 23186 # number of WriteReq MSHR misses +system.cpu2.l1c.demand_mshr_misses::cpu2 59212 # number of demand (read+write) MSHR misses +system.cpu2.l1c.demand_mshr_misses::total 59212 # number of demand (read+write) MSHR misses +system.cpu2.l1c.overall_mshr_misses::cpu2 59212 # number of overall MSHR misses +system.cpu2.l1c.overall_mshr_misses::total 59212 # number of overall MSHR misses +system.cpu2.l1c.ReadReq_mshr_miss_latency::cpu2 862954550 # number of ReadReq MSHR miss cycles +system.cpu2.l1c.ReadReq_mshr_miss_latency::total 862954550 # number of ReadReq MSHR miss cycles +system.cpu2.l1c.WriteReq_mshr_miss_latency::cpu2 790376865 # number of WriteReq MSHR miss cycles +system.cpu2.l1c.WriteReq_mshr_miss_latency::total 790376865 # number of WriteReq MSHR miss cycles +system.cpu2.l1c.demand_mshr_miss_latency::cpu2 1653331415 # number of demand (read+write) MSHR miss cycles +system.cpu2.l1c.demand_mshr_miss_latency::total 1653331415 # number of demand (read+write) MSHR miss cycles +system.cpu2.l1c.overall_mshr_miss_latency::cpu2 1653331415 # number of overall MSHR miss cycles +system.cpu2.l1c.overall_mshr_miss_latency::total 1653331415 # number of overall MSHR miss cycles +system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::cpu2 676110998 # number of ReadReq MSHR uncacheable cycles +system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::total 676110998 # number of ReadReq MSHR uncacheable cycles +system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::cpu2 681557695 # number of WriteReq MSHR uncacheable cycles +system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::total 681557695 # number of WriteReq MSHR uncacheable cycles +system.cpu2.l1c.overall_mshr_uncacheable_latency::cpu2 1357668693 # number of overall MSHR uncacheable cycles +system.cpu2.l1c.overall_mshr_uncacheable_latency::total 1357668693 # number of overall MSHR uncacheable cycles +system.cpu2.l1c.ReadReq_mshr_miss_rate::cpu2 0.805122 # mshr miss rate for ReadReq accesses +system.cpu2.l1c.ReadReq_mshr_miss_rate::total 0.805122 # mshr miss rate for ReadReq accesses +system.cpu2.l1c.WriteReq_mshr_miss_rate::cpu2 0.955100 # mshr miss rate for WriteReq accesses +system.cpu2.l1c.WriteReq_mshr_miss_rate::total 0.955100 # mshr miss rate for WriteReq accesses +system.cpu2.l1c.demand_mshr_miss_rate::cpu2 0.857871 # mshr miss rate for demand accesses +system.cpu2.l1c.demand_mshr_miss_rate::total 0.857871 # mshr miss rate for demand accesses +system.cpu2.l1c.overall_mshr_miss_rate::cpu2 0.857871 # mshr miss rate for overall accesses +system.cpu2.l1c.overall_mshr_miss_rate::total 0.857871 # mshr miss rate for overall accesses +system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::cpu2 23953.659857 # average ReadReq mshr miss latency +system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::total 23953.659857 # average ReadReq mshr miss latency +system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::cpu2 34088.538989 # average WriteReq mshr miss latency +system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::total 34088.538989 # average WriteReq mshr miss latency +system.cpu2.l1c.demand_avg_mshr_miss_latency::cpu2 27922.235611 # average overall mshr miss latency +system.cpu2.l1c.demand_avg_mshr_miss_latency::total 27922.235611 # average overall mshr miss latency +system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 27922.235611 # average overall mshr miss latency +system.cpu2.l1c.overall_avg_mshr_miss_latency::total 27922.235611 # average overall mshr miss latency system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu2 inf # average ReadReq mshr uncacheable latency system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu2 inf # average WriteReq mshr uncacheable latency @@ -1005,114 +1008,114 @@ system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::cpu2 inf # average overall mshr uncacheable latency system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu2.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.num_reads 98310 # number of read accesses completed -system.cpu3.num_writes 53451 # number of write accesses completed +system.cpu3.num_reads 98954 # number of read accesses completed +system.cpu3.num_writes 53519 # number of write accesses completed system.cpu3.num_copies 0 # number of copy accesses completed -system.cpu3.l1c.replacements 21775 # number of replacements -system.cpu3.l1c.tagsinuse 395.971374 # Cycle average of tags in use -system.cpu3.l1c.total_refs 13179 # Total number of references to valid blocks. -system.cpu3.l1c.sampled_refs 22179 # Sample count of references to valid blocks. -system.cpu3.l1c.avg_refs 0.594211 # Average number of references to valid blocks. +system.cpu3.l1c.replacements 21866 # number of replacements +system.cpu3.l1c.tagsinuse 395.683419 # Cycle average of tags in use +system.cpu3.l1c.total_refs 13218 # Total number of references to valid blocks. +system.cpu3.l1c.sampled_refs 22277 # Sample count of references to valid blocks. +system.cpu3.l1c.avg_refs 0.593347 # Average number of references to valid blocks. system.cpu3.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.l1c.occ_blocks::cpu3 395.971374 # Average occupied blocks per requestor -system.cpu3.l1c.occ_percent::cpu3 0.773382 # Average percentage of cache occupancy -system.cpu3.l1c.occ_percent::total 0.773382 # Average percentage of cache occupancy -system.cpu3.l1c.ReadReq_hits::cpu3 8374 # number of ReadReq hits -system.cpu3.l1c.ReadReq_hits::total 8374 # number of ReadReq hits -system.cpu3.l1c.WriteReq_hits::cpu3 1100 # number of WriteReq hits -system.cpu3.l1c.WriteReq_hits::total 1100 # number of WriteReq hits -system.cpu3.l1c.demand_hits::cpu3 9474 # number of demand (read+write) hits -system.cpu3.l1c.demand_hits::total 9474 # number of demand (read+write) hits -system.cpu3.l1c.overall_hits::cpu3 9474 # number of overall hits -system.cpu3.l1c.overall_hits::total 9474 # number of overall hits -system.cpu3.l1c.ReadReq_misses::cpu3 35667 # number of ReadReq misses -system.cpu3.l1c.ReadReq_misses::total 35667 # number of ReadReq misses -system.cpu3.l1c.WriteReq_misses::cpu3 23305 # number of WriteReq misses -system.cpu3.l1c.WriteReq_misses::total 23305 # number of WriteReq misses -system.cpu3.l1c.demand_misses::cpu3 58972 # number of demand (read+write) misses -system.cpu3.l1c.demand_misses::total 58972 # number of demand (read+write) misses -system.cpu3.l1c.overall_misses::cpu3 58972 # number of overall misses -system.cpu3.l1c.overall_misses::total 58972 # number of overall misses -system.cpu3.l1c.ReadReq_miss_latency::cpu3 919630073 # number of ReadReq miss cycles -system.cpu3.l1c.ReadReq_miss_latency::total 919630073 # number of ReadReq miss cycles -system.cpu3.l1c.WriteReq_miss_latency::cpu3 893117472 # number of WriteReq miss cycles -system.cpu3.l1c.WriteReq_miss_latency::total 893117472 # number of WriteReq miss cycles -system.cpu3.l1c.demand_miss_latency::cpu3 1812747545 # number of demand (read+write) miss cycles -system.cpu3.l1c.demand_miss_latency::total 1812747545 # number of demand (read+write) miss cycles -system.cpu3.l1c.overall_miss_latency::cpu3 1812747545 # number of overall miss cycles -system.cpu3.l1c.overall_miss_latency::total 1812747545 # number of overall miss cycles -system.cpu3.l1c.ReadReq_accesses::cpu3 44041 # number of ReadReq accesses(hits+misses) -system.cpu3.l1c.ReadReq_accesses::total 44041 # number of ReadReq accesses(hits+misses) -system.cpu3.l1c.WriteReq_accesses::cpu3 24405 # number of WriteReq accesses(hits+misses) -system.cpu3.l1c.WriteReq_accesses::total 24405 # number of WriteReq accesses(hits+misses) -system.cpu3.l1c.demand_accesses::cpu3 68446 # number of demand (read+write) accesses -system.cpu3.l1c.demand_accesses::total 68446 # number of demand (read+write) accesses -system.cpu3.l1c.overall_accesses::cpu3 68446 # number of overall (read+write) accesses -system.cpu3.l1c.overall_accesses::total 68446 # number of overall (read+write) accesses -system.cpu3.l1c.ReadReq_miss_rate::cpu3 0.809859 # miss rate for ReadReq accesses -system.cpu3.l1c.ReadReq_miss_rate::total 0.809859 # miss rate for ReadReq accesses -system.cpu3.l1c.WriteReq_miss_rate::cpu3 0.954927 # miss rate for WriteReq accesses -system.cpu3.l1c.WriteReq_miss_rate::total 0.954927 # miss rate for WriteReq accesses -system.cpu3.l1c.demand_miss_rate::cpu3 0.861584 # miss rate for demand accesses -system.cpu3.l1c.demand_miss_rate::total 0.861584 # miss rate for demand accesses -system.cpu3.l1c.overall_miss_rate::cpu3 0.861584 # miss rate for overall accesses -system.cpu3.l1c.overall_miss_rate::total 0.861584 # miss rate for overall accesses -system.cpu3.l1c.ReadReq_avg_miss_latency::cpu3 25783.779768 # average ReadReq miss latency -system.cpu3.l1c.ReadReq_avg_miss_latency::total 25783.779768 # average ReadReq miss latency -system.cpu3.l1c.WriteReq_avg_miss_latency::cpu3 38322.998155 # average WriteReq miss latency -system.cpu3.l1c.WriteReq_avg_miss_latency::total 38322.998155 # average WriteReq miss latency -system.cpu3.l1c.demand_avg_miss_latency::cpu3 30739.122719 # average overall miss latency -system.cpu3.l1c.demand_avg_miss_latency::total 30739.122719 # average overall miss latency -system.cpu3.l1c.overall_avg_miss_latency::cpu3 30739.122719 # average overall miss latency -system.cpu3.l1c.overall_avg_miss_latency::total 30739.122719 # average overall miss latency -system.cpu3.l1c.blocked_cycles::no_mshrs 213693223 # number of cycles access was blocked +system.cpu3.l1c.occ_blocks::cpu3 395.683419 # Average occupied blocks per requestor +system.cpu3.l1c.occ_percent::cpu3 0.772819 # Average percentage of cache occupancy +system.cpu3.l1c.occ_percent::total 0.772819 # Average percentage of cache occupancy +system.cpu3.l1c.ReadReq_hits::cpu3 8562 # number of ReadReq hits +system.cpu3.l1c.ReadReq_hits::total 8562 # number of ReadReq hits +system.cpu3.l1c.WriteReq_hits::cpu3 1098 # number of WriteReq hits +system.cpu3.l1c.WriteReq_hits::total 1098 # number of WriteReq hits +system.cpu3.l1c.demand_hits::cpu3 9660 # number of demand (read+write) hits +system.cpu3.l1c.demand_hits::total 9660 # number of demand (read+write) hits +system.cpu3.l1c.overall_hits::cpu3 9660 # number of overall hits +system.cpu3.l1c.overall_hits::total 9660 # number of overall hits +system.cpu3.l1c.ReadReq_misses::cpu3 35996 # number of ReadReq misses +system.cpu3.l1c.ReadReq_misses::total 35996 # number of ReadReq misses +system.cpu3.l1c.WriteReq_misses::cpu3 23029 # number of WriteReq misses +system.cpu3.l1c.WriteReq_misses::total 23029 # number of WriteReq misses +system.cpu3.l1c.demand_misses::cpu3 59025 # number of demand (read+write) misses +system.cpu3.l1c.demand_misses::total 59025 # number of demand (read+write) misses +system.cpu3.l1c.overall_misses::cpu3 59025 # number of overall misses +system.cpu3.l1c.overall_misses::total 59025 # number of overall misses +system.cpu3.l1c.ReadReq_miss_latency::cpu3 899058428 # number of ReadReq miss cycles +system.cpu3.l1c.ReadReq_miss_latency::total 899058428 # number of ReadReq miss cycles +system.cpu3.l1c.WriteReq_miss_latency::cpu3 817455350 # number of WriteReq miss cycles +system.cpu3.l1c.WriteReq_miss_latency::total 817455350 # number of WriteReq miss cycles +system.cpu3.l1c.demand_miss_latency::cpu3 1716513778 # number of demand (read+write) miss cycles +system.cpu3.l1c.demand_miss_latency::total 1716513778 # number of demand (read+write) miss cycles +system.cpu3.l1c.overall_miss_latency::cpu3 1716513778 # number of overall miss cycles +system.cpu3.l1c.overall_miss_latency::total 1716513778 # number of overall miss cycles +system.cpu3.l1c.ReadReq_accesses::cpu3 44558 # number of ReadReq accesses(hits+misses) +system.cpu3.l1c.ReadReq_accesses::total 44558 # number of ReadReq accesses(hits+misses) +system.cpu3.l1c.WriteReq_accesses::cpu3 24127 # number of WriteReq accesses(hits+misses) +system.cpu3.l1c.WriteReq_accesses::total 24127 # number of WriteReq accesses(hits+misses) +system.cpu3.l1c.demand_accesses::cpu3 68685 # number of demand (read+write) accesses +system.cpu3.l1c.demand_accesses::total 68685 # number of demand (read+write) accesses +system.cpu3.l1c.overall_accesses::cpu3 68685 # number of overall (read+write) accesses +system.cpu3.l1c.overall_accesses::total 68685 # number of overall (read+write) accesses +system.cpu3.l1c.ReadReq_miss_rate::cpu3 0.807846 # miss rate for ReadReq accesses +system.cpu3.l1c.ReadReq_miss_rate::total 0.807846 # miss rate for ReadReq accesses +system.cpu3.l1c.WriteReq_miss_rate::cpu3 0.954491 # miss rate for WriteReq accesses +system.cpu3.l1c.WriteReq_miss_rate::total 0.954491 # miss rate for WriteReq accesses +system.cpu3.l1c.demand_miss_rate::cpu3 0.859358 # miss rate for demand accesses +system.cpu3.l1c.demand_miss_rate::total 0.859358 # miss rate for demand accesses +system.cpu3.l1c.overall_miss_rate::cpu3 0.859358 # miss rate for overall accesses +system.cpu3.l1c.overall_miss_rate::total 0.859358 # miss rate for overall accesses +system.cpu3.l1c.ReadReq_avg_miss_latency::cpu3 24976.620402 # average ReadReq miss latency +system.cpu3.l1c.ReadReq_avg_miss_latency::total 24976.620402 # average ReadReq miss latency +system.cpu3.l1c.WriteReq_avg_miss_latency::cpu3 35496.780147 # average WriteReq miss latency +system.cpu3.l1c.WriteReq_avg_miss_latency::total 35496.780147 # average WriteReq miss latency +system.cpu3.l1c.demand_avg_miss_latency::cpu3 29081.131351 # average overall miss latency +system.cpu3.l1c.demand_avg_miss_latency::total 29081.131351 # average overall miss latency +system.cpu3.l1c.overall_avg_miss_latency::cpu3 29081.131351 # average overall miss latency +system.cpu3.l1c.overall_avg_miss_latency::total 29081.131351 # average overall miss latency +system.cpu3.l1c.blocked_cycles::no_mshrs 155038956 # number of cycles access was blocked system.cpu3.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu3.l1c.blocked::no_mshrs 67039 # number of cycles access was blocked +system.cpu3.l1c.blocked::no_mshrs 53124 # number of cycles access was blocked system.cpu3.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu3.l1c.avg_blocked_cycles::no_mshrs 3187.595623 # average number of cycles each access was blocked +system.cpu3.l1c.avg_blocked_cycles::no_mshrs 2918.435283 # average number of cycles each access was blocked system.cpu3.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu3.l1c.fast_writes 0 # number of fast writes performed system.cpu3.l1c.cache_copies 0 # number of cache copies performed -system.cpu3.l1c.writebacks::writebacks 9546 # number of writebacks -system.cpu3.l1c.writebacks::total 9546 # number of writebacks -system.cpu3.l1c.ReadReq_mshr_misses::cpu3 35667 # number of ReadReq MSHR misses -system.cpu3.l1c.ReadReq_mshr_misses::total 35667 # number of ReadReq MSHR misses -system.cpu3.l1c.WriteReq_mshr_misses::cpu3 23305 # number of WriteReq MSHR misses -system.cpu3.l1c.WriteReq_mshr_misses::total 23305 # number of WriteReq MSHR misses -system.cpu3.l1c.demand_mshr_misses::cpu3 58972 # number of demand (read+write) MSHR misses -system.cpu3.l1c.demand_mshr_misses::total 58972 # number of demand (read+write) MSHR misses -system.cpu3.l1c.overall_mshr_misses::cpu3 58972 # number of overall MSHR misses -system.cpu3.l1c.overall_mshr_misses::total 58972 # number of overall MSHR misses -system.cpu3.l1c.ReadReq_mshr_miss_latency::cpu3 883822339 # number of ReadReq MSHR miss cycles -system.cpu3.l1c.ReadReq_mshr_miss_latency::total 883822339 # number of ReadReq MSHR miss cycles -system.cpu3.l1c.WriteReq_mshr_miss_latency::cpu3 869724232 # number of WriteReq MSHR miss cycles -system.cpu3.l1c.WriteReq_mshr_miss_latency::total 869724232 # number of WriteReq MSHR miss cycles -system.cpu3.l1c.demand_mshr_miss_latency::cpu3 1753546571 # number of demand (read+write) MSHR miss cycles -system.cpu3.l1c.demand_mshr_miss_latency::total 1753546571 # number of demand (read+write) MSHR miss cycles -system.cpu3.l1c.overall_mshr_miss_latency::cpu3 1753546571 # number of overall MSHR miss cycles -system.cpu3.l1c.overall_mshr_miss_latency::total 1753546571 # number of overall MSHR miss cycles -system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::cpu3 901886993 # number of ReadReq MSHR uncacheable cycles -system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::total 901886993 # number of ReadReq MSHR uncacheable cycles -system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::cpu3 561139437 # number of WriteReq MSHR uncacheable cycles -system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::total 561139437 # number of WriteReq MSHR uncacheable cycles -system.cpu3.l1c.overall_mshr_uncacheable_latency::cpu3 1463026430 # number of overall MSHR uncacheable cycles -system.cpu3.l1c.overall_mshr_uncacheable_latency::total 1463026430 # number of overall MSHR uncacheable cycles -system.cpu3.l1c.ReadReq_mshr_miss_rate::cpu3 0.809859 # mshr miss rate for ReadReq accesses -system.cpu3.l1c.ReadReq_mshr_miss_rate::total 0.809859 # mshr miss rate for ReadReq accesses -system.cpu3.l1c.WriteReq_mshr_miss_rate::cpu3 0.954927 # mshr miss rate for WriteReq accesses -system.cpu3.l1c.WriteReq_mshr_miss_rate::total 0.954927 # mshr miss rate for WriteReq accesses -system.cpu3.l1c.demand_mshr_miss_rate::cpu3 0.861584 # mshr miss rate for demand accesses -system.cpu3.l1c.demand_mshr_miss_rate::total 0.861584 # mshr miss rate for demand accesses -system.cpu3.l1c.overall_mshr_miss_rate::cpu3 0.861584 # mshr miss rate for overall accesses -system.cpu3.l1c.overall_mshr_miss_rate::total 0.861584 # mshr miss rate for overall accesses -system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::cpu3 24779.833992 # average ReadReq mshr miss latency -system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::total 24779.833992 # average ReadReq mshr miss latency -system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::cpu3 37319.211843 # average WriteReq mshr miss latency -system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::total 37319.211843 # average WriteReq mshr miss latency -system.cpu3.l1c.demand_avg_mshr_miss_latency::cpu3 29735.239961 # average overall mshr miss latency -system.cpu3.l1c.demand_avg_mshr_miss_latency::total 29735.239961 # average overall mshr miss latency -system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 29735.239961 # average overall mshr miss latency -system.cpu3.l1c.overall_avg_mshr_miss_latency::total 29735.239961 # average overall mshr miss latency +system.cpu3.l1c.writebacks::writebacks 9442 # number of writebacks +system.cpu3.l1c.writebacks::total 9442 # number of writebacks +system.cpu3.l1c.ReadReq_mshr_misses::cpu3 35996 # number of ReadReq MSHR misses +system.cpu3.l1c.ReadReq_mshr_misses::total 35996 # number of ReadReq MSHR misses +system.cpu3.l1c.WriteReq_mshr_misses::cpu3 23029 # number of WriteReq MSHR misses +system.cpu3.l1c.WriteReq_mshr_misses::total 23029 # number of WriteReq MSHR misses +system.cpu3.l1c.demand_mshr_misses::cpu3 59025 # number of demand (read+write) MSHR misses +system.cpu3.l1c.demand_mshr_misses::total 59025 # number of demand (read+write) MSHR misses +system.cpu3.l1c.overall_mshr_misses::cpu3 59025 # number of overall MSHR misses +system.cpu3.l1c.overall_mshr_misses::total 59025 # number of overall MSHR misses +system.cpu3.l1c.ReadReq_mshr_miss_latency::cpu3 862924447 # number of ReadReq MSHR miss cycles +system.cpu3.l1c.ReadReq_mshr_miss_latency::total 862924447 # number of ReadReq MSHR miss cycles +system.cpu3.l1c.WriteReq_mshr_miss_latency::cpu3 794336234 # number of WriteReq MSHR miss cycles +system.cpu3.l1c.WriteReq_mshr_miss_latency::total 794336234 # number of WriteReq MSHR miss cycles +system.cpu3.l1c.demand_mshr_miss_latency::cpu3 1657260681 # number of demand (read+write) MSHR miss cycles +system.cpu3.l1c.demand_mshr_miss_latency::total 1657260681 # number of demand (read+write) MSHR miss cycles +system.cpu3.l1c.overall_mshr_miss_latency::cpu3 1657260681 # number of overall MSHR miss cycles +system.cpu3.l1c.overall_mshr_miss_latency::total 1657260681 # number of overall MSHR miss cycles +system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::cpu3 680106792 # number of ReadReq MSHR uncacheable cycles +system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::total 680106792 # number of ReadReq MSHR uncacheable cycles +system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::cpu3 674669668 # number of WriteReq MSHR uncacheable cycles +system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::total 674669668 # number of WriteReq MSHR uncacheable cycles +system.cpu3.l1c.overall_mshr_uncacheable_latency::cpu3 1354776460 # number of overall MSHR uncacheable cycles +system.cpu3.l1c.overall_mshr_uncacheable_latency::total 1354776460 # number of overall MSHR uncacheable cycles +system.cpu3.l1c.ReadReq_mshr_miss_rate::cpu3 0.807846 # mshr miss rate for ReadReq accesses +system.cpu3.l1c.ReadReq_mshr_miss_rate::total 0.807846 # mshr miss rate for ReadReq accesses +system.cpu3.l1c.WriteReq_mshr_miss_rate::cpu3 0.954491 # mshr miss rate for WriteReq accesses +system.cpu3.l1c.WriteReq_mshr_miss_rate::total 0.954491 # mshr miss rate for WriteReq accesses +system.cpu3.l1c.demand_mshr_miss_rate::cpu3 0.859358 # mshr miss rate for demand accesses +system.cpu3.l1c.demand_mshr_miss_rate::total 0.859358 # mshr miss rate for demand accesses +system.cpu3.l1c.overall_mshr_miss_rate::cpu3 0.859358 # mshr miss rate for overall accesses +system.cpu3.l1c.overall_mshr_miss_rate::total 0.859358 # mshr miss rate for overall accesses +system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::cpu3 23972.787171 # average ReadReq mshr miss latency +system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::total 23972.787171 # average ReadReq mshr miss latency +system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::cpu3 34492.866994 # average WriteReq mshr miss latency +system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::total 34492.866994 # average WriteReq mshr miss latency +system.cpu3.l1c.demand_avg_mshr_miss_latency::cpu3 28077.266938 # average overall mshr miss latency +system.cpu3.l1c.demand_avg_mshr_miss_latency::total 28077.266938 # average overall mshr miss latency +system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 28077.266938 # average overall mshr miss latency +system.cpu3.l1c.overall_avg_mshr_miss_latency::total 28077.266938 # average overall mshr miss latency system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu3 inf # average ReadReq mshr uncacheable latency system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu3 inf # average WriteReq mshr uncacheable latency @@ -1120,114 +1123,114 @@ system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::cpu3 inf # average overall mshr uncacheable latency system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu3.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu4.num_reads 100000 # number of read accesses completed -system.cpu4.num_writes 53697 # number of write accesses completed +system.cpu4.num_reads 99591 # number of read accesses completed +system.cpu4.num_writes 53646 # number of write accesses completed system.cpu4.num_copies 0 # number of copy accesses completed -system.cpu4.l1c.replacements 22069 # number of replacements -system.cpu4.l1c.tagsinuse 396.565187 # Cycle average of tags in use -system.cpu4.l1c.total_refs 13244 # Total number of references to valid blocks. -system.cpu4.l1c.sampled_refs 22489 # Sample count of references to valid blocks. -system.cpu4.l1c.avg_refs 0.588910 # Average number of references to valid blocks. +system.cpu4.l1c.replacements 22293 # number of replacements +system.cpu4.l1c.tagsinuse 397.816545 # Cycle average of tags in use +system.cpu4.l1c.total_refs 13327 # Total number of references to valid blocks. +system.cpu4.l1c.sampled_refs 22684 # Sample count of references to valid blocks. +system.cpu4.l1c.avg_refs 0.587507 # Average number of references to valid blocks. system.cpu4.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu4.l1c.occ_blocks::cpu4 396.565187 # Average occupied blocks per requestor -system.cpu4.l1c.occ_percent::cpu4 0.774541 # Average percentage of cache occupancy -system.cpu4.l1c.occ_percent::total 0.774541 # Average percentage of cache occupancy -system.cpu4.l1c.ReadReq_hits::cpu4 8614 # number of ReadReq hits -system.cpu4.l1c.ReadReq_hits::total 8614 # number of ReadReq hits -system.cpu4.l1c.WriteReq_hits::cpu4 1053 # number of WriteReq hits -system.cpu4.l1c.WriteReq_hits::total 1053 # number of WriteReq hits -system.cpu4.l1c.demand_hits::cpu4 9667 # number of demand (read+write) hits -system.cpu4.l1c.demand_hits::total 9667 # number of demand (read+write) hits -system.cpu4.l1c.overall_hits::cpu4 9667 # number of overall hits -system.cpu4.l1c.overall_hits::total 9667 # number of overall hits -system.cpu4.l1c.ReadReq_misses::cpu4 36078 # number of ReadReq misses -system.cpu4.l1c.ReadReq_misses::total 36078 # number of ReadReq misses -system.cpu4.l1c.WriteReq_misses::cpu4 23045 # number of WriteReq misses -system.cpu4.l1c.WriteReq_misses::total 23045 # number of WriteReq misses -system.cpu4.l1c.demand_misses::cpu4 59123 # number of demand (read+write) misses -system.cpu4.l1c.demand_misses::total 59123 # number of demand (read+write) misses -system.cpu4.l1c.overall_misses::cpu4 59123 # number of overall misses -system.cpu4.l1c.overall_misses::total 59123 # number of overall misses -system.cpu4.l1c.ReadReq_miss_latency::cpu4 933502205 # number of ReadReq miss cycles -system.cpu4.l1c.ReadReq_miss_latency::total 933502205 # number of ReadReq miss cycles -system.cpu4.l1c.WriteReq_miss_latency::cpu4 883607398 # number of WriteReq miss cycles -system.cpu4.l1c.WriteReq_miss_latency::total 883607398 # number of WriteReq miss cycles -system.cpu4.l1c.demand_miss_latency::cpu4 1817109603 # number of demand (read+write) miss cycles -system.cpu4.l1c.demand_miss_latency::total 1817109603 # number of demand (read+write) miss cycles -system.cpu4.l1c.overall_miss_latency::cpu4 1817109603 # number of overall miss cycles -system.cpu4.l1c.overall_miss_latency::total 1817109603 # number of overall miss cycles -system.cpu4.l1c.ReadReq_accesses::cpu4 44692 # number of ReadReq accesses(hits+misses) -system.cpu4.l1c.ReadReq_accesses::total 44692 # number of ReadReq accesses(hits+misses) -system.cpu4.l1c.WriteReq_accesses::cpu4 24098 # number of WriteReq accesses(hits+misses) -system.cpu4.l1c.WriteReq_accesses::total 24098 # number of WriteReq accesses(hits+misses) -system.cpu4.l1c.demand_accesses::cpu4 68790 # number of demand (read+write) accesses -system.cpu4.l1c.demand_accesses::total 68790 # number of demand (read+write) accesses -system.cpu4.l1c.overall_accesses::cpu4 68790 # number of overall (read+write) accesses -system.cpu4.l1c.overall_accesses::total 68790 # number of overall (read+write) accesses -system.cpu4.l1c.ReadReq_miss_rate::cpu4 0.807259 # miss rate for ReadReq accesses -system.cpu4.l1c.ReadReq_miss_rate::total 0.807259 # miss rate for ReadReq accesses -system.cpu4.l1c.WriteReq_miss_rate::cpu4 0.956303 # miss rate for WriteReq accesses -system.cpu4.l1c.WriteReq_miss_rate::total 0.956303 # miss rate for WriteReq accesses -system.cpu4.l1c.demand_miss_rate::cpu4 0.859471 # miss rate for demand accesses -system.cpu4.l1c.demand_miss_rate::total 0.859471 # miss rate for demand accesses -system.cpu4.l1c.overall_miss_rate::cpu4 0.859471 # miss rate for overall accesses -system.cpu4.l1c.overall_miss_rate::total 0.859471 # miss rate for overall accesses -system.cpu4.l1c.ReadReq_avg_miss_latency::cpu4 25874.555269 # average ReadReq miss latency -system.cpu4.l1c.ReadReq_avg_miss_latency::total 25874.555269 # average ReadReq miss latency -system.cpu4.l1c.WriteReq_avg_miss_latency::cpu4 38342.694641 # average WriteReq miss latency -system.cpu4.l1c.WriteReq_avg_miss_latency::total 38342.694641 # average WriteReq miss latency -system.cpu4.l1c.demand_avg_miss_latency::cpu4 30734.394449 # average overall miss latency -system.cpu4.l1c.demand_avg_miss_latency::total 30734.394449 # average overall miss latency -system.cpu4.l1c.overall_avg_miss_latency::cpu4 30734.394449 # average overall miss latency -system.cpu4.l1c.overall_avg_miss_latency::total 30734.394449 # average overall miss latency -system.cpu4.l1c.blocked_cycles::no_mshrs 213249503 # number of cycles access was blocked +system.cpu4.l1c.occ_blocks::cpu4 397.816545 # Average occupied blocks per requestor +system.cpu4.l1c.occ_percent::cpu4 0.776985 # Average percentage of cache occupancy +system.cpu4.l1c.occ_percent::total 0.776985 # Average percentage of cache occupancy +system.cpu4.l1c.ReadReq_hits::cpu4 8743 # number of ReadReq hits +system.cpu4.l1c.ReadReq_hits::total 8743 # number of ReadReq hits +system.cpu4.l1c.WriteReq_hits::cpu4 1036 # number of WriteReq hits +system.cpu4.l1c.WriteReq_hits::total 1036 # number of WriteReq hits +system.cpu4.l1c.demand_hits::cpu4 9779 # number of demand (read+write) hits +system.cpu4.l1c.demand_hits::total 9779 # number of demand (read+write) hits +system.cpu4.l1c.overall_hits::cpu4 9779 # number of overall hits +system.cpu4.l1c.overall_hits::total 9779 # number of overall hits +system.cpu4.l1c.ReadReq_misses::cpu4 35998 # number of ReadReq misses +system.cpu4.l1c.ReadReq_misses::total 35998 # number of ReadReq misses +system.cpu4.l1c.WriteReq_misses::cpu4 23232 # number of WriteReq misses +system.cpu4.l1c.WriteReq_misses::total 23232 # number of WriteReq misses +system.cpu4.l1c.demand_misses::cpu4 59230 # number of demand (read+write) misses +system.cpu4.l1c.demand_misses::total 59230 # number of demand (read+write) misses +system.cpu4.l1c.overall_misses::cpu4 59230 # number of overall misses +system.cpu4.l1c.overall_misses::total 59230 # number of overall misses +system.cpu4.l1c.ReadReq_miss_latency::cpu4 899681935 # number of ReadReq miss cycles +system.cpu4.l1c.ReadReq_miss_latency::total 899681935 # number of ReadReq miss cycles +system.cpu4.l1c.WriteReq_miss_latency::cpu4 816003996 # number of WriteReq miss cycles +system.cpu4.l1c.WriteReq_miss_latency::total 816003996 # number of WriteReq miss cycles +system.cpu4.l1c.demand_miss_latency::cpu4 1715685931 # number of demand (read+write) miss cycles +system.cpu4.l1c.demand_miss_latency::total 1715685931 # number of demand (read+write) miss cycles +system.cpu4.l1c.overall_miss_latency::cpu4 1715685931 # number of overall miss cycles +system.cpu4.l1c.overall_miss_latency::total 1715685931 # number of overall miss cycles +system.cpu4.l1c.ReadReq_accesses::cpu4 44741 # number of ReadReq accesses(hits+misses) +system.cpu4.l1c.ReadReq_accesses::total 44741 # number of ReadReq accesses(hits+misses) +system.cpu4.l1c.WriteReq_accesses::cpu4 24268 # number of WriteReq accesses(hits+misses) +system.cpu4.l1c.WriteReq_accesses::total 24268 # number of WriteReq accesses(hits+misses) +system.cpu4.l1c.demand_accesses::cpu4 69009 # number of demand (read+write) accesses +system.cpu4.l1c.demand_accesses::total 69009 # number of demand (read+write) accesses +system.cpu4.l1c.overall_accesses::cpu4 69009 # number of overall (read+write) accesses +system.cpu4.l1c.overall_accesses::total 69009 # number of overall (read+write) accesses +system.cpu4.l1c.ReadReq_miss_rate::cpu4 0.804586 # miss rate for ReadReq accesses +system.cpu4.l1c.ReadReq_miss_rate::total 0.804586 # miss rate for ReadReq accesses +system.cpu4.l1c.WriteReq_miss_rate::cpu4 0.957310 # miss rate for WriteReq accesses +system.cpu4.l1c.WriteReq_miss_rate::total 0.957310 # miss rate for WriteReq accesses +system.cpu4.l1c.demand_miss_rate::cpu4 0.858294 # miss rate for demand accesses +system.cpu4.l1c.demand_miss_rate::total 0.858294 # miss rate for demand accesses +system.cpu4.l1c.overall_miss_rate::cpu4 0.858294 # miss rate for overall accesses +system.cpu4.l1c.overall_miss_rate::total 0.858294 # miss rate for overall accesses +system.cpu4.l1c.ReadReq_avg_miss_latency::cpu4 24992.553336 # average ReadReq miss latency +system.cpu4.l1c.ReadReq_avg_miss_latency::total 24992.553336 # average ReadReq miss latency +system.cpu4.l1c.WriteReq_avg_miss_latency::cpu4 35124.138946 # average WriteReq miss latency +system.cpu4.l1c.WriteReq_avg_miss_latency::total 35124.138946 # average WriteReq miss latency +system.cpu4.l1c.demand_avg_miss_latency::cpu4 28966.502296 # average overall miss latency +system.cpu4.l1c.demand_avg_miss_latency::total 28966.502296 # average overall miss latency +system.cpu4.l1c.overall_avg_miss_latency::cpu4 28966.502296 # average overall miss latency +system.cpu4.l1c.overall_avg_miss_latency::total 28966.502296 # average overall miss latency +system.cpu4.l1c.blocked_cycles::no_mshrs 154355931 # number of cycles access was blocked system.cpu4.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu4.l1c.blocked::no_mshrs 67264 # number of cycles access was blocked +system.cpu4.l1c.blocked::no_mshrs 53171 # number of cycles access was blocked system.cpu4.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu4.l1c.avg_blocked_cycles::no_mshrs 3170.336331 # average number of cycles each access was blocked +system.cpu4.l1c.avg_blocked_cycles::no_mshrs 2903.009742 # average number of cycles each access was blocked system.cpu4.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu4.l1c.fast_writes 0 # number of fast writes performed system.cpu4.l1c.cache_copies 0 # number of cache copies performed -system.cpu4.l1c.writebacks::writebacks 9627 # number of writebacks -system.cpu4.l1c.writebacks::total 9627 # number of writebacks -system.cpu4.l1c.ReadReq_mshr_misses::cpu4 36078 # number of ReadReq MSHR misses -system.cpu4.l1c.ReadReq_mshr_misses::total 36078 # number of ReadReq MSHR misses -system.cpu4.l1c.WriteReq_mshr_misses::cpu4 23045 # number of WriteReq MSHR misses -system.cpu4.l1c.WriteReq_mshr_misses::total 23045 # number of WriteReq MSHR misses -system.cpu4.l1c.demand_mshr_misses::cpu4 59123 # number of demand (read+write) MSHR misses -system.cpu4.l1c.demand_mshr_misses::total 59123 # number of demand (read+write) MSHR misses -system.cpu4.l1c.overall_mshr_misses::cpu4 59123 # number of overall MSHR misses -system.cpu4.l1c.overall_mshr_misses::total 59123 # number of overall MSHR misses -system.cpu4.l1c.ReadReq_mshr_miss_latency::cpu4 897285830 # number of ReadReq MSHR miss cycles -system.cpu4.l1c.ReadReq_mshr_miss_latency::total 897285830 # number of ReadReq MSHR miss cycles -system.cpu4.l1c.WriteReq_mshr_miss_latency::cpu4 860474190 # number of WriteReq MSHR miss cycles -system.cpu4.l1c.WriteReq_mshr_miss_latency::total 860474190 # number of WriteReq MSHR miss cycles -system.cpu4.l1c.demand_mshr_miss_latency::cpu4 1757760020 # number of demand (read+write) MSHR miss cycles -system.cpu4.l1c.demand_mshr_miss_latency::total 1757760020 # number of demand (read+write) MSHR miss cycles -system.cpu4.l1c.overall_mshr_miss_latency::cpu4 1757760020 # number of overall MSHR miss cycles -system.cpu4.l1c.overall_mshr_miss_latency::total 1757760020 # number of overall MSHR miss cycles -system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::cpu4 897898466 # number of ReadReq MSHR uncacheable cycles -system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::total 897898466 # number of ReadReq MSHR uncacheable cycles -system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::cpu4 564390024 # number of WriteReq MSHR uncacheable cycles -system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::total 564390024 # number of WriteReq MSHR uncacheable cycles -system.cpu4.l1c.overall_mshr_uncacheable_latency::cpu4 1462288490 # number of overall MSHR uncacheable cycles -system.cpu4.l1c.overall_mshr_uncacheable_latency::total 1462288490 # number of overall MSHR uncacheable cycles -system.cpu4.l1c.ReadReq_mshr_miss_rate::cpu4 0.807259 # mshr miss rate for ReadReq accesses -system.cpu4.l1c.ReadReq_mshr_miss_rate::total 0.807259 # mshr miss rate for ReadReq accesses -system.cpu4.l1c.WriteReq_mshr_miss_rate::cpu4 0.956303 # mshr miss rate for WriteReq accesses -system.cpu4.l1c.WriteReq_mshr_miss_rate::total 0.956303 # mshr miss rate for WriteReq accesses -system.cpu4.l1c.demand_mshr_miss_rate::cpu4 0.859471 # mshr miss rate for demand accesses -system.cpu4.l1c.demand_mshr_miss_rate::total 0.859471 # mshr miss rate for demand accesses -system.cpu4.l1c.overall_mshr_miss_rate::cpu4 0.859471 # mshr miss rate for overall accesses -system.cpu4.l1c.overall_mshr_miss_rate::total 0.859471 # mshr miss rate for overall accesses -system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::cpu4 24870.719829 # average ReadReq mshr miss latency -system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::total 24870.719829 # average ReadReq mshr miss latency -system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::cpu4 37338.866999 # average WriteReq mshr miss latency -system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::total 37338.866999 # average WriteReq mshr miss latency -system.cpu4.l1c.demand_avg_mshr_miss_latency::cpu4 29730.562049 # average overall mshr miss latency -system.cpu4.l1c.demand_avg_mshr_miss_latency::total 29730.562049 # average overall mshr miss latency -system.cpu4.l1c.overall_avg_mshr_miss_latency::cpu4 29730.562049 # average overall mshr miss latency -system.cpu4.l1c.overall_avg_mshr_miss_latency::total 29730.562049 # average overall mshr miss latency +system.cpu4.l1c.writebacks::writebacks 9702 # number of writebacks +system.cpu4.l1c.writebacks::total 9702 # number of writebacks +system.cpu4.l1c.ReadReq_mshr_misses::cpu4 35998 # number of ReadReq MSHR misses +system.cpu4.l1c.ReadReq_mshr_misses::total 35998 # number of ReadReq MSHR misses +system.cpu4.l1c.WriteReq_mshr_misses::cpu4 23232 # number of WriteReq MSHR misses +system.cpu4.l1c.WriteReq_mshr_misses::total 23232 # number of WriteReq MSHR misses +system.cpu4.l1c.demand_mshr_misses::cpu4 59230 # number of demand (read+write) MSHR misses +system.cpu4.l1c.demand_mshr_misses::total 59230 # number of demand (read+write) MSHR misses +system.cpu4.l1c.overall_mshr_misses::cpu4 59230 # number of overall MSHR misses +system.cpu4.l1c.overall_mshr_misses::total 59230 # number of overall MSHR misses +system.cpu4.l1c.ReadReq_mshr_miss_latency::cpu4 863541936 # number of ReadReq MSHR miss cycles +system.cpu4.l1c.ReadReq_mshr_miss_latency::total 863541936 # number of ReadReq MSHR miss cycles +system.cpu4.l1c.WriteReq_mshr_miss_latency::cpu4 792684079 # number of WriteReq MSHR miss cycles +system.cpu4.l1c.WriteReq_mshr_miss_latency::total 792684079 # number of WriteReq MSHR miss cycles +system.cpu4.l1c.demand_mshr_miss_latency::cpu4 1656226015 # number of demand (read+write) MSHR miss cycles +system.cpu4.l1c.demand_mshr_miss_latency::total 1656226015 # number of demand (read+write) MSHR miss cycles +system.cpu4.l1c.overall_mshr_miss_latency::cpu4 1656226015 # number of overall MSHR miss cycles +system.cpu4.l1c.overall_mshr_miss_latency::total 1656226015 # number of overall MSHR miss cycles +system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::cpu4 681350371 # number of ReadReq MSHR uncacheable cycles +system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::total 681350371 # number of ReadReq MSHR uncacheable cycles +system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::cpu4 669996228 # number of WriteReq MSHR uncacheable cycles +system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::total 669996228 # number of WriteReq MSHR uncacheable cycles +system.cpu4.l1c.overall_mshr_uncacheable_latency::cpu4 1351346599 # number of overall MSHR uncacheable cycles +system.cpu4.l1c.overall_mshr_uncacheable_latency::total 1351346599 # number of overall MSHR uncacheable cycles +system.cpu4.l1c.ReadReq_mshr_miss_rate::cpu4 0.804586 # mshr miss rate for ReadReq accesses +system.cpu4.l1c.ReadReq_mshr_miss_rate::total 0.804586 # mshr miss rate for ReadReq accesses +system.cpu4.l1c.WriteReq_mshr_miss_rate::cpu4 0.957310 # mshr miss rate for WriteReq accesses +system.cpu4.l1c.WriteReq_mshr_miss_rate::total 0.957310 # mshr miss rate for WriteReq accesses +system.cpu4.l1c.demand_mshr_miss_rate::cpu4 0.858294 # mshr miss rate for demand accesses +system.cpu4.l1c.demand_mshr_miss_rate::total 0.858294 # mshr miss rate for demand accesses +system.cpu4.l1c.overall_mshr_miss_rate::cpu4 0.858294 # mshr miss rate for overall accesses +system.cpu4.l1c.overall_mshr_miss_rate::total 0.858294 # mshr miss rate for overall accesses +system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::cpu4 23988.608700 # average ReadReq mshr miss latency +system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::total 23988.608700 # average ReadReq mshr miss latency +system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::cpu4 34120.354640 # average WriteReq mshr miss latency +system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::total 34120.354640 # average WriteReq mshr miss latency +system.cpu4.l1c.demand_avg_mshr_miss_latency::cpu4 27962.620547 # average overall mshr miss latency +system.cpu4.l1c.demand_avg_mshr_miss_latency::total 27962.620547 # average overall mshr miss latency +system.cpu4.l1c.overall_avg_mshr_miss_latency::cpu4 27962.620547 # average overall mshr miss latency +system.cpu4.l1c.overall_avg_mshr_miss_latency::total 27962.620547 # average overall mshr miss latency system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu4 inf # average ReadReq mshr uncacheable latency system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu4 inf # average WriteReq mshr uncacheable latency @@ -1235,114 +1238,114 @@ system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::cpu4 inf # average overall mshr uncacheable latency system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu4.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu5.num_reads 98755 # number of read accesses completed -system.cpu5.num_writes 53000 # number of write accesses completed +system.cpu5.num_reads 99523 # number of read accesses completed +system.cpu5.num_writes 53948 # number of write accesses completed system.cpu5.num_copies 0 # number of copy accesses completed -system.cpu5.l1c.replacements 21964 # number of replacements -system.cpu5.l1c.tagsinuse 395.335157 # Cycle average of tags in use -system.cpu5.l1c.total_refs 13162 # Total number of references to valid blocks. -system.cpu5.l1c.sampled_refs 22364 # Sample count of references to valid blocks. -system.cpu5.l1c.avg_refs 0.588535 # Average number of references to valid blocks. +system.cpu5.l1c.replacements 22088 # number of replacements +system.cpu5.l1c.tagsinuse 397.555659 # Cycle average of tags in use +system.cpu5.l1c.total_refs 13442 # Total number of references to valid blocks. +system.cpu5.l1c.sampled_refs 22486 # Sample count of references to valid blocks. +system.cpu5.l1c.avg_refs 0.597794 # Average number of references to valid blocks. system.cpu5.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu5.l1c.occ_blocks::cpu5 395.335157 # Average occupied blocks per requestor -system.cpu5.l1c.occ_percent::cpu5 0.772139 # Average percentage of cache occupancy -system.cpu5.l1c.occ_percent::total 0.772139 # Average percentage of cache occupancy -system.cpu5.l1c.ReadReq_hits::cpu5 8580 # number of ReadReq hits -system.cpu5.l1c.ReadReq_hits::total 8580 # number of ReadReq hits -system.cpu5.l1c.WriteReq_hits::cpu5 1063 # number of WriteReq hits -system.cpu5.l1c.WriteReq_hits::total 1063 # number of WriteReq hits -system.cpu5.l1c.demand_hits::cpu5 9643 # number of demand (read+write) hits -system.cpu5.l1c.demand_hits::total 9643 # number of demand (read+write) hits -system.cpu5.l1c.overall_hits::cpu5 9643 # number of overall hits -system.cpu5.l1c.overall_hits::total 9643 # number of overall hits -system.cpu5.l1c.ReadReq_misses::cpu5 36060 # number of ReadReq misses -system.cpu5.l1c.ReadReq_misses::total 36060 # number of ReadReq misses -system.cpu5.l1c.WriteReq_misses::cpu5 22989 # number of WriteReq misses -system.cpu5.l1c.WriteReq_misses::total 22989 # number of WriteReq misses -system.cpu5.l1c.demand_misses::cpu5 59049 # number of demand (read+write) misses -system.cpu5.l1c.demand_misses::total 59049 # number of demand (read+write) misses -system.cpu5.l1c.overall_misses::cpu5 59049 # number of overall misses -system.cpu5.l1c.overall_misses::total 59049 # number of overall misses -system.cpu5.l1c.ReadReq_miss_latency::cpu5 944228607 # number of ReadReq miss cycles -system.cpu5.l1c.ReadReq_miss_latency::total 944228607 # number of ReadReq miss cycles -system.cpu5.l1c.WriteReq_miss_latency::cpu5 875107262 # number of WriteReq miss cycles -system.cpu5.l1c.WriteReq_miss_latency::total 875107262 # number of WriteReq miss cycles -system.cpu5.l1c.demand_miss_latency::cpu5 1819335869 # number of demand (read+write) miss cycles -system.cpu5.l1c.demand_miss_latency::total 1819335869 # number of demand (read+write) miss cycles -system.cpu5.l1c.overall_miss_latency::cpu5 1819335869 # number of overall miss cycles -system.cpu5.l1c.overall_miss_latency::total 1819335869 # number of overall miss cycles -system.cpu5.l1c.ReadReq_accesses::cpu5 44640 # number of ReadReq accesses(hits+misses) -system.cpu5.l1c.ReadReq_accesses::total 44640 # number of ReadReq accesses(hits+misses) -system.cpu5.l1c.WriteReq_accesses::cpu5 24052 # number of WriteReq accesses(hits+misses) -system.cpu5.l1c.WriteReq_accesses::total 24052 # number of WriteReq accesses(hits+misses) -system.cpu5.l1c.demand_accesses::cpu5 68692 # number of demand (read+write) accesses -system.cpu5.l1c.demand_accesses::total 68692 # number of demand (read+write) accesses -system.cpu5.l1c.overall_accesses::cpu5 68692 # number of overall (read+write) accesses -system.cpu5.l1c.overall_accesses::total 68692 # number of overall (read+write) accesses -system.cpu5.l1c.ReadReq_miss_rate::cpu5 0.807796 # miss rate for ReadReq accesses -system.cpu5.l1c.ReadReq_miss_rate::total 0.807796 # miss rate for ReadReq accesses -system.cpu5.l1c.WriteReq_miss_rate::cpu5 0.955804 # miss rate for WriteReq accesses -system.cpu5.l1c.WriteReq_miss_rate::total 0.955804 # miss rate for WriteReq accesses -system.cpu5.l1c.demand_miss_rate::cpu5 0.859620 # miss rate for demand accesses -system.cpu5.l1c.demand_miss_rate::total 0.859620 # miss rate for demand accesses -system.cpu5.l1c.overall_miss_rate::cpu5 0.859620 # miss rate for overall accesses -system.cpu5.l1c.overall_miss_rate::total 0.859620 # miss rate for overall accesses -system.cpu5.l1c.ReadReq_avg_miss_latency::cpu5 26184.930865 # average ReadReq miss latency -system.cpu5.l1c.ReadReq_avg_miss_latency::total 26184.930865 # average ReadReq miss latency -system.cpu5.l1c.WriteReq_avg_miss_latency::cpu5 38066.347471 # average WriteReq miss latency -system.cpu5.l1c.WriteReq_avg_miss_latency::total 38066.347471 # average WriteReq miss latency -system.cpu5.l1c.demand_avg_miss_latency::cpu5 30810.612695 # average overall miss latency -system.cpu5.l1c.demand_avg_miss_latency::total 30810.612695 # average overall miss latency -system.cpu5.l1c.overall_avg_miss_latency::cpu5 30810.612695 # average overall miss latency -system.cpu5.l1c.overall_avg_miss_latency::total 30810.612695 # average overall miss latency -system.cpu5.l1c.blocked_cycles::no_mshrs 213071792 # number of cycles access was blocked +system.cpu5.l1c.occ_blocks::cpu5 397.555659 # Average occupied blocks per requestor +system.cpu5.l1c.occ_percent::cpu5 0.776476 # Average percentage of cache occupancy +system.cpu5.l1c.occ_percent::total 0.776476 # Average percentage of cache occupancy +system.cpu5.l1c.ReadReq_hits::cpu5 8700 # number of ReadReq hits +system.cpu5.l1c.ReadReq_hits::total 8700 # number of ReadReq hits +system.cpu5.l1c.WriteReq_hits::cpu5 1066 # number of WriteReq hits +system.cpu5.l1c.WriteReq_hits::total 1066 # number of WriteReq hits +system.cpu5.l1c.demand_hits::cpu5 9766 # number of demand (read+write) hits +system.cpu5.l1c.demand_hits::total 9766 # number of demand (read+write) hits +system.cpu5.l1c.overall_hits::cpu5 9766 # number of overall hits +system.cpu5.l1c.overall_hits::total 9766 # number of overall hits +system.cpu5.l1c.ReadReq_misses::cpu5 36016 # number of ReadReq misses +system.cpu5.l1c.ReadReq_misses::total 36016 # number of ReadReq misses +system.cpu5.l1c.WriteReq_misses::cpu5 23333 # number of WriteReq misses +system.cpu5.l1c.WriteReq_misses::total 23333 # number of WriteReq misses +system.cpu5.l1c.demand_misses::cpu5 59349 # number of demand (read+write) misses +system.cpu5.l1c.demand_misses::total 59349 # number of demand (read+write) misses +system.cpu5.l1c.overall_misses::cpu5 59349 # number of overall misses +system.cpu5.l1c.overall_misses::total 59349 # number of overall misses +system.cpu5.l1c.ReadReq_miss_latency::cpu5 899040098 # number of ReadReq miss cycles +system.cpu5.l1c.ReadReq_miss_latency::total 899040098 # number of ReadReq miss cycles +system.cpu5.l1c.WriteReq_miss_latency::cpu5 826704780 # number of WriteReq miss cycles +system.cpu5.l1c.WriteReq_miss_latency::total 826704780 # number of WriteReq miss cycles +system.cpu5.l1c.demand_miss_latency::cpu5 1725744878 # number of demand (read+write) miss cycles +system.cpu5.l1c.demand_miss_latency::total 1725744878 # number of demand (read+write) miss cycles +system.cpu5.l1c.overall_miss_latency::cpu5 1725744878 # number of overall miss cycles +system.cpu5.l1c.overall_miss_latency::total 1725744878 # number of overall miss cycles +system.cpu5.l1c.ReadReq_accesses::cpu5 44716 # number of ReadReq accesses(hits+misses) +system.cpu5.l1c.ReadReq_accesses::total 44716 # number of ReadReq accesses(hits+misses) +system.cpu5.l1c.WriteReq_accesses::cpu5 24399 # number of WriteReq accesses(hits+misses) +system.cpu5.l1c.WriteReq_accesses::total 24399 # number of WriteReq accesses(hits+misses) +system.cpu5.l1c.demand_accesses::cpu5 69115 # number of demand (read+write) accesses +system.cpu5.l1c.demand_accesses::total 69115 # number of demand (read+write) accesses +system.cpu5.l1c.overall_accesses::cpu5 69115 # number of overall (read+write) accesses +system.cpu5.l1c.overall_accesses::total 69115 # number of overall (read+write) accesses +system.cpu5.l1c.ReadReq_miss_rate::cpu5 0.805439 # miss rate for ReadReq accesses +system.cpu5.l1c.ReadReq_miss_rate::total 0.805439 # miss rate for ReadReq accesses +system.cpu5.l1c.WriteReq_miss_rate::cpu5 0.956310 # miss rate for WriteReq accesses +system.cpu5.l1c.WriteReq_miss_rate::total 0.956310 # miss rate for WriteReq accesses +system.cpu5.l1c.demand_miss_rate::cpu5 0.858699 # miss rate for demand accesses +system.cpu5.l1c.demand_miss_rate::total 0.858699 # miss rate for demand accesses +system.cpu5.l1c.overall_miss_rate::cpu5 0.858699 # miss rate for overall accesses +system.cpu5.l1c.overall_miss_rate::total 0.858699 # miss rate for overall accesses +system.cpu5.l1c.ReadReq_avg_miss_latency::cpu5 24962.241726 # average ReadReq miss latency +system.cpu5.l1c.ReadReq_avg_miss_latency::total 24962.241726 # average ReadReq miss latency +system.cpu5.l1c.WriteReq_avg_miss_latency::cpu5 35430.711010 # average WriteReq miss latency +system.cpu5.l1c.WriteReq_avg_miss_latency::total 35430.711010 # average WriteReq miss latency +system.cpu5.l1c.demand_avg_miss_latency::cpu5 29077.909956 # average overall miss latency +system.cpu5.l1c.demand_avg_miss_latency::total 29077.909956 # average overall miss latency +system.cpu5.l1c.overall_avg_miss_latency::cpu5 29077.909956 # average overall miss latency +system.cpu5.l1c.overall_avg_miss_latency::total 29077.909956 # average overall miss latency +system.cpu5.l1c.blocked_cycles::no_mshrs 155795508 # number of cycles access was blocked system.cpu5.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu5.l1c.blocked::no_mshrs 67023 # number of cycles access was blocked +system.cpu5.l1c.blocked::no_mshrs 53352 # number of cycles access was blocked system.cpu5.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu5.l1c.avg_blocked_cycles::no_mshrs 3179.084672 # average number of cycles each access was blocked +system.cpu5.l1c.avg_blocked_cycles::no_mshrs 2920.143725 # average number of cycles each access was blocked system.cpu5.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu5.l1c.fast_writes 0 # number of fast writes performed system.cpu5.l1c.cache_copies 0 # number of cache copies performed -system.cpu5.l1c.writebacks::writebacks 9605 # number of writebacks -system.cpu5.l1c.writebacks::total 9605 # number of writebacks -system.cpu5.l1c.ReadReq_mshr_misses::cpu5 36060 # number of ReadReq MSHR misses -system.cpu5.l1c.ReadReq_mshr_misses::total 36060 # number of ReadReq MSHR misses -system.cpu5.l1c.WriteReq_mshr_misses::cpu5 22989 # number of WriteReq MSHR misses -system.cpu5.l1c.WriteReq_mshr_misses::total 22989 # number of WriteReq MSHR misses -system.cpu5.l1c.demand_mshr_misses::cpu5 59049 # number of demand (read+write) MSHR misses -system.cpu5.l1c.demand_mshr_misses::total 59049 # number of demand (read+write) MSHR misses -system.cpu5.l1c.overall_mshr_misses::cpu5 59049 # number of overall MSHR misses -system.cpu5.l1c.overall_mshr_misses::total 59049 # number of overall MSHR misses -system.cpu5.l1c.ReadReq_mshr_miss_latency::cpu5 908030320 # number of ReadReq MSHR miss cycles -system.cpu5.l1c.ReadReq_mshr_miss_latency::total 908030320 # number of ReadReq MSHR miss cycles -system.cpu5.l1c.WriteReq_mshr_miss_latency::cpu5 852027269 # number of WriteReq MSHR miss cycles -system.cpu5.l1c.WriteReq_mshr_miss_latency::total 852027269 # number of WriteReq MSHR miss cycles -system.cpu5.l1c.demand_mshr_miss_latency::cpu5 1760057589 # number of demand (read+write) MSHR miss cycles -system.cpu5.l1c.demand_mshr_miss_latency::total 1760057589 # number of demand (read+write) MSHR miss cycles -system.cpu5.l1c.overall_mshr_miss_latency::cpu5 1760057589 # number of overall MSHR miss cycles -system.cpu5.l1c.overall_mshr_miss_latency::total 1760057589 # number of overall MSHR miss cycles -system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::cpu5 893562759 # number of ReadReq MSHR uncacheable cycles -system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::total 893562759 # number of ReadReq MSHR uncacheable cycles -system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::cpu5 567489251 # number of WriteReq MSHR uncacheable cycles -system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::total 567489251 # number of WriteReq MSHR uncacheable cycles -system.cpu5.l1c.overall_mshr_uncacheable_latency::cpu5 1461052010 # number of overall MSHR uncacheable cycles -system.cpu5.l1c.overall_mshr_uncacheable_latency::total 1461052010 # number of overall MSHR uncacheable cycles -system.cpu5.l1c.ReadReq_mshr_miss_rate::cpu5 0.807796 # mshr miss rate for ReadReq accesses -system.cpu5.l1c.ReadReq_mshr_miss_rate::total 0.807796 # mshr miss rate for ReadReq accesses -system.cpu5.l1c.WriteReq_mshr_miss_rate::cpu5 0.955804 # mshr miss rate for WriteReq accesses -system.cpu5.l1c.WriteReq_mshr_miss_rate::total 0.955804 # mshr miss rate for WriteReq accesses -system.cpu5.l1c.demand_mshr_miss_rate::cpu5 0.859620 # mshr miss rate for demand accesses -system.cpu5.l1c.demand_mshr_miss_rate::total 0.859620 # mshr miss rate for demand accesses -system.cpu5.l1c.overall_mshr_miss_rate::cpu5 0.859620 # mshr miss rate for overall accesses -system.cpu5.l1c.overall_mshr_miss_rate::total 0.859620 # mshr miss rate for overall accesses -system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::cpu5 25181.095951 # average ReadReq mshr miss latency -system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::total 25181.095951 # average ReadReq mshr miss latency -system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::cpu5 37062.389360 # average WriteReq mshr miss latency -system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::total 37062.389360 # average WriteReq mshr miss latency -system.cpu5.l1c.demand_avg_mshr_miss_latency::cpu5 29806.729818 # average overall mshr miss latency -system.cpu5.l1c.demand_avg_mshr_miss_latency::total 29806.729818 # average overall mshr miss latency -system.cpu5.l1c.overall_avg_mshr_miss_latency::cpu5 29806.729818 # average overall mshr miss latency -system.cpu5.l1c.overall_avg_mshr_miss_latency::total 29806.729818 # average overall mshr miss latency +system.cpu5.l1c.writebacks::writebacks 9610 # number of writebacks +system.cpu5.l1c.writebacks::total 9610 # number of writebacks +system.cpu5.l1c.ReadReq_mshr_misses::cpu5 36016 # number of ReadReq MSHR misses +system.cpu5.l1c.ReadReq_mshr_misses::total 36016 # number of ReadReq MSHR misses +system.cpu5.l1c.WriteReq_mshr_misses::cpu5 23333 # number of WriteReq MSHR misses +system.cpu5.l1c.WriteReq_mshr_misses::total 23333 # number of WriteReq MSHR misses +system.cpu5.l1c.demand_mshr_misses::cpu5 59349 # number of demand (read+write) MSHR misses +system.cpu5.l1c.demand_mshr_misses::total 59349 # number of demand (read+write) MSHR misses +system.cpu5.l1c.overall_mshr_misses::cpu5 59349 # number of overall MSHR misses +system.cpu5.l1c.overall_mshr_misses::total 59349 # number of overall MSHR misses +system.cpu5.l1c.ReadReq_mshr_miss_latency::cpu5 862885041 # number of ReadReq MSHR miss cycles +system.cpu5.l1c.ReadReq_mshr_miss_latency::total 862885041 # number of ReadReq MSHR miss cycles +system.cpu5.l1c.WriteReq_mshr_miss_latency::cpu5 803284460 # number of WriteReq MSHR miss cycles +system.cpu5.l1c.WriteReq_mshr_miss_latency::total 803284460 # number of WriteReq MSHR miss cycles +system.cpu5.l1c.demand_mshr_miss_latency::cpu5 1666169501 # number of demand (read+write) MSHR miss cycles +system.cpu5.l1c.demand_mshr_miss_latency::total 1666169501 # number of demand (read+write) MSHR miss cycles +system.cpu5.l1c.overall_mshr_miss_latency::cpu5 1666169501 # number of overall MSHR miss cycles +system.cpu5.l1c.overall_mshr_miss_latency::total 1666169501 # number of overall MSHR miss cycles +system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::cpu5 674425818 # number of ReadReq MSHR uncacheable cycles +system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::total 674425818 # number of ReadReq MSHR uncacheable cycles +system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::cpu5 675374924 # number of WriteReq MSHR uncacheable cycles +system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::total 675374924 # number of WriteReq MSHR uncacheable cycles +system.cpu5.l1c.overall_mshr_uncacheable_latency::cpu5 1349800742 # number of overall MSHR uncacheable cycles +system.cpu5.l1c.overall_mshr_uncacheable_latency::total 1349800742 # number of overall MSHR uncacheable cycles +system.cpu5.l1c.ReadReq_mshr_miss_rate::cpu5 0.805439 # mshr miss rate for ReadReq accesses +system.cpu5.l1c.ReadReq_mshr_miss_rate::total 0.805439 # mshr miss rate for ReadReq accesses +system.cpu5.l1c.WriteReq_mshr_miss_rate::cpu5 0.956310 # mshr miss rate for WriteReq accesses +system.cpu5.l1c.WriteReq_mshr_miss_rate::total 0.956310 # mshr miss rate for WriteReq accesses +system.cpu5.l1c.demand_mshr_miss_rate::cpu5 0.858699 # mshr miss rate for demand accesses +system.cpu5.l1c.demand_mshr_miss_rate::total 0.858699 # mshr miss rate for demand accesses +system.cpu5.l1c.overall_mshr_miss_rate::cpu5 0.858699 # mshr miss rate for overall accesses +system.cpu5.l1c.overall_mshr_miss_rate::total 0.858699 # mshr miss rate for overall accesses +system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::cpu5 23958.380747 # average ReadReq mshr miss latency +system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::total 23958.380747 # average ReadReq mshr miss latency +system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::cpu5 34426.968671 # average WriteReq mshr miss latency +system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::total 34426.968671 # average WriteReq mshr miss latency +system.cpu5.l1c.demand_avg_mshr_miss_latency::cpu5 28074.095621 # average overall mshr miss latency +system.cpu5.l1c.demand_avg_mshr_miss_latency::total 28074.095621 # average overall mshr miss latency +system.cpu5.l1c.overall_avg_mshr_miss_latency::cpu5 28074.095621 # average overall mshr miss latency +system.cpu5.l1c.overall_avg_mshr_miss_latency::total 28074.095621 # average overall mshr miss latency system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu5 inf # average ReadReq mshr uncacheable latency system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu5 inf # average WriteReq mshr uncacheable latency @@ -1350,114 +1353,114 @@ system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::cpu5 inf # average overall mshr uncacheable latency system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu5.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu6.num_reads 99515 # number of read accesses completed -system.cpu6.num_writes 53091 # number of write accesses completed +system.cpu6.num_reads 100000 # number of read accesses completed +system.cpu6.num_writes 53510 # number of write accesses completed system.cpu6.num_copies 0 # number of copy accesses completed -system.cpu6.l1c.replacements 21875 # number of replacements -system.cpu6.l1c.tagsinuse 395.073790 # Cycle average of tags in use -system.cpu6.l1c.total_refs 13163 # Total number of references to valid blocks. -system.cpu6.l1c.sampled_refs 22301 # Sample count of references to valid blocks. -system.cpu6.l1c.avg_refs 0.590243 # Average number of references to valid blocks. +system.cpu6.l1c.replacements 22177 # number of replacements +system.cpu6.l1c.tagsinuse 397.660479 # Cycle average of tags in use +system.cpu6.l1c.total_refs 13364 # Total number of references to valid blocks. +system.cpu6.l1c.sampled_refs 22573 # Sample count of references to valid blocks. +system.cpu6.l1c.avg_refs 0.592035 # Average number of references to valid blocks. system.cpu6.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu6.l1c.occ_blocks::cpu6 395.073790 # Average occupied blocks per requestor -system.cpu6.l1c.occ_percent::cpu6 0.771628 # Average percentage of cache occupancy -system.cpu6.l1c.occ_percent::total 0.771628 # Average percentage of cache occupancy -system.cpu6.l1c.ReadReq_hits::cpu6 8660 # number of ReadReq hits -system.cpu6.l1c.ReadReq_hits::total 8660 # number of ReadReq hits -system.cpu6.l1c.WriteReq_hits::cpu6 1070 # number of WriteReq hits -system.cpu6.l1c.WriteReq_hits::total 1070 # number of WriteReq hits -system.cpu6.l1c.demand_hits::cpu6 9730 # number of demand (read+write) hits -system.cpu6.l1c.demand_hits::total 9730 # number of demand (read+write) hits -system.cpu6.l1c.overall_hits::cpu6 9730 # number of overall hits -system.cpu6.l1c.overall_hits::total 9730 # number of overall hits -system.cpu6.l1c.ReadReq_misses::cpu6 36079 # number of ReadReq misses -system.cpu6.l1c.ReadReq_misses::total 36079 # number of ReadReq misses -system.cpu6.l1c.WriteReq_misses::cpu6 22730 # number of WriteReq misses -system.cpu6.l1c.WriteReq_misses::total 22730 # number of WriteReq misses -system.cpu6.l1c.demand_misses::cpu6 58809 # number of demand (read+write) misses -system.cpu6.l1c.demand_misses::total 58809 # number of demand (read+write) misses -system.cpu6.l1c.overall_misses::cpu6 58809 # number of overall misses -system.cpu6.l1c.overall_misses::total 58809 # number of overall misses -system.cpu6.l1c.ReadReq_miss_latency::cpu6 942403765 # number of ReadReq miss cycles -system.cpu6.l1c.ReadReq_miss_latency::total 942403765 # number of ReadReq miss cycles -system.cpu6.l1c.WriteReq_miss_latency::cpu6 866225957 # number of WriteReq miss cycles -system.cpu6.l1c.WriteReq_miss_latency::total 866225957 # number of WriteReq miss cycles -system.cpu6.l1c.demand_miss_latency::cpu6 1808629722 # number of demand (read+write) miss cycles -system.cpu6.l1c.demand_miss_latency::total 1808629722 # number of demand (read+write) miss cycles -system.cpu6.l1c.overall_miss_latency::cpu6 1808629722 # number of overall miss cycles -system.cpu6.l1c.overall_miss_latency::total 1808629722 # number of overall miss cycles -system.cpu6.l1c.ReadReq_accesses::cpu6 44739 # number of ReadReq accesses(hits+misses) -system.cpu6.l1c.ReadReq_accesses::total 44739 # number of ReadReq accesses(hits+misses) -system.cpu6.l1c.WriteReq_accesses::cpu6 23800 # number of WriteReq accesses(hits+misses) -system.cpu6.l1c.WriteReq_accesses::total 23800 # number of WriteReq accesses(hits+misses) -system.cpu6.l1c.demand_accesses::cpu6 68539 # number of demand (read+write) accesses -system.cpu6.l1c.demand_accesses::total 68539 # number of demand (read+write) accesses -system.cpu6.l1c.overall_accesses::cpu6 68539 # number of overall (read+write) accesses -system.cpu6.l1c.overall_accesses::total 68539 # number of overall (read+write) accesses -system.cpu6.l1c.ReadReq_miss_rate::cpu6 0.806433 # miss rate for ReadReq accesses -system.cpu6.l1c.ReadReq_miss_rate::total 0.806433 # miss rate for ReadReq accesses -system.cpu6.l1c.WriteReq_miss_rate::cpu6 0.955042 # miss rate for WriteReq accesses -system.cpu6.l1c.WriteReq_miss_rate::total 0.955042 # miss rate for WriteReq accesses -system.cpu6.l1c.demand_miss_rate::cpu6 0.858037 # miss rate for demand accesses -system.cpu6.l1c.demand_miss_rate::total 0.858037 # miss rate for demand accesses -system.cpu6.l1c.overall_miss_rate::cpu6 0.858037 # miss rate for overall accesses -system.cpu6.l1c.overall_miss_rate::total 0.858037 # miss rate for overall accesses -system.cpu6.l1c.ReadReq_avg_miss_latency::cpu6 26120.562238 # average ReadReq miss latency -system.cpu6.l1c.ReadReq_avg_miss_latency::total 26120.562238 # average ReadReq miss latency -system.cpu6.l1c.WriteReq_avg_miss_latency::cpu6 38109.368984 # average WriteReq miss latency -system.cpu6.l1c.WriteReq_avg_miss_latency::total 38109.368984 # average WriteReq miss latency -system.cpu6.l1c.demand_avg_miss_latency::cpu6 30754.301586 # average overall miss latency -system.cpu6.l1c.demand_avg_miss_latency::total 30754.301586 # average overall miss latency -system.cpu6.l1c.overall_avg_miss_latency::cpu6 30754.301586 # average overall miss latency -system.cpu6.l1c.overall_avg_miss_latency::total 30754.301586 # average overall miss latency -system.cpu6.l1c.blocked_cycles::no_mshrs 212806358 # number of cycles access was blocked +system.cpu6.l1c.occ_blocks::cpu6 397.660479 # Average occupied blocks per requestor +system.cpu6.l1c.occ_percent::cpu6 0.776681 # Average percentage of cache occupancy +system.cpu6.l1c.occ_percent::total 0.776681 # Average percentage of cache occupancy +system.cpu6.l1c.ReadReq_hits::cpu6 8760 # number of ReadReq hits +system.cpu6.l1c.ReadReq_hits::total 8760 # number of ReadReq hits +system.cpu6.l1c.WriteReq_hits::cpu6 1035 # number of WriteReq hits +system.cpu6.l1c.WriteReq_hits::total 1035 # number of WriteReq hits +system.cpu6.l1c.demand_hits::cpu6 9795 # number of demand (read+write) hits +system.cpu6.l1c.demand_hits::total 9795 # number of demand (read+write) hits +system.cpu6.l1c.overall_hits::cpu6 9795 # number of overall hits +system.cpu6.l1c.overall_hits::total 9795 # number of overall hits +system.cpu6.l1c.ReadReq_misses::cpu6 36279 # number of ReadReq misses +system.cpu6.l1c.ReadReq_misses::total 36279 # number of ReadReq misses +system.cpu6.l1c.WriteReq_misses::cpu6 23033 # number of WriteReq misses +system.cpu6.l1c.WriteReq_misses::total 23033 # number of WriteReq misses +system.cpu6.l1c.demand_misses::cpu6 59312 # number of demand (read+write) misses +system.cpu6.l1c.demand_misses::total 59312 # number of demand (read+write) misses +system.cpu6.l1c.overall_misses::cpu6 59312 # number of overall misses +system.cpu6.l1c.overall_misses::total 59312 # number of overall misses +system.cpu6.l1c.ReadReq_miss_latency::cpu6 908517794 # number of ReadReq miss cycles +system.cpu6.l1c.ReadReq_miss_latency::total 908517794 # number of ReadReq miss cycles +system.cpu6.l1c.WriteReq_miss_latency::cpu6 809582336 # number of WriteReq miss cycles +system.cpu6.l1c.WriteReq_miss_latency::total 809582336 # number of WriteReq miss cycles +system.cpu6.l1c.demand_miss_latency::cpu6 1718100130 # number of demand (read+write) miss cycles +system.cpu6.l1c.demand_miss_latency::total 1718100130 # number of demand (read+write) miss cycles +system.cpu6.l1c.overall_miss_latency::cpu6 1718100130 # number of overall miss cycles +system.cpu6.l1c.overall_miss_latency::total 1718100130 # number of overall miss cycles +system.cpu6.l1c.ReadReq_accesses::cpu6 45039 # number of ReadReq accesses(hits+misses) +system.cpu6.l1c.ReadReq_accesses::total 45039 # number of ReadReq accesses(hits+misses) +system.cpu6.l1c.WriteReq_accesses::cpu6 24068 # number of WriteReq accesses(hits+misses) +system.cpu6.l1c.WriteReq_accesses::total 24068 # number of WriteReq accesses(hits+misses) +system.cpu6.l1c.demand_accesses::cpu6 69107 # number of demand (read+write) accesses +system.cpu6.l1c.demand_accesses::total 69107 # number of demand (read+write) accesses +system.cpu6.l1c.overall_accesses::cpu6 69107 # number of overall (read+write) accesses +system.cpu6.l1c.overall_accesses::total 69107 # number of overall (read+write) accesses +system.cpu6.l1c.ReadReq_miss_rate::cpu6 0.805502 # miss rate for ReadReq accesses +system.cpu6.l1c.ReadReq_miss_rate::total 0.805502 # miss rate for ReadReq accesses +system.cpu6.l1c.WriteReq_miss_rate::cpu6 0.956997 # miss rate for WriteReq accesses +system.cpu6.l1c.WriteReq_miss_rate::total 0.956997 # miss rate for WriteReq accesses +system.cpu6.l1c.demand_miss_rate::cpu6 0.858263 # miss rate for demand accesses +system.cpu6.l1c.demand_miss_rate::total 0.858263 # miss rate for demand accesses +system.cpu6.l1c.overall_miss_rate::cpu6 0.858263 # miss rate for overall accesses +system.cpu6.l1c.overall_miss_rate::total 0.858263 # miss rate for overall accesses +system.cpu6.l1c.ReadReq_avg_miss_latency::cpu6 25042.525814 # average ReadReq miss latency +system.cpu6.l1c.ReadReq_avg_miss_latency::total 25042.525814 # average ReadReq miss latency +system.cpu6.l1c.WriteReq_avg_miss_latency::cpu6 35148.801111 # average WriteReq miss latency +system.cpu6.l1c.WriteReq_avg_miss_latency::total 35148.801111 # average WriteReq miss latency +system.cpu6.l1c.demand_avg_miss_latency::cpu6 28967.158922 # average overall miss latency +system.cpu6.l1c.demand_avg_miss_latency::total 28967.158922 # average overall miss latency +system.cpu6.l1c.overall_avg_miss_latency::cpu6 28967.158922 # average overall miss latency +system.cpu6.l1c.overall_avg_miss_latency::total 28967.158922 # average overall miss latency +system.cpu6.l1c.blocked_cycles::no_mshrs 154185284 # number of cycles access was blocked system.cpu6.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu6.l1c.blocked::no_mshrs 66914 # number of cycles access was blocked +system.cpu6.l1c.blocked::no_mshrs 52977 # number of cycles access was blocked system.cpu6.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu6.l1c.avg_blocked_cycles::no_mshrs 3180.296470 # average number of cycles each access was blocked +system.cpu6.l1c.avg_blocked_cycles::no_mshrs 2910.419314 # average number of cycles each access was blocked system.cpu6.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu6.l1c.fast_writes 0 # number of fast writes performed system.cpu6.l1c.cache_copies 0 # number of cache copies performed -system.cpu6.l1c.writebacks::writebacks 9438 # number of writebacks -system.cpu6.l1c.writebacks::total 9438 # number of writebacks -system.cpu6.l1c.ReadReq_mshr_misses::cpu6 36079 # number of ReadReq MSHR misses -system.cpu6.l1c.ReadReq_mshr_misses::total 36079 # number of ReadReq MSHR misses -system.cpu6.l1c.WriteReq_mshr_misses::cpu6 22730 # number of WriteReq MSHR misses -system.cpu6.l1c.WriteReq_mshr_misses::total 22730 # number of WriteReq MSHR misses -system.cpu6.l1c.demand_mshr_misses::cpu6 58809 # number of demand (read+write) MSHR misses -system.cpu6.l1c.demand_mshr_misses::total 58809 # number of demand (read+write) MSHR misses -system.cpu6.l1c.overall_mshr_misses::cpu6 58809 # number of overall MSHR misses -system.cpu6.l1c.overall_mshr_misses::total 58809 # number of overall MSHR misses -system.cpu6.l1c.ReadReq_mshr_miss_latency::cpu6 906189412 # number of ReadReq MSHR miss cycles -system.cpu6.l1c.ReadReq_mshr_miss_latency::total 906189412 # number of ReadReq MSHR miss cycles -system.cpu6.l1c.WriteReq_mshr_miss_latency::cpu6 843405989 # number of WriteReq MSHR miss cycles -system.cpu6.l1c.WriteReq_mshr_miss_latency::total 843405989 # number of WriteReq MSHR miss cycles -system.cpu6.l1c.demand_mshr_miss_latency::cpu6 1749595401 # number of demand (read+write) MSHR miss cycles -system.cpu6.l1c.demand_mshr_miss_latency::total 1749595401 # number of demand (read+write) MSHR miss cycles -system.cpu6.l1c.overall_mshr_miss_latency::cpu6 1749595401 # number of overall MSHR miss cycles -system.cpu6.l1c.overall_mshr_miss_latency::total 1749595401 # number of overall MSHR miss cycles -system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::cpu6 905213986 # number of ReadReq MSHR uncacheable cycles -system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::total 905213986 # number of ReadReq MSHR uncacheable cycles -system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::cpu6 576398345 # number of WriteReq MSHR uncacheable cycles -system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::total 576398345 # number of WriteReq MSHR uncacheable cycles -system.cpu6.l1c.overall_mshr_uncacheable_latency::cpu6 1481612331 # number of overall MSHR uncacheable cycles -system.cpu6.l1c.overall_mshr_uncacheable_latency::total 1481612331 # number of overall MSHR uncacheable cycles -system.cpu6.l1c.ReadReq_mshr_miss_rate::cpu6 0.806433 # mshr miss rate for ReadReq accesses -system.cpu6.l1c.ReadReq_mshr_miss_rate::total 0.806433 # mshr miss rate for ReadReq accesses -system.cpu6.l1c.WriteReq_mshr_miss_rate::cpu6 0.955042 # mshr miss rate for WriteReq accesses -system.cpu6.l1c.WriteReq_mshr_miss_rate::total 0.955042 # mshr miss rate for WriteReq accesses -system.cpu6.l1c.demand_mshr_miss_rate::cpu6 0.858037 # mshr miss rate for demand accesses -system.cpu6.l1c.demand_mshr_miss_rate::total 0.858037 # mshr miss rate for demand accesses -system.cpu6.l1c.overall_mshr_miss_rate::cpu6 0.858037 # mshr miss rate for overall accesses -system.cpu6.l1c.overall_mshr_miss_rate::total 0.858037 # mshr miss rate for overall accesses -system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::cpu6 25116.810665 # average ReadReq mshr miss latency -system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::total 25116.810665 # average ReadReq mshr miss latency -system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::cpu6 37105.410867 # average WriteReq mshr miss latency -system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::total 37105.410867 # average WriteReq mshr miss latency -system.cpu6.l1c.demand_avg_mshr_miss_latency::cpu6 29750.470183 # average overall mshr miss latency -system.cpu6.l1c.demand_avg_mshr_miss_latency::total 29750.470183 # average overall mshr miss latency -system.cpu6.l1c.overall_avg_mshr_miss_latency::cpu6 29750.470183 # average overall mshr miss latency -system.cpu6.l1c.overall_avg_mshr_miss_latency::total 29750.470183 # average overall mshr miss latency +system.cpu6.l1c.writebacks::writebacks 9564 # number of writebacks +system.cpu6.l1c.writebacks::total 9564 # number of writebacks +system.cpu6.l1c.ReadReq_mshr_misses::cpu6 36279 # number of ReadReq MSHR misses +system.cpu6.l1c.ReadReq_mshr_misses::total 36279 # number of ReadReq MSHR misses +system.cpu6.l1c.WriteReq_mshr_misses::cpu6 23033 # number of WriteReq MSHR misses +system.cpu6.l1c.WriteReq_mshr_misses::total 23033 # number of WriteReq MSHR misses +system.cpu6.l1c.demand_mshr_misses::cpu6 59312 # number of demand (read+write) MSHR misses +system.cpu6.l1c.demand_mshr_misses::total 59312 # number of demand (read+write) MSHR misses +system.cpu6.l1c.overall_mshr_misses::cpu6 59312 # number of overall MSHR misses +system.cpu6.l1c.overall_mshr_misses::total 59312 # number of overall MSHR misses +system.cpu6.l1c.ReadReq_mshr_miss_latency::cpu6 872097671 # number of ReadReq MSHR miss cycles +system.cpu6.l1c.ReadReq_mshr_miss_latency::total 872097671 # number of ReadReq MSHR miss cycles +system.cpu6.l1c.WriteReq_mshr_miss_latency::cpu6 786461211 # number of WriteReq MSHR miss cycles +system.cpu6.l1c.WriteReq_mshr_miss_latency::total 786461211 # number of WriteReq MSHR miss cycles +system.cpu6.l1c.demand_mshr_miss_latency::cpu6 1658558882 # number of demand (read+write) MSHR miss cycles +system.cpu6.l1c.demand_mshr_miss_latency::total 1658558882 # number of demand (read+write) MSHR miss cycles +system.cpu6.l1c.overall_mshr_miss_latency::cpu6 1658558882 # number of overall MSHR miss cycles +system.cpu6.l1c.overall_mshr_miss_latency::total 1658558882 # number of overall MSHR miss cycles +system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::cpu6 680107967 # number of ReadReq MSHR uncacheable cycles +system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::total 680107967 # number of ReadReq MSHR uncacheable cycles +system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::cpu6 681972539 # number of WriteReq MSHR uncacheable cycles +system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::total 681972539 # number of WriteReq MSHR uncacheable cycles +system.cpu6.l1c.overall_mshr_uncacheable_latency::cpu6 1362080506 # number of overall MSHR uncacheable cycles +system.cpu6.l1c.overall_mshr_uncacheable_latency::total 1362080506 # number of overall MSHR uncacheable cycles +system.cpu6.l1c.ReadReq_mshr_miss_rate::cpu6 0.805502 # mshr miss rate for ReadReq accesses +system.cpu6.l1c.ReadReq_mshr_miss_rate::total 0.805502 # mshr miss rate for ReadReq accesses +system.cpu6.l1c.WriteReq_mshr_miss_rate::cpu6 0.956997 # mshr miss rate for WriteReq accesses +system.cpu6.l1c.WriteReq_mshr_miss_rate::total 0.956997 # mshr miss rate for WriteReq accesses +system.cpu6.l1c.demand_mshr_miss_rate::cpu6 0.858263 # mshr miss rate for demand accesses +system.cpu6.l1c.demand_mshr_miss_rate::total 0.858263 # mshr miss rate for demand accesses +system.cpu6.l1c.overall_mshr_miss_rate::cpu6 0.858263 # mshr miss rate for overall accesses +system.cpu6.l1c.overall_mshr_miss_rate::total 0.858263 # mshr miss rate for overall accesses +system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::cpu6 24038.635878 # average ReadReq mshr miss latency +system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::total 24038.635878 # average ReadReq mshr miss latency +system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::cpu6 34144.975079 # average WriteReq mshr miss latency +system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::total 34144.975079 # average WriteReq mshr miss latency +system.cpu6.l1c.demand_avg_mshr_miss_latency::cpu6 27963.293802 # average overall mshr miss latency +system.cpu6.l1c.demand_avg_mshr_miss_latency::total 27963.293802 # average overall mshr miss latency +system.cpu6.l1c.overall_avg_mshr_miss_latency::cpu6 27963.293802 # average overall mshr miss latency +system.cpu6.l1c.overall_avg_mshr_miss_latency::total 27963.293802 # average overall mshr miss latency system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu6 inf # average ReadReq mshr uncacheable latency system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu6 inf # average WriteReq mshr uncacheable latency @@ -1465,114 +1468,114 @@ system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::cpu6 inf # average overall mshr uncacheable latency system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu6.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu7.num_reads 98608 # number of read accesses completed -system.cpu7.num_writes 53688 # number of write accesses completed +system.cpu7.num_reads 99201 # number of read accesses completed +system.cpu7.num_writes 53497 # number of write accesses completed system.cpu7.num_copies 0 # number of copy accesses completed -system.cpu7.l1c.replacements 21767 # number of replacements -system.cpu7.l1c.tagsinuse 394.473547 # Cycle average of tags in use -system.cpu7.l1c.total_refs 13199 # Total number of references to valid blocks. -system.cpu7.l1c.sampled_refs 22171 # Sample count of references to valid blocks. -system.cpu7.l1c.avg_refs 0.595327 # Average number of references to valid blocks. +system.cpu7.l1c.replacements 22218 # number of replacements +system.cpu7.l1c.tagsinuse 396.828031 # Cycle average of tags in use +system.cpu7.l1c.total_refs 13271 # Total number of references to valid blocks. +system.cpu7.l1c.sampled_refs 22622 # Sample count of references to valid blocks. +system.cpu7.l1c.avg_refs 0.586641 # Average number of references to valid blocks. system.cpu7.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu7.l1c.occ_blocks::cpu7 394.473547 # Average occupied blocks per requestor -system.cpu7.l1c.occ_percent::cpu7 0.770456 # Average percentage of cache occupancy -system.cpu7.l1c.occ_percent::total 0.770456 # Average percentage of cache occupancy -system.cpu7.l1c.ReadReq_hits::cpu7 8649 # number of ReadReq hits -system.cpu7.l1c.ReadReq_hits::total 8649 # number of ReadReq hits -system.cpu7.l1c.WriteReq_hits::cpu7 995 # number of WriteReq hits -system.cpu7.l1c.WriteReq_hits::total 995 # number of WriteReq hits -system.cpu7.l1c.demand_hits::cpu7 9644 # number of demand (read+write) hits -system.cpu7.l1c.demand_hits::total 9644 # number of demand (read+write) hits -system.cpu7.l1c.overall_hits::cpu7 9644 # number of overall hits -system.cpu7.l1c.overall_hits::total 9644 # number of overall hits -system.cpu7.l1c.ReadReq_misses::cpu7 35884 # number of ReadReq misses -system.cpu7.l1c.ReadReq_misses::total 35884 # number of ReadReq misses -system.cpu7.l1c.WriteReq_misses::cpu7 23099 # number of WriteReq misses -system.cpu7.l1c.WriteReq_misses::total 23099 # number of WriteReq misses -system.cpu7.l1c.demand_misses::cpu7 58983 # number of demand (read+write) misses -system.cpu7.l1c.demand_misses::total 58983 # number of demand (read+write) misses -system.cpu7.l1c.overall_misses::cpu7 58983 # number of overall misses -system.cpu7.l1c.overall_misses::total 58983 # number of overall misses -system.cpu7.l1c.ReadReq_miss_latency::cpu7 932010776 # number of ReadReq miss cycles -system.cpu7.l1c.ReadReq_miss_latency::total 932010776 # number of ReadReq miss cycles -system.cpu7.l1c.WriteReq_miss_latency::cpu7 877703149 # number of WriteReq miss cycles -system.cpu7.l1c.WriteReq_miss_latency::total 877703149 # number of WriteReq miss cycles -system.cpu7.l1c.demand_miss_latency::cpu7 1809713925 # number of demand (read+write) miss cycles -system.cpu7.l1c.demand_miss_latency::total 1809713925 # number of demand (read+write) miss cycles -system.cpu7.l1c.overall_miss_latency::cpu7 1809713925 # number of overall miss cycles -system.cpu7.l1c.overall_miss_latency::total 1809713925 # number of overall miss cycles -system.cpu7.l1c.ReadReq_accesses::cpu7 44533 # number of ReadReq accesses(hits+misses) -system.cpu7.l1c.ReadReq_accesses::total 44533 # number of ReadReq accesses(hits+misses) -system.cpu7.l1c.WriteReq_accesses::cpu7 24094 # number of WriteReq accesses(hits+misses) -system.cpu7.l1c.WriteReq_accesses::total 24094 # number of WriteReq accesses(hits+misses) -system.cpu7.l1c.demand_accesses::cpu7 68627 # number of demand (read+write) accesses -system.cpu7.l1c.demand_accesses::total 68627 # number of demand (read+write) accesses -system.cpu7.l1c.overall_accesses::cpu7 68627 # number of overall (read+write) accesses -system.cpu7.l1c.overall_accesses::total 68627 # number of overall (read+write) accesses -system.cpu7.l1c.ReadReq_miss_rate::cpu7 0.805784 # miss rate for ReadReq accesses -system.cpu7.l1c.ReadReq_miss_rate::total 0.805784 # miss rate for ReadReq accesses -system.cpu7.l1c.WriteReq_miss_rate::cpu7 0.958703 # miss rate for WriteReq accesses -system.cpu7.l1c.WriteReq_miss_rate::total 0.958703 # miss rate for WriteReq accesses -system.cpu7.l1c.demand_miss_rate::cpu7 0.859472 # miss rate for demand accesses -system.cpu7.l1c.demand_miss_rate::total 0.859472 # miss rate for demand accesses -system.cpu7.l1c.overall_miss_rate::cpu7 0.859472 # miss rate for overall accesses -system.cpu7.l1c.overall_miss_rate::total 0.859472 # miss rate for overall accesses -system.cpu7.l1c.ReadReq_avg_miss_latency::cpu7 25972.878609 # average ReadReq miss latency -system.cpu7.l1c.ReadReq_avg_miss_latency::total 25972.878609 # average ReadReq miss latency -system.cpu7.l1c.WriteReq_avg_miss_latency::cpu7 37997.452227 # average WriteReq miss latency -system.cpu7.l1c.WriteReq_avg_miss_latency::total 37997.452227 # average WriteReq miss latency -system.cpu7.l1c.demand_avg_miss_latency::cpu7 30681.957937 # average overall miss latency -system.cpu7.l1c.demand_avg_miss_latency::total 30681.957937 # average overall miss latency -system.cpu7.l1c.overall_avg_miss_latency::cpu7 30681.957937 # average overall miss latency -system.cpu7.l1c.overall_avg_miss_latency::total 30681.957937 # average overall miss latency -system.cpu7.l1c.blocked_cycles::no_mshrs 213241981 # number of cycles access was blocked +system.cpu7.l1c.occ_blocks::cpu7 396.828031 # Average occupied blocks per requestor +system.cpu7.l1c.occ_percent::cpu7 0.775055 # Average percentage of cache occupancy +system.cpu7.l1c.occ_percent::total 0.775055 # Average percentage of cache occupancy +system.cpu7.l1c.ReadReq_hits::cpu7 8703 # number of ReadReq hits +system.cpu7.l1c.ReadReq_hits::total 8703 # number of ReadReq hits +system.cpu7.l1c.WriteReq_hits::cpu7 1096 # number of WriteReq hits +system.cpu7.l1c.WriteReq_hits::total 1096 # number of WriteReq hits +system.cpu7.l1c.demand_hits::cpu7 9799 # number of demand (read+write) hits +system.cpu7.l1c.demand_hits::total 9799 # number of demand (read+write) hits +system.cpu7.l1c.overall_hits::cpu7 9799 # number of overall hits +system.cpu7.l1c.overall_hits::total 9799 # number of overall hits +system.cpu7.l1c.ReadReq_misses::cpu7 36453 # number of ReadReq misses +system.cpu7.l1c.ReadReq_misses::total 36453 # number of ReadReq misses +system.cpu7.l1c.WriteReq_misses::cpu7 22910 # number of WriteReq misses +system.cpu7.l1c.WriteReq_misses::total 22910 # number of WriteReq misses +system.cpu7.l1c.demand_misses::cpu7 59363 # number of demand (read+write) misses +system.cpu7.l1c.demand_misses::total 59363 # number of demand (read+write) misses +system.cpu7.l1c.overall_misses::cpu7 59363 # number of overall misses +system.cpu7.l1c.overall_misses::total 59363 # number of overall misses +system.cpu7.l1c.ReadReq_miss_latency::cpu7 908883238 # number of ReadReq miss cycles +system.cpu7.l1c.ReadReq_miss_latency::total 908883238 # number of ReadReq miss cycles +system.cpu7.l1c.WriteReq_miss_latency::cpu7 808946616 # number of WriteReq miss cycles +system.cpu7.l1c.WriteReq_miss_latency::total 808946616 # number of WriteReq miss cycles +system.cpu7.l1c.demand_miss_latency::cpu7 1717829854 # number of demand (read+write) miss cycles +system.cpu7.l1c.demand_miss_latency::total 1717829854 # number of demand (read+write) miss cycles +system.cpu7.l1c.overall_miss_latency::cpu7 1717829854 # number of overall miss cycles +system.cpu7.l1c.overall_miss_latency::total 1717829854 # number of overall miss cycles +system.cpu7.l1c.ReadReq_accesses::cpu7 45156 # number of ReadReq accesses(hits+misses) +system.cpu7.l1c.ReadReq_accesses::total 45156 # number of ReadReq accesses(hits+misses) +system.cpu7.l1c.WriteReq_accesses::cpu7 24006 # number of WriteReq accesses(hits+misses) +system.cpu7.l1c.WriteReq_accesses::total 24006 # number of WriteReq accesses(hits+misses) +system.cpu7.l1c.demand_accesses::cpu7 69162 # number of demand (read+write) accesses +system.cpu7.l1c.demand_accesses::total 69162 # number of demand (read+write) accesses +system.cpu7.l1c.overall_accesses::cpu7 69162 # number of overall (read+write) accesses +system.cpu7.l1c.overall_accesses::total 69162 # number of overall (read+write) accesses +system.cpu7.l1c.ReadReq_miss_rate::cpu7 0.807268 # miss rate for ReadReq accesses +system.cpu7.l1c.ReadReq_miss_rate::total 0.807268 # miss rate for ReadReq accesses +system.cpu7.l1c.WriteReq_miss_rate::cpu7 0.954345 # miss rate for WriteReq accesses +system.cpu7.l1c.WriteReq_miss_rate::total 0.954345 # miss rate for WriteReq accesses +system.cpu7.l1c.demand_miss_rate::cpu7 0.858318 # miss rate for demand accesses +system.cpu7.l1c.demand_miss_rate::total 0.858318 # miss rate for demand accesses +system.cpu7.l1c.overall_miss_rate::cpu7 0.858318 # miss rate for overall accesses +system.cpu7.l1c.overall_miss_rate::total 0.858318 # miss rate for overall accesses +system.cpu7.l1c.ReadReq_avg_miss_latency::cpu7 24933.016158 # average ReadReq miss latency +system.cpu7.l1c.ReadReq_avg_miss_latency::total 24933.016158 # average ReadReq miss latency +system.cpu7.l1c.WriteReq_avg_miss_latency::cpu7 35309.760629 # average WriteReq miss latency +system.cpu7.l1c.WriteReq_avg_miss_latency::total 35309.760629 # average WriteReq miss latency +system.cpu7.l1c.demand_avg_miss_latency::cpu7 28937.719691 # average overall miss latency +system.cpu7.l1c.demand_avg_miss_latency::total 28937.719691 # average overall miss latency +system.cpu7.l1c.overall_avg_miss_latency::cpu7 28937.719691 # average overall miss latency +system.cpu7.l1c.overall_avg_miss_latency::total 28937.719691 # average overall miss latency +system.cpu7.l1c.blocked_cycles::no_mshrs 153732048 # number of cycles access was blocked system.cpu7.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu7.l1c.blocked::no_mshrs 67091 # number of cycles access was blocked +system.cpu7.l1c.blocked::no_mshrs 53029 # number of cycles access was blocked system.cpu7.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu7.l1c.avg_blocked_cycles::no_mshrs 3178.399204 # average number of cycles each access was blocked +system.cpu7.l1c.avg_blocked_cycles::no_mshrs 2899.018424 # average number of cycles each access was blocked system.cpu7.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu7.l1c.fast_writes 0 # number of fast writes performed system.cpu7.l1c.cache_copies 0 # number of cache copies performed -system.cpu7.l1c.writebacks::writebacks 9457 # number of writebacks -system.cpu7.l1c.writebacks::total 9457 # number of writebacks -system.cpu7.l1c.ReadReq_mshr_misses::cpu7 35884 # number of ReadReq MSHR misses -system.cpu7.l1c.ReadReq_mshr_misses::total 35884 # number of ReadReq MSHR misses -system.cpu7.l1c.WriteReq_mshr_misses::cpu7 23099 # number of WriteReq MSHR misses -system.cpu7.l1c.WriteReq_mshr_misses::total 23099 # number of WriteReq MSHR misses -system.cpu7.l1c.demand_mshr_misses::cpu7 58983 # number of demand (read+write) MSHR misses -system.cpu7.l1c.demand_mshr_misses::total 58983 # number of demand (read+write) MSHR misses -system.cpu7.l1c.overall_mshr_misses::cpu7 58983 # number of overall MSHR misses -system.cpu7.l1c.overall_mshr_misses::total 58983 # number of overall MSHR misses -system.cpu7.l1c.ReadReq_mshr_miss_latency::cpu7 895990178 # number of ReadReq MSHR miss cycles -system.cpu7.l1c.ReadReq_mshr_miss_latency::total 895990178 # number of ReadReq MSHR miss cycles -system.cpu7.l1c.WriteReq_mshr_miss_latency::cpu7 854514720 # number of WriteReq MSHR miss cycles -system.cpu7.l1c.WriteReq_mshr_miss_latency::total 854514720 # number of WriteReq MSHR miss cycles -system.cpu7.l1c.demand_mshr_miss_latency::cpu7 1750504898 # number of demand (read+write) MSHR miss cycles -system.cpu7.l1c.demand_mshr_miss_latency::total 1750504898 # number of demand (read+write) MSHR miss cycles -system.cpu7.l1c.overall_mshr_miss_latency::cpu7 1750504898 # number of overall MSHR miss cycles -system.cpu7.l1c.overall_mshr_miss_latency::total 1750504898 # number of overall MSHR miss cycles -system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::cpu7 906836045 # number of ReadReq MSHR uncacheable cycles -system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::total 906836045 # number of ReadReq MSHR uncacheable cycles -system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::cpu7 572746318 # number of WriteReq MSHR uncacheable cycles -system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::total 572746318 # number of WriteReq MSHR uncacheable cycles -system.cpu7.l1c.overall_mshr_uncacheable_latency::cpu7 1479582363 # number of overall MSHR uncacheable cycles -system.cpu7.l1c.overall_mshr_uncacheable_latency::total 1479582363 # number of overall MSHR uncacheable cycles -system.cpu7.l1c.ReadReq_mshr_miss_rate::cpu7 0.805784 # mshr miss rate for ReadReq accesses -system.cpu7.l1c.ReadReq_mshr_miss_rate::total 0.805784 # mshr miss rate for ReadReq accesses -system.cpu7.l1c.WriteReq_mshr_miss_rate::cpu7 0.958703 # mshr miss rate for WriteReq accesses -system.cpu7.l1c.WriteReq_mshr_miss_rate::total 0.958703 # mshr miss rate for WriteReq accesses -system.cpu7.l1c.demand_mshr_miss_rate::cpu7 0.859472 # mshr miss rate for demand accesses -system.cpu7.l1c.demand_mshr_miss_rate::total 0.859472 # mshr miss rate for demand accesses -system.cpu7.l1c.overall_mshr_miss_rate::cpu7 0.859472 # mshr miss rate for overall accesses -system.cpu7.l1c.overall_mshr_miss_rate::total 0.859472 # mshr miss rate for overall accesses -system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::cpu7 24969.071954 # average ReadReq mshr miss latency -system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::total 24969.071954 # average ReadReq mshr miss latency -system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::cpu7 36993.580674 # average WriteReq mshr miss latency -system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::total 36993.580674 # average WriteReq mshr miss latency -system.cpu7.l1c.demand_avg_mshr_miss_latency::cpu7 29678.125867 # average overall mshr miss latency -system.cpu7.l1c.demand_avg_mshr_miss_latency::total 29678.125867 # average overall mshr miss latency -system.cpu7.l1c.overall_avg_mshr_miss_latency::cpu7 29678.125867 # average overall mshr miss latency -system.cpu7.l1c.overall_avg_mshr_miss_latency::total 29678.125867 # average overall mshr miss latency +system.cpu7.l1c.writebacks::writebacks 9581 # number of writebacks +system.cpu7.l1c.writebacks::total 9581 # number of writebacks +system.cpu7.l1c.ReadReq_mshr_misses::cpu7 36453 # number of ReadReq MSHR misses +system.cpu7.l1c.ReadReq_mshr_misses::total 36453 # number of ReadReq MSHR misses +system.cpu7.l1c.WriteReq_mshr_misses::cpu7 22910 # number of WriteReq MSHR misses +system.cpu7.l1c.WriteReq_mshr_misses::total 22910 # number of WriteReq MSHR misses +system.cpu7.l1c.demand_mshr_misses::cpu7 59363 # number of demand (read+write) MSHR misses +system.cpu7.l1c.demand_mshr_misses::total 59363 # number of demand (read+write) MSHR misses +system.cpu7.l1c.overall_mshr_misses::cpu7 59363 # number of overall MSHR misses +system.cpu7.l1c.overall_mshr_misses::total 59363 # number of overall MSHR misses +system.cpu7.l1c.ReadReq_mshr_miss_latency::cpu7 872289420 # number of ReadReq MSHR miss cycles +system.cpu7.l1c.ReadReq_mshr_miss_latency::total 872289420 # number of ReadReq MSHR miss cycles +system.cpu7.l1c.WriteReq_mshr_miss_latency::cpu7 785947981 # number of WriteReq MSHR miss cycles +system.cpu7.l1c.WriteReq_mshr_miss_latency::total 785947981 # number of WriteReq MSHR miss cycles +system.cpu7.l1c.demand_mshr_miss_latency::cpu7 1658237401 # number of demand (read+write) MSHR miss cycles +system.cpu7.l1c.demand_mshr_miss_latency::total 1658237401 # number of demand (read+write) MSHR miss cycles +system.cpu7.l1c.overall_mshr_miss_latency::cpu7 1658237401 # number of overall MSHR miss cycles +system.cpu7.l1c.overall_mshr_miss_latency::total 1658237401 # number of overall MSHR miss cycles +system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::cpu7 674384984 # number of ReadReq MSHR uncacheable cycles +system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::total 674384984 # number of ReadReq MSHR uncacheable cycles +system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::cpu7 681937361 # number of WriteReq MSHR uncacheable cycles +system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::total 681937361 # number of WriteReq MSHR uncacheable cycles +system.cpu7.l1c.overall_mshr_uncacheable_latency::cpu7 1356322345 # number of overall MSHR uncacheable cycles +system.cpu7.l1c.overall_mshr_uncacheable_latency::total 1356322345 # number of overall MSHR uncacheable cycles +system.cpu7.l1c.ReadReq_mshr_miss_rate::cpu7 0.807268 # mshr miss rate for ReadReq accesses +system.cpu7.l1c.ReadReq_mshr_miss_rate::total 0.807268 # mshr miss rate for ReadReq accesses +system.cpu7.l1c.WriteReq_mshr_miss_rate::cpu7 0.954345 # mshr miss rate for WriteReq accesses +system.cpu7.l1c.WriteReq_mshr_miss_rate::total 0.954345 # mshr miss rate for WriteReq accesses +system.cpu7.l1c.demand_mshr_miss_rate::cpu7 0.858318 # mshr miss rate for demand accesses +system.cpu7.l1c.demand_mshr_miss_rate::total 0.858318 # mshr miss rate for demand accesses +system.cpu7.l1c.overall_mshr_miss_rate::cpu7 0.858318 # mshr miss rate for overall accesses +system.cpu7.l1c.overall_mshr_miss_rate::total 0.858318 # mshr miss rate for overall accesses +system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::cpu7 23929.153156 # average ReadReq mshr miss latency +system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::total 23929.153156 # average ReadReq mshr miss latency +system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::cpu7 34305.891794 # average WriteReq mshr miss latency +system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::total 34305.891794 # average WriteReq mshr miss latency +system.cpu7.l1c.demand_avg_mshr_miss_latency::cpu7 27933.854438 # average overall mshr miss latency +system.cpu7.l1c.demand_avg_mshr_miss_latency::total 27933.854438 # average overall mshr miss latency +system.cpu7.l1c.overall_avg_mshr_miss_latency::cpu7 27933.854438 # average overall mshr miss latency +system.cpu7.l1c.overall_avg_mshr_miss_latency::total 27933.854438 # average overall mshr miss latency system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu7 inf # average ReadReq mshr uncacheable latency system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu7 inf # average WriteReq mshr uncacheable latency |