diff options
| author | Ali Saidi <Ali.Saidi@ARM.com> | 2012-02-13 12:30:30 -0600 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2012-02-13 12:30:30 -0600 |
| commit | 0d46708dc20c438d29bd724fb7d4b54d4d2f318a (patch) | |
| tree | 337e1a7404c57817cd08106a0369542ea5c4ac30 /tests/quick/se | |
| parent | 9b05e96b9efdb9cdcc4e40ef9c96b1228df7a175 (diff) | |
| download | gem5-0d46708dc20c438d29bd724fb7d4b54d4d2f318a.tar.xz | |
bp: fix up stats for changes to branch predictor
Diffstat (limited to 'tests/quick/se')
26 files changed, 5963 insertions, 5966 deletions
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/simout b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/simout index ff8d4bf12..89a25c4c1 100755 --- a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/simout +++ b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 11 2012 13:05:17 -gem5 started Feb 11 2012 13:09:12 +gem5 compiled Feb 12 2012 17:15:14 +gem5 started Feb 12 2012 17:33:02 gem5 executing on zizzer command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/quick/se/00.hello/alpha/linux/inorder-timing -re tests/run.py build/ALPHA/tests/fast/quick/se/00.hello/alpha/linux/inorder-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello world! -Exiting @ tick 21216000 because target called exit() +Exiting @ tick 21234500 because target called exit() diff --git a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt index fc30a21c8..fdd02b36e 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000021 # Number of seconds simulated -sim_ticks 21216000 # Number of ticks simulated -final_tick 21216000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 21234500 # Number of ticks simulated +final_tick 21234500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 38129 # Simulator instruction rate (inst/s) -host_op_rate 38124 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 126288909 # Simulator tick rate (ticks/s) -host_mem_usage 209388 # Number of bytes of host memory used -host_seconds 0.17 # Real time elapsed on the host +host_inst_rate 95244 # Simulator instruction rate (inst/s) +host_op_rate 95219 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 315647941 # Simulator tick rate (ticks/s) +host_mem_usage 209384 # Number of bytes of host memory used +host_seconds 0.07 # Real time elapsed on the host sim_insts 6404 # Number of instructions simulated sim_ops 6404 # Number of ops (including micro ops) simulated system.physmem.bytes_read 30016 # Number of bytes read from this memory @@ -17,9 +17,9 @@ system.physmem.bytes_written 0 # Nu system.physmem.num_reads 469 # Number of read requests responded to by this memory system.physmem.num_writes 0 # Number of write requests responded to by this memory system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 1414781297 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 907993967 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total 1414781297 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read 1413548706 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 907202901 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total 1413548706 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -36,10 +36,10 @@ system.cpu.dtb.data_hits 2084 # DT system.cpu.dtb.data_misses 10 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations system.cpu.dtb.data_accesses 2094 # DTB accesses -system.cpu.itb.fetch_hits 929 # ITB hits +system.cpu.itb.fetch_hits 908 # ITB hits system.cpu.itb.fetch_misses 17 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 946 # ITB accesses +system.cpu.itb.fetch_accesses 925 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -53,16 +53,16 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 42433 # number of cpu cycles simulated +system.cpu.numCycles 42470 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 11397 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 11434 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 442 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 35050 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 7383 # Number of cycles cpu stages are processed. -system.cpu.activity 17.399194 # Percentage of cycles cpu is active +system.cpu.timesIdled 443 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 35079 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 7391 # Number of cycles cpu stages are processed. +system.cpu.activity 17.402873 # Percentage of cycles cpu is active system.cpu.comLoads 1185 # Number of Load instructions committed system.cpu.comStores 865 # Number of Store instructions committed system.cpu.comBranches 1051 # Number of Branches instructions committed @@ -74,92 +74,92 @@ system.cpu.committedInsts 6404 # Nu system.cpu.committedOps 6404 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 6404 # Number of Instructions committed (Total) -system.cpu.cpi 6.626015 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 6.631793 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi no_value # CPI: Total SMT-CPI -system.cpu.cpi_total 6.626015 # CPI: Total CPI of All Threads -system.cpu.ipc 0.150920 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 6.631793 # CPI: Total CPI of All Threads +system.cpu.ipc 0.150789 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc no_value # IPC: Total SMT-IPC -system.cpu.ipc_total 0.150920 # IPC: Total IPC of All Threads -system.cpu.branch_predictor.lookups 1670 # Number of BP lookups -system.cpu.branch_predictor.condPredicted 1199 # Number of conditional branches predicted +system.cpu.ipc_total 0.150789 # IPC: Total IPC of All Threads +system.cpu.branch_predictor.lookups 1608 # Number of BP lookups +system.cpu.branch_predictor.condPredicted 1127 # Number of conditional branches predicted system.cpu.branch_predictor.condIncorrect 712 # Number of conditional branches incorrect -system.cpu.branch_predictor.BTBLookups 1410 # Number of BTB lookups -system.cpu.branch_predictor.BTBHits 414 # Number of BTB hits +system.cpu.branch_predictor.BTBLookups 1187 # Number of BTB lookups +system.cpu.branch_predictor.BTBHits 314 # Number of BTB hits system.cpu.branch_predictor.usedRAS 126 # Number of times the RAS was used to get a target. system.cpu.branch_predictor.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.branch_predictor.BTBHitPct 29.361702 # BTB Hit Percentage -system.cpu.branch_predictor.predictedTaken 565 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.predictedNotTaken 1105 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 5165 # Number of Reads from Int. Register File +system.cpu.branch_predictor.BTBHitPct 26.453243 # BTB Hit Percentage +system.cpu.branch_predictor.predictedTaken 464 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.predictedNotTaken 1144 # Number of Branches Predicted As Not Taken (False). +system.cpu.regfile_manager.intRegFileReads 5213 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 4580 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 9745 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.intRegFileAccesses 9793 # Total Accesses (Read+Write) to the Int. Register File system.cpu.regfile_manager.floatRegFileReads 8 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 2 # Number of Writes to FP Register File system.cpu.regfile_manager.floatRegFileAccesses 10 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 3002 # Number of Registers Read Through Forwarding Logic -system.cpu.agen_unit.agens 2138 # Number of Address Generations -system.cpu.execution_unit.predictedTakenIncorrect 357 # Number of Branches Incorrectly Predicted As Taken. -system.cpu.execution_unit.predictedNotTakenIncorrect 294 # Number of Branches Incorrectly Predicted As Not Taken). +system.cpu.regfile_manager.regForwards 2970 # Number of Registers Read Through Forwarding Logic +system.cpu.agen_unit.agens 2183 # Number of Address Generations +system.cpu.execution_unit.predictedTakenIncorrect 284 # Number of Branches Incorrectly Predicted As Taken. +system.cpu.execution_unit.predictedNotTakenIncorrect 367 # Number of Branches Incorrectly Predicted As Not Taken). system.cpu.execution_unit.mispredicted 651 # Number of Branches Incorrectly Predicted system.cpu.execution_unit.predicted 401 # Number of Branches Incorrectly Predicted system.cpu.execution_unit.mispredictPct 61.882129 # Percentage of Incorrect Branches Predicts -system.cpu.execution_unit.executions 4447 # Number of Instructions Executed. +system.cpu.execution_unit.executions 4474 # Number of Instructions Executed. system.cpu.mult_div_unit.multiplies 1 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed -system.cpu.stage0.idleCycles 37465 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 4968 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 11.707869 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 38516 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 3917 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 9.231023 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 38252 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 4181 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 9.853180 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 41093 # Number of cycles 0 instructions are processed. +system.cpu.stage0.idleCycles 37550 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 4920 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 11.584648 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 38585 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 3885 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 9.147634 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 38290 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 4180 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 9.842242 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 41130 # Number of cycles 0 instructions are processed. system.cpu.stage3.runCycles 1340 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 3.157920 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 37964 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 4469 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 10.531897 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.utilization 3.155168 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 38002 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 4468 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 10.520367 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 138.882502 # Cycle average of tags in use -system.cpu.icache.total_refs 581 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 138.955928 # Cycle average of tags in use +system.cpu.icache.total_refs 558 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 301 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 1.930233 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 1.853821 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 138.882502 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.067814 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.067814 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 581 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 581 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 581 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 581 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 581 # number of overall hits -system.cpu.icache.overall_hits::total 581 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 348 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 348 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 348 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 348 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 348 # number of overall misses -system.cpu.icache.overall_misses::total 348 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 19241000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 19241000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 19241000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 19241000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 19241000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 19241000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 929 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 929 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 929 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 929 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 929 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 929 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.374596 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.374596 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.374596 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55290.229885 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 55290.229885 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 55290.229885 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 138.955928 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.067850 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.067850 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 558 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 558 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 558 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 558 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 558 # number of overall hits +system.cpu.icache.overall_hits::total 558 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 350 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 350 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 350 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 350 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 350 # number of overall misses +system.cpu.icache.overall_misses::total 350 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 19343500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 19343500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 19343500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 19343500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 19343500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 19343500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 908 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 908 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 908 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 908 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 908 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 908 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.385463 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.385463 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.385463 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55267.142857 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 55267.142857 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 55267.142857 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -168,40 +168,40 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 46 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 46 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 46 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 46 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 46 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 46 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 48 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 48 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 48 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 48 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 48 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 48 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 302 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 302 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 302 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 302 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 302 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 302 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 16049000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 16049000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 16049000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 16049000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 16049000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 16049000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.325081 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.325081 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.325081 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53142.384106 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53142.384106 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53142.384106 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 16051500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 16051500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 16051500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 16051500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 16051500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 16051500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.332599 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.332599 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.332599 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53150.662252 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53150.662252 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53150.662252 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 102.671807 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 102.711534 # Cycle average of tags in use system.cpu.dcache.total_refs 1703 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 168 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 10.136905 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 102.671807 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.025066 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.025066 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::cpu.data 102.711534 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.025076 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.025076 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 1088 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1088 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 615 # number of WriteReq hits @@ -218,14 +218,14 @@ system.cpu.dcache.demand_misses::cpu.data 347 # n system.cpu.dcache.demand_misses::total 347 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 347 # number of overall misses system.cpu.dcache.overall_misses::total 347 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5508500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5508500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 13555500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 13555500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 19064000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 19064000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 19064000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 19064000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5507500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5507500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 13555000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 13555000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 19062500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 19062500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 19062500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 19062500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 1185 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1185 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses) @@ -238,10 +238,10 @@ system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.081857 system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289017 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.169268 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.169268 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56788.659794 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54222 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 54939.481268 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 54939.481268 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56778.350515 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54220 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 54935.158501 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 54935.158501 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 1656000 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -266,34 +266,34 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 168 system.cpu.dcache.demand_mshr_misses::total 168 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 168 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5114000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 5114000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3910000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3910000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9024000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 9024000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9024000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 9024000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5113000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 5113000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3909500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3909500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9022500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 9022500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9022500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 9022500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.080169 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.081951 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.081951 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53831.578947 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53561.643836 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53714.285714 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53714.285714 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53821.052632 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53554.794521 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53705.357143 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53705.357143 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 195.209568 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 195.300582 # Cycle average of tags in use system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 395 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.002532 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 138.958412 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 56.251157 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.004241 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 139.031748 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 56.268833 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.004243 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.001717 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.005957 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.005960 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits @@ -311,17 +311,17 @@ system.cpu.l2cache.demand_misses::total 469 # nu system.cpu.l2cache.overall_misses::cpu.inst 301 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 168 # number of overall misses system.cpu.l2cache.overall_misses::total 469 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 15707000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4995000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 15708000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4994000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::total 20702000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3822000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 3822000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 15707000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 8817000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 24524000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 15707000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 8817000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 24524000 # number of overall miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3821500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 3821500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 15708000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 8815500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 24523500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 15708000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 8815500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 24523500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 302 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 95 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 397 # number of ReadReq accesses(hits+misses) @@ -340,13 +340,13 @@ system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996689 system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996689 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52182.724252 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52578.947368 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52356.164384 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52182.724252 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52482.142857 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52182.724252 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52482.142857 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52186.046512 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52568.421053 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52349.315068 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52186.046512 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52473.214286 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52186.046512 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52473.214286 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -367,16 +367,16 @@ system.cpu.l2cache.overall_mshr_misses::cpu.inst 301 system.cpu.l2cache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 469 # number of overall MSHR misses system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 12038500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3838500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15877000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3838000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15876500 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2942500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2942500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 12038500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6781000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 18819500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6780500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 18819000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 12038500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6781000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 18819500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6780500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 18819000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996689 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses @@ -385,12 +385,12 @@ system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996689 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 39995.016611 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40405.263158 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40400 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40308.219178 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 39995.016611 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40363.095238 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40360.119048 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 39995.016611 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40363.095238 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40360.119048 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout index 684d7e9b2..16153e12a 100755 --- a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout +++ b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 11 2012 13:05:17 -gem5 started Feb 11 2012 13:09:12 +gem5 compiled Feb 12 2012 17:15:14 +gem5 started Feb 12 2012 17:33:02 gem5 executing on zizzer command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/quick/se/00.hello/alpha/linux/o3-timing -re tests/run.py build/ALPHA/tests/fast/quick/se/00.hello/alpha/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello world! -Exiting @ tick 12004500 because target called exit() +Exiting @ tick 12450500 because target called exit() diff --git a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt index 49671266a..bfc4cc915 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt @@ -1,45 +1,45 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000012 # Number of seconds simulated -sim_ticks 12004500 # Number of ticks simulated -final_tick 12004500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 12450500 # Number of ticks simulated +final_tick 12450500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 42281 # Simulator instruction rate (inst/s) -host_op_rate 42276 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 79460110 # Simulator tick rate (ticks/s) -host_mem_usage 210060 # Number of bytes of host memory used -host_seconds 0.15 # Real time elapsed on the host +host_inst_rate 87465 # Simulator instruction rate (inst/s) +host_op_rate 87444 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 170447462 # Simulator tick rate (ticks/s) +host_mem_usage 210080 # Number of bytes of host memory used +host_seconds 0.07 # Real time elapsed on the host sim_insts 6386 # Number of instructions simulated sim_ops 6386 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 31040 # Number of bytes read from this memory -system.physmem.bytes_inst_read 19904 # Number of instructions bytes read from this memory +system.physmem.bytes_read 31360 # Number of bytes read from this memory +system.physmem.bytes_inst_read 20096 # Number of instructions bytes read from this memory system.physmem.bytes_written 0 # Number of bytes written to this memory -system.physmem.num_reads 485 # Number of read requests responded to by this memory +system.physmem.num_reads 490 # Number of read requests responded to by this memory system.physmem.num_writes 0 # Number of write requests responded to by this memory system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 2585697030 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 1658044900 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total 2585697030 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read 2518774346 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 1614071724 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total 2518774346 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 1860 # DTB read hits -system.cpu.dtb.read_misses 44 # DTB read misses +system.cpu.dtb.read_hits 1943 # DTB read hits +system.cpu.dtb.read_misses 53 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 1904 # DTB read accesses -system.cpu.dtb.write_hits 1041 # DTB write hits -system.cpu.dtb.write_misses 28 # DTB write misses +system.cpu.dtb.read_accesses 1996 # DTB read accesses +system.cpu.dtb.write_hits 1071 # DTB write hits +system.cpu.dtb.write_misses 32 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 1069 # DTB write accesses -system.cpu.dtb.data_hits 2901 # DTB hits -system.cpu.dtb.data_misses 72 # DTB misses +system.cpu.dtb.write_accesses 1103 # DTB write accesses +system.cpu.dtb.data_hits 3014 # DTB hits +system.cpu.dtb.data_misses 85 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 2973 # DTB accesses -system.cpu.itb.fetch_hits 2039 # ITB hits -system.cpu.itb.fetch_misses 29 # ITB misses +system.cpu.dtb.data_accesses 3099 # DTB accesses +system.cpu.itb.fetch_hits 2367 # ITB hits +system.cpu.itb.fetch_misses 26 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 2068 # ITB accesses +system.cpu.itb.fetch_accesses 2393 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -53,246 +53,246 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 24010 # number of cpu cycles simulated +system.cpu.numCycles 24902 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 2507 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 1457 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 459 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 1937 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 718 # Number of BTB hits +system.cpu.BPredUnit.lookups 2873 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 1642 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 561 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 2186 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 748 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 373 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 67 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 7150 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 14456 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2507 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 1091 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 2619 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1556 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 1112 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 24 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 631 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 2039 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 318 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 12592 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.148030 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.530696 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 430 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 100 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 7799 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 16643 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2873 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 1178 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 2979 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1864 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 854 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 22 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 590 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 2367 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 368 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 13505 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.232358 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.611762 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 9973 79.20% 79.20% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 274 2.18% 81.38% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 224 1.78% 83.16% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 222 1.76% 84.92% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 234 1.86% 86.78% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 178 1.41% 88.19% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 257 2.04% 90.23% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 140 1.11% 91.34% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1090 8.66% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 10526 77.94% 77.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 289 2.14% 80.08% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 251 1.86% 81.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 257 1.90% 83.84% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 272 2.01% 85.86% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 206 1.53% 87.38% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 248 1.84% 89.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 173 1.28% 90.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1283 9.50% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 12592 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.104415 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.602082 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 7970 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 1126 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2449 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 69 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 978 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 214 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 85 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 13378 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 215 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 978 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 8160 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 432 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 358 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2318 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 346 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 12829 # Number of instructions processed by rename -system.cpu.rename.IQFullEvents 11 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 291 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 9573 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 16037 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 16020 # Number of integer rename lookups +system.cpu.fetch.rateDist::total 13505 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.115372 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.668340 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 8546 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 938 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 2784 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 62 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1175 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 292 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 96 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 15310 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 265 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1175 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 8782 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 334 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 357 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 2587 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 270 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 14488 # Number of instructions processed by rename +system.cpu.rename.IQFullEvents 7 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 212 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 10864 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 18125 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 18108 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 17 # Number of floating rename lookups system.cpu.rename.CommittedMaps 4583 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 4990 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 6281 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 28 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 22 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 881 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2391 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1271 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 4 # Number of conflicting loads. +system.cpu.rename.skidInsts 777 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2616 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1352 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 7 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 11558 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 27 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 9757 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 47 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 4883 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 2853 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 10 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 12592 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.774857 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.395692 # Number of insts issued each cycle +system.cpu.iq.iqInstsAdded 12765 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 26 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 10522 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 44 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 6026 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 3602 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 9 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 13505 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.779119 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.404443 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 8510 67.58% 67.58% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1462 11.61% 79.19% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 1072 8.51% 87.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 685 5.44% 93.15% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 440 3.49% 96.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 254 2.02% 98.66% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 128 1.02% 99.67% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 30 0.24% 99.91% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 11 0.09% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 9165 67.86% 67.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1484 10.99% 78.85% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 1164 8.62% 87.47% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 762 5.64% 93.11% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 469 3.47% 96.59% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 274 2.03% 98.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 142 1.05% 99.67% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 34 0.25% 99.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 11 0.08% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 12592 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 13505 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 13 12.26% 12.26% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 12.26% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 12.26% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 12.26% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 12.26% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 12.26% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 12.26% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 12.26% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 12.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 12.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 12.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 12.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 12.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 12.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 12.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 12.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 12.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 12.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 12.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 12.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 12.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 12.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 12.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 12.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 12.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 12.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 12.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 12.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 12.26% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 54 50.94% 63.21% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 39 36.79% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 10 8.93% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 65 58.04% 66.96% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 37 33.04% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 6575 67.39% 67.41% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 1 0.01% 67.42% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.42% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 67.44% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.44% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.44% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.44% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.44% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.44% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2074 21.26% 88.70% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1103 11.30% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 7148 67.93% 67.95% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 1 0.01% 67.96% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.96% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 67.98% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.98% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.98% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.98% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.98% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.98% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2225 21.15% 89.13% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1144 10.87% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 9757 # Type of FU issued -system.cpu.iq.rate 0.406372 # Inst issue rate -system.cpu.iq.fu_busy_cnt 106 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.010864 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 32238 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 16474 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 8982 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 10522 # Type of FU issued +system.cpu.iq.rate 0.422536 # Inst issue rate +system.cpu.iq.fu_busy_cnt 112 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.010644 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 34684 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 18825 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 9477 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 21 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 10 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 10 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 9850 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 10621 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 11 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 60 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 63 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1206 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1431 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 17 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 406 # Number of stores squashed +system.cpu.iew.lsq.thread0.memOrderViolation 19 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 487 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 978 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 150 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 8 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 11665 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 142 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2391 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1271 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 27 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 5 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 1175 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 41 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 12870 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 183 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2616 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1352 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 26 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 17 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 120 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 327 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 447 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 9313 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 1914 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 444 # Number of squashed instructions skipped in execute +system.cpu.iew.memOrderViolationEvents 19 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 166 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 401 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 567 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 9878 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 2009 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 644 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 80 # number of nop insts executed -system.cpu.iew.exec_refs 2985 # number of memory reference insts executed -system.cpu.iew.exec_branches 1504 # Number of branches executed -system.cpu.iew.exec_stores 1071 # Number of stores executed -system.cpu.iew.exec_rate 0.387880 # Inst execution rate -system.cpu.iew.wb_sent 9119 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 8992 # cumulative count of insts written-back -system.cpu.iew.wb_producers 4719 # num instructions producing a value -system.cpu.iew.wb_consumers 6404 # num instructions consuming a value +system.cpu.iew.exec_nop 79 # number of nop insts executed +system.cpu.iew.exec_refs 3117 # number of memory reference insts executed +system.cpu.iew.exec_branches 1605 # Number of branches executed +system.cpu.iew.exec_stores 1108 # Number of stores executed +system.cpu.iew.exec_rate 0.396675 # Inst execution rate +system.cpu.iew.wb_sent 9634 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 9487 # cumulative count of insts written-back +system.cpu.iew.wb_producers 4957 # num instructions producing a value +system.cpu.iew.wb_consumers 6732 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.374511 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.736883 # average fanout of values written-back +system.cpu.iew.wb_rate 0.380973 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.736334 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 6403 # The number of committed instructions system.cpu.commit.commitCommittedOps 6403 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 5259 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 6436 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 381 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 11614 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.551317 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.413084 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 475 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 12330 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.519303 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.354208 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 8938 76.96% 76.96% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1410 12.14% 89.10% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 462 3.98% 93.08% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 240 2.07% 95.14% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 159 1.37% 96.51% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 87 0.75% 97.26% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 110 0.95% 98.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 46 0.40% 98.61% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 162 1.39% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 9591 77.79% 77.79% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1448 11.74% 89.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 489 3.97% 93.50% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 259 2.10% 95.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 152 1.23% 96.83% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 96 0.78% 97.61% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 104 0.84% 98.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 40 0.32% 98.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 151 1.22% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 11614 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 12330 # Number of insts commited each cycle system.cpu.commit.committedInsts 6403 # Number of instructions committed system.cpu.commit.committedOps 6403 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -303,64 +303,64 @@ system.cpu.commit.branches 1051 # Nu system.cpu.commit.fp_insts 10 # Number of committed floating point instructions. system.cpu.commit.int_insts 6321 # Number of committed integer instructions. system.cpu.commit.function_calls 127 # Number of function calls committed. -system.cpu.commit.bw_lim_events 162 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 151 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 22763 # The number of ROB reads -system.cpu.rob.rob_writes 24313 # The number of ROB writes -system.cpu.timesIdled 230 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 11418 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 24667 # The number of ROB reads +system.cpu.rob.rob_writes 26868 # The number of ROB writes +system.cpu.timesIdled 232 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 11397 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 6386 # Number of Instructions Simulated system.cpu.committedOps 6386 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 6386 # Number of Instructions Simulated -system.cpu.cpi 3.759787 # CPI: Cycles Per Instruction -system.cpu.cpi_total 3.759787 # CPI: Total CPI of All Threads -system.cpu.ipc 0.265973 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.265973 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 11830 # number of integer regfile reads -system.cpu.int_regfile_writes 6732 # number of integer regfile writes +system.cpu.cpi 3.899468 # CPI: Cycles Per Instruction +system.cpu.cpi_total 3.899468 # CPI: Total CPI of All Threads +system.cpu.ipc 0.256445 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.256445 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 12526 # number of integer regfile reads +system.cpu.int_regfile_writes 7116 # number of integer regfile writes system.cpu.fp_regfile_reads 8 # number of floating regfile reads system.cpu.fp_regfile_writes 2 # number of floating regfile writes system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 160.112304 # Cycle average of tags in use -system.cpu.icache.total_refs 1606 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 312 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 5.147436 # Average number of references to valid blocks. +system.cpu.icache.tagsinuse 162.256588 # Cycle average of tags in use +system.cpu.icache.total_refs 1909 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 315 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 6.060317 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 160.112304 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.078180 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.078180 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 1606 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1606 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1606 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1606 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1606 # number of overall hits -system.cpu.icache.overall_hits::total 1606 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 433 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 433 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 433 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 433 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 433 # number of overall misses -system.cpu.icache.overall_misses::total 433 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 15431000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 15431000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 15431000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 15431000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 15431000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 15431000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 2039 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 2039 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 2039 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 2039 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 2039 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 2039 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.212359 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.212359 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.212359 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35637.413395 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 35637.413395 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 35637.413395 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 162.256588 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.079227 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.079227 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 1909 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1909 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1909 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1909 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1909 # number of overall hits +system.cpu.icache.overall_hits::total 1909 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 458 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 458 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 458 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 458 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 458 # number of overall misses +system.cpu.icache.overall_misses::total 458 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 16026500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 16026500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 16026500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 16026500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 16026500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 16026500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 2367 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 2367 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 2367 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 2367 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 2367 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 2367 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.193494 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.193494 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.193494 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34992.358079 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 34992.358079 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 34992.358079 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -369,80 +369,80 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 121 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 121 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 121 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 121 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 121 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 121 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 312 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 312 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 312 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 312 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 312 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 312 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11021000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 11021000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11021000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 11021000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11021000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 11021000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.153016 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.153016 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.153016 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35323.717949 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35323.717949 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35323.717949 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 143 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 143 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 143 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 143 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 143 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 143 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 315 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 315 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 315 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 315 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 315 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 315 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11133500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 11133500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11133500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 11133500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11133500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 11133500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.133080 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.133080 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.133080 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35344.444444 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35344.444444 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35344.444444 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 109.290272 # Cycle average of tags in use -system.cpu.dcache.total_refs 2154 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 174 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 12.379310 # Average number of references to valid blocks. +system.cpu.dcache.tagsinuse 109.847039 # Cycle average of tags in use +system.cpu.dcache.total_refs 2244 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 175 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 12.822857 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 109.290272 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.026682 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.026682 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 1645 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1645 # number of ReadReq hits +system.cpu.dcache.occ_blocks::cpu.data 109.847039 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.026818 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.026818 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 1735 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1735 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 509 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 509 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 2154 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2154 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2154 # number of overall hits -system.cpu.dcache.overall_hits::total 2154 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 154 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 154 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 2244 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2244 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2244 # number of overall hits +system.cpu.dcache.overall_hits::total 2244 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 144 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 144 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 356 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 356 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 510 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 510 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 510 # number of overall misses -system.cpu.dcache.overall_misses::total 510 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5497500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5497500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 12467500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 12467500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 17965000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 17965000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 17965000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 17965000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1799 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1799 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 500 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 500 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 500 # number of overall misses +system.cpu.dcache.overall_misses::total 500 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5240000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5240000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 12485500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 12485500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 17725500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 17725500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 17725500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 17725500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1879 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1879 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2664 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2664 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2664 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2664 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.085603 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 2744 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2744 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2744 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2744 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.076637 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.411561 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.191441 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.191441 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 35698.051948 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35021.067416 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 35225.490196 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 35225.490196 # average overall miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.182216 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.182216 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 36388.888889 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35071.629213 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 35451 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 35451 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -451,103 +451,103 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 53 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 53 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 283 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 283 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 336 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 336 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 336 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 336 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 101 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 101 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 73 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 73 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 174 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 174 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 174 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 174 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3654500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 3654500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2611500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2611500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6266000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6266000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6266000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6266000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.056142 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.065315 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.065315 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 36183.168317 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35773.972603 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 36011.494253 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 36011.494253 # average overall mshr miss latency +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 40 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 40 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 284 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 284 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 324 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 324 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 324 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 324 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 104 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 104 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 72 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 72 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 176 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 176 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 176 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 176 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3722000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 3722000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2575500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2575500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6297500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6297500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6297500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6297500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.055349 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.083237 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.064140 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.064140 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 35788.461538 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35770.833333 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 35781.250000 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 35781.250000 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 221.643066 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 224.787735 # Cycle average of tags in use system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 412 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.002427 # Average number of references to valid blocks. +system.cpu.l2cache.sampled_refs 418 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.002392 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 160.084939 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 61.558127 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.004885 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.001879 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.006764 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 162.229240 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 62.558495 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.004951 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.001909 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.006860 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::total 1 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits system.cpu.l2cache.overall_hits::total 1 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 311 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 101 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 412 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 73 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 73 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 311 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 174 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 485 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 311 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 174 # number of overall misses -system.cpu.l2cache.overall_misses::total 485 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 10665000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3498000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 14163000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2513500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 2513500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 10665000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 6011500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 16676500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 10665000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 6011500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 16676500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 312 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 101 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 413 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 73 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 73 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 312 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 174 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 486 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 312 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 174 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 486 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996795 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses::cpu.inst 314 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 104 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 418 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 72 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 72 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 314 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 176 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 490 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 314 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 176 # number of overall misses +system.cpu.l2cache.overall_misses::total 490 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 10779500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3600000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 14379500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2488500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 2488500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 10779500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 6088500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 16868000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 10779500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 6088500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 16868000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 315 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 104 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 419 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 72 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 72 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 315 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 176 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 491 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 315 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 176 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 491 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996825 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996795 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996825 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996795 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996825 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34292.604502 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34633.663366 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34431.506849 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34292.604502 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34548.850575 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34292.604502 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34548.850575 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34329.617834 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34615.384615 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34562.500000 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34329.617834 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34593.750000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34329.617834 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34593.750000 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -556,42 +556,42 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 311 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 101 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 412 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 73 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 73 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 311 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 174 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 485 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 311 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 174 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 485 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 9672000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3178000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 12850000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2286000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2286000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 9672000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5464000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 15136000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 9672000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5464000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 15136000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996795 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 314 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 104 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 418 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 72 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 72 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 314 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 176 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 490 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 314 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 176 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 490 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 9770500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3273500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13044000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2264000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2264000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 9770500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5537500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 15308000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 9770500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5537500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 15308000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996825 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996795 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996825 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996795 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996825 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31099.678457 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31465.346535 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31315.068493 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31099.678457 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31402.298851 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31099.678457 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31402.298851 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31116.242038 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31475.961538 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31444.444444 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31116.242038 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31463.068182 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31116.242038 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31463.068182 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simout b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simout index 6aed6d3ac..eb202613d 100755 --- a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simout +++ b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 11 2012 13:05:17 -gem5 started Feb 11 2012 13:09:23 +gem5 compiled Feb 12 2012 17:15:14 +gem5 started Feb 12 2012 17:33:03 gem5 executing on zizzer command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/quick/se/00.hello/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/fast/quick/se/00.hello/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello world! -Exiting @ tick 6833000 because target called exit() +Exiting @ tick 7015000 because target called exit() diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt index d93b581f0..686010297 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt @@ -1,45 +1,45 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000007 # Number of seconds simulated -sim_ticks 6833000 # Number of ticks simulated -final_tick 6833000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 7015000 # Number of ticks simulated +final_tick 7015000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 16400 # Simulator instruction rate (inst/s) -host_op_rate 16398 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 46934615 # Simulator tick rate (ticks/s) -host_mem_usage 209144 # Number of bytes of host memory used -host_seconds 0.15 # Real time elapsed on the host +host_inst_rate 73930 # Simulator instruction rate (inst/s) +host_op_rate 73884 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 217009042 # Simulator tick rate (ticks/s) +host_mem_usage 209140 # Number of bytes of host memory used +host_seconds 0.03 # Real time elapsed on the host sim_insts 2387 # Number of instructions simulated sim_ops 2387 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 17280 # Number of bytes read from this memory -system.physmem.bytes_inst_read 11840 # Number of instructions bytes read from this memory +system.physmem.bytes_read 17600 # Number of bytes read from this memory +system.physmem.bytes_inst_read 12096 # Number of instructions bytes read from this memory system.physmem.bytes_written 0 # Number of bytes written to this memory -system.physmem.num_reads 270 # Number of read requests responded to by this memory +system.physmem.num_reads 275 # Number of read requests responded to by this memory system.physmem.num_writes 0 # Number of write requests responded to by this memory system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 2528903849 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 1732767452 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total 2528903849 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read 2508909480 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 1724305061 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total 2508909480 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 679 # DTB read hits -system.cpu.dtb.read_misses 26 # DTB read misses +system.cpu.dtb.read_hits 711 # DTB read hits +system.cpu.dtb.read_misses 43 # DTB read misses system.cpu.dtb.read_acv 1 # DTB read access violations -system.cpu.dtb.read_accesses 705 # DTB read accesses -system.cpu.dtb.write_hits 356 # DTB write hits -system.cpu.dtb.write_misses 18 # DTB write misses +system.cpu.dtb.read_accesses 754 # DTB read accesses +system.cpu.dtb.write_hits 380 # DTB write hits +system.cpu.dtb.write_misses 23 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 374 # DTB write accesses -system.cpu.dtb.data_hits 1035 # DTB hits -system.cpu.dtb.data_misses 44 # DTB misses +system.cpu.dtb.write_accesses 403 # DTB write accesses +system.cpu.dtb.data_hits 1091 # DTB hits +system.cpu.dtb.data_misses 66 # DTB misses system.cpu.dtb.data_acv 1 # DTB access violations -system.cpu.dtb.data_accesses 1079 # DTB accesses -system.cpu.itb.fetch_hits 941 # ITB hits -system.cpu.itb.fetch_misses 30 # ITB misses +system.cpu.dtb.data_accesses 1157 # DTB accesses +system.cpu.itb.fetch_hits 1067 # ITB hits +system.cpu.itb.fetch_misses 33 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 971 # ITB accesses +system.cpu.itb.fetch_accesses 1100 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -53,245 +53,246 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4 # Number of system calls -system.cpu.numCycles 13667 # number of cpu cycles simulated +system.cpu.numCycles 14031 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 1038 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 518 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 226 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 732 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 219 # Number of BTB hits +system.cpu.BPredUnit.lookups 1201 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 569 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 276 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 824 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 230 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 208 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 34 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 3757 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 6399 # Number of instructions fetch has processed -system.cpu.fetch.Branches 1038 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 427 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 1112 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 750 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 212 # Number of cycles fetch has spent blocked +system.cpu.BPredUnit.usedRAS 243 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 55 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 3890 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 7412 # Number of instructions fetch has processed +system.cpu.fetch.Branches 1201 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 473 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 1260 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 922 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 250 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 17 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 785 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 941 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 156 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 6383 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.002507 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.418848 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.PendingTrapStallCycles 780 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 1067 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 174 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 6820 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.086804 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.510240 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 5271 82.58% 82.58% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 60 0.94% 83.52% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 117 1.83% 85.35% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 94 1.47% 86.82% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 140 2.19% 89.02% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 57 0.89% 89.91% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 55 0.86% 90.77% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 64 1.00% 91.78% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 525 8.22% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 5560 81.52% 81.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 47 0.69% 82.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 133 1.95% 84.16% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 103 1.51% 85.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 148 2.17% 87.84% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 78 1.14% 88.99% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 68 1.00% 89.99% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 64 0.94% 90.92% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 619 9.08% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 6383 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.075949 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.468208 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 4647 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 226 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 1081 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 6 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 423 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 158 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 80 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 5725 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 284 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 423 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 4742 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 57 # Number of cycles rename is blocking +system.cpu.fetch.rateDist::total 6820 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.085596 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.528259 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 4790 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 271 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 1197 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 17 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 545 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 185 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 83 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 6535 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 298 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 545 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 4889 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 77 # Number of cycles rename is blocking system.cpu.rename.serializeStallCycles 147 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 995 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 19 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 5471 # Number of instructions processed by rename -system.cpu.rename.LSQFullEvents 14 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 3940 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 6152 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 6140 # Number of integer rename lookups +system.cpu.rename.RunCycles 1115 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 47 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 6259 # Number of instructions processed by rename +system.cpu.rename.IQFullEvents 17 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 24 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 4535 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 7053 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 7041 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 12 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1768 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 2172 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 2767 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 8 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 6 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 107 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 881 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 453 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 3 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 3 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 4657 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 6 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 3881 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 49 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 2074 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1177 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 6383 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.608021 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.298413 # Number of insts issued each cycle +system.cpu.rename.skidInsts 162 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 996 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 505 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 0 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 5232 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 7 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 4206 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 51 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 2612 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1532 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 3 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 6820 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.616716 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.331431 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 4813 75.40% 75.40% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 542 8.49% 83.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 388 6.08% 89.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 264 4.14% 94.11% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 199 3.12% 97.23% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 107 1.68% 98.90% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 55 0.86% 99.77% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 10 0.16% 99.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 5 0.08% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 5134 75.28% 75.28% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 613 8.99% 84.27% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 383 5.62% 89.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 269 3.94% 93.83% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 207 3.04% 96.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 134 1.96% 98.83% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 52 0.76% 99.59% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 14 0.21% 99.79% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 14 0.21% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 6383 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 6820 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 1 2.44% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 17 41.46% 43.90% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 23 56.10% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 5 11.63% 11.63% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 11.63% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 11.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 11.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 11.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 11.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.63% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 15 34.88% 46.51% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 23 53.49% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 2767 71.30% 71.30% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 1 0.03% 71.32% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 71.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 71.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 71.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 71.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 71.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 71.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 71.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 71.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 71.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 71.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 71.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 71.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 71.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 71.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 71.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 71.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 71.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 71.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 71.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 71.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 71.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 71.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 71.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 71.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 71.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 71.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 71.32% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 733 18.89% 90.21% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 380 9.79% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 2987 71.02% 71.02% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 1 0.02% 71.04% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 71.04% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 71.04% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 71.04% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 71.04% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 71.04% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 71.04% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 71.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 71.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 71.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 71.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 71.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 71.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 71.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 71.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 71.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 71.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 71.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 71.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 71.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 71.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 71.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 71.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 71.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 71.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 71.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 71.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 71.04% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 805 19.14% 90.18% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 413 9.82% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 3881 # Type of FU issued -system.cpu.iq.rate 0.283969 # Inst issue rate -system.cpu.iq.fu_busy_cnt 41 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.010564 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 14222 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 6735 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 3573 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 4206 # Type of FU issued +system.cpu.iq.rate 0.299765 # Inst issue rate +system.cpu.iq.fu_busy_cnt 43 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.010223 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 15313 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 7848 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 3807 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 13 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 6 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 6 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 3915 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 4242 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 7 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 35 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 33 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 466 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.squashedLoads 581 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 1 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 5 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 159 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 211 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 423 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 44 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 6 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 5001 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 64 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 881 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 453 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 6 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 3 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 545 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 53 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 17 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 5607 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 106 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 996 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 505 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 7 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 17 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 5 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 54 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 121 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 175 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 3749 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 706 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 132 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedTakenIncorrect 80 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 161 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 241 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 4005 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 757 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 201 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 338 # number of nop insts executed -system.cpu.iew.exec_refs 1080 # number of memory reference insts executed -system.cpu.iew.exec_branches 629 # Number of branches executed -system.cpu.iew.exec_stores 374 # Number of stores executed -system.cpu.iew.exec_rate 0.274310 # Inst execution rate -system.cpu.iew.wb_sent 3647 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 3579 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1702 # num instructions producing a value -system.cpu.iew.wb_consumers 2165 # num instructions consuming a value +system.cpu.iew.exec_nop 368 # number of nop insts executed +system.cpu.iew.exec_refs 1160 # number of memory reference insts executed +system.cpu.iew.exec_branches 681 # Number of branches executed +system.cpu.iew.exec_stores 403 # Number of stores executed +system.cpu.iew.exec_rate 0.285439 # Inst execution rate +system.cpu.iew.wb_sent 3920 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 3813 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1793 # num instructions producing a value +system.cpu.iew.wb_consumers 2339 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.261872 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.786143 # average fanout of values written-back +system.cpu.iew.wb_rate 0.271755 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.766567 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 2576 # The number of committed instructions system.cpu.commit.commitCommittedOps 2576 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 2416 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 3022 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 4 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 149 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 5960 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.432215 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.290536 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 198 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 6275 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.410518 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.252508 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 5068 85.03% 85.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 222 3.72% 88.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 314 5.27% 94.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 119 2.00% 96.02% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 70 1.17% 97.20% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 53 0.89% 98.09% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 34 0.57% 98.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 20 0.34% 98.99% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 60 1.01% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 5374 85.64% 85.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 226 3.60% 89.24% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 318 5.07% 94.31% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 120 1.91% 96.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 75 1.20% 97.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 53 0.84% 98.26% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 33 0.53% 98.79% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 17 0.27% 99.06% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 59 0.94% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 5960 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 6275 # Number of insts commited each cycle system.cpu.commit.committedInsts 2576 # Number of instructions committed system.cpu.commit.committedOps 2576 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -302,63 +303,63 @@ system.cpu.commit.branches 396 # Nu system.cpu.commit.fp_insts 6 # Number of committed floating point instructions. system.cpu.commit.int_insts 2367 # Number of committed integer instructions. system.cpu.commit.function_calls 71 # Number of function calls committed. -system.cpu.commit.bw_lim_events 60 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 59 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 10645 # The number of ROB reads -system.cpu.rob.rob_writes 10410 # The number of ROB writes -system.cpu.timesIdled 139 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 7284 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 11567 # The number of ROB reads +system.cpu.rob.rob_writes 11753 # The number of ROB writes +system.cpu.timesIdled 138 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 7211 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 2387 # Number of Instructions Simulated system.cpu.committedOps 2387 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 2387 # Number of Instructions Simulated -system.cpu.cpi 5.725597 # CPI: Cycles Per Instruction -system.cpu.cpi_total 5.725597 # CPI: Total CPI of All Threads -system.cpu.ipc 0.174654 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.174654 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 4520 # number of integer regfile reads -system.cpu.int_regfile_writes 2768 # number of integer regfile writes +system.cpu.cpi 5.878090 # CPI: Cycles Per Instruction +system.cpu.cpi_total 5.878090 # CPI: Total CPI of All Threads +system.cpu.ipc 0.170123 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.170123 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 4832 # number of integer regfile reads +system.cpu.int_regfile_writes 2958 # number of integer regfile writes system.cpu.fp_regfile_reads 6 # number of floating regfile reads system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 91.574139 # Cycle average of tags in use -system.cpu.icache.total_refs 700 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 185 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 3.783784 # Average number of references to valid blocks. +system.cpu.icache.tagsinuse 93.540284 # Cycle average of tags in use +system.cpu.icache.total_refs 817 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 189 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 4.322751 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 91.574139 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.044714 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.044714 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 700 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 700 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 700 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 700 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 700 # number of overall hits -system.cpu.icache.overall_hits::total 700 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 241 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 241 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 241 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 241 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 241 # number of overall misses -system.cpu.icache.overall_misses::total 241 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 8777500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 8777500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 8777500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 8777500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 8777500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 8777500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 941 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 941 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 941 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 941 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 941 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 941 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.256111 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.256111 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.256111 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 36421.161826 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 36421.161826 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 36421.161826 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 93.540284 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.045674 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.045674 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 817 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 817 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 817 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 817 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 817 # number of overall hits +system.cpu.icache.overall_hits::total 817 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 250 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 250 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 250 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 250 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 250 # number of overall misses +system.cpu.icache.overall_misses::total 250 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 8957500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 8957500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 8957500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 8957500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 8957500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 8957500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1067 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1067 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1067 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1067 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1067 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1067 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.234302 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.234302 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.234302 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35830 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 35830 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 35830 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -367,80 +368,80 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 56 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 56 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 56 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 56 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 56 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 56 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 185 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 185 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 185 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 185 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 185 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 185 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 6554500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 6554500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 6554500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 6554500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 6554500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 6554500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.196599 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.196599 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.196599 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35429.729730 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35429.729730 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35429.729730 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 61 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 61 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 61 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 61 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 61 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 61 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 189 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 189 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 189 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 189 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 189 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 189 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 6695500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 6695500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 6695500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 6695500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 6695500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 6695500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.177132 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.177132 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.177132 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35425.925926 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35425.925926 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35425.925926 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 45.439198 # Cycle average of tags in use -system.cpu.dcache.total_refs 765 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 85 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 9 # Average number of references to valid blocks. +system.cpu.dcache.tagsinuse 46.152964 # Cycle average of tags in use +system.cpu.dcache.total_refs 793 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 86 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 9.220930 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 45.439198 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.011094 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.011094 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 543 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 543 # number of ReadReq hits +system.cpu.dcache.occ_blocks::cpu.data 46.152964 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.011268 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.011268 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 571 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 571 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 222 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 222 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 765 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 765 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 765 # number of overall hits -system.cpu.dcache.overall_hits::total 765 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 101 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 101 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 793 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 793 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 793 # number of overall hits +system.cpu.dcache.overall_hits::total 793 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 107 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 107 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 72 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 72 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 173 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 173 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 173 # number of overall misses -system.cpu.dcache.overall_misses::total 173 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 3605000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 3605000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 2816500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 2816500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 6421500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 6421500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 6421500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 6421500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 644 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 644 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 179 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 179 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 179 # number of overall misses +system.cpu.dcache.overall_misses::total 179 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 3676500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 3676500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 2816000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 2816000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 6492500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 6492500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 6492500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 6492500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 678 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 678 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 294 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 294 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 938 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 938 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 938 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 938 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.156832 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 972 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 972 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 972 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 972 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.157817 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.244898 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.184435 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.184435 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 35693.069307 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39118.055556 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 37118.497110 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 37118.497110 # average overall miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.184156 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.184156 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34359.813084 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39111.111111 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 36270.949721 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 36270.949721 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -449,83 +450,83 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 40 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 40 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 45 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 45 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 48 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 48 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 88 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 88 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 88 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 88 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 61 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 61 # number of ReadReq MSHR misses +system.cpu.dcache.demand_mshr_hits::cpu.data 93 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 93 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 93 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 93 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 62 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 62 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 24 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 24 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 85 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 85 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 85 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 85 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2169000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2169000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 872000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 872000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 3041000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 3041000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 3041000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 3041000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.094720 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_misses::cpu.data 86 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 86 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 86 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 86 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2205000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2205000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 873500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 873500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 3078500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 3078500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 3078500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 3078500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.091445 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.081633 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.090618 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.090618 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 35557.377049 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 36333.333333 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 35776.470588 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 35776.470588 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.088477 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.088477 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 35564.516129 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 36395.833333 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 35796.511628 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 35796.511628 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 120.203882 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 122.732805 # Cycle average of tags in use system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 246 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 251 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 91.660485 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 28.543397 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.002797 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.000871 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.003668 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_misses::cpu.inst 185 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 61 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 246 # number of ReadReq misses +system.cpu.l2cache.occ_blocks::cpu.inst 93.626172 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 29.106633 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.002857 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.000888 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.003746 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_misses::cpu.inst 189 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 62 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 251 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 24 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 24 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 185 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 85 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 270 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 185 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 85 # number of overall misses -system.cpu.l2cache.overall_misses::total 270 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 6346000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2101500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 8447500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 831000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 831000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 6346000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 2932500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 9278500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 6346000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 2932500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 9278500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 185 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 61 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 246 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.demand_misses::cpu.inst 189 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 86 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 275 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 189 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 86 # number of overall misses +system.cpu.l2cache.overall_misses::total 275 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 6484000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2135500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 8619500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 832000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 832000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 6484000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 2967500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 9451500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 6484000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 2967500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 9451500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 189 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 62 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 251 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 24 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 24 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 185 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 85 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 270 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 185 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 85 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 270 # number of overall (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 189 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 86 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 275 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 189 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 86 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 275 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses @@ -533,13 +534,13 @@ system.cpu.l2cache.demand_miss_rate::cpu.inst 1 system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34302.702703 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34450.819672 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34625 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34302.702703 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34500 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34302.702703 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34500 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34306.878307 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34443.548387 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34666.666667 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34306.878307 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34505.813953 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34306.878307 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34505.813953 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -548,28 +549,28 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 185 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 61 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 246 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 189 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 62 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 251 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 24 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 24 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 185 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 85 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 270 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 185 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 85 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 270 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 5756000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1905500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 7661500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 756000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 756000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 5756000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 2661500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 8417500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 5756000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 2661500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 8417500 # number of overall MSHR miss cycles +system.cpu.l2cache.demand_mshr_misses::cpu.inst 189 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 86 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 275 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 189 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 86 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 275 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 5881500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1936500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 7818000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 757500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 757500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 5881500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 2694000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 8575500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 5881500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 2694000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 8575500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses @@ -577,13 +578,13 @@ system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31113.513514 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31237.704918 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31500 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31113.513514 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31311.764706 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31113.513514 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31311.764706 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31119.047619 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31233.870968 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31562.500000 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31119.047619 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31325.581395 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31119.047619 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31325.581395 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout index ab1ef55e9..e7e46b503 100755 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout @@ -1,11 +1,11 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 11 2012 13:10:40 -gem5 started Feb 11 2012 15:35:50 +gem5 compiled Feb 12 2012 17:19:56 +gem5 started Feb 12 2012 19:57:12 gem5 executing on zizzer command line: build/ARM/gem5.fast -d build/ARM/tests/fast/quick/se/00.hello/arm/linux/o3-timing -re tests/run.py build/ARM/tests/fast/quick/se/00.hello/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 10000500 because target called exit() +Exiting @ tick 10389500 because target called exit() diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt index 010933949..6eeb02481 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt @@ -1,25 +1,25 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000010 # Number of seconds simulated -sim_ticks 10000500 # Number of ticks simulated -final_tick 10000500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 10389500 # Number of ticks simulated +final_tick 10389500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 72927 # Simulator instruction rate (inst/s) -host_op_rate 90959 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 158457261 # Simulator tick rate (ticks/s) -host_mem_usage 221260 # Number of bytes of host memory used -host_seconds 0.06 # Real time elapsed on the host +host_inst_rate 66059 # Simulator instruction rate (inst/s) +host_op_rate 82394 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 149123755 # Simulator tick rate (ticks/s) +host_mem_usage 221320 # Number of bytes of host memory used +host_seconds 0.07 # Real time elapsed on the host sim_insts 4600 # Number of instructions simulated sim_ops 5739 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 25856 # Number of bytes read from this memory -system.physmem.bytes_inst_read 17856 # Number of instructions bytes read from this memory +system.physmem.bytes_read 25600 # Number of bytes read from this memory +system.physmem.bytes_inst_read 17664 # Number of instructions bytes read from this memory system.physmem.bytes_written 0 # Number of bytes written to this memory -system.physmem.num_reads 404 # Number of read requests responded to by this memory +system.physmem.num_reads 400 # Number of read requests responded to by this memory system.physmem.num_writes 0 # Number of write requests responded to by this memory system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 2585470726 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 1785510724 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total 2585470726 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read 2464026180 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 1700178064 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total 2464026180 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -63,245 +63,246 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 13 # Number of system calls -system.cpu.numCycles 20002 # number of cpu cycles simulated +system.cpu.numCycles 20780 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 2398 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 1771 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 436 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 1789 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 703 # Number of BTB hits +system.cpu.BPredUnit.lookups 2550 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 1890 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 477 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 1987 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 688 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 246 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 51 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 6118 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 12133 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2398 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 949 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 2694 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1578 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 1626 # Number of cycles fetch has spent blocked +system.cpu.BPredUnit.usedRAS 244 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 55 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 6285 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 13028 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2550 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 932 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 2849 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1782 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 1735 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 2 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 19 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 1919 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 303 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 11508 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.338286 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.716814 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.PendingTrapStallCycles 42 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 2028 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 296 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 12124 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.372402 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.762919 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 8814 76.59% 76.59% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 262 2.28% 78.87% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 169 1.47% 80.34% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 225 1.96% 82.29% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 227 1.97% 84.26% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 313 2.72% 86.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 109 0.95% 87.93% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 113 0.98% 88.91% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1276 11.09% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 9275 76.50% 76.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 244 2.01% 78.51% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 198 1.63% 80.15% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 226 1.86% 82.01% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 226 1.86% 83.87% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 278 2.29% 86.17% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 125 1.03% 87.20% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 139 1.15% 88.35% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1413 11.65% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 11508 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.119888 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.606589 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 6263 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 1809 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2491 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 58 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 887 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 401 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 168 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 13387 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 587 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 887 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 6539 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 230 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 1411 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2270 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 171 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 12504 # Number of instructions processed by rename -system.cpu.rename.LSQFullEvents 153 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 12063 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 57218 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 56026 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 1192 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 12124 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.122714 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.626949 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 6488 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 1902 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 2634 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 56 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1044 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 445 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 175 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 14514 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 580 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1044 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 6777 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 274 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 1438 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 2397 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 194 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 13625 # Number of instructions processed by rename +system.cpu.rename.IQFullEvents 14 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 154 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 13271 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 62674 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 61282 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 1392 # Number of floating rename lookups system.cpu.rename.CommittedMaps 5684 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 6379 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 41 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 39 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 478 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2574 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1703 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 9 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 8 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 10784 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 49 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 8706 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 95 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 4802 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 13397 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 12 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 11508 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.756517 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.438154 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 7587 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 48 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 46 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 646 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2866 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1785 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 16 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 12 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 11782 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 56 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 9138 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 109 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 5710 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 16685 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 19 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 12124 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.753712 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.440468 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 8023 69.72% 69.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1281 11.13% 80.85% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 772 6.71% 87.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 541 4.70% 92.26% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 447 3.88% 96.14% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 256 2.22% 98.37% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 137 1.19% 99.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 40 0.35% 99.90% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 11 0.10% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 8489 70.02% 70.02% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1331 10.98% 81.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 789 6.51% 87.50% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 561 4.63% 92.13% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 477 3.93% 96.07% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 294 2.42% 98.49% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 126 1.04% 99.53% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 44 0.36% 99.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 13 0.11% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 11508 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 12124 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 2 0.99% 0.99% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 0.99% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 0.99% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.99% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.99% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.99% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 0.99% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.99% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 0.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 0.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.99% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 137 67.49% 68.47% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 64 31.53% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 2 0.93% 0.93% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 0.93% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 0.93% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.93% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.93% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.93% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 0.93% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.93% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 0.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 0.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.93% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 150 69.77% 70.70% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 63 29.30% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 5272 60.56% 60.56% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 6 0.07% 60.62% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.62% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.62% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.62% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.62% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.62% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.62% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.66% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2203 25.30% 85.96% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1222 14.04% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 5491 60.09% 60.09% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 7 0.08% 60.17% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.17% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.17% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.17% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.17% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.17% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.17% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2383 26.08% 86.28% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1254 13.72% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 8706 # Type of FU issued -system.cpu.iq.rate 0.435256 # Inst issue rate -system.cpu.iq.fu_busy_cnt 203 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.023317 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 29182 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 15632 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 7824 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 9138 # Type of FU issued +system.cpu.iq.rate 0.439750 # Inst issue rate +system.cpu.iq.fu_busy_cnt 215 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.023528 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 30688 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 17549 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 8140 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 16 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 8889 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 9333 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 51 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 60 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1373 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1665 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 14 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 765 # Number of stores squashed +system.cpu.iew.lsq.thread0.memOrderViolation 19 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 847 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 887 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 121 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 8 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 10834 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 1044 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 169 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 21 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 11839 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 179 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2574 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1703 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 37 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewDispLoadInsts 2866 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1785 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 44 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 13 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 14 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 90 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 295 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 385 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 8282 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 2009 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 424 # Number of squashed instructions skipped in execute +system.cpu.iew.memOrderViolationEvents 19 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 100 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 326 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 426 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 8635 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 2130 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 503 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 1 # number of nop insts executed -system.cpu.iew.exec_refs 3178 # number of memory reference insts executed -system.cpu.iew.exec_branches 1354 # Number of branches executed -system.cpu.iew.exec_stores 1169 # Number of stores executed -system.cpu.iew.exec_rate 0.414059 # Inst execution rate -system.cpu.iew.wb_sent 7957 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 7840 # cumulative count of insts written-back -system.cpu.iew.wb_producers 3690 # num instructions producing a value -system.cpu.iew.wb_consumers 7291 # num instructions consuming a value +system.cpu.iew.exec_refs 3325 # number of memory reference insts executed +system.cpu.iew.exec_branches 1404 # Number of branches executed +system.cpu.iew.exec_stores 1195 # Number of stores executed +system.cpu.iew.exec_rate 0.415544 # Inst execution rate +system.cpu.iew.wb_sent 8328 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 8156 # cumulative count of insts written-back +system.cpu.iew.wb_producers 3863 # num instructions producing a value +system.cpu.iew.wb_consumers 7813 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.391961 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.506103 # average fanout of values written-back +system.cpu.iew.wb_rate 0.392493 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.494432 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 4600 # The number of committed instructions system.cpu.commit.commitCommittedOps 5739 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 5094 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 6099 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 345 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 10622 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.540294 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.352838 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 380 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 11081 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.517914 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.332416 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 8286 78.01% 78.01% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1088 10.24% 88.25% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 420 3.95% 92.20% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 282 2.65% 94.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 183 1.72% 96.58% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 168 1.58% 98.16% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 65 0.61% 98.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 37 0.35% 99.12% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 93 0.88% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 8736 78.84% 78.84% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1106 9.98% 88.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 431 3.89% 92.71% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 257 2.32% 95.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 182 1.64% 96.67% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 177 1.60% 98.27% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 55 0.50% 98.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 39 0.35% 99.12% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 98 0.88% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 10622 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 11081 # Number of insts commited each cycle system.cpu.commit.committedInsts 4600 # Number of instructions committed system.cpu.commit.committedOps 5739 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -312,63 +313,63 @@ system.cpu.commit.branches 945 # Nu system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. system.cpu.commit.int_insts 4985 # Number of committed integer instructions. system.cpu.commit.function_calls 82 # Number of function calls committed. -system.cpu.commit.bw_lim_events 93 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 98 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 21205 # The number of ROB reads -system.cpu.rob.rob_writes 22566 # The number of ROB writes -system.cpu.timesIdled 180 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 8494 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 22664 # The number of ROB reads +system.cpu.rob.rob_writes 24737 # The number of ROB writes +system.cpu.timesIdled 179 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 8656 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 4600 # Number of Instructions Simulated system.cpu.committedOps 5739 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 4600 # Number of Instructions Simulated -system.cpu.cpi 4.348261 # CPI: Cycles Per Instruction -system.cpu.cpi_total 4.348261 # CPI: Total CPI of All Threads -system.cpu.ipc 0.229977 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.229977 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 37816 # number of integer regfile reads -system.cpu.int_regfile_writes 7658 # number of integer regfile writes +system.cpu.cpi 4.517391 # CPI: Cycles Per Instruction +system.cpu.cpi_total 4.517391 # CPI: Total CPI of All Threads +system.cpu.ipc 0.221367 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.221367 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 39570 # number of integer regfile reads +system.cpu.int_regfile_writes 8020 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.misc_regfile_reads 14992 # number of misc regfile reads +system.cpu.misc_regfile_reads 16023 # number of misc regfile reads system.cpu.misc_regfile_writes 24 # number of misc regfile writes system.cpu.icache.replacements 2 # number of replacements -system.cpu.icache.tagsinuse 148.855822 # Cycle average of tags in use -system.cpu.icache.total_refs 1559 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 297 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 5.249158 # Average number of references to valid blocks. +system.cpu.icache.tagsinuse 152.513802 # Cycle average of tags in use +system.cpu.icache.total_refs 1663 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 296 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 5.618243 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 148.855822 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.072684 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.072684 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 1559 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1559 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1559 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1559 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1559 # number of overall hits -system.cpu.icache.overall_hits::total 1559 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 360 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 360 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 360 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 360 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 360 # number of overall misses -system.cpu.icache.overall_misses::total 360 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 12552000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 12552000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 12552000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 12552000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 12552000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 12552000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1919 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1919 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1919 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1919 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1919 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1919 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.187598 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.187598 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.187598 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34866.666667 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 34866.666667 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 34866.666667 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 152.513802 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.074470 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.074470 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 1663 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1663 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1663 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1663 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1663 # number of overall hits +system.cpu.icache.overall_hits::total 1663 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 365 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 365 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 365 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 365 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 365 # number of overall misses +system.cpu.icache.overall_misses::total 365 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 12618000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 12618000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 12618000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 12618000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 12618000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 12618000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 2028 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 2028 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 2028 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 2028 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 2028 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 2028 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.179980 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.179980 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.179980 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34569.863014 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 34569.863014 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 34569.863014 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -377,94 +378,94 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 63 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 63 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 63 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 63 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 63 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 63 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 297 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 297 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 297 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 297 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 297 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 297 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9945000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 9945000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9945000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 9945000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9945000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 9945000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.154768 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.154768 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.154768 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 33484.848485 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 33484.848485 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 33484.848485 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 69 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 69 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 69 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 69 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 69 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 69 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 296 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 296 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 296 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 296 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 296 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 296 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9837000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 9837000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9837000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 9837000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9837000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 9837000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.145957 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.145957 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.145957 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 33233.108108 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 33233.108108 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 33233.108108 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 89.085552 # Cycle average of tags in use -system.cpu.dcache.total_refs 2331 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 154 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 15.136364 # Average number of references to valid blocks. +system.cpu.dcache.tagsinuse 87.512831 # Cycle average of tags in use +system.cpu.dcache.total_refs 2409 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 149 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 16.167785 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 89.085552 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.021749 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.021749 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 1702 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1702 # number of ReadReq hits +system.cpu.dcache.occ_blocks::cpu.data 87.512831 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.021365 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.021365 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 1780 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1780 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 609 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 609 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 9 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 9 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 2311 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2311 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2311 # number of overall hits -system.cpu.dcache.overall_hits::total 2311 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 169 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 169 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 2389 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2389 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2389 # number of overall hits +system.cpu.dcache.overall_hits::total 2389 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 170 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 170 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 304 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 304 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 473 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 473 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 473 # number of overall misses -system.cpu.dcache.overall_misses::total 473 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5350500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5350500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 10725000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 10725000 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 474 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 474 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 474 # number of overall misses +system.cpu.dcache.overall_misses::total 474 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5506000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5506000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 10844000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 10844000 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 76500 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 76500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 16075500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 16075500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 16075500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 16075500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1871 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1871 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 16350000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 16350000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 16350000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 16350000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1950 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1950 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 11 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2784 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2784 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2784 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2784 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.090326 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 2863 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2863 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2863 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2863 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.087179 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.332968 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.181818 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.169899 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.169899 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 31659.763314 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35279.605263 # average WriteReq miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.165561 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.165561 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32388.235294 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35671.052632 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 38250 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 33986.257928 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 33986.257928 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 34493.670886 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 34493.670886 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -473,108 +474,108 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 57 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 57 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 63 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 63 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 262 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 262 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 319 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 319 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 319 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 319 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 112 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 112 # number of ReadReq MSHR misses +system.cpu.dcache.demand_mshr_hits::cpu.data 325 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 325 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 325 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 325 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 107 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 107 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 42 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 42 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 154 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 154 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 154 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 154 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3230000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 3230000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1505000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1505000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 4735000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 4735000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 4735000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 4735000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.059861 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_misses::cpu.data 149 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 149 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 149 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 149 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3156500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 3156500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1501500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1501500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 4658000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 4658000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 4658000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 4658000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.054872 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.046002 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.055316 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.055316 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 28839.285714 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35833.333333 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 30746.753247 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 30746.753247 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.052043 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.052043 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 29500 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35750 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 31261.744966 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 31261.744966 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 188.110462 # Cycle average of tags in use -system.cpu.l2cache.total_refs 42 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 362 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.116022 # Average number of references to valid blocks. +system.cpu.l2cache.tagsinuse 189.446862 # Cycle average of tags in use +system.cpu.l2cache.total_refs 41 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 358 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.114525 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 140.315748 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 47.794714 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.004282 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.001459 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.005741 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 18 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 24 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 42 # number of ReadReq hits -system.cpu.l2cache.demand_hits::cpu.inst 18 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 24 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 42 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 18 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 24 # number of overall hits -system.cpu.l2cache.overall_hits::total 42 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 279 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 88 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 367 # number of ReadReq misses +system.cpu.l2cache.occ_blocks::cpu.inst 142.892597 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 46.554265 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.004361 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.001421 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.005781 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 20 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 21 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 41 # number of ReadReq hits +system.cpu.l2cache.demand_hits::cpu.inst 20 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 21 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 41 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 20 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 21 # number of overall hits +system.cpu.l2cache.overall_hits::total 41 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 276 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 86 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 362 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 42 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 42 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 279 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 130 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 409 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 279 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 130 # number of overall misses -system.cpu.l2cache.overall_misses::total 409 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 9586000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3027500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 12613500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1452000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 1452000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 9586000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 4479500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 14065500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 9586000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 4479500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 14065500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 297 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 112 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 409 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.demand_misses::cpu.inst 276 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 128 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 404 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 276 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 128 # number of overall misses +system.cpu.l2cache.overall_misses::total 404 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 9478000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2963500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 12441500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1446500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 1446500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 9478000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 4410000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 13888000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 9478000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 4410000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 13888000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 296 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 107 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 403 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 42 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 42 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 297 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 154 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 451 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 297 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 154 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 451 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.939394 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.785714 # miss rate for ReadReq accesses +system.cpu.l2cache.demand_accesses::cpu.inst 296 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 149 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 445 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 296 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 149 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 445 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.932432 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.803738 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.939394 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.844156 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.939394 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.844156 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34358.422939 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34403.409091 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34571.428571 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34358.422939 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34457.692308 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34358.422939 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34457.692308 # average overall miss latency +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.932432 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.859060 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.932432 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.859060 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34340.579710 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34459.302326 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34440.476190 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34340.579710 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34453.125000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34340.579710 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34453.125000 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -583,48 +584,48 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 5 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 5 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 5 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 5 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 5 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 5 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 279 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 83 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 362 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 4 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 4 # number of ReadReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 4 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 4 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 4 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 4 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 276 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 82 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 358 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 42 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 42 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 279 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 125 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 404 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 279 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 125 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 404 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 8692000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2612000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 11304000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1319000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1319000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 8692000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3931000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 12623000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 8692000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3931000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 12623000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.939394 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.741071 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 276 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 124 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 400 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 276 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 124 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 400 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 8590500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2580000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 11170500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1315000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1315000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 8590500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3895000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 12485500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 8590500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3895000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 12485500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.932432 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.766355 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.939394 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.811688 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.939394 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.811688 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31154.121864 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31469.879518 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31404.761905 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31154.121864 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31448 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31154.121864 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31448 # average overall mshr miss latency +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.932432 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.832215 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.932432 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.832215 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31125 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31463.414634 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31309.523810 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31125 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31411.290323 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31125 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31411.290323 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/simout b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/simout index 9f59be0ce..e34fa5006 100755 --- a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/simout +++ b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 11 2012 13:07:32 -gem5 started Feb 11 2012 13:54:30 +gem5 compiled Feb 12 2012 17:16:48 +gem5 started Feb 12 2012 18:16:47 gem5 executing on zizzer command line: build/MIPS/gem5.fast -d build/MIPS/tests/fast/quick/se/00.hello/mips/linux/inorder-timing -re tests/run.py build/MIPS/tests/fast/quick/se/00.hello/mips/linux/inorder-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello World! -Exiting @ tick 19785000 because target called exit() +Exiting @ tick 19775000 because target called exit() diff --git a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt index 6cd55fbff..e8bd2f84c 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000020 # Number of seconds simulated -sim_ticks 19785000 # Number of ticks simulated -final_tick 19785000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 19775000 # Number of ticks simulated +final_tick 19775000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 101976 # Simulator instruction rate (inst/s) -host_op_rate 101944 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 346042004 # Simulator tick rate (ticks/s) -host_mem_usage 210372 # Number of bytes of host memory used -host_seconds 0.06 # Real time elapsed on the host +host_inst_rate 108846 # Simulator instruction rate (inst/s) +host_op_rate 108810 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 369151681 # Simulator tick rate (ticks/s) +host_mem_usage 210376 # Number of bytes of host memory used +host_seconds 0.05 # Real time elapsed on the host sim_insts 5827 # Number of instructions simulated sim_ops 5827 # Number of ops (including micro ops) simulated system.physmem.bytes_read 29120 # Number of bytes read from this memory @@ -17,9 +17,9 @@ system.physmem.bytes_written 0 # Nu system.physmem.num_reads 455 # Number of read requests responded to by this memory system.physmem.num_writes 0 # Number of write requests responded to by this memory system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 1471822087 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 1025423300 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total 1471822087 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read 1472566372 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 1025941846 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total 1472566372 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses system.cpu.dtb.read_accesses 0 # DTB read accesses @@ -39,16 +39,16 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 8 # Number of system calls -system.cpu.numCycles 39571 # number of cpu cycles simulated +system.cpu.numCycles 39551 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 9159 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 9142 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 403 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 34166 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 5405 # Number of cycles cpu stages are processed. -system.cpu.activity 13.658993 # Percentage of cycles cpu is active +system.cpu.timesIdled 404 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 34183 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 5368 # Number of cycles cpu stages are processed. +system.cpu.activity 13.572350 # Percentage of cycles cpu is active system.cpu.comLoads 1164 # Number of Load instructions committed system.cpu.comStores 925 # Number of Store instructions committed system.cpu.comBranches 916 # Number of Branches instructions committed @@ -60,92 +60,92 @@ system.cpu.committedInsts 5827 # Nu system.cpu.committedOps 5827 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 5827 # Number of Instructions committed (Total) -system.cpu.cpi 6.790973 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 6.787541 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi no_value # CPI: Total SMT-CPI -system.cpu.cpi_total 6.790973 # CPI: Total CPI of All Threads -system.cpu.ipc 0.147254 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 6.787541 # CPI: Total CPI of All Threads +system.cpu.ipc 0.147329 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc no_value # IPC: Total SMT-IPC -system.cpu.ipc_total 0.147254 # IPC: Total IPC of All Threads -system.cpu.branch_predictor.lookups 1185 # Number of BP lookups -system.cpu.branch_predictor.condPredicted 896 # Number of conditional branches predicted -system.cpu.branch_predictor.condIncorrect 611 # Number of conditional branches incorrect -system.cpu.branch_predictor.BTBLookups 1035 # Number of BTB lookups -system.cpu.branch_predictor.BTBHits 443 # Number of BTB hits +system.cpu.ipc_total 0.147329 # IPC: Total IPC of All Threads +system.cpu.branch_predictor.lookups 1152 # Number of BP lookups +system.cpu.branch_predictor.condPredicted 851 # Number of conditional branches predicted +system.cpu.branch_predictor.condIncorrect 605 # Number of conditional branches incorrect +system.cpu.branch_predictor.BTBLookups 867 # Number of BTB lookups +system.cpu.branch_predictor.BTBHits 309 # Number of BTB hits system.cpu.branch_predictor.usedRAS 86 # Number of times the RAS was used to get a target. system.cpu.branch_predictor.RASInCorrect 32 # Number of incorrect RAS predictions. -system.cpu.branch_predictor.BTBHitPct 42.801932 # BTB Hit Percentage -system.cpu.branch_predictor.predictedTaken 536 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.predictedNotTaken 649 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 5108 # Number of Reads from Int. Register File +system.cpu.branch_predictor.BTBHitPct 35.640138 # BTB Hit Percentage +system.cpu.branch_predictor.predictedTaken 402 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.predictedNotTaken 750 # Number of Branches Predicted As Not Taken (False). +system.cpu.regfile_manager.intRegFileReads 5104 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 3408 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 8516 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.intRegFileAccesses 8512 # Total Accesses (Read+Write) to the Int. Register File system.cpu.regfile_manager.floatRegFileReads 3 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 1 # Number of Writes to FP Register File system.cpu.regfile_manager.floatRegFileAccesses 4 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 1344 # Number of Registers Read Through Forwarding Logic -system.cpu.agen_unit.agens 2228 # Number of Address Generations -system.cpu.execution_unit.predictedTakenIncorrect 317 # Number of Branches Incorrectly Predicted As Taken. -system.cpu.execution_unit.predictedNotTakenIncorrect 285 # Number of Branches Incorrectly Predicted As Not Taken). -system.cpu.execution_unit.mispredicted 602 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.predicted 314 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.mispredictPct 65.720524 # Percentage of Incorrect Branches Predicts -system.cpu.execution_unit.executions 3132 # Number of Instructions Executed. +system.cpu.regfile_manager.regForwards 1330 # Number of Registers Read Through Forwarding Logic +system.cpu.agen_unit.agens 2238 # Number of Address Generations +system.cpu.execution_unit.predictedTakenIncorrect 262 # Number of Branches Incorrectly Predicted As Taken. +system.cpu.execution_unit.predictedNotTakenIncorrect 334 # Number of Branches Incorrectly Predicted As Not Taken). +system.cpu.execution_unit.mispredicted 596 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.predicted 320 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.mispredictPct 65.065502 # Percentage of Incorrect Branches Predicts +system.cpu.execution_unit.executions 3155 # Number of Instructions Executed. system.cpu.mult_div_unit.multiplies 3 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 1 # Number of Divide Operations Executed -system.cpu.stage0.idleCycles 35846 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 3725 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 9.413459 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 36723 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 2848 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 7.197190 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 36778 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 2793 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 7.058199 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 38328 # Number of cycles 0 instructions are processed. +system.cpu.stage0.idleCycles 35911 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 3640 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 9.203307 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 36722 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 2829 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 7.152790 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 36760 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 2791 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 7.056712 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 38308 # Number of cycles 0 instructions are processed. system.cpu.stage3.runCycles 1243 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 3.141189 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 36666 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 2905 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 7.341235 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.utilization 3.142778 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 36647 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 2904 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 7.342419 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.replacements 13 # number of replacements -system.cpu.icache.tagsinuse 148.138598 # Cycle average of tags in use -system.cpu.icache.total_refs 443 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 148.175887 # Cycle average of tags in use +system.cpu.icache.total_refs 411 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 319 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 1.388715 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 1.288401 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 148.138598 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.072333 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.072333 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 443 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 443 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 443 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 443 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 443 # number of overall hits -system.cpu.icache.overall_hits::total 443 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 341 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 341 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 341 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 341 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 341 # number of overall misses -system.cpu.icache.overall_misses::total 341 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 19027500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 19027500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 19027500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 19027500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 19027500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 19027500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 784 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 784 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 784 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 784 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 784 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 784 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.434949 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.434949 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.434949 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55799.120235 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 55799.120235 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 55799.120235 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 148.175887 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.072352 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.072352 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 411 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 411 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 411 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 411 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 411 # number of overall hits +system.cpu.icache.overall_hits::total 411 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 343 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 343 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 343 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 343 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 343 # number of overall misses +system.cpu.icache.overall_misses::total 343 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 19128500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 19128500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 19128500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 19128500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 19128500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 19128500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 754 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 754 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 754 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 754 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 754 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 754 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.454907 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.454907 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.454907 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55768.221574 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 55768.221574 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 55768.221574 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 29000 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -154,40 +154,40 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets 29000 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 22 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 22 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 22 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 22 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 22 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 22 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 24 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 24 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 24 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 24 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 24 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 24 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 319 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 319 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 319 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 319 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 319 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 319 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 16952500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 16952500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 16952500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 16952500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 16952500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 16952500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.406888 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.406888 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.406888 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53142.633229 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53142.633229 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53142.633229 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 16951500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 16951500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 16951500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 16951500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 16951500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 16951500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.423077 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.423077 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.423077 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53139.498433 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53139.498433 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53139.498433 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 89.732679 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 89.746602 # Cycle average of tags in use system.cpu.dcache.total_refs 1838 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 138 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 13.318841 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 89.732679 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.021907 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.021907 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::cpu.data 89.746602 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.021911 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.021911 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 1075 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1075 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 763 # number of WriteReq hits @@ -206,12 +206,12 @@ system.cpu.dcache.overall_misses::cpu.data 251 # system.cpu.dcache.overall_misses::total 251 # number of overall misses system.cpu.dcache.ReadReq_miss_latency::cpu.data 5072500 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::total 5072500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 8912000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 8912000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 13984500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 13984500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 13984500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 13984500 # number of overall miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 8910500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 8910500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 13983000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 13983000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 13983000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 13983000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 1164 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1164 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 925 # number of WriteReq accesses(hits+misses) @@ -225,9 +225,9 @@ system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.175135 system.cpu.dcache.demand_miss_rate::cpu.data 0.120153 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.120153 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56994.382022 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55012.345679 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 55715.139442 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 55715.139442 # average overall miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55003.086420 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 55709.163347 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 55709.163347 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 1153500 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -254,32 +254,32 @@ system.cpu.dcache.overall_mshr_misses::cpu.data 138 system.cpu.dcache.overall_mshr_misses::total 138 # number of overall MSHR misses system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4702500 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::total 4702500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2746000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2746000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7448500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 7448500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7448500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 7448500 # number of overall MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2745500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2745500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7448000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 7448000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7448000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 7448000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.074742 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055135 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.066060 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.066060 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 54051.724138 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53843.137255 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53974.637681 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53974.637681 # average overall mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53833.333333 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53971.014493 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53971.014493 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 205.469583 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 205.517886 # Cycle average of tags in use system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 404 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.004950 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 149.779235 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 55.690348 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.004571 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 149.817885 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 55.700002 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.004572 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.001700 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.006270 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.006272 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits @@ -297,17 +297,17 @@ system.cpu.l2cache.demand_misses::total 455 # nu system.cpu.l2cache.overall_misses::cpu.inst 317 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 138 # number of overall misses system.cpu.l2cache.overall_misses::total 455 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 16585500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 16585000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4585000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 21170500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2682500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 2682500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 16585500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 7267500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 23853000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 16585500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 7267500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 23853000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 21170000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2682000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 2682000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 16585000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 7267000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 23852000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 16585000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 7267000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 23852000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 319 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 87 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 406 # number of ReadReq accesses(hits+misses) @@ -326,13 +326,13 @@ system.cpu.l2cache.demand_miss_rate::cpu.inst 0.993730 system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993730 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52320.189274 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52318.611987 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52701.149425 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52598.039216 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52320.189274 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52663.043478 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52320.189274 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52663.043478 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52588.235294 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52318.611987 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52659.420290 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52318.611987 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52659.420290 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked diff --git a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/simout index afa267678..e545392ce 100755 --- a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/simout +++ b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 11 2012 13:07:32 -gem5 started Feb 11 2012 13:54:39 +gem5 compiled Feb 12 2012 17:16:48 +gem5 started Feb 12 2012 18:16:57 gem5 executing on zizzer command line: build/MIPS/gem5.fast -d build/MIPS/tests/fast/quick/se/00.hello/mips/linux/o3-timing -re tests/run.py build/MIPS/tests/fast/quick/se/00.hello/mips/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello World! -Exiting @ tick 12272500 because target called exit() +Exiting @ tick 12671500 because target called exit() diff --git a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt index 9ff42644b..f9bef2483 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt @@ -1,25 +1,25 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000012 # Number of seconds simulated -sim_ticks 12272500 # Number of ticks simulated -final_tick 12272500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000013 # Number of seconds simulated +sim_ticks 12671500 # Number of ticks simulated +final_tick 12671500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 97350 # Simulator instruction rate (inst/s) -host_op_rate 97317 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 230983195 # Simulator tick rate (ticks/s) -host_mem_usage 211060 # Number of bytes of host memory used -host_seconds 0.05 # Real time elapsed on the host +host_inst_rate 93816 # Simulator instruction rate (inst/s) +host_op_rate 93786 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 229841550 # Simulator tick rate (ticks/s) +host_mem_usage 211032 # Number of bytes of host memory used +host_seconds 0.06 # Real time elapsed on the host sim_insts 5169 # Number of instructions simulated sim_ops 5169 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 30400 # Number of bytes read from this memory -system.physmem.bytes_inst_read 21312 # Number of instructions bytes read from this memory +system.physmem.bytes_read 30912 # Number of bytes read from this memory +system.physmem.bytes_inst_read 21824 # Number of instructions bytes read from this memory system.physmem.bytes_written 0 # Number of bytes written to this memory -system.physmem.num_reads 475 # Number of read requests responded to by this memory +system.physmem.num_reads 483 # Number of read requests responded to by this memory system.physmem.num_writes 0 # Number of write requests responded to by this memory system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 2477082909 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 1736565492 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total 2477082909 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read 2439490195 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 1722290179 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total 2439490195 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses system.cpu.dtb.read_accesses 0 # DTB read accesses @@ -39,245 +39,245 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 8 # Number of system calls -system.cpu.numCycles 24546 # number of cpu cycles simulated +system.cpu.numCycles 25344 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 1975 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 1343 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 399 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 1578 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 493 # Number of BTB hits +system.cpu.BPredUnit.lookups 2242 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 1547 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 477 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 1757 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 473 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 251 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 71 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 7903 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 12258 # Number of instructions fetch has processed -system.cpu.fetch.Branches 1975 # Number of branches that fetch encountered +system.cpu.BPredUnit.usedRAS 271 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 92 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 8296 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 13683 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2242 # Number of branches that fetch encountered system.cpu.fetch.predictedBranches 744 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 3024 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1186 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 756 # Number of cycles fetch has spent blocked +system.cpu.fetch.Cycles 3324 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1376 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 663 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 145 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 1781 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 229 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 12608 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.972240 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.277843 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.PendingTrapStallCycles 87 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 2039 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 282 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 13263 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.031667 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.344238 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 9584 76.02% 76.02% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1250 9.91% 85.93% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 108 0.86% 86.79% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 139 1.10% 87.89% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 289 2.29% 90.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 92 0.73% 90.91% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 132 1.05% 91.96% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 145 1.15% 93.11% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 869 6.89% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 9939 74.94% 74.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1348 10.16% 85.10% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 128 0.97% 86.07% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 139 1.05% 87.11% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 303 2.28% 89.40% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 122 0.92% 90.32% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 146 1.10% 91.42% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 140 1.06% 92.48% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 998 7.52% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 12608 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.080461 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.499389 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 8092 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 871 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2857 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 51 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 737 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 107 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 43 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 11425 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 162 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 737 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 8263 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 258 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 499 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2740 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 111 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 11004 # Number of instructions processed by rename -system.cpu.rename.LSQFullEvents 101 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 6697 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 13109 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 13105 # Number of integer rename lookups +system.cpu.fetch.rateDist::total 13263 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.088463 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.539891 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 8460 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 795 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 3128 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 40 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 840 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 144 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 52 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 12579 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 215 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 840 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 8664 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 204 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 498 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 2966 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 91 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 11935 # Number of instructions processed by rename +system.cpu.rename.LSQFullEvents 82 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 7222 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 14215 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 14211 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 4 # Number of floating rename lookups system.cpu.rename.CommittedMaps 3410 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 3287 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 18 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 11 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 281 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2346 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1174 # Number of stores inserted to the mem dependence unit. +system.cpu.rename.UndoneMaps 3812 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 17 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 12 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 229 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2496 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1209 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 1 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 1 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 8640 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 9121 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 13 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 7815 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 50 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 2984 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1806 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 8177 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 38 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 3469 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 2115 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 3 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 12608 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.619845 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.285923 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 13263 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.616527 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.283212 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 9257 73.42% 73.42% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1317 10.45% 83.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 832 6.60% 90.47% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 510 4.05% 94.51% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 356 2.82% 97.34% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 201 1.59% 98.93% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 85 0.67% 99.60% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 35 0.28% 99.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 15 0.12% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 9760 73.59% 73.59% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1384 10.44% 84.02% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 845 6.37% 90.39% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 558 4.21% 94.60% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 351 2.65% 97.25% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 227 1.71% 98.96% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 90 0.68% 99.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 34 0.26% 99.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 14 0.11% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 12608 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 13263 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 3 2.05% 2.05% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 2.05% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 2.05% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.05% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.05% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.05% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 2.05% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.05% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 2.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 2.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.05% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 91 62.33% 64.38% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 52 35.62% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 4 2.63% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 97 63.82% 66.45% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 51 33.55% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 4596 58.81% 58.81% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 4 0.05% 58.86% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 2 0.03% 58.89% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.03% 58.91% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 58.91% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 58.91% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 58.91% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 58.91% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 58.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 58.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 58.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 58.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 58.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 58.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 58.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 58.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 58.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 58.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 58.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 58.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 58.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 58.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 58.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 58.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 58.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 58.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 58.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 58.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 58.91% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2128 27.23% 86.14% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1083 13.86% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 4822 58.97% 58.97% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 4 0.05% 59.02% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 2 0.02% 59.04% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 59.07% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 59.07% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 59.07% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 59.07% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.07% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.07% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.07% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.07% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.07% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.07% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.07% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.07% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.07% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.07% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.07% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.07% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.07% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.07% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.07% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.07% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.07% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.07% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.07% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.07% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.07% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.07% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2258 27.61% 86.68% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1089 13.32% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 7815 # Type of FU issued -system.cpu.iq.rate 0.318382 # Inst issue rate -system.cpu.iq.fu_busy_cnt 146 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.018682 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 28430 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 11643 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 7116 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 8177 # Type of FU issued +system.cpu.iq.rate 0.322640 # Inst issue rate +system.cpu.iq.fu_busy_cnt 152 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.018589 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 29803 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 12607 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 7305 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 4 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 2 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 2 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 7959 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 8327 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 2 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 65 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 55 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1182 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 4 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 8 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 249 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 1332 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 7 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 284 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 737 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 165 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 13 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 10031 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 128 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2346 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1174 # Number of dispatched store instructions +system.cpu.iew.iewSquashCycles 840 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 139 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 9 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 10598 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 139 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2496 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1209 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 13 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 6 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewIQFullEvents 2 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 8 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 107 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 309 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 416 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 7531 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 2028 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 284 # Number of squashed instructions skipped in execute +system.cpu.iew.memOrderViolationEvents 7 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 132 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 371 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 503 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 7763 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 2105 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 414 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1378 # number of nop insts executed -system.cpu.iew.exec_refs 3087 # number of memory reference insts executed -system.cpu.iew.exec_branches 1271 # Number of branches executed -system.cpu.iew.exec_stores 1059 # Number of stores executed -system.cpu.iew.exec_rate 0.306812 # Inst execution rate -system.cpu.iew.wb_sent 7210 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 7118 # cumulative count of insts written-back -system.cpu.iew.wb_producers 2758 # num instructions producing a value -system.cpu.iew.wb_consumers 3946 # num instructions consuming a value +system.cpu.iew.exec_nop 1464 # number of nop insts executed +system.cpu.iew.exec_refs 3166 # number of memory reference insts executed +system.cpu.iew.exec_branches 1317 # Number of branches executed +system.cpu.iew.exec_stores 1061 # Number of stores executed +system.cpu.iew.exec_rate 0.306305 # Inst execution rate +system.cpu.iew.wb_sent 7406 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 7307 # cumulative count of insts written-back +system.cpu.iew.wb_producers 2841 # num instructions producing a value +system.cpu.iew.wb_consumers 4060 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.289986 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.698936 # average fanout of values written-back +system.cpu.iew.wb_rate 0.288313 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.699754 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 5826 # The number of committed instructions system.cpu.commit.commitCommittedOps 5826 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 4197 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 4764 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 10 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 357 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 11871 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.490776 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.277197 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 425 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 12423 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.468969 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.246143 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 9472 79.79% 79.79% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 966 8.14% 87.93% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 656 5.53% 93.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 321 2.70% 96.16% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 147 1.24% 97.40% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 102 0.86% 98.26% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 64 0.54% 98.80% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 41 0.35% 99.14% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 102 0.86% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 9990 80.42% 80.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1014 8.16% 88.58% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 641 5.16% 93.74% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 335 2.70% 96.43% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 140 1.13% 97.56% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 89 0.72% 98.28% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 74 0.60% 98.87% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 44 0.35% 99.23% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 96 0.77% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 11871 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 12423 # Number of insts commited each cycle system.cpu.commit.committedInsts 5826 # Number of instructions committed system.cpu.commit.committedOps 5826 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -288,63 +288,63 @@ system.cpu.commit.branches 916 # Nu system.cpu.commit.fp_insts 2 # Number of committed floating point instructions. system.cpu.commit.int_insts 5124 # Number of committed integer instructions. system.cpu.commit.function_calls 87 # Number of function calls committed. -system.cpu.commit.bw_lim_events 102 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 96 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 21779 # The number of ROB reads -system.cpu.rob.rob_writes 20794 # The number of ROB writes +system.cpu.rob.rob_reads 22904 # The number of ROB reads +system.cpu.rob.rob_writes 22029 # The number of ROB writes system.cpu.timesIdled 251 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 11938 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.idleCycles 12081 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 5169 # Number of Instructions Simulated system.cpu.committedOps 5169 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 5169 # Number of Instructions Simulated -system.cpu.cpi 4.748694 # CPI: Cycles Per Instruction -system.cpu.cpi_total 4.748694 # CPI: Total CPI of All Threads -system.cpu.ipc 0.210584 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.210584 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 10280 # number of integer regfile reads -system.cpu.int_regfile_writes 4987 # number of integer regfile writes +system.cpu.cpi 4.903076 # CPI: Cycles Per Instruction +system.cpu.cpi_total 4.903076 # CPI: Total CPI of All Threads +system.cpu.ipc 0.203954 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.203954 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 10565 # number of integer regfile reads +system.cpu.int_regfile_writes 5131 # number of integer regfile writes system.cpu.fp_regfile_reads 3 # number of floating regfile reads system.cpu.fp_regfile_writes 1 # number of floating regfile writes -system.cpu.misc_regfile_reads 153 # number of misc regfile reads -system.cpu.icache.replacements 17 # number of replacements -system.cpu.icache.tagsinuse 161.224498 # Cycle average of tags in use -system.cpu.icache.total_refs 1363 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 336 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 4.056548 # Average number of references to valid blocks. +system.cpu.misc_regfile_reads 151 # number of misc regfile reads +system.cpu.icache.replacements 19 # number of replacements +system.cpu.icache.tagsinuse 165.584947 # Cycle average of tags in use +system.cpu.icache.total_refs 1592 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 344 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 4.627907 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 161.224498 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.078723 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.078723 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 1363 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1363 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1363 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1363 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1363 # number of overall hits -system.cpu.icache.overall_hits::total 1363 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 418 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 418 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 418 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 418 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 418 # number of overall misses -system.cpu.icache.overall_misses::total 418 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 15148000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 15148000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 15148000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 15148000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 15148000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 15148000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1781 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1781 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1781 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1781 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1781 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1781 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.234700 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.234700 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.234700 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 36239.234450 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 36239.234450 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 36239.234450 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 165.584947 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.080852 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.080852 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 1592 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1592 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1592 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1592 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1592 # number of overall hits +system.cpu.icache.overall_hits::total 1592 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 447 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 447 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 447 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 447 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 447 # number of overall misses +system.cpu.icache.overall_misses::total 447 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 15909500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 15909500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 15909500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 15909500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 15909500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 15909500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 2039 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 2039 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 2039 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 2039 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 2039 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 2039 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.219225 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.219225 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.219225 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35591.722595 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 35591.722595 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 35591.722595 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -353,80 +353,80 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 82 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 82 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 82 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 82 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 82 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 82 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 336 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 336 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 336 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 336 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 336 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 336 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11784000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 11784000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11784000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 11784000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11784000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 11784000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.188658 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.188658 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.188658 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35071.428571 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35071.428571 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35071.428571 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 103 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 103 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 103 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 103 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 103 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 103 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 344 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 344 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 344 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 344 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 344 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 344 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12065000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 12065000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12065000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 12065000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12065000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 12065000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.168710 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.168710 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.168710 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35072.674419 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35072.674419 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35072.674419 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 92.121984 # Cycle average of tags in use -system.cpu.dcache.total_refs 2380 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 92.322697 # Cycle average of tags in use +system.cpu.dcache.total_refs 2472 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 142 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 16.760563 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 17.408451 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 92.121984 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.022491 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.022491 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 1802 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1802 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 578 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 578 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 2380 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2380 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2380 # number of overall hits -system.cpu.dcache.overall_hits::total 2380 # number of overall hits +system.cpu.dcache.occ_blocks::cpu.data 92.322697 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.022540 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.022540 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 1886 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1886 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 586 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 586 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 2472 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2472 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2472 # number of overall hits +system.cpu.dcache.overall_hits::total 2472 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 133 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 133 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 347 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 347 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 480 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 480 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 480 # number of overall misses -system.cpu.dcache.overall_misses::total 480 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 4767500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 4767500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 11508000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 11508000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 16275500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 16275500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 16275500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 16275500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1935 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1935 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_misses::cpu.data 339 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 339 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 472 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 472 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 472 # number of overall misses +system.cpu.dcache.overall_misses::total 472 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 4826500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 4826500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 11393500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 11393500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 16220000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 16220000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 16220000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 16220000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 2019 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 2019 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 925 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 925 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2860 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2860 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2860 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2860 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.068734 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.375135 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.167832 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.167832 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 35845.864662 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33164.265130 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 33907.291667 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 33907.291667 # average overall miss latency +system.cpu.dcache.demand_accesses::cpu.data 2944 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2944 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2944 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2944 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.065874 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.366486 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.160326 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.160326 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 36289.473684 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33609.144543 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 34364.406780 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 34364.406780 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -437,12 +437,12 @@ system.cpu.dcache.fast_writes 0 # nu system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.ReadReq_mshr_hits::cpu.data 42 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 42 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 296 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 296 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 338 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 338 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 338 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 338 # number of overall MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 288 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 288 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 330 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 330 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 330 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 330 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 91 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 91 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 51 # number of WriteReq MSHR misses @@ -451,87 +451,87 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 142 system.cpu.dcache.demand_mshr_misses::total 142 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 142 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 142 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3272000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 3272000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1836000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1836000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5108000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 5108000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5108000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 5108000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.047028 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3267500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 3267500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1845500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1845500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5113000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 5113000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5113000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 5113000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.045072 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055135 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.049650 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.049650 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 35956.043956 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 36000 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 35971.830986 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 35971.830986 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.048234 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.048234 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 35906.593407 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 36186.274510 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 36007.042254 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 36007.042254 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 221.521956 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 226.359524 # Cycle average of tags in use system.cpu.l2cache.total_refs 3 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 424 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.007075 # Average number of references to valid blocks. +system.cpu.l2cache.sampled_refs 432 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.006944 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 163.434563 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 58.087393 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.004988 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.001773 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.006760 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 168.225322 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 58.134201 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.005134 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.001774 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.006908 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 3 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 3 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 3 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::total 3 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.inst 3 # number of overall hits system.cpu.l2cache.overall_hits::total 3 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 333 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.inst 341 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.data 91 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 424 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 432 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 51 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 51 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 333 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 341 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.data 142 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 475 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 333 # number of overall misses +system.cpu.l2cache.demand_misses::total 483 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 341 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 142 # number of overall misses -system.cpu.l2cache.overall_misses::total 475 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 11418500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3142500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 14561000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1760500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 1760500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 11418500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 4903000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 16321500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 11418500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 4903000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 16321500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 336 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.overall_misses::total 483 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 11691000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3142000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 14833000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1769000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 1769000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 11691000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 4911000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 16602000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 11691000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 4911000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 16602000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 344 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 91 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 427 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 435 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 51 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 51 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 336 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 344 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 142 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 478 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 336 # number of overall (read+write) accesses +system.cpu.l2cache.demand_accesses::total 486 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 344 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 142 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 478 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.991071 # miss rate for ReadReq accesses +system.cpu.l2cache.overall_accesses::total 486 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.991279 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.991071 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.991279 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.991071 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.991279 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34289.789790 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34532.967033 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34519.607843 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34289.789790 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34528.169014 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34289.789790 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34528.169014 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34284.457478 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34527.472527 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34686.274510 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34284.457478 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34584.507042 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34284.457478 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34584.507042 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -540,42 +540,42 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 333 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 341 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 91 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 424 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 432 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 51 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 51 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 333 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 341 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 142 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 475 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 333 # number of overall MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 483 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 341 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 142 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 475 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10340500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2857500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13198000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1598500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1598500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10340500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4456000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 14796500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10340500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4456000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 14796500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.991071 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.overall_mshr_misses::total 483 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10590500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2858000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13448500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1604000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1604000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10590500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4462000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 15052500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10590500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4462000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 15052500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.991279 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.991071 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.991279 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.991071 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.991279 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31052.552553 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31401.098901 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31343.137255 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31052.552553 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31380.281690 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31052.552553 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31380.281690 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31057.184751 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31406.593407 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31450.980392 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31057.184751 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31422.535211 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31057.184751 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31422.535211 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/power/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/power/linux/o3-timing/simout index 8e7d01159..a3c2e1876 100755 --- a/tests/quick/se/00.hello/ref/power/linux/o3-timing/simout +++ b/tests/quick/se/00.hello/ref/power/linux/o3-timing/simout @@ -1,11 +1,11 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 11 2012 13:07:55 -gem5 started Feb 11 2012 13:55:01 +gem5 compiled Feb 12 2012 17:17:52 +gem5 started Feb 12 2012 18:17:19 gem5 executing on zizzer command line: build/POWER/gem5.fast -d build/POWER/tests/fast/quick/se/00.hello/power/linux/o3-timing -re tests/run.py build/POWER/tests/fast/quick/se/00.hello/power/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 10910500 because target called exit() +Exiting @ tick 11243500 because target called exit() diff --git a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt index 7c789f568..e78f47ce4 100644 --- a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt @@ -1,25 +1,25 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000011 # Number of seconds simulated -sim_ticks 10910500 # Number of ticks simulated -final_tick 10910500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 11243500 # Number of ticks simulated +final_tick 11243500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 114395 # Simulator instruction rate (inst/s) -host_op_rate 114354 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 215042277 # Simulator tick rate (ticks/s) -host_mem_usage 207892 # Number of bytes of host memory used +host_inst_rate 108078 # Simulator instruction rate (inst/s) +host_op_rate 108043 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 209380098 # Simulator tick rate (ticks/s) +host_mem_usage 207884 # Number of bytes of host memory used host_seconds 0.05 # Real time elapsed on the host sim_insts 5800 # Number of instructions simulated sim_ops 5800 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 28608 # Number of bytes read from this memory -system.physmem.bytes_inst_read 22016 # Number of instructions bytes read from this memory +system.physmem.bytes_read 28736 # Number of bytes read from this memory +system.physmem.bytes_inst_read 22400 # Number of instructions bytes read from this memory system.physmem.bytes_written 0 # Number of bytes written to this memory -system.physmem.num_reads 447 # Number of read requests responded to by this memory +system.physmem.num_reads 449 # Number of read requests responded to by this memory system.physmem.num_writes 0 # Number of write requests responded to by this memory system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 2622061317 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 2017872691 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total 2622061317 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read 2555787789 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 1992262196 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total 2555787789 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses system.cpu.dtb.read_accesses 0 # DTB read accesses @@ -39,245 +39,245 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 9 # Number of system calls -system.cpu.numCycles 21822 # number of cpu cycles simulated +system.cpu.numCycles 22488 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 2297 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 1905 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 402 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 1853 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 666 # Number of BTB hits +system.cpu.BPredUnit.lookups 2514 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 2062 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 468 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 2079 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 622 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 189 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 30 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 6507 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 12976 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2297 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 855 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 2210 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1212 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 909 # Number of cycles fetch has spent blocked +system.cpu.BPredUnit.usedRAS 153 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 36 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 6888 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 14589 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2514 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 775 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 2426 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1431 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 816 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.CacheLines 1711 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 280 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 10433 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.243746 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.642546 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 1899 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 313 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 11089 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.315628 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.735108 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 8223 78.82% 78.82% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 152 1.46% 80.27% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 173 1.66% 81.93% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 127 1.22% 83.15% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 217 2.08% 85.23% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 137 1.31% 86.54% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 283 2.71% 89.26% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 122 1.17% 90.42% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 999 9.58% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 8663 78.12% 78.12% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 176 1.59% 79.71% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 171 1.54% 81.25% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 143 1.29% 82.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 201 1.81% 84.35% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 144 1.30% 85.65% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 252 2.27% 87.92% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 106 0.96% 88.88% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1233 11.12% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 10433 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.105261 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.594629 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 6670 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 983 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2045 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 79 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 656 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 304 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 152 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 11459 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 428 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 656 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 6866 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 379 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 350 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 1920 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 262 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 10928 # Number of instructions processed by rename -system.cpu.rename.IQFullEvents 7 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 207 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 9549 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 17852 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 17781 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 71 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 11089 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.111793 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.648746 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 7080 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 888 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 2252 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 74 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 795 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 365 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 168 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 12905 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 444 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 795 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 7301 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 305 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 349 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 2095 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 244 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 12210 # Number of instructions processed by rename +system.cpu.rename.IQFullEvents 3 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 200 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 10547 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 19978 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 19923 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 55 # Number of floating rename lookups system.cpu.rename.CommittedMaps 5007 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 4542 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 5540 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 25 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 25 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 544 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 1864 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1573 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 52 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 44 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 9933 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 69 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 8536 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 64 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 3878 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 3544 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 53 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 10433 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.818173 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.531685 # Number of insts issued each cycle +system.cpu.rename.tempSerializingInsts 24 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 515 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2074 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1892 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 55 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 30 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 10875 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 62 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 9284 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 151 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 4827 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 4112 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 46 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 11089 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.837226 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.572881 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 7234 69.34% 69.34% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1021 9.79% 79.12% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 762 7.30% 86.43% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 472 4.52% 90.95% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 448 4.29% 95.25% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 290 2.78% 98.03% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 132 1.27% 99.29% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 51 0.49% 99.78% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 23 0.22% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 7692 69.37% 69.37% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1077 9.71% 79.08% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 744 6.71% 85.79% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 533 4.81% 90.59% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 478 4.31% 94.90% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 322 2.90% 97.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 147 1.33% 99.13% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 52 0.47% 99.60% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 44 0.40% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 10433 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 11089 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 9 5.84% 5.84% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 5.84% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 5.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 5.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 5.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 5.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.84% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 68 44.16% 50.00% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 77 50.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 6 3.47% 3.47% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 3.47% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 3.47% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.47% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.47% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.47% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 3.47% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.47% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 3.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 3.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.47% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 76 43.93% 47.40% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 91 52.60% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 5388 63.12% 63.12% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 63.12% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 63.12% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 63.14% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 63.14% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 63.14% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 63.14% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 63.14% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 63.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 63.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 63.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 63.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 63.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 63.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 63.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 63.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 63.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 63.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 63.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 63.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 63.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 63.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 63.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 63.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 63.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 63.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 63.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 63.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 63.14% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 1717 20.11% 83.26% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1429 16.74% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 5734 61.76% 61.76% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 61.76% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.76% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 61.78% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.78% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.78% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.78% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.78% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 61.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 61.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.78% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 1852 19.95% 81.73% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1696 18.27% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 8536 # Type of FU issued -system.cpu.iq.rate 0.391165 # Inst issue rate -system.cpu.iq.fu_busy_cnt 154 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.018041 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 27649 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 13831 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 7849 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 74 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 52 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 30 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 8652 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 38 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 68 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 9284 # Type of FU issued +system.cpu.iq.rate 0.412842 # Inst issue rate +system.cpu.iq.fu_busy_cnt 173 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.018634 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 29919 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 15735 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 8360 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 62 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 36 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 27 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 9423 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 34 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 67 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 902 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 1 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 6 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 527 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 1112 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 7 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 846 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 656 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 186 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 23 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 10002 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 43 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 1864 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1573 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 60 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 14 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 6 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 62 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 238 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 300 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 8170 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 1611 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 366 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 795 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 113 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 17 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 10937 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 113 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2074 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1892 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 52 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 9 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 3 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 7 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 89 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 309 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 398 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 8754 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 1704 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 530 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 2952 # number of memory reference insts executed -system.cpu.iew.exec_branches 1313 # Number of branches executed -system.cpu.iew.exec_stores 1341 # Number of stores executed -system.cpu.iew.exec_rate 0.374393 # Inst execution rate -system.cpu.iew.wb_sent 7993 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 7879 # cumulative count of insts written-back -system.cpu.iew.wb_producers 4173 # num instructions producing a value -system.cpu.iew.wb_consumers 6691 # num instructions consuming a value +system.cpu.iew.exec_refs 3258 # number of memory reference insts executed +system.cpu.iew.exec_branches 1391 # Number of branches executed +system.cpu.iew.exec_stores 1554 # Number of stores executed +system.cpu.iew.exec_rate 0.389274 # Inst execution rate +system.cpu.iew.wb_sent 8553 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 8387 # cumulative count of insts written-back +system.cpu.iew.wb_producers 4351 # num instructions producing a value +system.cpu.iew.wb_consumers 7020 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.361058 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.623674 # average fanout of values written-back +system.cpu.iew.wb_rate 0.372954 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.619801 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 5800 # The number of committed instructions system.cpu.commit.commitCommittedOps 5800 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 4208 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 5146 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 16 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 252 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 9777 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.593229 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.375317 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 305 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 10294 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.563435 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.344775 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 7386 75.54% 75.54% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 981 10.03% 85.58% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 642 6.57% 92.14% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 262 2.68% 94.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 190 1.94% 96.77% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 116 1.19% 97.95% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 75 0.77% 98.72% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 41 0.42% 99.14% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 84 0.86% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 7857 76.33% 76.33% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1043 10.13% 86.46% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 648 6.29% 92.75% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 255 2.48% 95.23% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 186 1.81% 97.04% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 110 1.07% 98.11% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 58 0.56% 98.67% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 42 0.41% 99.08% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 95 0.92% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 9777 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 10294 # Number of insts commited each cycle system.cpu.commit.committedInsts 5800 # Number of instructions committed system.cpu.commit.committedOps 5800 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -288,62 +288,62 @@ system.cpu.commit.branches 1038 # Nu system.cpu.commit.fp_insts 22 # Number of committed floating point instructions. system.cpu.commit.int_insts 5706 # Number of committed integer instructions. system.cpu.commit.function_calls 103 # Number of function calls committed. -system.cpu.commit.bw_lim_events 84 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 95 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 19701 # The number of ROB reads -system.cpu.rob.rob_writes 20673 # The number of ROB writes -system.cpu.timesIdled 218 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 11389 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 21145 # The number of ROB reads +system.cpu.rob.rob_writes 22688 # The number of ROB writes +system.cpu.timesIdled 217 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 11399 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 5800 # Number of Instructions Simulated system.cpu.committedOps 5800 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 5800 # Number of Instructions Simulated -system.cpu.cpi 3.762414 # CPI: Cycles Per Instruction -system.cpu.cpi_total 3.762414 # CPI: Total CPI of All Threads -system.cpu.ipc 0.265787 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.265787 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 12979 # number of integer regfile reads -system.cpu.int_regfile_writes 6957 # number of integer regfile writes -system.cpu.fp_regfile_reads 28 # number of floating regfile reads +system.cpu.cpi 3.877241 # CPI: Cycles Per Instruction +system.cpu.cpi_total 3.877241 # CPI: Total CPI of All Threads +system.cpu.ipc 0.257915 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.257915 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 13921 # number of integer regfile reads +system.cpu.int_regfile_writes 7265 # number of integer regfile writes +system.cpu.fp_regfile_reads 25 # number of floating regfile reads system.cpu.fp_regfile_writes 2 # number of floating regfile writes system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 169.539680 # Cycle average of tags in use -system.cpu.icache.total_refs 1291 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 351 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 3.678063 # Average number of references to valid blocks. +system.cpu.icache.tagsinuse 172.379391 # Cycle average of tags in use +system.cpu.icache.total_refs 1462 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 355 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 4.118310 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 169.539680 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.082783 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.082783 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 1291 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1291 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1291 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1291 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1291 # number of overall hits -system.cpu.icache.overall_hits::total 1291 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 420 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 420 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 420 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 420 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 420 # number of overall misses -system.cpu.icache.overall_misses::total 420 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 15114500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 15114500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 15114500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 15114500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 15114500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 15114500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1711 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1711 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1711 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1711 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1711 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1711 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.245470 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.245470 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.245470 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35986.904762 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 35986.904762 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 35986.904762 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 172.379391 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.084170 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.084170 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 1462 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1462 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1462 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1462 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1462 # number of overall hits +system.cpu.icache.overall_hits::total 1462 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 437 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 437 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 437 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 437 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 437 # number of overall misses +system.cpu.icache.overall_misses::total 437 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 15734000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 15734000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 15734000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 15734000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 15734000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 15734000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1899 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1899 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1899 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1899 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1899 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1899 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.230121 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.230121 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.230121 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 36004.576659 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 36004.576659 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 36004.576659 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -352,80 +352,80 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 69 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 69 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 69 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 69 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 69 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 69 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 351 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 351 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 351 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 351 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 351 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 351 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12207500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 12207500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12207500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 12207500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12207500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 12207500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.205143 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.205143 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.205143 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 34779.202279 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 34779.202279 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34779.202279 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 82 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 82 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 82 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 82 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 82 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 82 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 355 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 355 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 355 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 355 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 355 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 355 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12417500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 12417500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12417500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 12417500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12417500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 12417500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.186940 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.186940 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.186940 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 34978.873239 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 34978.873239 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34978.873239 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 66.296919 # Cycle average of tags in use -system.cpu.dcache.total_refs 2156 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 105 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 20.533333 # Average number of references to valid blocks. +system.cpu.dcache.tagsinuse 62.512522 # Cycle average of tags in use +system.cpu.dcache.total_refs 2216 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 99 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 22.383838 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 66.296919 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.016186 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.016186 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 1428 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1428 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 728 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 728 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 2156 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2156 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2156 # number of overall hits -system.cpu.dcache.overall_hits::total 2156 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 88 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 88 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 318 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 318 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 406 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 406 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 406 # number of overall misses -system.cpu.dcache.overall_misses::total 406 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 2947000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 2947000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 10802500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 10802500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 13749500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 13749500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 13749500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 13749500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1516 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1516 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.occ_blocks::cpu.data 62.512522 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.015262 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.015262 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 1486 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1486 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 730 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 730 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 2216 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2216 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2216 # number of overall hits +system.cpu.dcache.overall_hits::total 2216 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 83 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 83 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 316 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 316 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 399 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 399 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 399 # number of overall misses +system.cpu.dcache.overall_misses::total 399 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 2993000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 2993000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 10587500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 10587500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 13580500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 13580500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 13580500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 13580500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1569 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1569 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 1046 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 1046 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2562 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2562 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2562 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2562 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.058047 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.304015 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.158470 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.158470 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 33488.636364 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33970.125786 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 33865.763547 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 33865.763547 # average overall miss latency +system.cpu.dcache.demand_accesses::cpu.data 2615 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2615 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2615 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2615 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.052900 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.302103 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.152581 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.152581 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 36060.240964 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33504.746835 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 34036.340852 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 34036.340852 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -434,106 +434,103 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 31 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 31 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 270 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 270 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 301 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 301 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 301 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 301 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 57 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 57 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 32 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 32 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 268 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 268 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 300 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 300 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 300 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 300 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 51 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 51 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 48 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 48 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 105 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 105 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 105 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 105 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1963500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 1963500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1751000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1751000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 3714500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 3714500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 3714500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 3714500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.037599 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_misses::cpu.data 99 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 99 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 99 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 99 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1819500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 1819500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1750500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1750500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 3570000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 3570000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 3570000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 3570000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.032505 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.045889 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.040984 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.040984 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 34447.368421 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 36479.166667 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 35376.190476 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 35376.190476 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.037859 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.037859 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 35676.470588 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 36468.750000 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 36060.606061 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 36060.606061 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 200.613051 # Cycle average of tags in use -system.cpu.l2cache.total_refs 9 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 399 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.022556 # Average number of references to valid blocks. +system.cpu.l2cache.tagsinuse 201.766772 # Cycle average of tags in use +system.cpu.l2cache.total_refs 5 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 401 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.012469 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 168.132824 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 32.480228 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.005131 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.000991 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.006122 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 7 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 2 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 9 # number of ReadReq hits -system.cpu.l2cache.demand_hits::cpu.inst 7 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 2 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 9 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 7 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 2 # number of overall hits -system.cpu.l2cache.overall_hits::total 9 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 344 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 55 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 399 # number of ReadReq misses +system.cpu.l2cache.occ_blocks::cpu.inst 171.497459 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 30.269313 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.005234 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.000924 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.006157 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 5 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 5 # number of ReadReq hits +system.cpu.l2cache.demand_hits::cpu.inst 5 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 5 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 5 # number of overall hits +system.cpu.l2cache.overall_hits::total 5 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 350 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 51 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 401 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 48 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 48 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 344 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 103 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 447 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 344 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 103 # number of overall misses -system.cpu.l2cache.overall_misses::total 447 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 11818500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1895500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 13714000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1678500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 1678500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 11818500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 3574000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 15392500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 11818500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 3574000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 15392500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 351 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 57 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 408 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.demand_misses::cpu.inst 350 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 99 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 449 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 350 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 99 # number of overall misses +system.cpu.l2cache.overall_misses::total 449 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 12030500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1761000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 13791500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1675000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 1675000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 12030500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 3436000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 15466500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 12030500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 3436000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 15466500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 355 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 51 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 406 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 48 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 48 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 351 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 105 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 456 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 351 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 105 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 456 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.980057 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.964912 # miss rate for ReadReq accesses +system.cpu.l2cache.demand_accesses::cpu.inst 355 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 99 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 454 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 355 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 99 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 454 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.985915 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.980057 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.980952 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.980057 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.980952 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34356.104651 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34463.636364 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34968.750000 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34356.104651 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34699.029126 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34356.104651 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34699.029126 # average overall miss latency +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.985915 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.985915 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34372.857143 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34529.411765 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34895.833333 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34372.857143 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34707.070707 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34372.857143 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34707.070707 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -542,42 +539,42 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 344 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 55 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 399 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 350 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 51 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 401 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 48 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 48 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 344 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 103 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 447 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 344 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 103 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 447 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10708500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1725500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 12434000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1526000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1526000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10708500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3251500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 13960000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10708500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3251500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 13960000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.980057 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.964912 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 350 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 99 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 449 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 350 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 99 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 449 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10905000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1600500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 12505500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1521000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1521000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10905000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3121500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 14026500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10905000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3121500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 14026500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.985915 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.980057 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.980952 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.980057 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.980952 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31129.360465 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31372.727273 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31791.666667 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31129.360465 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31567.961165 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31129.360465 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31567.961165 # average overall mshr miss latency +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.985915 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.985915 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31157.142857 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31382.352941 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31687.500000 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31157.142857 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31530.303030 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31157.142857 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31530.303030 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/simout b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/simout index 13c85267e..cf9740828 100755 --- a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/simout +++ b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 11 2012 13:08:33 -gem5 started Feb 11 2012 13:55:12 +gem5 compiled Feb 12 2012 17:18:12 +gem5 started Feb 12 2012 18:17:30 gem5 executing on zizzer command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/quick/se/00.hello/sparc/linux/inorder-timing -re tests/run.py build/SPARC/tests/fast/quick/se/00.hello/sparc/linux/inorder-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... -Hello World!Exiting @ tick 18201500 because target called exit() +Hello World!Exiting @ tick 18196500 because target called exit() diff --git a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt index 99d0ed042..440f0bc0a 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000018 # Number of seconds simulated -sim_ticks 18201500 # Number of ticks simulated -final_tick 18201500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 18196500 # Number of ticks simulated +final_tick 18196500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 71915 # Simulator instruction rate (inst/s) -host_op_rate 71898 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 245008016 # Simulator tick rate (ticks/s) -host_mem_usage 211144 # Number of bytes of host memory used -host_seconds 0.07 # Real time elapsed on the host +host_inst_rate 90140 # Simulator instruction rate (inst/s) +host_op_rate 90112 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 306976844 # Simulator tick rate (ticks/s) +host_mem_usage 211148 # Number of bytes of host memory used +host_seconds 0.06 # Real time elapsed on the host sim_insts 5340 # Number of instructions simulated sim_ops 5340 # Number of ops (including micro ops) simulated system.physmem.bytes_read 27072 # Number of bytes read from this memory @@ -17,20 +17,20 @@ system.physmem.bytes_written 0 # Nu system.physmem.num_reads 423 # Number of read requests responded to by this memory system.physmem.num_writes 0 # Number of write requests responded to by this memory system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 1487349944 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 1016179985 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total 1487349944 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read 1487758635 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 1016459209 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total 1487758635 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 11 # Number of system calls -system.cpu.numCycles 36404 # number of cpu cycles simulated +system.cpu.numCycles 36394 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 9720 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 9708 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode system.cpu.timesIdled 421 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 30130 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 6274 # Number of cycles cpu stages are processed. -system.cpu.activity 17.234370 # Percentage of cycles cpu is active +system.cpu.idleCycles 30167 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 6227 # Number of cycles cpu stages are processed. +system.cpu.activity 17.109963 # Percentage of cycles cpu is active system.cpu.comLoads 716 # Number of Load instructions committed system.cpu.comStores 673 # Number of Store instructions committed system.cpu.comBranches 1116 # Number of Branches instructions committed @@ -42,98 +42,98 @@ system.cpu.committedInsts 5340 # Nu system.cpu.committedOps 5340 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 5340 # Number of Instructions committed (Total) -system.cpu.cpi 6.817228 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 6.815356 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi no_value # CPI: Total SMT-CPI -system.cpu.cpi_total 6.817228 # CPI: Total CPI of All Threads -system.cpu.ipc 0.146687 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 6.815356 # CPI: Total CPI of All Threads +system.cpu.ipc 0.146727 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc no_value # IPC: Total SMT-IPC -system.cpu.ipc_total 0.146687 # IPC: Total IPC of All Threads -system.cpu.branch_predictor.lookups 1662 # Number of BP lookups -system.cpu.branch_predictor.condPredicted 1123 # Number of conditional branches predicted +system.cpu.ipc_total 0.146727 # IPC: Total IPC of All Threads +system.cpu.branch_predictor.lookups 1617 # Number of BP lookups +system.cpu.branch_predictor.condPredicted 1022 # Number of conditional branches predicted system.cpu.branch_predictor.condIncorrect 899 # Number of conditional branches incorrect -system.cpu.branch_predictor.BTBLookups 1455 # Number of BTB lookups -system.cpu.branch_predictor.BTBHits 643 # Number of BTB hits +system.cpu.branch_predictor.BTBLookups 1172 # Number of BTB lookups +system.cpu.branch_predictor.BTBHits 435 # Number of BTB hits system.cpu.branch_predictor.usedRAS 67 # Number of times the RAS was used to get a target. system.cpu.branch_predictor.RASInCorrect 4 # Number of incorrect RAS predictions. -system.cpu.branch_predictor.BTBHitPct 44.192440 # BTB Hit Percentage -system.cpu.branch_predictor.predictedTaken 710 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.predictedNotTaken 952 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 5612 # Number of Reads from Int. Register File +system.cpu.branch_predictor.BTBHitPct 37.116041 # BTB Hit Percentage +system.cpu.branch_predictor.predictedTaken 502 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.predictedNotTaken 1115 # Number of Branches Predicted As Not Taken (False). +system.cpu.regfile_manager.intRegFileReads 5634 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 4000 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 9612 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.intRegFileAccesses 9634 # Total Accesses (Read+Write) to the Int. Register File system.cpu.regfile_manager.floatRegFileReads 0 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 0 # Number of Writes to FP Register File system.cpu.regfile_manager.floatRegFileAccesses 0 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 1747 # Number of Registers Read Through Forwarding Logic -system.cpu.agen_unit.agens 1473 # Number of Address Generations -system.cpu.execution_unit.predictedTakenIncorrect 394 # Number of Branches Incorrectly Predicted As Taken. -system.cpu.execution_unit.predictedNotTakenIncorrect 442 # Number of Branches Incorrectly Predicted As Not Taken). +system.cpu.regfile_manager.regForwards 1686 # Number of Registers Read Through Forwarding Logic +system.cpu.agen_unit.agens 1487 # Number of Address Generations +system.cpu.execution_unit.predictedTakenIncorrect 319 # Number of Branches Incorrectly Predicted As Taken. +system.cpu.execution_unit.predictedNotTakenIncorrect 517 # Number of Branches Incorrectly Predicted As Not Taken). system.cpu.execution_unit.mispredicted 836 # Number of Branches Incorrectly Predicted system.cpu.execution_unit.predicted 280 # Number of Branches Incorrectly Predicted system.cpu.execution_unit.mispredictPct 74.910394 # Percentage of Incorrect Branches Predicts -system.cpu.execution_unit.executions 3977 # Number of Instructions Executed. +system.cpu.execution_unit.executions 3979 # Number of Instructions Executed. system.cpu.mult_div_unit.multiplies 0 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed -system.cpu.stage0.idleCycles 31738 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 4666 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 12.817273 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 33193 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 3211 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 8.820459 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 33357 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 3047 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 8.369959 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 35421 # Number of cycles 0 instructions are processed. +system.cpu.stage0.idleCycles 31821 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 4573 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 12.565258 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 33191 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 3203 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 8.800901 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 33344 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 3050 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 8.380502 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 35411 # Number of cycles 0 instructions are processed. system.cpu.stage3.runCycles 983 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 2.700253 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 33233 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 3171 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 8.710581 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.utilization 2.700995 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 33220 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 3174 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 8.721218 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 136.669321 # Cycle average of tags in use -system.cpu.icache.total_refs 791 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 136.672418 # Cycle average of tags in use +system.cpu.icache.total_refs 827 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 291 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 2.718213 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 2.841924 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 136.669321 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.066733 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.066733 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 791 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 791 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 791 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 791 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 791 # number of overall hits -system.cpu.icache.overall_hits::total 791 # number of overall hits +system.cpu.icache.occ_blocks::cpu.inst 136.672418 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.066735 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.066735 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 827 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 827 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 827 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 827 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 827 # number of overall hits +system.cpu.icache.overall_hits::total 827 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 347 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 347 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 347 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 347 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 347 # number of overall misses system.cpu.icache.overall_misses::total 347 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 19110500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 19110500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 19110500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 19110500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 19110500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 19110500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1138 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1138 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1138 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1138 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1138 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1138 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.304921 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.304921 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.304921 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55073.487032 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 55073.487032 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 55073.487032 # average overall miss latency +system.cpu.icache.ReadReq_miss_latency::cpu.inst 19107000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 19107000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 19107000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 19107000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 19107000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 19107000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1174 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1174 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1174 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1174 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1174 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1174 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.295571 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.295571 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.295571 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55063.400576 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 55063.400576 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 55063.400576 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 104500 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 106000 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 3 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 34833.333333 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 35333.333333 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.ReadReq_mshr_hits::cpu.inst 56 # number of ReadReq MSHR hits @@ -148,28 +148,28 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 291 system.cpu.icache.demand_mshr_misses::total 291 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 291 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 291 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15470000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 15470000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15470000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 15470000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15470000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 15470000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.255712 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.255712 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.255712 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53161.512027 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53161.512027 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53161.512027 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15468000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 15468000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15468000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 15468000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15468000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 15468000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.247871 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.247871 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.247871 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53154.639175 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53154.639175 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53154.639175 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 82.859932 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 82.864730 # Cycle average of tags in use system.cpu.dcache.total_refs 1049 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 135 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 7.770370 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 82.859932 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.020229 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.020229 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::cpu.data 82.864730 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.020231 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.020231 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 657 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 657 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 392 # number of WriteReq hits @@ -186,14 +186,14 @@ system.cpu.dcache.demand_misses::cpu.data 340 # n system.cpu.dcache.demand_misses::total 340 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 340 # number of overall misses system.cpu.dcache.overall_misses::total 340 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 3290500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 3290500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 15457500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 15457500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 18748000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 18748000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 18748000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 18748000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 3291500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 3291500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 15458000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 15458000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 18749500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 18749500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 18749500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 18749500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 716 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 716 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 673 # number of WriteReq accesses(hits+misses) @@ -206,10 +206,10 @@ system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.082402 system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.417533 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.244780 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.244780 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55771.186441 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55008.896797 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 55141.176471 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 55141.176471 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55788.135593 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55010.676157 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 55145.588235 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 55145.588235 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 2259500 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -234,31 +234,31 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 135 system.cpu.dcache.demand_mshr_misses::total 135 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 135 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 135 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2865500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2865500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4327000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4327000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7192500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 7192500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7192500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 7192500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2866000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2866000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4327500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4327500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7193500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 7193500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7193500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 7193500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.075419 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.120357 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.097192 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.097192 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53064.814815 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53419.753086 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53277.777778 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53277.777778 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53074.074074 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53425.925926 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53285.185185 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53285.185185 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 162.297266 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 162.299655 # Cycle average of tags in use system.cpu.l2cache.total_refs 3 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 342 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.008772 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 136.185515 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 26.111751 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 136.188396 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 26.111259 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::cpu.inst 0.004156 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.000797 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::total 0.004953 # Average percentage of cache occupancy @@ -282,17 +282,17 @@ system.cpu.l2cache.demand_misses::total 423 # nu system.cpu.l2cache.overall_misses::cpu.inst 289 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 134 # number of overall misses system.cpu.l2cache.overall_misses::total 423 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 15132500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2786000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 17918500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 15131000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2786500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 17917500 # number of ReadReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4230500 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 4230500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 15132500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 7016500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 22149000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 15132500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 7016500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 22149000 # number of overall miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 15131000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 7017000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 22148000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 15131000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 7017000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 22148000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 291 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 54 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 345 # number of ReadReq accesses(hits+misses) @@ -311,13 +311,13 @@ system.cpu.l2cache.demand_miss_rate::cpu.inst 0.993127 system.cpu.l2cache.demand_miss_rate::cpu.data 0.992593 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993127 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.992593 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52361.591696 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52566.037736 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52356.401384 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52575.471698 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52228.395062 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52361.591696 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52361.940299 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52361.591696 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52361.940299 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52356.401384 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52365.671642 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52356.401384 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52365.671642 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simout index ac1cd3610..eda7f85a5 100755 --- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simout +++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simout @@ -1,11 +1,11 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 11 2012 13:08:53 -gem5 started Feb 11 2012 14:04:05 +gem5 compiled Feb 12 2012 17:18:12 +gem5 started Feb 12 2012 18:26:23 gem5 executing on zizzer command line: build/X86/gem5.fast -d build/X86/tests/fast/quick/se/00.hello/x86/linux/o3-timing -re tests/run.py build/X86/tests/fast/quick/se/00.hello/x86/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 11989500 because target called exit() +Exiting @ tick 12299500 because target called exit() diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt index 658a056fb..475f993c2 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt @@ -1,264 +1,264 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000012 # Number of seconds simulated -sim_ticks 11989500 # Number of ticks simulated -final_tick 11989500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 12299500 # Number of ticks simulated +final_tick 12299500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 61798 # Simulator instruction rate (inst/s) -host_op_rate 111900 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 136747555 # Simulator tick rate (ticks/s) -host_mem_usage 218292 # Number of bytes of host memory used +host_inst_rate 59298 # Simulator instruction rate (inst/s) +host_op_rate 107375 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 134612595 # Simulator tick rate (ticks/s) +host_mem_usage 218308 # Number of bytes of host memory used host_seconds 0.09 # Real time elapsed on the host sim_insts 5416 # Number of instructions simulated sim_ops 9809 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 28288 # Number of bytes read from this memory -system.physmem.bytes_inst_read 18944 # Number of instructions bytes read from this memory +system.physmem.bytes_read 28864 # Number of bytes read from this memory +system.physmem.bytes_inst_read 19328 # Number of instructions bytes read from this memory system.physmem.bytes_written 0 # Number of bytes written to this memory -system.physmem.num_reads 442 # Number of read requests responded to by this memory +system.physmem.num_reads 451 # Number of read requests responded to by this memory system.physmem.num_writes 0 # Number of write requests responded to by this memory system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 2359397806 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 1580049210 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total 2359397806 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read 2346762063 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 1571445994 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total 2346762063 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 11 # Number of system calls -system.cpu.numCycles 23980 # number of cpu cycles simulated +system.cpu.numCycles 24600 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 3019 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 3019 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 495 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 2695 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 978 # Number of BTB hits +system.cpu.BPredUnit.lookups 3225 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 3225 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 566 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 2653 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 811 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 7194 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 13831 # Number of instructions fetch has processed -system.cpu.fetch.Branches 3019 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 978 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 3921 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 2194 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 3367 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 9 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 1866 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 269 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 16182 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.543567 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.980612 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 7427 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 15574 # Number of instructions fetch has processed +system.cpu.fetch.Branches 3225 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 811 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 4199 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 2532 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 3117 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 33 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 203 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 1968 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 283 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 16907 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.630863 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.070076 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 12367 76.42% 76.42% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 166 1.03% 77.45% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 172 1.06% 78.51% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 238 1.47% 79.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 224 1.38% 81.37% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 191 1.18% 82.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 276 1.71% 84.25% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 137 0.85% 85.10% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 2411 14.90% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 12804 75.73% 75.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 179 1.06% 76.79% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 164 0.97% 77.76% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 216 1.28% 79.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 176 1.04% 80.08% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 185 1.09% 81.17% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 253 1.50% 82.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 169 1.00% 83.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 2761 16.33% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 16182 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.125897 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.576772 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 7550 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 3315 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 3508 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 122 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1687 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 23802 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 1687 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 7843 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 2077 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 553 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 3329 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 693 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 22457 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 2 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 68 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 553 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 21026 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 47090 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 47074 # Number of integer rename lookups +system.cpu.fetch.rateDist::total 16907 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.131098 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.633089 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 7993 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 3065 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 3795 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 126 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1928 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 26201 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 1928 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 8331 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 1936 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 442 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 3571 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 699 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 24623 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 3 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 40 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 586 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 22939 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 51440 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 51424 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 16 # Number of floating rename lookups system.cpu.rename.CommittedMaps 9368 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 11658 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 13571 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 33 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 33 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 1820 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2219 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1751 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 13 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 8 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 20306 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 37 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 16792 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 56 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 10001 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 12754 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 24 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 16182 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.037696 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.845376 # Number of insts issued each cycle +system.cpu.rename.skidInsts 1885 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2380 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1795 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 11 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 3 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 21756 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 39 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 17955 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 74 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 11342 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 13993 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 26 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 16907 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.061986 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.892645 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 10903 67.38% 67.38% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1372 8.48% 75.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 1062 6.56% 82.42% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 680 4.20% 86.62% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 659 4.07% 90.69% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 684 4.23% 94.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 588 3.63% 98.55% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 200 1.24% 99.79% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 34 0.21% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 11435 67.63% 67.63% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1387 8.20% 75.84% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 1028 6.08% 81.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 682 4.03% 85.95% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 697 4.12% 90.08% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 717 4.24% 94.32% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 667 3.95% 98.26% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 261 1.54% 99.80% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 33 0.20% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 16182 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 16907 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 86 64.66% 64.66% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 64.66% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 64.66% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 64.66% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 64.66% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 64.66% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 64.66% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 64.66% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 64.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 64.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 64.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 64.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 64.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 64.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 64.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 64.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 64.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 64.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 64.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 64.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 64.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 64.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 64.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 64.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 64.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 64.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 64.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 64.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 64.66% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 24 18.05% 82.71% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 23 17.29% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 147 74.24% 74.24% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 74.24% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 74.24% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 74.24% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 74.24% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 74.24% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 74.24% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 74.24% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 74.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 74.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 74.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 74.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 74.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 74.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 74.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 74.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 74.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 74.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 74.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 74.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 74.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 74.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 74.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 74.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 74.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 74.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 74.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 74.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 74.24% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 30 15.15% 89.39% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 21 10.61% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 4 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 13517 80.50% 80.52% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 80.52% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 80.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 80.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 80.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 80.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 80.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 80.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 80.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 80.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 80.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 80.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 80.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 80.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 80.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 80.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 80.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 80.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 80.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 80.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 80.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 80.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 80.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 80.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 80.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 80.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 80.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 80.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 80.52% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 1828 10.89% 91.41% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1443 8.59% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 14483 80.66% 80.69% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 80.69% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 80.69% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 80.69% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 80.69% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 80.69% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 80.69% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 80.69% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 80.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 80.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 80.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 80.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 80.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 80.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 80.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 80.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 80.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 80.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 80.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 80.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 80.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 80.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 80.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 80.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 80.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 80.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 80.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 80.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 80.69% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 1993 11.10% 91.79% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1475 8.21% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 16792 # Type of FU issued -system.cpu.iq.rate 0.700250 # Inst issue rate -system.cpu.iq.fu_busy_cnt 133 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.007920 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 49947 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 30352 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 15608 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 17955 # Type of FU issued +system.cpu.iq.rate 0.729878 # Inst issue rate +system.cpu.iq.fu_busy_cnt 198 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.011028 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 53081 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 33143 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 16452 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 8 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 4 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 4 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 16917 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 18145 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 4 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 142 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 152 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1163 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 12 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 12 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 817 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 1324 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 24 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 11 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 861 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1687 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1417 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 38 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 20343 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 26 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2219 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1751 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 33 # Number of dispatched non-speculative instructions +system.cpu.iew.iewSquashCycles 1928 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1329 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 36 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 21795 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 32 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2380 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1795 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 35 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 6 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 12 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 65 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 525 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 590 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 15942 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 1725 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 850 # Number of squashed instructions skipped in execute +system.cpu.iew.memOrderViolationEvents 11 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 63 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 653 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 716 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 16888 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 1847 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1067 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 3065 # number of memory reference insts executed -system.cpu.iew.exec_branches 1589 # Number of branches executed -system.cpu.iew.exec_stores 1340 # Number of stores executed -system.cpu.iew.exec_rate 0.664804 # Inst execution rate -system.cpu.iew.wb_sent 15766 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 15612 # cumulative count of insts written-back -system.cpu.iew.wb_producers 10251 # num instructions producing a value -system.cpu.iew.wb_consumers 15131 # num instructions consuming a value +system.cpu.iew.exec_refs 3212 # number of memory reference insts executed +system.cpu.iew.exec_branches 1649 # Number of branches executed +system.cpu.iew.exec_stores 1365 # Number of stores executed +system.cpu.iew.exec_rate 0.686504 # Inst execution rate +system.cpu.iew.wb_sent 16662 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 16456 # cumulative count of insts written-back +system.cpu.iew.wb_producers 10670 # num instructions producing a value +system.cpu.iew.wb_consumers 15796 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.651043 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.677483 # average fanout of values written-back +system.cpu.iew.wb_rate 0.668943 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.675487 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 5416 # The number of committed instructions system.cpu.commit.commitCommittedOps 9809 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 10533 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 11985 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 13 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 495 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 14495 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.676716 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.510487 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 593 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 14979 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.654850 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.499757 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 10831 74.72% 74.72% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1349 9.31% 84.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 680 4.69% 88.72% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 780 5.38% 94.10% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 337 2.32% 96.43% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 129 0.89% 97.32% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 140 0.97% 98.28% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 65 0.45% 98.73% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 184 1.27% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 11331 75.65% 75.65% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1373 9.17% 84.81% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 652 4.35% 89.16% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 726 4.85% 94.01% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 372 2.48% 96.50% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 130 0.87% 97.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 138 0.92% 98.28% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 68 0.45% 98.74% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 189 1.26% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 14495 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 14979 # Number of insts commited each cycle system.cpu.commit.committedInsts 5416 # Number of instructions committed system.cpu.commit.committedOps 9809 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -269,62 +269,62 @@ system.cpu.commit.branches 1214 # Nu system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. system.cpu.commit.int_insts 9714 # Number of committed integer instructions. system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 184 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 189 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 34653 # The number of ROB reads -system.cpu.rob.rob_writes 42403 # The number of ROB writes +system.cpu.rob.rob_reads 36584 # The number of ROB reads +system.cpu.rob.rob_writes 45550 # The number of ROB writes system.cpu.timesIdled 150 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 7798 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.idleCycles 7693 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 5416 # Number of Instructions Simulated system.cpu.committedOps 9809 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 5416 # Number of Instructions Simulated -system.cpu.cpi 4.427622 # CPI: Cycles Per Instruction -system.cpu.cpi_total 4.427622 # CPI: Total CPI of All Threads -system.cpu.ipc 0.225855 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.225855 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 23430 # number of integer regfile reads -system.cpu.int_regfile_writes 14518 # number of integer regfile writes +system.cpu.cpi 4.542097 # CPI: Cycles Per Instruction +system.cpu.cpi_total 4.542097 # CPI: Total CPI of All Threads +system.cpu.ipc 0.220163 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.220163 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 24791 # number of integer regfile reads +system.cpu.int_regfile_writes 15157 # number of integer regfile writes system.cpu.fp_regfile_reads 4 # number of floating regfile reads -system.cpu.misc_regfile_reads 7136 # number of misc regfile reads +system.cpu.misc_regfile_reads 7406 # number of misc regfile reads system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 140.870525 # Cycle average of tags in use -system.cpu.icache.total_refs 1498 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 298 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 5.026846 # Average number of references to valid blocks. +system.cpu.icache.tagsinuse 146.671178 # Cycle average of tags in use +system.cpu.icache.total_refs 1576 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 304 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 5.184211 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 140.870525 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.068784 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.068784 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 1498 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1498 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1498 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1498 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1498 # number of overall hits -system.cpu.icache.overall_hits::total 1498 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 368 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 368 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 368 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 368 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 368 # number of overall misses -system.cpu.icache.overall_misses::total 368 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 13394000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 13394000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 13394000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 13394000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 13394000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 13394000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1866 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1866 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1866 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1866 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1866 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1866 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.197213 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.197213 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.197213 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 36396.739130 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 36396.739130 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 36396.739130 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 146.671178 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.071617 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.071617 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 1576 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1576 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1576 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1576 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1576 # number of overall hits +system.cpu.icache.overall_hits::total 1576 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 392 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 392 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 392 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 392 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 392 # number of overall misses +system.cpu.icache.overall_misses::total 392 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 13905000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 13905000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 13905000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 13905000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 13905000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 13905000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1968 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1968 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1968 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1968 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1968 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1968 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.199187 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.199187 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.199187 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35471.938776 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 35471.938776 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 35471.938776 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -333,80 +333,80 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 70 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 70 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 70 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 70 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 70 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 70 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 298 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 298 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 298 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 298 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 298 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 298 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 10471500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 10471500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 10471500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 10471500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 10471500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 10471500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.159700 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.159700 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.159700 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35139.261745 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35139.261745 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35139.261745 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 88 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 88 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 88 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 88 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 88 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 88 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 304 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 304 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 304 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 304 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 304 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 304 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 10684500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 10684500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 10684500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 10684500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 10684500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 10684500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.154472 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.154472 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.154472 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35146.381579 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35146.381579 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35146.381579 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 83.526549 # Cycle average of tags in use -system.cpu.dcache.total_refs 2275 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 145 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 15.689655 # Average number of references to valid blocks. +system.cpu.dcache.tagsinuse 85.091432 # Cycle average of tags in use +system.cpu.dcache.total_refs 2365 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 148 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 15.979730 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 83.526549 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.020392 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.020392 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 1417 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1417 # number of ReadReq hits +system.cpu.dcache.occ_blocks::cpu.data 85.091432 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.020774 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.020774 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 1507 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1507 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 858 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 858 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 2275 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2275 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2275 # number of overall hits -system.cpu.dcache.overall_hits::total 2275 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 111 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 111 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 2365 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2365 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2365 # number of overall hits +system.cpu.dcache.overall_hits::total 2365 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 117 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 117 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 76 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 76 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 187 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 187 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 187 # number of overall misses -system.cpu.dcache.overall_misses::total 187 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 3859500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 3859500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 2916500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 2916500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 6776000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 6776000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 6776000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 6776000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1528 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1528 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 193 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 193 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 193 # number of overall misses +system.cpu.dcache.overall_misses::total 193 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 4056500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 4056500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 2917500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 2917500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 6974000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 6974000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 6974000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 6974000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1624 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1624 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 934 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 934 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2462 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2462 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2462 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2462 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.072644 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 2558 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2558 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2558 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2558 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.072044 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.081370 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.075955 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.075955 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34770.270270 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38375 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 36235.294118 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 36235.294118 # average overall miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.075450 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.075450 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34670.940171 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38388.157895 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 36134.715026 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 36134.715026 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -415,101 +415,101 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 41 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 41 # number of ReadReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 41 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 41 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 41 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 41 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 70 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 70 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 44 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 44 # number of ReadReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 44 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 44 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 44 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 44 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 73 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 73 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 76 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 76 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 146 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 146 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 146 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 146 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2463000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2463000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2688500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2688500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5151500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 5151500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5151500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 5151500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.045812 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_misses::cpu.data 149 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 149 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 149 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 149 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2572000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2572000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2689500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2689500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5261500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 5261500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5261500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 5261500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.044951 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.081370 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.059301 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.059301 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 35185.714286 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35375 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 35284.246575 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 35284.246575 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.058249 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.058249 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 35232.876712 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35388.157895 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 35312.080537 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 35312.080537 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 173.809724 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 180.810821 # Cycle average of tags in use system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 365 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.005479 # Average number of references to valid blocks. +system.cpu.l2cache.sampled_refs 374 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.005348 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 140.468506 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 33.341218 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.004287 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.001017 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.005304 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 146.260836 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 34.549985 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.004464 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.001054 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.005518 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::total 2 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.inst 2 # number of overall hits system.cpu.l2cache.overall_hits::total 2 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 296 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 70 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 366 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.inst 302 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 73 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 375 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 76 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 76 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 296 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 146 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 442 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 296 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 146 # number of overall misses -system.cpu.l2cache.overall_misses::total 442 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 10158000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2383000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 12541000 # number of ReadReq miss cycles +system.cpu.l2cache.demand_misses::cpu.inst 302 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 149 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 451 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 302 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 149 # number of overall misses +system.cpu.l2cache.overall_misses::total 451 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 10365500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2486500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 12852000 # number of ReadReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2603000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 2603000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 10158000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 4986000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 15144000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 10158000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 4986000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 15144000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 298 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 70 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 368 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.demand_miss_latency::cpu.inst 10365500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 5089500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 15455000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 10365500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 5089500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 15455000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 304 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 73 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 377 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 76 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 76 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 298 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 146 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 444 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 298 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 146 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 444 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.993289 # miss rate for ReadReq accesses +system.cpu.l2cache.demand_accesses::cpu.inst 304 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 149 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 453 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 304 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 149 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 453 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.993421 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.993289 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.993421 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993289 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993421 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34317.567568 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34042.857143 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34322.847682 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34061.643836 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34250 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34317.567568 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34150.684932 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34317.567568 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34150.684932 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34322.847682 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34157.718121 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34322.847682 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34157.718121 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -518,42 +518,42 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 296 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 70 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 366 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 302 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 73 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 375 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 76 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 76 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 296 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 146 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 442 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 296 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 146 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 442 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 9202000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2167000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 11369000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2368500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2368500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 9202000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4535500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 13737500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 9202000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4535500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 13737500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993289 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 302 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 149 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 451 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 302 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 149 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 451 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 9393500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2262000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 11655500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2369500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2369500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 9393500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4631500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 14025000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 9393500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4631500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 14025000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993421 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.993289 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.993421 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993289 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993421 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31087.837838 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 30957.142857 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31164.473684 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31087.837838 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31065.068493 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31087.837838 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31065.068493 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31104.304636 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 30986.301370 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31177.631579 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31104.304636 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31083.892617 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31104.304636 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31083.892617 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout index 4edc89b33..2e652c55a 100755 --- a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout +++ b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout @@ -1,8 +1,8 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 11 2012 13:05:17 -gem5 started Feb 11 2012 13:09:24 +gem5 compiled Feb 12 2012 17:15:14 +gem5 started Feb 12 2012 17:33:14 gem5 executing on zizzer command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/quick/se/01.hello-2T-smt/alpha/linux/o3-timing -re tests/run.py build/ALPHA/tests/fast/quick/se/01.hello-2T-smt/alpha/linux/o3-timing Global frequency set at 1000000000000 ticks per second @@ -11,4 +11,4 @@ info: Increasing stack size by one page. info: Increasing stack size by one page. Hello world! Hello world! -Exiting @ tick 13202000 because target called exit() +Exiting @ tick 13973500 because target called exit() diff --git a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt index 292756fa3..f99bdda93 100644 --- a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt +++ b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt @@ -1,45 +1,45 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000013 # Number of seconds simulated -sim_ticks 13202000 # Number of ticks simulated -final_tick 13202000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000014 # Number of seconds simulated +sim_ticks 13973500 # Number of ticks simulated +final_tick 13973500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 91406 # Simulator instruction rate (inst/s) -host_op_rate 91394 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 94452628 # Simulator tick rate (ticks/s) -host_mem_usage 210624 # Number of bytes of host memory used +host_inst_rate 94205 # Simulator instruction rate (inst/s) +host_op_rate 94192 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 103032063 # Simulator tick rate (ticks/s) +host_mem_usage 210576 # Number of bytes of host memory used host_seconds 0.14 # Real time elapsed on the host sim_insts 12773 # Number of instructions simulated sim_ops 12773 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 62144 # Number of bytes read from this memory -system.physmem.bytes_inst_read 39936 # Number of instructions bytes read from this memory +system.physmem.bytes_read 62784 # Number of bytes read from this memory +system.physmem.bytes_inst_read 40192 # Number of instructions bytes read from this memory system.physmem.bytes_written 0 # Number of bytes written to this memory -system.physmem.num_reads 971 # Number of read requests responded to by this memory +system.physmem.num_reads 981 # Number of read requests responded to by this memory system.physmem.num_writes 0 # Number of write requests responded to by this memory system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 4707165581 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 3024996213 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total 4707165581 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read 4493076180 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 2876301571 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total 4493076180 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 3722 # DTB read hits -system.cpu.dtb.read_misses 94 # DTB read misses +system.cpu.dtb.read_hits 4112 # DTB read hits +system.cpu.dtb.read_misses 99 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 3816 # DTB read accesses -system.cpu.dtb.write_hits 1984 # DTB write hits -system.cpu.dtb.write_misses 61 # DTB write misses +system.cpu.dtb.read_accesses 4211 # DTB read accesses +system.cpu.dtb.write_hits 2113 # DTB write hits +system.cpu.dtb.write_misses 55 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 2045 # DTB write accesses -system.cpu.dtb.data_hits 5706 # DTB hits -system.cpu.dtb.data_misses 155 # DTB misses +system.cpu.dtb.write_accesses 2168 # DTB write accesses +system.cpu.dtb.data_hits 6225 # DTB hits +system.cpu.dtb.data_misses 154 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 5861 # DTB accesses -system.cpu.itb.fetch_hits 4091 # ITB hits -system.cpu.itb.fetch_misses 56 # ITB misses +system.cpu.dtb.data_accesses 6379 # DTB accesses +system.cpu.itb.fetch_hits 5262 # ITB hits +system.cpu.itb.fetch_misses 46 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 4147 # ITB accesses +system.cpu.itb.fetch_accesses 5308 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -54,360 +54,361 @@ system.cpu.itb.data_acv 0 # DT system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload0.num_syscalls 17 # Number of system calls system.cpu.workload1.num_syscalls 17 # Number of system calls -system.cpu.numCycles 26405 # number of cpu cycles simulated +system.cpu.numCycles 27948 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 5174 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 2964 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 1252 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 3548 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 1004 # Number of BTB hits +system.cpu.BPredUnit.lookups 6404 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 3641 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 1747 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 4779 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 777 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 734 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 158 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 1115 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 28962 # Number of instructions fetch has processed -system.cpu.fetch.Branches 5174 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 1738 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 4987 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1325 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 44 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.CacheLines 4091 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 637 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 20201 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.433691 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.801868 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 907 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 237 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 1564 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 36319 # Number of instructions fetch has processed +system.cpu.fetch.Branches 6404 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 1684 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 6095 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1819 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 42 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.CacheLines 5262 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 778 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 22184 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.637171 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.955550 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 15214 75.31% 75.31% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 449 2.22% 77.54% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 365 1.81% 79.34% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 384 1.90% 81.24% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 390 1.93% 83.17% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 328 1.62% 84.80% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 404 2.00% 86.80% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 329 1.63% 88.43% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 2338 11.57% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 16089 72.53% 72.53% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 484 2.18% 74.71% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 383 1.73% 76.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 489 2.20% 78.64% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 412 1.86% 80.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 381 1.72% 82.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 471 2.12% 84.34% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 577 2.60% 86.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 2898 13.06% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 20201 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.195948 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.096838 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 27985 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 5533 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 4328 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 445 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1869 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 485 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 315 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 25962 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 512 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1869 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 28534 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 2990 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 752 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 4136 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 1879 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 24542 # Number of instructions processed by rename +system.cpu.fetch.rateDist::total 22184 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.229140 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.299521 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 30972 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 4872 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 5207 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 530 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 2493 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 640 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 419 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 31709 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 698 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 2493 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 31718 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 2312 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 672 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 4929 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 1950 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 29261 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 12 # Number of times rename has blocked due to ROB full -system.cpu.rename.LSQFullEvents 1739 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 18358 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 30575 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 30541 # Number of integer rename lookups +system.cpu.rename.IQFullEvents 6 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 1965 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 22098 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 36589 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 36555 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 34 # Number of floating rename lookups system.cpu.rename.CommittedMaps 9166 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 9192 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 52 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 40 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 4646 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2308 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1190 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1 # Number of conflicting loads. +system.cpu.rename.UndoneMaps 12932 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 50 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 38 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 5419 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2664 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1324 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 9 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. -system.cpu.memDep1.insertedLoads 2319 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep1.insertedStores 1181 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep1.conflictingLoads 3 # Number of conflicting loads. +system.cpu.memDep1.insertedLoads 2650 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep1.insertedStores 1324 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep1.conflictingLoads 24 # Number of conflicting loads. system.cpu.memDep1.conflictingStores 0 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 22288 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 49 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 19435 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 67 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 8694 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 4709 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 15 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 20201 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.962081 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.481018 # Number of insts issued each cycle +system.cpu.iq.iqInstsAdded 25756 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 47 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 21797 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 116 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 11896 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 6581 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 13 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 22184 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.982555 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.521995 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 11990 59.35% 59.35% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 2928 14.49% 73.85% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 2232 11.05% 84.90% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 1366 6.76% 91.66% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 891 4.41% 96.07% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 479 2.37% 98.44% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 237 1.17% 99.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 60 0.30% 99.91% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 18 0.09% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 13300 59.95% 59.95% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 3017 13.60% 73.55% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 2291 10.33% 83.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 1563 7.05% 90.93% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 1046 4.72% 95.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 585 2.64% 98.28% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 293 1.32% 99.60% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 70 0.32% 99.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 19 0.09% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 20201 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 22184 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 9 4.92% 4.92% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 4.92% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 4.92% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.92% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.92% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.92% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 4.92% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.92% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 4.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 4.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.92% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 106 57.92% 62.84% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 68 37.16% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 16 8.00% 8.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 8.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 8.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 8.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 8.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 8.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 8.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 8.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 8.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 8.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 8.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 8.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 8.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 8.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 8.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 8.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 8.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 8.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 8.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 8.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 8.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 8.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 8.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 8.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 8.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 8.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 8.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 8.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 115 57.50% 65.50% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 69 34.50% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 6617 67.89% 67.91% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 1 0.01% 67.92% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.92% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 67.94% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.94% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.94% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.94% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.94% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.94% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.94% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.94% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.94% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.94% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.94% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.94% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.94% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.94% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.94% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.94% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.94% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.94% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.94% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.94% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.94% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.94% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.94% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.94% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.94% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.94% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2056 21.09% 89.03% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1069 10.97% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 7481 68.23% 68.24% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 1 0.01% 68.25% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.25% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 68.27% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.27% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.27% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.27% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 68.27% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.27% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2338 21.32% 89.59% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1141 10.41% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 9747 # Type of FU issued +system.cpu.iq.FU_type_0::total 10965 # Type of FU issued system.cpu.iq.FU_type_1::No_OpClass 2 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type_1::IntAlu 6565 67.76% 67.78% # Type of FU issued -system.cpu.iq.FU_type_1::IntMult 1 0.01% 67.80% # Type of FU issued -system.cpu.iq.FU_type_1::IntDiv 0 0.00% 67.80% # Type of FU issued -system.cpu.iq.FU_type_1::FloatAdd 2 0.02% 67.82% # Type of FU issued -system.cpu.iq.FU_type_1::FloatCmp 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_1::FloatCvt 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_1::FloatMult 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_1::FloatDiv 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_1::FloatSqrt 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_1::SimdAdd 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_1::SimdAddAcc 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_1::SimdAlu 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_1::SimdCmp 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_1::SimdCvt 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_1::SimdMisc 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_1::SimdMult 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_1::SimdMultAcc 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_1::SimdShift 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_1::SimdShiftAcc 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_1::SimdSqrt 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatAdd 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatAlu 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatCmp 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatCvt 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatDiv 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatMisc 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatMult 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatMultAcc 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatSqrt 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_1::MemRead 2046 21.12% 88.93% # Type of FU issued -system.cpu.iq.FU_type_1::MemWrite 1072 11.07% 100.00% # Type of FU issued +system.cpu.iq.FU_type_1::IntAlu 7346 67.82% 67.84% # Type of FU issued +system.cpu.iq.FU_type_1::IntMult 1 0.01% 67.85% # Type of FU issued +system.cpu.iq.FU_type_1::IntDiv 0 0.00% 67.85% # Type of FU issued +system.cpu.iq.FU_type_1::FloatAdd 2 0.02% 67.86% # Type of FU issued +system.cpu.iq.FU_type_1::FloatCmp 0 0.00% 67.86% # Type of FU issued +system.cpu.iq.FU_type_1::FloatCvt 0 0.00% 67.86% # Type of FU issued +system.cpu.iq.FU_type_1::FloatMult 0 0.00% 67.86% # Type of FU issued +system.cpu.iq.FU_type_1::FloatDiv 0 0.00% 67.86% # Type of FU issued +system.cpu.iq.FU_type_1::FloatSqrt 0 0.00% 67.86% # Type of FU issued +system.cpu.iq.FU_type_1::SimdAdd 0 0.00% 67.86% # Type of FU issued +system.cpu.iq.FU_type_1::SimdAddAcc 0 0.00% 67.86% # Type of FU issued +system.cpu.iq.FU_type_1::SimdAlu 0 0.00% 67.86% # Type of FU issued +system.cpu.iq.FU_type_1::SimdCmp 0 0.00% 67.86% # Type of FU issued +system.cpu.iq.FU_type_1::SimdCvt 0 0.00% 67.86% # Type of FU issued +system.cpu.iq.FU_type_1::SimdMisc 0 0.00% 67.86% # Type of FU issued +system.cpu.iq.FU_type_1::SimdMult 0 0.00% 67.86% # Type of FU issued +system.cpu.iq.FU_type_1::SimdMultAcc 0 0.00% 67.86% # Type of FU issued +system.cpu.iq.FU_type_1::SimdShift 0 0.00% 67.86% # Type of FU issued +system.cpu.iq.FU_type_1::SimdShiftAcc 0 0.00% 67.86% # Type of FU issued +system.cpu.iq.FU_type_1::SimdSqrt 0 0.00% 67.86% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatAdd 0 0.00% 67.86% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatAlu 0 0.00% 67.86% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatCmp 0 0.00% 67.86% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatCvt 0 0.00% 67.86% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatDiv 0 0.00% 67.86% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatMisc 0 0.00% 67.86% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatMult 0 0.00% 67.86% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatMultAcc 0 0.00% 67.86% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatSqrt 0 0.00% 67.86% # Type of FU issued +system.cpu.iq.FU_type_1::MemRead 2331 21.52% 89.38% # Type of FU issued +system.cpu.iq.FU_type_1::MemWrite 1150 10.62% 100.00% # Type of FU issued system.cpu.iq.FU_type_1::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_1::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_1::total 9688 # Type of FU issued +system.cpu.iq.FU_type_1::total 10832 # Type of FU issued system.cpu.iq.FU_type::No_OpClass 4 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type::IntAlu 13182 67.83% 67.85% # Type of FU issued -system.cpu.iq.FU_type::IntMult 2 0.01% 67.86% # Type of FU issued -system.cpu.iq.FU_type::IntDiv 0 0.00% 67.86% # Type of FU issued -system.cpu.iq.FU_type::FloatAdd 4 0.02% 67.88% # Type of FU issued -system.cpu.iq.FU_type::FloatCmp 0 0.00% 67.88% # Type of FU issued -system.cpu.iq.FU_type::FloatCvt 0 0.00% 67.88% # Type of FU issued -system.cpu.iq.FU_type::FloatMult 0 0.00% 67.88% # Type of FU issued -system.cpu.iq.FU_type::FloatDiv 0 0.00% 67.88% # Type of FU issued -system.cpu.iq.FU_type::FloatSqrt 0 0.00% 67.88% # Type of FU issued -system.cpu.iq.FU_type::SimdAdd 0 0.00% 67.88% # Type of FU issued -system.cpu.iq.FU_type::SimdAddAcc 0 0.00% 67.88% # Type of FU issued -system.cpu.iq.FU_type::SimdAlu 0 0.00% 67.88% # Type of FU issued -system.cpu.iq.FU_type::SimdCmp 0 0.00% 67.88% # Type of FU issued -system.cpu.iq.FU_type::SimdCvt 0 0.00% 67.88% # Type of FU issued -system.cpu.iq.FU_type::SimdMisc 0 0.00% 67.88% # Type of FU issued -system.cpu.iq.FU_type::SimdMult 0 0.00% 67.88% # Type of FU issued -system.cpu.iq.FU_type::SimdMultAcc 0 0.00% 67.88% # Type of FU issued -system.cpu.iq.FU_type::SimdShift 0 0.00% 67.88% # Type of FU issued -system.cpu.iq.FU_type::SimdShiftAcc 0 0.00% 67.88% # Type of FU issued -system.cpu.iq.FU_type::SimdSqrt 0 0.00% 67.88% # Type of FU issued -system.cpu.iq.FU_type::SimdFloatAdd 0 0.00% 67.88% # Type of FU issued -system.cpu.iq.FU_type::SimdFloatAlu 0 0.00% 67.88% # Type of FU issued -system.cpu.iq.FU_type::SimdFloatCmp 0 0.00% 67.88% # Type of FU issued -system.cpu.iq.FU_type::SimdFloatCvt 0 0.00% 67.88% # Type of FU issued -system.cpu.iq.FU_type::SimdFloatDiv 0 0.00% 67.88% # Type of FU issued -system.cpu.iq.FU_type::SimdFloatMisc 0 0.00% 67.88% # Type of FU issued -system.cpu.iq.FU_type::SimdFloatMult 0 0.00% 67.88% # Type of FU issued -system.cpu.iq.FU_type::SimdFloatMultAcc 0 0.00% 67.88% # Type of FU issued -system.cpu.iq.FU_type::SimdFloatSqrt 0 0.00% 67.88% # Type of FU issued -system.cpu.iq.FU_type::MemRead 4102 21.11% 88.98% # Type of FU issued -system.cpu.iq.FU_type::MemWrite 2141 11.02% 100.00% # Type of FU issued +system.cpu.iq.FU_type::IntAlu 14827 68.02% 68.04% # Type of FU issued +system.cpu.iq.FU_type::IntMult 2 0.01% 68.05% # Type of FU issued +system.cpu.iq.FU_type::IntDiv 0 0.00% 68.05% # Type of FU issued +system.cpu.iq.FU_type::FloatAdd 4 0.02% 68.07% # Type of FU issued +system.cpu.iq.FU_type::FloatCmp 0 0.00% 68.07% # Type of FU issued +system.cpu.iq.FU_type::FloatCvt 0 0.00% 68.07% # Type of FU issued +system.cpu.iq.FU_type::FloatMult 0 0.00% 68.07% # Type of FU issued +system.cpu.iq.FU_type::FloatDiv 0 0.00% 68.07% # Type of FU issued +system.cpu.iq.FU_type::FloatSqrt 0 0.00% 68.07% # Type of FU issued +system.cpu.iq.FU_type::SimdAdd 0 0.00% 68.07% # Type of FU issued +system.cpu.iq.FU_type::SimdAddAcc 0 0.00% 68.07% # Type of FU issued +system.cpu.iq.FU_type::SimdAlu 0 0.00% 68.07% # Type of FU issued +system.cpu.iq.FU_type::SimdCmp 0 0.00% 68.07% # Type of FU issued +system.cpu.iq.FU_type::SimdCvt 0 0.00% 68.07% # Type of FU issued +system.cpu.iq.FU_type::SimdMisc 0 0.00% 68.07% # Type of FU issued +system.cpu.iq.FU_type::SimdMult 0 0.00% 68.07% # Type of FU issued +system.cpu.iq.FU_type::SimdMultAcc 0 0.00% 68.07% # Type of FU issued +system.cpu.iq.FU_type::SimdShift 0 0.00% 68.07% # Type of FU issued +system.cpu.iq.FU_type::SimdShiftAcc 0 0.00% 68.07% # Type of FU issued +system.cpu.iq.FU_type::SimdSqrt 0 0.00% 68.07% # Type of FU issued +system.cpu.iq.FU_type::SimdFloatAdd 0 0.00% 68.07% # Type of FU issued +system.cpu.iq.FU_type::SimdFloatAlu 0 0.00% 68.07% # Type of FU issued +system.cpu.iq.FU_type::SimdFloatCmp 0 0.00% 68.07% # Type of FU issued +system.cpu.iq.FU_type::SimdFloatCvt 0 0.00% 68.07% # Type of FU issued +system.cpu.iq.FU_type::SimdFloatDiv 0 0.00% 68.07% # Type of FU issued +system.cpu.iq.FU_type::SimdFloatMisc 0 0.00% 68.07% # Type of FU issued +system.cpu.iq.FU_type::SimdFloatMult 0 0.00% 68.07% # Type of FU issued +system.cpu.iq.FU_type::SimdFloatMultAcc 0 0.00% 68.07% # Type of FU issued +system.cpu.iq.FU_type::SimdFloatSqrt 0 0.00% 68.07% # Type of FU issued +system.cpu.iq.FU_type::MemRead 4669 21.42% 89.49% # Type of FU issued +system.cpu.iq.FU_type::MemWrite 2291 10.51% 100.00% # Type of FU issued system.cpu.iq.FU_type::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type::total 19435 # Type of FU issued -system.cpu.iq.rate 0.736035 # Inst issue rate -system.cpu.iq.fu_busy_cnt::0 94 # FU busy when requested -system.cpu.iq.fu_busy_cnt::1 89 # FU busy when requested -system.cpu.iq.fu_busy_cnt::total 183 # FU busy when requested -system.cpu.iq.fu_busy_rate::0 0.004837 # FU busy rate (busy events/executed inst) -system.cpu.iq.fu_busy_rate::1 0.004579 # FU busy rate (busy events/executed inst) -system.cpu.iq.fu_busy_rate::total 0.009416 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 59279 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 31036 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 17747 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type::total 21797 # Type of FU issued +system.cpu.iq.rate 0.779913 # Inst issue rate +system.cpu.iq.fu_busy_cnt::0 93 # FU busy when requested +system.cpu.iq.fu_busy_cnt::1 107 # FU busy when requested +system.cpu.iq.fu_busy_cnt::total 200 # FU busy when requested +system.cpu.iq.fu_busy_rate::0 0.004267 # FU busy rate (busy events/executed inst) +system.cpu.iq.fu_busy_rate::1 0.004909 # FU busy rate (busy events/executed inst) +system.cpu.iq.fu_busy_rate::total 0.009176 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 66052 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 37703 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 19403 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 42 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 20 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 20 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 19592 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 21971 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 22 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 48 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 51 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1123 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 13 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 325 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 1479 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 11 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 459 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread1.forwLoads 61 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread1.forwLoads 72 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread1.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread1.squashedLoads 1134 # Number of loads squashed -system.cpu.iew.lsq.thread1.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread1.memOrderViolation 14 # Number of memory ordering violations -system.cpu.iew.lsq.thread1.squashedStores 316 # Number of stores squashed +system.cpu.iew.lsq.thread1.squashedLoads 1465 # Number of loads squashed +system.cpu.iew.lsq.thread1.ignoredResponses 6 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread1.memOrderViolation 19 # Number of memory ordering violations +system.cpu.iew.lsq.thread1.squashedStores 459 # Number of stores squashed system.cpu.iew.lsq.thread1.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread1.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread1.rescheduledLoads 1 # Number of loads that were rescheduled system.cpu.iew.lsq.thread1.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1869 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1204 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 64 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 22477 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 401 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 4627 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 2371 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 49 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 38 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 1 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 27 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 218 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 882 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1100 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 18425 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts::0 1901 # Number of load instructions executed -system.cpu.iew.iewExecLoadInsts::1 1921 # Number of load instructions executed -system.cpu.iew.iewExecLoadInsts::total 3822 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1010 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 2493 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 461 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 37 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 25944 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 945 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 5314 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 2648 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 47 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 29 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 2 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 30 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 326 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 1247 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1573 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 20270 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts::0 2100 # Number of load instructions executed +system.cpu.iew.iewExecLoadInsts::1 2134 # Number of load instructions executed +system.cpu.iew.iewExecLoadInsts::total 4234 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1527 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp::0 0 # number of swp insts executed system.cpu.iew.exec_swp::1 0 # number of swp insts executed system.cpu.iew.exec_swp::total 0 # number of swp insts executed -system.cpu.iew.exec_nop::0 75 # number of nop insts executed -system.cpu.iew.exec_nop::1 65 # number of nop insts executed -system.cpu.iew.exec_nop::total 140 # number of nop insts executed -system.cpu.iew.exec_refs::0 2932 # number of memory reference insts executed -system.cpu.iew.exec_refs::1 2948 # number of memory reference insts executed -system.cpu.iew.exec_refs::total 5880 # number of memory reference insts executed -system.cpu.iew.exec_branches::0 1521 # Number of branches executed -system.cpu.iew.exec_branches::1 1526 # Number of branches executed -system.cpu.iew.exec_branches::total 3047 # Number of branches executed -system.cpu.iew.exec_stores::0 1031 # Number of stores executed -system.cpu.iew.exec_stores::1 1027 # Number of stores executed -system.cpu.iew.exec_stores::total 2058 # Number of stores executed -system.cpu.iew.exec_rate 0.697785 # Inst execution rate -system.cpu.iew.wb_sent::0 9024 # cumulative count of insts sent to commit -system.cpu.iew.wb_sent::1 8991 # cumulative count of insts sent to commit -system.cpu.iew.wb_sent::total 18015 # cumulative count of insts sent to commit -system.cpu.iew.wb_count::0 8913 # cumulative count of insts written-back -system.cpu.iew.wb_count::1 8854 # cumulative count of insts written-back -system.cpu.iew.wb_count::total 17767 # cumulative count of insts written-back -system.cpu.iew.wb_producers::0 4555 # num instructions producing a value -system.cpu.iew.wb_producers::1 4549 # num instructions producing a value -system.cpu.iew.wb_producers::total 9104 # num instructions producing a value -system.cpu.iew.wb_consumers::0 5963 # num instructions consuming a value -system.cpu.iew.wb_consumers::1 5961 # num instructions consuming a value -system.cpu.iew.wb_consumers::total 11924 # num instructions consuming a value +system.cpu.iew.exec_nop::0 72 # number of nop insts executed +system.cpu.iew.exec_nop::1 69 # number of nop insts executed +system.cpu.iew.exec_nop::total 141 # number of nop insts executed +system.cpu.iew.exec_refs::0 3199 # number of memory reference insts executed +system.cpu.iew.exec_refs::1 3222 # number of memory reference insts executed +system.cpu.iew.exec_refs::total 6421 # number of memory reference insts executed +system.cpu.iew.exec_branches::0 1640 # Number of branches executed +system.cpu.iew.exec_branches::1 1645 # Number of branches executed +system.cpu.iew.exec_branches::total 3285 # Number of branches executed +system.cpu.iew.exec_stores::0 1099 # Number of stores executed +system.cpu.iew.exec_stores::1 1088 # Number of stores executed +system.cpu.iew.exec_stores::total 2187 # Number of stores executed +system.cpu.iew.exec_rate 0.725276 # Inst execution rate +system.cpu.iew.wb_sent::0 9893 # cumulative count of insts sent to commit +system.cpu.iew.wb_sent::1 9800 # cumulative count of insts sent to commit +system.cpu.iew.wb_sent::total 19693 # cumulative count of insts sent to commit +system.cpu.iew.wb_count::0 9771 # cumulative count of insts written-back +system.cpu.iew.wb_count::1 9652 # cumulative count of insts written-back +system.cpu.iew.wb_count::total 19423 # cumulative count of insts written-back +system.cpu.iew.wb_producers::0 5068 # num instructions producing a value +system.cpu.iew.wb_producers::1 5042 # num instructions producing a value +system.cpu.iew.wb_producers::total 10110 # num instructions producing a value +system.cpu.iew.wb_consumers::0 6625 # num instructions consuming a value +system.cpu.iew.wb_consumers::1 6584 # num instructions consuming a value +system.cpu.iew.wb_consumers::total 13209 # num instructions consuming a value system.cpu.iew.wb_penalized::0 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.wb_penalized::1 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.wb_penalized::total 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate::0 0.337550 # insts written-back per cycle -system.cpu.iew.wb_rate::1 0.335315 # insts written-back per cycle -system.cpu.iew.wb_rate::total 0.672865 # insts written-back per cycle -system.cpu.iew.wb_fanout::0 0.763877 # average fanout of values written-back -system.cpu.iew.wb_fanout::1 0.763127 # average fanout of values written-back -system.cpu.iew.wb_fanout::total 1.527004 # average fanout of values written-back +system.cpu.iew.wb_rate::0 0.349614 # insts written-back per cycle +system.cpu.iew.wb_rate::1 0.345356 # insts written-back per cycle +system.cpu.iew.wb_rate::total 0.694969 # insts written-back per cycle +system.cpu.iew.wb_fanout::0 0.764981 # average fanout of values written-back +system.cpu.iew.wb_fanout::1 0.765796 # average fanout of values written-back +system.cpu.iew.wb_fanout::total 1.530777 # average fanout of values written-back system.cpu.iew.wb_penalized_rate::0 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.iew.wb_penalized_rate::1 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.iew.wb_penalized_rate::total 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 12807 # The number of committed instructions system.cpu.commit.commitCommittedOps 12807 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 9596 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 13040 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 34 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 953 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 20176 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.634764 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.436773 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 1358 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 22111 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.579214 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.379258 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 14631 72.52% 72.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 2865 14.20% 86.72% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 1050 5.20% 91.92% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 518 2.57% 94.49% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 346 1.71% 96.20% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 239 1.18% 97.39% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 208 1.03% 98.42% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 91 0.45% 98.87% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 228 1.13% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 16588 75.02% 75.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 2733 12.36% 87.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 1194 5.40% 92.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 519 2.35% 95.13% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 313 1.42% 96.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 257 1.16% 97.71% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 189 0.85% 98.56% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 86 0.39% 98.95% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 232 1.05% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 20176 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 22111 # Number of insts commited each cycle system.cpu.commit.committedInsts::0 6403 # Number of instructions committed system.cpu.commit.committedInsts::1 6404 # Number of instructions committed system.cpu.commit.committedInsts::total 12807 # Number of instructions committed @@ -438,72 +439,72 @@ system.cpu.commit.int_insts::total 12642 # Nu system.cpu.commit.function_calls::0 127 # Number of function calls committed. system.cpu.commit.function_calls::1 127 # Number of function calls committed. system.cpu.commit.function_calls::total 254 # Number of function calls committed. -system.cpu.commit.bw_lim_events 228 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 232 # number cycles where commit BW limit reached system.cpu.commit.bw_limited::0 0 # number of insts not committed due to BW limits system.cpu.commit.bw_limited::1 0 # number of insts not committed due to BW limits system.cpu.commit.bw_limited::total 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 101307 # The number of ROB reads -system.cpu.rob.rob_writes 46689 # The number of ROB writes -system.cpu.timesIdled 233 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 6204 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 114163 # The number of ROB reads +system.cpu.rob.rob_writes 54209 # The number of ROB writes +system.cpu.timesIdled 228 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 5764 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts::0 6386 # Number of Instructions Simulated system.cpu.committedInsts::1 6387 # Number of Instructions Simulated system.cpu.committedOps::0 6386 # Number of Ops (including micro ops) Simulated system.cpu.committedOps::1 6387 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 12773 # Number of Instructions Simulated -system.cpu.cpi::0 4.134826 # CPI: Cycles Per Instruction -system.cpu.cpi::1 4.134179 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.067251 # CPI: Total CPI of All Threads -system.cpu.ipc::0 0.241848 # IPC: Instructions Per Cycle -system.cpu.ipc::1 0.241886 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.483734 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 23374 # number of integer regfile reads -system.cpu.int_regfile_writes 13316 # number of integer regfile writes +system.cpu.cpi::0 4.376448 # CPI: Cycles Per Instruction +system.cpu.cpi::1 4.375763 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.188053 # CPI: Total CPI of All Threads +system.cpu.ipc::0 0.228496 # IPC: Instructions Per Cycle +system.cpu.ipc::1 0.228532 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.457027 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 25651 # number of integer regfile reads +system.cpu.int_regfile_writes 14680 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads system.cpu.fp_regfile_writes 4 # number of floating regfile writes system.cpu.misc_regfile_reads 2 # number of misc regfile reads system.cpu.misc_regfile_writes 2 # number of misc regfile writes -system.cpu.icache.replacements::0 6 # number of replacements +system.cpu.icache.replacements::0 7 # number of replacements system.cpu.icache.replacements::1 0 # number of replacements -system.cpu.icache.replacements::total 6 # number of replacements -system.cpu.icache.tagsinuse 314.165301 # Cycle average of tags in use -system.cpu.icache.total_refs 3236 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 626 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 5.169329 # Average number of references to valid blocks. +system.cpu.icache.replacements::total 7 # number of replacements +system.cpu.icache.tagsinuse 324.653687 # Cycle average of tags in use +system.cpu.icache.total_refs 4369 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 631 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 6.923930 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 314.165301 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.153401 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.153401 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 3236 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 3236 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 3236 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 3236 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 3236 # number of overall hits -system.cpu.icache.overall_hits::total 3236 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 855 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 855 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 855 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 855 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 855 # number of overall misses -system.cpu.icache.overall_misses::total 855 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 30710500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 30710500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 30710500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 30710500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 30710500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 30710500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 4091 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 4091 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 4091 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 4091 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 4091 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 4091 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.208995 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.208995 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.208995 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35918.713450 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 35918.713450 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 35918.713450 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 324.653687 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.158522 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.158522 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 4369 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 4369 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 4369 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 4369 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 4369 # number of overall hits +system.cpu.icache.overall_hits::total 4369 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 893 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 893 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 893 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 893 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 893 # number of overall misses +system.cpu.icache.overall_misses::total 893 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 31736000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 31736000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 31736000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 31736000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 31736000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 31736000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 5262 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 5262 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 5262 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 5262 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 5262 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 5262 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.169707 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.169707 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.169707 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35538.633819 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 35538.633819 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 35538.633819 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -512,82 +513,82 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 229 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 229 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 229 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 229 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 229 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 229 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 626 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 626 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 626 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 626 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 626 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 626 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22267000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 22267000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22267000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 22267000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22267000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 22267000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.153019 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.153019 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.153019 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35570.287540 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35570.287540 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35570.287540 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 262 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 262 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 262 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 262 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 262 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 262 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 631 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 631 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 631 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 631 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 631 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 631 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22442500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 22442500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22442500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 22442500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22442500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 22442500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.119916 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.119916 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.119916 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35566.561014 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35566.561014 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35566.561014 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements::0 0 # number of replacements system.cpu.dcache.replacements::1 0 # number of replacements system.cpu.dcache.replacements::total 0 # number of replacements -system.cpu.dcache.tagsinuse 216.133399 # Cycle average of tags in use -system.cpu.dcache.total_refs 4323 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 347 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 12.458213 # Average number of references to valid blocks. +system.cpu.dcache.tagsinuse 221.504894 # Cycle average of tags in use +system.cpu.dcache.total_refs 4696 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 353 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 13.303116 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 216.133399 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.052767 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.052767 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 3303 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 3303 # number of ReadReq hits +system.cpu.dcache.occ_blocks::cpu.data 221.504894 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.054078 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.054078 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 3676 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 3676 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 1020 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 1020 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 4323 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 4323 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 4323 # number of overall hits -system.cpu.dcache.overall_hits::total 4323 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 308 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 308 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 4696 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 4696 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 4696 # number of overall hits +system.cpu.dcache.overall_hits::total 4696 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 311 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 311 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 710 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 710 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 1018 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1018 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1018 # number of overall misses -system.cpu.dcache.overall_misses::total 1018 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 11179500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 11179500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 24106500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 24106500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 35286000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 35286000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 35286000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 35286000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 3611 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 3611 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 1021 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1021 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1021 # number of overall misses +system.cpu.dcache.overall_misses::total 1021 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 11221000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 11221000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 22533500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 22533500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 33754500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 33754500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 33754500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 33754500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 3987 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 3987 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 1730 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 1730 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 5341 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 5341 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 5341 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 5341 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.085295 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 5717 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 5717 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 5717 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 5717 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.078004 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.410405 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.190601 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.190601 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 36297.077922 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33952.816901 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 34662.082515 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 34662.082515 # average overall miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.178590 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.178590 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 36080.385852 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31737.323944 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 33060.235064 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 33060.235064 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -596,105 +597,105 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 107 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 107 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 104 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 104 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 564 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 564 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 671 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 671 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 671 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 671 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 201 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 201 # number of ReadReq MSHR misses +system.cpu.dcache.demand_mshr_hits::cpu.data 668 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 668 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 668 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 668 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 207 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 207 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 146 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 146 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 347 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 347 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 347 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 347 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7376000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 7376000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5298000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5298000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12674000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 12674000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12674000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 12674000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.055663 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_misses::cpu.data 353 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 353 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 353 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 353 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7607500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 7607500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5291500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5291500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12899000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 12899000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12899000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 12899000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.051919 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.064969 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.064969 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 36696.517413 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 36287.671233 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 36524.495677 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 36524.495677 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.061746 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.061746 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 36751.207729 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 36243.150685 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 36541.076487 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 36541.076487 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements::0 0 # number of replacements system.cpu.l2cache.replacements::1 0 # number of replacements system.cpu.l2cache.replacements::total 0 # number of replacements -system.cpu.l2cache.tagsinuse 435.235373 # Cycle average of tags in use -system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 825 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.002424 # Average number of references to valid blocks. +system.cpu.l2cache.tagsinuse 449.601344 # Cycle average of tags in use +system.cpu.l2cache.total_refs 3 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 835 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.003593 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 314.499531 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 120.735842 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.009598 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.003685 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.013282 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits -system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 2 # number of overall hits -system.cpu.l2cache.overall_hits::total 2 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 624 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 201 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 825 # number of ReadReq misses +system.cpu.l2cache.occ_blocks::cpu.inst 324.972112 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 124.629233 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.009917 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.003803 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.013721 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 3 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 3 # number of ReadReq hits +system.cpu.l2cache.demand_hits::cpu.inst 3 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 3 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 3 # number of overall hits +system.cpu.l2cache.overall_hits::total 3 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 628 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 207 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 835 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 146 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 146 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 624 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 347 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 971 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 624 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 347 # number of overall misses -system.cpu.l2cache.overall_misses::total 971 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 21475000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 6995000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 28470000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5066000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 5066000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 21475000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 12061000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 33536000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 21475000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 12061000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 33536000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 626 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 201 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 827 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.demand_misses::cpu.inst 628 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 353 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 981 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 628 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 353 # number of overall misses +system.cpu.l2cache.overall_misses::total 981 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 21636000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 7216000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 28852000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5063500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 5063500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 21636000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 12279500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 33915500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 21636000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 12279500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 33915500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 631 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 207 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 838 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 146 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 146 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 626 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 347 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 973 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 626 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 347 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 973 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996805 # miss rate for ReadReq accesses +system.cpu.l2cache.demand_accesses::cpu.inst 631 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 353 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 984 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 631 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 353 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 984 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.995246 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996805 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.995246 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996805 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.995246 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34415.064103 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34800.995025 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34698.630137 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34415.064103 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34757.925072 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34415.064103 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34757.925072 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34452.229299 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34859.903382 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34681.506849 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34452.229299 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34786.118980 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34452.229299 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34786.118980 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 21000 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 4 # number of cycles access was blocked @@ -703,42 +704,42 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs 5250 system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 624 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 201 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 825 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 628 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 207 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 835 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 146 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 146 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 624 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 347 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 971 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 624 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 347 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 971 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 19514500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 6372500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 25887000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4614000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4614000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19514500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10986500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 30501000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19514500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10986500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 30501000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996805 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 628 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 353 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 981 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 628 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 353 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 981 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 19659500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 6570000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 26229500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4611000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4611000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19659500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11181000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 30840500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19659500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11181000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 30840500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.995246 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996805 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.995246 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996805 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.995246 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31273.237179 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31703.980100 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31602.739726 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31273.237179 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31661.383285 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31273.237179 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31661.383285 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31304.936306 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31739.130435 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31582.191781 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31304.936306 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31674.220963 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31304.936306 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31674.220963 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/simout b/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/simout index 71793d455..0e8b3f2e0 100755 --- a/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/simout +++ b/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/simout @@ -1,8 +1,8 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 11 2012 13:08:33 -gem5 started Feb 11 2012 13:55:34 +gem5 compiled Feb 12 2012 17:18:12 +gem5 started Feb 12 2012 18:17:51 gem5 executing on zizzer command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/quick/se/02.insttest/sparc/linux/inorder-timing -re tests/run.py build/SPARC/tests/fast/quick/se/02.insttest/sparc/linux/inorder-timing Global frequency set at 1000000000000 ticks per second @@ -18,4 +18,4 @@ LDTX: Passed LDTW: Passed STTW: Passed Done -Exiting @ tick 25058500 because target called exit() +Exiting @ tick 25007500 because target called exit() diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt index f7efdf641..a378be567 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt +++ b/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000025 # Number of seconds simulated -sim_ticks 25058500 # Number of ticks simulated -final_tick 25058500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 25007500 # Number of ticks simulated +final_tick 25007500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 93467 # Simulator instruction rate (inst/s) -host_op_rate 93457 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 154309649 # Simulator tick rate (ticks/s) -host_mem_usage 211048 # Number of bytes of host memory used -host_seconds 0.16 # Real time elapsed on the host +host_inst_rate 100667 # Simulator instruction rate (inst/s) +host_op_rate 100655 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 165855291 # Simulator tick rate (ticks/s) +host_mem_usage 211052 # Number of bytes of host memory used +host_seconds 0.15 # Real time elapsed on the host sim_insts 15175 # Number of instructions simulated sim_ops 15175 # Number of ops (including micro ops) simulated system.physmem.bytes_read 27904 # Number of bytes read from this memory @@ -17,20 +17,20 @@ system.physmem.bytes_written 0 # Nu system.physmem.num_reads 436 # Number of read requests responded to by this memory system.physmem.num_writes 0 # Number of write requests responded to by this memory system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 1113554283 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 761099028 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total 1113554283 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read 1115825252 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 762651205 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total 1115825252 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 18 # Number of system calls -system.cpu.numCycles 50118 # number of cpu cycles simulated +system.cpu.numCycles 50016 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 21993 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 21887 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 454 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 32493 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 17625 # Number of cycles cpu stages are processed. -system.cpu.activity 35.167006 # Percentage of cycles cpu is active +system.cpu.timesIdled 453 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 32683 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 17333 # Number of cycles cpu stages are processed. +system.cpu.activity 34.654910 # Percentage of cycles cpu is active system.cpu.comLoads 2226 # Number of Load instructions committed system.cpu.comStores 1448 # Number of Store instructions committed system.cpu.comBranches 3359 # Number of Branches instructions committed @@ -42,106 +42,106 @@ system.cpu.committedInsts 15175 # Nu system.cpu.committedOps 15175 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 15175 # Number of Instructions committed (Total) -system.cpu.cpi 3.302669 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 3.295947 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi no_value # CPI: Total SMT-CPI -system.cpu.cpi_total 3.302669 # CPI: Total CPI of All Threads -system.cpu.ipc 0.302785 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 3.295947 # CPI: Total CPI of All Threads +system.cpu.ipc 0.303403 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc no_value # IPC: Total SMT-IPC -system.cpu.ipc_total 0.302785 # IPC: Total IPC of All Threads -system.cpu.branch_predictor.lookups 5166 # Number of BP lookups -system.cpu.branch_predictor.condPredicted 3601 # Number of conditional branches predicted -system.cpu.branch_predictor.condIncorrect 2377 # Number of conditional branches incorrect -system.cpu.branch_predictor.BTBLookups 4346 # Number of BTB lookups -system.cpu.branch_predictor.BTBHits 2912 # Number of BTB hits -system.cpu.branch_predictor.usedRAS 172 # Number of times the RAS was used to get a target. +system.cpu.ipc_total 0.303403 # IPC: Total IPC of All Threads +system.cpu.branch_predictor.lookups 5015 # Number of BP lookups +system.cpu.branch_predictor.condPredicted 3353 # Number of conditional branches predicted +system.cpu.branch_predictor.condIncorrect 2379 # Number of conditional branches incorrect +system.cpu.branch_predictor.BTBLookups 3332 # Number of BTB lookups +system.cpu.branch_predictor.BTBHits 2040 # Number of BTB hits +system.cpu.branch_predictor.usedRAS 174 # Number of times the RAS was used to get a target. system.cpu.branch_predictor.RASInCorrect 5 # Number of incorrect RAS predictions. -system.cpu.branch_predictor.BTBHitPct 67.004142 # BTB Hit Percentage -system.cpu.branch_predictor.predictedTaken 3084 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.predictedNotTaken 2082 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 14334 # Number of Reads from Int. Register File +system.cpu.branch_predictor.BTBHitPct 61.224490 # BTB Hit Percentage +system.cpu.branch_predictor.predictedTaken 2214 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.predictedNotTaken 2801 # Number of Branches Predicted As Not Taken (False). +system.cpu.regfile_manager.intRegFileReads 14401 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 11111 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 25445 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.intRegFileAccesses 25512 # Total Accesses (Read+Write) to the Int. Register File system.cpu.regfile_manager.floatRegFileReads 0 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 0 # Number of Writes to FP Register File system.cpu.regfile_manager.floatRegFileAccesses 0 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 5192 # Number of Registers Read Through Forwarding Logic -system.cpu.agen_unit.agens 3845 # Number of Address Generations -system.cpu.execution_unit.predictedTakenIncorrect 1598 # Number of Branches Incorrectly Predicted As Taken. -system.cpu.execution_unit.predictedNotTakenIncorrect 716 # Number of Branches Incorrectly Predicted As Not Taken). -system.cpu.execution_unit.mispredicted 2314 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.predicted 1045 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.mispredictPct 68.889550 # Percentage of Incorrect Branches Predicts -system.cpu.execution_unit.executions 11051 # Number of Instructions Executed. +system.cpu.regfile_manager.regForwards 4993 # Number of Registers Read Through Forwarding Logic +system.cpu.agen_unit.agens 3952 # Number of Address Generations +system.cpu.execution_unit.predictedTakenIncorrect 1316 # Number of Branches Incorrectly Predicted As Taken. +system.cpu.execution_unit.predictedNotTakenIncorrect 1000 # Number of Branches Incorrectly Predicted As Not Taken). +system.cpu.execution_unit.mispredicted 2316 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.predicted 1043 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.mispredictPct 68.949092 # Percentage of Incorrect Branches Predicts +system.cpu.execution_unit.executions 11084 # Number of Instructions Executed. system.cpu.mult_div_unit.multiplies 0 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed -system.cpu.stage0.idleCycles 36528 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 13590 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 27.116006 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 40773 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 9345 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 18.645995 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 41295 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 8823 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 17.604453 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 47234 # Number of cycles 0 instructions are processed. +system.cpu.stage0.idleCycles 36923 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 13093 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 26.177623 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 40814 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 9202 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 18.398113 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 41191 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 8825 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 17.644354 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 47132 # Number of cycles 0 instructions are processed. system.cpu.stage3.runCycles 2884 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 5.754420 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 40795 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 9323 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 18.602099 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.utilization 5.766155 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 40690 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 9326 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 18.646033 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 165.645515 # Cycle average of tags in use -system.cpu.icache.total_refs 3085 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 165.557258 # Cycle average of tags in use +system.cpu.icache.total_refs 2602 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 299 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 10.317726 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 8.702341 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 165.645515 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.080882 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.080882 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 3085 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 3085 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 3085 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 3085 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 3085 # number of overall hits -system.cpu.icache.overall_hits::total 3085 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 366 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 366 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 366 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 366 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 366 # number of overall misses -system.cpu.icache.overall_misses::total 366 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 20100000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 20100000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 20100000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 20100000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 20100000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 20100000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 3451 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 3451 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 3451 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 3451 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 3451 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 3451 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.106056 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.106056 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.106056 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54918.032787 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 54918.032787 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 54918.032787 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 165.557258 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.080839 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.080839 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 2602 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 2602 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 2602 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 2602 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 2602 # number of overall hits +system.cpu.icache.overall_hits::total 2602 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 368 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 368 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 368 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 368 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 368 # number of overall misses +system.cpu.icache.overall_misses::total 368 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 20203500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 20203500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 20203500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 20203500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 20203500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 20203500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 2970 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 2970 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 2970 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 2970 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 2970 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 2970 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.123906 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.123906 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.123906 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54900.815217 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 54900.815217 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 54900.815217 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 19500 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 65500 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 2 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 19500 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 32750 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 65 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 65 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 65 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 65 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 65 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 65 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 67 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 67 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 67 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 67 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 67 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 67 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 301 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 301 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 301 # number of demand (read+write) MSHR misses @@ -154,22 +154,22 @@ system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15872000 system.cpu.icache.demand_mshr_miss_latency::total 15872000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15872000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 15872000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.087221 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.087221 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.087221 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.101347 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.101347 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.101347 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52730.897010 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52730.897010 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52730.897010 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 97.082868 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 97.041769 # Cycle average of tags in use system.cpu.dcache.total_refs 3316 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 138 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 24.028986 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 97.082868 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.023702 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.023702 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::cpu.data 97.041769 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.023692 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.023692 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 2168 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 2168 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 1142 # number of WriteReq hits @@ -188,14 +188,14 @@ system.cpu.dcache.demand_misses::cpu.data 358 # n system.cpu.dcache.demand_misses::total 358 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 358 # number of overall misses system.cpu.dcache.overall_misses::total 358 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 3282500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 3282500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 16398000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 16398000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 19680500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 19680500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 19680500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 19680500 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 3281500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 3281500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 16397000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 16397000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 19678500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 19678500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 19678500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 19678500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 2226 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 2226 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 1442 # number of WriteReq accesses(hits+misses) @@ -210,10 +210,10 @@ system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.026056 system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.208044 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.097601 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.097601 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56594.827586 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54660 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 54973.463687 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 54973.463687 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56577.586207 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54656.666667 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 54967.877095 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 54967.877095 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 2208000 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -238,34 +238,34 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 138 system.cpu.dcache.demand_mshr_misses::total 138 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 138 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2838000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2838000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2837000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2837000 # number of ReadReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4545000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 4545000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7383000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 7383000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7383000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 7383000 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7382000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 7382000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7382000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 7382000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.023810 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.058946 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.037623 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.037623 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53547.169811 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53528.301887 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53470.588235 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53500 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53500 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53492.753623 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53492.753623 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 196.307447 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 196.205624 # Cycle average of tags in use system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 350 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.005714 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 165.036640 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 31.270807 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.005037 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 164.948941 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 31.256684 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.005034 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.000954 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.005991 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.005988 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits @@ -284,16 +284,16 @@ system.cpu.l2cache.overall_misses::cpu.inst 299 # system.cpu.l2cache.overall_misses::cpu.data 138 # number of overall misses system.cpu.l2cache.overall_misses::total 437 # number of overall misses system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 15533000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2777500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 18310500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2776500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 18309500 # number of ReadReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4442500 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 4442500 # number of ReadExReq miss cycles system.cpu.l2cache.demand_miss_latency::cpu.inst 15533000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 7220000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 22753000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 7219000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 22752000 # number of demand (read+write) miss cycles system.cpu.l2cache.overall_miss_latency::cpu.inst 15533000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 7220000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 22753000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 7219000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 22752000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 301 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 53 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 354 # number of ReadReq accesses(hits+misses) @@ -313,12 +313,12 @@ system.cpu.l2cache.demand_miss_rate::cpu.data 1 system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993355 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 51949.832776 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52405.660377 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52386.792453 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52264.705882 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 51949.832776 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52318.840580 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52311.594203 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 51949.832776 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52318.840580 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52311.594203 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simout b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simout index 2cf0bff32..37bab0cbc 100755 --- a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simout +++ b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simout @@ -1,8 +1,8 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 11 2012 13:08:33 -gem5 started Feb 11 2012 13:55:35 +gem5 compiled Feb 12 2012 17:18:12 +gem5 started Feb 12 2012 18:17:52 gem5 executing on zizzer command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/quick/se/02.insttest/sparc/linux/o3-timing -re tests/run.py build/SPARC/tests/fast/quick/se/02.insttest/sparc/linux/o3-timing Global frequency set at 1000000000000 ticks per second @@ -18,4 +18,4 @@ LDTX: Passed LDTW: Passed STTW: Passed Done -Exiting @ tick 18114000 because target called exit() +Exiting @ tick 19744500 because target called exit() diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt index b63661760..dae08ebeb 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt +++ b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt @@ -1,262 +1,262 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000018 # Number of seconds simulated -sim_ticks 18114000 # Number of ticks simulated -final_tick 18114000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000020 # Number of seconds simulated +sim_ticks 19744500 # Number of ticks simulated +final_tick 19744500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 120891 # Simulator instruction rate (inst/s) -host_op_rate 120873 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 151511225 # Simulator tick rate (ticks/s) -host_mem_usage 211580 # Number of bytes of host memory used -host_seconds 0.12 # Real time elapsed on the host +host_inst_rate 108489 # Simulator instruction rate (inst/s) +host_op_rate 108474 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 148211557 # Simulator tick rate (ticks/s) +host_mem_usage 211612 # Number of bytes of host memory used +host_seconds 0.13 # Real time elapsed on the host sim_insts 14449 # Number of instructions simulated sim_ops 14449 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 30464 # Number of bytes read from this memory -system.physmem.bytes_inst_read 21120 # Number of instructions bytes read from this memory +system.physmem.bytes_read 30976 # Number of bytes read from this memory +system.physmem.bytes_inst_read 21632 # Number of instructions bytes read from this memory system.physmem.bytes_written 0 # Number of bytes written to this memory -system.physmem.num_reads 476 # Number of read requests responded to by this memory +system.physmem.num_reads 484 # Number of read requests responded to by this memory system.physmem.num_writes 0 # Number of write requests responded to by this memory system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 1681793088 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 1165948990 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total 1681793088 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read 1568841956 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 1095596242 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total 1568841956 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 18 # Number of system calls -system.cpu.numCycles 36229 # number of cpu cycles simulated +system.cpu.numCycles 39490 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 5641 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 3757 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 847 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 5015 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 2638 # Number of BTB hits +system.cpu.BPredUnit.lookups 6899 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 4560 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 1119 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 5346 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 2573 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 357 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 168 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 10704 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 25822 # Number of instructions fetch has processed -system.cpu.fetch.Branches 5641 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 2995 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 8176 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 2307 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 6717 # Number of cycles fetch has spent blocked +system.cpu.BPredUnit.usedRAS 464 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 172 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 11886 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 32156 # Number of instructions fetch has processed +system.cpu.fetch.Branches 6899 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 3037 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 9512 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 3178 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 6896 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 641 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 4608 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 368 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 27606 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.935376 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.035144 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.PendingTrapStallCycles 726 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 5506 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 480 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 30987 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.037725 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.210162 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 19430 70.38% 70.38% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 4056 14.69% 85.08% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 538 1.95% 87.02% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 472 1.71% 88.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 725 2.63% 91.36% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 639 2.31% 93.68% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 274 0.99% 94.67% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 241 0.87% 95.54% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1231 4.46% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 21475 69.30% 69.30% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 4729 15.26% 84.56% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 477 1.54% 86.10% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 446 1.44% 87.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 688 2.22% 89.76% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 747 2.41% 92.17% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 238 0.77% 92.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 276 0.89% 93.83% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1911 6.17% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 27606 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.155704 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.712744 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 11125 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 7403 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 7524 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 190 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1364 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 24270 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 1364 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 11622 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 225 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 6687 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 7253 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 455 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 22509 # Number of instructions processed by rename -system.cpu.rename.IQFullEvents 3 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 135 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 20189 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 41765 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 41765 # Number of integer rename lookups +system.cpu.fetch.rateDist::total 30987 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.174702 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.814282 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 12512 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 7643 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 8680 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 189 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1963 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 29984 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 1963 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 13183 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 245 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 6907 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 8245 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 444 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 27285 # Number of instructions processed by rename +system.cpu.rename.IQFullEvents 2 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 121 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 24368 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 50732 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 50732 # Number of integer rename lookups system.cpu.rename.CommittedMaps 13832 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 6357 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 639 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 633 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 2443 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 3114 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1976 # Number of stores inserted to the mem dependence unit. +system.cpu.rename.UndoneMaps 10536 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 705 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 708 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 2853 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 3628 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 2437 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 4 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 19328 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 615 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 18581 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 81 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 4856 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 3975 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 140 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 27606 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.673078 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.254278 # Number of insts issued each cycle +system.cpu.iq.iqInstsAdded 23083 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 663 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 21701 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 105 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 8350 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 5831 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 188 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 30987 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.700326 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.316293 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 19117 69.25% 69.25% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 3446 12.48% 81.73% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 2219 8.04% 89.77% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 1536 5.56% 95.33% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 657 2.38% 97.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 384 1.39% 99.11% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 197 0.71% 99.82% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 41 0.15% 99.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 9 0.03% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 21563 69.59% 69.59% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 3594 11.60% 81.19% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 2382 7.69% 88.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 1729 5.58% 94.45% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 896 2.89% 97.34% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 479 1.55% 98.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 250 0.81% 99.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 75 0.24% 99.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 19 0.06% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 27606 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 30987 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 35 25.18% 25.18% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 25.18% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 25.18% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 25.18% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 25.18% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 25.18% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 25.18% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 25.18% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 25.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 25.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 25.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 25.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 25.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 25.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 25.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 25.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 25.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 25.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 25.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 25.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 25.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 25.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 25.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 25.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 25.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 25.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 25.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 25.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 25.18% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 26 18.71% 43.88% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 78 56.12% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 54 30.17% 30.17% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 30.17% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 30.17% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 30.17% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 30.17% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 30.17% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 30.17% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 30.17% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 30.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 30.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 30.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 30.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 30.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 30.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 30.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 30.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 30.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 30.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 30.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 30.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 30.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 30.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 30.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 30.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 30.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 30.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 30.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 30.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 30.17% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 26 14.53% 44.69% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 99 55.31% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 13779 74.16% 74.16% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 74.16% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 74.16% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 74.16% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 74.16% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 74.16% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 74.16% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 74.16% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 74.16% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 74.16% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 74.16% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 74.16% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 74.16% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 74.16% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 74.16% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 74.16% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 74.16% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 74.16% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 74.16% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 74.16% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 74.16% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 74.16% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 74.16% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 74.16% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 74.16% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 74.16% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 74.16% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 74.16% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 74.16% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2952 15.89% 90.04% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1850 9.96% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 16032 73.88% 73.88% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 73.88% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 73.88% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 73.88% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 73.88% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 73.88% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 73.88% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 73.88% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 73.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 73.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 73.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 73.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 73.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 73.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 73.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 73.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 73.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 73.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 73.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 73.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 73.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 73.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 73.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 73.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 73.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 73.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 73.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 73.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 73.88% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 3432 15.81% 89.69% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 2237 10.31% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 18581 # Type of FU issued -system.cpu.iq.rate 0.512876 # Inst issue rate -system.cpu.iq.fu_busy_cnt 139 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.007481 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 64988 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 24825 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 17429 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 21701 # Type of FU issued +system.cpu.iq.rate 0.549532 # Inst issue rate +system.cpu.iq.fu_busy_cnt 179 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.008248 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 74673 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 32122 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 19916 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 18720 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 21880 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 26 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 888 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1402 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 27 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 528 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 989 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1364 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 96 # Number of cycles IEW is blocking +system.cpu.iew.iewSquashCycles 1963 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 144 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 10 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 21045 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 247 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 3114 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1976 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 615 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispatchedInsts 24909 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 369 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 3628 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 2437 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 663 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 2 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 27 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 371 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 573 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 944 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 17855 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 2862 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 726 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedTakenIncorrect 296 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 956 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1252 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 20511 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 3278 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1190 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1102 # number of nop insts executed -system.cpu.iew.exec_refs 4620 # number of memory reference insts executed -system.cpu.iew.exec_branches 3963 # Number of branches executed -system.cpu.iew.exec_stores 1758 # Number of stores executed -system.cpu.iew.exec_rate 0.492837 # Inst execution rate -system.cpu.iew.wb_sent 17592 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 17429 # cumulative count of insts written-back -system.cpu.iew.wb_producers 8123 # num instructions producing a value -system.cpu.iew.wb_consumers 9726 # num instructions consuming a value +system.cpu.iew.exec_nop 1163 # number of nop insts executed +system.cpu.iew.exec_refs 5392 # number of memory reference insts executed +system.cpu.iew.exec_branches 4300 # Number of branches executed +system.cpu.iew.exec_stores 2114 # Number of stores executed +system.cpu.iew.exec_rate 0.519397 # Inst execution rate +system.cpu.iew.wb_sent 20186 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 19916 # cumulative count of insts written-back +system.cpu.iew.wb_producers 9270 # num instructions producing a value +system.cpu.iew.wb_consumers 11399 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.481079 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.835184 # average fanout of values written-back +system.cpu.iew.wb_rate 0.504330 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.813229 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 15175 # The number of committed instructions system.cpu.commit.commitCommittedOps 15175 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 5794 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 9652 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 475 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 847 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 26259 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.577897 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.280480 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 1119 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 29041 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.522537 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.206609 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 19069 72.62% 72.62% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 3994 15.21% 87.83% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 1208 4.60% 92.43% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 790 3.01% 95.44% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 369 1.41% 96.84% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 322 1.23% 98.07% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 345 1.31% 99.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 57 0.22% 99.60% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 105 0.40% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 21661 74.59% 74.59% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 4067 14.00% 88.59% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 1430 4.92% 93.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 794 2.73% 96.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 339 1.17% 97.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 260 0.90% 98.31% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 321 1.11% 99.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 68 0.23% 99.65% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 101 0.35% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 26259 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 29041 # Number of insts commited each cycle system.cpu.commit.committedInsts 15175 # Number of instructions committed system.cpu.commit.committedOps 15175 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -267,62 +267,62 @@ system.cpu.commit.branches 3359 # Nu system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. system.cpu.commit.int_insts 12186 # Number of committed integer instructions. system.cpu.commit.function_calls 187 # Number of function calls committed. -system.cpu.commit.bw_lim_events 105 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 101 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 46300 # The number of ROB reads -system.cpu.rob.rob_writes 43308 # The number of ROB writes -system.cpu.timesIdled 181 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 8623 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 52944 # The number of ROB reads +system.cpu.rob.rob_writes 51625 # The number of ROB writes +system.cpu.timesIdled 185 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 8503 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 14449 # Number of Instructions Simulated system.cpu.committedOps 14449 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 14449 # Number of Instructions Simulated -system.cpu.cpi 2.507371 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.507371 # CPI: Total CPI of All Threads -system.cpu.ipc 0.398824 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.398824 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 28557 # number of integer regfile reads -system.cpu.int_regfile_writes 15938 # number of integer regfile writes -system.cpu.misc_regfile_reads 6251 # number of misc regfile reads +system.cpu.cpi 2.733061 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.733061 # CPI: Total CPI of All Threads +system.cpu.ipc 0.365890 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.365890 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 32680 # number of integer regfile reads +system.cpu.int_regfile_writes 18187 # number of integer regfile writes +system.cpu.misc_regfile_reads 7045 # number of misc regfile reads system.cpu.misc_regfile_writes 569 # number of misc regfile writes system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 193.216525 # Cycle average of tags in use -system.cpu.icache.total_refs 4151 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 332 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 12.503012 # Average number of references to valid blocks. +system.cpu.icache.tagsinuse 200.774248 # Cycle average of tags in use +system.cpu.icache.total_refs 5020 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 340 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 14.764706 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 193.216525 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.094344 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.094344 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 4151 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 4151 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 4151 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 4151 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 4151 # number of overall hits -system.cpu.icache.overall_hits::total 4151 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 457 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 457 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 457 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 457 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 457 # number of overall misses -system.cpu.icache.overall_misses::total 457 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 15956000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 15956000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 15956000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 15956000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 15956000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 15956000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 4608 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 4608 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 4608 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 4608 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 4608 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 4608 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.099175 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.099175 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.099175 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34914.660832 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 34914.660832 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 34914.660832 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 200.774248 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.098034 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.098034 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 5020 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 5020 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 5020 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 5020 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 5020 # number of overall hits +system.cpu.icache.overall_hits::total 5020 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 486 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 486 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 486 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 486 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 486 # number of overall misses +system.cpu.icache.overall_misses::total 486 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 16725500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 16725500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 16725500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 16725500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 16725500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 16725500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 5506 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 5506 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 5506 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 5506 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 5506 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 5506 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.088267 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.088267 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.088267 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34414.609053 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 34414.609053 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 34414.609053 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -331,84 +331,84 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 125 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 125 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 125 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 125 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 125 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 125 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 332 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 332 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 332 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 332 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 332 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 332 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11653500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 11653500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11653500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 11653500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11653500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 11653500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.072049 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.072049 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.072049 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35100.903614 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35100.903614 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35100.903614 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 146 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 146 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 146 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 146 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 146 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 146 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 340 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 340 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 340 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 340 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 340 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 340 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11937500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 11937500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11937500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 11937500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11937500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 11937500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.061751 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.061751 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.061751 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35110.294118 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35110.294118 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35110.294118 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 102.149831 # Cycle average of tags in use -system.cpu.dcache.total_refs 3712 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 103.476464 # Cycle average of tags in use +system.cpu.dcache.total_refs 4083 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 146 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 25.424658 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 27.965753 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 102.149831 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.024939 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.024939 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 2672 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 2672 # number of ReadReq hits +system.cpu.dcache.occ_blocks::cpu.data 103.476464 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.025263 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.025263 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 3043 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 3043 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 1034 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 1034 # number of WriteReq hits system.cpu.dcache.SwapReq_hits::cpu.data 6 # number of SwapReq hits system.cpu.dcache.SwapReq_hits::total 6 # number of SwapReq hits -system.cpu.dcache.demand_hits::cpu.data 3706 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 3706 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 3706 # number of overall hits -system.cpu.dcache.overall_hits::total 3706 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 114 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 114 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 4077 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 4077 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 4077 # number of overall hits +system.cpu.dcache.overall_hits::total 4077 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 118 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 118 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 408 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 408 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 522 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 522 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 522 # number of overall misses -system.cpu.dcache.overall_misses::total 522 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 3994500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 3994500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 14649500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 14649500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 18644000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 18644000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 18644000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 18644000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 2786 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 2786 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 526 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 526 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 526 # number of overall misses +system.cpu.dcache.overall_misses::total 526 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 4092500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 4092500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 14593500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 14593500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 18686000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 18686000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 18686000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 18686000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 3161 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 3161 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 1442 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 1442 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SwapReq_accesses::cpu.data 6 # number of SwapReq accesses(hits+misses) system.cpu.dcache.SwapReq_accesses::total 6 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 4228 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 4228 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 4228 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 4228 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040919 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 4603 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 4603 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 4603 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 4603 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.037330 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.282940 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.123463 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.123463 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 35039.473684 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35905.637255 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 35716.475096 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 35716.475096 # average overall miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.114273 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.114273 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34682.203390 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35768.382353 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 35524.714829 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 35524.714829 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -417,14 +417,14 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 51 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 51 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 55 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 55 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 325 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 325 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 376 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 376 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 376 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 376 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 380 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 380 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 380 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 380 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 63 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 63 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 83 # number of WriteReq MSHR misses @@ -433,87 +433,87 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 146 system.cpu.dcache.demand_mshr_misses::total 146 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 146 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 146 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2241500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2241500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2985000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2985000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5226500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 5226500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5226500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 5226500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.022613 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2243500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2243500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2979500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2979500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5223000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 5223000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5223000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 5223000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.019930 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.057559 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.034532 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.034532 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 35579.365079 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35963.855422 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 35797.945205 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 35797.945205 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.031718 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.031718 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 35611.111111 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35897.590361 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 35773.972603 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 35773.972603 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 228.374360 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 236.259194 # Cycle average of tags in use system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 393 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.005089 # Average number of references to valid blocks. +system.cpu.l2cache.sampled_refs 401 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.004988 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 192.484909 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 35.889452 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.005874 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.001095 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.006969 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 200.029408 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 36.229787 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.006104 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.001106 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.007210 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::total 2 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.inst 2 # number of overall hits system.cpu.l2cache.overall_hits::total 2 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 330 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.inst 338 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.data 63 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 393 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 401 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 83 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 83 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 330 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 338 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.data 146 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 476 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 330 # number of overall misses +system.cpu.l2cache.demand_misses::total 484 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 338 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 146 # number of overall misses -system.cpu.l2cache.overall_misses::total 476 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 11308000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2167000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 13475000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2872000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 2872000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 11308000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 5039000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 16347000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 11308000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 5039000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 16347000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 332 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.overall_misses::total 484 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 11582500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2169000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 13751500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2869000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 2869000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 11582500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 5038000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 16620500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 11582500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 5038000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 16620500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 340 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 63 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 395 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 403 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 83 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 83 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 332 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 340 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 146 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 478 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 332 # number of overall (read+write) accesses +system.cpu.l2cache.demand_accesses::total 486 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 340 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 146 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 478 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.993976 # miss rate for ReadReq accesses +system.cpu.l2cache.overall_accesses::total 486 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.994118 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.993976 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.994118 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993976 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.994118 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34266.666667 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34396.825397 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34602.409639 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34266.666667 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34513.698630 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34266.666667 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34513.698630 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34267.751479 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34428.571429 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34566.265060 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34267.751479 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34506.849315 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34267.751479 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34506.849315 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -522,42 +522,42 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 330 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 338 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 63 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 393 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 401 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 83 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 83 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 330 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 338 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 146 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 476 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 330 # number of overall MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 484 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 338 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 146 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 476 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10246500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.overall_mshr_misses::total 484 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10497000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1968500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 12215000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2608500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2608500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10246500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4577000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 14823500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10246500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4577000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 14823500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993976 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 12465500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2607500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2607500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10497000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4576000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 15073000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10497000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4576000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 15073000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.994118 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.993976 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.994118 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993976 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.994118 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31050 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31056.213018 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31246.031746 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31427.710843 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31050 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31349.315068 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31050 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31349.315068 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31415.662651 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31056.213018 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31342.465753 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31056.213018 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31342.465753 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout index 2bb2951e2..84d6c3ee2 100755 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout @@ -1,8 +1,8 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 11 2012 13:08:33 -gem5 started Feb 11 2012 13:55:55 +gem5 compiled Feb 12 2012 17:18:12 +gem5 started Feb 12 2012 18:18:13 gem5 executing on zizzer command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp -re tests/run.py build/SPARC/tests/fast/quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp Global frequency set at 1000000000000 ticks per second @@ -10,10 +10,10 @@ info: Entering event queue @ 0. Starting simulation... Init done [Iteration 1, Thread 2] Got lock [Iteration 1, Thread 2] Critical section done, previously next=0, now next=2 -[Iteration 1, Thread 1] Got lock -[Iteration 1, Thread 1] Critical section done, previously next=2, now next=1 [Iteration 1, Thread 3] Got lock -[Iteration 1, Thread 3] Critical section done, previously next=1, now next=3 +[Iteration 1, Thread 3] Critical section done, previously next=2, now next=3 +[Iteration 1, Thread 1] Got lock +[Iteration 1, Thread 1] Critical section done, previously next=3, now next=1 Iteration 1 completed [Iteration 2, Thread 1] Got lock [Iteration 2, Thread 1] Critical section done, previously next=0, now next=1 @@ -22,12 +22,12 @@ Iteration 1 completed [Iteration 2, Thread 2] Got lock [Iteration 2, Thread 2] Critical section done, previously next=3, now next=2 Iteration 2 completed -[Iteration 3, Thread 2] Got lock -[Iteration 3, Thread 2] Critical section done, previously next=0, now next=2 -[Iteration 3, Thread 3] Got lock -[Iteration 3, Thread 3] Critical section done, previously next=2, now next=3 [Iteration 3, Thread 1] Got lock -[Iteration 3, Thread 1] Critical section done, previously next=3, now next=1 +[Iteration 3, Thread 1] Critical section done, previously next=0, now next=1 +[Iteration 3, Thread 3] Got lock +[Iteration 3, Thread 3] Critical section done, previously next=1, now next=3 +[Iteration 3, Thread 2] Got lock +[Iteration 3, Thread 2] Critical section done, previously next=3, now next=2 Iteration 3 completed [Iteration 4, Thread 1] Got lock [Iteration 4, Thread 1] Critical section done, previously next=0, now next=1 @@ -36,19 +36,19 @@ Iteration 3 completed [Iteration 4, Thread 3] Got lock [Iteration 4, Thread 3] Critical section done, previously next=2, now next=3 Iteration 4 completed +[Iteration 5, Thread 2] Got lock +[Iteration 5, Thread 2] Critical section done, previously next=0, now next=2 [Iteration 5, Thread 1] Got lock -[Iteration 5, Thread 1] Critical section done, previously next=0, now next=1 +[Iteration 5, Thread 1] Critical section done, previously next=2, now next=1 [Iteration 5, Thread 3] Got lock [Iteration 5, Thread 3] Critical section done, previously next=1, now next=3 -[Iteration 5, Thread 2] Got lock -[Iteration 5, Thread 2] Critical section done, previously next=3, now next=2 Iteration 5 completed +[Iteration 6, Thread 3] Got lock +[Iteration 6, Thread 3] Critical section done, previously next=0, now next=3 [Iteration 6, Thread 1] Got lock -[Iteration 6, Thread 1] Critical section done, previously next=0, now next=1 +[Iteration 6, Thread 1] Critical section done, previously next=3, now next=1 [Iteration 6, Thread 2] Got lock [Iteration 6, Thread 2] Critical section done, previously next=1, now next=2 -[Iteration 6, Thread 3] Got lock -[Iteration 6, Thread 3] Critical section done, previously next=2, now next=3 Iteration 6 completed [Iteration 7, Thread 1] Got lock [Iteration 7, Thread 1] Critical section done, previously next=0, now next=1 @@ -57,26 +57,26 @@ Iteration 6 completed [Iteration 7, Thread 3] Got lock [Iteration 7, Thread 3] Critical section done, previously next=2, now next=3 Iteration 7 completed -[Iteration 8, Thread 3] Got lock -[Iteration 8, Thread 3] Critical section done, previously next=0, now next=3 [Iteration 8, Thread 2] Got lock -[Iteration 8, Thread 2] Critical section done, previously next=3, now next=2 +[Iteration 8, Thread 2] Critical section done, previously next=0, now next=2 [Iteration 8, Thread 1] Got lock [Iteration 8, Thread 1] Critical section done, previously next=2, now next=1 +[Iteration 8, Thread 3] Got lock +[Iteration 8, Thread 3] Critical section done, previously next=1, now next=3 Iteration 8 completed [Iteration 9, Thread 3] Got lock [Iteration 9, Thread 3] Critical section done, previously next=0, now next=3 -[Iteration 9, Thread 1] Got lock -[Iteration 9, Thread 1] Critical section done, previously next=3, now next=1 [Iteration 9, Thread 2] Got lock -[Iteration 9, Thread 2] Critical section done, previously next=1, now next=2 +[Iteration 9, Thread 2] Critical section done, previously next=3, now next=2 +[Iteration 9, Thread 1] Got lock +[Iteration 9, Thread 1] Critical section done, previously next=2, now next=1 Iteration 9 completed -[Iteration 10, Thread 2] Got lock -[Iteration 10, Thread 2] Critical section done, previously next=0, now next=2 -[Iteration 10, Thread 3] Got lock -[Iteration 10, Thread 3] Critical section done, previously next=2, now next=3 [Iteration 10, Thread 1] Got lock -[Iteration 10, Thread 1] Critical section done, previously next=3, now next=1 +[Iteration 10, Thread 1] Critical section done, previously next=0, now next=1 +[Iteration 10, Thread 3] Got lock +[Iteration 10, Thread 3] Critical section done, previously next=1, now next=3 +[Iteration 10, Thread 2] Got lock +[Iteration 10, Thread 2] Critical section done, previously next=3, now next=2 Iteration 10 completed PASSED :-) -Exiting @ tick 104317500 because target called exit() +Exiting @ tick 111402500 because target called exit() diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt index befe09ef8..f6ac2f26c 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt @@ -1,329 +1,329 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000104 # Number of seconds simulated -sim_ticks 104317500 # Number of ticks simulated -final_tick 104317500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000111 # Number of seconds simulated +sim_ticks 111402500 # Number of ticks simulated +final_tick 111402500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 190796 # Simulator instruction rate (inst/s) -host_op_rate 190795 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 19532213 # Simulator tick rate (ticks/s) -host_mem_usage 225896 # Number of bytes of host memory used -host_seconds 5.34 # Real time elapsed on the host -sim_insts 1018993 # Number of instructions simulated -sim_ops 1018993 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 41984 # Number of bytes read from this memory -system.physmem.bytes_inst_read 28224 # Number of instructions bytes read from this memory +host_inst_rate 189621 # Simulator instruction rate (inst/s) +host_op_rate 189621 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 19396106 # Simulator tick rate (ticks/s) +host_mem_usage 226052 # Number of bytes of host memory used +host_seconds 5.74 # Real time elapsed on the host +sim_insts 1089093 # Number of instructions simulated +sim_ops 1089093 # Number of ops (including micro ops) simulated +system.physmem.bytes_read 43072 # Number of bytes read from this memory +system.physmem.bytes_inst_read 29312 # Number of instructions bytes read from this memory system.physmem.bytes_written 0 # Number of bytes written to this memory -system.physmem.num_reads 656 # Number of read requests responded to by this memory +system.physmem.num_reads 673 # Number of read requests responded to by this memory system.physmem.num_writes 0 # Number of write requests responded to by this memory system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 402463633 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 270558631 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total 402463633 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read 386634052 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 263117973 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total 386634052 # Total bandwidth to/from this memory (bytes/s) system.cpu0.workload.num_syscalls 89 # Number of system calls -system.cpu0.numCycles 208636 # number of cpu cycles simulated +system.cpu0.numCycles 222806 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.BPredUnit.lookups 80640 # Number of BP lookups -system.cpu0.BPredUnit.condPredicted 78657 # Number of conditional branches predicted -system.cpu0.BPredUnit.condIncorrect 1043 # Number of conditional branches incorrect -system.cpu0.BPredUnit.BTBLookups 79781 # Number of BTB lookups -system.cpu0.BPredUnit.BTBHits 77332 # Number of BTB hits +system.cpu0.BPredUnit.lookups 87253 # Number of BP lookups +system.cpu0.BPredUnit.condPredicted 84917 # Number of conditional branches predicted +system.cpu0.BPredUnit.condIncorrect 1303 # Number of conditional branches incorrect +system.cpu0.BPredUnit.BTBLookups 84794 # Number of BTB lookups +system.cpu0.BPredUnit.BTBHits 82358 # Number of BTB hits system.cpu0.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.BPredUnit.usedRAS 408 # Number of times the RAS was used to get a target. -system.cpu0.BPredUnit.RASInCorrect 132 # Number of incorrect RAS predictions. -system.cpu0.fetch.icacheStallCycles 16565 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 478922 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 80640 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 77740 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 158137 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 3216 # Number of cycles fetch has spent squashing -system.cpu0.fetch.BlockedCycles 12889 # Number of cycles fetch has spent blocked +system.cpu0.BPredUnit.usedRAS 518 # Number of times the RAS was used to get a target. +system.cpu0.BPredUnit.RASInCorrect 136 # Number of incorrect RAS predictions. +system.cpu0.fetch.icacheStallCycles 17579 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 517995 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 87253 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 82876 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 170053 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 3992 # Number of cycles fetch has spent squashing +system.cpu0.fetch.BlockedCycles 13261 # Number of cycles fetch has spent blocked system.cpu0.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 1227 # Number of stall cycles due to pending traps -system.cpu0.fetch.CacheLines 5515 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 447 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.rateDist::samples 190846 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 2.509468 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.192643 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.PendingTrapStallCycles 1318 # Number of stall cycles due to pending traps +system.cpu0.fetch.CacheLines 6218 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 521 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.rateDist::samples 204756 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 2.529816 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.210666 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 32709 17.14% 17.14% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 78517 41.14% 58.28% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 548 0.29% 58.57% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 994 0.52% 59.09% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 666 0.35% 59.44% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 74596 39.09% 98.52% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 801 0.42% 98.94% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 243 0.13% 99.07% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 1772 0.93% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 34703 16.95% 16.95% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 84234 41.14% 58.09% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 594 0.29% 58.38% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 959 0.47% 58.85% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 591 0.29% 59.13% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 80169 39.15% 98.29% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 594 0.29% 98.58% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 373 0.18% 98.76% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 2539 1.24% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 190846 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.386510 # Number of branch fetches per cycle -system.cpu0.fetch.rate 2.295491 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 16943 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 14345 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 157232 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 303 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 2023 # Number of cycles decode is squashing -system.cpu0.decode.DecodedInsts 476750 # Number of instructions handled by decode -system.cpu0.rename.SquashCycles 2023 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 17547 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 1397 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 12300 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 156956 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 623 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 474177 # Number of instructions processed by rename +system.cpu0.fetch.rateDist::total 204756 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.391610 # Number of branch fetches per cycle +system.cpu0.fetch.rate 2.324870 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 18003 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 14874 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 169024 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 315 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 2540 # Number of cycles decode is squashing +system.cpu0.decode.DecodedInsts 515001 # Number of instructions handled by decode +system.cpu0.rename.SquashCycles 2540 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 18709 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 1371 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 12822 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 168665 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 649 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 511590 # Number of instructions processed by rename system.cpu0.rename.IQFullEvents 5 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LSQFullEvents 220 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.RenamedOperands 323986 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 945682 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 945682 # Number of integer rename lookups -system.cpu0.rename.CommittedMaps 313636 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 10350 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 803 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 824 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 3595 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 152097 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 76745 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 74317 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 74189 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 396725 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 846 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 395036 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 98 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 8285 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 7136 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 287 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 190846 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 2.069920 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.087146 # Number of insts issued each cycle +system.cpu0.rename.LSQFullEvents 235 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.RenamedOperands 349678 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 1020456 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 1020456 # Number of integer rename lookups +system.cpu0.rename.CommittedMaps 335896 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 13782 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 911 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 939 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 4054 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 163918 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 82754 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 79985 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 79744 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 427655 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 948 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 424795 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 156 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 11264 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 10234 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 389 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 204756 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 2.074640 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.085274 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 31787 16.66% 16.66% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 5152 2.70% 19.36% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 75953 39.80% 59.15% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 75299 39.46% 98.61% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 1582 0.83% 99.44% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 772 0.40% 99.84% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 222 0.12% 99.96% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 71 0.04% 100.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 8 0.00% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 33869 16.54% 16.54% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 5212 2.55% 19.09% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 81806 39.95% 59.04% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 81161 39.64% 98.68% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 1586 0.77% 99.45% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 710 0.35% 99.80% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 306 0.15% 99.95% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 90 0.04% 99.99% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 16 0.01% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 190846 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 204756 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 35 14.96% 14.96% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 0 0.00% 14.96% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 14.96% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 14.96% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 14.96% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 14.96% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 14.96% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 14.96% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 14.96% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 14.96% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 14.96% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 14.96% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 14.96% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 14.96% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 14.96% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 14.96% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 14.96% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 14.96% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 14.96% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 14.96% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 14.96% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 14.96% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 14.96% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 14.96% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 14.96% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 14.96% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 14.96% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 14.96% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 14.96% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 80 34.19% 49.15% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 119 50.85% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 53 21.81% 21.81% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 0 0.00% 21.81% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 21.81% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 21.81% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 21.81% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 21.81% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 21.81% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 21.81% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 21.81% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 21.81% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 21.81% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 21.81% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 21.81% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 21.81% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 21.81% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 21.81% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 21.81% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 21.81% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 21.81% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 21.81% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 21.81% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 21.81% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 21.81% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 21.81% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 21.81% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 21.81% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 21.81% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 21.81% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 21.81% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 78 32.10% 53.91% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 112 46.09% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 166893 42.25% 42.25% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 0 0.00% 42.25% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 42.25% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 42.25% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 42.25% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 42.25% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 42.25% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 42.25% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 42.25% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 42.25% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 42.25% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 42.25% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 42.25% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 42.25% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 42.25% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 42.25% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 42.25% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 42.25% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 42.25% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 42.25% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.25% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.25% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.25% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.25% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.25% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 42.25% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 42.25% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 42.25% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.25% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 151805 38.43% 80.68% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 76338 19.32% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 179222 42.19% 42.19% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 0 0.00% 42.19% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 42.19% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 42.19% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 42.19% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 42.19% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 42.19% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 42.19% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 42.19% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 42.19% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 42.19% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 42.19% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 42.19% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 42.19% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 42.19% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 42.19% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 42.19% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 42.19% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 42.19% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 42.19% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.19% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.19% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.19% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.19% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.19% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 42.19% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 42.19% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 42.19% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.19% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 163383 38.46% 80.65% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 82190 19.35% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 395036 # Type of FU issued -system.cpu0.iq.rate 1.893422 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 234 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.000592 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 981250 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 405901 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 393576 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.FU_type_0::total 424795 # Type of FU issued +system.cpu0.iq.rate 1.906569 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 243 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.000572 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 1054745 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 439928 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 422836 # Number of integer instruction queue wakeup accesses system.cpu0.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu0.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu0.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 395270 # Number of integer alu accesses +system.cpu0.iq.int_alu_accesses 425038 # Number of integer alu accesses system.cpu0.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 73924 # Number of loads that had data forwarded from stores +system.cpu0.iew.lsq.thread0.forwLoads 79492 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 1695 # Number of loads squashed +system.cpu0.iew.lsq.thread0.squashedLoads 2386 # Number of loads squashed system.cpu0.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 45 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 1038 # Number of stores squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 61 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 1482 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu0.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 18 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.cacheBlocked 16 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 2023 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 1027 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 29 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 472373 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 357 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 152097 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 76745 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 745 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 27 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewSquashCycles 2540 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 996 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 37 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 509141 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 346 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 163918 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 82754 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 837 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 38 # Number of times the IQ has become full, causing a stall system.cpu0.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 45 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 467 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 734 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 1201 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 394155 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 151500 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 881 # Number of squashed instructions skipped in execute +system.cpu0.iew.memOrderViolationEvents 61 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 382 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 1141 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 1523 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 423658 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 163081 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 1137 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 74802 # number of nop insts executed -system.cpu0.iew.exec_refs 227728 # number of memory reference insts executed -system.cpu0.iew.exec_branches 78432 # Number of branches executed -system.cpu0.iew.exec_stores 76228 # Number of stores executed -system.cpu0.iew.exec_rate 1.889199 # Inst execution rate -system.cpu0.iew.wb_sent 393836 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 393576 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 233255 # num instructions producing a value -system.cpu0.iew.wb_consumers 235364 # num instructions consuming a value +system.cpu0.iew.exec_nop 80538 # number of nop insts executed +system.cpu0.iew.exec_refs 245123 # number of memory reference insts executed +system.cpu0.iew.exec_branches 84187 # Number of branches executed +system.cpu0.iew.exec_stores 82042 # Number of stores executed +system.cpu0.iew.exec_rate 1.901466 # Inst execution rate +system.cpu0.iew.wb_sent 423189 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 422836 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 250585 # num instructions producing a value +system.cpu0.iew.wb_consumers 253105 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 1.886424 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.991039 # average fanout of values written-back +system.cpu0.iew.wb_rate 1.897777 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.990044 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitCommittedInsts 462799 # The number of committed instructions -system.cpu0.commit.commitCommittedOps 462799 # The number of committed instructions -system.cpu0.commit.commitSquashedInsts 9535 # The number of squashed insts skipped by commit +system.cpu0.commit.commitCommittedInsts 496189 # The number of committed instructions +system.cpu0.commit.commitCommittedOps 496189 # The number of committed instructions +system.cpu0.commit.commitSquashedInsts 12929 # The number of squashed insts skipped by commit system.cpu0.commit.commitNonSpecStalls 559 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 1043 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 188840 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 2.450747 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 2.135046 # Number of insts commited each cycle +system.cpu0.commit.branchMispredicts 1303 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 202233 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 2.453551 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 2.134267 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 32333 17.12% 17.12% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 78258 41.44% 58.56% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 2188 1.16% 59.72% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 719 0.38% 60.10% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 659 0.35% 60.45% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 73614 38.98% 99.43% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 485 0.26% 99.69% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 280 0.15% 99.84% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 304 0.16% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 34442 17.03% 17.03% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 83893 41.48% 58.51% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 2396 1.18% 59.70% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 690 0.34% 60.04% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 548 0.27% 60.31% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 79225 39.18% 99.49% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 480 0.24% 99.72% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 235 0.12% 99.84% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 324 0.16% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 188840 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 462799 # Number of instructions committed -system.cpu0.commit.committedOps 462799 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 202233 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 496189 # Number of instructions committed +system.cpu0.commit.committedOps 496189 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 226109 # Number of memory references committed -system.cpu0.commit.loads 150402 # Number of loads committed +system.cpu0.commit.refs 242804 # Number of memory references committed +system.cpu0.commit.loads 161532 # Number of loads committed system.cpu0.commit.membars 84 # Number of memory barriers committed -system.cpu0.commit.branches 77595 # Number of branches committed +system.cpu0.commit.branches 83160 # Number of branches committed system.cpu0.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 311966 # Number of committed integer instructions. +system.cpu0.commit.int_insts 334226 # Number of committed integer instructions. system.cpu0.commit.function_calls 223 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 304 # number cycles where commit BW limit reached +system.cpu0.commit.bw_lim_events 324 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 659709 # The number of ROB reads -system.cpu0.rob.rob_writes 946703 # The number of ROB writes +system.cpu0.rob.rob_reads 709866 # The number of ROB reads +system.cpu0.rob.rob_writes 1020791 # The number of ROB writes system.cpu0.timesIdled 320 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 17790 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.committedInsts 388389 # Number of Instructions Simulated -system.cpu0.committedOps 388389 # Number of Ops (including micro ops) Simulated -system.cpu0.committedInsts_total 388389 # Number of Instructions Simulated -system.cpu0.cpi 0.537183 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 0.537183 # CPI: Total CPI of All Threads -system.cpu0.ipc 1.861563 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 1.861563 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 705230 # number of integer regfile reads -system.cpu0.int_regfile_writes 317935 # number of integer regfile writes +system.cpu0.idleCycles 18050 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.committedInsts 416214 # Number of Instructions Simulated +system.cpu0.committedOps 416214 # Number of Ops (including micro ops) Simulated +system.cpu0.committedInsts_total 416214 # Number of Instructions Simulated +system.cpu0.cpi 0.535316 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 0.535316 # CPI: Total CPI of All Threads +system.cpu0.ipc 1.868056 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 1.868056 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 757980 # number of integer regfile reads +system.cpu0.int_regfile_writes 341432 # number of integer regfile writes system.cpu0.fp_regfile_reads 192 # number of floating regfile reads -system.cpu0.misc_regfile_reads 229503 # number of misc regfile reads +system.cpu0.misc_regfile_reads 246952 # number of misc regfile reads system.cpu0.misc_regfile_writes 564 # number of misc regfile writes -system.cpu0.icache.replacements 294 # number of replacements -system.cpu0.icache.tagsinuse 244.353680 # Cycle average of tags in use -system.cpu0.icache.total_refs 4810 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 581 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 8.278830 # Average number of references to valid blocks. +system.cpu0.icache.replacements 300 # number of replacements +system.cpu0.icache.tagsinuse 248.673809 # Cycle average of tags in use +system.cpu0.icache.total_refs 5459 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 593 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 9.205734 # Average number of references to valid blocks. system.cpu0.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 244.353680 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.477253 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.477253 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 4810 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 4810 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 4810 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 4810 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 4810 # number of overall hits -system.cpu0.icache.overall_hits::total 4810 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 705 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 705 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 705 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 705 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 705 # number of overall misses -system.cpu0.icache.overall_misses::total 705 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 27622000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 27622000 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 27622000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 27622000 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 27622000 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 27622000 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 5515 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 5515 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 5515 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 5515 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 5515 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 5515 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.127833 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.127833 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.127833 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 39180.141844 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 39180.141844 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 39180.141844 # average overall miss latency +system.cpu0.icache.occ_blocks::cpu0.inst 248.673809 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.485691 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.485691 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 5459 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 5459 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 5459 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 5459 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 5459 # number of overall hits +system.cpu0.icache.overall_hits::total 5459 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 759 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 759 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 759 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 759 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 759 # number of overall misses +system.cpu0.icache.overall_misses::total 759 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 29159500 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 29159500 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 29159500 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 29159500 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 29159500 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 29159500 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 6218 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 6218 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 6218 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 6218 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 6218 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 6218 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.122065 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.122065 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.122065 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 38418.313570 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 38418.313570 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 38418.313570 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 15500 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 1 # number of cycles access was blocked @@ -332,444 +332,444 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs 15500 system.cpu0.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 123 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 123 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 123 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 123 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 123 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 123 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 582 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 582 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 582 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 582 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 582 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 582 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 21369000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 21369000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 21369000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 21369000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 21369000 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 21369000 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.105530 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.105530 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.105530 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 36716.494845 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 36716.494845 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 36716.494845 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 165 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 165 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 165 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 165 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 165 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 165 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 594 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 594 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 594 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 594 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 594 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 594 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 21891000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 21891000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 21891000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 21891000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 21891000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 21891000 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.095529 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.095529 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.095529 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 36853.535354 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 36853.535354 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 36853.535354 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 9 # number of replacements -system.cpu0.dcache.tagsinuse 140.432794 # Cycle average of tags in use -system.cpu0.dcache.total_refs 97328 # Total number of references to valid blocks. +system.cpu0.dcache.replacements 8 # number of replacements +system.cpu0.dcache.tagsinuse 141.285775 # Cycle average of tags in use +system.cpu0.dcache.total_refs 100453 # Total number of references to valid blocks. system.cpu0.dcache.sampled_refs 174 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 559.356322 # Average number of references to valid blocks. +system.cpu0.dcache.avg_refs 577.316092 # Average number of references to valid blocks. system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 140.432794 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.274283 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.274283 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 77005 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 77005 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 75125 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 75125 # number of WriteReq hits -system.cpu0.dcache.SwapReq_hits::cpu0.data 23 # number of SwapReq hits -system.cpu0.dcache.SwapReq_hits::total 23 # number of SwapReq hits -system.cpu0.dcache.demand_hits::cpu0.data 152130 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 152130 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 152130 # number of overall hits -system.cpu0.dcache.overall_hits::total 152130 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 517 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 517 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 540 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 540 # number of WriteReq misses -system.cpu0.dcache.SwapReq_misses::cpu0.data 19 # number of SwapReq misses -system.cpu0.dcache.SwapReq_misses::total 19 # number of SwapReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1057 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1057 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1057 # number of overall misses -system.cpu0.dcache.overall_misses::total 1057 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 14734500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 14734500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 24692984 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 24692984 # number of WriteReq miss cycles -system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 371000 # number of SwapReq miss cycles -system.cpu0.dcache.SwapReq_miss_latency::total 371000 # number of SwapReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 39427484 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 39427484 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 39427484 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 39427484 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 77522 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 77522 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 75665 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 75665 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.occ_blocks::cpu0.data 141.285775 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.275949 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::total 0.275949 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 83026 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 83026 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 80684 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 80684 # number of WriteReq hits +system.cpu0.dcache.SwapReq_hits::cpu0.data 22 # number of SwapReq hits +system.cpu0.dcache.SwapReq_hits::total 22 # number of SwapReq hits +system.cpu0.dcache.demand_hits::cpu0.data 163710 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 163710 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 163710 # number of overall hits +system.cpu0.dcache.overall_hits::total 163710 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 495 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 495 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 546 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 546 # number of WriteReq misses +system.cpu0.dcache.SwapReq_misses::cpu0.data 20 # number of SwapReq misses +system.cpu0.dcache.SwapReq_misses::total 20 # number of SwapReq misses +system.cpu0.dcache.demand_misses::cpu0.data 1041 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1041 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1041 # number of overall misses +system.cpu0.dcache.overall_misses::total 1041 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 13976000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 13976000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 24361986 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 24361986 # number of WriteReq miss cycles +system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 380500 # number of SwapReq miss cycles +system.cpu0.dcache.SwapReq_miss_latency::total 380500 # number of SwapReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 38337986 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 38337986 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 38337986 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 38337986 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 83521 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 83521 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 81230 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 81230 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses) system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 153187 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 153187 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 153187 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 153187 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.006669 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007137 # miss rate for WriteReq accesses -system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.452381 # miss rate for SwapReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.006900 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.006900 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 28500 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 45727.748148 # average WriteReq miss latency -system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 19526.315789 # average SwapReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 37301.309366 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 37301.309366 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 180500 # number of cycles access was blocked +system.cpu0.dcache.demand_accesses::cpu0.data 164751 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 164751 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 164751 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 164751 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.005927 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.006722 # miss rate for WriteReq accesses +system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.476190 # miss rate for SwapReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.006319 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.006319 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 28234.343434 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 44619.021978 # average WriteReq miss latency +system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 19025 # average SwapReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 36828.036503 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 36828.036503 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 194000 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 21 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 19 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 8595.238095 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 10210.526316 # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed system.cpu0.dcache.writebacks::writebacks 6 # number of writebacks system.cpu0.dcache.writebacks::total 6 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 327 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 327 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 368 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 368 # number of WriteReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 695 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 695 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 695 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 695 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 190 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 190 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 172 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 172 # number of WriteReq MSHR misses -system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data 19 # number of SwapReq MSHR misses -system.cpu0.dcache.SwapReq_mshr_misses::total 19 # number of SwapReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 362 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 362 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 362 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 362 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 5255000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5255000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6251500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6251500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 314000 # number of SwapReq MSHR miss cycles -system.cpu0.dcache.SwapReq_mshr_miss_latency::total 314000 # number of SwapReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 11506500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 11506500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 11506500 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 11506500 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.002451 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.002273 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.452381 # mshr miss rate for SwapReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.002363 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.002363 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 27657.894737 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 36345.930233 # average WriteReq mshr miss latency -system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 16526.315789 # average SwapReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 31785.911602 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 31785.911602 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 313 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 313 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 370 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 370 # number of WriteReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 683 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 683 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 683 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 683 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 182 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 182 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 176 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 176 # number of WriteReq MSHR misses +system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data 20 # number of SwapReq MSHR misses +system.cpu0.dcache.SwapReq_mshr_misses::total 20 # number of SwapReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 358 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 358 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 358 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 358 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4954500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4954500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6250000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6250000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 320500 # number of SwapReq MSHR miss cycles +system.cpu0.dcache.SwapReq_mshr_miss_latency::total 320500 # number of SwapReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 11204500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 11204500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 11204500 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 11204500 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.002179 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.002167 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.476190 # mshr miss rate for SwapReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.002173 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.002173 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 27222.527473 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 35511.363636 # average WriteReq mshr miss latency +system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 16025 # average SwapReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 31297.486034 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 31297.486034 # average overall mshr miss latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.numCycles 174305 # number of cpu cycles simulated +system.cpu1.numCycles 187393 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.BPredUnit.lookups 52112 # Number of BP lookups -system.cpu1.BPredUnit.condPredicted 49475 # Number of conditional branches predicted -system.cpu1.BPredUnit.condIncorrect 1085 # Number of conditional branches incorrect -system.cpu1.BPredUnit.BTBLookups 48064 # Number of BTB lookups -system.cpu1.BPredUnit.BTBHits 46080 # Number of BTB hits +system.cpu1.BPredUnit.lookups 57495 # Number of BP lookups +system.cpu1.BPredUnit.condPredicted 54509 # Number of conditional branches predicted +system.cpu1.BPredUnit.condIncorrect 1432 # Number of conditional branches incorrect +system.cpu1.BPredUnit.BTBLookups 50945 # Number of BTB lookups +system.cpu1.BPredUnit.BTBHits 49902 # Number of BTB hits system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.BPredUnit.usedRAS 697 # Number of times the RAS was used to get a target. +system.cpu1.BPredUnit.usedRAS 759 # Number of times the RAS was used to get a target. system.cpu1.BPredUnit.RASInCorrect 232 # Number of incorrect RAS predictions. -system.cpu1.fetch.icacheStallCycles 26834 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 291745 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 52112 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 46777 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 102740 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 3160 # Number of cycles fetch has spent squashing -system.cpu1.fetch.BlockedCycles 32953 # Number of cycles fetch has spent blocked +system.cpu1.fetch.icacheStallCycles 28506 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 323137 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 57495 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 50661 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 112599 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 4204 # Number of cycles fetch has spent squashing +system.cpu1.fetch.BlockedCycles 33253 # Number of cycles fetch has spent blocked system.cpu1.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.NoActiveThreadStallCycles 6397 # Number of stall cycles due to no active thread to fetch from -system.cpu1.fetch.PendingTrapStallCycles 670 # Number of stall cycles due to pending traps -system.cpu1.fetch.CacheLines 18341 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 181 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.rateDist::samples 171598 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 1.700166 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.136223 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.NoActiveThreadStallCycles 6513 # Number of stall cycles due to no active thread to fetch from +system.cpu1.fetch.PendingTrapStallCycles 1058 # Number of stall cycles due to pending traps +system.cpu1.fetch.CacheLines 19809 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 287 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.rateDist::samples 184628 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 1.750206 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.168540 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 68858 40.13% 40.13% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 52177 30.41% 70.53% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 5705 3.32% 73.86% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 3354 1.95% 75.81% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 589 0.34% 76.16% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 36153 21.07% 97.22% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 1352 0.79% 98.01% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 417 0.24% 98.26% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 2993 1.74% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 72029 39.01% 39.01% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 57027 30.89% 69.90% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 6026 3.26% 73.16% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 3313 1.79% 74.96% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 681 0.37% 75.33% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 39928 21.63% 96.95% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 1176 0.64% 97.59% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 885 0.48% 98.07% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 3563 1.93% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 171598 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.298970 # Number of branch fetches per cycle -system.cpu1.fetch.rate 1.673762 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 31662 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 29517 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 97194 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 4829 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 1999 # Number of cycles decode is squashing -system.cpu1.decode.DecodedInsts 288983 # Number of instructions handled by decode -system.cpu1.rename.SquashCycles 1999 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 32299 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 14957 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 13738 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 92834 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 9374 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 287085 # Number of instructions processed by rename +system.cpu1.fetch.rateDist::total 184628 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.306815 # Number of branch fetches per cycle +system.cpu1.fetch.rate 1.724381 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 34082 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 29678 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 106549 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 5112 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 2694 # Number of cycles decode is squashing +system.cpu1.decode.DecodedInsts 318863 # Number of instructions handled by decode +system.cpu1.rename.SquashCycles 2694 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 34823 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 15756 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 13064 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 101771 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 10007 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 316589 # Number of instructions processed by rename system.cpu1.rename.IQFullEvents 26 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 60 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.RenamedOperands 200836 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 551958 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 551958 # Number of integer rename lookups -system.cpu1.rename.CommittedMaps 191192 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 9644 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 1080 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 1209 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 11997 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 82183 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 38955 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 39306 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 34408 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 238857 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 6064 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 241490 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 3 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 8361 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 7490 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 637 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 171598 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 1.407301 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.310079 # Number of insts issued each cycle +system.cpu1.rename.LSQFullEvents 63 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.RenamedOperands 221379 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 610170 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 610170 # Number of integer rename lookups +system.cpu1.rename.CommittedMaps 206274 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 15105 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 1171 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 1292 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 12551 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 90746 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 43396 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 43483 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 38230 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 262560 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 6300 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 264126 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 64 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 12570 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 11522 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 654 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 184628 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 1.430585 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.313833 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 65840 38.37% 38.37% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 21732 12.66% 51.03% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 38892 22.66% 73.70% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 40381 23.53% 97.23% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 3339 1.95% 99.18% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 1157 0.67% 99.85% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 163 0.09% 99.95% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 40 0.02% 99.97% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 54 0.03% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 69552 37.67% 37.67% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 22561 12.22% 49.89% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 43412 23.51% 73.40% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 44019 23.84% 97.25% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 3358 1.82% 99.07% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 1272 0.69% 99.75% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 343 0.19% 99.94% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 54 0.03% 99.97% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 57 0.03% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 171598 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 184628 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 12 4.55% 4.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 0 0.00% 4.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 4.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 4.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 4.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 4.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 4.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 4.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 4.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 4.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 4.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 4.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 4.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 4.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 4.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 4.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 4.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 4.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 4.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 4.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 4.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 4.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 4.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 4.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 4.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 4.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 4.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 4.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 62 23.48% 28.03% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 190 71.97% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 21 6.65% 6.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 0 0.00% 6.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 6.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 6.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 6.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 6.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 6.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 6.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 6.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 6.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 6.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 6.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 6.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 6.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 6.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 6.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 6.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 6.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 6.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 6.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 6.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 6.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 6.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 6.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 6.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 6.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 6.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 6.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 85 26.90% 33.54% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 210 66.46% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 116592 48.28% 48.28% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 0 0.00% 48.28% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 48.28% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 48.28% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 48.28% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 48.28% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 48.28% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 48.28% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 48.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 48.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 48.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 48.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 48.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 48.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 48.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 48.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 48.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 48.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 48.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 48.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 48.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 48.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 48.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 48.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.28% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 86338 35.75% 84.03% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 38560 15.97% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 126488 47.89% 47.89% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 0 0.00% 47.89% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 47.89% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 47.89% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 47.89% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 47.89% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 47.89% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 47.89% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 47.89% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 47.89% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 47.89% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 47.89% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 47.89% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 47.89% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 47.89% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 47.89% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 47.89% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 47.89% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 47.89% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 47.89% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.89% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.89% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.89% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.89% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.89% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 47.89% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 47.89% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.89% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.89% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 94921 35.94% 83.83% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 42717 16.17% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 241490 # Type of FU issued -system.cpu1.iq.rate 1.385445 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 264 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.001093 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 654845 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 253312 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 240391 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.FU_type_0::total 264126 # Type of FU issued +system.cpu1.iq.rate 1.409476 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 316 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.001196 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 713260 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 281477 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 262161 # Number of integer instruction queue wakeup accesses system.cpu1.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu1.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu1.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 241754 # Number of integer alu accesses +system.cpu1.iq.int_alu_accesses 264442 # Number of integer alu accesses system.cpu1.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 34276 # Number of loads that had data forwarded from stores +system.cpu1.iew.lsq.thread0.forwLoads 37998 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 1784 # Number of loads squashed +system.cpu1.iew.lsq.thread0.squashedLoads 2692 # Number of loads squashed system.cpu1.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 30 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 861 # Number of stores squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 47 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 1591 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu1.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu1.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 1999 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 1765 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 48 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 285210 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 302 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 82183 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 38955 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 1043 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewSquashCycles 2694 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 1681 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 49 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 313238 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 386 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 90746 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 43396 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 1094 # Number of dispatched non-speculative instructions system.cpu1.iew.iewIQFullEvents 45 # Number of times the IQ has become full, causing a stall system.cpu1.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 30 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 599 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 655 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 1254 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 240751 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 81429 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 739 # Number of squashed instructions skipped in execute +system.cpu1.iew.memOrderViolationEvents 47 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 484 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 1109 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 1593 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 262830 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 89694 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 1296 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 40289 # number of nop insts executed -system.cpu1.iew.exec_refs 119949 # number of memory reference insts executed -system.cpu1.iew.exec_branches 49362 # Number of branches executed -system.cpu1.iew.exec_stores 38520 # Number of stores executed -system.cpu1.iew.exec_rate 1.381205 # Inst execution rate -system.cpu1.iew.wb_sent 240558 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 240391 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 136702 # num instructions producing a value -system.cpu1.iew.wb_consumers 141193 # num instructions consuming a value +system.cpu1.iew.exec_nop 44378 # number of nop insts executed +system.cpu1.iew.exec_refs 132319 # number of memory reference insts executed +system.cpu1.iew.exec_branches 53738 # Number of branches executed +system.cpu1.iew.exec_stores 42625 # Number of stores executed +system.cpu1.iew.exec_rate 1.402560 # Inst execution rate +system.cpu1.iew.wb_sent 262446 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 262161 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 149144 # num instructions producing a value +system.cpu1.iew.wb_consumers 154061 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 1.379140 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.968192 # average fanout of values written-back +system.cpu1.iew.wb_rate 1.398990 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.968084 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitCommittedInsts 275667 # The number of committed instructions -system.cpu1.commit.commitCommittedOps 275667 # The number of committed instructions -system.cpu1.commit.commitSquashedInsts 9533 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 5427 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 1085 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 163203 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 1.689105 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 2.043033 # Number of insts commited each cycle +system.cpu1.commit.commitCommittedInsts 298843 # The number of committed instructions +system.cpu1.commit.commitCommittedOps 298843 # The number of committed instructions +system.cpu1.commit.commitSquashedInsts 14389 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 5646 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 1432 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 175422 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 1.703566 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 2.044466 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 64641 39.61% 39.61% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 47587 29.16% 68.77% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 5957 3.65% 72.42% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 6309 3.87% 76.28% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 1571 0.96% 77.24% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 34602 21.20% 98.45% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 646 0.40% 98.84% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 1051 0.64% 99.49% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 839 0.51% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 68710 39.17% 39.17% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 51651 29.44% 68.61% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 6180 3.52% 72.14% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 6549 3.73% 75.87% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 1541 0.88% 76.75% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 38344 21.86% 98.61% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 640 0.36% 98.97% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 995 0.57% 99.54% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 812 0.46% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 163203 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 275667 # Number of instructions committed -system.cpu1.commit.committedOps 275667 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 175422 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 298843 # Number of instructions committed +system.cpu1.commit.committedOps 298843 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 118493 # Number of memory references committed -system.cpu1.commit.loads 80399 # Number of loads committed -system.cpu1.commit.membars 4716 # Number of memory barriers committed -system.cpu1.commit.branches 48773 # Number of branches committed +system.cpu1.commit.refs 129859 # Number of memory references committed +system.cpu1.commit.loads 88054 # Number of loads committed +system.cpu1.commit.membars 4938 # Number of memory barriers committed +system.cpu1.commit.branches 52708 # Number of branches committed system.cpu1.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 189391 # Number of committed integer instructions. +system.cpu1.commit.int_insts 204694 # Number of committed integer instructions. system.cpu1.commit.function_calls 322 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 839 # number cycles where commit BW limit reached +system.cpu1.commit.bw_lim_events 812 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 446977 # The number of ROB reads -system.cpu1.rob.rob_writes 572400 # The number of ROB writes -system.cpu1.timesIdled 225 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 2707 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 34329 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 231385 # Number of Instructions Simulated -system.cpu1.committedOps 231385 # Number of Ops (including micro ops) Simulated -system.cpu1.committedInsts_total 231385 # Number of Instructions Simulated -system.cpu1.cpi 0.753312 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 0.753312 # CPI: Total CPI of All Threads -system.cpu1.ipc 1.327472 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 1.327472 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 418065 # number of integer regfile reads -system.cpu1.int_regfile_writes 194844 # number of integer regfile writes +system.cpu1.rob.rob_reads 487255 # The number of ROB reads +system.cpu1.rob.rob_writes 629168 # The number of ROB writes +system.cpu1.timesIdled 232 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 2765 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 35411 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 250401 # Number of Instructions Simulated +system.cpu1.committedOps 250401 # Number of Ops (including micro ops) Simulated +system.cpu1.committedInsts_total 250401 # Number of Instructions Simulated +system.cpu1.cpi 0.748372 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 0.748372 # CPI: Total CPI of All Threads +system.cpu1.ipc 1.336235 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 1.336235 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 456552 # number of integer regfile reads +system.cpu1.int_regfile_writes 212248 # number of integer regfile writes system.cpu1.fp_regfile_writes 64 # number of floating regfile writes -system.cpu1.misc_regfile_reads 121500 # number of misc regfile reads +system.cpu1.misc_regfile_reads 133945 # number of misc regfile reads system.cpu1.misc_regfile_writes 646 # number of misc regfile writes -system.cpu1.icache.replacements 317 # number of replacements -system.cpu1.icache.tagsinuse 84.541118 # Cycle average of tags in use -system.cpu1.icache.total_refs 17870 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 427 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 41.850117 # Average number of references to valid blocks. +system.cpu1.icache.replacements 322 # number of replacements +system.cpu1.icache.tagsinuse 82.769076 # Cycle average of tags in use +system.cpu1.icache.total_refs 19304 # Total number of references to valid blocks. +system.cpu1.icache.sampled_refs 435 # Sample count of references to valid blocks. +system.cpu1.icache.avg_refs 44.377011 # Average number of references to valid blocks. system.cpu1.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 84.541118 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.165119 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.165119 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 17870 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 17870 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 17870 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 17870 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 17870 # number of overall hits -system.cpu1.icache.overall_hits::total 17870 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 471 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 471 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 471 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 471 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 471 # number of overall misses -system.cpu1.icache.overall_misses::total 471 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7203000 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 7203000 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 7203000 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 7203000 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 7203000 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 7203000 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 18341 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 18341 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 18341 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 18341 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 18341 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 18341 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.025680 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.025680 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.025680 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 15292.993631 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 15292.993631 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 15292.993631 # average overall miss latency +system.cpu1.icache.occ_blocks::cpu1.inst 82.769076 # Average occupied blocks per requestor +system.cpu1.icache.occ_percent::cpu1.inst 0.161658 # Average percentage of cache occupancy +system.cpu1.icache.occ_percent::total 0.161658 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 19304 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 19304 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 19304 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 19304 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 19304 # number of overall hits +system.cpu1.icache.overall_hits::total 19304 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 505 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 505 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 505 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 505 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 505 # number of overall misses +system.cpu1.icache.overall_misses::total 505 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7500500 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 7500500 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 7500500 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 7500500 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 7500500 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 7500500 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 19809 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 19809 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 19809 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 19809 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 19809 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 19809 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.025493 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.025493 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.025493 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14852.475248 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14852.475248 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14852.475248 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -778,90 +778,90 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs no_value system.cpu1.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 44 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 44 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 44 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 44 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 44 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 44 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 427 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 427 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 427 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 427 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 427 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 427 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5374000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 5374000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5374000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 5374000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5374000 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 5374000 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.023281 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.023281 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.023281 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12585.480094 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12585.480094 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12585.480094 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 70 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 70 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 70 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 70 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 70 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 70 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 435 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 435 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 435 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 435 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 435 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 435 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5474500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 5474500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5474500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 5474500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5474500 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 5474500 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.021960 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.021960 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.021960 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12585.057471 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12585.057471 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12585.057471 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dcache.replacements 2 # number of replacements -system.cpu1.dcache.tagsinuse 24.401572 # Cycle average of tags in use -system.cpu1.dcache.total_refs 44082 # Total number of references to valid blocks. +system.cpu1.dcache.tagsinuse 24.070551 # Cycle average of tags in use +system.cpu1.dcache.total_refs 48111 # Total number of references to valid blocks. system.cpu1.dcache.sampled_refs 30 # Sample count of references to valid blocks. -system.cpu1.dcache.avg_refs 1469.400000 # Average number of references to valid blocks. +system.cpu1.dcache.avg_refs 1603.700000 # Average number of references to valid blocks. system.cpu1.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::cpu1.data 24.401572 # Average occupied blocks per requestor -system.cpu1.dcache.occ_percent::cpu1.data 0.047659 # Average percentage of cache occupancy -system.cpu1.dcache.occ_percent::total 0.047659 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::cpu1.data 46660 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 46660 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 37905 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 37905 # number of WriteReq hits -system.cpu1.dcache.SwapReq_hits::cpu1.data 13 # number of SwapReq hits -system.cpu1.dcache.SwapReq_hits::total 13 # number of SwapReq hits -system.cpu1.dcache.demand_hits::cpu1.data 84565 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 84565 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 84565 # number of overall hits -system.cpu1.dcache.overall_hits::total 84565 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 478 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 478 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 124 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 124 # number of WriteReq misses -system.cpu1.dcache.SwapReq_misses::cpu1.data 52 # number of SwapReq misses -system.cpu1.dcache.SwapReq_misses::total 52 # number of SwapReq misses -system.cpu1.dcache.demand_misses::cpu1.data 602 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 602 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 602 # number of overall misses -system.cpu1.dcache.overall_misses::total 602 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 10261500 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 10261500 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2943000 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 2943000 # number of WriteReq miss cycles -system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 1149500 # number of SwapReq miss cycles -system.cpu1.dcache.SwapReq_miss_latency::total 1149500 # number of SwapReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 13204500 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 13204500 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 13204500 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 13204500 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 47138 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 47138 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 38029 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 38029 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SwapReq_accesses::cpu1.data 65 # number of SwapReq accesses(hits+misses) -system.cpu1.dcache.SwapReq_accesses::total 65 # number of SwapReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 85167 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 85167 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 85167 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 85167 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.010140 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.003261 # miss rate for WriteReq accesses -system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.800000 # miss rate for SwapReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.007068 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.007068 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 21467.573222 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 23733.870968 # average WriteReq miss latency -system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 22105.769231 # average SwapReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 21934.385382 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 21934.385382 # average overall miss latency +system.cpu1.dcache.occ_blocks::cpu1.data 24.070551 # Average occupied blocks per requestor +system.cpu1.dcache.occ_percent::cpu1.data 0.047013 # Average percentage of cache occupancy +system.cpu1.dcache.occ_percent::total 0.047013 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::cpu1.data 51204 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 51204 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 41589 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 41589 # number of WriteReq hits +system.cpu1.dcache.SwapReq_hits::cpu1.data 12 # number of SwapReq hits +system.cpu1.dcache.SwapReq_hits::total 12 # number of SwapReq hits +system.cpu1.dcache.demand_hits::cpu1.data 92793 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 92793 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 92793 # number of overall hits +system.cpu1.dcache.overall_hits::total 92793 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 475 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 475 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 154 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 154 # number of WriteReq misses +system.cpu1.dcache.SwapReq_misses::cpu1.data 50 # number of SwapReq misses +system.cpu1.dcache.SwapReq_misses::total 50 # number of SwapReq misses +system.cpu1.dcache.demand_misses::cpu1.data 629 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 629 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 629 # number of overall misses +system.cpu1.dcache.overall_misses::total 629 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 9635500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 9635500 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2967500 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 2967500 # number of WriteReq miss cycles +system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 1038500 # number of SwapReq miss cycles +system.cpu1.dcache.SwapReq_miss_latency::total 1038500 # number of SwapReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 12603000 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 12603000 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 12603000 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 12603000 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 51679 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 51679 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 41743 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 41743 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SwapReq_accesses::cpu1.data 62 # number of SwapReq accesses(hits+misses) +system.cpu1.dcache.SwapReq_accesses::total 62 # number of SwapReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 93422 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 93422 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 93422 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 93422 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.009191 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.003689 # miss rate for WriteReq accesses +system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.806452 # miss rate for SwapReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.006733 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.006733 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 20285.263158 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 19269.480519 # average WriteReq miss latency +system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 20770 # average SwapReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20036.565978 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20036.565978 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -872,350 +872,350 @@ system.cpu1.dcache.fast_writes 0 # nu system.cpu1.dcache.cache_copies 0 # number of cache copies performed system.cpu1.dcache.writebacks::writebacks 1 # number of writebacks system.cpu1.dcache.writebacks::total 1 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 323 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 323 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 18 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 18 # number of WriteReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 341 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 341 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 341 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 341 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 155 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 155 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 106 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 106 # number of WriteReq MSHR misses -system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 52 # number of SwapReq MSHR misses -system.cpu1.dcache.SwapReq_mshr_misses::total 52 # number of SwapReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 261 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 261 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 261 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 261 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2079000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2079000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1617000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1617000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 993500 # number of SwapReq MSHR miss cycles -system.cpu1.dcache.SwapReq_mshr_miss_latency::total 993500 # number of SwapReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3696000 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 3696000 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 3696000 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 3696000 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.003288 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.002787 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.800000 # mshr miss rate for SwapReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.003065 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.003065 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13412.903226 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 15254.716981 # average WriteReq mshr miss latency -system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 19105.769231 # average SwapReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 14160.919540 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 14160.919540 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 319 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 319 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 45 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 45 # number of WriteReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 364 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 364 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 364 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 364 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 156 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 156 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 109 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 109 # number of WriteReq MSHR misses +system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 50 # number of SwapReq MSHR misses +system.cpu1.dcache.SwapReq_mshr_misses::total 50 # number of SwapReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 265 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 265 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 265 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 265 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2052000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2052000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1523500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1523500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 888500 # number of SwapReq MSHR miss cycles +system.cpu1.dcache.SwapReq_mshr_miss_latency::total 888500 # number of SwapReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3575500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 3575500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 3575500 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 3575500 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.003019 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.002611 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.806452 # mshr miss rate for SwapReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.002837 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.002837 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13153.846154 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 13977.064220 # average WriteReq mshr miss latency +system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 17770 # average SwapReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 13492.452830 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 13492.452830 # average overall mshr miss latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.numCycles 174018 # number of cpu cycles simulated +system.cpu2.numCycles 187102 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.BPredUnit.lookups 49365 # Number of BP lookups -system.cpu2.BPredUnit.condPredicted 46733 # Number of conditional branches predicted -system.cpu2.BPredUnit.condIncorrect 1149 # Number of conditional branches incorrect -system.cpu2.BPredUnit.BTBLookups 45641 # Number of BTB lookups -system.cpu2.BPredUnit.BTBHits 43566 # Number of BTB hits +system.cpu2.BPredUnit.lookups 52366 # Number of BP lookups +system.cpu2.BPredUnit.condPredicted 49346 # Number of conditional branches predicted +system.cpu2.BPredUnit.condIncorrect 1501 # Number of conditional branches incorrect +system.cpu2.BPredUnit.BTBLookups 45884 # Number of BTB lookups +system.cpu2.BPredUnit.BTBHits 44697 # Number of BTB hits system.cpu2.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.BPredUnit.usedRAS 657 # Number of times the RAS was used to get a target. -system.cpu2.BPredUnit.RASInCorrect 232 # Number of incorrect RAS predictions. -system.cpu2.fetch.icacheStallCycles 27807 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 273933 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 49365 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 44223 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 97490 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 3286 # Number of cycles fetch has spent squashing -system.cpu2.fetch.BlockedCycles 34440 # Number of cycles fetch has spent blocked +system.cpu2.BPredUnit.usedRAS 764 # Number of times the RAS was used to get a target. +system.cpu2.BPredUnit.RASInCorrect 230 # Number of incorrect RAS predictions. +system.cpu2.fetch.icacheStallCycles 30829 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 289891 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 52366 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 45461 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 103159 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 4491 # Number of cycles fetch has spent squashing +system.cpu2.fetch.BlockedCycles 37226 # Number of cycles fetch has spent blocked system.cpu2.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu2.fetch.NoActiveThreadStallCycles 6393 # Number of stall cycles due to no active thread to fetch from -system.cpu2.fetch.PendingTrapStallCycles 776 # Number of stall cycles due to pending traps -system.cpu2.fetch.CacheLines 19059 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 204 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.rateDist::samples 168970 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.621193 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 2.105353 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.NoActiveThreadStallCycles 6501 # Number of stall cycles due to no active thread to fetch from +system.cpu2.fetch.PendingTrapStallCycles 1096 # Number of stall cycles due to pending traps +system.cpu2.fetch.CacheLines 21870 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 331 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.rateDist::samples 181728 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.595192 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 2.120038 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 71480 42.30% 42.30% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 49528 29.31% 71.62% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 6067 3.59% 75.21% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 3620 2.14% 77.35% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 727 0.43% 77.78% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 32913 19.48% 97.26% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 1356 0.80% 98.06% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 430 0.25% 98.31% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 2849 1.69% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 78569 43.23% 43.23% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 52779 29.04% 72.28% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 6971 3.84% 76.11% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 3518 1.94% 78.05% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 702 0.39% 78.44% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 33444 18.40% 96.84% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 1229 0.68% 97.51% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 914 0.50% 98.02% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 3602 1.98% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 168970 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.283678 # Number of branch fetches per cycle -system.cpu2.fetch.rate 1.574165 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 32851 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 30938 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 91697 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 5032 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 2059 # Number of cycles decode is squashing -system.cpu2.decode.DecodedInsts 271122 # Number of instructions handled by decode -system.cpu2.rename.SquashCycles 2059 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 33552 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 15710 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 14412 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 87163 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 9681 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 268918 # Number of instructions processed by rename -system.cpu2.rename.IQFullEvents 31 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LSQFullEvents 44 # Number of times rename has blocked due to LSQ full -system.cpu2.rename.RenamedOperands 188425 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 514118 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 514118 # Number of integer rename lookups -system.cpu2.rename.CommittedMaps 178130 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 10295 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 1067 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 1200 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 12339 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 75827 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 35627 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 36245 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 31070 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 223191 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 6330 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 225872 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 3 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 8710 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 8050 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 644 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 168970 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 1.336758 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 1.306399 # Number of insts issued each cycle +system.cpu2.fetch.rateDist::total 181728 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.279879 # Number of branch fetches per cycle +system.cpu2.fetch.rate 1.549374 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 37176 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 32970 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 96308 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 5861 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 2912 # Number of cycles decode is squashing +system.cpu2.decode.DecodedInsts 285362 # Number of instructions handled by decode +system.cpu2.rename.SquashCycles 2912 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 37970 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 18336 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 13742 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 90714 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 11553 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 283108 # Number of instructions processed by rename +system.cpu2.rename.IQFullEvents 27 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LSQFullEvents 56 # Number of times rename has blocked due to LSQ full +system.cpu2.rename.RenamedOperands 197373 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 538438 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 538438 # Number of integer rename lookups +system.cpu2.rename.CommittedMaps 181356 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 16017 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 1193 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 1308 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 14181 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 79045 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 36977 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 38155 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 31746 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 233020 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 7475 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 234915 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 73 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 13691 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 12875 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 913 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 181728 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 1.292674 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 1.310296 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 68735 40.68% 40.68% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 22585 13.37% 54.05% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 35942 21.27% 75.32% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 37104 21.96% 97.28% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 3355 1.99% 99.26% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 981 0.58% 99.84% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 168 0.10% 99.94% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 42 0.02% 99.97% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 58 0.03% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 76657 42.18% 42.18% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 25237 13.89% 56.07% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 37132 20.43% 76.50% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 37732 20.76% 97.27% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 3274 1.80% 99.07% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 1229 0.68% 99.74% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 353 0.19% 99.94% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 53 0.03% 99.97% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 61 0.03% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 168970 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 181728 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 19 7.04% 7.04% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 0 0.00% 7.04% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 0 0.00% 7.04% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 7.04% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 7.04% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 7.04% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 7.04% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 7.04% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 7.04% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 7.04% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 7.04% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 7.04% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 7.04% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 7.04% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 7.04% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 7.04% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 7.04% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 7.04% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 7.04% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 7.04% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 7.04% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 7.04% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 7.04% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 7.04% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 7.04% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 7.04% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 7.04% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 7.04% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 7.04% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 61 22.59% 29.63% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 190 70.37% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 21 6.69% 6.69% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 0 0.00% 6.69% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 0 0.00% 6.69% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 6.69% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 6.69% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 6.69% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 6.69% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 6.69% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 6.69% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 6.69% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 6.69% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 6.69% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 6.69% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 6.69% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 6.69% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 6.69% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 6.69% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 6.69% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 6.69% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 6.69% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 6.69% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 6.69% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 6.69% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 6.69% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 6.69% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 6.69% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 6.69% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.69% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 6.69% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 83 26.43% 33.12% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 210 66.88% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 110495 48.92% 48.92% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 0 0.00% 48.92% # Type of FU issued -system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 48.92% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 48.92% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 48.92% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 48.92% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 48.92% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 48.92% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 48.92% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 48.92% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 48.92% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 48.92% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 48.92% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 48.92% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 48.92% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 48.92% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 48.92% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 48.92% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.92% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 48.92% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 48.92% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.92% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 48.92% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 48.92% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 48.92% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.92% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 48.92% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.92% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.92% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 80157 35.49% 84.41% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 35220 15.59% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 114779 48.86% 48.86% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 0 0.00% 48.86% # Type of FU issued +system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 48.86% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 48.86% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 48.86% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 48.86% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 48.86% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 48.86% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 48.86% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 48.86% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 48.86% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 48.86% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 48.86% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 48.86% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 48.86% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 48.86% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 48.86% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 48.86% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.86% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 48.86% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 48.86% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.86% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 48.86% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 48.86% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 48.86% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.86% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 48.86% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.86% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.86% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 83862 35.70% 84.56% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 36274 15.44% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 225872 # Type of FU issued -system.cpu2.iq.rate 1.297981 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 270 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.001195 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 620987 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 238263 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 224632 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.FU_type_0::total 234915 # Type of FU issued +system.cpu2.iq.rate 1.255545 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 314 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.001337 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 651945 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 254231 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 232815 # Number of integer instruction queue wakeup accesses system.cpu2.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu2.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu2.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 226142 # Number of integer alu accesses +system.cpu2.iq.int_alu_accesses 235229 # Number of integer alu accesses system.cpu2.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 30940 # Number of loads that had data forwarded from stores +system.cpu2.iew.lsq.thread0.forwLoads 31545 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 1843 # Number of loads squashed -system.cpu2.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 32 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 852 # Number of stores squashed +system.cpu2.iew.lsq.thread0.squashedLoads 3013 # Number of loads squashed +system.cpu2.iew.lsq.thread0.ignoredResponses 8 # Number of memory responses ignored because the instruction is squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 45 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 1611 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu2.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu2.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 2059 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 1941 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 63 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 266786 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 354 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 75827 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 35627 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 1018 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 57 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewSquashCycles 2912 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 1924 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 66 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 279572 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 369 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 79045 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 36977 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 1114 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 62 # Number of times the IQ has become full, causing a stall system.cpu2.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 32 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 683 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 611 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 1294 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 225039 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 74986 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 833 # Number of squashed instructions skipped in execute +system.cpu2.iew.memOrderViolationEvents 45 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 517 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 1138 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 1655 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 233532 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 77718 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 1383 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed -system.cpu2.iew.exec_nop 37265 # number of nop insts executed -system.cpu2.iew.exec_refs 110171 # number of memory reference insts executed -system.cpu2.iew.exec_branches 46373 # Number of branches executed -system.cpu2.iew.exec_stores 35185 # Number of stores executed -system.cpu2.iew.exec_rate 1.293194 # Inst execution rate -system.cpu2.iew.wb_sent 224805 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 224632 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 127007 # num instructions producing a value -system.cpu2.iew.wb_consumers 131418 # num instructions consuming a value +system.cpu2.iew.exec_nop 39077 # number of nop insts executed +system.cpu2.iew.exec_refs 113896 # number of memory reference insts executed +system.cpu2.iew.exec_branches 48223 # Number of branches executed +system.cpu2.iew.exec_stores 36178 # Number of stores executed +system.cpu2.iew.exec_rate 1.248153 # Inst execution rate +system.cpu2.iew.wb_sent 233124 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 232815 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 130712 # num instructions producing a value +system.cpu2.iew.wb_consumers 135609 # num instructions consuming a value system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_rate 1.290855 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.966435 # average fanout of values written-back +system.cpu2.iew.wb_rate 1.244321 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.963889 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.commit.commitCommittedInsts 256708 # The number of committed instructions -system.cpu2.commit.commitCommittedOps 256708 # The number of committed instructions -system.cpu2.commit.commitSquashedInsts 10074 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 5686 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 1149 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 160519 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 1.599237 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 2.012927 # Number of insts commited each cycle +system.cpu2.commit.commitCommittedInsts 263733 # The number of committed instructions +system.cpu2.commit.commitCommittedOps 263733 # The number of committed instructions +system.cpu2.commit.commitSquashedInsts 15844 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 6562 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 1501 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 172316 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 1.530520 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 1.983884 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 67924 42.32% 42.32% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 44668 27.83% 70.14% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 6005 3.74% 73.88% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 6542 4.08% 77.96% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 1606 1.00% 78.96% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 31385 19.55% 98.51% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 504 0.31% 98.83% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 1049 0.65% 99.48% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 836 0.52% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 76563 44.43% 44.43% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 46194 26.81% 71.24% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 6230 3.62% 74.85% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 7466 4.33% 79.19% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 1536 0.89% 80.08% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 32043 18.60% 98.67% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 480 0.28% 98.95% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 990 0.57% 99.53% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 814 0.47% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 160519 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 256708 # Number of instructions committed -system.cpu2.commit.committedOps 256708 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 172316 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 263733 # Number of instructions committed +system.cpu2.commit.committedOps 263733 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 108759 # Number of memory references committed -system.cpu2.commit.loads 73984 # Number of loads committed -system.cpu2.commit.membars 4966 # Number of memory barriers committed -system.cpu2.commit.branches 45704 # Number of branches committed +system.cpu2.commit.refs 111398 # Number of memory references committed +system.cpu2.commit.loads 76032 # Number of loads committed +system.cpu2.commit.membars 5840 # Number of memory barriers committed +system.cpu2.commit.branches 47167 # Number of branches committed system.cpu2.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 176579 # Number of committed integer instructions. +system.cpu2.commit.int_insts 180680 # Number of committed integer instructions. system.cpu2.commit.function_calls 322 # Number of function calls committed. -system.cpu2.commit.bw_lim_events 836 # number cycles where commit BW limit reached +system.cpu2.commit.bw_lim_events 814 # number cycles where commit BW limit reached system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu2.rob.rob_reads 425878 # The number of ROB reads -system.cpu2.rob.rob_writes 535627 # The number of ROB writes -system.cpu2.timesIdled 232 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 5048 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 34616 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 215254 # Number of Instructions Simulated -system.cpu2.committedOps 215254 # Number of Ops (including micro ops) Simulated -system.cpu2.committedInsts_total 215254 # Number of Instructions Simulated -system.cpu2.cpi 0.808431 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 0.808431 # CPI: Total CPI of All Threads -system.cpu2.ipc 1.236964 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 1.236964 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 389052 # number of integer regfile reads -system.cpu2.int_regfile_writes 181919 # number of integer regfile writes +system.cpu2.rob.rob_reads 450492 # The number of ROB reads +system.cpu2.rob.rob_writes 562082 # The number of ROB writes +system.cpu2.timesIdled 233 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 5374 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 35702 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 219944 # Number of Instructions Simulated +system.cpu2.committedOps 219944 # Number of Ops (including micro ops) Simulated +system.cpu2.committedInsts_total 219944 # Number of Instructions Simulated +system.cpu2.cpi 0.850680 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 0.850680 # CPI: Total CPI of All Threads +system.cpu2.ipc 1.175530 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 1.175530 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 401453 # number of integer regfile reads +system.cpu2.int_regfile_writes 187612 # number of integer regfile writes system.cpu2.fp_regfile_writes 64 # number of floating regfile writes -system.cpu2.misc_regfile_reads 111746 # number of misc regfile reads +system.cpu2.misc_regfile_reads 115545 # number of misc regfile reads system.cpu2.misc_regfile_writes 646 # number of misc regfile writes -system.cpu2.icache.replacements 321 # number of replacements -system.cpu2.icache.tagsinuse 85.227474 # Cycle average of tags in use -system.cpu2.icache.total_refs 18578 # Total number of references to valid blocks. -system.cpu2.icache.sampled_refs 427 # Sample count of references to valid blocks. -system.cpu2.icache.avg_refs 43.508197 # Average number of references to valid blocks. +system.cpu2.icache.replacements 325 # number of replacements +system.cpu2.icache.tagsinuse 91.851117 # Cycle average of tags in use +system.cpu2.icache.total_refs 21358 # Total number of references to valid blocks. +system.cpu2.icache.sampled_refs 440 # Sample count of references to valid blocks. +system.cpu2.icache.avg_refs 48.540909 # Average number of references to valid blocks. system.cpu2.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.icache.occ_blocks::cpu2.inst 85.227474 # Average occupied blocks per requestor -system.cpu2.icache.occ_percent::cpu2.inst 0.166460 # Average percentage of cache occupancy -system.cpu2.icache.occ_percent::total 0.166460 # Average percentage of cache occupancy -system.cpu2.icache.ReadReq_hits::cpu2.inst 18578 # number of ReadReq hits -system.cpu2.icache.ReadReq_hits::total 18578 # number of ReadReq hits -system.cpu2.icache.demand_hits::cpu2.inst 18578 # number of demand (read+write) hits -system.cpu2.icache.demand_hits::total 18578 # number of demand (read+write) hits -system.cpu2.icache.overall_hits::cpu2.inst 18578 # number of overall hits -system.cpu2.icache.overall_hits::total 18578 # number of overall hits -system.cpu2.icache.ReadReq_misses::cpu2.inst 481 # number of ReadReq misses -system.cpu2.icache.ReadReq_misses::total 481 # number of ReadReq misses -system.cpu2.icache.demand_misses::cpu2.inst 481 # number of demand (read+write) misses -system.cpu2.icache.demand_misses::total 481 # number of demand (read+write) misses -system.cpu2.icache.overall_misses::cpu2.inst 481 # number of overall misses -system.cpu2.icache.overall_misses::total 481 # number of overall misses -system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 10446500 # number of ReadReq miss cycles -system.cpu2.icache.ReadReq_miss_latency::total 10446500 # number of ReadReq miss cycles -system.cpu2.icache.demand_miss_latency::cpu2.inst 10446500 # number of demand (read+write) miss cycles -system.cpu2.icache.demand_miss_latency::total 10446500 # number of demand (read+write) miss cycles -system.cpu2.icache.overall_miss_latency::cpu2.inst 10446500 # number of overall miss cycles -system.cpu2.icache.overall_miss_latency::total 10446500 # number of overall miss cycles -system.cpu2.icache.ReadReq_accesses::cpu2.inst 19059 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.ReadReq_accesses::total 19059 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.demand_accesses::cpu2.inst 19059 # number of demand (read+write) accesses -system.cpu2.icache.demand_accesses::total 19059 # number of demand (read+write) accesses -system.cpu2.icache.overall_accesses::cpu2.inst 19059 # number of overall (read+write) accesses -system.cpu2.icache.overall_accesses::total 19059 # number of overall (read+write) accesses -system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.025237 # miss rate for ReadReq accesses -system.cpu2.icache.demand_miss_rate::cpu2.inst 0.025237 # miss rate for demand accesses -system.cpu2.icache.overall_miss_rate::cpu2.inst 0.025237 # miss rate for overall accesses -system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 21718.295218 # average ReadReq miss latency -system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 21718.295218 # average overall miss latency -system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 21718.295218 # average overall miss latency +system.cpu2.icache.occ_blocks::cpu2.inst 91.851117 # Average occupied blocks per requestor +system.cpu2.icache.occ_percent::cpu2.inst 0.179397 # Average percentage of cache occupancy +system.cpu2.icache.occ_percent::total 0.179397 # Average percentage of cache occupancy +system.cpu2.icache.ReadReq_hits::cpu2.inst 21358 # number of ReadReq hits +system.cpu2.icache.ReadReq_hits::total 21358 # number of ReadReq hits +system.cpu2.icache.demand_hits::cpu2.inst 21358 # number of demand (read+write) hits +system.cpu2.icache.demand_hits::total 21358 # number of demand (read+write) hits +system.cpu2.icache.overall_hits::cpu2.inst 21358 # number of overall hits +system.cpu2.icache.overall_hits::total 21358 # number of overall hits +system.cpu2.icache.ReadReq_misses::cpu2.inst 512 # number of ReadReq misses +system.cpu2.icache.ReadReq_misses::total 512 # number of ReadReq misses +system.cpu2.icache.demand_misses::cpu2.inst 512 # number of demand (read+write) misses +system.cpu2.icache.demand_misses::total 512 # number of demand (read+write) misses +system.cpu2.icache.overall_misses::cpu2.inst 512 # number of overall misses +system.cpu2.icache.overall_misses::total 512 # number of overall misses +system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 11141500 # number of ReadReq miss cycles +system.cpu2.icache.ReadReq_miss_latency::total 11141500 # number of ReadReq miss cycles +system.cpu2.icache.demand_miss_latency::cpu2.inst 11141500 # number of demand (read+write) miss cycles +system.cpu2.icache.demand_miss_latency::total 11141500 # number of demand (read+write) miss cycles +system.cpu2.icache.overall_miss_latency::cpu2.inst 11141500 # number of overall miss cycles +system.cpu2.icache.overall_miss_latency::total 11141500 # number of overall miss cycles +system.cpu2.icache.ReadReq_accesses::cpu2.inst 21870 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.ReadReq_accesses::total 21870 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.demand_accesses::cpu2.inst 21870 # number of demand (read+write) accesses +system.cpu2.icache.demand_accesses::total 21870 # number of demand (read+write) accesses +system.cpu2.icache.overall_accesses::cpu2.inst 21870 # number of overall (read+write) accesses +system.cpu2.icache.overall_accesses::total 21870 # number of overall (read+write) accesses +system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.023411 # miss rate for ReadReq accesses +system.cpu2.icache.demand_miss_rate::cpu2.inst 0.023411 # miss rate for demand accesses +system.cpu2.icache.overall_miss_rate::cpu2.inst 0.023411 # miss rate for overall accesses +system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 21760.742188 # average ReadReq miss latency +system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 21760.742188 # average overall miss latency +system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 21760.742188 # average overall miss latency system.cpu2.icache.blocked_cycles::no_mshrs 33000 # number of cycles access was blocked system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.icache.blocked::no_mshrs 1 # number of cycles access was blocked @@ -1224,90 +1224,90 @@ system.cpu2.icache.avg_blocked_cycles::no_mshrs 33000 system.cpu2.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu2.icache.fast_writes 0 # number of fast writes performed system.cpu2.icache.cache_copies 0 # number of cache copies performed -system.cpu2.icache.ReadReq_mshr_hits::cpu2.inst 54 # number of ReadReq MSHR hits -system.cpu2.icache.ReadReq_mshr_hits::total 54 # number of ReadReq MSHR hits -system.cpu2.icache.demand_mshr_hits::cpu2.inst 54 # number of demand (read+write) MSHR hits -system.cpu2.icache.demand_mshr_hits::total 54 # number of demand (read+write) MSHR hits -system.cpu2.icache.overall_mshr_hits::cpu2.inst 54 # number of overall MSHR hits -system.cpu2.icache.overall_mshr_hits::total 54 # number of overall MSHR hits -system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst 427 # number of ReadReq MSHR misses -system.cpu2.icache.ReadReq_mshr_misses::total 427 # number of ReadReq MSHR misses -system.cpu2.icache.demand_mshr_misses::cpu2.inst 427 # number of demand (read+write) MSHR misses -system.cpu2.icache.demand_mshr_misses::total 427 # number of demand (read+write) MSHR misses -system.cpu2.icache.overall_mshr_misses::cpu2.inst 427 # number of overall MSHR misses -system.cpu2.icache.overall_mshr_misses::total 427 # number of overall MSHR misses -system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 8026500 # number of ReadReq MSHR miss cycles -system.cpu2.icache.ReadReq_mshr_miss_latency::total 8026500 # number of ReadReq MSHR miss cycles -system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 8026500 # number of demand (read+write) MSHR miss cycles -system.cpu2.icache.demand_mshr_miss_latency::total 8026500 # number of demand (read+write) MSHR miss cycles -system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 8026500 # number of overall MSHR miss cycles -system.cpu2.icache.overall_mshr_miss_latency::total 8026500 # number of overall MSHR miss cycles -system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.022404 # mshr miss rate for ReadReq accesses -system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.022404 # mshr miss rate for demand accesses -system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.022404 # mshr miss rate for overall accesses -system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 18797.423888 # average ReadReq mshr miss latency -system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 18797.423888 # average overall mshr miss latency -system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 18797.423888 # average overall mshr miss latency +system.cpu2.icache.ReadReq_mshr_hits::cpu2.inst 72 # number of ReadReq MSHR hits +system.cpu2.icache.ReadReq_mshr_hits::total 72 # number of ReadReq MSHR hits +system.cpu2.icache.demand_mshr_hits::cpu2.inst 72 # number of demand (read+write) MSHR hits +system.cpu2.icache.demand_mshr_hits::total 72 # number of demand (read+write) MSHR hits +system.cpu2.icache.overall_mshr_hits::cpu2.inst 72 # number of overall MSHR hits +system.cpu2.icache.overall_mshr_hits::total 72 # number of overall MSHR hits +system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst 440 # number of ReadReq MSHR misses +system.cpu2.icache.ReadReq_mshr_misses::total 440 # number of ReadReq MSHR misses +system.cpu2.icache.demand_mshr_misses::cpu2.inst 440 # number of demand (read+write) MSHR misses +system.cpu2.icache.demand_mshr_misses::total 440 # number of demand (read+write) MSHR misses +system.cpu2.icache.overall_mshr_misses::cpu2.inst 440 # number of overall MSHR misses +system.cpu2.icache.overall_mshr_misses::total 440 # number of overall MSHR misses +system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 8467000 # number of ReadReq MSHR miss cycles +system.cpu2.icache.ReadReq_mshr_miss_latency::total 8467000 # number of ReadReq MSHR miss cycles +system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 8467000 # number of demand (read+write) MSHR miss cycles +system.cpu2.icache.demand_mshr_miss_latency::total 8467000 # number of demand (read+write) MSHR miss cycles +system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 8467000 # number of overall MSHR miss cycles +system.cpu2.icache.overall_mshr_miss_latency::total 8467000 # number of overall MSHR miss cycles +system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.020119 # mshr miss rate for ReadReq accesses +system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.020119 # mshr miss rate for demand accesses +system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.020119 # mshr miss rate for overall accesses +system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 19243.181818 # average ReadReq mshr miss latency +system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 19243.181818 # average overall mshr miss latency +system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 19243.181818 # average overall mshr miss latency system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu2.dcache.replacements 2 # number of replacements -system.cpu2.dcache.tagsinuse 26.582846 # Cycle average of tags in use -system.cpu2.dcache.total_refs 40686 # Total number of references to valid blocks. -system.cpu2.dcache.sampled_refs 30 # Sample count of references to valid blocks. -system.cpu2.dcache.avg_refs 1356.200000 # Average number of references to valid blocks. +system.cpu2.dcache.tagsinuse 26.720433 # Cycle average of tags in use +system.cpu2.dcache.total_refs 41712 # Total number of references to valid blocks. +system.cpu2.dcache.sampled_refs 31 # Sample count of references to valid blocks. +system.cpu2.dcache.avg_refs 1345.548387 # Average number of references to valid blocks. system.cpu2.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.dcache.occ_blocks::cpu2.data 26.582846 # Average occupied blocks per requestor -system.cpu2.dcache.occ_percent::cpu2.data 0.051920 # Average percentage of cache occupancy -system.cpu2.dcache.occ_percent::total 0.051920 # Average percentage of cache occupancy -system.cpu2.dcache.ReadReq_hits::cpu2.data 43569 # number of ReadReq hits -system.cpu2.dcache.ReadReq_hits::total 43569 # number of ReadReq hits -system.cpu2.dcache.WriteReq_hits::cpu2.data 34581 # number of WriteReq hits -system.cpu2.dcache.WriteReq_hits::total 34581 # number of WriteReq hits -system.cpu2.dcache.SwapReq_hits::cpu2.data 13 # number of SwapReq hits -system.cpu2.dcache.SwapReq_hits::total 13 # number of SwapReq hits -system.cpu2.dcache.demand_hits::cpu2.data 78150 # number of demand (read+write) hits -system.cpu2.dcache.demand_hits::total 78150 # number of demand (read+write) hits -system.cpu2.dcache.overall_hits::cpu2.data 78150 # number of overall hits -system.cpu2.dcache.overall_hits::total 78150 # number of overall hits -system.cpu2.dcache.ReadReq_misses::cpu2.data 459 # number of ReadReq misses -system.cpu2.dcache.ReadReq_misses::total 459 # number of ReadReq misses -system.cpu2.dcache.WriteReq_misses::cpu2.data 120 # number of WriteReq misses -system.cpu2.dcache.WriteReq_misses::total 120 # number of WriteReq misses -system.cpu2.dcache.SwapReq_misses::cpu2.data 61 # number of SwapReq misses -system.cpu2.dcache.SwapReq_misses::total 61 # number of SwapReq misses -system.cpu2.dcache.demand_misses::cpu2.data 579 # number of demand (read+write) misses -system.cpu2.dcache.demand_misses::total 579 # number of demand (read+write) misses -system.cpu2.dcache.overall_misses::cpu2.data 579 # number of overall misses -system.cpu2.dcache.overall_misses::total 579 # number of overall misses -system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 10999500 # number of ReadReq miss cycles -system.cpu2.dcache.ReadReq_miss_latency::total 10999500 # number of ReadReq miss cycles -system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 2980500 # number of WriteReq miss cycles -system.cpu2.dcache.WriteReq_miss_latency::total 2980500 # number of WriteReq miss cycles -system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 1343500 # number of SwapReq miss cycles -system.cpu2.dcache.SwapReq_miss_latency::total 1343500 # number of SwapReq miss cycles -system.cpu2.dcache.demand_miss_latency::cpu2.data 13980000 # number of demand (read+write) miss cycles -system.cpu2.dcache.demand_miss_latency::total 13980000 # number of demand (read+write) miss cycles -system.cpu2.dcache.overall_miss_latency::cpu2.data 13980000 # number of overall miss cycles -system.cpu2.dcache.overall_miss_latency::total 13980000 # number of overall miss cycles -system.cpu2.dcache.ReadReq_accesses::cpu2.data 44028 # number of ReadReq accesses(hits+misses) -system.cpu2.dcache.ReadReq_accesses::total 44028 # number of ReadReq accesses(hits+misses) -system.cpu2.dcache.WriteReq_accesses::cpu2.data 34701 # number of WriteReq accesses(hits+misses) -system.cpu2.dcache.WriteReq_accesses::total 34701 # number of WriteReq accesses(hits+misses) -system.cpu2.dcache.SwapReq_accesses::cpu2.data 74 # number of SwapReq accesses(hits+misses) -system.cpu2.dcache.SwapReq_accesses::total 74 # number of SwapReq accesses(hits+misses) -system.cpu2.dcache.demand_accesses::cpu2.data 78729 # number of demand (read+write) accesses -system.cpu2.dcache.demand_accesses::total 78729 # number of demand (read+write) accesses -system.cpu2.dcache.overall_accesses::cpu2.data 78729 # number of overall (read+write) accesses -system.cpu2.dcache.overall_accesses::total 78729 # number of overall (read+write) accesses -system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.010425 # miss rate for ReadReq accesses -system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.003458 # miss rate for WriteReq accesses -system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.824324 # miss rate for SwapReq accesses -system.cpu2.dcache.demand_miss_rate::cpu2.data 0.007354 # miss rate for demand accesses -system.cpu2.dcache.overall_miss_rate::cpu2.data 0.007354 # miss rate for overall accesses -system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 23964.052288 # average ReadReq miss latency -system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 24837.500000 # average WriteReq miss latency -system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 22024.590164 # average SwapReq miss latency -system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 24145.077720 # average overall miss latency -system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 24145.077720 # average overall miss latency +system.cpu2.dcache.occ_blocks::cpu2.data 26.720433 # Average occupied blocks per requestor +system.cpu2.dcache.occ_percent::cpu2.data 0.052188 # Average percentage of cache occupancy +system.cpu2.dcache.occ_percent::total 0.052188 # Average percentage of cache occupancy +system.cpu2.dcache.ReadReq_hits::cpu2.data 45716 # number of ReadReq hits +system.cpu2.dcache.ReadReq_hits::total 45716 # number of ReadReq hits +system.cpu2.dcache.WriteReq_hits::cpu2.data 35144 # number of WriteReq hits +system.cpu2.dcache.WriteReq_hits::total 35144 # number of WriteReq hits +system.cpu2.dcache.SwapReq_hits::cpu2.data 14 # number of SwapReq hits +system.cpu2.dcache.SwapReq_hits::total 14 # number of SwapReq hits +system.cpu2.dcache.demand_hits::cpu2.data 80860 # number of demand (read+write) hits +system.cpu2.dcache.demand_hits::total 80860 # number of demand (read+write) hits +system.cpu2.dcache.overall_hits::cpu2.data 80860 # number of overall hits +system.cpu2.dcache.overall_hits::total 80860 # number of overall hits +system.cpu2.dcache.ReadReq_misses::cpu2.data 438 # number of ReadReq misses +system.cpu2.dcache.ReadReq_misses::total 438 # number of ReadReq misses +system.cpu2.dcache.WriteReq_misses::cpu2.data 146 # number of WriteReq misses +system.cpu2.dcache.WriteReq_misses::total 146 # number of WriteReq misses +system.cpu2.dcache.SwapReq_misses::cpu2.data 62 # number of SwapReq misses +system.cpu2.dcache.SwapReq_misses::total 62 # number of SwapReq misses +system.cpu2.dcache.demand_misses::cpu2.data 584 # number of demand (read+write) misses +system.cpu2.dcache.demand_misses::total 584 # number of demand (read+write) misses +system.cpu2.dcache.overall_misses::cpu2.data 584 # number of overall misses +system.cpu2.dcache.overall_misses::total 584 # number of overall misses +system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 10255000 # number of ReadReq miss cycles +system.cpu2.dcache.ReadReq_miss_latency::total 10255000 # number of ReadReq miss cycles +system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 2937000 # number of WriteReq miss cycles +system.cpu2.dcache.WriteReq_miss_latency::total 2937000 # number of WriteReq miss cycles +system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 1181000 # number of SwapReq miss cycles +system.cpu2.dcache.SwapReq_miss_latency::total 1181000 # number of SwapReq miss cycles +system.cpu2.dcache.demand_miss_latency::cpu2.data 13192000 # number of demand (read+write) miss cycles +system.cpu2.dcache.demand_miss_latency::total 13192000 # number of demand (read+write) miss cycles +system.cpu2.dcache.overall_miss_latency::cpu2.data 13192000 # number of overall miss cycles +system.cpu2.dcache.overall_miss_latency::total 13192000 # number of overall miss cycles +system.cpu2.dcache.ReadReq_accesses::cpu2.data 46154 # number of ReadReq accesses(hits+misses) +system.cpu2.dcache.ReadReq_accesses::total 46154 # number of ReadReq accesses(hits+misses) +system.cpu2.dcache.WriteReq_accesses::cpu2.data 35290 # number of WriteReq accesses(hits+misses) +system.cpu2.dcache.WriteReq_accesses::total 35290 # number of WriteReq accesses(hits+misses) +system.cpu2.dcache.SwapReq_accesses::cpu2.data 76 # number of SwapReq accesses(hits+misses) +system.cpu2.dcache.SwapReq_accesses::total 76 # number of SwapReq accesses(hits+misses) +system.cpu2.dcache.demand_accesses::cpu2.data 81444 # number of demand (read+write) accesses +system.cpu2.dcache.demand_accesses::total 81444 # number of demand (read+write) accesses +system.cpu2.dcache.overall_accesses::cpu2.data 81444 # number of overall (read+write) accesses +system.cpu2.dcache.overall_accesses::total 81444 # number of overall (read+write) accesses +system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.009490 # miss rate for ReadReq accesses +system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.004137 # miss rate for WriteReq accesses +system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.815789 # miss rate for SwapReq accesses +system.cpu2.dcache.demand_miss_rate::cpu2.data 0.007171 # miss rate for demand accesses +system.cpu2.dcache.overall_miss_rate::cpu2.data 0.007171 # miss rate for overall accesses +system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 23413.242009 # average ReadReq miss latency +system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 20116.438356 # average WriteReq miss latency +system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 19048.387097 # average SwapReq miss latency +system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 22589.041096 # average overall miss latency +system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 22589.041096 # average overall miss latency system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1318,350 +1318,350 @@ system.cpu2.dcache.fast_writes 0 # nu system.cpu2.dcache.cache_copies 0 # number of cache copies performed system.cpu2.dcache.writebacks::writebacks 1 # number of writebacks system.cpu2.dcache.writebacks::total 1 # number of writebacks -system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data 297 # number of ReadReq MSHR hits -system.cpu2.dcache.ReadReq_mshr_hits::total 297 # number of ReadReq MSHR hits -system.cpu2.dcache.WriteReq_mshr_hits::cpu2.data 18 # number of WriteReq MSHR hits -system.cpu2.dcache.WriteReq_mshr_hits::total 18 # number of WriteReq MSHR hits -system.cpu2.dcache.demand_mshr_hits::cpu2.data 315 # number of demand (read+write) MSHR hits -system.cpu2.dcache.demand_mshr_hits::total 315 # number of demand (read+write) MSHR hits -system.cpu2.dcache.overall_mshr_hits::cpu2.data 315 # number of overall MSHR hits -system.cpu2.dcache.overall_mshr_hits::total 315 # number of overall MSHR hits -system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 162 # number of ReadReq MSHR misses -system.cpu2.dcache.ReadReq_mshr_misses::total 162 # number of ReadReq MSHR misses -system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 102 # number of WriteReq MSHR misses -system.cpu2.dcache.WriteReq_mshr_misses::total 102 # number of WriteReq MSHR misses -system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 61 # number of SwapReq MSHR misses -system.cpu2.dcache.SwapReq_mshr_misses::total 61 # number of SwapReq MSHR misses -system.cpu2.dcache.demand_mshr_misses::cpu2.data 264 # number of demand (read+write) MSHR misses -system.cpu2.dcache.demand_mshr_misses::total 264 # number of demand (read+write) MSHR misses -system.cpu2.dcache.overall_mshr_misses::cpu2.data 264 # number of overall MSHR misses -system.cpu2.dcache.overall_mshr_misses::total 264 # number of overall MSHR misses -system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 2380000 # number of ReadReq MSHR miss cycles -system.cpu2.dcache.ReadReq_mshr_miss_latency::total 2380000 # number of ReadReq MSHR miss cycles -system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1660000 # number of WriteReq MSHR miss cycles -system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1660000 # number of WriteReq MSHR miss cycles -system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 1160500 # number of SwapReq MSHR miss cycles -system.cpu2.dcache.SwapReq_mshr_miss_latency::total 1160500 # number of SwapReq MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 4040000 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_latency::total 4040000 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 4040000 # number of overall MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_latency::total 4040000 # number of overall MSHR miss cycles -system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003679 # mshr miss rate for ReadReq accesses -system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.002939 # mshr miss rate for WriteReq accesses -system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.824324 # mshr miss rate for SwapReq accesses -system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.003353 # mshr miss rate for demand accesses -system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.003353 # mshr miss rate for overall accesses -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 14691.358025 # average ReadReq mshr miss latency -system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 16274.509804 # average WriteReq mshr miss latency -system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 19024.590164 # average SwapReq mshr miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 15303.030303 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 15303.030303 # average overall mshr miss latency +system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data 267 # number of ReadReq MSHR hits +system.cpu2.dcache.ReadReq_mshr_hits::total 267 # number of ReadReq MSHR hits +system.cpu2.dcache.WriteReq_mshr_hits::cpu2.data 45 # number of WriteReq MSHR hits +system.cpu2.dcache.WriteReq_mshr_hits::total 45 # number of WriteReq MSHR hits +system.cpu2.dcache.demand_mshr_hits::cpu2.data 312 # number of demand (read+write) MSHR hits +system.cpu2.dcache.demand_mshr_hits::total 312 # number of demand (read+write) MSHR hits +system.cpu2.dcache.overall_mshr_hits::cpu2.data 312 # number of overall MSHR hits +system.cpu2.dcache.overall_mshr_hits::total 312 # number of overall MSHR hits +system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 171 # number of ReadReq MSHR misses +system.cpu2.dcache.ReadReq_mshr_misses::total 171 # number of ReadReq MSHR misses +system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 101 # number of WriteReq MSHR misses +system.cpu2.dcache.WriteReq_mshr_misses::total 101 # number of WriteReq MSHR misses +system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 62 # number of SwapReq MSHR misses +system.cpu2.dcache.SwapReq_mshr_misses::total 62 # number of SwapReq MSHR misses +system.cpu2.dcache.demand_mshr_misses::cpu2.data 272 # number of demand (read+write) MSHR misses +system.cpu2.dcache.demand_mshr_misses::total 272 # number of demand (read+write) MSHR misses +system.cpu2.dcache.overall_mshr_misses::cpu2.data 272 # number of overall MSHR misses +system.cpu2.dcache.overall_mshr_misses::total 272 # number of overall MSHR misses +system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 2480000 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_latency::total 2480000 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1516500 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1516500 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 995000 # number of SwapReq MSHR miss cycles +system.cpu2.dcache.SwapReq_mshr_miss_latency::total 995000 # number of SwapReq MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 3996500 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_latency::total 3996500 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 3996500 # number of overall MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_latency::total 3996500 # number of overall MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003705 # mshr miss rate for ReadReq accesses +system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.002862 # mshr miss rate for WriteReq accesses +system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.815789 # mshr miss rate for SwapReq accesses +system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.003340 # mshr miss rate for demand accesses +system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.003340 # mshr miss rate for overall accesses +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 14502.923977 # average ReadReq mshr miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 15014.851485 # average WriteReq mshr miss latency +system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 16048.387097 # average SwapReq mshr miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 14693.014706 # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 14693.014706 # average overall mshr miss latency system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.numCycles 173752 # number of cpu cycles simulated +system.cpu3.numCycles 186832 # number of cpu cycles simulated system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu3.BPredUnit.lookups 43974 # Number of BP lookups -system.cpu3.BPredUnit.condPredicted 41362 # Number of conditional branches predicted -system.cpu3.BPredUnit.condIncorrect 1065 # Number of conditional branches incorrect -system.cpu3.BPredUnit.BTBLookups 40218 # Number of BTB lookups -system.cpu3.BPredUnit.BTBHits 38243 # Number of BTB hits +system.cpu3.BPredUnit.lookups 49447 # Number of BP lookups +system.cpu3.BPredUnit.condPredicted 46344 # Number of conditional branches predicted +system.cpu3.BPredUnit.condIncorrect 1525 # Number of conditional branches incorrect +system.cpu3.BPredUnit.BTBLookups 42752 # Number of BTB lookups +system.cpu3.BPredUnit.BTBHits 41712 # Number of BTB hits system.cpu3.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu3.BPredUnit.usedRAS 627 # Number of times the RAS was used to get a target. +system.cpu3.BPredUnit.usedRAS 813 # Number of times the RAS was used to get a target. system.cpu3.BPredUnit.RASInCorrect 232 # Number of incorrect RAS predictions. -system.cpu3.fetch.icacheStallCycles 31228 # Number of cycles fetch is stalled on an Icache miss -system.cpu3.fetch.Insts 238342 # Number of instructions fetch has processed -system.cpu3.fetch.Branches 43974 # Number of branches that fetch encountered -system.cpu3.fetch.predictedBranches 38870 # Number of branches that fetch has predicted taken -system.cpu3.fetch.Cycles 88902 # Number of cycles fetch has run and was not squashing or blocked -system.cpu3.fetch.SquashCycles 3085 # Number of cycles fetch has spent squashing -system.cpu3.fetch.BlockedCycles 41810 # Number of cycles fetch has spent blocked +system.cpu3.fetch.icacheStallCycles 32933 # Number of cycles fetch is stalled on an Icache miss +system.cpu3.fetch.Insts 270157 # Number of instructions fetch has processed +system.cpu3.fetch.Branches 49447 # Number of branches that fetch encountered +system.cpu3.fetch.predictedBranches 42525 # Number of branches that fetch has predicted taken +system.cpu3.fetch.Cycles 98584 # Number of cycles fetch has run and was not squashing or blocked +system.cpu3.fetch.SquashCycles 4439 # Number of cycles fetch has spent squashing +system.cpu3.fetch.BlockedCycles 41922 # Number of cycles fetch has spent blocked system.cpu3.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu3.fetch.NoActiveThreadStallCycles 6387 # Number of stall cycles due to no active thread to fetch from -system.cpu3.fetch.PendingTrapStallCycles 706 # Number of stall cycles due to pending traps -system.cpu3.fetch.CacheLines 22959 # Number of cache lines fetched -system.cpu3.fetch.IcacheSquashes 173 # Number of outstanding Icache misses that were squashed -system.cpu3.fetch.rateDist::samples 170982 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::mean 1.393960 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::stdev 2.002021 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.NoActiveThreadStallCycles 6509 # Number of stall cycles due to no active thread to fetch from +system.cpu3.fetch.PendingTrapStallCycles 1070 # Number of stall cycles due to pending traps +system.cpu3.fetch.CacheLines 24454 # Number of cache lines fetched +system.cpu3.fetch.IcacheSquashes 317 # Number of outstanding Icache misses that were squashed +system.cpu3.fetch.rateDist::samples 183862 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::mean 1.469347 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::stdev 2.064581 # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::0 82080 48.01% 48.01% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::1 46273 27.06% 75.07% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::2 8028 4.70% 79.76% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::3 3581 2.09% 81.86% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::4 661 0.39% 82.24% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::5 25734 15.05% 97.30% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::6 1333 0.78% 98.07% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::7 378 0.22% 98.30% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::8 2914 1.70% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::0 85278 46.38% 46.38% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::1 51117 27.80% 74.18% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::2 8231 4.48% 78.66% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::3 3382 1.84% 80.50% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::4 704 0.38% 80.88% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::5 29457 16.02% 96.90% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::6 1168 0.64% 97.54% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::7 877 0.48% 98.02% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::8 3648 1.98% 100.00% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::total 170982 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.branchRate 0.253085 # Number of branch fetches per cycle -system.cpu3.fetch.rate 1.371737 # Number of inst fetches per cycle -system.cpu3.decode.IdleCycles 38250 # Number of cycles decode is idle -system.cpu3.decode.BlockedCycles 36210 # Number of cycles decode is blocked -system.cpu3.decode.RunCycles 81249 # Number of cycles decode is running -system.cpu3.decode.UnblockCycles 6942 # Number of cycles decode is unblocking -system.cpu3.decode.SquashCycles 1944 # Number of cycles decode is squashing -system.cpu3.decode.DecodedInsts 235582 # Number of instructions handled by decode -system.cpu3.rename.SquashCycles 1944 # Number of cycles rename is squashing -system.cpu3.rename.IdleCycles 38898 # Number of cycles rename is idle -system.cpu3.rename.BlockCycles 21197 # Number of cycles rename is blocking -system.cpu3.rename.serializeStallCycles 14171 # count of cycles rename stalled for serializing inst -system.cpu3.rename.RunCycles 74841 # Number of cycles rename is running -system.cpu3.rename.UnblockCycles 13544 # Number of cycles rename is unblocking -system.cpu3.rename.RenamedInsts 233650 # Number of instructions processed by rename -system.cpu3.rename.IQFullEvents 34 # Number of times rename has blocked due to IQ full -system.cpu3.rename.LSQFullEvents 44 # Number of times rename has blocked due to LSQ full -system.cpu3.rename.RenamedOperands 161376 # Number of destination operands rename has renamed -system.cpu3.rename.RenameLookups 435940 # Number of register rename lookups that rename has made -system.cpu3.rename.int_rename_lookups 435940 # Number of integer rename lookups -system.cpu3.rename.CommittedMaps 151925 # Number of HB maps that are committed -system.cpu3.rename.UndoneMaps 9451 # Number of HB maps that are undone due to squashing -system.cpu3.rename.serializingInsts 1060 # count of serializing insts renamed -system.cpu3.rename.tempSerializingInsts 1201 # count of temporary serializing insts renamed -system.cpu3.rename.skidInsts 16222 # count of insts added to the skid buffer -system.cpu3.memDep0.insertedLoads 63593 # Number of loads inserted to the mem dependence unit. -system.cpu3.memDep0.insertedStores 28573 # Number of stores inserted to the mem dependence unit. -system.cpu3.memDep0.conflictingLoads 31152 # Number of conflicting loads. -system.cpu3.memDep0.conflictingStores 24018 # Number of conflicting stores. -system.cpu3.iq.iqInstsAdded 191280 # Number of instructions added to the IQ (excludes non-spec) -system.cpu3.iq.iqNonSpecInstsAdded 8270 # Number of non-speculative instructions added to the IQ -system.cpu3.iq.iqInstsIssued 196054 # Number of instructions issued -system.cpu3.iq.iqSquashedInstsIssued 3 # Number of squashed instructions issued -system.cpu3.iq.iqSquashedInstsExamined 8200 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu3.iq.iqSquashedOperandsExamined 7610 # Number of squashed operands that are examined and possibly removed from graph -system.cpu3.iq.iqSquashedNonSpecRemoved 629 # Number of squashed non-spec instructions that were removed -system.cpu3.iq.issued_per_cycle::samples 170982 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::mean 1.146635 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::stdev 1.276395 # Number of insts issued each cycle +system.cpu3.fetch.rateDist::total 183862 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.branchRate 0.264660 # Number of branch fetches per cycle +system.cpu3.fetch.rate 1.445989 # Number of inst fetches per cycle +system.cpu3.decode.IdleCycles 40520 # Number of cycles decode is idle +system.cpu3.decode.BlockedCycles 36424 # Number of cycles decode is blocked +system.cpu3.decode.RunCycles 90525 # Number of cycles decode is running +system.cpu3.decode.UnblockCycles 7045 # Number of cycles decode is unblocking +system.cpu3.decode.SquashCycles 2839 # Number of cycles decode is squashing +system.cpu3.decode.DecodedInsts 265643 # Number of instructions handled by decode +system.cpu3.rename.SquashCycles 2839 # Number of cycles rename is squashing +system.cpu3.rename.IdleCycles 41308 # Number of cycles rename is idle +system.cpu3.rename.BlockCycles 21637 # Number of cycles rename is blocking +system.cpu3.rename.serializeStallCycles 13915 # count of cycles rename stalled for serializing inst +system.cpu3.rename.RunCycles 83785 # Number of cycles rename is running +system.cpu3.rename.UnblockCycles 13869 # Number of cycles rename is unblocking +system.cpu3.rename.RenamedInsts 263122 # Number of instructions processed by rename +system.cpu3.rename.IQFullEvents 18 # Number of times rename has blocked due to IQ full +system.cpu3.rename.LSQFullEvents 51 # Number of times rename has blocked due to LSQ full +system.cpu3.rename.RenamedOperands 182223 # Number of destination operands rename has renamed +system.cpu3.rename.RenameLookups 494224 # Number of register rename lookups that rename has made +system.cpu3.rename.int_rename_lookups 494224 # Number of integer rename lookups +system.cpu3.rename.CommittedMaps 166723 # Number of HB maps that are committed +system.cpu3.rename.UndoneMaps 15500 # Number of HB maps that are undone due to squashing +system.cpu3.rename.serializingInsts 1230 # count of serializing insts renamed +system.cpu3.rename.tempSerializingInsts 1367 # count of temporary serializing insts renamed +system.cpu3.rename.skidInsts 16602 # count of insts added to the skid buffer +system.cpu3.memDep0.insertedLoads 72088 # Number of loads inserted to the mem dependence unit. +system.cpu3.memDep0.insertedStores 32971 # Number of stores inserted to the mem dependence unit. +system.cpu3.memDep0.conflictingLoads 35168 # Number of conflicting loads. +system.cpu3.memDep0.conflictingStores 27743 # Number of conflicting stores. +system.cpu3.iq.iqInstsAdded 215022 # Number of instructions added to the IQ (excludes non-spec) +system.cpu3.iq.iqNonSpecInstsAdded 8560 # Number of non-speculative instructions added to the IQ +system.cpu3.iq.iqInstsIssued 218529 # Number of instructions issued +system.cpu3.iq.iqSquashedInstsIssued 46 # Number of squashed instructions issued +system.cpu3.iq.iqSquashedInstsExamined 12998 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu3.iq.iqSquashedOperandsExamined 11805 # Number of squashed operands that are examined and possibly removed from graph +system.cpu3.iq.iqSquashedNonSpecRemoved 824 # Number of squashed non-spec instructions that were removed +system.cpu3.iq.issued_per_cycle::samples 183862 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::mean 1.188549 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::stdev 1.293380 # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::0 79237 46.34% 46.34% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::1 28336 16.57% 62.91% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::2 28717 16.80% 79.71% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::3 30135 17.62% 97.33% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::4 3289 1.92% 99.26% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::5 1034 0.60% 99.86% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::6 139 0.08% 99.94% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::7 41 0.02% 99.97% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::8 54 0.03% 100.00% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::0 83207 45.26% 45.26% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::1 28783 15.65% 60.91% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::2 33187 18.05% 78.96% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::3 33716 18.34% 97.30% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::4 3245 1.76% 99.06% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::5 1264 0.69% 99.75% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::6 353 0.19% 99.94% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::7 50 0.03% 99.97% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::8 57 0.03% 100.00% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::total 170982 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::total 183862 # Number of insts issued each cycle system.cpu3.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntAlu 11 4.49% 4.49% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntMult 0 0.00% 4.49% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntDiv 0 0.00% 4.49% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatAdd 0 0.00% 4.49% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatCmp 0 0.00% 4.49% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatCvt 0 0.00% 4.49% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatMult 0 0.00% 4.49% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatDiv 0 0.00% 4.49% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 4.49% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAdd 0 0.00% 4.49% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 4.49% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAlu 0 0.00% 4.49% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdCmp 0 0.00% 4.49% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdCvt 0 0.00% 4.49% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMisc 0 0.00% 4.49% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMult 0 0.00% 4.49% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 4.49% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdShift 0 0.00% 4.49% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 4.49% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 4.49% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 4.49% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 4.49% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 4.49% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 4.49% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 4.49% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 4.49% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 4.49% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.49% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 4.49% # attempts to use FU when none available -system.cpu3.iq.fu_full::MemRead 44 17.96% 22.45% # attempts to use FU when none available -system.cpu3.iq.fu_full::MemWrite 190 77.55% 100.00% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntAlu 21 7.02% 7.02% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntMult 0 0.00% 7.02% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntDiv 0 0.00% 7.02% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatAdd 0 0.00% 7.02% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatCmp 0 0.00% 7.02% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatCvt 0 0.00% 7.02% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatMult 0 0.00% 7.02% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatDiv 0 0.00% 7.02% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 7.02% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAdd 0 0.00% 7.02% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 7.02% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAlu 0 0.00% 7.02% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdCmp 0 0.00% 7.02% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdCvt 0 0.00% 7.02% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMisc 0 0.00% 7.02% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMult 0 0.00% 7.02% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 7.02% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdShift 0 0.00% 7.02% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 7.02% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 7.02% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 7.02% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 7.02% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 7.02% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 7.02% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 7.02% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 7.02% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 7.02% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 7.02% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 7.02% # attempts to use FU when none available +system.cpu3.iq.fu_full::MemRead 68 22.74% 29.77% # attempts to use FU when none available +system.cpu3.iq.fu_full::MemWrite 210 70.23% 100.00% # attempts to use FU when none available system.cpu3.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu3.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu3.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu3.iq.FU_type_0::IntAlu 97962 49.97% 49.97% # Type of FU issued -system.cpu3.iq.FU_type_0::IntMult 0 0.00% 49.97% # Type of FU issued -system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 49.97% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 49.97% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 49.97% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 49.97% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 49.97% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 49.97% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 49.97% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 49.97% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 49.97% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 49.97% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 49.97% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 49.97% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 49.97% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 49.97% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 49.97% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 49.97% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.97% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 49.97% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.97% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.97% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.97% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.97% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.97% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.97% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 49.97% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.97% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.97% # Type of FU issued -system.cpu3.iq.FU_type_0::MemRead 69919 35.66% 85.63% # Type of FU issued -system.cpu3.iq.FU_type_0::MemWrite 28173 14.37% 100.00% # Type of FU issued +system.cpu3.iq.FU_type_0::IntAlu 107929 49.39% 49.39% # Type of FU issued +system.cpu3.iq.FU_type_0::IntMult 0 0.00% 49.39% # Type of FU issued +system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 49.39% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 49.39% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 49.39% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 49.39% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 49.39% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 49.39% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 49.39% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 49.39% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 49.39% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 49.39% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 49.39% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 49.39% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 49.39% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 49.39% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 49.39% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 49.39% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.39% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 49.39% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.39% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.39% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.39% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.39% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.39% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.39% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 49.39% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.39% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.39% # Type of FU issued +system.cpu3.iq.FU_type_0::MemRead 78286 35.82% 85.21% # Type of FU issued +system.cpu3.iq.FU_type_0::MemWrite 32314 14.79% 100.00% # Type of FU issued system.cpu3.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu3.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu3.iq.FU_type_0::total 196054 # Type of FU issued -system.cpu3.iq.rate 1.128355 # Inst issue rate -system.cpu3.iq.fu_busy_cnt 245 # FU busy when requested -system.cpu3.iq.fu_busy_rate 0.001250 # FU busy rate (busy events/executed inst) -system.cpu3.iq.int_inst_queue_reads 563338 # Number of integer instruction queue reads -system.cpu3.iq.int_inst_queue_writes 207780 # Number of integer instruction queue writes -system.cpu3.iq.int_inst_queue_wakeup_accesses 194934 # Number of integer instruction queue wakeup accesses +system.cpu3.iq.FU_type_0::total 218529 # Type of FU issued +system.cpu3.iq.rate 1.169655 # Inst issue rate +system.cpu3.iq.fu_busy_cnt 299 # FU busy when requested +system.cpu3.iq.fu_busy_rate 0.001368 # FU busy rate (busy events/executed inst) +system.cpu3.iq.int_inst_queue_reads 621265 # Number of integer instruction queue reads +system.cpu3.iq.int_inst_queue_writes 236621 # Number of integer instruction queue writes +system.cpu3.iq.int_inst_queue_wakeup_accesses 216530 # Number of integer instruction queue wakeup accesses system.cpu3.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu3.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu3.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu3.iq.int_alu_accesses 196299 # Number of integer alu accesses +system.cpu3.iq.int_alu_accesses 218828 # Number of integer alu accesses system.cpu3.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu3.iew.lsq.thread0.forwLoads 23899 # Number of loads that had data forwarded from stores +system.cpu3.iew.lsq.thread0.forwLoads 27592 # Number of loads that had data forwarded from stores system.cpu3.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu3.iew.lsq.thread0.squashedLoads 1728 # Number of loads squashed -system.cpu3.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed -system.cpu3.iew.lsq.thread0.memOrderViolation 30 # Number of memory ordering violations -system.cpu3.iew.lsq.thread0.squashedStores 841 # Number of stores squashed +system.cpu3.iew.lsq.thread0.squashedLoads 2778 # Number of loads squashed +system.cpu3.iew.lsq.thread0.ignoredResponses 6 # Number of memory responses ignored because the instruction is squashed +system.cpu3.iew.lsq.thread0.memOrderViolation 41 # Number of memory ordering violations +system.cpu3.iew.lsq.thread0.squashedStores 1562 # Number of stores squashed system.cpu3.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu3.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu3.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu3.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu3.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu3.iew.iewSquashCycles 1944 # Number of cycles IEW is squashing -system.cpu3.iew.iewBlockCycles 1688 # Number of cycles IEW is blocking -system.cpu3.iew.iewUnblockCycles 45 # Number of cycles IEW is unblocking -system.cpu3.iew.iewDispatchedInsts 231715 # Number of instructions dispatched to IQ -system.cpu3.iew.iewDispSquashedInsts 366 # Number of squashed instructions skipped by dispatch -system.cpu3.iew.iewDispLoadInsts 63593 # Number of dispatched load instructions -system.cpu3.iew.iewDispStoreInsts 28573 # Number of dispatched store instructions -system.cpu3.iew.iewDispNonSpecInsts 992 # Number of dispatched non-speculative instructions -system.cpu3.iew.iewIQFullEvents 40 # Number of times the IQ has become full, causing a stall +system.cpu3.iew.iewSquashCycles 2839 # Number of cycles IEW is squashing +system.cpu3.iew.iewBlockCycles 1746 # Number of cycles IEW is blocking +system.cpu3.iew.iewUnblockCycles 57 # Number of cycles IEW is unblocking +system.cpu3.iew.iewDispatchedInsts 259780 # Number of instructions dispatched to IQ +system.cpu3.iew.iewDispSquashedInsts 389 # Number of squashed instructions skipped by dispatch +system.cpu3.iew.iewDispLoadInsts 72088 # Number of dispatched load instructions +system.cpu3.iew.iewDispStoreInsts 32971 # Number of dispatched store instructions +system.cpu3.iew.iewDispNonSpecInsts 1143 # Number of dispatched non-speculative instructions +system.cpu3.iew.iewIQFullEvents 55 # Number of times the IQ has become full, causing a stall system.cpu3.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu3.iew.memOrderViolationEvents 30 # Number of memory order violations -system.cpu3.iew.predictedTakenIncorrect 631 # Number of branches that were predicted taken incorrectly -system.cpu3.iew.predictedNotTakenIncorrect 549 # Number of branches that were predicted not taken incorrectly -system.cpu3.iew.branchMispredicts 1180 # Number of branch mispredicts detected at execute -system.cpu3.iew.iewExecutedInsts 195273 # Number of executed instructions -system.cpu3.iew.iewExecLoadInsts 62778 # Number of load instructions executed -system.cpu3.iew.iewExecSquashedInsts 781 # Number of squashed instructions skipped in execute +system.cpu3.iew.memOrderViolationEvents 41 # Number of memory order violations +system.cpu3.iew.predictedTakenIncorrect 513 # Number of branches that were predicted taken incorrectly +system.cpu3.iew.predictedNotTakenIncorrect 1186 # Number of branches that were predicted not taken incorrectly +system.cpu3.iew.branchMispredicts 1699 # Number of branch mispredicts detected at execute +system.cpu3.iew.iewExecutedInsts 217228 # Number of executed instructions +system.cpu3.iew.iewExecLoadInsts 70964 # Number of load instructions executed +system.cpu3.iew.iewExecSquashedInsts 1301 # Number of squashed instructions skipped in execute system.cpu3.iew.exec_swp 0 # number of swp insts executed -system.cpu3.iew.exec_nop 32165 # number of nop insts executed -system.cpu3.iew.exec_refs 90920 # number of memory reference insts executed -system.cpu3.iew.exec_branches 41191 # Number of branches executed -system.cpu3.iew.exec_stores 28142 # Number of stores executed -system.cpu3.iew.exec_rate 1.123860 # Inst execution rate -system.cpu3.iew.wb_sent 195091 # cumulative count of insts sent to commit -system.cpu3.iew.wb_count 194934 # cumulative count of insts written-back -system.cpu3.iew.wb_producers 107675 # num instructions producing a value -system.cpu3.iew.wb_consumers 111992 # num instructions consuming a value +system.cpu3.iew.exec_nop 36198 # number of nop insts executed +system.cpu3.iew.exec_refs 103196 # number of memory reference insts executed +system.cpu3.iew.exec_branches 45494 # Number of branches executed +system.cpu3.iew.exec_stores 32232 # Number of stores executed +system.cpu3.iew.exec_rate 1.162692 # Inst execution rate +system.cpu3.iew.wb_sent 216841 # cumulative count of insts sent to commit +system.cpu3.iew.wb_count 216530 # cumulative count of insts written-back +system.cpu3.iew.wb_producers 119982 # num instructions producing a value +system.cpu3.iew.wb_consumers 124874 # num instructions consuming a value system.cpu3.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu3.iew.wb_rate 1.121909 # insts written-back per cycle -system.cpu3.iew.wb_fanout 0.961453 # average fanout of values written-back +system.cpu3.iew.wb_rate 1.158956 # insts written-back per cycle +system.cpu3.iew.wb_fanout 0.960825 # average fanout of values written-back system.cpu3.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu3.commit.commitCommittedInsts 222296 # The number of committed instructions -system.cpu3.commit.commitCommittedOps 222296 # The number of committed instructions -system.cpu3.commit.commitSquashedInsts 9409 # The number of squashed insts skipped by commit -system.cpu3.commit.commitNonSpecStalls 7641 # The number of times commit has been forced to stall to communicate backwards -system.cpu3.commit.branchMispredicts 1065 # The number of times a branch was mispredicted -system.cpu3.commit.committed_per_cycle::samples 162652 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::mean 1.366697 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::stdev 1.912123 # Number of insts commited each cycle +system.cpu3.commit.commitCommittedInsts 244729 # The number of committed instructions +system.cpu3.commit.commitCommittedOps 244729 # The number of committed instructions +system.cpu3.commit.commitSquashedInsts 15046 # The number of squashed insts skipped by commit +system.cpu3.commit.commitNonSpecStalls 7736 # The number of times commit has been forced to stall to communicate backwards +system.cpu3.commit.branchMispredicts 1525 # The number of times a branch was mispredicted +system.cpu3.commit.committed_per_cycle::samples 174515 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::mean 1.402338 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::stdev 1.927125 # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::0 80351 49.40% 49.40% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::1 39430 24.24% 73.64% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::2 6019 3.70% 77.34% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::3 8502 5.23% 82.57% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::4 1632 1.00% 83.57% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::5 24257 14.91% 98.49% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::6 559 0.34% 98.83% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::7 1061 0.65% 99.48% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::8 841 0.52% 100.00% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::0 84328 48.32% 48.32% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::1 43439 24.89% 73.21% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::2 6199 3.55% 76.76% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::3 8632 4.95% 81.71% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::4 1540 0.88% 82.59% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::5 28042 16.07% 98.66% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::6 531 0.30% 98.97% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::7 992 0.57% 99.53% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::8 812 0.47% 100.00% # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::total 162652 # Number of insts commited each cycle -system.cpu3.commit.committedInsts 222296 # Number of instructions committed -system.cpu3.commit.committedOps 222296 # Number of ops (including micro ops) committed +system.cpu3.commit.committed_per_cycle::total 174515 # Number of insts commited each cycle +system.cpu3.commit.committedInsts 244729 # Number of instructions committed +system.cpu3.commit.committedOps 244729 # Number of ops (including micro ops) committed system.cpu3.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu3.commit.refs 89597 # Number of memory references committed -system.cpu3.commit.loads 61865 # Number of loads committed -system.cpu3.commit.membars 6925 # Number of memory barriers committed -system.cpu3.commit.branches 40618 # Number of branches committed +system.cpu3.commit.refs 100719 # Number of memory references committed +system.cpu3.commit.loads 69310 # Number of loads committed +system.cpu3.commit.membars 7019 # Number of memory barriers committed +system.cpu3.commit.branches 44389 # Number of branches committed system.cpu3.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu3.commit.int_insts 152335 # Number of committed integer instructions. +system.cpu3.commit.int_insts 167227 # Number of committed integer instructions. system.cpu3.commit.function_calls 322 # Number of function calls committed. -system.cpu3.commit.bw_lim_events 841 # number cycles where commit BW limit reached +system.cpu3.commit.bw_lim_events 812 # number cycles where commit BW limit reached system.cpu3.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu3.rob.rob_reads 392929 # The number of ROB reads -system.cpu3.rob.rob_writes 465356 # The number of ROB writes -system.cpu3.timesIdled 234 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu3.idleCycles 2770 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu3.quiesceCycles 34882 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu3.committedInsts 183965 # Number of Instructions Simulated -system.cpu3.committedOps 183965 # Number of Ops (including micro ops) Simulated -system.cpu3.committedInsts_total 183965 # Number of Instructions Simulated -system.cpu3.cpi 0.944484 # CPI: Cycles Per Instruction -system.cpu3.cpi_total 0.944484 # CPI: Total CPI of All Threads -system.cpu3.ipc 1.058779 # IPC: Instructions Per Cycle -system.cpu3.ipc_total 1.058779 # IPC: Total IPC of All Threads -system.cpu3.int_regfile_reads 330929 # number of integer regfile reads -system.cpu3.int_regfile_writes 155348 # number of integer regfile writes +system.cpu3.rob.rob_reads 432891 # The number of ROB reads +system.cpu3.rob.rob_writes 522404 # The number of ROB writes +system.cpu3.timesIdled 228 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu3.idleCycles 2970 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu3.quiesceCycles 35972 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu3.committedInsts 202534 # Number of Instructions Simulated +system.cpu3.committedOps 202534 # Number of Ops (including micro ops) Simulated +system.cpu3.committedInsts_total 202534 # Number of Instructions Simulated +system.cpu3.cpi 0.922472 # CPI: Cycles Per Instruction +system.cpu3.cpi_total 0.922472 # CPI: Total CPI of All Threads +system.cpu3.ipc 1.084043 # IPC: Instructions Per Cycle +system.cpu3.ipc_total 1.084043 # IPC: Total IPC of All Threads +system.cpu3.int_regfile_reads 369217 # number of integer regfile reads +system.cpu3.int_regfile_writes 172842 # number of integer regfile writes system.cpu3.fp_regfile_writes 64 # number of floating regfile writes -system.cpu3.misc_regfile_reads 92475 # number of misc regfile reads +system.cpu3.misc_regfile_reads 104868 # number of misc regfile reads system.cpu3.misc_regfile_writes 646 # number of misc regfile writes -system.cpu3.icache.replacements 318 # number of replacements -system.cpu3.icache.tagsinuse 80.006059 # Cycle average of tags in use -system.cpu3.icache.total_refs 22493 # Total number of references to valid blocks. -system.cpu3.icache.sampled_refs 426 # Sample count of references to valid blocks. -system.cpu3.icache.avg_refs 52.800469 # Average number of references to valid blocks. +system.cpu3.icache.replacements 320 # number of replacements +system.cpu3.icache.tagsinuse 85.923076 # Cycle average of tags in use +system.cpu3.icache.total_refs 23951 # Total number of references to valid blocks. +system.cpu3.icache.sampled_refs 432 # Sample count of references to valid blocks. +system.cpu3.icache.avg_refs 55.442130 # Average number of references to valid blocks. system.cpu3.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.icache.occ_blocks::cpu3.inst 80.006059 # Average occupied blocks per requestor -system.cpu3.icache.occ_percent::cpu3.inst 0.156262 # Average percentage of cache occupancy -system.cpu3.icache.occ_percent::total 0.156262 # Average percentage of cache occupancy -system.cpu3.icache.ReadReq_hits::cpu3.inst 22493 # number of ReadReq hits -system.cpu3.icache.ReadReq_hits::total 22493 # number of ReadReq hits -system.cpu3.icache.demand_hits::cpu3.inst 22493 # number of demand (read+write) hits -system.cpu3.icache.demand_hits::total 22493 # number of demand (read+write) hits -system.cpu3.icache.overall_hits::cpu3.inst 22493 # number of overall hits -system.cpu3.icache.overall_hits::total 22493 # number of overall hits -system.cpu3.icache.ReadReq_misses::cpu3.inst 466 # number of ReadReq misses -system.cpu3.icache.ReadReq_misses::total 466 # number of ReadReq misses -system.cpu3.icache.demand_misses::cpu3.inst 466 # number of demand (read+write) misses -system.cpu3.icache.demand_misses::total 466 # number of demand (read+write) misses -system.cpu3.icache.overall_misses::cpu3.inst 466 # number of overall misses -system.cpu3.icache.overall_misses::total 466 # number of overall misses -system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 6527000 # number of ReadReq miss cycles -system.cpu3.icache.ReadReq_miss_latency::total 6527000 # number of ReadReq miss cycles -system.cpu3.icache.demand_miss_latency::cpu3.inst 6527000 # number of demand (read+write) miss cycles -system.cpu3.icache.demand_miss_latency::total 6527000 # number of demand (read+write) miss cycles -system.cpu3.icache.overall_miss_latency::cpu3.inst 6527000 # number of overall miss cycles -system.cpu3.icache.overall_miss_latency::total 6527000 # number of overall miss cycles -system.cpu3.icache.ReadReq_accesses::cpu3.inst 22959 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.ReadReq_accesses::total 22959 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.demand_accesses::cpu3.inst 22959 # number of demand (read+write) accesses -system.cpu3.icache.demand_accesses::total 22959 # number of demand (read+write) accesses -system.cpu3.icache.overall_accesses::cpu3.inst 22959 # number of overall (read+write) accesses -system.cpu3.icache.overall_accesses::total 22959 # number of overall (read+write) accesses -system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.020297 # miss rate for ReadReq accesses -system.cpu3.icache.demand_miss_rate::cpu3.inst 0.020297 # miss rate for demand accesses -system.cpu3.icache.overall_miss_rate::cpu3.inst 0.020297 # miss rate for overall accesses -system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 14006.437768 # average ReadReq miss latency -system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 14006.437768 # average overall miss latency -system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 14006.437768 # average overall miss latency +system.cpu3.icache.occ_blocks::cpu3.inst 85.923076 # Average occupied blocks per requestor +system.cpu3.icache.occ_percent::cpu3.inst 0.167819 # Average percentage of cache occupancy +system.cpu3.icache.occ_percent::total 0.167819 # Average percentage of cache occupancy +system.cpu3.icache.ReadReq_hits::cpu3.inst 23951 # number of ReadReq hits +system.cpu3.icache.ReadReq_hits::total 23951 # number of ReadReq hits +system.cpu3.icache.demand_hits::cpu3.inst 23951 # number of demand (read+write) hits +system.cpu3.icache.demand_hits::total 23951 # number of demand (read+write) hits +system.cpu3.icache.overall_hits::cpu3.inst 23951 # number of overall hits +system.cpu3.icache.overall_hits::total 23951 # number of overall hits +system.cpu3.icache.ReadReq_misses::cpu3.inst 503 # number of ReadReq misses +system.cpu3.icache.ReadReq_misses::total 503 # number of ReadReq misses +system.cpu3.icache.demand_misses::cpu3.inst 503 # number of demand (read+write) misses +system.cpu3.icache.demand_misses::total 503 # number of demand (read+write) misses +system.cpu3.icache.overall_misses::cpu3.inst 503 # number of overall misses +system.cpu3.icache.overall_misses::total 503 # number of overall misses +system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 6843000 # number of ReadReq miss cycles +system.cpu3.icache.ReadReq_miss_latency::total 6843000 # number of ReadReq miss cycles +system.cpu3.icache.demand_miss_latency::cpu3.inst 6843000 # number of demand (read+write) miss cycles +system.cpu3.icache.demand_miss_latency::total 6843000 # number of demand (read+write) miss cycles +system.cpu3.icache.overall_miss_latency::cpu3.inst 6843000 # number of overall miss cycles +system.cpu3.icache.overall_miss_latency::total 6843000 # number of overall miss cycles +system.cpu3.icache.ReadReq_accesses::cpu3.inst 24454 # number of ReadReq accesses(hits+misses) +system.cpu3.icache.ReadReq_accesses::total 24454 # number of ReadReq accesses(hits+misses) +system.cpu3.icache.demand_accesses::cpu3.inst 24454 # number of demand (read+write) accesses +system.cpu3.icache.demand_accesses::total 24454 # number of demand (read+write) accesses +system.cpu3.icache.overall_accesses::cpu3.inst 24454 # number of overall (read+write) accesses +system.cpu3.icache.overall_accesses::total 24454 # number of overall (read+write) accesses +system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.020569 # miss rate for ReadReq accesses +system.cpu3.icache.demand_miss_rate::cpu3.inst 0.020569 # miss rate for demand accesses +system.cpu3.icache.overall_miss_rate::cpu3.inst 0.020569 # miss rate for overall accesses +system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 13604.373757 # average ReadReq miss latency +system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 13604.373757 # average overall miss latency +system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 13604.373757 # average overall miss latency system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1670,90 +1670,90 @@ system.cpu3.icache.avg_blocked_cycles::no_mshrs no_value system.cpu3.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu3.icache.fast_writes 0 # number of fast writes performed system.cpu3.icache.cache_copies 0 # number of cache copies performed -system.cpu3.icache.ReadReq_mshr_hits::cpu3.inst 40 # number of ReadReq MSHR hits -system.cpu3.icache.ReadReq_mshr_hits::total 40 # number of ReadReq MSHR hits -system.cpu3.icache.demand_mshr_hits::cpu3.inst 40 # number of demand (read+write) MSHR hits -system.cpu3.icache.demand_mshr_hits::total 40 # number of demand (read+write) MSHR hits -system.cpu3.icache.overall_mshr_hits::cpu3.inst 40 # number of overall MSHR hits -system.cpu3.icache.overall_mshr_hits::total 40 # number of overall MSHR hits -system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst 426 # number of ReadReq MSHR misses -system.cpu3.icache.ReadReq_mshr_misses::total 426 # number of ReadReq MSHR misses -system.cpu3.icache.demand_mshr_misses::cpu3.inst 426 # number of demand (read+write) MSHR misses -system.cpu3.icache.demand_mshr_misses::total 426 # number of demand (read+write) MSHR misses -system.cpu3.icache.overall_mshr_misses::cpu3.inst 426 # number of overall MSHR misses -system.cpu3.icache.overall_mshr_misses::total 426 # number of overall MSHR misses -system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 4833500 # number of ReadReq MSHR miss cycles -system.cpu3.icache.ReadReq_mshr_miss_latency::total 4833500 # number of ReadReq MSHR miss cycles -system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 4833500 # number of demand (read+write) MSHR miss cycles -system.cpu3.icache.demand_mshr_miss_latency::total 4833500 # number of demand (read+write) MSHR miss cycles -system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 4833500 # number of overall MSHR miss cycles -system.cpu3.icache.overall_mshr_miss_latency::total 4833500 # number of overall MSHR miss cycles -system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.018555 # mshr miss rate for ReadReq accesses -system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.018555 # mshr miss rate for demand accesses -system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.018555 # mshr miss rate for overall accesses -system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 11346.244131 # average ReadReq mshr miss latency -system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 11346.244131 # average overall mshr miss latency -system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 11346.244131 # average overall mshr miss latency +system.cpu3.icache.ReadReq_mshr_hits::cpu3.inst 71 # number of ReadReq MSHR hits +system.cpu3.icache.ReadReq_mshr_hits::total 71 # number of ReadReq MSHR hits +system.cpu3.icache.demand_mshr_hits::cpu3.inst 71 # number of demand (read+write) MSHR hits +system.cpu3.icache.demand_mshr_hits::total 71 # number of demand (read+write) MSHR hits +system.cpu3.icache.overall_mshr_hits::cpu3.inst 71 # number of overall MSHR hits +system.cpu3.icache.overall_mshr_hits::total 71 # number of overall MSHR hits +system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst 432 # number of ReadReq MSHR misses +system.cpu3.icache.ReadReq_mshr_misses::total 432 # number of ReadReq MSHR misses +system.cpu3.icache.demand_mshr_misses::cpu3.inst 432 # number of demand (read+write) MSHR misses +system.cpu3.icache.demand_mshr_misses::total 432 # number of demand (read+write) MSHR misses +system.cpu3.icache.overall_mshr_misses::cpu3.inst 432 # number of overall MSHR misses +system.cpu3.icache.overall_mshr_misses::total 432 # number of overall MSHR misses +system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 4912000 # number of ReadReq MSHR miss cycles +system.cpu3.icache.ReadReq_mshr_miss_latency::total 4912000 # number of ReadReq MSHR miss cycles +system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 4912000 # number of demand (read+write) MSHR miss cycles +system.cpu3.icache.demand_mshr_miss_latency::total 4912000 # number of demand (read+write) MSHR miss cycles +system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 4912000 # number of overall MSHR miss cycles +system.cpu3.icache.overall_mshr_miss_latency::total 4912000 # number of overall MSHR miss cycles +system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.017666 # mshr miss rate for ReadReq accesses +system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.017666 # mshr miss rate for demand accesses +system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.017666 # mshr miss rate for overall accesses +system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 11370.370370 # average ReadReq mshr miss latency +system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 11370.370370 # average overall mshr miss latency +system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 11370.370370 # average overall mshr miss latency system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu3.dcache.replacements 2 # number of replacements -system.cpu3.dcache.tagsinuse 23.407477 # Cycle average of tags in use -system.cpu3.dcache.total_refs 33584 # Total number of references to valid blocks. -system.cpu3.dcache.sampled_refs 29 # Sample count of references to valid blocks. -system.cpu3.dcache.avg_refs 1158.068966 # Average number of references to valid blocks. +system.cpu3.dcache.tagsinuse 25.290478 # Cycle average of tags in use +system.cpu3.dcache.total_refs 37716 # Total number of references to valid blocks. +system.cpu3.dcache.sampled_refs 30 # Sample count of references to valid blocks. +system.cpu3.dcache.avg_refs 1257.200000 # Average number of references to valid blocks. system.cpu3.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.dcache.occ_blocks::cpu3.data 23.407477 # Average occupied blocks per requestor -system.cpu3.dcache.occ_percent::cpu3.data 0.045718 # Average percentage of cache occupancy -system.cpu3.dcache.occ_percent::total 0.045718 # Average percentage of cache occupancy -system.cpu3.dcache.ReadReq_hits::cpu3.data 38412 # number of ReadReq hits -system.cpu3.dcache.ReadReq_hits::total 38412 # number of ReadReq hits -system.cpu3.dcache.WriteReq_hits::cpu3.data 27537 # number of WriteReq hits -system.cpu3.dcache.WriteReq_hits::total 27537 # number of WriteReq hits +system.cpu3.dcache.occ_blocks::cpu3.data 25.290478 # Average occupied blocks per requestor +system.cpu3.dcache.occ_percent::cpu3.data 0.049395 # Average percentage of cache occupancy +system.cpu3.dcache.occ_percent::total 0.049395 # Average percentage of cache occupancy +system.cpu3.dcache.ReadReq_hits::cpu3.data 42933 # number of ReadReq hits +system.cpu3.dcache.ReadReq_hits::total 42933 # number of ReadReq hits +system.cpu3.dcache.WriteReq_hits::cpu3.data 31189 # number of WriteReq hits +system.cpu3.dcache.WriteReq_hits::total 31189 # number of WriteReq hits system.cpu3.dcache.SwapReq_hits::cpu3.data 14 # number of SwapReq hits system.cpu3.dcache.SwapReq_hits::total 14 # number of SwapReq hits -system.cpu3.dcache.demand_hits::cpu3.data 65949 # number of demand (read+write) hits -system.cpu3.dcache.demand_hits::total 65949 # number of demand (read+write) hits -system.cpu3.dcache.overall_hits::cpu3.data 65949 # number of overall hits -system.cpu3.dcache.overall_hits::total 65949 # number of overall hits -system.cpu3.dcache.ReadReq_misses::cpu3.data 448 # number of ReadReq misses -system.cpu3.dcache.ReadReq_misses::total 448 # number of ReadReq misses -system.cpu3.dcache.WriteReq_misses::cpu3.data 125 # number of WriteReq misses -system.cpu3.dcache.WriteReq_misses::total 125 # number of WriteReq misses -system.cpu3.dcache.SwapReq_misses::cpu3.data 56 # number of SwapReq misses -system.cpu3.dcache.SwapReq_misses::total 56 # number of SwapReq misses -system.cpu3.dcache.demand_misses::cpu3.data 573 # number of demand (read+write) misses -system.cpu3.dcache.demand_misses::total 573 # number of demand (read+write) misses -system.cpu3.dcache.overall_misses::cpu3.data 573 # number of overall misses -system.cpu3.dcache.overall_misses::total 573 # number of overall misses -system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 9358000 # number of ReadReq miss cycles -system.cpu3.dcache.ReadReq_miss_latency::total 9358000 # number of ReadReq miss cycles -system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 2911000 # number of WriteReq miss cycles -system.cpu3.dcache.WriteReq_miss_latency::total 2911000 # number of WriteReq miss cycles -system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 1350500 # number of SwapReq miss cycles -system.cpu3.dcache.SwapReq_miss_latency::total 1350500 # number of SwapReq miss cycles -system.cpu3.dcache.demand_miss_latency::cpu3.data 12269000 # number of demand (read+write) miss cycles -system.cpu3.dcache.demand_miss_latency::total 12269000 # number of demand (read+write) miss cycles -system.cpu3.dcache.overall_miss_latency::cpu3.data 12269000 # number of overall miss cycles -system.cpu3.dcache.overall_miss_latency::total 12269000 # number of overall miss cycles -system.cpu3.dcache.ReadReq_accesses::cpu3.data 38860 # number of ReadReq accesses(hits+misses) -system.cpu3.dcache.ReadReq_accesses::total 38860 # number of ReadReq accesses(hits+misses) -system.cpu3.dcache.WriteReq_accesses::cpu3.data 27662 # number of WriteReq accesses(hits+misses) -system.cpu3.dcache.WriteReq_accesses::total 27662 # number of WriteReq accesses(hits+misses) -system.cpu3.dcache.SwapReq_accesses::cpu3.data 70 # number of SwapReq accesses(hits+misses) -system.cpu3.dcache.SwapReq_accesses::total 70 # number of SwapReq accesses(hits+misses) -system.cpu3.dcache.demand_accesses::cpu3.data 66522 # number of demand (read+write) accesses -system.cpu3.dcache.demand_accesses::total 66522 # number of demand (read+write) accesses -system.cpu3.dcache.overall_accesses::cpu3.data 66522 # number of overall (read+write) accesses -system.cpu3.dcache.overall_accesses::total 66522 # number of overall (read+write) accesses -system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.011529 # miss rate for ReadReq accesses -system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.004519 # miss rate for WriteReq accesses -system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.800000 # miss rate for SwapReq accesses -system.cpu3.dcache.demand_miss_rate::cpu3.data 0.008614 # miss rate for demand accesses -system.cpu3.dcache.overall_miss_rate::cpu3.data 0.008614 # miss rate for overall accesses -system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 20888.392857 # average ReadReq miss latency -system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 23288 # average WriteReq miss latency -system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 24116.071429 # average SwapReq miss latency -system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 21411.867365 # average overall miss latency -system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 21411.867365 # average overall miss latency +system.cpu3.dcache.demand_hits::cpu3.data 74122 # number of demand (read+write) hits +system.cpu3.dcache.demand_hits::total 74122 # number of demand (read+write) hits +system.cpu3.dcache.overall_hits::cpu3.data 74122 # number of overall hits +system.cpu3.dcache.overall_hits::total 74122 # number of overall hits +system.cpu3.dcache.ReadReq_misses::cpu3.data 420 # number of ReadReq misses +system.cpu3.dcache.ReadReq_misses::total 420 # number of ReadReq misses +system.cpu3.dcache.WriteReq_misses::cpu3.data 149 # number of WriteReq misses +system.cpu3.dcache.WriteReq_misses::total 149 # number of WriteReq misses +system.cpu3.dcache.SwapReq_misses::cpu3.data 57 # number of SwapReq misses +system.cpu3.dcache.SwapReq_misses::total 57 # number of SwapReq misses +system.cpu3.dcache.demand_misses::cpu3.data 569 # number of demand (read+write) misses +system.cpu3.dcache.demand_misses::total 569 # number of demand (read+write) misses +system.cpu3.dcache.overall_misses::cpu3.data 569 # number of overall misses +system.cpu3.dcache.overall_misses::total 569 # number of overall misses +system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 8616000 # number of ReadReq miss cycles +system.cpu3.dcache.ReadReq_miss_latency::total 8616000 # number of ReadReq miss cycles +system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 3007500 # number of WriteReq miss cycles +system.cpu3.dcache.WriteReq_miss_latency::total 3007500 # number of WriteReq miss cycles +system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 1198000 # number of SwapReq miss cycles +system.cpu3.dcache.SwapReq_miss_latency::total 1198000 # number of SwapReq miss cycles +system.cpu3.dcache.demand_miss_latency::cpu3.data 11623500 # number of demand (read+write) miss cycles +system.cpu3.dcache.demand_miss_latency::total 11623500 # number of demand (read+write) miss cycles +system.cpu3.dcache.overall_miss_latency::cpu3.data 11623500 # number of overall miss cycles +system.cpu3.dcache.overall_miss_latency::total 11623500 # number of overall miss cycles +system.cpu3.dcache.ReadReq_accesses::cpu3.data 43353 # number of ReadReq accesses(hits+misses) +system.cpu3.dcache.ReadReq_accesses::total 43353 # number of ReadReq accesses(hits+misses) +system.cpu3.dcache.WriteReq_accesses::cpu3.data 31338 # number of WriteReq accesses(hits+misses) +system.cpu3.dcache.WriteReq_accesses::total 31338 # number of WriteReq accesses(hits+misses) +system.cpu3.dcache.SwapReq_accesses::cpu3.data 71 # number of SwapReq accesses(hits+misses) +system.cpu3.dcache.SwapReq_accesses::total 71 # number of SwapReq accesses(hits+misses) +system.cpu3.dcache.demand_accesses::cpu3.data 74691 # number of demand (read+write) accesses +system.cpu3.dcache.demand_accesses::total 74691 # number of demand (read+write) accesses +system.cpu3.dcache.overall_accesses::cpu3.data 74691 # number of overall (read+write) accesses +system.cpu3.dcache.overall_accesses::total 74691 # number of overall (read+write) accesses +system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.009688 # miss rate for ReadReq accesses +system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.004755 # miss rate for WriteReq accesses +system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.802817 # miss rate for SwapReq accesses +system.cpu3.dcache.demand_miss_rate::cpu3.data 0.007618 # miss rate for demand accesses +system.cpu3.dcache.overall_miss_rate::cpu3.data 0.007618 # miss rate for overall accesses +system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 20514.285714 # average ReadReq miss latency +system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 20184.563758 # average WriteReq miss latency +system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 21017.543860 # average SwapReq miss latency +system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 20427.943761 # average overall miss latency +system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 20427.943761 # average overall miss latency system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1764,222 +1764,222 @@ system.cpu3.dcache.fast_writes 0 # nu system.cpu3.dcache.cache_copies 0 # number of cache copies performed system.cpu3.dcache.writebacks::writebacks 1 # number of writebacks system.cpu3.dcache.writebacks::total 1 # number of writebacks -system.cpu3.dcache.ReadReq_mshr_hits::cpu3.data 279 # number of ReadReq MSHR hits -system.cpu3.dcache.ReadReq_mshr_hits::total 279 # number of ReadReq MSHR hits -system.cpu3.dcache.WriteReq_mshr_hits::cpu3.data 17 # number of WriteReq MSHR hits -system.cpu3.dcache.WriteReq_mshr_hits::total 17 # number of WriteReq MSHR hits -system.cpu3.dcache.demand_mshr_hits::cpu3.data 296 # number of demand (read+write) MSHR hits -system.cpu3.dcache.demand_mshr_hits::total 296 # number of demand (read+write) MSHR hits -system.cpu3.dcache.overall_mshr_hits::cpu3.data 296 # number of overall MSHR hits -system.cpu3.dcache.overall_mshr_hits::total 296 # number of overall MSHR hits -system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 169 # number of ReadReq MSHR misses -system.cpu3.dcache.ReadReq_mshr_misses::total 169 # number of ReadReq MSHR misses -system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 108 # number of WriteReq MSHR misses -system.cpu3.dcache.WriteReq_mshr_misses::total 108 # number of WriteReq MSHR misses -system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 56 # number of SwapReq MSHR misses -system.cpu3.dcache.SwapReq_mshr_misses::total 56 # number of SwapReq MSHR misses -system.cpu3.dcache.demand_mshr_misses::cpu3.data 277 # number of demand (read+write) MSHR misses -system.cpu3.dcache.demand_mshr_misses::total 277 # number of demand (read+write) MSHR misses -system.cpu3.dcache.overall_mshr_misses::cpu3.data 277 # number of overall MSHR misses -system.cpu3.dcache.overall_mshr_misses::total 277 # number of overall MSHR misses -system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 2218000 # number of ReadReq MSHR miss cycles -system.cpu3.dcache.ReadReq_mshr_miss_latency::total 2218000 # number of ReadReq MSHR miss cycles -system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1624500 # number of WriteReq MSHR miss cycles -system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1624500 # number of WriteReq MSHR miss cycles -system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 1182500 # number of SwapReq MSHR miss cycles -system.cpu3.dcache.SwapReq_mshr_miss_latency::total 1182500 # number of SwapReq MSHR miss cycles -system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 3842500 # number of demand (read+write) MSHR miss cycles -system.cpu3.dcache.demand_mshr_miss_latency::total 3842500 # number of demand (read+write) MSHR miss cycles -system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 3842500 # number of overall MSHR miss cycles -system.cpu3.dcache.overall_mshr_miss_latency::total 3842500 # number of overall MSHR miss cycles -system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.004349 # mshr miss rate for ReadReq accesses -system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.003904 # mshr miss rate for WriteReq accesses -system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.800000 # mshr miss rate for SwapReq accesses -system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.004164 # mshr miss rate for demand accesses -system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.004164 # mshr miss rate for overall accesses -system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 13124.260355 # average ReadReq mshr miss latency -system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 15041.666667 # average WriteReq mshr miss latency -system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 21116.071429 # average SwapReq mshr miss latency -system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 13871.841155 # average overall mshr miss latency -system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 13871.841155 # average overall mshr miss latency +system.cpu3.dcache.ReadReq_mshr_hits::cpu3.data 257 # number of ReadReq MSHR hits +system.cpu3.dcache.ReadReq_mshr_hits::total 257 # number of ReadReq MSHR hits +system.cpu3.dcache.WriteReq_mshr_hits::cpu3.data 45 # number of WriteReq MSHR hits +system.cpu3.dcache.WriteReq_mshr_hits::total 45 # number of WriteReq MSHR hits +system.cpu3.dcache.demand_mshr_hits::cpu3.data 302 # number of demand (read+write) MSHR hits +system.cpu3.dcache.demand_mshr_hits::total 302 # number of demand (read+write) MSHR hits +system.cpu3.dcache.overall_mshr_hits::cpu3.data 302 # number of overall MSHR hits +system.cpu3.dcache.overall_mshr_hits::total 302 # number of overall MSHR hits +system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 163 # number of ReadReq MSHR misses +system.cpu3.dcache.ReadReq_mshr_misses::total 163 # number of ReadReq MSHR misses +system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 104 # number of WriteReq MSHR misses +system.cpu3.dcache.WriteReq_mshr_misses::total 104 # number of WriteReq MSHR misses +system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 57 # number of SwapReq MSHR misses +system.cpu3.dcache.SwapReq_mshr_misses::total 57 # number of SwapReq MSHR misses +system.cpu3.dcache.demand_mshr_misses::cpu3.data 267 # number of demand (read+write) MSHR misses +system.cpu3.dcache.demand_mshr_misses::total 267 # number of demand (read+write) MSHR misses +system.cpu3.dcache.overall_mshr_misses::cpu3.data 267 # number of overall MSHR misses +system.cpu3.dcache.overall_mshr_misses::total 267 # number of overall MSHR misses +system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 2151000 # number of ReadReq MSHR miss cycles +system.cpu3.dcache.ReadReq_mshr_miss_latency::total 2151000 # number of ReadReq MSHR miss cycles +system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1621000 # number of WriteReq MSHR miss cycles +system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1621000 # number of WriteReq MSHR miss cycles +system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 1027000 # number of SwapReq MSHR miss cycles +system.cpu3.dcache.SwapReq_mshr_miss_latency::total 1027000 # number of SwapReq MSHR miss cycles +system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 3772000 # number of demand (read+write) MSHR miss cycles +system.cpu3.dcache.demand_mshr_miss_latency::total 3772000 # number of demand (read+write) MSHR miss cycles +system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 3772000 # number of overall MSHR miss cycles +system.cpu3.dcache.overall_mshr_miss_latency::total 3772000 # number of overall MSHR miss cycles +system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.003760 # mshr miss rate for ReadReq accesses +system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.003319 # mshr miss rate for WriteReq accesses +system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.802817 # mshr miss rate for SwapReq accesses +system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.003575 # mshr miss rate for demand accesses +system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.003575 # mshr miss rate for overall accesses +system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 13196.319018 # average ReadReq mshr miss latency +system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 15586.538462 # average WriteReq mshr miss latency +system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 18017.543860 # average SwapReq mshr miss latency +system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 14127.340824 # average overall mshr miss latency +system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 14127.340824 # average overall mshr miss latency system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.l2c.replacements 0 # number of replacements -system.l2c.tagsinuse 428.231635 # Cycle average of tags in use -system.l2c.total_refs 1446 # Total number of references to valid blocks. -system.l2c.sampled_refs 527 # Sample count of references to valid blocks. -system.l2c.avg_refs 2.743833 # Average number of references to valid blocks. +system.l2c.tagsinuse 441.136869 # Cycle average of tags in use +system.l2c.total_refs 1471 # Total number of references to valid blocks. +system.l2c.sampled_refs 544 # Sample count of references to valid blocks. +system.l2c.avg_refs 2.704044 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 4.965624 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 287.776309 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 59.398265 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 10.494682 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 0.774865 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu2.inst 57.571117 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu2.data 5.683514 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu3.inst 0.828706 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu3.data 0.738553 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.000076 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.004391 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.000906 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.000160 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.data 0.000012 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu2.inst 0.000878 # Average percentage of cache occupancy +system.l2c.occ_blocks::writebacks 4.878414 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.inst 294.783080 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.data 59.595754 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.inst 9.493651 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.data 0.732946 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu2.inst 64.319288 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu2.data 5.723296 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu3.inst 0.834559 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu3.data 0.775880 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.000074 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.inst 0.004498 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.data 0.000909 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.inst 0.000145 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.data 0.000011 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu2.inst 0.000981 # Average percentage of cache occupancy system.l2c.occ_percent::cpu2.data 0.000087 # Average percentage of cache occupancy system.l2c.occ_percent::cpu3.inst 0.000013 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu3.data 0.000011 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.006534 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.inst 228 # number of ReadReq hits +system.l2c.occ_percent::cpu3.data 0.000012 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.006731 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0.inst 231 # number of ReadReq hits system.l2c.ReadReq_hits::cpu0.data 5 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 412 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 12 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.inst 349 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 420 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 13 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.inst 355 # number of ReadReq hits system.l2c.ReadReq_hits::cpu2.data 7 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu3.inst 424 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu3.data 12 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1449 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu3.inst 430 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu3.data 13 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1474 # number of ReadReq hits system.l2c.Writeback_hits::writebacks 9 # number of Writeback hits system.l2c.Writeback_hits::total 9 # number of Writeback hits system.l2c.UpgradeReq_hits::cpu0.data 3 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 3 # number of UpgradeReq hits -system.l2c.demand_hits::cpu0.inst 228 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 231 # number of demand (read+write) hits system.l2c.demand_hits::cpu0.data 5 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 412 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 12 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.inst 349 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 420 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 13 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.inst 355 # number of demand (read+write) hits system.l2c.demand_hits::cpu2.data 7 # number of demand (read+write) hits -system.l2c.demand_hits::cpu3.inst 424 # number of demand (read+write) hits -system.l2c.demand_hits::cpu3.data 12 # number of demand (read+write) hits -system.l2c.demand_hits::total 1449 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.inst 228 # number of overall hits +system.l2c.demand_hits::cpu3.inst 430 # number of demand (read+write) hits +system.l2c.demand_hits::cpu3.data 13 # number of demand (read+write) hits +system.l2c.demand_hits::total 1474 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.inst 231 # number of overall hits system.l2c.overall_hits::cpu0.data 5 # number of overall hits -system.l2c.overall_hits::cpu1.inst 412 # number of overall hits -system.l2c.overall_hits::cpu1.data 12 # number of overall hits -system.l2c.overall_hits::cpu2.inst 349 # number of overall hits +system.l2c.overall_hits::cpu1.inst 420 # number of overall hits +system.l2c.overall_hits::cpu1.data 13 # number of overall hits +system.l2c.overall_hits::cpu2.inst 355 # number of overall hits system.l2c.overall_hits::cpu2.data 7 # number of overall hits -system.l2c.overall_hits::cpu3.inst 424 # number of overall hits -system.l2c.overall_hits::cpu3.data 12 # number of overall hits -system.l2c.overall_hits::total 1449 # number of overall hits -system.l2c.ReadReq_misses::cpu0.inst 354 # number of ReadReq misses +system.l2c.overall_hits::cpu3.inst 430 # number of overall hits +system.l2c.overall_hits::cpu3.data 13 # number of overall hits +system.l2c.overall_hits::total 1474 # number of overall hits +system.l2c.ReadReq_misses::cpu0.inst 363 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.data 75 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.inst 15 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.data 1 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.inst 78 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu2.inst 85 # number of ReadReq misses system.l2c.ReadReq_misses::cpu2.data 7 # number of ReadReq misses system.l2c.ReadReq_misses::cpu3.inst 2 # number of ReadReq misses system.l2c.ReadReq_misses::cpu3.data 1 # number of ReadReq misses -system.l2c.ReadReq_misses::total 533 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 21 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 22 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu2.data 22 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu3.data 22 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 87 # number of UpgradeReq misses +system.l2c.ReadReq_misses::total 549 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 22 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 21 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu2.data 17 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu3.data 20 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 80 # number of UpgradeReq misses system.l2c.ReadExReq_misses::cpu0.data 94 # number of ReadExReq misses system.l2c.ReadExReq_misses::cpu1.data 12 # number of ReadExReq misses system.l2c.ReadExReq_misses::cpu2.data 13 # number of ReadExReq misses system.l2c.ReadExReq_misses::cpu3.data 12 # number of ReadExReq misses system.l2c.ReadExReq_misses::total 131 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.inst 354 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 363 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.data 169 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.inst 15 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.data 13 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.inst 78 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2.inst 85 # number of demand (read+write) misses system.l2c.demand_misses::cpu2.data 20 # number of demand (read+write) misses system.l2c.demand_misses::cpu3.inst 2 # number of demand (read+write) misses system.l2c.demand_misses::cpu3.data 13 # number of demand (read+write) misses -system.l2c.demand_misses::total 664 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.inst 354 # number of overall misses +system.l2c.demand_misses::total 680 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.inst 363 # number of overall misses system.l2c.overall_misses::cpu0.data 169 # number of overall misses system.l2c.overall_misses::cpu1.inst 15 # number of overall misses system.l2c.overall_misses::cpu1.data 13 # number of overall misses -system.l2c.overall_misses::cpu2.inst 78 # number of overall misses +system.l2c.overall_misses::cpu2.inst 85 # number of overall misses system.l2c.overall_misses::cpu2.data 20 # number of overall misses system.l2c.overall_misses::cpu3.inst 2 # number of overall misses system.l2c.overall_misses::cpu3.data 13 # number of overall misses -system.l2c.overall_misses::total 664 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.inst 18441500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 3931500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 745000 # number of ReadReq miss cycles +system.l2c.overall_misses::total 680 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu0.inst 18919500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.data 3929500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.inst 744500 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu1.data 52500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2.inst 4016500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2.data 365500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu3.inst 96000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu2.inst 4376000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu2.data 366000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu3.inst 99500 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu3.data 52500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 27701000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 28540000 # number of ReadReq miss cycles system.l2c.UpgradeReq_miss_latency::cpu1.data 52500 # number of UpgradeReq miss cycles system.l2c.UpgradeReq_miss_latency::cpu2.data 52500 # number of UpgradeReq miss cycles system.l2c.UpgradeReq_miss_latency::cpu3.data 52500 # number of UpgradeReq miss cycles system.l2c.UpgradeReq_miss_latency::total 157500 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 4940000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 4939500 # number of ReadExReq miss cycles system.l2c.ReadExReq_miss_latency::cpu1.data 627500 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu2.data 683000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu2.data 680500 # number of ReadExReq miss cycles system.l2c.ReadExReq_miss_latency::cpu3.data 627500 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 6878000 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.inst 18441500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 8871500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 745000 # number of demand (read+write) miss cycles +system.l2c.ReadExReq_miss_latency::total 6875000 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu0.inst 18919500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 8869000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 744500 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu1.data 680000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.inst 4016500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.data 1048500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu3.inst 96000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.inst 4376000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.data 1046500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu3.inst 99500 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu3.data 680000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 34579000 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.inst 18441500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 8871500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 745000 # number of overall miss cycles +system.l2c.demand_miss_latency::total 35415000 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.inst 18919500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 8869000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 744500 # number of overall miss cycles system.l2c.overall_miss_latency::cpu1.data 680000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.inst 4016500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.data 1048500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu3.inst 96000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.inst 4376000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.data 1046500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu3.inst 99500 # number of overall miss cycles system.l2c.overall_miss_latency::cpu3.data 680000 # number of overall miss cycles -system.l2c.overall_miss_latency::total 34579000 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.inst 582 # number of ReadReq accesses(hits+misses) +system.l2c.overall_miss_latency::total 35415000 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.inst 594 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu0.data 80 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 427 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 13 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.inst 427 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 435 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 14 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2.inst 440 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu2.data 14 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu3.inst 426 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu3.data 13 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 1982 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu3.inst 432 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu3.data 14 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2023 # number of ReadReq accesses(hits+misses) system.l2c.Writeback_accesses::writebacks 9 # number of Writeback accesses(hits+misses) system.l2c.Writeback_accesses::total 9 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 24 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 22 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu2.data 22 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu3.data 22 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 90 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 25 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 21 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu2.data 17 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu3.data 20 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 83 # number of UpgradeReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu0.data 94 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu1.data 12 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu2.data 13 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu3.data 12 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::total 131 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.inst 582 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 594 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu0.data 174 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 427 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 25 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.inst 427 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 435 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 26 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.inst 440 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu2.data 27 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu3.inst 426 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu3.data 25 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2113 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 582 # number of overall (read+write) accesses +system.l2c.demand_accesses::cpu3.inst 432 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu3.data 26 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 2154 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 594 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu0.data 174 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 427 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 25 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.inst 427 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 435 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 26 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.inst 440 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu2.data 27 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu3.inst 426 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu3.data 25 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2113 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.608247 # miss rate for ReadReq accesses +system.l2c.overall_accesses::cpu3.inst 432 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu3.data 26 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 2154 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.611111 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu0.data 0.937500 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.035129 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.076923 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2.inst 0.182670 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.034483 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.071429 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2.inst 0.193182 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu2.data 0.500000 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu3.inst 0.004695 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu3.data 0.076923 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.875000 # miss rate for UpgradeReq accesses +system.l2c.ReadReq_miss_rate::cpu3.inst 0.004630 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu3.data 0.071429 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.880000 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::cpu2.data 1 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::cpu3.data 1 # miss rate for UpgradeReq accesses @@ -1987,52 +1987,52 @@ system.l2c.ReadExReq_miss_rate::cpu0.data 1 # m system.l2c.ReadExReq_miss_rate::cpu1.data 1 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::cpu3.data 1 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.inst 0.608247 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.611111 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu0.data 0.971264 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.035129 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.520000 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.inst 0.182670 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.034483 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.500000 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.inst 0.193182 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu2.data 0.740741 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu3.inst 0.004695 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu3.data 0.520000 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.inst 0.608247 # miss rate for overall accesses +system.l2c.demand_miss_rate::cpu3.inst 0.004630 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu3.data 0.500000 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.inst 0.611111 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu0.data 0.971264 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.035129 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.520000 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.inst 0.182670 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.034483 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.500000 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.inst 0.193182 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu2.data 0.740741 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu3.inst 0.004695 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu3.data 0.520000 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52094.632768 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.data 52420 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 49666.666667 # average ReadReq miss latency +system.l2c.overall_miss_rate::cpu3.inst 0.004630 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu3.data 0.500000 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52119.834711 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.data 52393.333333 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 49633.333333 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu1.data 52500 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2.inst 51493.589744 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2.data 52214.285714 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu3.inst 48000 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2.inst 51482.352941 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2.data 52285.714286 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu3.inst 49750 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu3.data 52500 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 2386.363636 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 2386.363636 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu3.data 2386.363636 # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52553.191489 # average ReadExReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 2500 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 3088.235294 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu3.data 2625 # average UpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52547.872340 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::cpu1.data 52291.666667 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu2.data 52538.461538 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu2.data 52346.153846 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::cpu3.data 52291.666667 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 52094.632768 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 52494.082840 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 49666.666667 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 52119.834711 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 52479.289941 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 49633.333333 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu1.data 52307.692308 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.inst 51493.589744 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.data 52425 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu3.inst 48000 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.inst 51482.352941 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.data 52325 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu3.inst 49750 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu3.data 52307.692308 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 52094.632768 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 52494.082840 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 49666.666667 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 52119.834711 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 52479.289941 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 49633.333333 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu1.data 52307.692308 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.inst 51493.589744 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.data 52425 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu3.inst 48000 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.inst 51482.352941 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.data 52325 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu3.inst 49750 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu3.data 52307.692308 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked @@ -2042,104 +2042,101 @@ system.l2c.avg_blocked_cycles::no_mshrs no_value # av system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.ReadReq_mshr_hits::cpu0.inst 1 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::cpu1.inst 1 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::cpu2.inst 5 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::cpu3.inst 1 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::total 8 # number of ReadReq MSHR hits -system.l2c.demand_mshr_hits::cpu0.inst 1 # number of demand (read+write) MSHR hits +system.l2c.ReadReq_mshr_hits::total 7 # number of ReadReq MSHR hits system.l2c.demand_mshr_hits::cpu1.inst 1 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_hits::cpu2.inst 5 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_hits::cpu3.inst 1 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::total 8 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits::cpu0.inst 1 # number of overall MSHR hits +system.l2c.demand_mshr_hits::total 7 # number of demand (read+write) MSHR hits system.l2c.overall_mshr_hits::cpu1.inst 1 # number of overall MSHR hits system.l2c.overall_mshr_hits::cpu2.inst 5 # number of overall MSHR hits system.l2c.overall_mshr_hits::cpu3.inst 1 # number of overall MSHR hits -system.l2c.overall_mshr_hits::total 8 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses::cpu0.inst 353 # number of ReadReq MSHR misses +system.l2c.overall_mshr_hits::total 7 # number of overall MSHR hits +system.l2c.ReadReq_mshr_misses::cpu0.inst 363 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu0.data 75 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu1.inst 14 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu1.data 1 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu2.inst 73 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu2.inst 80 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu2.data 7 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu3.inst 1 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu3.data 1 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 525 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.data 21 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 22 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu2.data 22 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu3.data 22 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 87 # number of UpgradeReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 542 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0.data 22 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 21 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu2.data 17 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu3.data 20 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 80 # number of UpgradeReq MSHR misses system.l2c.ReadExReq_mshr_misses::cpu0.data 94 # number of ReadExReq MSHR misses system.l2c.ReadExReq_mshr_misses::cpu1.data 12 # number of ReadExReq MSHR misses system.l2c.ReadExReq_mshr_misses::cpu2.data 13 # number of ReadExReq MSHR misses system.l2c.ReadExReq_mshr_misses::cpu3.data 12 # number of ReadExReq MSHR misses system.l2c.ReadExReq_mshr_misses::total 131 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 353 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 363 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu0.data 169 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu1.inst 14 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu1.data 13 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2.inst 73 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2.inst 80 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu2.data 20 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu3.inst 1 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu3.data 13 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 656 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 353 # number of overall MSHR misses +system.l2c.demand_mshr_misses::total 673 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0.inst 363 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu0.data 169 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu1.inst 14 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu1.data 13 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2.inst 73 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2.inst 80 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu2.data 20 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu3.inst 1 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu3.data 13 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 656 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 14091500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.data 3019000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 561000 # number of ReadReq MSHR miss cycles +system.l2c.overall_mshr_misses::total 673 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 14492500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.data 3016500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 560000 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::cpu1.data 40000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 2922000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 3200000 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::cpu2.data 280000 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::cpu3.inst 40000 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::cpu3.data 40000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 20993500 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 840000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 880000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 880000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data 880000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 3480000 # number of UpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 3792000 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 481000 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 524500 # number of ReadExReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 21669000 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 880000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 840000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 680000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data 800000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 3200000 # number of UpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 3793000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 481500 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 522500 # number of ReadExReq MSHR miss cycles system.l2c.ReadExReq_mshr_miss_latency::cpu3.data 481500 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 5279000 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 14091500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 6811000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 561000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 521000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2.inst 2922000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2.data 804500 # number of demand (read+write) MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 5278500 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 14492500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 6809500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 560000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 521500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.inst 3200000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.data 802500 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu3.inst 40000 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu3.data 521500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 26272500 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 14091500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 6811000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 561000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 521000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.inst 2922000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.data 804500 # number of overall MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 26947500 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 14492500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 6809500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 560000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 521500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.inst 3200000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.data 802500 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu3.inst 40000 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu3.data 521500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 26272500 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.606529 # mshr miss rate for ReadReq accesses +system.l2c.overall_mshr_miss_latency::total 26947500 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.611111 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.937500 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.032787 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.076923 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.170960 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.032184 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.071429 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.181818 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.500000 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu3.inst 0.002347 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu3.data 0.076923 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.875000 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu3.inst 0.002315 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu3.data 0.071429 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.880000 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for UpgradeReq accesses @@ -2147,27 +2144,27 @@ system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 1 system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.606529 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.611111 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu0.data 0.971264 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.032787 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.520000 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.inst 0.170960 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.032184 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.500000 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.inst 0.181818 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu2.data 0.740741 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu3.inst 0.002347 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu3.data 0.520000 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.606529 # mshr miss rate for overall accesses +system.l2c.demand_mshr_miss_rate::cpu3.inst 0.002315 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3.data 0.500000 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.611111 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu0.data 0.971264 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.032787 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.520000 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.inst 0.170960 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.032184 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.500000 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.inst 0.181818 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu2.data 0.740741 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu3.inst 0.002347 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu3.data 0.520000 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 39919.263456 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40253.333333 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40071.428571 # average ReadReq mshr miss latency +system.l2c.overall_mshr_miss_rate::cpu3.inst 0.002315 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3.data 0.500000 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 39924.242424 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40220 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40000 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 40027.397260 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 40000 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 40000 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst 40000 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.data 40000 # average ReadReq mshr miss latency @@ -2175,24 +2172,24 @@ system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40000 system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40000 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 40000 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 40000 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40340.425532 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40083.333333 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 40346.153846 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40351.063830 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40125 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 40192.307692 # average ReadExReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 40125 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 39919.263456 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40301.775148 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40071.428571 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40076.923077 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 40027.397260 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.data 40225 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 39924.242424 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40292.899408 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40115.384615 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 40000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 40125 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 40000 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu3.data 40115.384615 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 39919.263456 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40301.775148 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40071.428571 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40076.923077 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 40027.397260 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.data 40225 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 39924.242424 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40292.899408 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40115.384615 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 40000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 40125 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 40000 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu3.data 40115.384615 # average overall mshr miss latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate |