diff options
| author | Jason Lowe-Power <jason@lowepower.com> | 2016-11-30 17:12:59 -0500 |
|---|---|---|
| committer | Jason Lowe-Power <jason@lowepower.com> | 2016-11-30 17:12:59 -0500 |
| commit | 752033140228c790e51954bd8ccd3728f4dd7e08 (patch) | |
| tree | 3e3858dd900fed04d38cd331feadc140bec2e530 /tests/quick/se | |
| parent | 33683bd087c2009db588844e8fa89b454a5c3d77 (diff) | |
| download | gem5-752033140228c790e51954bd8ccd3728f4dd7e08.tar.xz | |
tests: Regression stats updated for recent patches
Diffstat (limited to 'tests/quick/se')
165 files changed, 67988 insertions, 4403 deletions
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/config.ini index dc66b2c5c..2a35cf845 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/config.ini @@ -177,10 +177,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=false max_miss_count=0 mshrs=4 @@ -194,6 +194,7 @@ response_latency=2 sequential_access=false size=262144 system=system +tag_latency=2 tags=system.cpu.dcache.tags tgts_per_mshr=20 write_buffers=8 @@ -206,15 +207,16 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=262144 +tag_latency=2 [system.cpu.dtb] type=AlphaTLB @@ -292,10 +294,10 @@ pipelined=true [system.cpu.fuPool.FUList3] type=FUDesc -children=opList0 opList1 opList2 +children=opList0 opList1 opList2 opList3 opList4 count=2 eventq_index=0 -opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 +opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 system.cpu.fuPool.FUList3.opList3 system.cpu.fuPool.FUList3.opList4 [system.cpu.fuPool.FUList3.opList0] type=OpDesc @@ -307,11 +309,25 @@ pipelined=true [system.cpu.fuPool.FUList3.opList1] type=OpDesc eventq_index=0 +opClass=FloatMultAcc +opLat=5 +pipelined=true + +[system.cpu.fuPool.FUList3.opList2] +type=OpDesc +eventq_index=0 +opClass=FloatMisc +opLat=3 +pipelined=true + +[system.cpu.fuPool.FUList3.opList3] +type=OpDesc +eventq_index=0 opClass=FloatDiv opLat=12 pipelined=false -[system.cpu.fuPool.FUList3.opList2] +[system.cpu.fuPool.FUList3.opList4] type=OpDesc eventq_index=0 opClass=FloatSqrt @@ -320,18 +336,25 @@ pipelined=false [system.cpu.fuPool.FUList4] type=FUDesc -children=opList +children=opList0 opList1 count=0 eventq_index=0 -opList=system.cpu.fuPool.FUList4.opList +opList=system.cpu.fuPool.FUList4.opList0 system.cpu.fuPool.FUList4.opList1 -[system.cpu.fuPool.FUList4.opList] +[system.cpu.fuPool.FUList4.opList0] type=OpDesc eventq_index=0 opClass=MemRead opLat=1 pipelined=true +[system.cpu.fuPool.FUList4.opList1] +type=OpDesc +eventq_index=0 +opClass=FloatMemRead +opLat=1 +pipelined=true + [system.cpu.fuPool.FUList5] type=FUDesc children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 @@ -481,24 +504,31 @@ pipelined=true [system.cpu.fuPool.FUList6] type=FUDesc -children=opList +children=opList0 opList1 count=0 eventq_index=0 -opList=system.cpu.fuPool.FUList6.opList +opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1 -[system.cpu.fuPool.FUList6.opList] +[system.cpu.fuPool.FUList6.opList0] type=OpDesc eventq_index=0 opClass=MemWrite opLat=1 pipelined=true +[system.cpu.fuPool.FUList6.opList1] +type=OpDesc +eventq_index=0 +opClass=FloatMemWrite +opLat=1 +pipelined=true + [system.cpu.fuPool.FUList7] type=FUDesc -children=opList0 opList1 +children=opList0 opList1 opList2 opList3 count=4 eventq_index=0 -opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 +opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 system.cpu.fuPool.FUList7.opList2 system.cpu.fuPool.FUList7.opList3 [system.cpu.fuPool.FUList7.opList0] type=OpDesc @@ -514,6 +544,20 @@ opClass=MemWrite opLat=1 pipelined=true +[system.cpu.fuPool.FUList7.opList2] +type=OpDesc +eventq_index=0 +opClass=FloatMemRead +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList7.opList3] +type=OpDesc +eventq_index=0 +opClass=FloatMemWrite +opLat=1 +pipelined=true + [system.cpu.fuPool.FUList8] type=FUDesc children=opList @@ -535,10 +579,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=true max_miss_count=0 mshrs=4 @@ -552,6 +596,7 @@ response_latency=2 sequential_access=false size=131072 system=system +tag_latency=2 tags=system.cpu.icache.tags tgts_per_mshr=20 write_buffers=8 @@ -564,15 +609,16 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=131072 +tag_latency=2 [system.cpu.interrupts] type=AlphaInterrupts @@ -595,10 +641,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0 assoc=8 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=20 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=20 is_read_only=false max_miss_count=0 mshrs=20 @@ -612,6 +658,7 @@ response_latency=20 sequential_access=false size=2097152 system=system +tag_latency=20 tags=system.cpu.l2cache.tags tgts_per_mshr=12 write_buffers=8 @@ -624,15 +671,16 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=20 default_p_state=UNDEFINED eventq_index=0 -hit_latency=20 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=2097152 +tag_latency=20 [system.cpu.toL2Bus] type=CoherentXBar @@ -677,7 +725,7 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/test-progs/hello/bin/alpha/linux/hello +executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello gid=100 input=cin kvmInSE=false diff --git a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout index 27b942df1..06bbc9f54 100755 --- a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout +++ b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout @@ -3,10 +3,10 @@ Redirecting stderr to build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-tim gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Oct 11 2016 00:00:58 -gem5 started Oct 13 2016 20:19:49 -gem5 executing on e108600-lin, pid 28099 -command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/00.hello/alpha/linux/o3-timing +gem5 compiled Nov 29 2016 18:06:09 +gem5 started Nov 29 2016 18:06:29 +gem5 executing on zizzer, pid 27582 +command line: /z/powerjg/gem5-upstream/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-timing -re /z/powerjg/gem5-upstream/tests/testing/../run.py quick/se/00.hello/alpha/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt index 6cc52ba2c..3af1cbc4b 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000024 # Nu sim_ticks 23776000 # Number of ticks simulated final_tick 23776000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 139405 # Simulator instruction rate (inst/s) -host_op_rate 139373 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 518883929 # Simulator tick rate (ticks/s) -host_mem_usage 254032 # Number of bytes of host memory used -host_seconds 0.05 # Real time elapsed on the host +host_inst_rate 4743 # Simulator instruction rate (inst/s) +host_op_rate 4743 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 17659718 # Simulator tick rate (ticks/s) +host_mem_usage 236044 # Number of bytes of host memory used +host_seconds 1.35 # Real time elapsed on the host sim_insts 6385 # Number of instructions simulated sim_ops 6385 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -201,12 +201,12 @@ system.physmem.bytesPerActivate::768-895 2 2.25% 87.64% # By system.physmem.bytesPerActivate::896-1023 1 1.12% 88.76% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 10 11.24% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 89 # Bytes accessed per row activation -system.physmem.totQLat 8009750 # Total ticks spent queuing -system.physmem.totMemAccLat 17103500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 8008750 # Total ticks spent queuing +system.physmem.totMemAccLat 17102500 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 2425000 # Total ticks spent in databus transfers -system.physmem.avgQLat 16514.95 # Average queueing delay per DRAM burst +system.physmem.avgQLat 16512.89 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 35264.95 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 35262.89 # Average memory access latency per DRAM burst system.physmem.avgRdBW 1305.52 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 1305.52 # Average system read bandwidth in MiByte/s @@ -228,20 +228,20 @@ system.physmem_0.preEnergy 125235 # En system.physmem_0.readEnergy 1763580 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 1843920.000000 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 3005040 # Energy for active background per rank (pJ) +system.physmem_0.actBackEnergy 3004470 # Energy for active background per rank (pJ) system.physmem_0.preBackEnergy 47520 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 7623180 # Energy for active power-down per rank (pJ) +system.physmem_0.actPowerDownEnergy 7623750 # Energy for active power-down per rank (pJ) system.physmem_0.prePowerDownEnergy 132480 # Energy for precharge power-down per rank (pJ) system.physmem_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) system.physmem_0.totalEnergy 14783715 # Total energy per rank (pJ) system.physmem_0.averagePower 621.784975 # Core power per rank (mW) -system.physmem_0.totalIdleTime 16957250 # Total Idle time Per DRAM Rank +system.physmem_0.totalIdleTime 16958250 # Total Idle time Per DRAM Rank system.physmem_0.memoryStateTime::IDLE 40500 # Time in different power states system.physmem_0.memoryStateTime::REF 780000 # Time in different power states system.physmem_0.memoryStateTime::SREF 0 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 344500 # Time in different power states -system.physmem_0.memoryStateTime::ACT 5900500 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 16710500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 5899500 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 16711500 # Time in different power states system.physmem_1.actEnergy 399840 # Energy for activate commands per rank (pJ) system.physmem_1.preEnergy 212520 # Energy for precharge commands per rank (pJ) system.physmem_1.readEnergy 1699320 # Energy for read commands per rank (pJ) @@ -313,7 +313,7 @@ system.cpu.pwrStateResidencyTicks::ON 23776000 # Cu system.cpu.numCycles 47553 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 8496 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.icacheStallCycles 8498 # Number of cycles fetch is stalled on an Icache miss system.cpu.fetch.Insts 16559 # Number of instructions fetch has processed system.cpu.fetch.Branches 2854 # Number of branches that fetch encountered system.cpu.fetch.predictedBranches 1179 # Number of branches that fetch has predicted taken @@ -323,11 +323,11 @@ system.cpu.fetch.MiscStallCycles 22 # Nu system.cpu.fetch.PendingTrapStallCycles 656 # Number of stall cycles due to pending traps system.cpu.fetch.CacheLines 2295 # Number of cache lines fetched system.cpu.fetch.IcacheSquashes 335 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 15456 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.071364 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.458774 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::samples 15458 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.071225 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.458645 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 12470 80.68% 80.68% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 12472 80.68% 80.68% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::1 297 1.92% 82.60% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::2 230 1.49% 84.09% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::3 258 1.67% 85.76% # Number of instructions fetched each cycle (Total) @@ -339,10 +339,10 @@ system.cpu.fetch.rateDist::8 1247 8.07% 100.00% # Nu system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 15456 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 15458 # Number of instructions fetched each cycle (Total) system.cpu.fetch.branchRate 0.060017 # Number of branch fetches per cycle system.cpu.fetch.rate 0.348222 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 8339 # Number of cycles decode is idle +system.cpu.decode.IdleCycles 8341 # Number of cycles decode is idle system.cpu.decode.BlockedCycles 4008 # Number of cycles decode is blocked system.cpu.decode.RunCycles 2446 # Number of cycles decode is running system.cpu.decode.UnblockCycles 214 # Number of cycles decode is unblocking @@ -352,7 +352,7 @@ system.cpu.decode.BranchMispred 75 # Nu system.cpu.decode.DecodedInsts 15004 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 221 # Number of squashed instructions handled by decode system.cpu.rename.SquashCycles 449 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 8498 # Number of cycles rename is idle +system.cpu.rename.IdleCycles 8500 # Number of cycles rename is idle system.cpu.rename.BlockCycles 1841 # Number of cycles rename is blocking system.cpu.rename.serializeStallCycles 655 # count of cycles rename stalled for serializing inst system.cpu.rename.RunCycles 2476 # Number of cycles rename is running @@ -382,23 +382,23 @@ system.cpu.iq.iqSquashedInstsIssued 17 # Nu system.cpu.iq.iqSquashedInstsExamined 6695 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu.iq.iqSquashedOperandsExamined 3669 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 10 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 15456 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.697205 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.442232 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 15458 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.697115 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.442161 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 11416 73.86% 73.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1297 8.39% 82.25% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 11418 73.86% 73.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1297 8.39% 82.26% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::2 916 5.93% 88.18% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::3 681 4.41% 92.59% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::4 517 3.34% 95.93% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 347 2.25% 98.18% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 347 2.24% 98.18% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 200 1.29% 99.47% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 55 0.36% 99.83% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 27 0.17% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 15456 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 15458 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 21 14.89% 14.89% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 14.89% # attempts to use FU when none available @@ -479,7 +479,7 @@ system.cpu.iq.FU_type_0::total 10776 # Ty system.cpu.iq.rate 0.226610 # Inst issue rate system.cpu.iq.fu_busy_cnt 141 # FU busy when requested system.cpu.iq.fu_busy_rate 0.013085 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 37145 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_reads 37147 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_writes 19787 # Number of integer instruction queue writes system.cpu.iq.int_inst_queue_wakeup_accesses 9745 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 21 # Number of floating instruction queue reads @@ -530,11 +530,11 @@ system.cpu.iew.wb_fanout 0.733808 # av system.cpu.commit.commitSquashedInsts 6712 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 408 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 14219 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.450243 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.361136 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 14221 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.450179 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.361050 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 11792 82.93% 82.93% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 11794 82.93% 82.93% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::1 1158 8.14% 91.08% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::2 469 3.30% 94.37% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::3 205 1.44% 95.82% # Number of insts commited each cycle @@ -546,7 +546,7 @@ system.cpu.commit.committed_per_cycle::8 192 1.35% 100.00% # Nu system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 14219 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 14221 # Number of insts commited each cycle system.cpu.commit.committedInsts 6402 # Number of instructions committed system.cpu.commit.committedOps 6402 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -597,10 +597,10 @@ system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Cl system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 6402 # Class of committed instruction system.cpu.commit.bw_lim_events 192 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 26790 # The number of ROB reads +system.cpu.rob.rob_reads 26792 # The number of ROB reads system.cpu.rob.rob_writes 27482 # The number of ROB writes system.cpu.timesIdled 250 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 32097 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.idleCycles 32095 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 6385 # Number of Instructions Simulated system.cpu.committedOps 6385 # Number of Ops (including micro ops) Simulated system.cpu.cpi 7.447612 # CPI: Cycles Per Instruction @@ -753,12 +753,12 @@ system.cpu.icache.demand_misses::cpu.inst 458 # n system.cpu.icache.demand_misses::total 458 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 458 # number of overall misses system.cpu.icache.overall_misses::total 458 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 35507500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 35507500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 35507500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 35507500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 35507500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 35507500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 35506500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 35506500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 35506500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 35506500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 35506500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 35506500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 2295 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 2295 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 2295 # number of demand (read+write) accesses @@ -771,12 +771,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.199564 system.cpu.icache.demand_miss_rate::total 0.199564 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.199564 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.199564 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 77527.292576 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 77527.292576 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 77527.292576 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 77527.292576 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 77527.292576 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 77527.292576 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 77525.109170 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 77525.109170 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 77525.109170 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 77525.109170 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 77525.109170 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 77525.109170 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 67 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked @@ -795,24 +795,24 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 313 system.cpu.icache.demand_mshr_misses::total 313 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 313 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 313 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 26275500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 26275500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 26275500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 26275500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 26275500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 26275500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 26274500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 26274500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 26274500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 26274500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 26274500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 26274500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.136383 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.136383 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.136383 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.136383 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.136383 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.136383 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 83947.284345 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 83947.284345 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 83947.284345 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 83947.284345 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 83947.284345 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 83947.284345 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 83944.089457 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 83944.089457 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 83944.089457 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 83944.089457 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 83944.089457 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 83944.089457 # average overall mshr miss latency system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 23776000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements system.cpu.l2cache.tags.tagsinuse 270.818986 # Cycle average of tags in use @@ -852,16 +852,16 @@ system.cpu.l2cache.overall_misses::cpu.data 173 # system.cpu.l2cache.overall_misses::total 485 # number of overall misses system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6902500 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 6902500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 25792500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 25792500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 25791500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 25791500 # number of ReadCleanReq miss cycles system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 9241500 # number of ReadSharedReq miss cycles system.cpu.l2cache.ReadSharedReq_miss_latency::total 9241500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 25792500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 25791500 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.data 16144000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 41936500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 25792500 # number of overall miss cycles +system.cpu.l2cache.demand_miss_latency::total 41935500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 25791500 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.data 16144000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 41936500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 41935500 # number of overall miss cycles system.cpu.l2cache.ReadExReq_accesses::cpu.data 72 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 72 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 313 # number of ReadCleanReq accesses(hits+misses) @@ -888,16 +888,16 @@ system.cpu.l2cache.overall_miss_rate::cpu.data 1 system.cpu.l2cache.overall_miss_rate::total 0.997942 # miss rate for overall accesses system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 95868.055556 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 95868.055556 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 82668.269231 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 82668.269231 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 82665.064103 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 82665.064103 # average ReadCleanReq miss latency system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 91500 # average ReadSharedReq miss latency system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 91500 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82668.269231 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82665.064103 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 93317.919075 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 86467.010309 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82668.269231 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 86464.948454 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82665.064103 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 93317.919075 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 86467.010309 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 86464.948454 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -918,16 +918,16 @@ system.cpu.l2cache.overall_mshr_misses::cpu.data 173 system.cpu.l2cache.overall_mshr_misses::total 485 # number of overall MSHR misses system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6182500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6182500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 22672500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 22672500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 22671500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 22671500 # number of ReadCleanReq MSHR miss cycles system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 8231500 # number of ReadSharedReq MSHR miss cycles system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 8231500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 22672500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 22671500 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 14414000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 37086500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 22672500 # number of overall MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 37085500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 22671500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 14414000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 37086500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 37085500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.996805 # mshr miss rate for ReadCleanReq accesses @@ -942,16 +942,16 @@ system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 system.cpu.l2cache.overall_mshr_miss_rate::total 0.997942 # mshr miss rate for overall accesses system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 85868.055556 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 85868.055556 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72668.269231 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72668.269231 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72665.064103 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72665.064103 # average ReadCleanReq mshr miss latency system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 81500 # average ReadSharedReq mshr miss latency system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 81500 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72668.269231 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72665.064103 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 83317.919075 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 76467.010309 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72668.269231 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 76464.948454 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72665.064103 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 83317.919075 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 76467.010309 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 76464.948454 # average overall mshr miss latency system.cpu.toL2Bus.snoop_filter.tot_requests 486 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 1 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini index 4a82d75c8..3cdf3afd3 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini @@ -176,10 +176,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=false max_miss_count=0 mshrs=6 @@ -193,6 +193,7 @@ response_latency=2 sequential_access=false size=32768 system=system +tag_latency=2 tags=system.cpu.dcache.tags tgts_per_mshr=8 write_buffers=16 @@ -205,15 +206,16 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=32768 +tag_latency=2 [system.cpu.dstage2_mmu] type=ArmStage2MMU @@ -316,38 +318,52 @@ pipelined=true [system.cpu.fuPool.FUList2] type=FUDesc -children=opList +children=opList0 opList1 count=1 eventq_index=0 -opList=system.cpu.fuPool.FUList2.opList +opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 -[system.cpu.fuPool.FUList2.opList] +[system.cpu.fuPool.FUList2.opList0] type=OpDesc eventq_index=0 opClass=MemRead opLat=2 pipelined=true +[system.cpu.fuPool.FUList2.opList1] +type=OpDesc +eventq_index=0 +opClass=FloatMemRead +opLat=2 +pipelined=true + [system.cpu.fuPool.FUList3] type=FUDesc -children=opList +children=opList0 opList1 count=1 eventq_index=0 -opList=system.cpu.fuPool.FUList3.opList +opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 -[system.cpu.fuPool.FUList3.opList] +[system.cpu.fuPool.FUList3.opList0] type=OpDesc eventq_index=0 opClass=MemWrite opLat=2 pipelined=true +[system.cpu.fuPool.FUList3.opList1] +type=OpDesc +eventq_index=0 +opClass=FloatMemWrite +opLat=2 +pipelined=true + [system.cpu.fuPool.FUList4] type=FUDesc -children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25 +children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25 opList26 opList27 count=2 eventq_index=0 -opList=system.cpu.fuPool.FUList4.opList00 system.cpu.fuPool.FUList4.opList01 system.cpu.fuPool.FUList4.opList02 system.cpu.fuPool.FUList4.opList03 system.cpu.fuPool.FUList4.opList04 system.cpu.fuPool.FUList4.opList05 system.cpu.fuPool.FUList4.opList06 system.cpu.fuPool.FUList4.opList07 system.cpu.fuPool.FUList4.opList08 system.cpu.fuPool.FUList4.opList09 system.cpu.fuPool.FUList4.opList10 system.cpu.fuPool.FUList4.opList11 system.cpu.fuPool.FUList4.opList12 system.cpu.fuPool.FUList4.opList13 system.cpu.fuPool.FUList4.opList14 system.cpu.fuPool.FUList4.opList15 system.cpu.fuPool.FUList4.opList16 system.cpu.fuPool.FUList4.opList17 system.cpu.fuPool.FUList4.opList18 system.cpu.fuPool.FUList4.opList19 system.cpu.fuPool.FUList4.opList20 system.cpu.fuPool.FUList4.opList21 system.cpu.fuPool.FUList4.opList22 system.cpu.fuPool.FUList4.opList23 system.cpu.fuPool.FUList4.opList24 system.cpu.fuPool.FUList4.opList25 +opList=system.cpu.fuPool.FUList4.opList00 system.cpu.fuPool.FUList4.opList01 system.cpu.fuPool.FUList4.opList02 system.cpu.fuPool.FUList4.opList03 system.cpu.fuPool.FUList4.opList04 system.cpu.fuPool.FUList4.opList05 system.cpu.fuPool.FUList4.opList06 system.cpu.fuPool.FUList4.opList07 system.cpu.fuPool.FUList4.opList08 system.cpu.fuPool.FUList4.opList09 system.cpu.fuPool.FUList4.opList10 system.cpu.fuPool.FUList4.opList11 system.cpu.fuPool.FUList4.opList12 system.cpu.fuPool.FUList4.opList13 system.cpu.fuPool.FUList4.opList14 system.cpu.fuPool.FUList4.opList15 system.cpu.fuPool.FUList4.opList16 system.cpu.fuPool.FUList4.opList17 system.cpu.fuPool.FUList4.opList18 system.cpu.fuPool.FUList4.opList19 system.cpu.fuPool.FUList4.opList20 system.cpu.fuPool.FUList4.opList21 system.cpu.fuPool.FUList4.opList22 system.cpu.fuPool.FUList4.opList23 system.cpu.fuPool.FUList4.opList24 system.cpu.fuPool.FUList4.opList25 system.cpu.fuPool.FUList4.opList26 system.cpu.fuPool.FUList4.opList27 [system.cpu.fuPool.FUList4.opList00] type=OpDesc @@ -479,7 +495,7 @@ pipelined=true type=OpDesc eventq_index=0 opClass=SimdFloatMultAcc -opLat=1 +opLat=5 pipelined=true [system.cpu.fuPool.FUList4.opList19] @@ -531,6 +547,20 @@ opClass=FloatMult opLat=4 pipelined=true +[system.cpu.fuPool.FUList4.opList26] +type=OpDesc +eventq_index=0 +opClass=FloatMultAcc +opLat=5 +pipelined=true + +[system.cpu.fuPool.FUList4.opList27] +type=OpDesc +eventq_index=0 +opClass=FloatMisc +opLat=3 +pipelined=true + [system.cpu.icache] type=Cache children=tags @@ -538,10 +568,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=1 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=1 is_read_only=true max_miss_count=0 mshrs=2 @@ -555,6 +585,7 @@ response_latency=1 sequential_access=false size=32768 system=system +tag_latency=1 tags=system.cpu.icache.tags tgts_per_mshr=8 write_buffers=8 @@ -567,15 +598,16 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=1 default_p_state=UNDEFINED eventq_index=0 -hit_latency=1 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=32768 +tag_latency=1 [system.cpu.interrupts] type=ArmInterrupts @@ -670,10 +702,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0 assoc=16 clk_domain=system.cpu_clk_domain clusivity=mostly_excl +data_latency=12 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=12 is_read_only=false max_miss_count=0 mshrs=16 @@ -687,6 +719,7 @@ response_latency=12 sequential_access=false size=1048576 system=system +tag_latency=12 tags=system.cpu.l2cache.tags tgts_per_mshr=8 write_buffers=8 @@ -729,15 +762,16 @@ type=RandomRepl assoc=16 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=12 default_p_state=UNDEFINED eventq_index=0 -hit_latency=12 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=1048576 +tag_latency=12 [system.cpu.toL2Bus] type=CoherentXBar @@ -782,7 +816,7 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/test-progs/hello/bin/arm/linux/hello +executable=/dist/m5/regression/test-progs/hello/bin/arm/linux/hello gid=100 input=cin kvmInSE=false diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout index 81299f400..d64ac9ed3 100755 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout @@ -3,12 +3,12 @@ Redirecting stderr to build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing/ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Oct 11 2016 00:00:58 -gem5 started Oct 13 2016 20:52:56 -gem5 executing on e108600-lin, pid 17478 -command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/00.hello/arm/linux/o3-timing +gem5 compiled Nov 29 2016 19:03:48 +gem5 started Nov 29 2016 19:06:55 +gem5 executing on zizzer, pid 5766 +command line: /z/powerjg/gem5-upstream/build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing -re /z/powerjg/gem5-upstream/tests/testing/../run.py quick/se/00.hello/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 20299000 because target called exit() +Exiting @ tick 20302000 because target called exit() diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt index 613bc274a..307f14079 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt @@ -1,19 +1,19 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000020 # Number of seconds simulated -sim_ticks 20299000 # Number of ticks simulated -final_tick 20299000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 20302000 # Number of ticks simulated +final_tick 20302000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 98455 # Simulator instruction rate (inst/s) -host_op_rate 115276 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 434998330 # Simulator tick rate (ticks/s) -host_mem_usage 266116 # Number of bytes of host memory used -host_seconds 0.05 # Real time elapsed on the host +host_inst_rate 10367 # Simulator instruction rate (inst/s) +host_op_rate 12141 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 45828431 # Simulator tick rate (ticks/s) +host_mem_usage 248616 # Number of bytes of host memory used +host_seconds 0.44 # Real time elapsed on the host sim_insts 4592 # Number of instructions simulated sim_ops 5378 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 20299000 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 20302000 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 18560 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 8128 # Number of bytes read from this memory system.physmem.bytes_read::cpu.l2cache.prefetcher 1728 # Number of bytes read from this memory @@ -24,16 +24,16 @@ system.physmem.num_reads::cpu.inst 290 # Nu system.physmem.num_reads::cpu.data 127 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.l2cache.prefetcher 27 # Number of read requests responded to by this memory system.physmem.num_reads::total 444 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 914330755 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 400413813 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 85127346 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1399871915 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 914330755 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 914330755 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 914330755 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 400413813 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 85127346 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1399871915 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 914195646 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 400354645 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 85114767 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1399665058 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 914195646 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 914195646 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 914195646 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 400354645 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 85114767 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1399665058 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 445 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 445 # Number of DRAM read bursts, including those serviced by the write queue @@ -80,7 +80,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 20257500 # Total gap between requests +system.physmem.totGap 20260500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -96,9 +96,9 @@ system.physmem.writePktSize::4 0 # Wr system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) system.physmem.rdQLenPdf::0 241 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 137 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 136 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 36 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 16 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 17 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 2 # What read queue length does an incoming req see @@ -193,8 +193,8 @@ system.physmem.wrQLenPdf::62 0 # Wh system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see system.physmem.bytesPerActivate::samples 62 # Bytes accessed per row activation system.physmem.bytesPerActivate::mean 435.612903 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 295.342416 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 353.563376 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 295.844737 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 352.802892 # Bytes accessed per row activation system.physmem.bytesPerActivate::0-127 8 12.90% 12.90% # Bytes accessed per row activation system.physmem.bytesPerActivate::128-255 16 25.81% 38.71% # Bytes accessed per row activation system.physmem.bytesPerActivate::256-383 10 16.13% 54.84% # Bytes accessed per row activation @@ -205,74 +205,74 @@ system.physmem.bytesPerActivate::768-895 2 3.23% 77.42% # By system.physmem.bytesPerActivate::896-1023 4 6.45% 83.87% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 10 16.13% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 62 # Bytes accessed per row activation -system.physmem.totQLat 6110750 # Total ticks spent queuing -system.physmem.totMemAccLat 14454500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 6124000 # Total ticks spent queuing +system.physmem.totMemAccLat 14467750 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 2225000 # Total ticks spent in databus transfers -system.physmem.avgQLat 13732.02 # Average queueing delay per DRAM burst +system.physmem.avgQLat 13761.80 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 32482.02 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1403.02 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 32511.80 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1402.82 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1403.02 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1402.82 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 10.96 # Data bus utilization in percentage system.physmem.busUtilRead 10.96 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.84 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.85 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing system.physmem.readRowHits 373 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 83.82 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 45522.47 # Average gap between requests +system.physmem.avgGap 45529.21 # Average gap between requests system.physmem.pageHitRate 83.82 # Row buffer hit rate, read and write combined system.physmem_0.actEnergy 349860 # Energy for activate commands per rank (pJ) system.physmem_0.preEnergy 170775 # Energy for precharge commands per rank (pJ) system.physmem_0.readEnergy 2334780 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 1229280.000000 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 3572760 # Energy for active background per rank (pJ) +system.physmem_0.actBackEnergy 3561360 # Energy for active background per rank (pJ) system.physmem_0.preBackEnergy 28800 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 5648700 # Energy for active power-down per rank (pJ) +system.physmem_0.actPowerDownEnergy 5661240 # Energy for active power-down per rank (pJ) system.physmem_0.prePowerDownEnergy 960 # Energy for precharge power-down per rank (pJ) system.physmem_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 13335915 # Total energy per rank (pJ) -system.physmem_0.averagePower 656.941626 # Core power per rank (mW) -system.physmem_0.totalIdleTime 12232500 # Total Idle time Per DRAM Rank +system.physmem_0.totalEnergy 13337055 # Total energy per rank (pJ) +system.physmem_0.averagePower 656.916882 # Core power per rank (mW) +system.physmem_0.totalIdleTime 12272000 # Total Idle time Per DRAM Rank system.physmem_0.memoryStateTime::IDLE 19000 # Time in different power states system.physmem_0.memoryStateTime::REF 520000 # Time in different power states system.physmem_0.memoryStateTime::SREF 0 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 2500 # Time in different power states -system.physmem_0.memoryStateTime::ACT 7376750 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 12380750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 7340250 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 12420250 # Time in different power states system.physmem_1.actEnergy 164220 # Energy for activate commands per rank (pJ) system.physmem_1.preEnergy 64515 # Energy for precharge commands per rank (pJ) system.physmem_1.readEnergy 842520 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 1229280.000000 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1468320 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 69120 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 7424250 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 237600 # Energy for precharge power-down per rank (pJ) +system.physmem_1.actBackEnergy 1479720 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 68640 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 7413420 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 238560 # Energy for precharge power-down per rank (pJ) system.physmem_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 11499825 # Total energy per rank (pJ) -system.physmem_1.averagePower 566.493842 # Core power per rank (mW) -system.physmem_1.totalIdleTime 16895250 # Total Idle time Per DRAM Rank +system.physmem_1.totalEnergy 11500875 # Total energy per rank (pJ) +system.physmem_1.averagePower 566.475803 # Core power per rank (mW) +system.physmem_1.totalIdleTime 16880000 # Total Idle time Per DRAM Rank system.physmem_1.memoryStateTime::IDLE 110000 # Time in different power states system.physmem_1.memoryStateTime::REF 520000 # Time in different power states system.physmem_1.memoryStateTime::SREF 0 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 618500 # Time in different power states -system.physmem_1.memoryStateTime::ACT 2773750 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 16276750 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 20299000 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 2441 # Number of BP lookups -system.cpu.branchPred.condPredicted 1444 # Number of conditional branches predicted +system.physmem_1.memoryStateTime::PRE_PDN 620500 # Time in different power states +system.physmem_1.memoryStateTime::ACT 2792000 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 16259500 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 20302000 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 2438 # Number of BP lookups +system.cpu.branchPred.condPredicted 1442 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 522 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 916 # Number of BTB lookups +system.cpu.branchPred.BTBLookups 915 # Number of BTB lookups system.cpu.branchPred.BTBHits 449 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 49.017467 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 49.071038 # BTB Hit Percentage system.cpu.branchPred.usedRAS 286 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 57 # Number of incorrect RAS predictions. system.cpu.branchPred.indirectLookups 163 # Number of indirect predictor lookups. @@ -280,7 +280,7 @@ system.cpu.branchPred.indirectHits 13 # Nu system.cpu.branchPred.indirectMisses 150 # Number of indirect misses. system.cpu.branchPredindirectMispredicted 59 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 20299000 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 20302000 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -310,7 +310,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 20299000 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 20302000 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -340,7 +340,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 20299000 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 20302000 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -370,7 +370,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 20299000 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 20302000 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -401,85 +401,85 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 13 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 20299000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 40599 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 20302000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 40605 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 6170 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 11468 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2441 # Number of branches that fetch encountered +system.cpu.fetch.icacheStallCycles 6160 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 11461 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2438 # Number of branches that fetch encountered system.cpu.fetch.predictedBranches 748 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 8322 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.Cycles 8317 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.SquashCycles 1087 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 161 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.MiscStallCycles 162 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 286 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 434 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 3907 # Number of cache lines fetched +system.cpu.fetch.IcacheWaitRetryStallCycles 447 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 3903 # Number of cache lines fetched system.cpu.fetch.IcacheSquashes 179 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 15916 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.856748 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.206522 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::samples 15915 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.856236 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.206395 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 9525 59.85% 59.85% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2508 15.76% 75.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 521 3.27% 78.88% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 3362 21.12% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 9529 59.87% 59.87% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2505 15.74% 75.61% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 521 3.27% 78.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 3360 21.11% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 15916 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.060125 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.282470 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 5812 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 4409 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 5179 # Number of cycles decode is running +system.cpu.fetch.rateDist::total 15915 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.060042 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.282256 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 5815 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 4410 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 5174 # Number of cycles decode is running system.cpu.decode.UnblockCycles 132 # Number of cycles decode is unblocking system.cpu.decode.SquashCycles 384 # Number of cycles decode is squashing system.cpu.decode.BranchResolved 374 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 162 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 10178 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 1683 # Number of squashed instructions handled by decode +system.cpu.decode.DecodedInsts 10174 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 1674 # Number of squashed instructions handled by decode system.cpu.rename.SquashCycles 384 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 6925 # Number of cycles rename is idle +system.cpu.rename.IdleCycles 6926 # Number of cycles rename is idle system.cpu.rename.BlockCycles 1165 # Number of cycles rename is blocking system.cpu.rename.serializeStallCycles 2515 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 4188 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 739 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 9100 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 467 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 24 # Number of times rename has blocked due to ROB full +system.cpu.rename.RunCycles 4185 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 740 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 9093 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 464 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 25 # Number of times rename has blocked due to ROB full system.cpu.rename.IQFullEvents 1 # Number of times rename has blocked due to IQ full system.cpu.rename.LQFullEvents 28 # Number of times rename has blocked due to LQ full system.cpu.rename.SQFullEvents 631 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 9458 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 41150 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 10006 # Number of integer rename lookups +system.cpu.rename.RenamedOperands 9451 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 41117 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 9997 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 17 # Number of floating rename lookups system.cpu.rename.CommittedMaps 5494 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 3964 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 3957 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 29 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 27 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 330 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 1823 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1289 # Number of stores inserted to the mem dependence unit. +system.cpu.rename.skidInsts 332 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 1821 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1286 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 1 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 8513 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 8508 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 38 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 7228 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 182 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 3173 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 8254 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 7222 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 185 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 3168 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 8232 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 1 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 15916 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.454134 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 0.844472 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 15915 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.453786 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 0.844098 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 11653 73.22% 73.22% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1992 12.52% 85.73% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 1620 10.18% 95.91% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 608 3.82% 99.73% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 43 0.27% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 11657 73.25% 73.25% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1985 12.47% 85.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 1624 10.20% 95.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 607 3.81% 99.74% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 42 0.26% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::5 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle @@ -487,101 +487,101 @@ system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Nu system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 4 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 15916 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 15915 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 416 28.75% 28.75% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 28.75% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 28.75% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 28.75% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 28.75% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 28.75% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 28.75% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 28.75% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 28.75% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMisc 0 0.00% 28.75% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 28.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 28.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 28.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 28.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 28.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 28.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 28.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 28.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 28.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 28.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 28.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 28.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 28.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 28.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 28.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 28.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 28.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 28.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 28.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 28.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 28.75% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 475 32.83% 61.58% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 539 37.25% 98.83% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemRead 0 0.00% 98.83% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemWrite 17 1.17% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 415 28.86% 28.86% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 28.86% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 28.86% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 28.86% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 28.86% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 28.86% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 28.86% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 28.86% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 28.86% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 0 0.00% 28.86% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 28.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 28.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 28.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 28.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 28.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 28.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 28.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 28.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 28.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 28.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 28.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 28.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 28.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 28.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 28.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 28.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 28.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 28.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 28.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 28.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 28.86% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 468 32.55% 61.40% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 538 37.41% 98.82% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemRead 0 0.00% 98.82% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemWrite 17 1.18% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 4533 62.71% 62.71% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 5 0.07% 62.78% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.78% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.78% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.78% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.78% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.78% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 62.78% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.78% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 62.78% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.04% 62.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.83% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 1605 22.21% 85.03% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1066 14.75% 99.78% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 4533 62.77% 62.77% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 5 0.07% 62.84% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.84% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.84% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.84% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.84% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.84% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 62.84% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.84% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 62.84% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.04% 62.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.88% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 1600 22.15% 85.03% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1065 14.75% 99.78% # Type of FU issued system.cpu.iq.FU_type_0::FloatMemRead 0 0.00% 99.78% # Type of FU issued system.cpu.iq.FU_type_0::FloatMemWrite 16 0.22% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 7228 # Type of FU issued -system.cpu.iq.rate 0.178034 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1447 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.200194 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 31952 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 11715 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 6617 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 7222 # Type of FU issued +system.cpu.iq.rate 0.177860 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1438 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.199114 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 31933 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 11705 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 6615 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 49 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 16 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 8642 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 8627 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 33 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 12 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 796 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 794 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 7 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 351 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 348 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 7 # Number of loads that were rescheduled @@ -590,10 +590,10 @@ system.cpu.iew.iewIdleCycles 0 # Nu system.cpu.iew.iewSquashCycles 384 # Number of cycles IEW is squashing system.cpu.iew.iewBlockCycles 345 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 11 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 8564 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispatchedInsts 8559 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 1823 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1289 # Number of dispatched store instructions +system.cpu.iew.iewDispLoadInsts 1821 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1286 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 26 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 3 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 6 # Number of times the LSQ has become full, causing a stall @@ -601,41 +601,41 @@ system.cpu.iew.memOrderViolationEvents 7 # Nu system.cpu.iew.predictedTakenIncorrect 60 # Number of branches that were predicted taken incorrectly system.cpu.iew.predictedNotTakenIncorrect 318 # Number of branches that were predicted not taken incorrectly system.cpu.iew.branchMispredicts 378 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 6821 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 1422 # Number of load instructions executed +system.cpu.iew.iewExecutedInsts 6815 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 1418 # Number of load instructions executed system.cpu.iew.iewExecSquashedInsts 407 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 13 # number of nop insts executed -system.cpu.iew.exec_refs 2447 # number of memory reference insts executed -system.cpu.iew.exec_branches 1298 # Number of branches executed -system.cpu.iew.exec_stores 1025 # Number of stores executed -system.cpu.iew.exec_rate 0.168009 # Inst execution rate -system.cpu.iew.wb_sent 6677 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 6633 # cumulative count of insts written-back +system.cpu.iew.exec_refs 2442 # number of memory reference insts executed +system.cpu.iew.exec_branches 1297 # Number of branches executed +system.cpu.iew.exec_stores 1024 # Number of stores executed +system.cpu.iew.exec_rate 0.167836 # Inst execution rate +system.cpu.iew.wb_sent 6675 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 6631 # cumulative count of insts written-back system.cpu.iew.wb_producers 2981 # num instructions producing a value -system.cpu.iew.wb_consumers 5419 # num instructions consuming a value -system.cpu.iew.wb_rate 0.163378 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.550101 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 2706 # The number of squashed insts skipped by commit +system.cpu.iew.wb_consumers 5426 # num instructions consuming a value +system.cpu.iew.wb_rate 0.163305 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.549392 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 2701 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 363 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 15349 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.350381 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 0.988718 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 15348 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.350404 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 0.989339 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 12681 82.62% 82.62% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1407 9.17% 91.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 599 3.90% 95.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 298 1.94% 97.63% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 170 1.11% 98.74% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 79 0.51% 99.25% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 44 0.29% 99.54% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 28 0.18% 99.72% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 43 0.28% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 12680 82.62% 82.62% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1404 9.15% 91.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 606 3.95% 95.71% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 298 1.94% 97.65% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 164 1.07% 98.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 80 0.52% 99.24% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 44 0.29% 99.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 28 0.18% 99.71% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 44 0.29% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 15349 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 15348 # Number of insts commited each cycle system.cpu.commit.committedInsts 4592 # Number of instructions committed system.cpu.commit.committedOps 5378 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -685,53 +685,53 @@ system.cpu.commit.op_class_0::FloatMemWrite 16 0.30% 100.00% # system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 5378 # Class of committed instruction -system.cpu.commit.bw_lim_events 43 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 23233 # The number of ROB reads -system.cpu.rob.rob_writes 16740 # The number of ROB writes -system.cpu.timesIdled 212 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 24683 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 44 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 23226 # The number of ROB reads +system.cpu.rob.rob_writes 16730 # The number of ROB writes +system.cpu.timesIdled 211 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 24690 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 4592 # Number of Instructions Simulated system.cpu.committedOps 5378 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 8.841246 # CPI: Cycles Per Instruction -system.cpu.cpi_total 8.841246 # CPI: Total CPI of All Threads -system.cpu.ipc 0.113106 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.113106 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 6772 # number of integer regfile reads -system.cpu.int_regfile_writes 3788 # number of integer regfile writes +system.cpu.cpi 8.842552 # CPI: Cycles Per Instruction +system.cpu.cpi_total 8.842552 # CPI: Total CPI of All Threads +system.cpu.ipc 0.113090 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.113090 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 6765 # number of integer regfile reads +system.cpu.int_regfile_writes 3787 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.cc_regfile_reads 24220 # number of cc regfile reads +system.cpu.cc_regfile_reads 24202 # number of cc regfile reads system.cpu.cc_regfile_writes 2924 # number of cc regfile writes -system.cpu.misc_regfile_reads 2559 # number of misc regfile reads +system.cpu.misc_regfile_reads 2558 # number of misc regfile reads system.cpu.misc_regfile_writes 24 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 20299000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 20302000 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 1 # number of replacements -system.cpu.dcache.tags.tagsinuse 84.063183 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 1930 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 84.060908 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 1926 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 143 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 13.496503 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 13.468531 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 84.063183 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.164186 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.164186 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 84.060908 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.164181 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.164181 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 142 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 90 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.277344 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 4723 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 4723 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 20299000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 1188 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1188 # number of ReadReq hits +system.cpu.dcache.tags.tag_accesses 4715 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 4715 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 20302000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 1184 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1184 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 722 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 722 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 9 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 9 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 1910 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 1910 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 1910 # number of overall hits -system.cpu.dcache.overall_hits::total 1910 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 1906 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 1906 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 1906 # number of overall hits +system.cpu.dcache.overall_hits::total 1906 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 167 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 167 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 191 # number of WriteReq misses @@ -742,48 +742,48 @@ system.cpu.dcache.demand_misses::cpu.data 358 # n system.cpu.dcache.demand_misses::total 358 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 358 # number of overall misses system.cpu.dcache.overall_misses::total 358 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 12032500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 12032500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 8019500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 8019500 # number of WriteReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 12046500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 12046500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 8016500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 8016500 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 139000 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 139000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 20052000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 20052000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 20052000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 20052000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1355 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1355 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 20063000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 20063000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 20063000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 20063000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1351 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1351 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 11 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2268 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2268 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2268 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2268 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.123247 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.123247 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 2264 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2264 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2264 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2264 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.123612 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.123612 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.209200 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.209200 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.181818 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.181818 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.157848 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.157848 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.157848 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.157848 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 72050.898204 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 72050.898204 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41986.910995 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 41986.910995 # average WriteReq miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.158127 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.158127 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.158127 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.158127 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 72134.730539 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 72134.730539 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41971.204188 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 41971.204188 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 69500 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 69500 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 56011.173184 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 56011.173184 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 56011.173184 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 56011.173184 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 56041.899441 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 56041.899441 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 56041.899441 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 56041.899441 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 853 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -810,88 +810,88 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 144 system.cpu.dcache.demand_mshr_misses::total 144 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 144 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 144 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7984500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 7984500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2595500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2595500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10580000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 10580000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10580000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 10580000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.076015 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.076015 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7999500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 7999500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2594500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2594500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10594000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 10594000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10594000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 10594000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.076240 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.076240 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044907 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.044907 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.063492 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.063492 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.063492 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.063492 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 77519.417476 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 77519.417476 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 63304.878049 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 63304.878049 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 73472.222222 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 73472.222222 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 73472.222222 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 73472.222222 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 20299000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.063604 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.063604 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.063604 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.063604 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 77665.048544 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 77665.048544 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 63280.487805 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 63280.487805 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 73569.444444 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 73569.444444 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 73569.444444 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 73569.444444 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 20302000 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 44 # number of replacements -system.cpu.icache.tags.tagsinuse 137.515573 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 3540 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 137.464664 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 3536 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 299 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 11.839465 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 11.826087 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 137.515573 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.268585 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.268585 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 137.464664 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.268486 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.268486 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 255 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 145 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 110 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.498047 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 8109 # Number of tag accesses -system.cpu.icache.tags.data_accesses 8109 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 20299000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 3540 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 3540 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 3540 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 3540 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 3540 # number of overall hits -system.cpu.icache.overall_hits::total 3540 # number of overall hits +system.cpu.icache.tags.tag_accesses 8101 # Number of tag accesses +system.cpu.icache.tags.data_accesses 8101 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 20302000 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 3536 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 3536 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 3536 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 3536 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 3536 # number of overall hits +system.cpu.icache.overall_hits::total 3536 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 365 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 365 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 365 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 365 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 365 # number of overall misses system.cpu.icache.overall_misses::total 365 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 25051490 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 25051490 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 25051490 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 25051490 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 25051490 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 25051490 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 3905 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 3905 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 3905 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 3905 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 3905 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 3905 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.093470 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.093470 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.093470 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.093470 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.093470 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.093470 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68634.219178 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 68634.219178 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 68634.219178 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 68634.219178 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 68634.219178 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 68634.219178 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 9850 # number of cycles access was blocked +system.cpu.icache.ReadReq_miss_latency::cpu.inst 25043490 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 25043490 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 25043490 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 25043490 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 25043490 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 25043490 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 3901 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 3901 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 3901 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 3901 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 3901 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 3901 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.093566 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.093566 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.093566 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.093566 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.093566 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.093566 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68612.301370 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 68612.301370 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 68612.301370 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 68612.301370 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 68612.301370 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 68612.301370 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 9833 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 47 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 96 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 97 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 102.604167 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 101.371134 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets 47 # average number of cycles each access was blocked system.cpu.icache.writebacks::writebacks 44 # number of writebacks system.cpu.icache.writebacks::total 44 # number of writebacks @@ -907,40 +907,40 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 299 system.cpu.icache.demand_mshr_misses::total 299 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 299 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 299 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22011990 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 22011990 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22011990 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 22011990 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22011990 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 22011990 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.076569 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.076569 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.076569 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.076569 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.076569 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.076569 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 73618.695652 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 73618.695652 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 73618.695652 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 73618.695652 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 73618.695652 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 73618.695652 # average overall mshr miss latency -system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 20299000 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22004990 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 22004990 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22004990 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 22004990 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22004990 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 22004990 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.076647 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.076647 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.076647 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.076647 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.076647 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.076647 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 73595.284281 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 73595.284281 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 73595.284281 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 73595.284281 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 73595.284281 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 73595.284281 # average overall mshr miss latency +system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 20302000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.prefetcher.num_hwpf_issued 112 # number of hwpf issued system.cpu.l2cache.prefetcher.pfIdentified 112 # number of prefetch candidates identified system.cpu.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size system.cpu.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 20299000 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 20302000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 17.353048 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 17.355508 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 3 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 41 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.073171 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 9.225603 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 8.127445 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 9.226998 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 8.128510 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.000563 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.000496 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.001059 # Average percentage of cache occupancy @@ -954,7 +954,7 @@ system.cpu.l2cache.tags.occ_task_id_percent::1022 0.000793 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.001709 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 7676 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 7676 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 20299000 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 20302000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackClean_hits::writebacks 33 # number of WritebackClean hits system.cpu.l2cache.WritebackClean_hits::total 33 # number of WritebackClean hits system.cpu.l2cache.ReadExReq_hits::cpu.data 11 # number of ReadExReq hits @@ -979,18 +979,18 @@ system.cpu.l2cache.demand_misses::total 424 # nu system.cpu.l2cache.overall_misses::cpu.inst 291 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 133 # number of overall misses system.cpu.l2cache.overall_misses::total 424 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2461000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 2461000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 21652500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 21652500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 7825000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 7825000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 21652500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 10286000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 31938500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 21652500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 10286000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 31938500 # number of overall miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2460000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 2460000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 21645500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 21645500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 7838000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 7838000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 21645500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 10298000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 31943500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 21645500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 10298000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 31943500 # number of overall miss cycles system.cpu.l2cache.WritebackClean_accesses::writebacks 33 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::total 33 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 41 # number of ReadExReq accesses(hits+misses) @@ -1017,18 +1017,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.957111 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.973244 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.923611 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.957111 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 82033.333333 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 82033.333333 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74407.216495 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74407.216495 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 75970.873786 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 75970.873786 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74407.216495 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77338.345865 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 75326.650943 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74407.216495 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77338.345865 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 75326.650943 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 82000 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 82000 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74383.161512 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74383.161512 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 76097.087379 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 76097.087379 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74383.161512 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77428.571429 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 75338.443396 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74383.161512 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77428.571429 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 75338.443396 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1062,19 +1062,19 @@ system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 53 system.cpu.l2cache.overall_mshr_misses::total 471 # number of overall MSHR misses system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 1766926 # number of HardPFReq MSHR miss cycles system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 1766926 # number of HardPFReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2281000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2281000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 19850000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 19850000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 6909500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 6909500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19850000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9190500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 29040500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19850000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9190500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2280000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2280000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 19843000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 19843000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 6922500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 6922500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19843000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9202500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 29045500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19843000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9202500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 1766926 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 30807426 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 30812426 # number of overall MSHR miss cycles system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.731707 # mshr miss rate for ReadExReq accesses @@ -1092,26 +1092,26 @@ system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf system.cpu.l2cache.overall_mshr_miss_rate::total 1.063205 # mshr miss rate for overall accesses system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 33338.226415 # average HardPFReq mshr miss latency system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 33338.226415 # average HardPFReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 76033.333333 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 76033.333333 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 68448.275862 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 68448.275862 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70505.102041 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70505.102041 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 68448.275862 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71800.781250 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69474.880383 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 68448.275862 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71800.781250 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 76000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 76000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 68424.137931 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 68424.137931 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70637.755102 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70637.755102 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 68424.137931 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71894.531250 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69486.842105 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 68424.137931 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71894.531250 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 33338.226415 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65408.547771 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65419.163482 # average overall mshr miss latency system.cpu.toL2Bus.snoop_filter.tot_requests 488 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 74 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 12 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 26 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 24 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 2 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 20299000 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 20302000 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 401 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 45 # Transaction distribution system.cpu.toL2Bus.trans_dist::HardPFReq 69 # Transaction distribution @@ -1150,7 +1150,7 @@ system.membus.snoop_filter.hit_multi_requests 0 system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 20299000 # Cumulative time (in ticks) in various power states +system.membus.pwrStateResidencyTicks::UNDEFINED 20302000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 414 # Transaction distribution system.membus.trans_dist::ReadExReq 30 # Transaction distribution system.membus.trans_dist::ReadExResp 30 # Transaction distribution @@ -1171,9 +1171,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 445 # Request fanout histogram -system.membus.reqLayer0.occupancy 564444 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 2.8 # Layer utilization (%) -system.membus.respLayer1.occupancy 2334750 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 554444 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 2.7 # Layer utilization (%) +system.membus.respLayer1.occupancy 2338000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 11.5 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/config.ini index 1e3a930b1..8fa043fc0 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/config.ini +++ b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/config.ini @@ -177,10 +177,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=false max_miss_count=0 mshrs=4 @@ -194,6 +194,7 @@ response_latency=2 sequential_access=false size=262144 system=system +tag_latency=2 tags=system.cpu.dcache.tags tgts_per_mshr=20 write_buffers=8 @@ -206,15 +207,16 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=262144 +tag_latency=2 [system.cpu.dtb] type=MipsTLB @@ -292,10 +294,10 @@ pipelined=true [system.cpu.fuPool.FUList3] type=FUDesc -children=opList0 opList1 opList2 +children=opList0 opList1 opList2 opList3 opList4 count=2 eventq_index=0 -opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 +opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 system.cpu.fuPool.FUList3.opList3 system.cpu.fuPool.FUList3.opList4 [system.cpu.fuPool.FUList3.opList0] type=OpDesc @@ -307,11 +309,25 @@ pipelined=true [system.cpu.fuPool.FUList3.opList1] type=OpDesc eventq_index=0 +opClass=FloatMultAcc +opLat=5 +pipelined=true + +[system.cpu.fuPool.FUList3.opList2] +type=OpDesc +eventq_index=0 +opClass=FloatMisc +opLat=3 +pipelined=true + +[system.cpu.fuPool.FUList3.opList3] +type=OpDesc +eventq_index=0 opClass=FloatDiv opLat=12 pipelined=false -[system.cpu.fuPool.FUList3.opList2] +[system.cpu.fuPool.FUList3.opList4] type=OpDesc eventq_index=0 opClass=FloatSqrt @@ -320,18 +336,25 @@ pipelined=false [system.cpu.fuPool.FUList4] type=FUDesc -children=opList +children=opList0 opList1 count=0 eventq_index=0 -opList=system.cpu.fuPool.FUList4.opList +opList=system.cpu.fuPool.FUList4.opList0 system.cpu.fuPool.FUList4.opList1 -[system.cpu.fuPool.FUList4.opList] +[system.cpu.fuPool.FUList4.opList0] type=OpDesc eventq_index=0 opClass=MemRead opLat=1 pipelined=true +[system.cpu.fuPool.FUList4.opList1] +type=OpDesc +eventq_index=0 +opClass=FloatMemRead +opLat=1 +pipelined=true + [system.cpu.fuPool.FUList5] type=FUDesc children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 @@ -481,24 +504,31 @@ pipelined=true [system.cpu.fuPool.FUList6] type=FUDesc -children=opList +children=opList0 opList1 count=0 eventq_index=0 -opList=system.cpu.fuPool.FUList6.opList +opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1 -[system.cpu.fuPool.FUList6.opList] +[system.cpu.fuPool.FUList6.opList0] type=OpDesc eventq_index=0 opClass=MemWrite opLat=1 pipelined=true +[system.cpu.fuPool.FUList6.opList1] +type=OpDesc +eventq_index=0 +opClass=FloatMemWrite +opLat=1 +pipelined=true + [system.cpu.fuPool.FUList7] type=FUDesc -children=opList0 opList1 +children=opList0 opList1 opList2 opList3 count=4 eventq_index=0 -opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 +opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 system.cpu.fuPool.FUList7.opList2 system.cpu.fuPool.FUList7.opList3 [system.cpu.fuPool.FUList7.opList0] type=OpDesc @@ -514,6 +544,20 @@ opClass=MemWrite opLat=1 pipelined=true +[system.cpu.fuPool.FUList7.opList2] +type=OpDesc +eventq_index=0 +opClass=FloatMemRead +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList7.opList3] +type=OpDesc +eventq_index=0 +opClass=FloatMemWrite +opLat=1 +pipelined=true + [system.cpu.fuPool.FUList8] type=FUDesc children=opList @@ -535,10 +579,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=true max_miss_count=0 mshrs=4 @@ -552,6 +596,7 @@ response_latency=2 sequential_access=false size=131072 system=system +tag_latency=2 tags=system.cpu.icache.tags tgts_per_mshr=20 write_buffers=8 @@ -564,15 +609,16 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=131072 +tag_latency=2 [system.cpu.interrupts] type=MipsInterrupts @@ -597,10 +643,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0 assoc=8 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=20 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=20 is_read_only=false max_miss_count=0 mshrs=20 @@ -614,6 +660,7 @@ response_latency=20 sequential_access=false size=2097152 system=system +tag_latency=20 tags=system.cpu.l2cache.tags tgts_per_mshr=12 write_buffers=8 @@ -626,15 +673,16 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=20 default_p_state=UNDEFINED eventq_index=0 -hit_latency=20 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=2097152 +tag_latency=20 [system.cpu.toL2Bus] type=CoherentXBar @@ -679,7 +727,7 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/test-progs/hello/bin/mips/linux/hello +executable=/dist/m5/regression/test-progs/hello/bin/mips/linux/hello gid=100 input=cin kvmInSE=false diff --git a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/simout index fa28c822f..b75343836 100755 --- a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/simout +++ b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/simout @@ -3,10 +3,10 @@ Redirecting stderr to build/MIPS/tests/opt/quick/se/00.hello/mips/linux/o3-timin gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Oct 13 2016 20:36:34 -gem5 started Oct 13 2016 20:36:59 -gem5 executing on e108600-lin, pid 36840 -command line: /work/curdun01/gem5-external.hg/build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/00.hello/mips/linux/o3-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/00.hello/mips/linux/o3-timing +gem5 compiled Nov 29 2016 18:13:44 +gem5 started Nov 29 2016 18:14:01 +gem5 executing on zizzer, pid 32698 +command line: /z/powerjg/gem5-upstream/build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/00.hello/mips/linux/o3-timing -re /z/powerjg/gem5-upstream/tests/testing/../run.py quick/se/00.hello/mips/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt index 10245d965..888fdd0d2 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000024 # Nu sim_ticks 24405000 # Number of ticks simulated final_tick 24405000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 123007 # Simulator instruction rate (inst/s) -host_op_rate 122970 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 600170719 # Simulator tick rate (ticks/s) -host_mem_usage 251144 # Number of bytes of host memory used -host_seconds 0.04 # Real time elapsed on the host +host_inst_rate 38911 # Simulator instruction rate (inst/s) +host_op_rate 38904 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 189891987 # Simulator tick rate (ticks/s) +host_mem_usage 234100 # Number of bytes of host memory used +host_seconds 0.13 # Real time elapsed on the host sim_insts 4999 # Number of instructions simulated sim_ops 4999 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -201,12 +201,12 @@ system.physmem.bytesPerActivate::768-895 4 3.51% 93.86% # By system.physmem.bytesPerActivate::896-1023 3 2.63% 96.49% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 4 3.51% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 114 # Bytes accessed per row activation -system.physmem.totQLat 7578250 # Total ticks spent queuing -system.physmem.totMemAccLat 16372000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 7577250 # Total ticks spent queuing +system.physmem.totMemAccLat 16371000 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 2345000 # Total ticks spent in databus transfers -system.physmem.avgQLat 16158.32 # Average queueing delay per DRAM burst +system.physmem.avgQLat 16156.18 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 34908.32 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 34906.18 # Average memory access latency per DRAM burst system.physmem.avgRdBW 1229.91 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 1229.91 # Average system read bandwidth in MiByte/s @@ -229,9 +229,9 @@ system.physmem_0.readEnergy 756840 # En system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 1843920.000000 # Energy for refresh commands per rank (pJ) system.physmem_0.actBackEnergy 1602840 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 46080 # Energy for precharge background per rank (pJ) +system.physmem_0.preBackEnergy 46560 # Energy for precharge background per rank (pJ) system.physmem_0.actPowerDownEnergy 8339100 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 953280 # Energy for precharge power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 952800 # Energy for precharge power-down per rank (pJ) system.physmem_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) system.physmem_0.totalEnergy 13833510 # Total energy per rank (pJ) system.physmem_0.averagePower 566.830977 # Core power per rank (mW) @@ -239,9 +239,9 @@ system.physmem_0.totalIdleTime 20709000 # To system.physmem_0.memoryStateTime::IDLE 23500 # Time in different power states system.physmem_0.memoryStateTime::REF 780000 # Time in different power states system.physmem_0.memoryStateTime::SREF 0 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 2481750 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 2481250 # Time in different power states system.physmem_0.memoryStateTime::ACT 2828750 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 18291000 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 18291500 # Time in different power states system.physmem_1.actEnergy 642600 # Energy for activate commands per rank (pJ) system.physmem_1.preEnergy 333960 # Energy for precharge commands per rank (pJ) system.physmem_1.readEnergy 2591820 # Energy for read commands per rank (pJ) @@ -299,7 +299,7 @@ system.cpu.pwrStateResidencyTicks::ON 24405000 # Cu system.cpu.numCycles 48811 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 9089 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.icacheStallCycles 9088 # Number of cycles fetch is stalled on an Icache miss system.cpu.fetch.Insts 13001 # Number of instructions fetch has processed system.cpu.fetch.Branches 2188 # Number of branches that fetch encountered system.cpu.fetch.predictedBranches 841 # Number of branches that fetch has predicted taken @@ -308,11 +308,11 @@ system.cpu.fetch.SquashCycles 868 # Nu system.cpu.fetch.PendingTrapStallCycles 205 # Number of stall cycles due to pending traps system.cpu.fetch.CacheLines 2050 # Number of cache lines fetched system.cpu.fetch.IcacheSquashes 263 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 15175 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.856738 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.144886 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::samples 15174 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.856795 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.144946 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 11815 77.86% 77.86% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 11814 77.86% 77.86% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::1 1507 9.93% 87.79% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::2 111 0.73% 88.52% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::3 162 1.07% 89.59% # Number of instructions fetched each cycle (Total) @@ -324,11 +324,11 @@ system.cpu.fetch.rateDist::8 903 5.95% 100.00% # Nu system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 15175 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 15174 # Number of instructions fetched each cycle (Total) system.cpu.fetch.branchRate 0.044826 # Number of branch fetches per cycle system.cpu.fetch.rate 0.266354 # Number of inst fetches per cycle system.cpu.decode.IdleCycles 8420 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 3451 # Number of cycles decode is blocked +system.cpu.decode.BlockedCycles 3450 # Number of cycles decode is blocked system.cpu.decode.RunCycles 2768 # Number of cycles decode is running system.cpu.decode.UnblockCycles 142 # Number of cycles decode is unblocking system.cpu.decode.SquashCycles 394 # Number of cycles decode is squashing @@ -338,7 +338,7 @@ system.cpu.decode.DecodedInsts 12000 # Nu system.cpu.decode.SquashedInsts 160 # Number of squashed instructions handled by decode system.cpu.rename.SquashCycles 394 # Number of cycles rename is squashing system.cpu.rename.IdleCycles 8571 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 621 # Number of cycles rename is blocking +system.cpu.rename.BlockCycles 620 # Number of cycles rename is blocking system.cpu.rename.serializeStallCycles 1023 # count of cycles rename stalled for serializing inst system.cpu.rename.RunCycles 2740 # Number of cycles rename is running system.cpu.rename.UnblockCycles 1826 # Number of cycles rename is unblocking @@ -356,25 +356,25 @@ system.cpu.rename.UndoneMaps 3635 # Nu system.cpu.rename.serializingInsts 13 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 9 # count of temporary serializing insts renamed system.cpu.rename.skidInsts 323 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2470 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1160 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.insertedLoads 2468 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1158 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 6 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 2 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 9019 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 9014 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 11 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 8119 # Number of instructions issued +system.cpu.iq.iqInstsIssued 8118 # Number of instructions issued system.cpu.iq.iqSquashedInstsIssued 19 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 4030 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 2019 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedInstsExamined 4025 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 2012 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 15175 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.535025 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.265920 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 15174 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.534994 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.265800 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 11852 78.10% 78.10% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1334 8.79% 86.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 728 4.80% 91.69% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 454 2.99% 94.68% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 11850 78.09% 78.09% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1336 8.80% 86.90% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 728 4.80% 91.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 453 2.99% 94.68% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::4 341 2.25% 96.93% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::5 284 1.87% 98.80% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 110 0.72% 99.53% # Number of insts issued each cycle @@ -383,7 +383,7 @@ system.cpu.iq.issued_per_cycle::8 19 0.13% 100.00% # Nu system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 15175 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 15174 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 6 3.33% 3.33% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 3.33% # attempts to use FU when none available @@ -423,73 +423,73 @@ system.cpu.iq.fu_full::FloatMemWrite 0 0.00% 100.00% # at system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 4775 58.81% 58.81% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 4 0.05% 58.86% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 1 0.01% 58.87% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 58.90% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 58.90% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 58.90% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 58.90% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 58.90% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 58.90% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 58.90% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 58.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 58.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 58.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 58.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 58.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 58.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 58.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 58.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 58.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 58.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 58.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 58.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 58.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 58.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 58.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 58.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 58.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 58.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 58.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 58.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 58.90% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2274 28.01% 86.91% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 4775 58.82% 58.82% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 4 0.05% 58.87% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 1 0.01% 58.88% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 58.91% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 58.91% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 58.91% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 58.91% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 58.91% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 58.91% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 58.91% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 58.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 58.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 58.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 58.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 58.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 58.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 58.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 58.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 58.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 58.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 58.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 58.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 58.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 58.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 58.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 58.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 58.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 58.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 58.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 58.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 58.91% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2273 28.00% 86.91% # Type of FU issued system.cpu.iq.FU_type_0::MemWrite 1063 13.09% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::FloatMemRead 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::FloatMemWrite 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 8119 # Type of FU issued -system.cpu.iq.rate 0.166335 # Inst issue rate +system.cpu.iq.FU_type_0::total 8118 # Type of FU issued +system.cpu.iq.rate 0.166315 # Inst issue rate system.cpu.iq.fu_busy_cnt 180 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.022170 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 31608 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 13067 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 7338 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fu_busy_rate 0.022173 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 31605 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 13057 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 7337 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 4 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 2 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 2 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 8297 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 8296 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 2 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 78 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1335 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1333 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 10 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 259 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 257 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 25 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewSquashCycles 394 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 491 # Number of cycles IEW is blocking +system.cpu.iew.iewBlockCycles 490 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 74 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 10629 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispatchedInsts 10621 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 154 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2470 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1160 # Number of dispatched store instructions +system.cpu.iew.iewDispLoadInsts 2468 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1158 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 11 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 75 # Number of times the LSQ has become full, causing a stall @@ -497,22 +497,22 @@ system.cpu.iew.memOrderViolationEvents 10 # Nu system.cpu.iew.predictedTakenIncorrect 101 # Number of branches that were predicted taken incorrectly system.cpu.iew.predictedNotTakenIncorrect 338 # Number of branches that were predicted not taken incorrectly system.cpu.iew.branchMispredicts 439 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 7792 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 2130 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 327 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 7790 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 2129 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 328 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1599 # number of nop insts executed -system.cpu.iew.exec_refs 3179 # number of memory reference insts executed -system.cpu.iew.exec_branches 1364 # Number of branches executed +system.cpu.iew.exec_nop 1596 # number of nop insts executed +system.cpu.iew.exec_refs 3178 # number of memory reference insts executed +system.cpu.iew.exec_branches 1363 # Number of branches executed system.cpu.iew.exec_stores 1049 # Number of stores executed -system.cpu.iew.exec_rate 0.159636 # Inst execution rate -system.cpu.iew.wb_sent 7433 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 7340 # cumulative count of insts written-back +system.cpu.iew.exec_rate 0.159595 # Inst execution rate +system.cpu.iew.wb_sent 7432 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 7339 # cumulative count of insts written-back system.cpu.iew.wb_producers 2867 # num instructions producing a value -system.cpu.iew.wb_consumers 4275 # num instructions consuming a value -system.cpu.iew.wb_rate 0.150376 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.670643 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 4990 # The number of squashed insts skipped by commit +system.cpu.iew.wb_consumers 4274 # num instructions consuming a value +system.cpu.iew.wb_rate 0.150355 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.670800 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 4982 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 9 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 384 # The number of times a branch was mispredicted system.cpu.commit.committed_per_cycle::samples 14293 # Number of insts commited each cycle @@ -582,46 +582,46 @@ system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Cl system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 5640 # Class of committed instruction system.cpu.commit.bw_lim_events 102 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 24808 # The number of ROB reads -system.cpu.rob.rob_writes 22150 # The number of ROB writes +system.cpu.rob.rob_reads 24800 # The number of ROB reads +system.cpu.rob.rob_writes 22133 # The number of ROB writes system.cpu.timesIdled 264 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 33636 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.idleCycles 33637 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 4999 # Number of Instructions Simulated system.cpu.committedOps 4999 # Number of Ops (including micro ops) Simulated system.cpu.cpi 9.764153 # CPI: Cycles Per Instruction system.cpu.cpi_total 9.764153 # CPI: Total CPI of All Threads system.cpu.ipc 0.102415 # IPC: Instructions Per Cycle system.cpu.ipc_total 0.102415 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 10563 # number of integer regfile reads +system.cpu.int_regfile_reads 10560 # number of integer regfile reads system.cpu.int_regfile_writes 5141 # number of integer regfile writes system.cpu.fp_regfile_reads 3 # number of floating regfile reads system.cpu.fp_regfile_writes 1 # number of floating regfile writes system.cpu.misc_regfile_reads 161 # number of misc regfile reads system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 24405000 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 91.114118 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 2396 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 91.114159 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 2395 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 140 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 17.114286 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 17.107143 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 91.114118 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 91.114159 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.022245 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.022245 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 140 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 31 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 109 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.034180 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 5954 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 5954 # Number of data accesses +system.cpu.dcache.tags.tag_accesses 5952 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 5952 # Number of data accesses system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 24405000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 1839 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1839 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::cpu.data 1838 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1838 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 557 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 557 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 2396 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2396 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2396 # number of overall hits -system.cpu.dcache.overall_hits::total 2396 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 2395 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2395 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2395 # number of overall hits +system.cpu.dcache.overall_hits::total 2395 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 167 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 167 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 344 # number of WriteReq misses @@ -630,38 +630,38 @@ system.cpu.dcache.demand_misses::cpu.data 511 # n system.cpu.dcache.demand_misses::total 511 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 511 # number of overall misses system.cpu.dcache.overall_misses::total 511 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 12711500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 12711500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 12709500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 12709500 # number of ReadReq miss cycles system.cpu.dcache.WriteReq_miss_latency::cpu.data 34219499 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 34219499 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 46930999 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 46930999 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 46930999 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 46930999 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 2006 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 2006 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 46928999 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 46928999 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 46928999 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 46928999 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 2005 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 2005 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 901 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 901 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2907 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2907 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2907 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2907 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.083250 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.083250 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 2906 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2906 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2906 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2906 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.083292 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.083292 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.381798 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.381798 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.175783 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.175783 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.175783 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.175783 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 76116.766467 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 76116.766467 # average ReadReq miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.175843 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.175843 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.175843 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.175843 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 76104.790419 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 76104.790419 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 99475.287791 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 99475.287791 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 91841.485323 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 91841.485323 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 91841.485323 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 91841.485323 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 91837.571429 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 91837.571429 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 91837.571429 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 91837.571429 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 636 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 10 # number of cycles access was blocked @@ -684,30 +684,30 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 140 system.cpu.dcache.demand_mshr_misses::total 140 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 140 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 140 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 8095000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 8095000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 8094500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 8094500 # number of ReadReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4915999 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 4915999 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13010999 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 13010999 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13010999 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 13010999 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.044865 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.044865 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13010499 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 13010499 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13010499 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 13010499 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.044888 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.044888 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055494 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.055494 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.048160 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.048160 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.048160 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.048160 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 89944.444444 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 89944.444444 # average ReadReq mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.048176 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.048176 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.048176 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.048176 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 89938.888889 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 89938.888889 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 98319.980000 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 98319.980000 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 92935.707143 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 92935.707143 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 92935.707143 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 92935.707143 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 92932.135714 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 92932.135714 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 92932.135714 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 92932.135714 # average overall mshr miss latency system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 24405000 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 17 # number of replacements system.cpu.icache.tags.tagsinuse 160.115290 # Cycle average of tags in use @@ -781,33 +781,33 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 332 system.cpu.icache.demand_mshr_misses::total 332 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 332 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 332 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 28113000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 28113000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 28113000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 28113000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 28113000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 28113000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 28112000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 28112000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 28112000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 28112000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 28112000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 28112000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.161951 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.161951 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.161951 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.161951 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.161951 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.161951 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 84677.710843 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 84677.710843 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 84677.710843 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 84677.710843 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 84677.710843 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 84677.710843 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 84674.698795 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 84674.698795 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 84674.698795 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 84674.698795 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 84674.698795 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 84674.698795 # average overall mshr miss latency system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 24405000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 253.317608 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 253.317649 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 20 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 469 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.042644 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.tags.occ_blocks::cpu.inst 162.143256 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 91.174352 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 91.174392 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004948 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.002782 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.007731 # Average percentage of cache occupancy @@ -840,16 +840,16 @@ system.cpu.l2cache.overall_misses::cpu.data 140 # system.cpu.l2cache.overall_misses::total 469 # number of overall misses system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4840000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 4840000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 27582000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 27582000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 7957000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 7957000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 27582000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 12797000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 40379000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 27582000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 12797000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 40379000 # number of overall miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 27581000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 27581000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 7956500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 7956500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 27581000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 12796500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 40377500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 27581000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 12796500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 40377500 # number of overall miss cycles system.cpu.l2cache.WritebackClean_accesses::writebacks 17 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::total 17 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 50 # number of ReadExReq accesses(hits+misses) @@ -878,16 +878,16 @@ system.cpu.l2cache.overall_miss_rate::cpu.data 1 system.cpu.l2cache.overall_miss_rate::total 0.993644 # miss rate for overall accesses system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 96800 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 96800 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 83835.866261 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 83835.866261 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 88411.111111 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 88411.111111 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 83835.866261 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 91407.142857 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 86095.948827 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 83835.866261 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 91407.142857 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 86095.948827 # average overall miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 83832.826748 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 83832.826748 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 88405.555556 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 88405.555556 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 83832.826748 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 91403.571429 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 86092.750533 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 83832.826748 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 91403.571429 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 86092.750533 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -908,16 +908,16 @@ system.cpu.l2cache.overall_mshr_misses::cpu.data 140 system.cpu.l2cache.overall_mshr_misses::total 469 # number of overall MSHR misses system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4340000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4340000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 24292000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 24292000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 7057000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 7057000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 24292000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11397000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 35689000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 24292000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11397000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 35689000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 24291000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 24291000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 7056500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 7056500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 24291000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11396500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 35687500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 24291000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11396500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 35687500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.990964 # mshr miss rate for ReadCleanReq accesses @@ -932,16 +932,16 @@ system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 system.cpu.l2cache.overall_mshr_miss_rate::total 0.993644 # mshr miss rate for overall accesses system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 86800 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 86800 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 73835.866261 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 73835.866261 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 78411.111111 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 78411.111111 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 73835.866261 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 81407.142857 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 76095.948827 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 73835.866261 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 81407.142857 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 76095.948827 # average overall mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 73832.826748 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 73832.826748 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 78405.555556 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 78405.555556 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 73832.826748 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 81403.571429 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 76092.750533 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 73832.826748 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 81403.571429 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 76092.750533 # average overall mshr miss latency system.cpu.toL2Bus.snoop_filter.tot_requests 489 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 17 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. @@ -1007,7 +1007,7 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 469 # Request fanout histogram -system.membus.reqLayer0.occupancy 581500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 581000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.4 # Layer utilization (%) system.membus.respLayer1.occupancy 2488500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 10.2 # Layer utilization (%) diff --git a/tests/quick/se/00.hello/ref/power/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/power/linux/o3-timing/config.ini index 08a1c6669..70198a6d7 100644 --- a/tests/quick/se/00.hello/ref/power/linux/o3-timing/config.ini +++ b/tests/quick/se/00.hello/ref/power/linux/o3-timing/config.ini @@ -178,10 +178,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=false max_miss_count=0 mshrs=4 @@ -195,6 +195,7 @@ response_latency=2 sequential_access=false size=262144 system=system +tag_latency=2 tags=system.cpu.dcache.tags tgts_per_mshr=20 write_buffers=8 @@ -207,15 +208,16 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=262144 +tag_latency=2 [system.cpu.dtb] type=PowerTLB @@ -293,10 +295,10 @@ pipelined=true [system.cpu.fuPool.FUList3] type=FUDesc -children=opList0 opList1 opList2 +children=opList0 opList1 opList2 opList3 opList4 count=2 eventq_index=0 -opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 +opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 system.cpu.fuPool.FUList3.opList3 system.cpu.fuPool.FUList3.opList4 [system.cpu.fuPool.FUList3.opList0] type=OpDesc @@ -308,11 +310,25 @@ pipelined=true [system.cpu.fuPool.FUList3.opList1] type=OpDesc eventq_index=0 +opClass=FloatMultAcc +opLat=5 +pipelined=true + +[system.cpu.fuPool.FUList3.opList2] +type=OpDesc +eventq_index=0 +opClass=FloatMisc +opLat=3 +pipelined=true + +[system.cpu.fuPool.FUList3.opList3] +type=OpDesc +eventq_index=0 opClass=FloatDiv opLat=12 pipelined=false -[system.cpu.fuPool.FUList3.opList2] +[system.cpu.fuPool.FUList3.opList4] type=OpDesc eventq_index=0 opClass=FloatSqrt @@ -321,18 +337,25 @@ pipelined=false [system.cpu.fuPool.FUList4] type=FUDesc -children=opList +children=opList0 opList1 count=0 eventq_index=0 -opList=system.cpu.fuPool.FUList4.opList +opList=system.cpu.fuPool.FUList4.opList0 system.cpu.fuPool.FUList4.opList1 -[system.cpu.fuPool.FUList4.opList] +[system.cpu.fuPool.FUList4.opList0] type=OpDesc eventq_index=0 opClass=MemRead opLat=1 pipelined=true +[system.cpu.fuPool.FUList4.opList1] +type=OpDesc +eventq_index=0 +opClass=FloatMemRead +opLat=1 +pipelined=true + [system.cpu.fuPool.FUList5] type=FUDesc children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 @@ -482,24 +505,31 @@ pipelined=true [system.cpu.fuPool.FUList6] type=FUDesc -children=opList +children=opList0 opList1 count=0 eventq_index=0 -opList=system.cpu.fuPool.FUList6.opList +opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1 -[system.cpu.fuPool.FUList6.opList] +[system.cpu.fuPool.FUList6.opList0] type=OpDesc eventq_index=0 opClass=MemWrite opLat=1 pipelined=true +[system.cpu.fuPool.FUList6.opList1] +type=OpDesc +eventq_index=0 +opClass=FloatMemWrite +opLat=1 +pipelined=true + [system.cpu.fuPool.FUList7] type=FUDesc -children=opList0 opList1 +children=opList0 opList1 opList2 opList3 count=4 eventq_index=0 -opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 +opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 system.cpu.fuPool.FUList7.opList2 system.cpu.fuPool.FUList7.opList3 [system.cpu.fuPool.FUList7.opList0] type=OpDesc @@ -515,6 +545,20 @@ opClass=MemWrite opLat=1 pipelined=true +[system.cpu.fuPool.FUList7.opList2] +type=OpDesc +eventq_index=0 +opClass=FloatMemRead +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList7.opList3] +type=OpDesc +eventq_index=0 +opClass=FloatMemWrite +opLat=1 +pipelined=true + [system.cpu.fuPool.FUList8] type=FUDesc children=opList @@ -536,10 +580,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=true max_miss_count=0 mshrs=4 @@ -553,6 +597,7 @@ response_latency=2 sequential_access=false size=131072 system=system +tag_latency=2 tags=system.cpu.icache.tags tgts_per_mshr=20 write_buffers=8 @@ -565,15 +610,16 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=131072 +tag_latency=2 [system.cpu.interrupts] type=PowerInterrupts @@ -595,10 +641,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0 assoc=8 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=20 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=20 is_read_only=false max_miss_count=0 mshrs=20 @@ -612,6 +658,7 @@ response_latency=20 sequential_access=false size=2097152 system=system +tag_latency=20 tags=system.cpu.l2cache.tags tgts_per_mshr=12 write_buffers=8 @@ -624,15 +671,16 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=20 default_p_state=UNDEFINED eventq_index=0 -hit_latency=20 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=2097152 +tag_latency=20 [system.cpu.toL2Bus] type=CoherentXBar @@ -677,7 +725,7 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/test-progs/hello/bin/power/linux/hello +executable=/dist/m5/regression/test-progs/hello/bin/power/linux/hello gid=100 input=cin kvmInSE=false diff --git a/tests/quick/se/00.hello/ref/power/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/power/linux/o3-timing/simout index 7df757697..5b262649f 100755 --- a/tests/quick/se/00.hello/ref/power/linux/o3-timing/simout +++ b/tests/quick/se/00.hello/ref/power/linux/o3-timing/simout @@ -3,10 +3,10 @@ Redirecting stderr to build/POWER/tests/opt/quick/se/00.hello/power/linux/o3-tim gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Oct 13 2016 20:40:28 -gem5 started Oct 13 2016 20:40:51 -gem5 executing on e108600-lin, pid 9917 -command line: /work/curdun01/gem5-external.hg/build/POWER/gem5.opt -d build/POWER/tests/opt/quick/se/00.hello/power/linux/o3-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/00.hello/power/linux/o3-timing +gem5 compiled Nov 29 2016 18:37:43 +gem5 started Nov 29 2016 18:37:59 +gem5 executing on zizzer, pid 53433 +command line: /z/powerjg/gem5-upstream/build/POWER/gem5.opt -d build/POWER/tests/opt/quick/se/00.hello/power/linux/o3-timing -re /z/powerjg/gem5-upstream/tests/testing/../run.py quick/se/00.hello/power/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt index fbc31e89b..1c774fd71 100644 --- a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000021 # Nu sim_ticks 21268000 # Number of ticks simulated final_tick 21268000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 133148 # Simulator instruction rate (inst/s) -host_op_rate 133114 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 488684971 # Simulator tick rate (ticks/s) -host_mem_usage 249832 # Number of bytes of host memory used -host_seconds 0.04 # Real time elapsed on the host +host_inst_rate 49400 # Simulator instruction rate (inst/s) +host_op_rate 49392 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 181337178 # Simulator tick rate (ticks/s) +host_mem_usage 231948 # Number of bytes of host memory used +host_seconds 0.12 # Real time elapsed on the host sim_insts 5792 # Number of instructions simulated sim_ops 5792 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -299,7 +299,7 @@ system.cpu.pwrStateResidencyTicks::ON 21268000 # Cu system.cpu.numCycles 42537 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 7672 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.icacheStallCycles 7674 # Number of cycles fetch is stalled on an Icache miss system.cpu.fetch.Insts 13369 # Number of instructions fetch has processed system.cpu.fetch.Branches 2411 # Number of branches that fetch encountered system.cpu.fetch.predictedBranches 939 # Number of branches that fetch has predicted taken @@ -310,26 +310,26 @@ system.cpu.fetch.PendingTrapStallCycles 146 # Nu system.cpu.fetch.IcacheWaitRetryStallCycles 22 # Number of stall cycles due to full MSHR system.cpu.fetch.CacheLines 1861 # Number of cache lines fetched system.cpu.fetch.IcacheSquashes 290 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 12418 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.076582 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.475981 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::samples 12420 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.076409 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.475819 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 10084 81.20% 81.20% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 10086 81.21% 81.21% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::1 166 1.34% 82.54% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 214 1.72% 84.26% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 214 1.72% 84.27% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::3 147 1.18% 85.45% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::4 241 1.94% 87.39% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::5 150 1.21% 88.60% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::6 280 2.25% 90.85% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 148 1.19% 92.04% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 988 7.96% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 148 1.19% 92.05% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 988 7.95% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 12418 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 12420 # Number of instructions fetched each cycle (Total) system.cpu.fetch.branchRate 0.056680 # Number of branch fetches per cycle system.cpu.fetch.rate 0.314291 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 7245 # Number of cycles decode is idle +system.cpu.decode.IdleCycles 7247 # Number of cycles decode is idle system.cpu.decode.BlockedCycles 2821 # Number of cycles decode is blocked system.cpu.decode.RunCycles 1946 # Number of cycles decode is running system.cpu.decode.UnblockCycles 130 # Number of cycles decode is unblocking @@ -339,7 +339,7 @@ system.cpu.decode.BranchMispred 149 # Nu system.cpu.decode.DecodedInsts 11479 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 451 # Number of squashed instructions handled by decode system.cpu.rename.SquashCycles 276 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 7413 # Number of cycles rename is idle +system.cpu.rename.IdleCycles 7415 # Number of cycles rename is idle system.cpu.rename.BlockCycles 800 # Number of cycles rename is blocking system.cpu.rename.serializeStallCycles 463 # count of cycles rename stalled for serializing inst system.cpu.rename.RunCycles 1897 # Number of cycles rename is running @@ -368,11 +368,11 @@ system.cpu.iq.iqSquashedInstsIssued 53 # Nu system.cpu.iq.iqSquashedInstsExamined 4442 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu.iq.iqSquashedOperandsExamined 3474 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 47 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 12418 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.709293 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.511827 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 12420 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.709179 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.511732 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 9303 74.92% 74.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 9305 74.92% 74.92% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::1 969 7.80% 82.72% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::2 656 5.28% 88.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::3 462 3.72% 91.72% # Number of insts issued each cycle @@ -384,7 +384,7 @@ system.cpu.iq.issued_per_cycle::8 30 0.24% 100.00% # Nu system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 12418 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 12420 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 12 6.06% 6.06% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 6.06% # attempts to use FU when none available @@ -465,7 +465,7 @@ system.cpu.iq.FU_type_0::total 8808 # Ty system.cpu.iq.rate 0.207067 # Inst issue rate system.cpu.iq.fu_busy_cnt 198 # FU busy when requested system.cpu.iq.fu_busy_rate 0.022480 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 30218 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_reads 30220 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_writes 14647 # Number of integer instruction queue writes system.cpu.iq.int_inst_queue_wakeup_accesses 8115 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 67 # Number of floating instruction queue reads @@ -516,14 +516,14 @@ system.cpu.iew.wb_fanout 0.621403 # av system.cpu.commit.commitSquashedInsts 4444 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 16 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 270 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 11716 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.494367 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.358573 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 11718 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.494282 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.358473 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 9551 81.52% 81.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 850 7.26% 88.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 527 4.50% 93.27% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 215 1.84% 95.11% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 9553 81.52% 81.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 850 7.25% 88.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 527 4.50% 93.28% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 215 1.83% 95.11% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::4 176 1.50% 96.61% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::5 112 0.96% 97.57% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::6 126 1.08% 98.64% # Number of insts commited each cycle @@ -532,7 +532,7 @@ system.cpu.commit.committed_per_cycle::8 110 0.94% 100.00% # Nu system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 11716 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 11718 # Number of insts commited each cycle system.cpu.commit.committedInsts 5792 # Number of instructions committed system.cpu.commit.committedOps 5792 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -583,10 +583,10 @@ system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Cl system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 5792 # Class of committed instruction system.cpu.commit.bw_lim_events 110 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 21842 # The number of ROB reads +system.cpu.rob.rob_reads 21844 # The number of ROB reads system.cpu.rob.rob_writes 21175 # The number of ROB writes system.cpu.timesIdled 228 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 30119 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.idleCycles 30117 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 5792 # Number of Instructions Simulated system.cpu.committedOps 5792 # Number of Ops (including micro ops) Simulated system.cpu.cpi 7.344095 # CPI: Cycles Per Instruction diff --git a/tests/quick/se/00.hello/ref/riscv/linux/minor-timing/config.ini b/tests/quick/se/00.hello/ref/riscv/linux/minor-timing/config.ini new file mode 100644 index 000000000..d51a8d121 --- /dev/null +++ b/tests/quick/se/00.hello/ref/riscv/linux/minor-timing/config.ini @@ -0,0 +1,902 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain +boot_osflags=a +cache_line_size=64 +clk_domain=system.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +exit_on_work_items=false +init_param=0 +kernel= +kernel_addr_check=true +load_addr_mask=1099511627775 +load_offset=0 +mem_mode=timing +mem_ranges= +memories=system.physmem +mmap_using_noreserve=false +multi_thread=false +num_work_ids=16 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +readfile= +symbolfile= +thermal_components= +thermal_model=Null +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=MinorCPU +children=branchPred dcache dtb executeFuncUnits icache interrupts isa itb l2cache toL2Bus tracer workload +branchPred=system.cpu.branchPred +checker=Null +clk_domain=system.cpu_clk_domain +cpu_id=0 +decodeCycleInput=true +decodeInputBufferSize=3 +decodeInputWidth=2 +decodeToExecuteForwardDelay=1 +default_p_state=UNDEFINED +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +enableIdling=true +eventq_index=0 +executeAllowEarlyMemoryIssue=true +executeBranchDelay=1 +executeCommitLimit=2 +executeCycleInput=true +executeFuncUnits=system.cpu.executeFuncUnits +executeInputBufferSize=7 +executeInputWidth=2 +executeIssueLimit=2 +executeLSQMaxStoreBufferStoresPerCycle=2 +executeLSQRequestsQueueSize=1 +executeLSQStoreBufferSize=5 +executeLSQTransfersQueueSize=2 +executeMaxAccessesInMemory=2 +executeMemoryCommitLimit=1 +executeMemoryIssueLimit=1 +executeMemoryWidth=0 +executeSetTraceTimeOnCommit=true +executeSetTraceTimeOnIssue=false +fetch1FetchLimit=1 +fetch1LineSnapWidth=0 +fetch1LineWidth=0 +fetch1ToFetch2BackwardDelay=1 +fetch1ToFetch2ForwardDelay=1 +fetch2CycleInput=true +fetch2InputBufferSize=2 +fetch2ToDecodeForwardDelay=1 +function_trace=false +function_trace_start=0 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +profile=0 +progress_interval=0 +simpoint_start_insts= +socket_id=0 +switched_out=false +system=system +threadPolicy=RoundRobin +tracer=system.cpu.tracer +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.branchPred] +type=TournamentBP +BTBEntries=4096 +BTBTagSize=16 +RASSize=16 +choiceCtrBits=2 +choicePredictorSize=8192 +eventq_index=0 +globalCtrBits=2 +globalPredictorSize=8192 +indirectHashGHR=true +indirectHashTargets=true +indirectPathLength=3 +indirectSets=256 +indirectTagSize=16 +indirectWays=2 +instShiftAmt=2 +localCtrBits=2 +localHistoryTableSize=2048 +localPredictorSize=2048 +numThreads=1 +useIndirect=true + +[system.cpu.dcache] +type=Cache +children=tags +addr_ranges=0:18446744073709551615:0:0:0:0 +assoc=2 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +data_latency=2 +default_p_state=UNDEFINED +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=4 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=262144 +system=system +tag_latency=2 +tags=system.cpu.dcache.tags +tgts_per_mshr=20 +write_buffers=8 +writeback_clean=false +cpu_side=system.cpu.dcache_port +mem_side=system.cpu.toL2Bus.slave[1] + +[system.cpu.dcache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +data_latency=2 +default_p_state=UNDEFINED +eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +sequential_access=false +size=262144 +tag_latency=2 + +[system.cpu.dtb] +type=RiscvTLB +eventq_index=0 +size=64 + +[system.cpu.executeFuncUnits] +type=MinorFUPool +children=funcUnits0 funcUnits1 funcUnits2 funcUnits3 funcUnits4 funcUnits5 funcUnits6 +eventq_index=0 +funcUnits=system.cpu.executeFuncUnits.funcUnits0 system.cpu.executeFuncUnits.funcUnits1 system.cpu.executeFuncUnits.funcUnits2 system.cpu.executeFuncUnits.funcUnits3 system.cpu.executeFuncUnits.funcUnits4 system.cpu.executeFuncUnits.funcUnits5 system.cpu.executeFuncUnits.funcUnits6 + +[system.cpu.executeFuncUnits.funcUnits0] +type=MinorFU +children=opClasses timings +cantForwardFromFUIndices= +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses +opLat=3 +timings=system.cpu.executeFuncUnits.funcUnits0.timings + +[system.cpu.executeFuncUnits.funcUnits0.opClasses] +type=MinorOpClassSet +children=opClasses +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses + +[system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses] +type=MinorOpClass +eventq_index=0 +opClass=IntAlu + +[system.cpu.executeFuncUnits.funcUnits0.timings] +type=MinorFUTiming +children=opClasses +description=Int +eventq_index=0 +extraAssumedLat=0 +extraCommitLat=0 +extraCommitLatExpr=Null +mask=0 +match=0 +opClasses=system.cpu.executeFuncUnits.funcUnits0.timings.opClasses +srcRegsRelativeLats=2 +suppress=false + +[system.cpu.executeFuncUnits.funcUnits0.timings.opClasses] +type=MinorOpClassSet +eventq_index=0 +opClasses= + +[system.cpu.executeFuncUnits.funcUnits1] +type=MinorFU +children=opClasses timings +cantForwardFromFUIndices= +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses +opLat=3 +timings=system.cpu.executeFuncUnits.funcUnits1.timings + +[system.cpu.executeFuncUnits.funcUnits1.opClasses] +type=MinorOpClassSet +children=opClasses +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses + +[system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses] +type=MinorOpClass +eventq_index=0 +opClass=IntAlu + +[system.cpu.executeFuncUnits.funcUnits1.timings] +type=MinorFUTiming +children=opClasses +description=Int +eventq_index=0 +extraAssumedLat=0 +extraCommitLat=0 +extraCommitLatExpr=Null +mask=0 +match=0 +opClasses=system.cpu.executeFuncUnits.funcUnits1.timings.opClasses +srcRegsRelativeLats=2 +suppress=false + +[system.cpu.executeFuncUnits.funcUnits1.timings.opClasses] +type=MinorOpClassSet +eventq_index=0 +opClasses= + +[system.cpu.executeFuncUnits.funcUnits2] +type=MinorFU +children=opClasses timings +cantForwardFromFUIndices= +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits2.opClasses +opLat=3 +timings=system.cpu.executeFuncUnits.funcUnits2.timings + +[system.cpu.executeFuncUnits.funcUnits2.opClasses] +type=MinorOpClassSet +children=opClasses +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses + +[system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses] +type=MinorOpClass +eventq_index=0 +opClass=IntMult + +[system.cpu.executeFuncUnits.funcUnits2.timings] +type=MinorFUTiming +children=opClasses +description=Mul +eventq_index=0 +extraAssumedLat=0 +extraCommitLat=0 +extraCommitLatExpr=Null +mask=0 +match=0 +opClasses=system.cpu.executeFuncUnits.funcUnits2.timings.opClasses +srcRegsRelativeLats=0 +suppress=false + +[system.cpu.executeFuncUnits.funcUnits2.timings.opClasses] +type=MinorOpClassSet +eventq_index=0 +opClasses= + +[system.cpu.executeFuncUnits.funcUnits3] +type=MinorFU +children=opClasses +cantForwardFromFUIndices= +eventq_index=0 +issueLat=9 +opClasses=system.cpu.executeFuncUnits.funcUnits3.opClasses +opLat=9 +timings= + +[system.cpu.executeFuncUnits.funcUnits3.opClasses] +type=MinorOpClassSet +children=opClasses +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses + +[system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses] +type=MinorOpClass +eventq_index=0 +opClass=IntDiv + +[system.cpu.executeFuncUnits.funcUnits4] +type=MinorFU +children=opClasses timings +cantForwardFromFUIndices= +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses +opLat=6 +timings=system.cpu.executeFuncUnits.funcUnits4.timings + +[system.cpu.executeFuncUnits.funcUnits4.opClasses] +type=MinorOpClassSet +children=opClasses00 opClasses01 opClasses02 opClasses03 opClasses04 opClasses05 opClasses06 opClasses07 opClasses08 opClasses09 opClasses10 opClasses11 opClasses12 opClasses13 opClasses14 opClasses15 opClasses16 opClasses17 opClasses18 opClasses19 opClasses20 opClasses21 opClasses22 opClasses23 opClasses24 opClasses25 opClasses26 opClasses27 +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses26 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses27 + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00] +type=MinorOpClass +eventq_index=0 +opClass=FloatAdd + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01] +type=MinorOpClass +eventq_index=0 +opClass=FloatCmp + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02] +type=MinorOpClass +eventq_index=0 +opClass=FloatCvt + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03] +type=MinorOpClass +eventq_index=0 +opClass=FloatMisc + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04] +type=MinorOpClass +eventq_index=0 +opClass=FloatMult + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05] +type=MinorOpClass +eventq_index=0 +opClass=FloatMultAcc + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06] +type=MinorOpClass +eventq_index=0 +opClass=FloatDiv + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07] +type=MinorOpClass +eventq_index=0 +opClass=FloatSqrt + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08] +type=MinorOpClass +eventq_index=0 +opClass=SimdAdd + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09] +type=MinorOpClass +eventq_index=0 +opClass=SimdAddAcc + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10] +type=MinorOpClass +eventq_index=0 +opClass=SimdAlu + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11] +type=MinorOpClass +eventq_index=0 +opClass=SimdCmp + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12] +type=MinorOpClass +eventq_index=0 +opClass=SimdCvt + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13] +type=MinorOpClass +eventq_index=0 +opClass=SimdMisc + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14] +type=MinorOpClass +eventq_index=0 +opClass=SimdMult + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15] +type=MinorOpClass +eventq_index=0 +opClass=SimdMultAcc + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16] +type=MinorOpClass +eventq_index=0 +opClass=SimdShift + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17] +type=MinorOpClass +eventq_index=0 +opClass=SimdShiftAcc + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18] +type=MinorOpClass +eventq_index=0 +opClass=SimdSqrt + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatAdd + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatAlu + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatCmp + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatCvt + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatDiv + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatMisc + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatMult + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses26] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatMultAcc + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses27] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatSqrt + +[system.cpu.executeFuncUnits.funcUnits4.timings] +type=MinorFUTiming +children=opClasses +description=FloatSimd +eventq_index=0 +extraAssumedLat=0 +extraCommitLat=0 +extraCommitLatExpr=Null +mask=0 +match=0 +opClasses=system.cpu.executeFuncUnits.funcUnits4.timings.opClasses +srcRegsRelativeLats=2 +suppress=false + +[system.cpu.executeFuncUnits.funcUnits4.timings.opClasses] +type=MinorOpClassSet +eventq_index=0 +opClasses= + +[system.cpu.executeFuncUnits.funcUnits5] +type=MinorFU +children=opClasses timings +cantForwardFromFUIndices= +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses +opLat=1 +timings=system.cpu.executeFuncUnits.funcUnits5.timings + +[system.cpu.executeFuncUnits.funcUnits5.opClasses] +type=MinorOpClassSet +children=opClasses0 opClasses1 opClasses2 opClasses3 +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1 system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses2 system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses3 + +[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0] +type=MinorOpClass +eventq_index=0 +opClass=MemRead + +[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1] +type=MinorOpClass +eventq_index=0 +opClass=MemWrite + +[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses2] +type=MinorOpClass +eventq_index=0 +opClass=FloatMemRead + +[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses3] +type=MinorOpClass +eventq_index=0 +opClass=FloatMemWrite + +[system.cpu.executeFuncUnits.funcUnits5.timings] +type=MinorFUTiming +children=opClasses +description=Mem +eventq_index=0 +extraAssumedLat=2 +extraCommitLat=0 +extraCommitLatExpr=Null +mask=0 +match=0 +opClasses=system.cpu.executeFuncUnits.funcUnits5.timings.opClasses +srcRegsRelativeLats=1 +suppress=false + +[system.cpu.executeFuncUnits.funcUnits5.timings.opClasses] +type=MinorOpClassSet +eventq_index=0 +opClasses= + +[system.cpu.executeFuncUnits.funcUnits6] +type=MinorFU +children=opClasses +cantForwardFromFUIndices= +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses +opLat=1 +timings= + +[system.cpu.executeFuncUnits.funcUnits6.opClasses] +type=MinorOpClassSet +children=opClasses0 opClasses1 +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1 + +[system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0] +type=MinorOpClass +eventq_index=0 +opClass=IprAccess + +[system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1] +type=MinorOpClass +eventq_index=0 +opClass=InstPrefetch + +[system.cpu.icache] +type=Cache +children=tags +addr_ranges=0:18446744073709551615:0:0:0:0 +assoc=2 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +data_latency=2 +default_p_state=UNDEFINED +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=true +max_miss_count=0 +mshrs=4 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=131072 +system=system +tag_latency=2 +tags=system.cpu.icache.tags +tgts_per_mshr=20 +write_buffers=8 +writeback_clean=true +cpu_side=system.cpu.icache_port +mem_side=system.cpu.toL2Bus.slave[0] + +[system.cpu.icache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +data_latency=2 +default_p_state=UNDEFINED +eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +sequential_access=false +size=131072 +tag_latency=2 + +[system.cpu.interrupts] +type=RiscvInterrupts +eventq_index=0 + +[system.cpu.isa] +type=RiscvISA +eventq_index=0 + +[system.cpu.itb] +type=RiscvTLB +eventq_index=0 +size=64 + +[system.cpu.l2cache] +type=Cache +children=tags +addr_ranges=0:18446744073709551615:0:0:0:0 +assoc=8 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +data_latency=20 +default_p_state=UNDEFINED +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=20 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +prefetch_on_access=false +prefetcher=Null +response_latency=20 +sequential_access=false +size=2097152 +system=system +tag_latency=20 +tags=system.cpu.l2cache.tags +tgts_per_mshr=12 +write_buffers=8 +writeback_clean=false +cpu_side=system.cpu.toL2Bus.master[0] +mem_side=system.membus.slave[1] + +[system.cpu.l2cache.tags] +type=LRU +assoc=8 +block_size=64 +clk_domain=system.cpu_clk_domain +data_latency=20 +default_p_state=UNDEFINED +eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +sequential_access=false +size=2097152 +tag_latency=20 + +[system.cpu.toL2Bus] +type=CoherentXBar +children=snoop_filter +clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED +eventq_index=0 +forward_latency=0 +frontend_latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +point_of_coherency=false +power_model=Null +response_latency=1 +snoop_filter=system.cpu.toL2Bus.snoop_filter +snoop_response_latency=1 +system=system +use_default_range=false +width=32 +master=system.cpu.l2cache.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side + +[system.cpu.toL2Bus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=0 +max_capacity=8388608 +system=system + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=LiveProcess +cmd=hello +cwd= +drivers= +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable=/z/powerjg/gem5-upstream/tests/test-progs/hello/bin/riscv/linux/hello +gid=100 +input=cin +kvmInSE=false +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=0 +system=system +uid=100 +useArchPT=false + +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000000 + +[system.membus] +type=CoherentXBar +children=snoop_filter +clk_domain=system.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +forward_latency=4 +frontend_latency=3 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +point_of_coherency=true +power_model=Null +response_latency=2 +snoop_filter=system.membus.snoop_filter +snoop_response_latency=4 +system=system +use_default_range=false +width=16 +master=system.physmem.port +slave=system.system_port system.cpu.l2cache.mem_side + +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + +[system.physmem] +type=DRAMCtrl +IDD0=0.055000 +IDD02=0.000000 +IDD2N=0.032000 +IDD2N2=0.000000 +IDD2P0=0.000000 +IDD2P02=0.000000 +IDD2P1=0.032000 +IDD2P12=0.000000 +IDD3N=0.038000 +IDD3N2=0.000000 +IDD3P0=0.000000 +IDD3P02=0.000000 +IDD3P1=0.038000 +IDD3P12=0.000000 +IDD4R=0.157000 +IDD4R2=0.000000 +IDD4W=0.125000 +IDD4W2=0.000000 +IDD5=0.235000 +IDD52=0.000000 +IDD6=0.020000 +IDD62=0.000000 +VDD=1.500000 +VDD2=0.000000 +activation_limit=4 +addr_mapping=RoRaBaCoCh +bank_groups_per_rank=0 +banks_per_rank=8 +burst_length=8 +channels=1 +clk_domain=system.clk_domain +conf_table_reported=true +default_p_state=UNDEFINED +device_bus_width=8 +device_rowbuffer_size=1024 +device_size=536870912 +devices_per_rank=8 +dll=true +eventq_index=0 +in_addr_map=true +kvm_map=true +max_accesses_per_row=16 +mem_sched_policy=frfcfs +min_writes_per_switch=16 +null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +page_policy=open_adaptive +power_model=Null +range=0:134217727:0:0:0:0 +ranks_per_channel=2 +read_buffer_size=32 +static_backend_latency=10000 +static_frontend_latency=10000 +tBURST=5000 +tCCD_L=0 +tCK=1250 +tCL=13750 +tCS=2500 +tRAS=35000 +tRCD=13750 +tREFI=7800000 +tRFC=260000 +tRP=13750 +tRRD=6000 +tRRD_L=0 +tRTP=7500 +tRTW=2500 +tWR=15000 +tWTR=7500 +tXAW=30000 +tXP=6000 +tXPDLL=0 +tXS=270000 +tXSDLL=0 +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 +port=system.membus.master[0] + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + diff --git a/tests/quick/se/00.hello/ref/riscv/linux/minor-timing/config.json b/tests/quick/se/00.hello/ref/riscv/linux/minor-timing/config.json new file mode 100644 index 000000000..0bb65c740 --- /dev/null +++ b/tests/quick/se/00.hello/ref/riscv/linux/minor-timing/config.json @@ -0,0 +1,1211 @@ +{ + "name": null, + "sim_quantum": 0, + "system": { + "kernel": "", + "mmap_using_noreserve": false, + "kernel_addr_check": true, + "membus": { + "point_of_coherency": true, + "system": "system", + "response_latency": 2, + "cxx_class": "CoherentXBar", + "forward_latency": 4, + "clk_domain": "system.clk_domain", + "width": 16, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "master": { + "peer": [ + "system.physmem.port" + ], + "role": "MASTER" + }, + "type": "CoherentXBar", + "frontend_latency": 3, + "slave": { + "peer": [ + "system.system_port", + "system.cpu.l2cache.mem_side" + ], + "role": "SLAVE" + }, + "p_state_clk_gate_min": 1000, + "snoop_filter": { + "name": "snoop_filter", + "system": "system", + "max_capacity": 8388608, + "eventq_index": 0, + "cxx_class": "SnoopFilter", + "path": "system.membus.snoop_filter", + "type": "SnoopFilter", + "lookup_latency": 1 + }, + "power_model": null, + "path": "system.membus", + "snoop_response_latency": 4, + "name": "membus", + "p_state_clk_gate_bins": 20, + "use_default_range": false + }, + "symbolfile": "", + "readfile": "", + "thermal_model": null, + "cxx_class": "System", + "work_begin_cpu_id_exit": -1, + "load_offset": 0, + "work_begin_exit_count": 0, + "p_state_clk_gate_min": 1000, + "memories": [ + "system.physmem" + ], + "work_begin_ckpt_count": 0, + "clk_domain": { + "name": "clk_domain", + "clock": [ + 1000 + ], + "init_perf_level": 0, + "voltage_domain": "system.voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "mem_ranges": [], + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "dvfs_handler": { + "enable": false, + "name": "dvfs_handler", + "sys_clk_domain": "system.clk_domain", + "transition_latency": 100000000, + "eventq_index": 0, + "cxx_class": "DVFSHandler", + "domains": [], + "path": "system.dvfs_handler", + "type": "DVFSHandler" + }, + "work_end_exit_count": 0, + "type": "System", + "voltage_domain": { + "name": "voltage_domain", + "eventq_index": 0, + "voltage": [ + "1.0" + ], + "cxx_class": "VoltageDomain", + "path": "system.voltage_domain", + "type": "VoltageDomain" + }, + "cache_line_size": 64, + "boot_osflags": "a", + "system_port": { + "peer": "system.membus.slave[0]", + "role": "MASTER" + }, + "physmem": { + "static_frontend_latency": 10000, + "tRFC": 260000, + "activation_limit": 4, + "in_addr_map": true, + "IDD3N2": "0.0", + "tWTR": 7500, + "IDD52": "0.0", + "clk_domain": "system.clk_domain", + "channels": 1, + "write_buffer_size": 64, + "device_bus_width": 8, + "VDD": "1.5", + "write_high_thresh_perc": 85, + "cxx_class": "DRAMCtrl", + "bank_groups_per_rank": 0, + "IDD2N2": "0.0", + "port": { + "peer": "system.membus.master[0]", + "role": "SLAVE" + }, + "tCCD_L": 0, + "IDD2N": "0.032", + "p_state_clk_gate_min": 1000, + "null": false, + "IDD2P1": "0.032", + "eventq_index": 0, + "tRRD": 6000, + "tRTW": 2500, + "IDD4R": "0.157", + "burst_length": 8, + "tRTP": 7500, + "IDD4W": "0.125", + "tWR": 15000, + "banks_per_rank": 8, + "devices_per_rank": 8, + "IDD2P02": "0.0", + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "IDD6": "0.02", + "IDD5": "0.235", + "tRCD": 13750, + "type": "DRAMCtrl", + "IDD3P02": "0.0", + "tRRD_L": 0, + "IDD0": "0.055", + "IDD62": "0.0", + "min_writes_per_switch": 16, + "mem_sched_policy": "frfcfs", + "IDD02": "0.0", + "IDD2P0": "0.0", + "ranks_per_channel": 2, + "page_policy": "open_adaptive", + "IDD4W2": "0.0", + "tCS": 2500, + "power_model": null, + "tCL": 13750, + "read_buffer_size": 32, + "conf_table_reported": true, + "tCK": 1250, + "tRAS": 35000, + "tRP": 13750, + "tBURST": 5000, + "path": "system.physmem", + "tXP": 6000, + "tXS": 270000, + "addr_mapping": "RoRaBaCoCh", + "IDD3P0": "0.0", + "IDD3P1": "0.038", + "IDD3N": "0.038", + "name": "physmem", + "tXSDLL": 0, + "device_size": 536870912, + "kvm_map": true, + "dll": true, + "tXAW": 30000, + "write_low_thresh_perc": 50, + "range": "0:134217727:0:0:0:0", + "VDD2": "0.0", + "IDD2P12": "0.0", + "p_state_clk_gate_bins": 20, + "tXPDLL": 0, + "IDD4R2": "0.0", + "device_rowbuffer_size": 1024, + "static_backend_latency": 10000, + "max_accesses_per_row": 16, + "IDD3P12": "0.0", + "tREFI": 7800000 + }, + "power_model": null, + "work_cpus_ckpt_count": 0, + "thermal_components": [], + "path": "system", + "cpu_clk_domain": { + "name": "cpu_clk_domain", + "clock": [ + 500 + ], + "init_perf_level": 0, + "voltage_domain": "system.voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.cpu_clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "work_end_ckpt_count": 0, + "mem_mode": "timing", + "name": "system", + "init_param": 0, + "p_state_clk_gate_bins": 20, + "load_addr_mask": 1099511627775, + "cpu": [ + { + "max_insts_any_thread": 0, + "do_statistics_insts": true, + "numThreads": 1, + "fetch1LineSnapWidth": 0, + "fetch1ToFetch2BackwardDelay": 1, + "fetch1FetchLimit": 1, + "executeIssueLimit": 2, + "system": "system", + "executeLSQMaxStoreBufferStoresPerCycle": 2, + "icache": { + "cpu_side": { + "peer": "system.cpu.icache_port", + "role": "SLAVE" + }, + "clusivity": "mostly_incl", + "prefetcher": null, + "system": "system", + "write_buffers": 8, + "response_latency": 2, + "cxx_class": "Cache", + "size": 131072, + "type": "Cache", + "clk_domain": "system.cpu_clk_domain", + "max_miss_count": 0, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "mem_side": { + "peer": "system.cpu.toL2Bus.slave[0]", + "role": "MASTER" + }, + "mshrs": 4, + "writeback_clean": true, + "p_state_clk_gate_min": 1000, + "tags": { + "size": 131072, + "tag_latency": 2, + "name": "tags", + "p_state_clk_gate_min": 1000, + "eventq_index": 0, + "p_state_clk_gate_bins": 20, + "default_p_state": "UNDEFINED", + "clk_domain": "system.cpu_clk_domain", + "power_model": null, + "sequential_access": false, + "assoc": 2, + "cxx_class": "LRU", + "p_state_clk_gate_max": 1000000000000, + "path": "system.cpu.icache.tags", + "block_size": 64, + "type": "LRU", + "data_latency": 2 + }, + "tgts_per_mshr": 20, + "demand_mshr_reserve": 1, + "power_model": null, + "addr_ranges": [ + "0:18446744073709551615:0:0:0:0" + ], + "is_read_only": true, + "prefetch_on_access": false, + "path": "system.cpu.icache", + "data_latency": 2, + "tag_latency": 2, + "name": "icache", + "p_state_clk_gate_bins": 20, + "sequential_access": false, + "assoc": 2 + }, + "function_trace": false, + "do_checkpoint_insts": true, + "decodeInputWidth": 2, + "cxx_class": "MinorCPU", + "max_loads_all_threads": 0, + "executeMemoryIssueLimit": 1, + "decodeCycleInput": true, + "max_loads_any_thread": 0, + "executeLSQTransfersQueueSize": 2, + "p_state_clk_gate_max": 1000000000000, + "clk_domain": "system.cpu_clk_domain", + "function_trace_start": 0, + "cpu_id": 0, + "checker": null, + "eventq_index": 0, + "executeMemoryWidth": 0, + "default_p_state": "UNDEFINED", + "executeBranchDelay": 1, + "executeMemoryCommitLimit": 1, + "l2cache": { + "cpu_side": { + "peer": "system.cpu.toL2Bus.master[0]", + "role": "SLAVE" + }, + "clusivity": "mostly_incl", + "prefetcher": null, + "system": "system", + "write_buffers": 8, + "response_latency": 20, + "cxx_class": "Cache", + "size": 2097152, + "type": "Cache", + "clk_domain": "system.cpu_clk_domain", + "max_miss_count": 0, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "mem_side": { + "peer": "system.membus.slave[1]", + "role": "MASTER" + }, + "mshrs": 20, + "writeback_clean": false, + "p_state_clk_gate_min": 1000, + "tags": { + "size": 2097152, + "tag_latency": 20, + "name": "tags", + "p_state_clk_gate_min": 1000, + "eventq_index": 0, + "p_state_clk_gate_bins": 20, + "default_p_state": "UNDEFINED", + "clk_domain": "system.cpu_clk_domain", + "power_model": null, + "sequential_access": false, + "assoc": 8, + "cxx_class": "LRU", + "p_state_clk_gate_max": 1000000000000, + "path": "system.cpu.l2cache.tags", + "block_size": 64, + "type": "LRU", + "data_latency": 20 + }, + "tgts_per_mshr": 12, + "demand_mshr_reserve": 1, + "power_model": null, + "addr_ranges": [ + "0:18446744073709551615:0:0:0:0" + ], + "is_read_only": false, + "prefetch_on_access": false, + "path": "system.cpu.l2cache", + "data_latency": 20, + "tag_latency": 20, + "name": "l2cache", + "p_state_clk_gate_bins": 20, + "sequential_access": false, + "assoc": 8 + }, + "do_quiesce": true, + "type": "MinorCPU", + "executeCycleInput": true, + "executeAllowEarlyMemoryIssue": true, + "executeInputBufferSize": 7, + "icache_port": { + "peer": "system.cpu.icache.cpu_side", + "role": "MASTER" + }, + "p_state_clk_gate_bins": 20, + "socket_id": 0, + "progress_interval": 0, + "p_state_clk_gate_min": 1000, + "toL2Bus": { + "point_of_coherency": false, + "system": "system", + "response_latency": 1, + "cxx_class": "CoherentXBar", + "forward_latency": 0, + "clk_domain": "system.cpu_clk_domain", + "width": 32, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "master": { + "peer": [ + "system.cpu.l2cache.cpu_side" + ], + "role": "MASTER" + }, + "type": "CoherentXBar", + "frontend_latency": 1, + "slave": { + "peer": [ + "system.cpu.icache.mem_side", + "system.cpu.dcache.mem_side" + ], + "role": "SLAVE" + }, + "p_state_clk_gate_min": 1000, + "snoop_filter": { + "name": "snoop_filter", + "system": "system", + "max_capacity": 8388608, + "eventq_index": 0, + "cxx_class": "SnoopFilter", + "path": "system.cpu.toL2Bus.snoop_filter", + "type": "SnoopFilter", + "lookup_latency": 0 + }, + "power_model": null, + "path": "system.cpu.toL2Bus", + "snoop_response_latency": 1, + "name": "toL2Bus", + "p_state_clk_gate_bins": 20, + "use_default_range": false + }, + "isa": [ + { + "eventq_index": 0, + "path": "system.cpu.isa", + "type": "RiscvISA", + "name": "isa", + "cxx_class": "RiscvISA::ISA" + } + ], + "itb": { + "name": "itb", + "eventq_index": 0, + "cxx_class": "RiscvISA::TLB", + "path": "system.cpu.itb", + "type": "RiscvTLB", + "size": 64 + }, + "interrupts": [ + { + "eventq_index": 0, + "path": "system.cpu.interrupts", + "type": "RiscvInterrupts", + "name": "interrupts", + "cxx_class": "RiscvISA::Interrupts" + } + ], + "dcache_port": { + "peer": "system.cpu.dcache.cpu_side", + "role": "MASTER" + }, + "executeFuncUnits": { + "name": "executeFuncUnits", + "eventq_index": 0, + "cxx_class": "MinorFUPool", + "path": "system.cpu.executeFuncUnits", + "funcUnits": [ + { + "issueLat": 1, + "opLat": 3, + "name": "funcUnits0", + "cantForwardFromFUIndices": [], + "opClasses": { + "name": "opClasses", + "opClasses": [ + { + "opClass": "IntAlu", + "name": "opClasses", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses", + "type": "MinorOpClass" + } + ], + "eventq_index": 0, + "cxx_class": "MinorOpClassSet", + "path": "system.cpu.executeFuncUnits.funcUnits0.opClasses", + "type": "MinorOpClassSet" + }, + "eventq_index": 0, + "timings": [ + { + "extraAssumedLat": 0, + "description": "Int", + "srcRegsRelativeLats": [ + 2 + ], + "suppress": false, + "mask": 0, + "extraCommitLat": 0, + "eventq_index": 0, + "opClasses": { + "name": "opClasses", + "opClasses": [], + "eventq_index": 0, + "cxx_class": "MinorOpClassSet", + "path": "system.cpu.executeFuncUnits.funcUnits0.timings.opClasses", + "type": "MinorOpClassSet" + }, + "cxx_class": "MinorFUTiming", + "path": "system.cpu.executeFuncUnits.funcUnits0.timings", + "extraCommitLatExpr": null, + "type": "MinorFUTiming", + "match": 0, + "name": "timings" + } + ], + "cxx_class": "MinorFU", + "path": "system.cpu.executeFuncUnits.funcUnits0", + "type": "MinorFU" + }, + { + "issueLat": 1, + "opLat": 3, + "name": "funcUnits1", + "cantForwardFromFUIndices": [], + "opClasses": { + "name": "opClasses", + "opClasses": [ + { + "opClass": "IntAlu", + "name": "opClasses", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses", + "type": "MinorOpClass" + } + ], + "eventq_index": 0, + "cxx_class": "MinorOpClassSet", + "path": "system.cpu.executeFuncUnits.funcUnits1.opClasses", + "type": "MinorOpClassSet" + }, + "eventq_index": 0, + "timings": [ + { + "extraAssumedLat": 0, + "description": "Int", + "srcRegsRelativeLats": [ + 2 + ], + "suppress": false, + "mask": 0, + "extraCommitLat": 0, + "eventq_index": 0, + "opClasses": { + "name": "opClasses", + "opClasses": [], + "eventq_index": 0, + "cxx_class": "MinorOpClassSet", + "path": "system.cpu.executeFuncUnits.funcUnits1.timings.opClasses", + "type": "MinorOpClassSet" + }, + "cxx_class": "MinorFUTiming", + "path": "system.cpu.executeFuncUnits.funcUnits1.timings", + "extraCommitLatExpr": null, + "type": "MinorFUTiming", + "match": 0, + "name": "timings" + } + ], + "cxx_class": "MinorFU", + "path": "system.cpu.executeFuncUnits.funcUnits1", + "type": "MinorFU" + }, + { + "issueLat": 1, + "opLat": 3, + "name": "funcUnits2", + "cantForwardFromFUIndices": [], + "opClasses": { + "name": "opClasses", + "opClasses": [ + { + "opClass": "IntMult", + "name": "opClasses", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses", + "type": "MinorOpClass" + } + ], + "eventq_index": 0, + "cxx_class": "MinorOpClassSet", + "path": "system.cpu.executeFuncUnits.funcUnits2.opClasses", + "type": "MinorOpClassSet" + }, + "eventq_index": 0, + "timings": [ + { + "extraAssumedLat": 0, + "description": "Mul", + "srcRegsRelativeLats": [ + 0 + ], + "suppress": false, + "mask": 0, + "extraCommitLat": 0, + "eventq_index": 0, + "opClasses": { + "name": "opClasses", + "opClasses": [], + "eventq_index": 0, + "cxx_class": "MinorOpClassSet", + "path": "system.cpu.executeFuncUnits.funcUnits2.timings.opClasses", + "type": "MinorOpClassSet" + }, + "cxx_class": "MinorFUTiming", + "path": "system.cpu.executeFuncUnits.funcUnits2.timings", + "extraCommitLatExpr": null, + "type": "MinorFUTiming", + "match": 0, + "name": "timings" + } + ], + "cxx_class": "MinorFU", + "path": "system.cpu.executeFuncUnits.funcUnits2", + "type": "MinorFU" + }, + { + "issueLat": 9, + "opLat": 9, + "name": "funcUnits3", + "cantForwardFromFUIndices": [], + "opClasses": { + "name": "opClasses", + "opClasses": [ + { + "opClass": "IntDiv", + "name": "opClasses", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses", + "type": "MinorOpClass" + } + ], + "eventq_index": 0, + "cxx_class": "MinorOpClassSet", + "path": "system.cpu.executeFuncUnits.funcUnits3.opClasses", + "type": "MinorOpClassSet" + }, + "eventq_index": 0, + "timings": [], + "cxx_class": "MinorFU", + "path": "system.cpu.executeFuncUnits.funcUnits3", + "type": "MinorFU" + }, + { + "issueLat": 1, + "opLat": 6, + "name": "funcUnits4", + "cantForwardFromFUIndices": [], + "opClasses": { + "name": "opClasses", + "opClasses": [ + { + "opClass": "FloatAdd", + "name": "opClasses00", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00", + "type": "MinorOpClass" + }, + { + "opClass": "FloatCmp", + "name": "opClasses01", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01", + "type": "MinorOpClass" + }, + { + "opClass": "FloatCvt", + "name": "opClasses02", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02", + "type": "MinorOpClass" + }, + { + "opClass": "FloatMisc", + "name": "opClasses03", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03", + "type": "MinorOpClass" + }, + { + "opClass": "FloatMult", + "name": "opClasses04", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04", + "type": "MinorOpClass" + }, + { + "opClass": "FloatMultAcc", + "name": "opClasses05", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05", + "type": "MinorOpClass" + }, + { + "opClass": "FloatDiv", + "name": "opClasses06", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06", + "type": "MinorOpClass" + }, + { + "opClass": "FloatSqrt", + "name": "opClasses07", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07", + "type": "MinorOpClass" + }, + { + "opClass": "SimdAdd", + "name": "opClasses08", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08", + "type": "MinorOpClass" + }, + { + "opClass": "SimdAddAcc", + "name": "opClasses09", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09", + "type": "MinorOpClass" + }, + { + "opClass": "SimdAlu", + "name": "opClasses10", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10", + "type": "MinorOpClass" + }, + { + "opClass": "SimdCmp", + "name": "opClasses11", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11", + "type": "MinorOpClass" + }, + { + "opClass": "SimdCvt", + "name": "opClasses12", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12", + "type": "MinorOpClass" + }, + { + "opClass": "SimdMisc", + "name": "opClasses13", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13", + "type": "MinorOpClass" + }, + { + "opClass": "SimdMult", + "name": "opClasses14", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14", + "type": "MinorOpClass" + }, + { + "opClass": "SimdMultAcc", + "name": "opClasses15", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15", + "type": "MinorOpClass" + }, + { + "opClass": "SimdShift", + "name": "opClasses16", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16", + "type": "MinorOpClass" + }, + { + "opClass": "SimdShiftAcc", + "name": "opClasses17", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17", + "type": "MinorOpClass" + }, + { + "opClass": "SimdSqrt", + "name": "opClasses18", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18", + "type": "MinorOpClass" + }, + { + "opClass": "SimdFloatAdd", + "name": "opClasses19", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19", + "type": "MinorOpClass" + }, + { + "opClass": "SimdFloatAlu", + "name": "opClasses20", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20", + "type": "MinorOpClass" + }, + { + "opClass": "SimdFloatCmp", + "name": "opClasses21", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21", + "type": "MinorOpClass" + }, + { + "opClass": "SimdFloatCvt", + "name": "opClasses22", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22", + "type": "MinorOpClass" + }, + { + "opClass": "SimdFloatDiv", + "name": "opClasses23", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23", + "type": "MinorOpClass" + }, + { + "opClass": "SimdFloatMisc", + "name": "opClasses24", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24", + "type": "MinorOpClass" + }, + { + "opClass": "SimdFloatMult", + "name": "opClasses25", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25", + "type": "MinorOpClass" + }, + { + "opClass": "SimdFloatMultAcc", + "name": "opClasses26", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses26", + "type": "MinorOpClass" + }, + { + "opClass": "SimdFloatSqrt", + "name": "opClasses27", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses27", + "type": "MinorOpClass" + } + ], + "eventq_index": 0, + "cxx_class": "MinorOpClassSet", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses", + "type": "MinorOpClassSet" + }, + "eventq_index": 0, + "timings": [ + { + "extraAssumedLat": 0, + "description": "FloatSimd", + "srcRegsRelativeLats": [ + 2 + ], + "suppress": false, + "mask": 0, + "extraCommitLat": 0, + "eventq_index": 0, + "opClasses": { + "name": "opClasses", + "opClasses": [], + "eventq_index": 0, + "cxx_class": "MinorOpClassSet", + "path": "system.cpu.executeFuncUnits.funcUnits4.timings.opClasses", + "type": "MinorOpClassSet" + }, + "cxx_class": "MinorFUTiming", + "path": "system.cpu.executeFuncUnits.funcUnits4.timings", + "extraCommitLatExpr": null, + "type": "MinorFUTiming", + "match": 0, + "name": "timings" + } + ], + "cxx_class": "MinorFU", + "path": "system.cpu.executeFuncUnits.funcUnits4", + "type": "MinorFU" + }, + { + "issueLat": 1, + "opLat": 1, + "name": "funcUnits5", + "cantForwardFromFUIndices": [], + "opClasses": { + "name": "opClasses", + "opClasses": [ + { + "opClass": "MemRead", + "name": "opClasses0", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0", + "type": "MinorOpClass" + }, + { + "opClass": "MemWrite", + "name": "opClasses1", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1", + "type": "MinorOpClass" + }, + { + "opClass": "FloatMemRead", + "name": "opClasses2", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses2", + "type": "MinorOpClass" + }, + { + "opClass": "FloatMemWrite", + "name": "opClasses3", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses3", + "type": "MinorOpClass" + } + ], + "eventq_index": 0, + "cxx_class": "MinorOpClassSet", + "path": "system.cpu.executeFuncUnits.funcUnits5.opClasses", + "type": "MinorOpClassSet" + }, + "eventq_index": 0, + "timings": [ + { + "extraAssumedLat": 2, + "description": "Mem", + "srcRegsRelativeLats": [ + 1 + ], + "suppress": false, + "mask": 0, + "extraCommitLat": 0, + "eventq_index": 0, + "opClasses": { + "name": "opClasses", + "opClasses": [], + "eventq_index": 0, + "cxx_class": "MinorOpClassSet", + "path": "system.cpu.executeFuncUnits.funcUnits5.timings.opClasses", + "type": "MinorOpClassSet" + }, + "cxx_class": "MinorFUTiming", + "path": "system.cpu.executeFuncUnits.funcUnits5.timings", + "extraCommitLatExpr": null, + "type": "MinorFUTiming", + "match": 0, + "name": "timings" + } + ], + "cxx_class": "MinorFU", + "path": "system.cpu.executeFuncUnits.funcUnits5", + "type": "MinorFU" + }, + { + "issueLat": 1, + "opLat": 1, + "name": "funcUnits6", + "cantForwardFromFUIndices": [], + "opClasses": { + "name": "opClasses", + "opClasses": [ + { + "opClass": "IprAccess", + "name": "opClasses0", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0", + "type": "MinorOpClass" + }, + { + "opClass": "InstPrefetch", + "name": "opClasses1", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1", + "type": "MinorOpClass" + } + ], + "eventq_index": 0, + "cxx_class": "MinorOpClassSet", + "path": "system.cpu.executeFuncUnits.funcUnits6.opClasses", + "type": "MinorOpClassSet" + }, + "eventq_index": 0, + "timings": [], + "cxx_class": "MinorFU", + "path": "system.cpu.executeFuncUnits.funcUnits6", + "type": "MinorFU" + } + ], + "type": "MinorFUPool" + }, + "switched_out": false, + "power_model": null, + "max_insts_all_threads": 0, + "executeSetTraceTimeOnIssue": false, + "fetch2InputBufferSize": 2, + "profile": 0, + "fetch2ToDecodeForwardDelay": 1, + "executeInputWidth": 2, + "decodeToExecuteForwardDelay": 1, + "executeLSQRequestsQueueSize": 1, + "fetch2CycleInput": true, + "executeMaxAccessesInMemory": 2, + "enableIdling": true, + "executeLSQStoreBufferSize": 5, + "workload": [ + { + "uid": 100, + "pid": 100, + "kvmInSE": false, + "cxx_class": "LiveProcess", + "executable": "/z/powerjg/gem5-upstream/tests/test-progs/hello/bin/riscv/linux/hello", + "drivers": [], + "system": "system", + "gid": 100, + "eventq_index": 0, + "env": [], + "input": "cin", + "ppid": 99, + "type": "LiveProcess", + "cwd": "", + "simpoint": 0, + "euid": 100, + "path": "system.cpu.workload", + "max_stack_size": 67108864, + "name": "workload", + "cmd": [ + "hello" + ], + "errout": "cerr", + "useArchPT": false, + "egid": 100, + "output": "cout" + } + ], + "name": "cpu", + "dtb": { + "name": "dtb", + "eventq_index": 0, + "cxx_class": "RiscvISA::TLB", + "path": "system.cpu.dtb", + "type": "RiscvTLB", + "size": 64 + }, + "simpoint_start_insts": [], + "executeSetTraceTimeOnCommit": true, + "tracer": { + "eventq_index": 0, + "path": "system.cpu.tracer", + "type": "ExeTracer", + "name": "tracer", + "cxx_class": "Trace::ExeTracer" + }, + "threadPolicy": "RoundRobin", + "executeCommitLimit": 2, + "fetch1LineWidth": 0, + "branchPred": { + "numThreads": 1, + "BTBEntries": 4096, + "cxx_class": "TournamentBP", + "indirectPathLength": 3, + "globalCtrBits": 2, + "choicePredictorSize": 8192, + "indirectHashGHR": true, + "eventq_index": 0, + "localHistoryTableSize": 2048, + "type": "TournamentBP", + "indirectSets": 256, + "indirectWays": 2, + "choiceCtrBits": 2, + "useIndirect": true, + "localCtrBits": 2, + "path": "system.cpu.branchPred", + "localPredictorSize": 2048, + "RASSize": 16, + "globalPredictorSize": 8192, + "name": "branchPred", + "indirectHashTargets": true, + "instShiftAmt": 2, + "indirectTagSize": 16, + "BTBTagSize": 16 + }, + "dcache": { + "cpu_side": { + "peer": "system.cpu.dcache_port", + "role": "SLAVE" + }, + "clusivity": "mostly_incl", + "prefetcher": null, + "system": "system", + "write_buffers": 8, + "response_latency": 2, + "cxx_class": "Cache", + "size": 262144, + "type": "Cache", + "clk_domain": "system.cpu_clk_domain", + "max_miss_count": 0, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "mem_side": { + "peer": "system.cpu.toL2Bus.slave[1]", + "role": "MASTER" + }, + "mshrs": 4, + "writeback_clean": false, + "p_state_clk_gate_min": 1000, + "tags": { + "size": 262144, + "tag_latency": 2, + "name": "tags", + "p_state_clk_gate_min": 1000, + "eventq_index": 0, + "p_state_clk_gate_bins": 20, + "default_p_state": "UNDEFINED", + "clk_domain": "system.cpu_clk_domain", + "power_model": null, + "sequential_access": false, + "assoc": 2, + "cxx_class": "LRU", + "p_state_clk_gate_max": 1000000000000, + "path": "system.cpu.dcache.tags", + "block_size": 64, + "type": "LRU", + "data_latency": 2 + }, + "tgts_per_mshr": 20, + "demand_mshr_reserve": 1, + "power_model": null, + "addr_ranges": [ + "0:18446744073709551615:0:0:0:0" + ], + "is_read_only": false, + "prefetch_on_access": false, + "path": "system.cpu.dcache", + "data_latency": 2, + "tag_latency": 2, + "name": "dcache", + "p_state_clk_gate_bins": 20, + "sequential_access": false, + "assoc": 2 + }, + "path": "system.cpu", + "fetch1ToFetch2ForwardDelay": 1, + "decodeInputBufferSize": 3 + } + ], + "multi_thread": false, + "exit_on_work_items": false, + "work_item_id": -1, + "num_work_ids": 16 + }, + "time_sync_period": 100000000000, + "eventq_index": 0, + "time_sync_spin_threshold": 100000000, + "cxx_class": "Root", + "path": "root", + "time_sync_enable": false, + "type": "Root", + "full_system": false +}
\ No newline at end of file diff --git a/tests/quick/se/00.hello/ref/riscv/linux/minor-timing/simerr b/tests/quick/se/00.hello/ref/riscv/linux/minor-timing/simerr new file mode 100755 index 000000000..85a6a33ad --- /dev/null +++ b/tests/quick/se/00.hello/ref/riscv/linux/minor-timing/simerr @@ -0,0 +1,4 @@ +warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes) +warn: Unknown operating system; assuming Linux. +warn: Sockets disabled, not accepting gdb connections +warn: ClockedObject: More than one power state change request encountered within the same simulation tick diff --git a/tests/quick/se/00.hello/ref/riscv/linux/minor-timing/simout b/tests/quick/se/00.hello/ref/riscv/linux/minor-timing/simout new file mode 100755 index 000000000..2251c9b4d --- /dev/null +++ b/tests/quick/se/00.hello/ref/riscv/linux/minor-timing/simout @@ -0,0 +1,15 @@ +Redirecting stdout to build/RISCV/tests/opt/quick/se/00.hello/riscv/linux/minor-timing/simout +Redirecting stderr to build/RISCV/tests/opt/quick/se/00.hello/riscv/linux/minor-timing/simerr +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled Nov 30 2016 14:33:35 +gem5 started Nov 30 2016 16:18:28 +gem5 executing on zizzer, pid 34056 +command line: /z/powerjg/gem5-upstream/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/00.hello/riscv/linux/minor-timing -re /z/powerjg/gem5-upstream/tests/testing/../run.py quick/se/00.hello/riscv/linux/minor-timing + +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. +Hello world! +Exiting @ tick 14435000 because target called exit() diff --git a/tests/quick/se/00.hello/ref/riscv/linux/minor-timing/stats.txt b/tests/quick/se/00.hello/ref/riscv/linux/minor-timing/stats.txt new file mode 100644 index 000000000..6dc71361b --- /dev/null +++ b/tests/quick/se/00.hello/ref/riscv/linux/minor-timing/stats.txt @@ -0,0 +1,749 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.000014 # Number of seconds simulated +sim_ticks 14435000 # Number of ticks simulated +final_tick 14435000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 13240 # Simulator instruction rate (inst/s) +host_op_rate 13237 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 119615611 # Simulator tick rate (ticks/s) +host_mem_usage 232036 # Number of bytes of host memory used +host_seconds 0.12 # Real time elapsed on the host +sim_insts 1597 # Number of instructions simulated +sim_ops 1597 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 14435000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 9984 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 2048 # Number of bytes read from this memory +system.physmem.bytes_read::total 12032 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 9984 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 9984 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 156 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 32 # Number of read requests responded to by this memory +system.physmem.num_reads::total 188 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 691652234 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 141877381 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 833529616 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 691652234 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 691652234 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 691652234 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 141877381 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 833529616 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 188 # Number of read requests accepted +system.physmem.writeReqs 0 # Number of write requests accepted +system.physmem.readBursts 188 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 12032 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue +system.physmem.bytesWritten 0 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 12032 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 97 # Per bank write bursts +system.physmem.perBankRdBursts::1 64 # Per bank write bursts +system.physmem.perBankRdBursts::2 18 # Per bank write bursts +system.physmem.perBankRdBursts::3 9 # Per bank write bursts +system.physmem.perBankRdBursts::4 0 # Per bank write bursts +system.physmem.perBankRdBursts::5 0 # Per bank write bursts +system.physmem.perBankRdBursts::6 0 # Per bank write bursts +system.physmem.perBankRdBursts::7 0 # Per bank write bursts +system.physmem.perBankRdBursts::8 0 # Per bank write bursts +system.physmem.perBankRdBursts::9 0 # Per bank write bursts +system.physmem.perBankRdBursts::10 0 # Per bank write bursts +system.physmem.perBankRdBursts::11 0 # Per bank write bursts +system.physmem.perBankRdBursts::12 0 # Per bank write bursts +system.physmem.perBankRdBursts::13 0 # Per bank write bursts +system.physmem.perBankRdBursts::14 0 # Per bank write bursts +system.physmem.perBankRdBursts::15 0 # Per bank write bursts +system.physmem.perBankWrBursts::0 0 # Per bank write bursts +system.physmem.perBankWrBursts::1 0 # Per bank write bursts +system.physmem.perBankWrBursts::2 0 # Per bank write bursts +system.physmem.perBankWrBursts::3 0 # Per bank write bursts +system.physmem.perBankWrBursts::4 0 # Per bank write bursts +system.physmem.perBankWrBursts::5 0 # Per bank write bursts +system.physmem.perBankWrBursts::6 0 # Per bank write bursts +system.physmem.perBankWrBursts::7 0 # Per bank write bursts +system.physmem.perBankWrBursts::8 0 # Per bank write bursts +system.physmem.perBankWrBursts::9 0 # Per bank write bursts +system.physmem.perBankWrBursts::10 0 # Per bank write bursts +system.physmem.perBankWrBursts::11 0 # Per bank write bursts +system.physmem.perBankWrBursts::12 0 # Per bank write bursts +system.physmem.perBankWrBursts::13 0 # Per bank write bursts +system.physmem.perBankWrBursts::14 0 # Per bank write bursts +system.physmem.perBankWrBursts::15 0 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 14206000 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 188 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 0 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 161 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 25 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 13 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 817.230769 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 665.111831 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 349.717542 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 1 7.69% 7.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 1 7.69% 15.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 1 7.69% 23.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1 7.69% 30.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 9 69.23% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 13 # Bytes accessed per row activation +system.physmem.totQLat 1580250 # Total ticks spent queuing +system.physmem.totMemAccLat 5105250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 940000 # Total ticks spent in databus transfers +system.physmem.avgQLat 8405.59 # Average queueing delay per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 27155.59 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 833.53 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 833.53 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.busUtil 6.51 # Data bus utilization in percentage +system.physmem.busUtilRead 6.51 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.14 # Average read queue length when enqueuing +system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing +system.physmem.readRowHits 171 # Number of row buffer hits during reads +system.physmem.writeRowHits 0 # Number of row buffer hits during writes +system.physmem.readRowHitRate 90.96 # Row buffer hit rate for reads +system.physmem.writeRowHitRate nan # Row buffer hit rate for writes +system.physmem.avgGap 75563.83 # Average gap between requests +system.physmem.pageHitRate 90.96 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 121380 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 49335 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1342320 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 614640.000000 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 2281140 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 17760 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 4279560 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 480 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 8706615 # Total energy per rank (pJ) +system.physmem_0.averagePower 603.160028 # Core power per rank (mW) +system.physmem_0.totalIdleTime 9188750 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 18000 # Time in different power states +system.physmem_0.memoryStateTime::REF 260000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 0 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 1250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 4776000 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 9379750 # Time in different power states +system.physmem_1.actEnergy 0 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 0 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 0 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 614640.000000 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 112290 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 2995200 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 2453280 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 6175410 # Total energy per rank (pJ) +system.physmem_1.averagePower 427.808105 # Core power per rank (mW) +system.physmem_1.totalIdleTime 0 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 7786250 # Time in different power states +system.physmem_1.memoryStateTime::REF 260000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 0 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 6388750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 14435000 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 995 # Number of BP lookups +system.cpu.branchPred.condPredicted 543 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 229 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 945 # Number of BTB lookups +system.cpu.branchPred.BTBHits 100 # Number of BTB hits +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 10.582011 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 0 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 204 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 11 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 193 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 64 # Number of mispredicted indirect branches. +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 9 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 14435000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 28870 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 1597 # Number of instructions committed +system.cpu.committedOps 1597 # Number of ops (including micro ops) committed +system.cpu.discardedOps 744 # Number of ops (including micro ops) which were discarded before commit +system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching +system.cpu.cpi 18.077646 # CPI: cycles per instruction +system.cpu.ipc 0.055317 # IPC: instructions per cycle +system.cpu.op_class_0::No_OpClass 9 0.56% 0.56% # Class of committed instruction +system.cpu.op_class_0::IntAlu 1019 63.81% 64.37% # Class of committed instruction +system.cpu.op_class_0::IntMult 0 0.00% 64.37% # Class of committed instruction +system.cpu.op_class_0::IntDiv 0 0.00% 64.37% # Class of committed instruction +system.cpu.op_class_0::FloatAdd 0 0.00% 64.37% # Class of committed instruction +system.cpu.op_class_0::FloatCmp 0 0.00% 64.37% # Class of committed instruction +system.cpu.op_class_0::FloatCvt 0 0.00% 64.37% # Class of committed instruction +system.cpu.op_class_0::FloatMult 0 0.00% 64.37% # Class of committed instruction +system.cpu.op_class_0::FloatMultAcc 0 0.00% 64.37% # Class of committed instruction +system.cpu.op_class_0::FloatDiv 0 0.00% 64.37% # Class of committed instruction +system.cpu.op_class_0::FloatMisc 0 0.00% 64.37% # Class of committed instruction +system.cpu.op_class_0::FloatSqrt 0 0.00% 64.37% # Class of committed instruction +system.cpu.op_class_0::SimdAdd 0 0.00% 64.37% # Class of committed instruction +system.cpu.op_class_0::SimdAddAcc 0 0.00% 64.37% # Class of committed instruction +system.cpu.op_class_0::SimdAlu 0 0.00% 64.37% # Class of committed instruction +system.cpu.op_class_0::SimdCmp 0 0.00% 64.37% # Class of committed instruction +system.cpu.op_class_0::SimdCvt 0 0.00% 64.37% # Class of committed instruction +system.cpu.op_class_0::SimdMisc 0 0.00% 64.37% # Class of committed instruction +system.cpu.op_class_0::SimdMult 0 0.00% 64.37% # Class of committed instruction +system.cpu.op_class_0::SimdMultAcc 0 0.00% 64.37% # Class of committed instruction +system.cpu.op_class_0::SimdShift 0 0.00% 64.37% # Class of committed instruction +system.cpu.op_class_0::SimdShiftAcc 0 0.00% 64.37% # Class of committed instruction +system.cpu.op_class_0::SimdSqrt 0 0.00% 64.37% # Class of committed instruction +system.cpu.op_class_0::SimdFloatAdd 0 0.00% 64.37% # Class of committed instruction +system.cpu.op_class_0::SimdFloatAlu 0 0.00% 64.37% # Class of committed instruction +system.cpu.op_class_0::SimdFloatCmp 0 0.00% 64.37% # Class of committed instruction +system.cpu.op_class_0::SimdFloatCvt 0 0.00% 64.37% # Class of committed instruction +system.cpu.op_class_0::SimdFloatDiv 0 0.00% 64.37% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMisc 0 0.00% 64.37% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMult 0 0.00% 64.37% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 64.37% # Class of committed instruction +system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 64.37% # Class of committed instruction +system.cpu.op_class_0::MemRead 289 18.10% 82.47% # Class of committed instruction +system.cpu.op_class_0::MemWrite 280 17.53% 100.00% # Class of committed instruction +system.cpu.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction +system.cpu.op_class_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction +system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.op_class_0::total 1597 # Class of committed instruction +system.cpu.tickCycles 4106 # Number of cycles that the object actually ticked +system.cpu.idleCycles 24764 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 14435000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 0 # number of replacements +system.cpu.dcache.tags.tagsinuse 24.135470 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 645 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 33 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 19.545455 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 24.135470 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.005892 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.005892 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 33 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 12 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 21 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.008057 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 1411 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1411 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 14435000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 394 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 394 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 251 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 251 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 645 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 645 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 645 # number of overall hits +system.cpu.dcache.overall_hits::total 645 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 16 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 16 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 28 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 28 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 44 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 44 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 44 # number of overall misses +system.cpu.dcache.overall_misses::total 44 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 1268000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 1268000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 2223500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 2223500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 3491500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 3491500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 3491500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 3491500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 410 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 410 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 279 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 279 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 689 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 689 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 689 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 689 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.039024 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.039024 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.100358 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.100358 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.063861 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.063861 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.063861 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.063861 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 79250 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 79250 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 79410.714286 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 79410.714286 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 79352.272727 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 79352.272727 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 79352.272727 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 79352.272727 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 11 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 11 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 11 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 11 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 11 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 11 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 16 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 16 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 17 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 17 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 33 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 33 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 33 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 33 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1252000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 1252000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1342000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1342000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 2594000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 2594000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 2594000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 2594000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.039024 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.039024 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.060932 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.060932 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.047896 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.047896 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.047896 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.047896 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78250 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78250 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 78941.176471 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 78941.176471 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 78606.060606 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 78606.060606 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78606.060606 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 78606.060606 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 14435000 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 0 # number of replacements +system.cpu.icache.tags.tagsinuse 79.926884 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 709 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 157 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 4.515924 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 79.926884 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.039027 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.039027 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 157 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 108 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 49 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.076660 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 1889 # Number of tag accesses +system.cpu.icache.tags.data_accesses 1889 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 14435000 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 709 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 709 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 709 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 709 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 709 # number of overall hits +system.cpu.icache.overall_hits::total 709 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 157 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 157 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 157 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 157 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 157 # number of overall misses +system.cpu.icache.overall_misses::total 157 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 12560500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 12560500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 12560500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 12560500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 12560500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 12560500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 866 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 866 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 866 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 866 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 866 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 866 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.181293 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.181293 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.181293 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.181293 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.181293 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.181293 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 80003.184713 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 80003.184713 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 80003.184713 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 80003.184713 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 80003.184713 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 80003.184713 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 157 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 157 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 157 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 157 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 157 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 157 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12403500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 12403500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12403500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 12403500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12403500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 12403500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.181293 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.181293 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.181293 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.181293 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.181293 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.181293 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 79003.184713 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 79003.184713 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 79003.184713 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 79003.184713 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 79003.184713 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 79003.184713 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 14435000 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.replacements 0 # number of replacements +system.cpu.l2cache.tags.tagsinuse 102.489649 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 188 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.010638 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::cpu.inst 79.179084 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 23.310565 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002416 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.000711 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.003128 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 188 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 120 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 68 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.005737 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 1708 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 1708 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 14435000 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 1 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 1 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 1 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 1 # number of overall hits +system.cpu.l2cache.overall_hits::total 2 # number of overall hits +system.cpu.l2cache.ReadExReq_misses::cpu.data 17 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 17 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 156 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 156 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 15 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 15 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.inst 156 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 32 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 188 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 156 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 32 # number of overall misses +system.cpu.l2cache.overall_misses::total 188 # number of overall misses +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1316500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 1316500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 12156500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 12156500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 1215500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 1215500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 12156500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 2532000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 14688500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 12156500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 2532000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 14688500 # number of overall miss cycles +system.cpu.l2cache.ReadExReq_accesses::cpu.data 17 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 17 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 157 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 157 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 16 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 16 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 157 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 33 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 190 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 157 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 33 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 190 # number of overall (read+write) accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.993631 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.993631 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.937500 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.937500 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.993631 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.969697 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.989474 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993631 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.969697 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.989474 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77441.176471 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 77441.176471 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 77926.282051 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 77926.282051 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 81033.333333 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 81033.333333 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77926.282051 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79125 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 78130.319149 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77926.282051 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79125 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 78130.319149 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 17 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 17 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 156 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 156 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 15 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 15 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 156 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 32 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 188 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 156 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 32 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 188 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1146500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1146500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 10596500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 10596500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1065500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1065500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10596500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 2212000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 12808500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10596500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 2212000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 12808500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.993631 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.993631 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.937500 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.937500 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.993631 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.969697 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.989474 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993631 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.969697 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.989474 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67441.176471 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67441.176471 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 67926.282051 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 67926.282051 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 71033.333333 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 71033.333333 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67926.282051 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69125 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68130.319149 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67926.282051 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69125 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68130.319149 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 190 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 14435000 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 173 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 17 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 17 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 157 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 16 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 314 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 66 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 380 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 10048 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2112 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 12160 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 190 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.010526 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.102326 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 188 98.95% 98.95% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 2 1.05% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 190 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 95000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 235500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 1.6 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 49500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.3 # Layer utilization (%) +system.membus.snoop_filter.tot_requests 188 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 14435000 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 171 # Transaction distribution +system.membus.trans_dist::ReadExReq 17 # Transaction distribution +system.membus.trans_dist::ReadExResp 17 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 171 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 376 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 376 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 12032 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 12032 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoopTraffic 0 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 188 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 188 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 188 # Request fanout histogram +system.membus.reqLayer0.occupancy 217500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 1.5 # Layer utilization (%) +system.membus.respLayer1.occupancy 991750 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 6.9 # Layer utilization (%) + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/riscv/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/riscv/linux/o3-timing/config.ini new file mode 100644 index 000000000..7fd46c549 --- /dev/null +++ b/tests/quick/se/00.hello/ref/riscv/linux/o3-timing/config.ini @@ -0,0 +1,872 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain +boot_osflags=a +cache_line_size=64 +clk_domain=system.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +exit_on_work_items=false +init_param=0 +kernel= +kernel_addr_check=true +load_addr_mask=1099511627775 +load_offset=0 +mem_mode=timing +mem_ranges= +memories=system.physmem +mmap_using_noreserve=false +multi_thread=false +num_work_ids=16 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +readfile= +symbolfile= +thermal_components= +thermal_model=Null +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=DerivO3CPU +children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload +LFSTSize=1024 +LQEntries=32 +LSQCheckLoads=true +LSQDepCheckShift=4 +SQEntries=32 +SSITSize=1024 +activity=0 +backComSize=5 +branchPred=system.cpu.branchPred +cachePorts=200 +checker=Null +clk_domain=system.cpu_clk_domain +commitToDecodeDelay=1 +commitToFetchDelay=1 +commitToIEWDelay=1 +commitToRenameDelay=1 +commitWidth=8 +cpu_id=0 +decodeToFetchDelay=1 +decodeToRenameDelay=1 +decodeWidth=8 +default_p_state=UNDEFINED +dispatchWidth=8 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +eventq_index=0 +fetchBufferSize=64 +fetchQueueSize=32 +fetchToDecodeDelay=1 +fetchTrapLatency=1 +fetchWidth=8 +forwardComSize=5 +fuPool=system.cpu.fuPool +function_trace=false +function_trace_start=0 +iewToCommitDelay=1 +iewToDecodeDelay=1 +iewToFetchDelay=1 +iewToRenameDelay=1 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +issueToExecuteDelay=1 +issueWidth=8 +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +needsTSO=false +numIQEntries=64 +numPhysCCRegs=0 +numPhysFloatRegs=256 +numPhysIntRegs=256 +numROBEntries=192 +numRobs=1 +numThreads=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +profile=0 +progress_interval=0 +renameToDecodeDelay=1 +renameToFetchDelay=1 +renameToIEWDelay=2 +renameToROBDelay=1 +renameWidth=8 +simpoint_start_insts= +smtCommitPolicy=RoundRobin +smtFetchPolicy=SingleThread +smtIQPolicy=Partitioned +smtIQThreshold=100 +smtLSQPolicy=Partitioned +smtLSQThreshold=100 +smtNumFetchingThreads=1 +smtROBPolicy=Partitioned +smtROBThreshold=100 +socket_id=0 +squashWidth=8 +store_set_clear_period=250000 +switched_out=false +system=system +tracer=system.cpu.tracer +trapLatency=13 +wbWidth=8 +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.branchPred] +type=TournamentBP +BTBEntries=4096 +BTBTagSize=16 +RASSize=16 +choiceCtrBits=2 +choicePredictorSize=8192 +eventq_index=0 +globalCtrBits=2 +globalPredictorSize=8192 +indirectHashGHR=true +indirectHashTargets=true +indirectPathLength=3 +indirectSets=256 +indirectTagSize=16 +indirectWays=2 +instShiftAmt=2 +localCtrBits=2 +localHistoryTableSize=2048 +localPredictorSize=2048 +numThreads=1 +useIndirect=true + +[system.cpu.dcache] +type=Cache +children=tags +addr_ranges=0:18446744073709551615:0:0:0:0 +assoc=2 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +data_latency=2 +default_p_state=UNDEFINED +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=4 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=262144 +system=system +tag_latency=2 +tags=system.cpu.dcache.tags +tgts_per_mshr=20 +write_buffers=8 +writeback_clean=false +cpu_side=system.cpu.dcache_port +mem_side=system.cpu.toL2Bus.slave[1] + +[system.cpu.dcache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +data_latency=2 +default_p_state=UNDEFINED +eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +sequential_access=false +size=262144 +tag_latency=2 + +[system.cpu.dtb] +type=RiscvTLB +eventq_index=0 +size=64 + +[system.cpu.fuPool] +type=FUPool +children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 +FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 +eventq_index=0 + +[system.cpu.fuPool.FUList0] +type=FUDesc +children=opList +count=6 +eventq_index=0 +opList=system.cpu.fuPool.FUList0.opList + +[system.cpu.fuPool.FUList0.opList] +type=OpDesc +eventq_index=0 +opClass=IntAlu +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList1] +type=FUDesc +children=opList0 opList1 +count=2 +eventq_index=0 +opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 + +[system.cpu.fuPool.FUList1.opList0] +type=OpDesc +eventq_index=0 +opClass=IntMult +opLat=3 +pipelined=true + +[system.cpu.fuPool.FUList1.opList1] +type=OpDesc +eventq_index=0 +opClass=IntDiv +opLat=20 +pipelined=false + +[system.cpu.fuPool.FUList2] +type=FUDesc +children=opList0 opList1 opList2 +count=4 +eventq_index=0 +opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 + +[system.cpu.fuPool.FUList2.opList0] +type=OpDesc +eventq_index=0 +opClass=FloatAdd +opLat=2 +pipelined=true + +[system.cpu.fuPool.FUList2.opList1] +type=OpDesc +eventq_index=0 +opClass=FloatCmp +opLat=2 +pipelined=true + +[system.cpu.fuPool.FUList2.opList2] +type=OpDesc +eventq_index=0 +opClass=FloatCvt +opLat=2 +pipelined=true + +[system.cpu.fuPool.FUList3] +type=FUDesc +children=opList0 opList1 opList2 opList3 opList4 +count=2 +eventq_index=0 +opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 system.cpu.fuPool.FUList3.opList3 system.cpu.fuPool.FUList3.opList4 + +[system.cpu.fuPool.FUList3.opList0] +type=OpDesc +eventq_index=0 +opClass=FloatMult +opLat=4 +pipelined=true + +[system.cpu.fuPool.FUList3.opList1] +type=OpDesc +eventq_index=0 +opClass=FloatMultAcc +opLat=5 +pipelined=true + +[system.cpu.fuPool.FUList3.opList2] +type=OpDesc +eventq_index=0 +opClass=FloatMisc +opLat=3 +pipelined=true + +[system.cpu.fuPool.FUList3.opList3] +type=OpDesc +eventq_index=0 +opClass=FloatDiv +opLat=12 +pipelined=false + +[system.cpu.fuPool.FUList3.opList4] +type=OpDesc +eventq_index=0 +opClass=FloatSqrt +opLat=24 +pipelined=false + +[system.cpu.fuPool.FUList4] +type=FUDesc +children=opList0 opList1 +count=0 +eventq_index=0 +opList=system.cpu.fuPool.FUList4.opList0 system.cpu.fuPool.FUList4.opList1 + +[system.cpu.fuPool.FUList4.opList0] +type=OpDesc +eventq_index=0 +opClass=MemRead +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList4.opList1] +type=OpDesc +eventq_index=0 +opClass=FloatMemRead +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5] +type=FUDesc +children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 +count=4 +eventq_index=0 +opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 + +[system.cpu.fuPool.FUList5.opList00] +type=OpDesc +eventq_index=0 +opClass=SimdAdd +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList01] +type=OpDesc +eventq_index=0 +opClass=SimdAddAcc +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList02] +type=OpDesc +eventq_index=0 +opClass=SimdAlu +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList03] +type=OpDesc +eventq_index=0 +opClass=SimdCmp +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList04] +type=OpDesc +eventq_index=0 +opClass=SimdCvt +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList05] +type=OpDesc +eventq_index=0 +opClass=SimdMisc +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList06] +type=OpDesc +eventq_index=0 +opClass=SimdMult +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList07] +type=OpDesc +eventq_index=0 +opClass=SimdMultAcc +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList08] +type=OpDesc +eventq_index=0 +opClass=SimdShift +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList09] +type=OpDesc +eventq_index=0 +opClass=SimdShiftAcc +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList10] +type=OpDesc +eventq_index=0 +opClass=SimdSqrt +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList11] +type=OpDesc +eventq_index=0 +opClass=SimdFloatAdd +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList12] +type=OpDesc +eventq_index=0 +opClass=SimdFloatAlu +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList13] +type=OpDesc +eventq_index=0 +opClass=SimdFloatCmp +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList14] +type=OpDesc +eventq_index=0 +opClass=SimdFloatCvt +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList15] +type=OpDesc +eventq_index=0 +opClass=SimdFloatDiv +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList16] +type=OpDesc +eventq_index=0 +opClass=SimdFloatMisc +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList17] +type=OpDesc +eventq_index=0 +opClass=SimdFloatMult +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList18] +type=OpDesc +eventq_index=0 +opClass=SimdFloatMultAcc +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList19] +type=OpDesc +eventq_index=0 +opClass=SimdFloatSqrt +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList6] +type=FUDesc +children=opList0 opList1 +count=0 +eventq_index=0 +opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1 + +[system.cpu.fuPool.FUList6.opList0] +type=OpDesc +eventq_index=0 +opClass=MemWrite +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList6.opList1] +type=OpDesc +eventq_index=0 +opClass=FloatMemWrite +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList7] +type=FUDesc +children=opList0 opList1 opList2 opList3 +count=4 +eventq_index=0 +opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 system.cpu.fuPool.FUList7.opList2 system.cpu.fuPool.FUList7.opList3 + +[system.cpu.fuPool.FUList7.opList0] +type=OpDesc +eventq_index=0 +opClass=MemRead +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList7.opList1] +type=OpDesc +eventq_index=0 +opClass=MemWrite +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList7.opList2] +type=OpDesc +eventq_index=0 +opClass=FloatMemRead +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList7.opList3] +type=OpDesc +eventq_index=0 +opClass=FloatMemWrite +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList8] +type=FUDesc +children=opList +count=1 +eventq_index=0 +opList=system.cpu.fuPool.FUList8.opList + +[system.cpu.fuPool.FUList8.opList] +type=OpDesc +eventq_index=0 +opClass=IprAccess +opLat=3 +pipelined=false + +[system.cpu.icache] +type=Cache +children=tags +addr_ranges=0:18446744073709551615:0:0:0:0 +assoc=2 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +data_latency=2 +default_p_state=UNDEFINED +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=true +max_miss_count=0 +mshrs=4 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=131072 +system=system +tag_latency=2 +tags=system.cpu.icache.tags +tgts_per_mshr=20 +write_buffers=8 +writeback_clean=true +cpu_side=system.cpu.icache_port +mem_side=system.cpu.toL2Bus.slave[0] + +[system.cpu.icache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +data_latency=2 +default_p_state=UNDEFINED +eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +sequential_access=false +size=131072 +tag_latency=2 + +[system.cpu.interrupts] +type=RiscvInterrupts +eventq_index=0 + +[system.cpu.isa] +type=RiscvISA +eventq_index=0 + +[system.cpu.itb] +type=RiscvTLB +eventq_index=0 +size=64 + +[system.cpu.l2cache] +type=Cache +children=tags +addr_ranges=0:18446744073709551615:0:0:0:0 +assoc=8 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +data_latency=20 +default_p_state=UNDEFINED +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=20 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +prefetch_on_access=false +prefetcher=Null +response_latency=20 +sequential_access=false +size=2097152 +system=system +tag_latency=20 +tags=system.cpu.l2cache.tags +tgts_per_mshr=12 +write_buffers=8 +writeback_clean=false +cpu_side=system.cpu.toL2Bus.master[0] +mem_side=system.membus.slave[1] + +[system.cpu.l2cache.tags] +type=LRU +assoc=8 +block_size=64 +clk_domain=system.cpu_clk_domain +data_latency=20 +default_p_state=UNDEFINED +eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +sequential_access=false +size=2097152 +tag_latency=20 + +[system.cpu.toL2Bus] +type=CoherentXBar +children=snoop_filter +clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED +eventq_index=0 +forward_latency=0 +frontend_latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +point_of_coherency=false +power_model=Null +response_latency=1 +snoop_filter=system.cpu.toL2Bus.snoop_filter +snoop_response_latency=1 +system=system +use_default_range=false +width=32 +master=system.cpu.l2cache.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side + +[system.cpu.toL2Bus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=0 +max_capacity=8388608 +system=system + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=LiveProcess +cmd=hello +cwd= +drivers= +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable=/z/powerjg/gem5-upstream/tests/test-progs/hello/bin/riscv/linux/hello +gid=100 +input=cin +kvmInSE=false +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=0 +system=system +uid=100 +useArchPT=false + +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000000 + +[system.membus] +type=CoherentXBar +children=snoop_filter +clk_domain=system.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +forward_latency=4 +frontend_latency=3 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +point_of_coherency=true +power_model=Null +response_latency=2 +snoop_filter=system.membus.snoop_filter +snoop_response_latency=4 +system=system +use_default_range=false +width=16 +master=system.physmem.port +slave=system.system_port system.cpu.l2cache.mem_side + +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + +[system.physmem] +type=DRAMCtrl +IDD0=0.055000 +IDD02=0.000000 +IDD2N=0.032000 +IDD2N2=0.000000 +IDD2P0=0.000000 +IDD2P02=0.000000 +IDD2P1=0.032000 +IDD2P12=0.000000 +IDD3N=0.038000 +IDD3N2=0.000000 +IDD3P0=0.000000 +IDD3P02=0.000000 +IDD3P1=0.038000 +IDD3P12=0.000000 +IDD4R=0.157000 +IDD4R2=0.000000 +IDD4W=0.125000 +IDD4W2=0.000000 +IDD5=0.235000 +IDD52=0.000000 +IDD6=0.020000 +IDD62=0.000000 +VDD=1.500000 +VDD2=0.000000 +activation_limit=4 +addr_mapping=RoRaBaCoCh +bank_groups_per_rank=0 +banks_per_rank=8 +burst_length=8 +channels=1 +clk_domain=system.clk_domain +conf_table_reported=true +default_p_state=UNDEFINED +device_bus_width=8 +device_rowbuffer_size=1024 +device_size=536870912 +devices_per_rank=8 +dll=true +eventq_index=0 +in_addr_map=true +kvm_map=true +max_accesses_per_row=16 +mem_sched_policy=frfcfs +min_writes_per_switch=16 +null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +page_policy=open_adaptive +power_model=Null +range=0:134217727:0:0:0:0 +ranks_per_channel=2 +read_buffer_size=32 +static_backend_latency=10000 +static_frontend_latency=10000 +tBURST=5000 +tCCD_L=0 +tCK=1250 +tCL=13750 +tCS=2500 +tRAS=35000 +tRCD=13750 +tREFI=7800000 +tRFC=260000 +tRP=13750 +tRRD=6000 +tRRD_L=0 +tRTP=7500 +tRTW=2500 +tWR=15000 +tWTR=7500 +tXAW=30000 +tXP=6000 +tXPDLL=0 +tXS=270000 +tXSDLL=0 +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 +port=system.membus.master[0] + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + diff --git a/tests/quick/se/00.hello/ref/riscv/linux/o3-timing/config.json b/tests/quick/se/00.hello/ref/riscv/linux/o3-timing/config.json new file mode 100644 index 000000000..45f6dace0 --- /dev/null +++ b/tests/quick/se/00.hello/ref/riscv/linux/o3-timing/config.json @@ -0,0 +1,1151 @@ +{ + "name": null, + "sim_quantum": 0, + "system": { + "kernel": "", + "mmap_using_noreserve": false, + "kernel_addr_check": true, + "membus": { + "point_of_coherency": true, + "system": "system", + "response_latency": 2, + "cxx_class": "CoherentXBar", + "forward_latency": 4, + "clk_domain": "system.clk_domain", + "width": 16, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "master": { + "peer": [ + "system.physmem.port" + ], + "role": "MASTER" + }, + "type": "CoherentXBar", + "frontend_latency": 3, + "slave": { + "peer": [ + "system.system_port", + "system.cpu.l2cache.mem_side" + ], + "role": "SLAVE" + }, + "p_state_clk_gate_min": 1000, + "snoop_filter": { + "name": "snoop_filter", + "system": "system", + "max_capacity": 8388608, + "eventq_index": 0, + "cxx_class": "SnoopFilter", + "path": "system.membus.snoop_filter", + "type": "SnoopFilter", + "lookup_latency": 1 + }, + "power_model": null, + "path": "system.membus", + "snoop_response_latency": 4, + "name": "membus", + "p_state_clk_gate_bins": 20, + "use_default_range": false + }, + "symbolfile": "", + "readfile": "", + "thermal_model": null, + "cxx_class": "System", + "work_begin_cpu_id_exit": -1, + "load_offset": 0, + "work_begin_exit_count": 0, + "p_state_clk_gate_min": 1000, + "memories": [ + "system.physmem" + ], + "work_begin_ckpt_count": 0, + "clk_domain": { + "name": "clk_domain", + "clock": [ + 1000 + ], + "init_perf_level": 0, + "voltage_domain": "system.voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "mem_ranges": [], + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "dvfs_handler": { + "enable": false, + "name": "dvfs_handler", + "sys_clk_domain": "system.clk_domain", + "transition_latency": 100000000, + "eventq_index": 0, + "cxx_class": "DVFSHandler", + "domains": [], + "path": "system.dvfs_handler", + "type": "DVFSHandler" + }, + "work_end_exit_count": 0, + "type": "System", + "voltage_domain": { + "name": "voltage_domain", + "eventq_index": 0, + "voltage": [ + "1.0" + ], + "cxx_class": "VoltageDomain", + "path": "system.voltage_domain", + "type": "VoltageDomain" + }, + "cache_line_size": 64, + "boot_osflags": "a", + "system_port": { + "peer": "system.membus.slave[0]", + "role": "MASTER" + }, + "physmem": { + "static_frontend_latency": 10000, + "tRFC": 260000, + "activation_limit": 4, + "in_addr_map": true, + "IDD3N2": "0.0", + "tWTR": 7500, + "IDD52": "0.0", + "clk_domain": "system.clk_domain", + "channels": 1, + "write_buffer_size": 64, + "device_bus_width": 8, + "VDD": "1.5", + "write_high_thresh_perc": 85, + "cxx_class": "DRAMCtrl", + "bank_groups_per_rank": 0, + "IDD2N2": "0.0", + "port": { + "peer": "system.membus.master[0]", + "role": "SLAVE" + }, + "tCCD_L": 0, + "IDD2N": "0.032", + "p_state_clk_gate_min": 1000, + "null": false, + "IDD2P1": "0.032", + "eventq_index": 0, + "tRRD": 6000, + "tRTW": 2500, + "IDD4R": "0.157", + "burst_length": 8, + "tRTP": 7500, + "IDD4W": "0.125", + "tWR": 15000, + "banks_per_rank": 8, + "devices_per_rank": 8, + "IDD2P02": "0.0", + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "IDD6": "0.02", + "IDD5": "0.235", + "tRCD": 13750, + "type": "DRAMCtrl", + "IDD3P02": "0.0", + "tRRD_L": 0, + "IDD0": "0.055", + "IDD62": "0.0", + "min_writes_per_switch": 16, + "mem_sched_policy": "frfcfs", + "IDD02": "0.0", + "IDD2P0": "0.0", + "ranks_per_channel": 2, + "page_policy": "open_adaptive", + "IDD4W2": "0.0", + "tCS": 2500, + "power_model": null, + "tCL": 13750, + "read_buffer_size": 32, + "conf_table_reported": true, + "tCK": 1250, + "tRAS": 35000, + "tRP": 13750, + "tBURST": 5000, + "path": "system.physmem", + "tXP": 6000, + "tXS": 270000, + "addr_mapping": "RoRaBaCoCh", + "IDD3P0": "0.0", + "IDD3P1": "0.038", + "IDD3N": "0.038", + "name": "physmem", + "tXSDLL": 0, + "device_size": 536870912, + "kvm_map": true, + "dll": true, + "tXAW": 30000, + "write_low_thresh_perc": 50, + "range": "0:134217727:0:0:0:0", + "VDD2": "0.0", + "IDD2P12": "0.0", + "p_state_clk_gate_bins": 20, + "tXPDLL": 0, + "IDD4R2": "0.0", + "device_rowbuffer_size": 1024, + "static_backend_latency": 10000, + "max_accesses_per_row": 16, + "IDD3P12": "0.0", + "tREFI": 7800000 + }, + "power_model": null, + "work_cpus_ckpt_count": 0, + "thermal_components": [], + "path": "system", + "cpu_clk_domain": { + "name": "cpu_clk_domain", + "clock": [ + 500 + ], + "init_perf_level": 0, + "voltage_domain": "system.voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.cpu_clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "work_end_ckpt_count": 0, + "mem_mode": "timing", + "name": "system", + "init_param": 0, + "p_state_clk_gate_bins": 20, + "load_addr_mask": 1099511627775, + "cpu": [ + { + "SQEntries": 32, + "smtLSQThreshold": 100, + "fetchTrapLatency": 1, + "iewToRenameDelay": 1, + "l2cache": { + "cpu_side": { + "peer": "system.cpu.toL2Bus.master[0]", + "role": "SLAVE" + }, + "clusivity": "mostly_incl", + "prefetcher": null, + "system": "system", + "write_buffers": 8, + "response_latency": 20, + "cxx_class": "Cache", + "size": 2097152, + "type": "Cache", + "clk_domain": "system.cpu_clk_domain", + "max_miss_count": 0, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "mem_side": { + "peer": "system.membus.slave[1]", + "role": "MASTER" + }, + "mshrs": 20, + "writeback_clean": false, + "p_state_clk_gate_min": 1000, + "tags": { + "size": 2097152, + "tag_latency": 20, + "name": "tags", + "p_state_clk_gate_min": 1000, + "eventq_index": 0, + "p_state_clk_gate_bins": 20, + "default_p_state": "UNDEFINED", + "clk_domain": "system.cpu_clk_domain", + "power_model": null, + "sequential_access": false, + "assoc": 8, + "cxx_class": "LRU", + "p_state_clk_gate_max": 1000000000000, + "path": "system.cpu.l2cache.tags", + "block_size": 64, + "type": "LRU", + "data_latency": 20 + }, + "tgts_per_mshr": 12, + "demand_mshr_reserve": 1, + "power_model": null, + "addr_ranges": [ + "0:18446744073709551615:0:0:0:0" + ], + "is_read_only": false, + "prefetch_on_access": false, + "path": "system.cpu.l2cache", + "data_latency": 20, + "tag_latency": 20, + "name": "l2cache", + "p_state_clk_gate_bins": 20, + "sequential_access": false, + "assoc": 8 + }, + "itb": { + "name": "itb", + "eventq_index": 0, + "cxx_class": "RiscvISA::TLB", + "path": "system.cpu.itb", + "type": "RiscvTLB", + "size": 64 + }, + "fetchWidth": 8, + "max_loads_all_threads": 0, + "cpu_id": 0, + "fetchToDecodeDelay": 1, + "renameToDecodeDelay": 1, + "do_quiesce": true, + "renameToROBDelay": 1, + "power_model": null, + "max_insts_all_threads": 0, + "decodeWidth": 8, + "commitToFetchDelay": 1, + "needsTSO": false, + "smtIQThreshold": 100, + "workload": [ + { + "uid": 100, + "pid": 100, + "kvmInSE": false, + "cxx_class": "LiveProcess", + "executable": "/z/powerjg/gem5-upstream/tests/test-progs/hello/bin/riscv/linux/hello", + "drivers": [], + "system": "system", + "gid": 100, + "eventq_index": 0, + "env": [], + "input": "cin", + "ppid": 99, + "type": "LiveProcess", + "cwd": "", + "simpoint": 0, + "euid": 100, + "path": "system.cpu.workload", + "max_stack_size": 67108864, + "name": "workload", + "cmd": [ + "hello" + ], + "errout": "cerr", + "useArchPT": false, + "egid": 100, + "output": "cout" + } + ], + "name": "cpu", + "SSITSize": 1024, + "activity": 0, + "max_loads_any_thread": 0, + "tracer": { + "eventq_index": 0, + "path": "system.cpu.tracer", + "type": "ExeTracer", + "name": "tracer", + "cxx_class": "Trace::ExeTracer" + }, + "decodeToFetchDelay": 1, + "renameWidth": 8, + "numThreads": 1, + "squashWidth": 8, + "function_trace": false, + "backComSize": 5, + "decodeToRenameDelay": 1, + "store_set_clear_period": 250000, + "numPhysIntRegs": 256, + "p_state_clk_gate_max": 1000000000000, + "toL2Bus": { + "point_of_coherency": false, + "system": "system", + "response_latency": 1, + "cxx_class": "CoherentXBar", + "forward_latency": 0, + "clk_domain": "system.cpu_clk_domain", + "width": 32, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "master": { + "peer": [ + "system.cpu.l2cache.cpu_side" + ], + "role": "MASTER" + }, + "type": "CoherentXBar", + "frontend_latency": 1, + "slave": { + "peer": [ + "system.cpu.icache.mem_side", + "system.cpu.dcache.mem_side" + ], + "role": "SLAVE" + }, + "p_state_clk_gate_min": 1000, + "snoop_filter": { + "name": "snoop_filter", + "system": "system", + "max_capacity": 8388608, + "eventq_index": 0, + "cxx_class": "SnoopFilter", + "path": "system.cpu.toL2Bus.snoop_filter", + "type": "SnoopFilter", + "lookup_latency": 0 + }, + "power_model": null, + "path": "system.cpu.toL2Bus", + "snoop_response_latency": 1, + "name": "toL2Bus", + "p_state_clk_gate_bins": 20, + "use_default_range": false + }, + "p_state_clk_gate_min": 1000, + "fuPool": { + "name": "fuPool", + "FUList": [ + { + "count": 6, + "opList": [ + { + "opClass": "IntAlu", + "opLat": 1, + "name": "opList", + "pipelined": true, + "eventq_index": 0, + "cxx_class": "OpDesc", + "path": "system.cpu.fuPool.FUList0.opList", + "type": "OpDesc" + } + ], + "name": "FUList0", + "eventq_index": 0, + "cxx_class": "FUDesc", + "path": "system.cpu.fuPool.FUList0", + "type": "FUDesc" + }, + { + "count": 2, + "opList": [ + { + "opClass": "IntMult", + "opLat": 3, + "name": "opList0", + "pipelined": true, + "eventq_index": 0, + "cxx_class": "OpDesc", + "path": "system.cpu.fuPool.FUList1.opList0", + "type": "OpDesc" + }, + { + "opClass": "IntDiv", + "opLat": 20, + "name": "opList1", + "pipelined": false, + "eventq_index": 0, + "cxx_class": "OpDesc", + "path": "system.cpu.fuPool.FUList1.opList1", + "type": "OpDesc" + } + ], + "name": "FUList1", + "eventq_index": 0, + "cxx_class": "FUDesc", + "path": "system.cpu.fuPool.FUList1", + "type": "FUDesc" + }, + { + "count": 4, + "opList": [ + { + "opClass": "FloatAdd", + "opLat": 2, + "name": "opList0", + "pipelined": true, + "eventq_index": 0, + "cxx_class": "OpDesc", + "path": "system.cpu.fuPool.FUList2.opList0", + "type": "OpDesc" + }, + { + "opClass": "FloatCmp", + "opLat": 2, + "name": "opList1", + "pipelined": true, + "eventq_index": 0, + "cxx_class": "OpDesc", + "path": "system.cpu.fuPool.FUList2.opList1", + "type": "OpDesc" + }, + { + "opClass": "FloatCvt", + "opLat": 2, + "name": "opList2", + "pipelined": true, + "eventq_index": 0, + "cxx_class": "OpDesc", + "path": "system.cpu.fuPool.FUList2.opList2", + "type": "OpDesc" + } + ], + "name": "FUList2", + "eventq_index": 0, + "cxx_class": "FUDesc", + "path": "system.cpu.fuPool.FUList2", + "type": "FUDesc" + }, + { + "count": 2, + "opList": [ + { + "opClass": "FloatMult", + "opLat": 4, + "name": "opList0", + "pipelined": true, + "eventq_index": 0, + "cxx_class": "OpDesc", + "path": "system.cpu.fuPool.FUList3.opList0", + "type": "OpDesc" + }, + { + "opClass": "FloatMultAcc", + "opLat": 5, + "name": "opList1", + "pipelined": true, + "eventq_index": 0, + "cxx_class": "OpDesc", + "path": "system.cpu.fuPool.FUList3.opList1", + "type": "OpDesc" + }, + { + "opClass": "FloatMisc", + "opLat": 3, + "name": "opList2", + "pipelined": true, + "eventq_index": 0, + "cxx_class": "OpDesc", + "path": "system.cpu.fuPool.FUList3.opList2", + "type": "OpDesc" + }, + { + "opClass": "FloatDiv", + "opLat": 12, + "name": "opList3", + "pipelined": false, + "eventq_index": 0, + "cxx_class": "OpDesc", + "path": "system.cpu.fuPool.FUList3.opList3", + "type": "OpDesc" + }, + { + "opClass": "FloatSqrt", + "opLat": 24, + "name": "opList4", + "pipelined": false, + "eventq_index": 0, + "cxx_class": "OpDesc", + "path": "system.cpu.fuPool.FUList3.opList4", + "type": "OpDesc" + } + ], + "name": "FUList3", + "eventq_index": 0, + "cxx_class": "FUDesc", + "path": "system.cpu.fuPool.FUList3", + "type": "FUDesc" + }, + { + "count": 0, + "opList": [ + { + "opClass": "MemRead", + "opLat": 1, + "name": "opList0", + "pipelined": true, + "eventq_index": 0, + "cxx_class": "OpDesc", + "path": "system.cpu.fuPool.FUList4.opList0", + "type": "OpDesc" + }, + { + "opClass": "FloatMemRead", + "opLat": 1, + "name": "opList1", + "pipelined": true, + "eventq_index": 0, + "cxx_class": "OpDesc", + "path": "system.cpu.fuPool.FUList4.opList1", + "type": "OpDesc" + } + ], + "name": "FUList4", + "eventq_index": 0, + "cxx_class": "FUDesc", + "path": "system.cpu.fuPool.FUList4", + "type": "FUDesc" + }, + { + "count": 4, + "opList": [ + { + "opClass": "SimdAdd", + "opLat": 1, + "name": "opList00", + "pipelined": true, + "eventq_index": 0, + "cxx_class": "OpDesc", + "path": "system.cpu.fuPool.FUList5.opList00", + "type": "OpDesc" + }, + { + "opClass": "SimdAddAcc", + "opLat": 1, + "name": "opList01", + "pipelined": true, + "eventq_index": 0, + "cxx_class": "OpDesc", + "path": "system.cpu.fuPool.FUList5.opList01", + "type": "OpDesc" + }, + { + "opClass": "SimdAlu", + "opLat": 1, + "name": "opList02", + "pipelined": true, + "eventq_index": 0, + "cxx_class": "OpDesc", + "path": "system.cpu.fuPool.FUList5.opList02", + "type": "OpDesc" + }, + { + "opClass": "SimdCmp", + "opLat": 1, + "name": "opList03", + "pipelined": true, + "eventq_index": 0, + "cxx_class": "OpDesc", + "path": "system.cpu.fuPool.FUList5.opList03", + "type": "OpDesc" + }, + { + "opClass": "SimdCvt", + "opLat": 1, + "name": "opList04", + "pipelined": true, + "eventq_index": 0, + "cxx_class": "OpDesc", + "path": "system.cpu.fuPool.FUList5.opList04", + "type": "OpDesc" + }, + { + "opClass": "SimdMisc", + "opLat": 1, + "name": "opList05", + "pipelined": true, + "eventq_index": 0, + "cxx_class": "OpDesc", + "path": "system.cpu.fuPool.FUList5.opList05", + "type": "OpDesc" + }, + { + "opClass": "SimdMult", + "opLat": 1, + "name": "opList06", + "pipelined": true, + "eventq_index": 0, + "cxx_class": "OpDesc", + "path": "system.cpu.fuPool.FUList5.opList06", + "type": "OpDesc" + }, + { + "opClass": "SimdMultAcc", + "opLat": 1, + "name": "opList07", + "pipelined": true, + "eventq_index": 0, + "cxx_class": "OpDesc", + "path": "system.cpu.fuPool.FUList5.opList07", + "type": "OpDesc" + }, + { + "opClass": "SimdShift", + "opLat": 1, + "name": "opList08", + "pipelined": true, + "eventq_index": 0, + "cxx_class": "OpDesc", + "path": "system.cpu.fuPool.FUList5.opList08", + "type": "OpDesc" + }, + { + "opClass": "SimdShiftAcc", + "opLat": 1, + "name": "opList09", + "pipelined": true, + "eventq_index": 0, + "cxx_class": "OpDesc", + "path": "system.cpu.fuPool.FUList5.opList09", + "type": "OpDesc" + }, + { + "opClass": "SimdSqrt", + "opLat": 1, + "name": "opList10", + "pipelined": true, + "eventq_index": 0, + "cxx_class": "OpDesc", + "path": "system.cpu.fuPool.FUList5.opList10", + "type": "OpDesc" + }, + { + "opClass": "SimdFloatAdd", + "opLat": 1, + "name": "opList11", + "pipelined": true, + "eventq_index": 0, + "cxx_class": "OpDesc", + "path": "system.cpu.fuPool.FUList5.opList11", + "type": "OpDesc" + }, + { + "opClass": "SimdFloatAlu", + "opLat": 1, + "name": "opList12", + "pipelined": true, + "eventq_index": 0, + "cxx_class": "OpDesc", + "path": "system.cpu.fuPool.FUList5.opList12", + "type": "OpDesc" + }, + { + "opClass": "SimdFloatCmp", + "opLat": 1, + "name": "opList13", + "pipelined": true, + "eventq_index": 0, + "cxx_class": "OpDesc", + "path": "system.cpu.fuPool.FUList5.opList13", + "type": "OpDesc" + }, + { + "opClass": "SimdFloatCvt", + "opLat": 1, + "name": "opList14", + "pipelined": true, + "eventq_index": 0, + "cxx_class": "OpDesc", + "path": "system.cpu.fuPool.FUList5.opList14", + "type": "OpDesc" + }, + { + "opClass": "SimdFloatDiv", + "opLat": 1, + "name": "opList15", + "pipelined": true, + "eventq_index": 0, + "cxx_class": "OpDesc", + "path": "system.cpu.fuPool.FUList5.opList15", + "type": "OpDesc" + }, + { + "opClass": "SimdFloatMisc", + "opLat": 1, + "name": "opList16", + "pipelined": true, + "eventq_index": 0, + "cxx_class": "OpDesc", + "path": "system.cpu.fuPool.FUList5.opList16", + "type": "OpDesc" + }, + { + "opClass": "SimdFloatMult", + "opLat": 1, + "name": "opList17", + "pipelined": true, + "eventq_index": 0, + "cxx_class": "OpDesc", + "path": "system.cpu.fuPool.FUList5.opList17", + "type": "OpDesc" + }, + { + "opClass": "SimdFloatMultAcc", + "opLat": 1, + "name": "opList18", + "pipelined": true, + "eventq_index": 0, + "cxx_class": "OpDesc", + "path": "system.cpu.fuPool.FUList5.opList18", + "type": "OpDesc" + }, + { + "opClass": "SimdFloatSqrt", + "opLat": 1, + "name": "opList19", + "pipelined": true, + "eventq_index": 0, + "cxx_class": "OpDesc", + "path": "system.cpu.fuPool.FUList5.opList19", + "type": "OpDesc" + } + ], + "name": "FUList5", + "eventq_index": 0, + "cxx_class": "FUDesc", + "path": "system.cpu.fuPool.FUList5", + "type": "FUDesc" + }, + { + "count": 0, + "opList": [ + { + "opClass": "MemWrite", + "opLat": 1, + "name": "opList0", + "pipelined": true, + "eventq_index": 0, + "cxx_class": "OpDesc", + "path": "system.cpu.fuPool.FUList6.opList0", + "type": "OpDesc" + }, + { + "opClass": "FloatMemWrite", + "opLat": 1, + "name": "opList1", + "pipelined": true, + "eventq_index": 0, + "cxx_class": "OpDesc", + "path": "system.cpu.fuPool.FUList6.opList1", + "type": "OpDesc" + } + ], + "name": "FUList6", + "eventq_index": 0, + "cxx_class": "FUDesc", + "path": "system.cpu.fuPool.FUList6", + "type": "FUDesc" + }, + { + "count": 4, + "opList": [ + { + "opClass": "MemRead", + "opLat": 1, + "name": "opList0", + "pipelined": true, + "eventq_index": 0, + "cxx_class": "OpDesc", + "path": "system.cpu.fuPool.FUList7.opList0", + "type": "OpDesc" + }, + { + "opClass": "MemWrite", + "opLat": 1, + "name": "opList1", + "pipelined": true, + "eventq_index": 0, + "cxx_class": "OpDesc", + "path": "system.cpu.fuPool.FUList7.opList1", + "type": "OpDesc" + }, + { + "opClass": "FloatMemRead", + "opLat": 1, + "name": "opList2", + "pipelined": true, + "eventq_index": 0, + "cxx_class": "OpDesc", + "path": "system.cpu.fuPool.FUList7.opList2", + "type": "OpDesc" + }, + { + "opClass": "FloatMemWrite", + "opLat": 1, + "name": "opList3", + "pipelined": true, + "eventq_index": 0, + "cxx_class": "OpDesc", + "path": "system.cpu.fuPool.FUList7.opList3", + "type": "OpDesc" + } + ], + "name": "FUList7", + "eventq_index": 0, + "cxx_class": "FUDesc", + "path": "system.cpu.fuPool.FUList7", + "type": "FUDesc" + }, + { + "count": 1, + "opList": [ + { + "opClass": "IprAccess", + "opLat": 3, + "name": "opList", + "pipelined": false, + "eventq_index": 0, + "cxx_class": "OpDesc", + "path": "system.cpu.fuPool.FUList8.opList", + "type": "OpDesc" + } + ], + "name": "FUList8", + "eventq_index": 0, + "cxx_class": "FUDesc", + "path": "system.cpu.fuPool.FUList8", + "type": "FUDesc" + } + ], + "eventq_index": 0, + "cxx_class": "FUPool", + "path": "system.cpu.fuPool", + "type": "FUPool" + }, + "socket_id": 0, + "renameToFetchDelay": 1, + "icache": { + "cpu_side": { + "peer": "system.cpu.icache_port", + "role": "SLAVE" + }, + "clusivity": "mostly_incl", + "prefetcher": null, + "system": "system", + "write_buffers": 8, + "response_latency": 2, + "cxx_class": "Cache", + "size": 131072, + "type": "Cache", + "clk_domain": "system.cpu_clk_domain", + "max_miss_count": 0, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "mem_side": { + "peer": "system.cpu.toL2Bus.slave[0]", + "role": "MASTER" + }, + "mshrs": 4, + "writeback_clean": true, + "p_state_clk_gate_min": 1000, + "tags": { + "size": 131072, + "tag_latency": 2, + "name": "tags", + "p_state_clk_gate_min": 1000, + "eventq_index": 0, + "p_state_clk_gate_bins": 20, + "default_p_state": "UNDEFINED", + "clk_domain": "system.cpu_clk_domain", + "power_model": null, + "sequential_access": false, + "assoc": 2, + "cxx_class": "LRU", + "p_state_clk_gate_max": 1000000000000, + "path": "system.cpu.icache.tags", + "block_size": 64, + "type": "LRU", + "data_latency": 2 + }, + "tgts_per_mshr": 20, + "demand_mshr_reserve": 1, + "power_model": null, + "addr_ranges": [ + "0:18446744073709551615:0:0:0:0" + ], + "is_read_only": true, + "prefetch_on_access": false, + "path": "system.cpu.icache", + "data_latency": 2, + "tag_latency": 2, + "name": "icache", + "p_state_clk_gate_bins": 20, + "sequential_access": false, + "assoc": 2 + }, + "path": "system.cpu", + "numRobs": 1, + "switched_out": false, + "smtLSQPolicy": "Partitioned", + "fetchBufferSize": 64, + "simpoint_start_insts": [], + "max_insts_any_thread": 0, + "smtROBThreshold": 100, + "numIQEntries": 64, + "branchPred": { + "numThreads": 1, + "BTBEntries": 4096, + "cxx_class": "TournamentBP", + "indirectPathLength": 3, + "globalCtrBits": 2, + "choicePredictorSize": 8192, + "indirectHashGHR": true, + "eventq_index": 0, + "localHistoryTableSize": 2048, + "type": "TournamentBP", + "indirectSets": 256, + "indirectWays": 2, + "choiceCtrBits": 2, + "useIndirect": true, + "localCtrBits": 2, + "path": "system.cpu.branchPred", + "localPredictorSize": 2048, + "RASSize": 16, + "globalPredictorSize": 8192, + "name": "branchPred", + "indirectHashTargets": true, + "instShiftAmt": 2, + "indirectTagSize": 16, + "BTBTagSize": 16 + }, + "LFSTSize": 1024, + "isa": [ + { + "eventq_index": 0, + "path": "system.cpu.isa", + "type": "RiscvISA", + "name": "isa", + "cxx_class": "RiscvISA::ISA" + } + ], + "smtROBPolicy": "Partitioned", + "iewToFetchDelay": 1, + "do_statistics_insts": true, + "dispatchWidth": 8, + "dcache": { + "cpu_side": { + "peer": "system.cpu.dcache_port", + "role": "SLAVE" + }, + "clusivity": "mostly_incl", + "prefetcher": null, + "system": "system", + "write_buffers": 8, + "response_latency": 2, + "cxx_class": "Cache", + "size": 262144, + "type": "Cache", + "clk_domain": "system.cpu_clk_domain", + "max_miss_count": 0, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "mem_side": { + "peer": "system.cpu.toL2Bus.slave[1]", + "role": "MASTER" + }, + "mshrs": 4, + "writeback_clean": false, + "p_state_clk_gate_min": 1000, + "tags": { + "size": 262144, + "tag_latency": 2, + "name": "tags", + "p_state_clk_gate_min": 1000, + "eventq_index": 0, + "p_state_clk_gate_bins": 20, + "default_p_state": "UNDEFINED", + "clk_domain": "system.cpu_clk_domain", + "power_model": null, + "sequential_access": false, + "assoc": 2, + "cxx_class": "LRU", + "p_state_clk_gate_max": 1000000000000, + "path": "system.cpu.dcache.tags", + "block_size": 64, + "type": "LRU", + "data_latency": 2 + }, + "tgts_per_mshr": 20, + "demand_mshr_reserve": 1, + "power_model": null, + "addr_ranges": [ + "0:18446744073709551615:0:0:0:0" + ], + "is_read_only": false, + "prefetch_on_access": false, + "path": "system.cpu.dcache", + "data_latency": 2, + "tag_latency": 2, + "name": "dcache", + "p_state_clk_gate_bins": 20, + "sequential_access": false, + "assoc": 2 + }, + "commitToDecodeDelay": 1, + "smtIQPolicy": "Partitioned", + "issueWidth": 8, + "LSQCheckLoads": true, + "commitToRenameDelay": 1, + "cachePorts": 200, + "system": "system", + "checker": null, + "numPhysFloatRegs": 256, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "type": "DerivO3CPU", + "wbWidth": 8, + "interrupts": [ + { + "eventq_index": 0, + "path": "system.cpu.interrupts", + "type": "RiscvInterrupts", + "name": "interrupts", + "cxx_class": "RiscvISA::Interrupts" + } + ], + "smtCommitPolicy": "RoundRobin", + "issueToExecuteDelay": 1, + "dtb": { + "name": "dtb", + "eventq_index": 0, + "cxx_class": "RiscvISA::TLB", + "path": "system.cpu.dtb", + "type": "RiscvTLB", + "size": 64 + }, + "numROBEntries": 192, + "fetchQueueSize": 32, + "iewToCommitDelay": 1, + "smtNumFetchingThreads": 1, + "forwardComSize": 5, + "do_checkpoint_insts": true, + "cxx_class": "DerivO3CPU", + "commitToIEWDelay": 1, + "commitWidth": 8, + "clk_domain": "system.cpu_clk_domain", + "function_trace_start": 0, + "smtFetchPolicy": "SingleThread", + "profile": 0, + "icache_port": { + "peer": "system.cpu.icache.cpu_side", + "role": "MASTER" + }, + "dcache_port": { + "peer": "system.cpu.dcache.cpu_side", + "role": "MASTER" + }, + "LSQDepCheckShift": 4, + "trapLatency": 13, + "iewToDecodeDelay": 1, + "numPhysCCRegs": 0, + "renameToIEWDelay": 2, + "p_state_clk_gate_bins": 20, + "progress_interval": 0, + "LQEntries": 32 + } + ], + "multi_thread": false, + "exit_on_work_items": false, + "work_item_id": -1, + "num_work_ids": 16 + }, + "time_sync_period": 100000000000, + "eventq_index": 0, + "time_sync_spin_threshold": 100000000, + "cxx_class": "Root", + "path": "root", + "time_sync_enable": false, + "type": "Root", + "full_system": false +}
\ No newline at end of file diff --git a/tests/quick/se/00.hello/ref/riscv/linux/o3-timing/simerr b/tests/quick/se/00.hello/ref/riscv/linux/o3-timing/simerr new file mode 100755 index 000000000..85a6a33ad --- /dev/null +++ b/tests/quick/se/00.hello/ref/riscv/linux/o3-timing/simerr @@ -0,0 +1,4 @@ +warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes) +warn: Unknown operating system; assuming Linux. +warn: Sockets disabled, not accepting gdb connections +warn: ClockedObject: More than one power state change request encountered within the same simulation tick diff --git a/tests/quick/se/00.hello/ref/riscv/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/riscv/linux/o3-timing/simout new file mode 100755 index 000000000..d5153ce3d --- /dev/null +++ b/tests/quick/se/00.hello/ref/riscv/linux/o3-timing/simout @@ -0,0 +1,15 @@ +Redirecting stdout to build/RISCV/tests/opt/quick/se/00.hello/riscv/linux/o3-timing/simout +Redirecting stderr to build/RISCV/tests/opt/quick/se/00.hello/riscv/linux/o3-timing/simerr +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled Nov 30 2016 14:33:35 +gem5 started Nov 30 2016 16:18:28 +gem5 executing on zizzer, pid 34057 +command line: /z/powerjg/gem5-upstream/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/00.hello/riscv/linux/o3-timing -re /z/powerjg/gem5-upstream/tests/testing/../run.py quick/se/00.hello/riscv/linux/o3-timing + +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. +Hello world! +Exiting @ tick 7939500 because target called exit() diff --git a/tests/quick/se/00.hello/ref/riscv/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/riscv/linux/o3-timing/stats.txt new file mode 100644 index 000000000..25d8ca24a --- /dev/null +++ b/tests/quick/se/00.hello/ref/riscv/linux/o3-timing/stats.txt @@ -0,0 +1,1000 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.000008 # Number of seconds simulated +sim_ticks 7939500 # Number of ticks simulated +final_tick 7939500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 22942 # Simulator instruction rate (inst/s) +host_op_rate 22935 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 114711600 # Simulator tick rate (ticks/s) +host_mem_usage 232976 # Number of bytes of host memory used +host_seconds 0.07 # Real time elapsed on the host +sim_insts 1587 # Number of instructions simulated +sim_ops 1587 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 7939500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 9600 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 2048 # Number of bytes read from this memory +system.physmem.bytes_read::total 11648 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 9600 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 9600 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 150 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 32 # Number of read requests responded to by this memory +system.physmem.num_reads::total 182 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1209144153 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 257950753 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1467094905 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1209144153 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1209144153 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1209144153 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 257950753 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1467094905 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 184 # Number of read requests accepted +system.physmem.writeReqs 0 # Number of write requests accepted +system.physmem.readBursts 184 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 11648 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue +system.physmem.bytesWritten 0 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 11776 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 93 # Per bank write bursts +system.physmem.perBankRdBursts::1 62 # Per bank write bursts +system.physmem.perBankRdBursts::2 18 # Per bank write bursts +system.physmem.perBankRdBursts::3 9 # Per bank write bursts +system.physmem.perBankRdBursts::4 0 # Per bank write bursts +system.physmem.perBankRdBursts::5 0 # Per bank write bursts +system.physmem.perBankRdBursts::6 0 # Per bank write bursts +system.physmem.perBankRdBursts::7 0 # Per bank write bursts +system.physmem.perBankRdBursts::8 0 # Per bank write bursts +system.physmem.perBankRdBursts::9 0 # Per bank write bursts +system.physmem.perBankRdBursts::10 0 # Per bank write bursts +system.physmem.perBankRdBursts::11 0 # Per bank write bursts +system.physmem.perBankRdBursts::12 0 # Per bank write bursts +system.physmem.perBankRdBursts::13 0 # Per bank write bursts +system.physmem.perBankRdBursts::14 0 # Per bank write bursts +system.physmem.perBankRdBursts::15 0 # Per bank write bursts +system.physmem.perBankWrBursts::0 0 # Per bank write bursts +system.physmem.perBankWrBursts::1 0 # Per bank write bursts +system.physmem.perBankWrBursts::2 0 # Per bank write bursts +system.physmem.perBankWrBursts::3 0 # Per bank write bursts +system.physmem.perBankWrBursts::4 0 # Per bank write bursts +system.physmem.perBankWrBursts::5 0 # Per bank write bursts +system.physmem.perBankWrBursts::6 0 # Per bank write bursts +system.physmem.perBankWrBursts::7 0 # Per bank write bursts +system.physmem.perBankWrBursts::8 0 # Per bank write bursts +system.physmem.perBankWrBursts::9 0 # Per bank write bursts +system.physmem.perBankWrBursts::10 0 # Per bank write bursts +system.physmem.perBankWrBursts::11 0 # Per bank write bursts +system.physmem.perBankWrBursts::12 0 # Per bank write bursts +system.physmem.perBankWrBursts::13 0 # Per bank write bursts +system.physmem.perBankWrBursts::14 0 # Per bank write bursts +system.physmem.perBankWrBursts::15 0 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 7854500 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 184 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 0 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 94 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 60 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 24 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 5 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 13 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 896 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 813.228460 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 265.169128 # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 1 7.69% 7.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 1 7.69% 15.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1 7.69% 23.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1 7.69% 30.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 9 69.23% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 13 # Bytes accessed per row activation +system.physmem.totQLat 1405000 # Total ticks spent queuing +system.physmem.totMemAccLat 4817500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 910000 # Total ticks spent in databus transfers +system.physmem.avgQLat 7635.87 # Average queueing delay per DRAM burst +system.physmem.avgBusLat 4945.65 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 26182.07 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1467.09 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1483.22 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.busUtil 11.46 # Data bus utilization in percentage +system.physmem.busUtilRead 11.46 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.90 # Average read queue length when enqueuing +system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing +system.physmem.readRowHits 169 # Number of row buffer hits during reads +system.physmem.writeRowHits 0 # Number of row buffer hits during writes +system.physmem.readRowHitRate 91.85 # Row buffer hit rate for reads +system.physmem.writeRowHitRate nan # Row buffer hit rate for writes +system.physmem.avgGap 42687.50 # Average gap between requests +system.physmem.pageHitRate 91.85 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 92820 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 49335 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1299480 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 614640.000000 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1581180 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 10080 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 2075940 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 5723475 # Total energy per rank (pJ) +system.physmem_0.averagePower 711.322044 # Core power per rank (mW) +system.physmem_0.totalIdleTime 4551000 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 11500 # Time in different power states +system.physmem_0.memoryStateTime::REF 139500 # Time in different power states +system.physmem_0.memoryStateTime::SREF 0 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 3237500 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 4551000 # Time in different power states +system.physmem_1.actEnergy 0 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 0 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 0 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 614640.000000 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 112290 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 2989920 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 3716850 # Total energy per rank (pJ) +system.physmem_1.averagePower 462.726424 # Core power per rank (mW) +system.physmem_1.totalIdleTime 0 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 7786250 # Time in different power states +system.physmem_1.memoryStateTime::REF 153250 # Time in different power states +system.physmem_1.memoryStateTime::SREF 0 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 7939500 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 1252 # Number of BP lookups +system.cpu.branchPred.condPredicted 681 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 259 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 1186 # Number of BTB lookups +system.cpu.branchPred.BTBHits 300 # Number of BTB hits +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 25.295110 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 0 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 253 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 25 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 228 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 67 # Number of mispredicted indirect branches. +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 9 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 7939500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 15880 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.fetch.icacheStallCycles 3023 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 4970 # Number of instructions fetch has processed +system.cpu.fetch.Branches 1252 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 325 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 964 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 540 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 183 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 6 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 1 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 803 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 191 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 4447 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.117607 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.502607 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 3513 79.00% 79.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 134 3.01% 82.01% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 87 1.96% 83.97% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 91 2.05% 86.01% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 45 1.01% 87.02% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 71 1.60% 88.62% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 65 1.46% 90.08% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 64 1.44% 91.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 377 8.48% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 4447 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.078841 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.312972 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 3140 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 349 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 756 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 17 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 185 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 187 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 86 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 3862 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 255 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 185 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 3239 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 107 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 243 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 672 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 1 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 3496 # Number of instructions processed by rename +system.cpu.rename.LQFullEvents 2 # Number of times rename has blocked due to LQ full +system.cpu.rename.RenamedOperands 2449 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 4481 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 4481 # Number of integer rename lookups +system.cpu.rename.CommittedMaps 1077 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 1372 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 16 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 16 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 82 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 548 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 470 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 0 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 3003 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 17 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 2694 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 21 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 1432 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 769 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 8 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 4447 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.605802 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.426720 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 3524 79.24% 79.24% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 251 5.64% 84.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 185 4.16% 89.05% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 180 4.05% 93.10% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 147 3.31% 96.40% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 65 1.46% 97.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 57 1.28% 99.15% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 26 0.58% 99.73% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 12 0.27% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 4447 # Number of insts issued each cycle +system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 4 5.71% 5.71% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 5.71% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 5.71% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.71% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.71% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.71% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 5.71% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 5.71% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.71% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 0 0.00% 5.71% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 5.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 5.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.71% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 30 42.86% 48.57% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 36 51.43% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemRead 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemWrite 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.FU_type_0::No_OpClass 9 0.33% 0.33% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1755 65.14% 65.48% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 1 0.04% 65.52% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.52% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 65.52% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 65.52% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 65.52% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 65.52% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 65.52% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 65.52% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 65.52% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 65.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.52% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 512 19.01% 84.52% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 417 15.48% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemRead 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemWrite 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::total 2694 # Type of FU issued +system.cpu.iq.rate 0.169647 # Inst issue rate +system.cpu.iq.fu_busy_cnt 70 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.025984 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 9926 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 4453 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 2310 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2755 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 14 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread0.squashedLoads 259 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 1 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 1 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 191 # Number of stores squashed +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu.iew.iewSquashCycles 185 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 106 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 2 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 3020 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 66 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 548 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 470 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 17 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 3 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 1 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 12 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 187 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 199 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 2452 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 472 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 242 # Number of squashed instructions skipped in execute +system.cpu.iew.exec_swp 0 # number of swp insts executed +system.cpu.iew.exec_nop 0 # number of nop insts executed +system.cpu.iew.exec_refs 847 # number of memory reference insts executed +system.cpu.iew.exec_branches 563 # Number of branches executed +system.cpu.iew.exec_stores 375 # Number of stores executed +system.cpu.iew.exec_rate 0.154408 # Inst execution rate +system.cpu.iew.wb_sent 2361 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 2310 # cumulative count of insts written-back +system.cpu.iew.wb_producers 793 # num instructions producing a value +system.cpu.iew.wb_consumers 1130 # num instructions consuming a value +system.cpu.iew.wb_rate 0.145466 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.701770 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 1436 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 9 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 174 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 4156 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.381858 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.174026 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 3562 85.71% 85.71% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 208 5.00% 90.71% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 146 3.51% 94.23% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 85 2.05% 96.27% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 60 1.44% 97.71% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 34 0.82% 98.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 26 0.63% 99.16% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 14 0.34% 99.49% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 21 0.51% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 4156 # Number of insts commited each cycle +system.cpu.commit.committedInsts 1587 # Number of instructions committed +system.cpu.commit.committedOps 1587 # Number of ops (including micro ops) committed +system.cpu.commit.swp_count 0 # Number of s/w prefetches committed +system.cpu.commit.refs 568 # Number of memory references committed +system.cpu.commit.loads 289 # Number of loads committed +system.cpu.commit.membars 0 # Number of memory barriers committed +system.cpu.commit.branches 373 # Number of branches committed +system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. +system.cpu.commit.int_insts 1587 # Number of committed integer instructions. +system.cpu.commit.function_calls 142 # Number of function calls committed. +system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 1019 64.21% 64.21% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 0 0.00% 64.21% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 0 0.00% 64.21% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 0 0.00% 64.21% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 0 0.00% 64.21% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 0 0.00% 64.21% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 0 0.00% 64.21% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 64.21% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 0 0.00% 64.21% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMisc 0 0.00% 64.21% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 64.21% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 0 0.00% 64.21% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 64.21% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 0 0.00% 64.21% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 0 0.00% 64.21% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 64.21% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 0 0.00% 64.21% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 64.21% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 64.21% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 64.21% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 64.21% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 64.21% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 64.21% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 64.21% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 64.21% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 64.21% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 64.21% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 64.21% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 64.21% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 64.21% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 64.21% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 289 18.21% 82.42% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 279 17.58% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::total 1587 # Class of committed instruction +system.cpu.commit.bw_lim_events 21 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 7041 # The number of ROB reads +system.cpu.rob.rob_writes 6340 # The number of ROB writes +system.cpu.timesIdled 96 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 11433 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 1587 # Number of Instructions Simulated +system.cpu.committedOps 1587 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 10.006301 # CPI: Cycles Per Instruction +system.cpu.cpi_total 10.006301 # CPI: Total CPI of All Threads +system.cpu.ipc 0.099937 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.099937 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3068 # number of integer regfile reads +system.cpu.int_regfile_writes 1663 # number of integer regfile writes +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 7939500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 0 # number of replacements +system.cpu.dcache.tags.tagsinuse 24.179106 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 626 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 33 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 18.969697 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 24.179106 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.005903 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.005903 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 33 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 33 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.008057 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 1497 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1497 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 7939500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 432 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 432 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 194 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 194 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 626 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 626 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 626 # number of overall hits +system.cpu.dcache.overall_hits::total 626 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 21 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 21 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 85 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 85 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 106 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 106 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 106 # number of overall misses +system.cpu.dcache.overall_misses::total 106 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 1305000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 1305000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 6101500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 6101500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 7406500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 7406500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 7406500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 7406500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 453 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 453 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 279 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 279 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 732 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 732 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 732 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 732 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.046358 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.046358 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.304659 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.304659 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.144809 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.144809 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.144809 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.144809 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62142.857143 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 62142.857143 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 71782.352941 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 71782.352941 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 69872.641509 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 69872.641509 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 69872.641509 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 69872.641509 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 5 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 5 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 67 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 67 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 72 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 72 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 72 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 72 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 16 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 16 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 18 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 18 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 34 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 34 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 34 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 34 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1141000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 1141000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1431500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1431500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 2572500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 2572500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 2572500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 2572500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.035320 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.035320 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.064516 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.064516 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.046448 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.046448 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.046448 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.046448 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 71312.500000 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 71312.500000 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79527.777778 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79527.777778 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75661.764706 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 75661.764706 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75661.764706 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 75661.764706 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 7939500 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 0 # number of replacements +system.cpu.icache.tags.tagsinuse 76.387250 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 579 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 151 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 3.834437 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 76.387250 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.037298 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.037298 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 151 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 151 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.073730 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 1753 # Number of tag accesses +system.cpu.icache.tags.data_accesses 1753 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 7939500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 579 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 579 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 579 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 579 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 579 # number of overall hits +system.cpu.icache.overall_hits::total 579 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 222 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 222 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 222 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 222 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 222 # number of overall misses +system.cpu.icache.overall_misses::total 222 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 16076000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 16076000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 16076000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 16076000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 16076000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 16076000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 801 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 801 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 801 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 801 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 801 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 801 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.277154 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.277154 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.277154 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.277154 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.277154 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.277154 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 72414.414414 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 72414.414414 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 72414.414414 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 72414.414414 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 72414.414414 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 72414.414414 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 447 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 89.400000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 69 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 69 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 69 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 69 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 69 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 69 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 153 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 153 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 153 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 153 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 153 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 153 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11858500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 11858500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11858500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 11858500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11858500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 11858500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.191011 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.191011 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.191011 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.191011 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.191011 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.191011 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 77506.535948 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 77506.535948 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 77506.535948 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 77506.535948 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 77506.535948 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 77506.535948 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 7939500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.replacements 0 # number of replacements +system.cpu.l2cache.tags.tagsinuse 99.069725 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 182 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.010989 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::cpu.inst 75.716364 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 23.353361 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002311 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.000713 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.003023 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 182 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 182 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.005554 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 1678 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 1678 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 7939500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 1 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 1 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 1 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 1 # number of overall hits +system.cpu.l2cache.overall_hits::total 2 # number of overall hits +system.cpu.l2cache.ReadExReq_misses::cpu.data 18 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 18 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 152 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 152 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 15 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 15 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.inst 152 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 33 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 185 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 152 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 33 # number of overall misses +system.cpu.l2cache.overall_misses::total 185 # number of overall misses +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1404500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 1404500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 11620000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 11620000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 1106000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 1106000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 11620000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 2510500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 14130500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 11620000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 2510500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 14130500 # number of overall miss cycles +system.cpu.l2cache.ReadExReq_accesses::cpu.data 18 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 18 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 153 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 153 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 16 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 16 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 153 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 34 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 187 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 153 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 34 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 187 # number of overall (read+write) accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.993464 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.993464 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.937500 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.937500 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.993464 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.970588 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.989305 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993464 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.970588 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.989305 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78027.777778 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 78027.777778 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 76447.368421 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 76447.368421 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 73733.333333 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 73733.333333 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76447.368421 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76075.757576 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 76381.081081 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76447.368421 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76075.757576 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 76381.081081 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 18 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 18 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 152 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 152 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 15 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 15 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 152 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 33 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 185 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 152 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 33 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 185 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1224500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1224500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 10120000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 10120000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 966000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 966000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10120000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 2190500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 12310500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10120000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 2190500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 12310500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.993464 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.993464 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.937500 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.937500 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.993464 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.970588 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.989305 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993464 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.970588 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.989305 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68027.777778 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68027.777778 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66578.947368 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66578.947368 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 64400 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 64400 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66578.947368 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66378.787879 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 66543.243243 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66578.947368 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66378.787879 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 66543.243243 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 187 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 7939500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 166 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 18 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 18 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 153 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 16 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 304 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 67 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 371 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9664 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2112 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 11776 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 187 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.010695 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.103139 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 185 98.93% 98.93% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 2 1.07% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 187 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 93500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 226500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 2.9 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 49500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.6 # Layer utilization (%) +system.membus.snoop_filter.tot_requests 184 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 7939500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 164 # Transaction distribution +system.membus.trans_dist::ReadExReq 18 # Transaction distribution +system.membus.trans_dist::ReadExResp 18 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 166 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 366 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 366 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 11648 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 11648 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoopTraffic 0 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 184 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 184 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 184 # Request fanout histogram +system.membus.reqLayer0.occupancy 228500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 2.9 # Layer utilization (%) +system.membus.respLayer1.occupancy 948750 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 11.9 # Layer utilization (%) + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/riscv/linux/simple-atomic/config.ini b/tests/quick/se/00.hello/ref/riscv/linux/simple-atomic/config.ini new file mode 100644 index 000000000..76abe1457 --- /dev/null +++ b/tests/quick/se/00.hello/ref/riscv/linux/simple-atomic/config.ini @@ -0,0 +1,211 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain +boot_osflags=a +cache_line_size=64 +clk_domain=system.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +exit_on_work_items=false +init_param=0 +kernel= +kernel_addr_check=true +load_addr_mask=1099511627775 +load_offset=0 +mem_mode=atomic +mem_ranges= +memories=system.physmem +mmap_using_noreserve=false +multi_thread=false +num_work_ids=16 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +readfile= +symbolfile= +thermal_components= +thermal_model=Null +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=AtomicSimpleCPU +children=dtb interrupts isa itb tracer workload +branchPred=Null +checker=Null +clk_domain=system.cpu_clk_domain +cpu_id=0 +default_p_state=UNDEFINED +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +eventq_index=0 +fastmem=false +function_trace=false +function_trace_start=0 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +profile=0 +progress_interval=0 +simpoint_start_insts= +simulate_data_stalls=false +simulate_inst_stalls=false +socket_id=0 +switched_out=false +system=system +tracer=system.cpu.tracer +width=1 +workload=system.cpu.workload +dcache_port=system.membus.slave[2] +icache_port=system.membus.slave[1] + +[system.cpu.dtb] +type=RiscvTLB +eventq_index=0 +size=64 + +[system.cpu.interrupts] +type=RiscvInterrupts +eventq_index=0 + +[system.cpu.isa] +type=RiscvISA +eventq_index=0 + +[system.cpu.itb] +type=RiscvTLB +eventq_index=0 +size=64 + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=LiveProcess +cmd=hello +cwd= +drivers= +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable=/z/powerjg/gem5-upstream/tests/test-progs/hello/bin/riscv/linux/hello +gid=100 +input=cin +kvmInSE=false +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=0 +system=system +uid=100 +useArchPT=false + +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000000 + +[system.membus] +type=CoherentXBar +children=snoop_filter +clk_domain=system.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +forward_latency=4 +frontend_latency=3 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +point_of_coherency=true +power_model=Null +response_latency=2 +snoop_filter=system.membus.snoop_filter +snoop_response_latency=4 +system=system +use_default_range=false +width=16 +master=system.physmem.port +slave=system.system_port system.cpu.icache_port system.cpu.dcache_port + +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + +[system.physmem] +type=SimpleMemory +bandwidth=73.000000 +clk_domain=system.clk_domain +conf_table_reported=true +default_p_state=UNDEFINED +eventq_index=0 +in_addr_map=true +kvm_map=true +latency=30000 +latency_var=0 +null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +range=0:134217727:0:0:0:0 +port=system.membus.master[0] + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + diff --git a/tests/quick/se/00.hello/ref/riscv/linux/simple-atomic/config.json b/tests/quick/se/00.hello/ref/riscv/linux/simple-atomic/config.json new file mode 100644 index 000000000..663d5cd98 --- /dev/null +++ b/tests/quick/se/00.hello/ref/riscv/linux/simple-atomic/config.json @@ -0,0 +1,289 @@ +{ + "name": null, + "sim_quantum": 0, + "system": { + "kernel": "", + "mmap_using_noreserve": false, + "kernel_addr_check": true, + "membus": { + "point_of_coherency": true, + "system": "system", + "response_latency": 2, + "cxx_class": "CoherentXBar", + "forward_latency": 4, + "clk_domain": "system.clk_domain", + "width": 16, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "master": { + "peer": [ + "system.physmem.port" + ], + "role": "MASTER" + }, + "type": "CoherentXBar", + "frontend_latency": 3, + "slave": { + "peer": [ + "system.system_port", + "system.cpu.icache_port", + "system.cpu.dcache_port" + ], + "role": "SLAVE" + }, + "p_state_clk_gate_min": 1000, + "snoop_filter": { + "name": "snoop_filter", + "system": "system", + "max_capacity": 8388608, + "eventq_index": 0, + "cxx_class": "SnoopFilter", + "path": "system.membus.snoop_filter", + "type": "SnoopFilter", + "lookup_latency": 1 + }, + "power_model": null, + "path": "system.membus", + "snoop_response_latency": 4, + "name": "membus", + "p_state_clk_gate_bins": 20, + "use_default_range": false + }, + "symbolfile": "", + "readfile": "", + "thermal_model": null, + "cxx_class": "System", + "work_begin_cpu_id_exit": -1, + "load_offset": 0, + "work_begin_exit_count": 0, + "p_state_clk_gate_min": 1000, + "memories": [ + "system.physmem" + ], + "work_begin_ckpt_count": 0, + "clk_domain": { + "name": "clk_domain", + "clock": [ + 1000 + ], + "init_perf_level": 0, + "voltage_domain": "system.voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "mem_ranges": [], + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "dvfs_handler": { + "enable": false, + "name": "dvfs_handler", + "sys_clk_domain": "system.clk_domain", + "transition_latency": 100000000, + "eventq_index": 0, + "cxx_class": "DVFSHandler", + "domains": [], + "path": "system.dvfs_handler", + "type": "DVFSHandler" + }, + "work_end_exit_count": 0, + "type": "System", + "voltage_domain": { + "name": "voltage_domain", + "eventq_index": 0, + "voltage": [ + "1.0" + ], + "cxx_class": "VoltageDomain", + "path": "system.voltage_domain", + "type": "VoltageDomain" + }, + "cache_line_size": 64, + "boot_osflags": "a", + "system_port": { + "peer": "system.membus.slave[0]", + "role": "MASTER" + }, + "physmem": { + "range": "0:134217727:0:0:0:0", + "latency": 30000, + "name": "physmem", + "p_state_clk_gate_min": 1000, + "eventq_index": 0, + "p_state_clk_gate_bins": 20, + "default_p_state": "UNDEFINED", + "kvm_map": true, + "clk_domain": "system.clk_domain", + "power_model": null, + "latency_var": 0, + "bandwidth": "73.000000", + "conf_table_reported": true, + "cxx_class": "SimpleMemory", + "p_state_clk_gate_max": 1000000000000, + "path": "system.physmem", + "null": false, + "type": "SimpleMemory", + "port": { + "peer": "system.membus.master[0]", + "role": "SLAVE" + }, + "in_addr_map": true + }, + "power_model": null, + "work_cpus_ckpt_count": 0, + "thermal_components": [], + "path": "system", + "cpu_clk_domain": { + "name": "cpu_clk_domain", + "clock": [ + 500 + ], + "init_perf_level": 0, + "voltage_domain": "system.voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.cpu_clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "work_end_ckpt_count": 0, + "mem_mode": "atomic", + "name": "system", + "init_param": 0, + "p_state_clk_gate_bins": 20, + "load_addr_mask": 1099511627775, + "cpu": [ + { + "do_statistics_insts": true, + "numThreads": 1, + "itb": { + "name": "itb", + "eventq_index": 0, + "cxx_class": "RiscvISA::TLB", + "path": "system.cpu.itb", + "type": "RiscvTLB", + "size": 64 + }, + "simulate_data_stalls": false, + "function_trace": false, + "do_checkpoint_insts": true, + "cxx_class": "AtomicSimpleCPU", + "max_loads_all_threads": 0, + "system": "system", + "clk_domain": "system.cpu_clk_domain", + "function_trace_start": 0, + "cpu_id": 0, + "width": 1, + "checker": null, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "do_quiesce": true, + "type": "AtomicSimpleCPU", + "fastmem": false, + "profile": 0, + "icache_port": { + "peer": "system.membus.slave[1]", + "role": "MASTER" + }, + "p_state_clk_gate_bins": 20, + "p_state_clk_gate_min": 1000, + "interrupts": [ + { + "eventq_index": 0, + "path": "system.cpu.interrupts", + "type": "RiscvInterrupts", + "name": "interrupts", + "cxx_class": "RiscvISA::Interrupts" + } + ], + "dcache_port": { + "peer": "system.membus.slave[2]", + "role": "MASTER" + }, + "socket_id": 0, + "power_model": null, + "max_insts_all_threads": 0, + "path": "system.cpu", + "max_loads_any_thread": 0, + "switched_out": false, + "workload": [ + { + "uid": 100, + "pid": 100, + "kvmInSE": false, + "cxx_class": "LiveProcess", + "executable": "/z/powerjg/gem5-upstream/tests/test-progs/hello/bin/riscv/linux/hello", + "drivers": [], + "system": "system", + "gid": 100, + "eventq_index": 0, + "env": [], + "input": "cin", + "ppid": 99, + "type": "LiveProcess", + "cwd": "", + "simpoint": 0, + "euid": 100, + "path": "system.cpu.workload", + "max_stack_size": 67108864, + "name": "workload", + "cmd": [ + "hello" + ], + "errout": "cerr", + "useArchPT": false, + "egid": 100, + "output": "cout" + } + ], + "name": "cpu", + "dtb": { + "name": "dtb", + "eventq_index": 0, + "cxx_class": "RiscvISA::TLB", + "path": "system.cpu.dtb", + "type": "RiscvTLB", + "size": 64 + }, + "simpoint_start_insts": [], + "max_insts_any_thread": 0, + "simulate_inst_stalls": false, + "progress_interval": 0, + "branchPred": null, + "isa": [ + { + "eventq_index": 0, + "path": "system.cpu.isa", + "type": "RiscvISA", + "name": "isa", + "cxx_class": "RiscvISA::ISA" + } + ], + "tracer": { + "eventq_index": 0, + "path": "system.cpu.tracer", + "type": "ExeTracer", + "name": "tracer", + "cxx_class": "Trace::ExeTracer" + } + } + ], + "multi_thread": false, + "exit_on_work_items": false, + "work_item_id": -1, + "num_work_ids": 16 + }, + "time_sync_period": 100000000000, + "eventq_index": 0, + "time_sync_spin_threshold": 100000000, + "cxx_class": "Root", + "path": "root", + "time_sync_enable": false, + "type": "Root", + "full_system": false +}
\ No newline at end of file diff --git a/tests/quick/se/00.hello/ref/riscv/linux/simple-atomic/simerr b/tests/quick/se/00.hello/ref/riscv/linux/simple-atomic/simerr new file mode 100755 index 000000000..fd133b12b --- /dev/null +++ b/tests/quick/se/00.hello/ref/riscv/linux/simple-atomic/simerr @@ -0,0 +1,3 @@ +warn: Unknown operating system; assuming Linux. +warn: Sockets disabled, not accepting gdb connections +warn: ClockedObject: More than one power state change request encountered within the same simulation tick diff --git a/tests/quick/se/00.hello/ref/riscv/linux/simple-atomic/simout b/tests/quick/se/00.hello/ref/riscv/linux/simple-atomic/simout new file mode 100755 index 000000000..0253c62ea --- /dev/null +++ b/tests/quick/se/00.hello/ref/riscv/linux/simple-atomic/simout @@ -0,0 +1,15 @@ +Redirecting stdout to build/RISCV/tests/opt/quick/se/00.hello/riscv/linux/simple-atomic/simout +Redirecting stderr to build/RISCV/tests/opt/quick/se/00.hello/riscv/linux/simple-atomic/simerr +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled Nov 30 2016 14:33:35 +gem5 started Nov 30 2016 16:18:29 +gem5 executing on zizzer, pid 34058 +command line: /z/powerjg/gem5-upstream/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/00.hello/riscv/linux/simple-atomic -re /z/powerjg/gem5-upstream/tests/testing/../run.py quick/se/00.hello/riscv/linux/simple-atomic + +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. +Hello world! +Exiting @ tick 798000 because target called exit() diff --git a/tests/quick/se/00.hello/ref/riscv/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/riscv/linux/simple-atomic/stats.txt new file mode 100644 index 000000000..c14fe390a --- /dev/null +++ b/tests/quick/se/00.hello/ref/riscv/linux/simple-atomic/stats.txt @@ -0,0 +1,153 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.000001 # Number of seconds simulated +sim_ticks 798000 # Number of ticks simulated +final_tick 798000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 49942 # Simulator instruction rate (inst/s) +host_op_rate 49911 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 25081647 # Simulator tick rate (ticks/s) +host_mem_usage 221640 # Number of bytes of host memory used +host_seconds 0.03 # Real time elapsed on the host +sim_insts 1587 # Number of instructions simulated +sim_ops 1587 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 798000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 6388 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 1816 # Number of bytes read from this memory +system.physmem.bytes_read::total 8204 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 6388 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 6388 # Number of instructions bytes read from this memory +system.physmem.bytes_written::cpu.data 1750 # Number of bytes written to this memory +system.physmem.bytes_written::total 1750 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 1597 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 289 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1886 # Number of read requests responded to by this memory +system.physmem.num_writes::cpu.data 279 # Number of write requests responded to by this memory +system.physmem.num_writes::total 279 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 8005012531 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2275689223 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 10280701754 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 8005012531 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 8005012531 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 2192982456 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2192982456 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 8005012531 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4468671679 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 12473684211 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 798000 # Cumulative time (in ticks) in various power states +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 9 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 798000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 1597 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 1587 # Number of instructions committed +system.cpu.committedOps 1587 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 1588 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses +system.cpu.num_func_calls 142 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 231 # number of instructions that are conditional controls +system.cpu.num_int_insts 1588 # number of integer instructions +system.cpu.num_fp_insts 0 # number of float instructions +system.cpu.num_int_register_reads 2062 # number of times the integer registers were read +system.cpu.num_int_register_writes 1077 # number of times the integer registers were written +system.cpu.num_fp_register_reads 0 # number of times the floating registers were read +system.cpu.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu.num_mem_refs 569 # number of memory refs +system.cpu.num_load_insts 289 # Number of load instructions +system.cpu.num_store_insts 280 # Number of store instructions +system.cpu.num_idle_cycles 0 # Number of idle cycles +system.cpu.num_busy_cycles 1597 # Number of busy cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.Branches 373 # Number of branches fetched +system.cpu.op_class::No_OpClass 9 0.56% 0.56% # Class of executed instruction +system.cpu.op_class::IntAlu 1019 63.81% 64.37% # Class of executed instruction +system.cpu.op_class::IntMult 0 0.00% 64.37% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 64.37% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 64.37% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 64.37% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 64.37% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 64.37% # Class of executed instruction +system.cpu.op_class::FloatMultAcc 0 0.00% 64.37% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 64.37% # Class of executed instruction +system.cpu.op_class::FloatMisc 0 0.00% 64.37% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 64.37% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 64.37% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 64.37% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 64.37% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 64.37% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 64.37% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 64.37% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 64.37% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 64.37% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 64.37% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 64.37% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 64.37% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 64.37% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 64.37% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 64.37% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 64.37% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 64.37% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 64.37% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 64.37% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 64.37% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 64.37% # Class of executed instruction +system.cpu.op_class::MemRead 289 18.10% 82.47% # Class of executed instruction +system.cpu.op_class::MemWrite 280 17.53% 100.00% # Class of executed instruction +system.cpu.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 1597 # Class of executed instruction +system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 798000 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadReq 1886 # Transaction distribution +system.membus.trans_dist::ReadResp 1886 # Transaction distribution +system.membus.trans_dist::WriteReq 279 # Transaction distribution +system.membus.trans_dist::WriteResp 279 # Transaction distribution +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 3194 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 1136 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 4330 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 6388 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 3566 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 9954 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoopTraffic 0 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 2165 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 2165 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 2165 # Request fanout histogram + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/riscv/linux/simple-timing-ruby/config.ini b/tests/quick/se/00.hello/ref/riscv/linux/simple-timing-ruby/config.ini new file mode 100644 index 000000000..9d9106168 --- /dev/null +++ b/tests/quick/se/00.hello/ref/riscv/linux/simple-timing-ruby/config.ini @@ -0,0 +1,1265 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000 +time_sync_spin_threshold=100000 + +[system] +type=System +children=clk_domain cpu dvfs_handler mem_ctrls ruby sys_port_proxy voltage_domain +boot_osflags=a +cache_line_size=64 +clk_domain=system.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +exit_on_work_items=false +init_param=0 +kernel= +kernel_addr_check=true +load_addr_mask=1099511627775 +load_offset=0 +mem_mode=timing +mem_ranges=0:268435455:0:0:0:0 +memories=system.mem_ctrls +mmap_using_noreserve=false +multi_thread=false +num_work_ids=16 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null +readfile= +symbolfile= +thermal_components= +thermal_model=Null +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.sys_port_proxy.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=TimingSimpleCPU +children=clk_domain dtb interrupts isa itb tracer workload +branchPred=Null +checker=Null +clk_domain=system.cpu.clk_domain +cpu_id=0 +default_p_state=UNDEFINED +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +eventq_index=0 +function_trace=false +function_trace_start=0 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null +profile=0 +progress_interval=0 +simpoint_start_insts= +socket_id=0 +switched_out=false +system=system +tracer=system.cpu.tracer +workload=system.cpu.workload +dcache_port=system.ruby.l1_cntrl0.sequencer.slave[1] +icache_port=system.ruby.l1_cntrl0.sequencer.slave[0] + +[system.cpu.clk_domain] +type=SrcClockDomain +clock=1 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu.dtb] +type=RiscvTLB +eventq_index=0 +size=64 + +[system.cpu.interrupts] +type=RiscvInterrupts +eventq_index=0 + +[system.cpu.isa] +type=RiscvISA +eventq_index=0 + +[system.cpu.itb] +type=RiscvTLB +eventq_index=0 +size=64 + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=LiveProcess +cmd=hello +cwd= +drivers= +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable=/z/powerjg/gem5-upstream/tests/test-progs/hello/bin/riscv/linux/hello +gid=100 +input=cin +kvmInSE=false +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=0 +system=system +uid=100 +useArchPT=false + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000 + +[system.mem_ctrls] +type=DRAMCtrl +IDD0=0.055000 +IDD02=0.000000 +IDD2N=0.032000 +IDD2N2=0.000000 +IDD2P0=0.000000 +IDD2P02=0.000000 +IDD2P1=0.032000 +IDD2P12=0.000000 +IDD3N=0.038000 +IDD3N2=0.000000 +IDD3P0=0.000000 +IDD3P02=0.000000 +IDD3P1=0.038000 +IDD3P12=0.000000 +IDD4R=0.157000 +IDD4R2=0.000000 +IDD4W=0.125000 +IDD4W2=0.000000 +IDD5=0.235000 +IDD52=0.000000 +IDD6=0.020000 +IDD62=0.000000 +VDD=1.500000 +VDD2=0.000000 +activation_limit=4 +addr_mapping=RoRaBaCoCh +bank_groups_per_rank=0 +banks_per_rank=8 +burst_length=8 +channels=1 +clk_domain=system.clk_domain +conf_table_reported=true +default_p_state=UNDEFINED +device_bus_width=8 +device_rowbuffer_size=1024 +device_size=536870912 +devices_per_rank=8 +dll=true +eventq_index=0 +in_addr_map=true +kvm_map=true +max_accesses_per_row=16 +mem_sched_policy=frfcfs +min_writes_per_switch=16 +null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +page_policy=open_adaptive +power_model=Null +range=0:268435455:5:19:0:0 +ranks_per_channel=2 +read_buffer_size=32 +static_backend_latency=10 +static_frontend_latency=10 +tBURST=5 +tCCD_L=0 +tCK=1 +tCL=14 +tCS=3 +tRAS=35 +tRCD=14 +tREFI=7800 +tRFC=260 +tRP=14 +tRRD=6 +tRRD_L=0 +tRTP=8 +tRTW=3 +tWR=15 +tWTR=8 +tXAW=30 +tXP=6 +tXPDLL=0 +tXS=270 +tXSDLL=0 +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 +port=system.ruby.dir_cntrl0.memory + +[system.ruby] +type=RubySystem +children=clk_domain dir_cntrl0 l1_cntrl0 memctrl_clk_domain network +access_backing_store=false +all_instructions=false +block_size_bytes=64 +clk_domain=system.ruby.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +hot_lines=false +memory_size_bits=48 +num_of_sequencers=1 +number_of_virtual_networks=5 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +phys_mem=Null +power_model=Null +randomization=false + +[system.ruby.clk_domain] +type=SrcClockDomain +clock=1 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.ruby.dir_cntrl0] +type=Directory_Controller +children=directory dmaRequestToDir dmaResponseFromDir forwardFromDir requestToDir responseFromDir responseFromMemory +buffer_size=0 +clk_domain=system.ruby.clk_domain +cluster_id=0 +default_p_state=UNDEFINED +directory=system.ruby.dir_cntrl0.directory +directory_latency=12 +dmaRequestToDir=system.ruby.dir_cntrl0.dmaRequestToDir +dmaResponseFromDir=system.ruby.dir_cntrl0.dmaResponseFromDir +eventq_index=0 +forwardFromDir=system.ruby.dir_cntrl0.forwardFromDir +number_of_TBEs=256 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null +recycle_latency=10 +requestToDir=system.ruby.dir_cntrl0.requestToDir +responseFromDir=system.ruby.dir_cntrl0.responseFromDir +responseFromMemory=system.ruby.dir_cntrl0.responseFromMemory +ruby_system=system.ruby +system=system +to_memory_controller_latency=1 +transitions_per_cycle=4 +version=0 +memory=system.mem_ctrls.port + +[system.ruby.dir_cntrl0.directory] +type=RubyDirectoryMemory +eventq_index=0 +numa_high_bit=5 +size=268435456 +version=0 + +[system.ruby.dir_cntrl0.dmaRequestToDir] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +slave=system.ruby.network.master[3] + +[system.ruby.dir_cntrl0.dmaResponseFromDir] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +master=system.ruby.network.slave[3] + +[system.ruby.dir_cntrl0.forwardFromDir] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=false +randomization=false +master=system.ruby.network.slave[4] + +[system.ruby.dir_cntrl0.requestToDir] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +slave=system.ruby.network.master[2] + +[system.ruby.dir_cntrl0.responseFromDir] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=false +randomization=false +master=system.ruby.network.slave[2] + +[system.ruby.dir_cntrl0.responseFromMemory] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=false +randomization=false + +[system.ruby.l1_cntrl0] +type=L1Cache_Controller +children=cacheMemory forwardToCache mandatoryQueue requestFromCache responseFromCache responseToCache sequencer +buffer_size=0 +cacheMemory=system.ruby.l1_cntrl0.cacheMemory +cache_response_latency=12 +clk_domain=system.cpu.clk_domain +cluster_id=0 +default_p_state=UNDEFINED +eventq_index=0 +forwardToCache=system.ruby.l1_cntrl0.forwardToCache +issue_latency=2 +mandatoryQueue=system.ruby.l1_cntrl0.mandatoryQueue +number_of_TBEs=256 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null +recycle_latency=10 +requestFromCache=system.ruby.l1_cntrl0.requestFromCache +responseFromCache=system.ruby.l1_cntrl0.responseFromCache +responseToCache=system.ruby.l1_cntrl0.responseToCache +ruby_system=system.ruby +send_evictions=false +sequencer=system.ruby.l1_cntrl0.sequencer +system=system +transitions_per_cycle=4 +version=0 + +[system.ruby.l1_cntrl0.cacheMemory] +type=RubyCache +children=replacement_policy +assoc=2 +block_size=0 +dataAccessLatency=1 +dataArrayBanks=1 +eventq_index=0 +is_icache=false +replacement_policy=system.ruby.l1_cntrl0.cacheMemory.replacement_policy +resourceStalls=false +ruby_system=system.ruby +size=256 +start_index_bit=6 +tagAccessLatency=1 +tagArrayBanks=1 + +[system.ruby.l1_cntrl0.cacheMemory.replacement_policy] +type=PseudoLRUReplacementPolicy +assoc=2 +block_size=64 +eventq_index=0 +size=256 + +[system.ruby.l1_cntrl0.forwardToCache] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +slave=system.ruby.network.master[0] + +[system.ruby.l1_cntrl0.mandatoryQueue] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=false +randomization=false + +[system.ruby.l1_cntrl0.requestFromCache] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +master=system.ruby.network.slave[0] + +[system.ruby.l1_cntrl0.responseFromCache] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +master=system.ruby.network.slave[1] + +[system.ruby.l1_cntrl0.responseToCache] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +slave=system.ruby.network.master[1] + +[system.ruby.l1_cntrl0.sequencer] +type=RubySequencer +clk_domain=system.cpu.clk_domain +coreid=99 +dcache=system.ruby.l1_cntrl0.cacheMemory +dcache_hit_latency=1 +deadlock_threshold=500000 +default_p_state=UNDEFINED +eventq_index=0 +garnet_standalone=false +icache=system.ruby.l1_cntrl0.cacheMemory +icache_hit_latency=1 +is_cpu_sequencer=true +max_outstanding_requests=16 +no_retry_on_stall=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null +ruby_system=system.ruby +support_data_reqs=true +support_inst_reqs=true +system=system +using_ruby_tester=false +version=0 +slave=system.cpu.icache_port system.cpu.dcache_port + +[system.ruby.memctrl_clk_domain] +type=DerivedClockDomain +clk_divider=3 +clk_domain=system.ruby.clk_domain +eventq_index=0 + +[system.ruby.network] +type=SimpleNetwork +children=ext_links0 ext_links1 int_link_buffers00 int_link_buffers01 int_link_buffers02 int_link_buffers03 int_link_buffers04 int_link_buffers05 int_link_buffers06 int_link_buffers07 int_link_buffers08 int_link_buffers09 int_link_buffers10 int_link_buffers11 int_link_buffers12 int_link_buffers13 int_link_buffers14 int_link_buffers15 int_link_buffers16 int_link_buffers17 int_link_buffers18 int_link_buffers19 int_link_buffers20 int_link_buffers21 int_link_buffers22 int_link_buffers23 int_link_buffers24 int_link_buffers25 int_link_buffers26 int_link_buffers27 int_link_buffers28 int_link_buffers29 int_link_buffers30 int_link_buffers31 int_link_buffers32 int_link_buffers33 int_link_buffers34 int_link_buffers35 int_link_buffers36 int_link_buffers37 int_link_buffers38 int_link_buffers39 int_links0 int_links1 int_links2 int_links3 routers0 routers1 routers2 +adaptive_routing=false +buffer_size=0 +clk_domain=system.ruby.clk_domain +control_msg_size=8 +default_p_state=UNDEFINED +endpoint_bandwidth=1000 +eventq_index=0 +ext_links=system.ruby.network.ext_links0 system.ruby.network.ext_links1 +int_link_buffers=system.ruby.network.int_link_buffers00 system.ruby.network.int_link_buffers01 system.ruby.network.int_link_buffers02 system.ruby.network.int_link_buffers03 system.ruby.network.int_link_buffers04 system.ruby.network.int_link_buffers05 system.ruby.network.int_link_buffers06 system.ruby.network.int_link_buffers07 system.ruby.network.int_link_buffers08 system.ruby.network.int_link_buffers09 system.ruby.network.int_link_buffers10 system.ruby.network.int_link_buffers11 system.ruby.network.int_link_buffers12 system.ruby.network.int_link_buffers13 system.ruby.network.int_link_buffers14 system.ruby.network.int_link_buffers15 system.ruby.network.int_link_buffers16 system.ruby.network.int_link_buffers17 system.ruby.network.int_link_buffers18 system.ruby.network.int_link_buffers19 system.ruby.network.int_link_buffers20 system.ruby.network.int_link_buffers21 system.ruby.network.int_link_buffers22 system.ruby.network.int_link_buffers23 system.ruby.network.int_link_buffers24 system.ruby.network.int_link_buffers25 system.ruby.network.int_link_buffers26 system.ruby.network.int_link_buffers27 system.ruby.network.int_link_buffers28 system.ruby.network.int_link_buffers29 system.ruby.network.int_link_buffers30 system.ruby.network.int_link_buffers31 system.ruby.network.int_link_buffers32 system.ruby.network.int_link_buffers33 system.ruby.network.int_link_buffers34 system.ruby.network.int_link_buffers35 system.ruby.network.int_link_buffers36 system.ruby.network.int_link_buffers37 system.ruby.network.int_link_buffers38 system.ruby.network.int_link_buffers39 +int_links=system.ruby.network.int_links0 system.ruby.network.int_links1 system.ruby.network.int_links2 system.ruby.network.int_links3 +netifs= +number_of_virtual_networks=5 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null +routers=system.ruby.network.routers0 system.ruby.network.routers1 system.ruby.network.routers2 +ruby_system=system.ruby +topology=Crossbar +master=system.ruby.l1_cntrl0.forwardToCache.slave system.ruby.l1_cntrl0.responseToCache.slave system.ruby.dir_cntrl0.requestToDir.slave system.ruby.dir_cntrl0.dmaRequestToDir.slave +slave=system.ruby.l1_cntrl0.requestFromCache.master system.ruby.l1_cntrl0.responseFromCache.master system.ruby.dir_cntrl0.responseFromDir.master system.ruby.dir_cntrl0.dmaResponseFromDir.master system.ruby.dir_cntrl0.forwardFromDir.master + +[system.ruby.network.ext_links0] +type=SimpleExtLink +bandwidth_factor=16 +eventq_index=0 +ext_node=system.ruby.l1_cntrl0 +int_node=system.ruby.network.routers0 +latency=1 +link_id=0 +weight=1 + +[system.ruby.network.ext_links1] +type=SimpleExtLink +bandwidth_factor=16 +eventq_index=0 +ext_node=system.ruby.dir_cntrl0 +int_node=system.ruby.network.routers1 +latency=1 +link_id=1 +weight=1 + +[system.ruby.network.int_link_buffers00] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers01] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers02] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers03] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers04] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers05] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers06] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers07] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers08] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers09] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers10] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers11] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers12] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers13] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers14] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers15] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers16] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers17] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers18] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers19] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers20] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers21] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers22] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers23] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers24] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers25] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers26] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers27] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers28] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers29] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers30] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers31] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers32] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers33] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers34] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers35] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers36] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers37] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers38] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers39] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_links0] +type=SimpleIntLink +bandwidth_factor=16 +dst_inport= +dst_node=system.ruby.network.routers2 +eventq_index=0 +latency=1 +link_id=2 +src_node=system.ruby.network.routers0 +src_outport= +weight=1 + +[system.ruby.network.int_links1] +type=SimpleIntLink +bandwidth_factor=16 +dst_inport= +dst_node=system.ruby.network.routers2 +eventq_index=0 +latency=1 +link_id=3 +src_node=system.ruby.network.routers1 +src_outport= +weight=1 + +[system.ruby.network.int_links2] +type=SimpleIntLink +bandwidth_factor=16 +dst_inport= +dst_node=system.ruby.network.routers0 +eventq_index=0 +latency=1 +link_id=4 +src_node=system.ruby.network.routers2 +src_outport= +weight=1 + +[system.ruby.network.int_links3] +type=SimpleIntLink +bandwidth_factor=16 +dst_inport= +dst_node=system.ruby.network.routers1 +eventq_index=0 +latency=1 +link_id=5 +src_node=system.ruby.network.routers2 +src_outport= +weight=1 + +[system.ruby.network.routers0] +type=Switch +children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14 +clk_domain=system.ruby.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +port_buffers=system.ruby.network.routers0.port_buffers00 system.ruby.network.routers0.port_buffers01 system.ruby.network.routers0.port_buffers02 system.ruby.network.routers0.port_buffers03 system.ruby.network.routers0.port_buffers04 system.ruby.network.routers0.port_buffers05 system.ruby.network.routers0.port_buffers06 system.ruby.network.routers0.port_buffers07 system.ruby.network.routers0.port_buffers08 system.ruby.network.routers0.port_buffers09 system.ruby.network.routers0.port_buffers10 system.ruby.network.routers0.port_buffers11 system.ruby.network.routers0.port_buffers12 system.ruby.network.routers0.port_buffers13 system.ruby.network.routers0.port_buffers14 +power_model=Null +router_id=0 +virt_nets=5 + +[system.ruby.network.routers0.port_buffers00] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers0.port_buffers01] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers0.port_buffers02] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers0.port_buffers03] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers0.port_buffers04] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers0.port_buffers05] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers0.port_buffers06] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers0.port_buffers07] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers0.port_buffers08] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers0.port_buffers09] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers0.port_buffers10] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers0.port_buffers11] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers0.port_buffers12] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers0.port_buffers13] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers0.port_buffers14] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers1] +type=Switch +children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14 +clk_domain=system.ruby.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +port_buffers=system.ruby.network.routers1.port_buffers00 system.ruby.network.routers1.port_buffers01 system.ruby.network.routers1.port_buffers02 system.ruby.network.routers1.port_buffers03 system.ruby.network.routers1.port_buffers04 system.ruby.network.routers1.port_buffers05 system.ruby.network.routers1.port_buffers06 system.ruby.network.routers1.port_buffers07 system.ruby.network.routers1.port_buffers08 system.ruby.network.routers1.port_buffers09 system.ruby.network.routers1.port_buffers10 system.ruby.network.routers1.port_buffers11 system.ruby.network.routers1.port_buffers12 system.ruby.network.routers1.port_buffers13 system.ruby.network.routers1.port_buffers14 +power_model=Null +router_id=1 +virt_nets=5 + +[system.ruby.network.routers1.port_buffers00] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers1.port_buffers01] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers1.port_buffers02] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers1.port_buffers03] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers1.port_buffers04] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers1.port_buffers05] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers1.port_buffers06] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers1.port_buffers07] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers1.port_buffers08] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers1.port_buffers09] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers1.port_buffers10] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers1.port_buffers11] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers1.port_buffers12] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers1.port_buffers13] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers1.port_buffers14] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2] +type=Switch +children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14 port_buffers15 port_buffers16 port_buffers17 port_buffers18 port_buffers19 +clk_domain=system.ruby.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +port_buffers=system.ruby.network.routers2.port_buffers00 system.ruby.network.routers2.port_buffers01 system.ruby.network.routers2.port_buffers02 system.ruby.network.routers2.port_buffers03 system.ruby.network.routers2.port_buffers04 system.ruby.network.routers2.port_buffers05 system.ruby.network.routers2.port_buffers06 system.ruby.network.routers2.port_buffers07 system.ruby.network.routers2.port_buffers08 system.ruby.network.routers2.port_buffers09 system.ruby.network.routers2.port_buffers10 system.ruby.network.routers2.port_buffers11 system.ruby.network.routers2.port_buffers12 system.ruby.network.routers2.port_buffers13 system.ruby.network.routers2.port_buffers14 system.ruby.network.routers2.port_buffers15 system.ruby.network.routers2.port_buffers16 system.ruby.network.routers2.port_buffers17 system.ruby.network.routers2.port_buffers18 system.ruby.network.routers2.port_buffers19 +power_model=Null +router_id=2 +virt_nets=5 + +[system.ruby.network.routers2.port_buffers00] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers01] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers02] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers03] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers04] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers05] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers06] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers07] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers08] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers09] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers10] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers11] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers12] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers13] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers14] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers15] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers16] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers17] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers18] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers19] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.sys_port_proxy] +type=RubyPortProxy +clk_domain=system.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +is_cpu_sequencer=true +no_retry_on_stall=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null +ruby_system=system.ruby +support_data_reqs=true +support_inst_reqs=true +system=system +using_ruby_tester=false +version=0 +slave=system.system_port + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + diff --git a/tests/quick/se/00.hello/ref/riscv/linux/simple-timing-ruby/config.json b/tests/quick/se/00.hello/ref/riscv/linux/simple-timing-ruby/config.json new file mode 100644 index 000000000..331c89064 --- /dev/null +++ b/tests/quick/se/00.hello/ref/riscv/linux/simple-timing-ruby/config.json @@ -0,0 +1,1734 @@ +{ + "name": null, + "sim_quantum": 0, + "system": { + "kernel": "", + "mmap_using_noreserve": false, + "kernel_addr_check": true, + "symbolfile": "", + "readfile": "", + "thermal_model": null, + "cxx_class": "System", + "work_begin_cpu_id_exit": -1, + "load_offset": 0, + "work_begin_exit_count": 0, + "p_state_clk_gate_min": 1, + "memories": [ + "system.mem_ctrls" + ], + "work_begin_ckpt_count": 0, + "clk_domain": { + "name": "clk_domain", + "clock": [ + 1 + ], + "init_perf_level": 0, + "voltage_domain": "system.voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "mem_ranges": [ + "0:268435455:0:0:0:0" + ], + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000, + "dvfs_handler": { + "enable": false, + "name": "dvfs_handler", + "sys_clk_domain": "system.clk_domain", + "transition_latency": 100000, + "eventq_index": 0, + "cxx_class": "DVFSHandler", + "domains": [], + "path": "system.dvfs_handler", + "type": "DVFSHandler" + }, + "work_end_exit_count": 0, + "type": "System", + "voltage_domain": { + "name": "voltage_domain", + "eventq_index": 0, + "voltage": [ + "1.0" + ], + "cxx_class": "VoltageDomain", + "path": "system.voltage_domain", + "type": "VoltageDomain" + }, + "cache_line_size": 64, + "boot_osflags": "a", + "system_port": { + "peer": "system.sys_port_proxy.slave[0]", + "role": "MASTER" + }, + "sys_port_proxy": { + "system": "system", + "support_inst_reqs": true, + "slave": { + "peer": [ + "system.system_port" + ], + "role": "SLAVE" + }, + "name": "sys_port_proxy", + "p_state_clk_gate_min": 1, + "no_retry_on_stall": false, + "p_state_clk_gate_bins": 20, + "support_data_reqs": true, + "cxx_class": "RubyPortProxy", + "clk_domain": "system.clk_domain", + "power_model": null, + "is_cpu_sequencer": true, + "version": 0, + "eventq_index": 0, + "using_ruby_tester": false, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000, + "path": "system.sys_port_proxy", + "type": "RubyPortProxy", + "ruby_system": "system.ruby" + }, + "power_model": null, + "work_cpus_ckpt_count": 0, + "thermal_components": [], + "path": "system", + "ruby": { + "all_instructions": false, + "memory_size_bits": 48, + "cxx_class": "RubySystem", + "l1_cntrl0": { + "requestFromCache": { + "ordered": true, + "name": "requestFromCache", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "master": { + "peer": "system.ruby.network.slave[0]", + "role": "MASTER" + }, + "buffer_size": 0, + "path": "system.ruby.l1_cntrl0.requestFromCache", + "type": "MessageBuffer" + }, + "cxx_class": "L1Cache_Controller", + "forwardToCache": { + "ordered": true, + "name": "forwardToCache", + "cxx_class": "MessageBuffer", + "slave": { + "peer": "system.ruby.network.master[0]", + "role": "SLAVE" + }, + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.l1_cntrl0.forwardToCache", + "type": "MessageBuffer" + }, + "system": "system", + "cluster_id": 0, + "sequencer": { + "no_retry_on_stall": false, + "deadlock_threshold": 500000, + "using_ruby_tester": false, + "system": "system", + "dcache": "system.ruby.l1_cntrl0.cacheMemory", + "cxx_class": "Sequencer", + "garnet_standalone": false, + "clk_domain": "system.cpu.clk_domain", + "icache_hit_latency": 1, + "version": 0, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000, + "type": "RubySequencer", + "icache": "system.ruby.l1_cntrl0.cacheMemory", + "slave": { + "peer": [ + "system.cpu.icache_port", + "system.cpu.dcache_port" + ], + "role": "SLAVE" + }, + "p_state_clk_gate_min": 1, + "power_model": null, + "coreid": 99, + "path": "system.ruby.l1_cntrl0.sequencer", + "ruby_system": "system.ruby", + "support_inst_reqs": true, + "name": "sequencer", + "max_outstanding_requests": 16, + "p_state_clk_gate_bins": 20, + "dcache_hit_latency": 1, + "support_data_reqs": true, + "is_cpu_sequencer": true + }, + "type": "L1Cache_Controller", + "issue_latency": 2, + "recycle_latency": 10, + "clk_domain": "system.cpu.clk_domain", + "version": 0, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000, + "number_of_TBEs": 256, + "p_state_clk_gate_min": 1, + "responseToCache": { + "ordered": true, + "name": "responseToCache", + "cxx_class": "MessageBuffer", + "slave": { + "peer": "system.ruby.network.master[1]", + "role": "SLAVE" + }, + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.l1_cntrl0.responseToCache", + "type": "MessageBuffer" + }, + "transitions_per_cycle": 4, + "responseFromCache": { + "ordered": true, + "name": "responseFromCache", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "master": { + "peer": "system.ruby.network.slave[1]", + "role": "MASTER" + }, + "buffer_size": 0, + "path": "system.ruby.l1_cntrl0.responseFromCache", + "type": "MessageBuffer" + }, + "power_model": null, + "cache_response_latency": 12, + "buffer_size": 0, + "send_evictions": false, + "cacheMemory": { + "size": 256, + "resourceStalls": false, + "is_icache": false, + "name": "cacheMemory", + "eventq_index": 0, + "dataAccessLatency": 1, + "tagArrayBanks": 1, + "tagAccessLatency": 1, + "replacement_policy": { + "name": "replacement_policy", + "eventq_index": 0, + "assoc": 2, + "cxx_class": "PseudoLRUPolicy", + "path": "system.ruby.l1_cntrl0.cacheMemory.replacement_policy", + "block_size": 64, + "type": "PseudoLRUReplacementPolicy", + "size": 256 + }, + "assoc": 2, + "start_index_bit": 6, + "cxx_class": "CacheMemory", + "path": "system.ruby.l1_cntrl0.cacheMemory", + "block_size": 0, + "type": "RubyCache", + "dataArrayBanks": 1, + "ruby_system": "system.ruby" + }, + "ruby_system": "system.ruby", + "name": "l1_cntrl0", + "p_state_clk_gate_bins": 20, + "mandatoryQueue": { + "ordered": false, + "name": "mandatoryQueue", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.l1_cntrl0.mandatoryQueue", + "type": "MessageBuffer" + }, + "path": "system.ruby.l1_cntrl0" + }, + "network": { + "int_link_buffers": [ + { + "ordered": true, + "name": "int_link_buffers00", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers00", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers01", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers01", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers02", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers02", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers03", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers03", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers04", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers04", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers05", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers05", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers06", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers06", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers07", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers07", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers08", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers08", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers09", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers09", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers10", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers10", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers11", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers11", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers12", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers12", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers13", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers13", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers14", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers14", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers15", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers15", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers16", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers16", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers17", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers17", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers18", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers18", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers19", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers19", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers20", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers20", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers21", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers21", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers22", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers22", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers23", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers23", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers24", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers24", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers25", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers25", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers26", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers26", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers27", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers27", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers28", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers28", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers29", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers29", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers30", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers30", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers31", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers31", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers32", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers32", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers33", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers33", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers34", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers34", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers35", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers35", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers36", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers36", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers37", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers37", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers38", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers38", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers39", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers39", + "type": "MessageBuffer" + } + ], + "cxx_class": "SimpleNetwork", + "clk_domain": "system.ruby.clk_domain", + "adaptive_routing": false, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000, + "master": { + "peer": [ + "system.ruby.l1_cntrl0.forwardToCache.slave", + "system.ruby.l1_cntrl0.responseToCache.slave", + "system.ruby.dir_cntrl0.requestToDir.slave", + "system.ruby.dir_cntrl0.dmaRequestToDir.slave" + ], + "role": "MASTER" + }, + "topology": "Crossbar", + "type": "SimpleNetwork", + "slave": { + "peer": [ + "system.ruby.l1_cntrl0.requestFromCache.master", + "system.ruby.l1_cntrl0.responseFromCache.master", + "system.ruby.dir_cntrl0.responseFromDir.master", + "system.ruby.dir_cntrl0.dmaResponseFromDir.master", + "system.ruby.dir_cntrl0.forwardFromDir.master" + ], + "role": "SLAVE" + }, + "p_state_clk_gate_min": 1, + "int_links": [ + { + "latency": 1, + "name": "int_links0", + "weight": 1, + "src_node": "system.ruby.network.routers0", + "dst_inport": "", + "link_id": 2, + "dst_node": "system.ruby.network.routers2", + "eventq_index": 0, + "src_outport": "", + "cxx_class": "SimpleIntLink", + "path": "system.ruby.network.int_links0", + "type": "SimpleIntLink", + "bandwidth_factor": 16 + }, + { + "latency": 1, + "name": "int_links1", + "weight": 1, + "src_node": "system.ruby.network.routers1", + "dst_inport": "", + "link_id": 3, + "dst_node": "system.ruby.network.routers2", + "eventq_index": 0, + "src_outport": "", + "cxx_class": "SimpleIntLink", + "path": "system.ruby.network.int_links1", + "type": "SimpleIntLink", + "bandwidth_factor": 16 + }, + { + "latency": 1, + "name": "int_links2", + "weight": 1, + "src_node": "system.ruby.network.routers2", + "dst_inport": "", + "link_id": 4, + "dst_node": "system.ruby.network.routers0", + "eventq_index": 0, + "src_outport": "", + "cxx_class": "SimpleIntLink", + "path": "system.ruby.network.int_links2", + "type": "SimpleIntLink", + "bandwidth_factor": 16 + }, + { + "latency": 1, + "name": "int_links3", + "weight": 1, + "src_node": "system.ruby.network.routers2", + "dst_inport": "", + "link_id": 5, + "dst_node": "system.ruby.network.routers1", + "eventq_index": 0, + "src_outport": "", + "cxx_class": "SimpleIntLink", + "path": "system.ruby.network.int_links3", + "type": "SimpleIntLink", + "bandwidth_factor": 16 + } + ], + "routers": [ + { + "router_id": 0, + "latency": 1, + "name": "routers0", + "p_state_clk_gate_min": 1, + "virt_nets": 5, + "p_state_clk_gate_bins": 20, + "cxx_class": "Switch", + "clk_domain": "system.ruby.clk_domain", + "power_model": null, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000, + "path": "system.ruby.network.routers0", + "type": "Switch", + "port_buffers": [ + { + "ordered": true, + "name": "port_buffers00", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers0.port_buffers00", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers01", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers0.port_buffers01", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers02", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers0.port_buffers02", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers03", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers0.port_buffers03", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers04", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers0.port_buffers04", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers05", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers0.port_buffers05", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers06", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers0.port_buffers06", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers07", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers0.port_buffers07", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers08", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers0.port_buffers08", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers09", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers0.port_buffers09", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers10", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers0.port_buffers10", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers11", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers0.port_buffers11", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers12", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers0.port_buffers12", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers13", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers0.port_buffers13", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers14", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers0.port_buffers14", + "type": "MessageBuffer" + } + ] + }, + { + "router_id": 1, + "latency": 1, + "name": "routers1", + "p_state_clk_gate_min": 1, + "virt_nets": 5, + "p_state_clk_gate_bins": 20, + "cxx_class": "Switch", + "clk_domain": "system.ruby.clk_domain", + "power_model": null, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000, + "path": "system.ruby.network.routers1", + "type": "Switch", + "port_buffers": [ + { + "ordered": true, + "name": "port_buffers00", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers1.port_buffers00", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers01", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers1.port_buffers01", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers02", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers1.port_buffers02", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers03", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers1.port_buffers03", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers04", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers1.port_buffers04", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers05", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers1.port_buffers05", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers06", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers1.port_buffers06", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers07", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers1.port_buffers07", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers08", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers1.port_buffers08", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers09", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers1.port_buffers09", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers10", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers1.port_buffers10", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers11", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers1.port_buffers11", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers12", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers1.port_buffers12", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers13", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers1.port_buffers13", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers14", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers1.port_buffers14", + "type": "MessageBuffer" + } + ] + }, + { + "router_id": 2, + "latency": 1, + "name": "routers2", + "p_state_clk_gate_min": 1, + "virt_nets": 5, + "p_state_clk_gate_bins": 20, + "cxx_class": "Switch", + "clk_domain": "system.ruby.clk_domain", + "power_model": null, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000, + "path": "system.ruby.network.routers2", + "type": "Switch", + "port_buffers": [ + { + "ordered": true, + "name": "port_buffers00", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers2.port_buffers00", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers01", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers2.port_buffers01", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers02", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers2.port_buffers02", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers03", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers2.port_buffers03", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers04", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers2.port_buffers04", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers05", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers2.port_buffers05", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers06", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers2.port_buffers06", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers07", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers2.port_buffers07", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers08", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers2.port_buffers08", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers09", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers2.port_buffers09", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers10", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers2.port_buffers10", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers11", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers2.port_buffers11", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers12", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers2.port_buffers12", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers13", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers2.port_buffers13", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers14", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers2.port_buffers14", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers15", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers2.port_buffers15", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers16", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers2.port_buffers16", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers17", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers2.port_buffers17", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers18", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers2.port_buffers18", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers19", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers2.port_buffers19", + "type": "MessageBuffer" + } + ] + } + ], + "power_model": null, + "netifs": [], + "control_msg_size": 8, + "buffer_size": 0, + "endpoint_bandwidth": 1000, + "ruby_system": "system.ruby", + "name": "network", + "p_state_clk_gate_bins": 20, + "ext_links": [ + { + "latency": 1, + "name": "ext_links0", + "weight": 1, + "ext_node": "system.ruby.l1_cntrl0", + "link_id": 0, + "eventq_index": 0, + "cxx_class": "SimpleExtLink", + "path": "system.ruby.network.ext_links0", + "int_node": "system.ruby.network.routers0", + "type": "SimpleExtLink", + "bandwidth_factor": 16 + }, + { + "latency": 1, + "name": "ext_links1", + "weight": 1, + "ext_node": "system.ruby.dir_cntrl0", + "link_id": 1, + "eventq_index": 0, + "cxx_class": "SimpleExtLink", + "path": "system.ruby.network.ext_links1", + "int_node": "system.ruby.network.routers1", + "type": "SimpleExtLink", + "bandwidth_factor": 16 + } + ], + "number_of_virtual_networks": 5, + "path": "system.ruby.network" + }, + "clk_domain": { + "name": "clk_domain", + "clock": [ + 1 + ], + "init_perf_level": 0, + "voltage_domain": "system.voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.ruby.clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "randomization": false, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000, + "phys_mem": null, + "type": "RubySystem", + "p_state_clk_gate_min": 1, + "hot_lines": false, + "power_model": null, + "path": "system.ruby", + "memctrl_clk_domain": { + "name": "memctrl_clk_domain", + "clk_domain": "system.ruby.clk_domain", + "eventq_index": 0, + "cxx_class": "DerivedClockDomain", + "path": "system.ruby.memctrl_clk_domain", + "type": "DerivedClockDomain", + "clk_divider": 3 + }, + "name": "ruby", + "p_state_clk_gate_bins": 20, + "block_size_bytes": 64, + "access_backing_store": false, + "number_of_virtual_networks": 5, + "num_of_sequencers": 1, + "dir_cntrl0": { + "system": "system", + "cluster_id": 0, + "responseFromMemory": { + "ordered": false, + "name": "responseFromMemory", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.dir_cntrl0.responseFromMemory", + "type": "MessageBuffer" + }, + "cxx_class": "Directory_Controller", + "forwardFromDir": { + "ordered": false, + "name": "forwardFromDir", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "master": { + "peer": "system.ruby.network.slave[4]", + "role": "MASTER" + }, + "buffer_size": 0, + "path": "system.ruby.dir_cntrl0.forwardFromDir", + "type": "MessageBuffer" + }, + "dmaRequestToDir": { + "ordered": true, + "name": "dmaRequestToDir", + "cxx_class": "MessageBuffer", + "slave": { + "peer": "system.ruby.network.master[3]", + "role": "SLAVE" + }, + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.dir_cntrl0.dmaRequestToDir", + "type": "MessageBuffer" + }, + "type": "Directory_Controller", + "recycle_latency": 10, + "clk_domain": "system.ruby.clk_domain", + "version": 0, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000, + "directory_latency": 12, + "number_of_TBEs": 256, + "to_memory_controller_latency": 1, + "p_state_clk_gate_min": 1, + "responseFromDir": { + "ordered": false, + "name": "responseFromDir", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "master": { + "peer": "system.ruby.network.slave[2]", + "role": "MASTER" + }, + "buffer_size": 0, + "path": "system.ruby.dir_cntrl0.responseFromDir", + "type": "MessageBuffer" + }, + "transitions_per_cycle": 4, + "memory": { + "peer": "system.mem_ctrls.port", + "role": "MASTER" + }, + "power_model": null, + "buffer_size": 0, + "ruby_system": "system.ruby", + "requestToDir": { + "ordered": true, + "name": "requestToDir", + "cxx_class": "MessageBuffer", + "slave": { + "peer": "system.ruby.network.master[2]", + "role": "SLAVE" + }, + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.dir_cntrl0.requestToDir", + "type": "MessageBuffer" + }, + "dmaResponseFromDir": { + "ordered": true, + "name": "dmaResponseFromDir", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "master": { + "peer": "system.ruby.network.slave[3]", + "role": "MASTER" + }, + "buffer_size": 0, + "path": "system.ruby.dir_cntrl0.dmaResponseFromDir", + "type": "MessageBuffer" + }, + "name": "dir_cntrl0", + "p_state_clk_gate_bins": 20, + "directory": { + "name": "directory", + "version": 0, + "eventq_index": 0, + "cxx_class": "DirectoryMemory", + "path": "system.ruby.dir_cntrl0.directory", + "type": "RubyDirectoryMemory", + "numa_high_bit": 5, + "size": 268435456 + }, + "path": "system.ruby.dir_cntrl0" + } + }, + "work_end_ckpt_count": 0, + "mem_mode": "timing", + "name": "system", + "init_param": 0, + "p_state_clk_gate_bins": 20, + "load_addr_mask": 1099511627775, + "cpu": { + "do_statistics_insts": true, + "numThreads": 1, + "itb": { + "name": "itb", + "eventq_index": 0, + "cxx_class": "RiscvISA::TLB", + "path": "system.cpu.itb", + "type": "RiscvTLB", + "size": 64 + }, + "system": "system", + "function_trace": false, + "do_checkpoint_insts": true, + "cxx_class": "TimingSimpleCPU", + "max_loads_all_threads": 0, + "clk_domain": { + "name": "clk_domain", + "clock": [ + 1 + ], + "init_perf_level": 0, + "voltage_domain": "system.voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.cpu.clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "function_trace_start": 0, + "cpu_id": 0, + "checker": null, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000, + "do_quiesce": true, + "type": "TimingSimpleCPU", + "profile": 0, + "icache_port": { + "peer": "system.ruby.l1_cntrl0.sequencer.slave[0]", + "role": "MASTER" + }, + "p_state_clk_gate_bins": 20, + "p_state_clk_gate_min": 1, + "interrupts": [ + { + "eventq_index": 0, + "path": "system.cpu.interrupts", + "type": "RiscvInterrupts", + "name": "interrupts", + "cxx_class": "RiscvISA::Interrupts" + } + ], + "dcache_port": { + "peer": "system.ruby.l1_cntrl0.sequencer.slave[1]", + "role": "MASTER" + }, + "socket_id": 0, + "power_model": null, + "max_insts_all_threads": 0, + "path": "system.cpu", + "max_loads_any_thread": 0, + "switched_out": false, + "workload": [ + { + "uid": 100, + "pid": 100, + "kvmInSE": false, + "cxx_class": "LiveProcess", + "executable": "/z/powerjg/gem5-upstream/tests/test-progs/hello/bin/riscv/linux/hello", + "drivers": [], + "system": "system", + "gid": 100, + "eventq_index": 0, + "env": [], + "input": "cin", + "ppid": 99, + "type": "LiveProcess", + "cwd": "", + "simpoint": 0, + "euid": 100, + "path": "system.cpu.workload", + "max_stack_size": 67108864, + "name": "workload", + "cmd": [ + "hello" + ], + "errout": "cerr", + "useArchPT": false, + "egid": 100, + "output": "cout" + } + ], + "name": "cpu", + "dtb": { + "name": "dtb", + "eventq_index": 0, + "cxx_class": "RiscvISA::TLB", + "path": "system.cpu.dtb", + "type": "RiscvTLB", + "size": 64 + }, + "simpoint_start_insts": [], + "max_insts_any_thread": 0, + "progress_interval": 0, + "branchPred": null, + "isa": [ + { + "eventq_index": 0, + "path": "system.cpu.isa", + "type": "RiscvISA", + "name": "isa", + "cxx_class": "RiscvISA::ISA" + } + ], + "tracer": { + "eventq_index": 0, + "path": "system.cpu.tracer", + "type": "ExeTracer", + "name": "tracer", + "cxx_class": "Trace::ExeTracer" + } + }, + "multi_thread": false, + "mem_ctrls": [ + { + "static_frontend_latency": 10, + "tRFC": 260, + "activation_limit": 4, + "in_addr_map": true, + "IDD3N2": "0.0", + "tWTR": 8, + "IDD52": "0.0", + "clk_domain": "system.clk_domain", + "channels": 1, + "write_buffer_size": 64, + "device_bus_width": 8, + "VDD": "1.5", + "write_high_thresh_perc": 85, + "cxx_class": "DRAMCtrl", + "bank_groups_per_rank": 0, + "IDD2N2": "0.0", + "port": { + "peer": "system.ruby.dir_cntrl0.memory", + "role": "SLAVE" + }, + "tCCD_L": 0, + "IDD2N": "0.032", + "p_state_clk_gate_min": 1, + "null": false, + "IDD2P1": "0.032", + "eventq_index": 0, + "tRRD": 6, + "tRTW": 3, + "IDD4R": "0.157", + "burst_length": 8, + "tRTP": 8, + "IDD4W": "0.125", + "tWR": 15, + "banks_per_rank": 8, + "devices_per_rank": 8, + "IDD2P02": "0.0", + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000, + "IDD6": "0.02", + "IDD5": "0.235", + "tRCD": 14, + "type": "DRAMCtrl", + "IDD3P02": "0.0", + "tRRD_L": 0, + "IDD0": "0.055", + "IDD62": "0.0", + "min_writes_per_switch": 16, + "mem_sched_policy": "frfcfs", + "IDD02": "0.0", + "IDD2P0": "0.0", + "ranks_per_channel": 2, + "page_policy": "open_adaptive", + "IDD4W2": "0.0", + "tCS": 3, + "power_model": null, + "tCL": 14, + "read_buffer_size": 32, + "conf_table_reported": true, + "tCK": 1, + "tRAS": 35, + "tRP": 14, + "tBURST": 5, + "path": "system.mem_ctrls", + "tXP": 6, + "tXS": 270, + "addr_mapping": "RoRaBaCoCh", + "IDD3P0": "0.0", + "IDD3P1": "0.038", + "IDD3N": "0.038", + "name": "mem_ctrls", + "tXSDLL": 0, + "device_size": 536870912, + "kvm_map": true, + "dll": true, + "tXAW": 30, + "write_low_thresh_perc": 50, + "range": "0:268435455:5:19:0:0", + "VDD2": "0.0", + "IDD2P12": "0.0", + "p_state_clk_gate_bins": 20, + "tXPDLL": 0, + "IDD4R2": "0.0", + "device_rowbuffer_size": 1024, + "static_backend_latency": 10, + "max_accesses_per_row": 16, + "IDD3P12": "0.0", + "tREFI": 7800 + } + ], + "exit_on_work_items": false, + "work_item_id": -1, + "num_work_ids": 16 + }, + "time_sync_period": 100000000, + "eventq_index": 0, + "time_sync_spin_threshold": 100000, + "cxx_class": "Root", + "path": "root", + "time_sync_enable": false, + "type": "Root", + "full_system": false +}
\ No newline at end of file diff --git a/tests/quick/se/00.hello/ref/riscv/linux/simple-timing-ruby/simerr b/tests/quick/se/00.hello/ref/riscv/linux/simple-timing-ruby/simerr new file mode 100755 index 000000000..63b14556f --- /dev/null +++ b/tests/quick/se/00.hello/ref/riscv/linux/simple-timing-ruby/simerr @@ -0,0 +1,11 @@ +warn: rounding error > tolerance + 1.250000 rounded to 1 +warn: rounding error > tolerance + 1.250000 rounded to 1 +warn: rounding error > tolerance + 1.250000 rounded to 1 +warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes) +warn: Unknown operating system; assuming Linux. +warn: Sockets disabled, not accepting gdb connections +warn: ClockedObject: More than one power state change request encountered within the same simulation tick +warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files! diff --git a/tests/quick/se/00.hello/ref/riscv/linux/simple-timing-ruby/simout b/tests/quick/se/00.hello/ref/riscv/linux/simple-timing-ruby/simout new file mode 100755 index 000000000..a4d87ef7e --- /dev/null +++ b/tests/quick/se/00.hello/ref/riscv/linux/simple-timing-ruby/simout @@ -0,0 +1,15 @@ +Redirecting stdout to build/RISCV/tests/opt/quick/se/00.hello/riscv/linux/simple-timing-ruby/simout +Redirecting stderr to build/RISCV/tests/opt/quick/se/00.hello/riscv/linux/simple-timing-ruby/simerr +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled Nov 30 2016 14:33:35 +gem5 started Nov 30 2016 16:18:29 +gem5 executing on zizzer, pid 34060 +command line: /z/powerjg/gem5-upstream/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/00.hello/riscv/linux/simple-timing-ruby -re /z/powerjg/gem5-upstream/tests/testing/../run.py quick/se/00.hello/riscv/linux/simple-timing-ruby + +Global frequency set at 1000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. +Hello world! +Exiting @ tick 27947 because target called exit() diff --git a/tests/quick/se/00.hello/ref/riscv/linux/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/riscv/linux/simple-timing-ruby/stats.txt new file mode 100644 index 000000000..e859af8d4 --- /dev/null +++ b/tests/quick/se/00.hello/ref/riscv/linux/simple-timing-ruby/stats.txt @@ -0,0 +1,639 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.000028 # Number of seconds simulated +sim_ticks 27947 # Number of ticks simulated +final_tick 27947 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000 # Frequency of simulated ticks +host_inst_rate 19868 # Simulator instruction rate (inst/s) +host_op_rate 19863 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 349695 # Simulator tick rate (ticks/s) +host_mem_usage 390760 # Number of bytes of host memory used +host_seconds 0.08 # Real time elapsed on the host +sim_insts 1587 # Number of instructions simulated +sim_ops 1587 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1 # Clock period in ticks +system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 27947 # Cumulative time (in ticks) in various power states +system.mem_ctrls.bytes_read::ruby.dir_cntrl0 28032 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::total 28032 # Number of bytes read from this memory +system.mem_ctrls.bytes_written::ruby.dir_cntrl0 27776 # Number of bytes written to this memory +system.mem_ctrls.bytes_written::total 27776 # Number of bytes written to this memory +system.mem_ctrls.num_reads::ruby.dir_cntrl0 438 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::total 438 # Number of read requests responded to by this memory +system.mem_ctrls.num_writes::ruby.dir_cntrl0 434 # Number of write requests responded to by this memory +system.mem_ctrls.num_writes::total 434 # Number of write requests responded to by this memory +system.mem_ctrls.bw_read::ruby.dir_cntrl0 1003041471 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::total 1003041471 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::ruby.dir_cntrl0 993881275 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::total 993881275 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_total::ruby.dir_cntrl0 1996922747 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::total 1996922747 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.readReqs 438 # Number of read requests accepted +system.mem_ctrls.writeReqs 434 # Number of write requests accepted +system.mem_ctrls.readBursts 438 # Number of DRAM read bursts, including those serviced by the write queue +system.mem_ctrls.writeBursts 434 # Number of DRAM write bursts, including those merged in the write queue +system.mem_ctrls.bytesReadDRAM 15616 # Total number of bytes read from DRAM +system.mem_ctrls.bytesReadWrQ 12416 # Total number of bytes read from write queue +system.mem_ctrls.bytesWritten 14912 # Total number of bytes written to DRAM +system.mem_ctrls.bytesReadSys 28032 # Total read bytes from the system interface side +system.mem_ctrls.bytesWrittenSys 27776 # Total written bytes from the system interface side +system.mem_ctrls.servicedByWrQ 194 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrls.mergedWrBursts 183 # Number of DRAM write bursts merged with an existing one +system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.mem_ctrls.perBankRdBursts::0 102 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::1 69 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::2 43 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::3 30 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::4 0 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::5 0 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::6 0 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::7 0 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::8 0 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::9 0 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::10 0 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::11 0 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::12 0 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::13 0 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::14 0 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::15 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::0 100 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::1 62 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::2 41 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::3 30 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::4 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::5 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::6 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::7 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::8 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::9 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::10 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::11 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::12 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::13 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::14 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts +system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry +system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry +system.mem_ctrls.totGap 27875 # Total gap between requests +system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::6 438 # Read request sizes (log2) +system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::6 434 # Write request sizes (log2) +system.mem_ctrls.rdQLenPdf::0 244 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::1 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::2 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::4 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::0 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::1 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::2 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::3 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::4 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::5 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::6 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::7 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::8 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::9 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::10 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::11 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::15 5 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::16 5 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::17 12 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::18 14 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::19 15 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::20 15 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::21 16 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::22 14 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::23 14 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::24 14 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::25 14 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::26 14 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::27 14 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::28 14 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::29 14 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::30 14 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::31 14 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::32 14 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.mem_ctrls.bytesPerActivate::samples 35 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::mean 835.657143 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::gmean 690.201292 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::stdev 331.080756 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::0-127 2 5.71% 5.71% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::128-255 2 5.71% 11.43% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::256-383 1 2.86% 14.29% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::384-511 1 2.86% 17.14% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::512-639 1 2.86% 20.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::640-767 3 8.57% 28.57% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::1024-1151 25 71.43% 100.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::total 35 # Bytes accessed per row activation +system.mem_ctrls.rdPerTurnAround::samples 14 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::mean 17.285714 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::gmean 16.736288 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::stdev 5.580579 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::12-13 1 7.14% 7.14% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::14-15 4 28.57% 35.71% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::16-17 7 50.00% 85.71% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::18-19 1 7.14% 92.86% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::36-37 1 7.14% 100.00% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::total 14 # Reads before turning the bus around for writes +system.mem_ctrls.wrPerTurnAround::samples 14 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::mean 16.642857 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::gmean 16.611629 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::stdev 1.081818 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::16 10 71.43% 71.43% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::18 3 21.43% 92.86% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::19 1 7.14% 100.00% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::total 14 # Writes before turning the bus around for reads +system.mem_ctrls.totQLat 2979 # Total ticks spent queuing +system.mem_ctrls.totMemAccLat 7615 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.totBusLat 1220 # Total ticks spent in databus transfers +system.mem_ctrls.avgQLat 12.21 # Average queueing delay per DRAM burst +system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst +system.mem_ctrls.avgMemAccLat 31.21 # Average memory access latency per DRAM burst +system.mem_ctrls.avgRdBW 558.77 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrls.avgWrBW 533.58 # Average achieved write bandwidth in MiByte/s +system.mem_ctrls.avgRdBWSys 1003.04 # Average system read bandwidth in MiByte/s +system.mem_ctrls.avgWrBWSys 993.88 # Average system write bandwidth in MiByte/s +system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.mem_ctrls.busUtil 8.53 # Data bus utilization in percentage +system.mem_ctrls.busUtilRead 4.37 # Data bus utilization in percentage for reads +system.mem_ctrls.busUtilWrite 4.17 # Data bus utilization in percentage for writes +system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing +system.mem_ctrls.avgWrQLen 24.44 # Average write queue length when enqueuing +system.mem_ctrls.readRowHits 212 # Number of row buffer hits during reads +system.mem_ctrls.writeRowHits 228 # Number of row buffer hits during writes +system.mem_ctrls.readRowHitRate 86.89 # Row buffer hit rate for reads +system.mem_ctrls.writeRowHitRate 90.84 # Row buffer hit rate for writes +system.mem_ctrls.avgGap 31.97 # Average gap between requests +system.mem_ctrls.pageHitRate 88.89 # Row buffer hit rate, read and write combined +system.mem_ctrls_0.actEnergy 264180 # Energy for activate commands per rank (pJ) +system.mem_ctrls_0.preEnergy 135240 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_0.readEnergy 2787456 # Energy for read commands per rank (pJ) +system.mem_ctrls_0.writeEnergy 1946016 # Energy for write commands per rank (pJ) +system.mem_ctrls_0.refreshEnergy 1843920.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_0.actBackEnergy 4405872 # Energy for active background per rank (pJ) +system.mem_ctrls_0.preBackEnergy 40704 # Energy for precharge background per rank (pJ) +system.mem_ctrls_0.actPowerDownEnergy 8149176 # Energy for active power-down per rank (pJ) +system.mem_ctrls_0.prePowerDownEnergy 118272 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrls_0.totalEnergy 19690836 # Total energy per rank (pJ) +system.mem_ctrls_0.averagePower 704.577808 # Core power per rank (mW) +system.mem_ctrls_0.totalIdleTime 18179 # Total Idle time Per DRAM Rank +system.mem_ctrls_0.memoryStateTime::IDLE 22 # Time in different power states +system.mem_ctrls_0.memoryStateTime::REF 780 # Time in different power states +system.mem_ctrls_0.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrls_0.memoryStateTime::PRE_PDN 308 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT 8966 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT_PDN 17871 # Time in different power states +system.mem_ctrls_1.actEnergy 0 # Energy for activate commands per rank (pJ) +system.mem_ctrls_1.preEnergy 0 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_1.readEnergy 0 # Energy for read commands per rank (pJ) +system.mem_ctrls_1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.mem_ctrls_1.refreshEnergy 1229280.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_1.actBackEnergy 224352 # Energy for active background per rank (pJ) +system.mem_ctrls_1.preBackEnergy 3002880 # Energy for precharge background per rank (pJ) +system.mem_ctrls_1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) +system.mem_ctrls_1.prePowerDownEnergy 2889984 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls_1.selfRefreshEnergy 2906160 # Energy for self refresh per rank (pJ) +system.mem_ctrls_1.totalEnergy 10252656 # Total energy per rank (pJ) +system.mem_ctrls_1.averagePower 366.860701 # Core power per rank (mW) +system.mem_ctrls_1.totalIdleTime 7526 # Total Idle time Per DRAM Rank +system.mem_ctrls_1.memoryStateTime::IDLE 7786 # Time in different power states +system.mem_ctrls_1.memoryStateTime::REF 526 # Time in different power states +system.mem_ctrls_1.memoryStateTime::SREF 12109 # Time in different power states +system.mem_ctrls_1.memoryStateTime::PRE_PDN 7526 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT 0 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 27947 # Cumulative time (in ticks) in various power states +system.cpu.clk_domain.clock 1 # Clock period in ticks +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 9 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 27947 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 27947 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 1587 # Number of instructions committed +system.cpu.committedOps 1587 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 1588 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses +system.cpu.num_func_calls 142 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 231 # number of instructions that are conditional controls +system.cpu.num_int_insts 1588 # number of integer instructions +system.cpu.num_fp_insts 0 # number of float instructions +system.cpu.num_int_register_reads 2062 # number of times the integer registers were read +system.cpu.num_int_register_writes 1077 # number of times the integer registers were written +system.cpu.num_fp_register_reads 0 # number of times the floating registers were read +system.cpu.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu.num_mem_refs 569 # number of memory refs +system.cpu.num_load_insts 289 # Number of load instructions +system.cpu.num_store_insts 280 # Number of store instructions +system.cpu.num_idle_cycles 0 # Number of idle cycles +system.cpu.num_busy_cycles 27947 # Number of busy cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.Branches 373 # Number of branches fetched +system.cpu.op_class::No_OpClass 9 0.56% 0.56% # Class of executed instruction +system.cpu.op_class::IntAlu 1019 63.81% 64.37% # Class of executed instruction +system.cpu.op_class::IntMult 0 0.00% 64.37% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 64.37% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 64.37% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 64.37% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 64.37% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 64.37% # Class of executed instruction +system.cpu.op_class::FloatMultAcc 0 0.00% 64.37% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 64.37% # Class of executed instruction +system.cpu.op_class::FloatMisc 0 0.00% 64.37% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 64.37% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 64.37% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 64.37% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 64.37% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 64.37% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 64.37% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 64.37% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 64.37% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 64.37% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 64.37% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 64.37% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 64.37% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 64.37% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 64.37% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 64.37% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 64.37% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 64.37% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 64.37% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 64.37% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 64.37% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 64.37% # Class of executed instruction +system.cpu.op_class::MemRead 289 18.10% 82.47% # Class of executed instruction +system.cpu.op_class::MemWrite 280 17.53% 100.00% # Class of executed instruction +system.cpu.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 1597 # Class of executed instruction +system.ruby.clk_domain.clock 1 # Clock period in ticks +system.ruby.pwrStateResidencyTicks::UNDEFINED 27947 # Cumulative time (in ticks) in various power states +system.ruby.delayHist::bucket_size 1 # delay histogram for all message +system.ruby.delayHist::max_bucket 9 # delay histogram for all message +system.ruby.delayHist::samples 872 # delay histogram for all message +system.ruby.delayHist | 872 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message +system.ruby.delayHist::total 872 # delay histogram for all message +system.ruby.outstanding_req_hist_seqr::bucket_size 1 +system.ruby.outstanding_req_hist_seqr::max_bucket 9 +system.ruby.outstanding_req_hist_seqr::samples 2166 +system.ruby.outstanding_req_hist_seqr::mean 1 +system.ruby.outstanding_req_hist_seqr::gmean 1 +system.ruby.outstanding_req_hist_seqr | 0 0.00% 0.00% | 2166 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.outstanding_req_hist_seqr::total 2166 +system.ruby.latency_hist_seqr::bucket_size 32 +system.ruby.latency_hist_seqr::max_bucket 319 +system.ruby.latency_hist_seqr::samples 2165 +system.ruby.latency_hist_seqr::mean 11.908545 +system.ruby.latency_hist_seqr::gmean 2.205817 +system.ruby.latency_hist_seqr::stdev 24.908130 +system.ruby.latency_hist_seqr | 1727 79.77% 79.77% | 202 9.33% 89.10% | 224 10.35% 99.45% | 2 0.09% 99.54% | 2 0.09% 99.63% | 7 0.32% 99.95% | 0 0.00% 99.95% | 0 0.00% 99.95% | 0 0.00% 99.95% | 1 0.05% 100.00% +system.ruby.latency_hist_seqr::total 2165 +system.ruby.hit_latency_hist_seqr::bucket_size 1 +system.ruby.hit_latency_hist_seqr::max_bucket 9 +system.ruby.hit_latency_hist_seqr::samples 1727 +system.ruby.hit_latency_hist_seqr::mean 1 +system.ruby.hit_latency_hist_seqr::gmean 1 +system.ruby.hit_latency_hist_seqr | 0 0.00% 0.00% | 1727 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.hit_latency_hist_seqr::total 1727 +system.ruby.miss_latency_hist_seqr::bucket_size 32 +system.ruby.miss_latency_hist_seqr::max_bucket 319 +system.ruby.miss_latency_hist_seqr::samples 438 +system.ruby.miss_latency_hist_seqr::mean 54.920091 +system.ruby.miss_latency_hist_seqr::gmean 49.915756 +system.ruby.miss_latency_hist_seqr::stdev 27.345330 +system.ruby.miss_latency_hist_seqr | 0 0.00% 0.00% | 202 46.12% 46.12% | 224 51.14% 97.26% | 2 0.46% 97.72% | 2 0.46% 98.17% | 7 1.60% 99.77% | 0 0.00% 99.77% | 0 0.00% 99.77% | 0 0.00% 99.77% | 1 0.23% 100.00% +system.ruby.miss_latency_hist_seqr::total 438 +system.ruby.Directory.incomplete_times_seqr 437 +system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 27947 # Cumulative time (in ticks) in various power states +system.ruby.l1_cntrl0.cacheMemory.demand_hits 1727 # Number of cache demand hits +system.ruby.l1_cntrl0.cacheMemory.demand_misses 438 # Number of cache demand misses +system.ruby.l1_cntrl0.cacheMemory.demand_accesses 2165 # Number of cache demand accesses +system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 27947 # Cumulative time (in ticks) in various power states +system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 27947 # Cumulative time (in ticks) in various power states +system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks +system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 27947 # Cumulative time (in ticks) in various power states +system.ruby.network.routers0.percent_links_utilized 7.800479 +system.ruby.network.routers0.msg_count.Control::2 438 +system.ruby.network.routers0.msg_count.Data::2 434 +system.ruby.network.routers0.msg_count.Response_Data::4 438 +system.ruby.network.routers0.msg_count.Writeback_Control::3 434 +system.ruby.network.routers0.msg_bytes.Control::2 3504 +system.ruby.network.routers0.msg_bytes.Data::2 31248 +system.ruby.network.routers0.msg_bytes.Response_Data::4 31536 +system.ruby.network.routers0.msg_bytes.Writeback_Control::3 3472 +system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 27947 # Cumulative time (in ticks) in various power states +system.ruby.network.routers1.percent_links_utilized 7.800479 +system.ruby.network.routers1.msg_count.Control::2 438 +system.ruby.network.routers1.msg_count.Data::2 434 +system.ruby.network.routers1.msg_count.Response_Data::4 438 +system.ruby.network.routers1.msg_count.Writeback_Control::3 434 +system.ruby.network.routers1.msg_bytes.Control::2 3504 +system.ruby.network.routers1.msg_bytes.Data::2 31248 +system.ruby.network.routers1.msg_bytes.Response_Data::4 31536 +system.ruby.network.routers1.msg_bytes.Writeback_Control::3 3472 +system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 27947 # Cumulative time (in ticks) in various power states +system.ruby.network.routers2.percent_links_utilized 7.800479 +system.ruby.network.routers2.msg_count.Control::2 438 +system.ruby.network.routers2.msg_count.Data::2 434 +system.ruby.network.routers2.msg_count.Response_Data::4 438 +system.ruby.network.routers2.msg_count.Writeback_Control::3 434 +system.ruby.network.routers2.msg_bytes.Control::2 3504 +system.ruby.network.routers2.msg_bytes.Data::2 31248 +system.ruby.network.routers2.msg_bytes.Response_Data::4 31536 +system.ruby.network.routers2.msg_bytes.Writeback_Control::3 3472 +system.ruby.network.pwrStateResidencyTicks::UNDEFINED 27947 # Cumulative time (in ticks) in various power states +system.ruby.network.msg_count.Control 1314 +system.ruby.network.msg_count.Data 1302 +system.ruby.network.msg_count.Response_Data 1314 +system.ruby.network.msg_count.Writeback_Control 1302 +system.ruby.network.msg_byte.Control 10512 +system.ruby.network.msg_byte.Data 93744 +system.ruby.network.msg_byte.Response_Data 94608 +system.ruby.network.msg_byte.Writeback_Control 10416 +system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 27947 # Cumulative time (in ticks) in various power states +system.ruby.network.routers0.throttle0.link_utilization 7.829105 +system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 438 +system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 434 +system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 31536 +system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3 3472 +system.ruby.network.routers0.throttle1.link_utilization 7.771854 +system.ruby.network.routers0.throttle1.msg_count.Control::2 438 +system.ruby.network.routers0.throttle1.msg_count.Data::2 434 +system.ruby.network.routers0.throttle1.msg_bytes.Control::2 3504 +system.ruby.network.routers0.throttle1.msg_bytes.Data::2 31248 +system.ruby.network.routers1.throttle0.link_utilization 7.771854 +system.ruby.network.routers1.throttle0.msg_count.Control::2 438 +system.ruby.network.routers1.throttle0.msg_count.Data::2 434 +system.ruby.network.routers1.throttle0.msg_bytes.Control::2 3504 +system.ruby.network.routers1.throttle0.msg_bytes.Data::2 31248 +system.ruby.network.routers1.throttle1.link_utilization 7.829105 +system.ruby.network.routers1.throttle1.msg_count.Response_Data::4 438 +system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::3 434 +system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4 31536 +system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::3 3472 +system.ruby.network.routers2.throttle0.link_utilization 7.829105 +system.ruby.network.routers2.throttle0.msg_count.Response_Data::4 438 +system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3 434 +system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4 31536 +system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3 3472 +system.ruby.network.routers2.throttle1.link_utilization 7.771854 +system.ruby.network.routers2.throttle1.msg_count.Control::2 438 +system.ruby.network.routers2.throttle1.msg_count.Data::2 434 +system.ruby.network.routers2.throttle1.msg_bytes.Control::2 3504 +system.ruby.network.routers2.throttle1.msg_bytes.Data::2 31248 +system.ruby.delayVCHist.vnet_1::bucket_size 1 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1::max_bucket 9 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1::samples 438 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1 | 438 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1::total 438 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_2::bucket_size 1 # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2::max_bucket 9 # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2::samples 434 # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2 | 434 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2::total 434 # delay histogram for vnet_2 +system.ruby.LD.latency_hist_seqr::bucket_size 32 +system.ruby.LD.latency_hist_seqr::max_bucket 319 +system.ruby.LD.latency_hist_seqr::samples 289 +system.ruby.LD.latency_hist_seqr::mean 23.332180 +system.ruby.LD.latency_hist_seqr::gmean 5.457216 +system.ruby.LD.latency_hist_seqr::stdev 32.553168 +system.ruby.LD.latency_hist_seqr | 161 55.71% 55.71% | 72 24.91% 80.62% | 54 18.69% 99.31% | 0 0.00% 99.31% | 0 0.00% 99.31% | 1 0.35% 99.65% | 0 0.00% 99.65% | 0 0.00% 99.65% | 0 0.00% 99.65% | 1 0.35% 100.00% +system.ruby.LD.latency_hist_seqr::total 289 +system.ruby.LD.hit_latency_hist_seqr::bucket_size 1 +system.ruby.LD.hit_latency_hist_seqr::max_bucket 9 +system.ruby.LD.hit_latency_hist_seqr::samples 161 +system.ruby.LD.hit_latency_hist_seqr::mean 1 +system.ruby.LD.hit_latency_hist_seqr::gmean 1 +system.ruby.LD.hit_latency_hist_seqr | 0 0.00% 0.00% | 161 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.hit_latency_hist_seqr::total 161 +system.ruby.LD.miss_latency_hist_seqr::bucket_size 32 +system.ruby.LD.miss_latency_hist_seqr::max_bucket 319 +system.ruby.LD.miss_latency_hist_seqr::samples 128 +system.ruby.LD.miss_latency_hist_seqr::mean 51.421875 +system.ruby.LD.miss_latency_hist_seqr::gmean 46.125665 +system.ruby.LD.miss_latency_hist_seqr::stdev 31.235103 +system.ruby.LD.miss_latency_hist_seqr | 0 0.00% 0.00% | 72 56.25% 56.25% | 54 42.19% 98.44% | 0 0.00% 98.44% | 0 0.00% 98.44% | 1 0.78% 99.22% | 0 0.00% 99.22% | 0 0.00% 99.22% | 0 0.00% 99.22% | 1 0.78% 100.00% +system.ruby.LD.miss_latency_hist_seqr::total 128 +system.ruby.ST.latency_hist_seqr::bucket_size 16 +system.ruby.ST.latency_hist_seqr::max_bucket 159 +system.ruby.ST.latency_hist_seqr::samples 279 +system.ruby.ST.latency_hist_seqr::mean 13.150538 +system.ruby.ST.latency_hist_seqr::gmean 2.682693 +system.ruby.ST.latency_hist_seqr::stdev 23.311750 +system.ruby.ST.latency_hist_seqr | 206 73.84% 73.84% | 0 0.00% 73.84% | 45 16.13% 89.96% | 2 0.72% 90.68% | 22 7.89% 98.57% | 2 0.72% 99.28% | 0 0.00% 99.28% | 1 0.36% 99.64% | 1 0.36% 100.00% | 0 0.00% 100.00% +system.ruby.ST.latency_hist_seqr::total 279 +system.ruby.ST.hit_latency_hist_seqr::bucket_size 1 +system.ruby.ST.hit_latency_hist_seqr::max_bucket 9 +system.ruby.ST.hit_latency_hist_seqr::samples 206 +system.ruby.ST.hit_latency_hist_seqr::mean 1 +system.ruby.ST.hit_latency_hist_seqr::gmean 1 +system.ruby.ST.hit_latency_hist_seqr | 0 0.00% 0.00% | 206 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.hit_latency_hist_seqr::total 206 +system.ruby.ST.miss_latency_hist_seqr::bucket_size 16 +system.ruby.ST.miss_latency_hist_seqr::max_bucket 159 +system.ruby.ST.miss_latency_hist_seqr::samples 73 +system.ruby.ST.miss_latency_hist_seqr::mean 47.438356 +system.ruby.ST.miss_latency_hist_seqr::gmean 43.447321 +system.ruby.ST.miss_latency_hist_seqr::stdev 21.997466 +system.ruby.ST.miss_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 45 61.64% 61.64% | 2 2.74% 64.38% | 22 30.14% 94.52% | 2 2.74% 97.26% | 0 0.00% 97.26% | 1 1.37% 98.63% | 1 1.37% 100.00% | 0 0.00% 100.00% +system.ruby.ST.miss_latency_hist_seqr::total 73 +system.ruby.IFETCH.latency_hist_seqr::bucket_size 32 +system.ruby.IFETCH.latency_hist_seqr::max_bucket 319 +system.ruby.IFETCH.latency_hist_seqr::samples 1597 +system.ruby.IFETCH.latency_hist_seqr::mean 9.624296 +system.ruby.IFETCH.latency_hist_seqr::gmean 1.809372 +system.ruby.IFETCH.latency_hist_seqr::stdev 22.939232 +system.ruby.IFETCH.latency_hist_seqr | 1360 85.16% 85.16% | 83 5.20% 90.36% | 146 9.14% 99.50% | 1 0.06% 99.56% | 1 0.06% 99.62% | 6 0.38% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.latency_hist_seqr::total 1597 +system.ruby.IFETCH.hit_latency_hist_seqr::bucket_size 1 +system.ruby.IFETCH.hit_latency_hist_seqr::max_bucket 9 +system.ruby.IFETCH.hit_latency_hist_seqr::samples 1360 +system.ruby.IFETCH.hit_latency_hist_seqr::mean 1 +system.ruby.IFETCH.hit_latency_hist_seqr::gmean 1 +system.ruby.IFETCH.hit_latency_hist_seqr | 0 0.00% 0.00% | 1360 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.hit_latency_hist_seqr::total 1360 +system.ruby.IFETCH.miss_latency_hist_seqr::bucket_size 32 +system.ruby.IFETCH.miss_latency_hist_seqr::max_bucket 319 +system.ruby.IFETCH.miss_latency_hist_seqr::samples 237 +system.ruby.IFETCH.miss_latency_hist_seqr::mean 59.113924 +system.ruby.IFETCH.miss_latency_hist_seqr::gmean 54.365760 +system.ruby.IFETCH.miss_latency_hist_seqr::stdev 25.891554 +system.ruby.IFETCH.miss_latency_hist_seqr | 0 0.00% 0.00% | 83 35.02% 35.02% | 146 61.60% 96.62% | 1 0.42% 97.05% | 1 0.42% 97.47% | 6 2.53% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.miss_latency_hist_seqr::total 237 +system.ruby.Directory.miss_mach_latency_hist_seqr::bucket_size 32 +system.ruby.Directory.miss_mach_latency_hist_seqr::max_bucket 319 +system.ruby.Directory.miss_mach_latency_hist_seqr::samples 438 +system.ruby.Directory.miss_mach_latency_hist_seqr::mean 54.920091 +system.ruby.Directory.miss_mach_latency_hist_seqr::gmean 49.915756 +system.ruby.Directory.miss_mach_latency_hist_seqr::stdev 27.345330 +system.ruby.Directory.miss_mach_latency_hist_seqr | 0 0.00% 0.00% | 202 46.12% 46.12% | 224 51.14% 97.26% | 2 0.46% 97.72% | 2 0.46% 98.17% | 7 1.60% 99.77% | 0 0.00% 99.77% | 0 0.00% 99.77% | 0 0.00% 99.77% | 1 0.23% 100.00% +system.ruby.Directory.miss_mach_latency_hist_seqr::total 438 +system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::bucket_size 1 +system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::max_bucket 9 +system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::samples 1 +system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::stdev nan +system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::total 1 +system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::bucket_size 1 +system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::max_bucket 9 +system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::samples 1 +system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::stdev nan +system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::total 1 +system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::bucket_size 1 +system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::max_bucket 9 +system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::samples 1 +system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::stdev nan +system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::total 1 +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::bucket_size 8 +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::max_bucket 79 +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::samples 1 +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::mean 75 +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::gmean 75.000000 +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::stdev nan +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::total 1 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::bucket_size 32 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::max_bucket 319 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::samples 128 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::mean 51.421875 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::gmean 46.125665 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::stdev 31.235103 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 72 56.25% 56.25% | 54 42.19% 98.44% | 0 0.00% 98.44% | 0 0.00% 98.44% | 1 0.78% 99.22% | 0 0.00% 99.22% | 0 0.00% 99.22% | 0 0.00% 99.22% | 1 0.78% 100.00% +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::total 128 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::bucket_size 16 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::max_bucket 159 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::samples 73 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::mean 47.438356 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::gmean 43.447321 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::stdev 21.997466 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 45 61.64% 61.64% | 2 2.74% 64.38% | 22 30.14% 94.52% | 2 2.74% 97.26% | 0 0.00% 97.26% | 1 1.37% 98.63% | 1 1.37% 100.00% | 0 0.00% 100.00% +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::total 73 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::bucket_size 32 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::max_bucket 319 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::samples 237 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::mean 59.113924 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::gmean 54.365760 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::stdev 25.891554 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 83 35.02% 35.02% | 146 61.60% 96.62% | 1 0.42% 97.05% | 1 0.42% 97.47% | 6 2.53% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::total 237 +system.ruby.Directory_Controller.GETX 438 0.00% 0.00% +system.ruby.Directory_Controller.PUTX 434 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Data 438 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Ack 434 0.00% 0.00% +system.ruby.Directory_Controller.I.GETX 438 0.00% 0.00% +system.ruby.Directory_Controller.M.PUTX 434 0.00% 0.00% +system.ruby.Directory_Controller.IM.Memory_Data 438 0.00% 0.00% +system.ruby.Directory_Controller.MI.Memory_Ack 434 0.00% 0.00% +system.ruby.L1Cache_Controller.Load 289 0.00% 0.00% +system.ruby.L1Cache_Controller.Ifetch 1597 0.00% 0.00% +system.ruby.L1Cache_Controller.Store 279 0.00% 0.00% +system.ruby.L1Cache_Controller.Data 438 0.00% 0.00% +system.ruby.L1Cache_Controller.Replacement 434 0.00% 0.00% +system.ruby.L1Cache_Controller.Writeback_Ack 434 0.00% 0.00% +system.ruby.L1Cache_Controller.I.Load 128 0.00% 0.00% +system.ruby.L1Cache_Controller.I.Ifetch 237 0.00% 0.00% +system.ruby.L1Cache_Controller.I.Store 73 0.00% 0.00% +system.ruby.L1Cache_Controller.M.Load 161 0.00% 0.00% +system.ruby.L1Cache_Controller.M.Ifetch 1360 0.00% 0.00% +system.ruby.L1Cache_Controller.M.Store 206 0.00% 0.00% +system.ruby.L1Cache_Controller.M.Replacement 434 0.00% 0.00% +system.ruby.L1Cache_Controller.MI.Writeback_Ack 434 0.00% 0.00% +system.ruby.L1Cache_Controller.IS.Data 365 0.00% 0.00% +system.ruby.L1Cache_Controller.IM.Data 73 0.00% 0.00% + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/riscv/linux/simple-timing/config.ini b/tests/quick/se/00.hello/ref/riscv/linux/simple-timing/config.ini new file mode 100644 index 000000000..95b43cc99 --- /dev/null +++ b/tests/quick/se/00.hello/ref/riscv/linux/simple-timing/config.ini @@ -0,0 +1,380 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain +boot_osflags=a +cache_line_size=64 +clk_domain=system.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +exit_on_work_items=false +init_param=0 +kernel= +kernel_addr_check=true +load_addr_mask=1099511627775 +load_offset=0 +mem_mode=timing +mem_ranges= +memories=system.physmem +mmap_using_noreserve=false +multi_thread=false +num_work_ids=16 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +readfile= +symbolfile= +thermal_components= +thermal_model=Null +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=TimingSimpleCPU +children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload +branchPred=Null +checker=Null +clk_domain=system.cpu_clk_domain +cpu_id=0 +default_p_state=UNDEFINED +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +eventq_index=0 +function_trace=false +function_trace_start=0 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +profile=0 +progress_interval=0 +simpoint_start_insts= +socket_id=0 +switched_out=false +system=system +tracer=system.cpu.tracer +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.dcache] +type=Cache +children=tags +addr_ranges=0:18446744073709551615:0:0:0:0 +assoc=2 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +data_latency=2 +default_p_state=UNDEFINED +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=4 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=262144 +system=system +tag_latency=2 +tags=system.cpu.dcache.tags +tgts_per_mshr=20 +write_buffers=8 +writeback_clean=false +cpu_side=system.cpu.dcache_port +mem_side=system.cpu.toL2Bus.slave[1] + +[system.cpu.dcache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +data_latency=2 +default_p_state=UNDEFINED +eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +sequential_access=false +size=262144 +tag_latency=2 + +[system.cpu.dtb] +type=RiscvTLB +eventq_index=0 +size=64 + +[system.cpu.icache] +type=Cache +children=tags +addr_ranges=0:18446744073709551615:0:0:0:0 +assoc=2 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +data_latency=2 +default_p_state=UNDEFINED +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=true +max_miss_count=0 +mshrs=4 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=131072 +system=system +tag_latency=2 +tags=system.cpu.icache.tags +tgts_per_mshr=20 +write_buffers=8 +writeback_clean=true +cpu_side=system.cpu.icache_port +mem_side=system.cpu.toL2Bus.slave[0] + +[system.cpu.icache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +data_latency=2 +default_p_state=UNDEFINED +eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +sequential_access=false +size=131072 +tag_latency=2 + +[system.cpu.interrupts] +type=RiscvInterrupts +eventq_index=0 + +[system.cpu.isa] +type=RiscvISA +eventq_index=0 + +[system.cpu.itb] +type=RiscvTLB +eventq_index=0 +size=64 + +[system.cpu.l2cache] +type=Cache +children=tags +addr_ranges=0:18446744073709551615:0:0:0:0 +assoc=8 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +data_latency=20 +default_p_state=UNDEFINED +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=20 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +prefetch_on_access=false +prefetcher=Null +response_latency=20 +sequential_access=false +size=2097152 +system=system +tag_latency=20 +tags=system.cpu.l2cache.tags +tgts_per_mshr=12 +write_buffers=8 +writeback_clean=false +cpu_side=system.cpu.toL2Bus.master[0] +mem_side=system.membus.slave[1] + +[system.cpu.l2cache.tags] +type=LRU +assoc=8 +block_size=64 +clk_domain=system.cpu_clk_domain +data_latency=20 +default_p_state=UNDEFINED +eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +sequential_access=false +size=2097152 +tag_latency=20 + +[system.cpu.toL2Bus] +type=CoherentXBar +children=snoop_filter +clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED +eventq_index=0 +forward_latency=0 +frontend_latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +point_of_coherency=false +power_model=Null +response_latency=1 +snoop_filter=system.cpu.toL2Bus.snoop_filter +snoop_response_latency=1 +system=system +use_default_range=false +width=32 +master=system.cpu.l2cache.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side + +[system.cpu.toL2Bus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=0 +max_capacity=8388608 +system=system + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=LiveProcess +cmd=hello +cwd= +drivers= +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable=/z/powerjg/gem5-upstream/tests/test-progs/hello/bin/riscv/linux/hello +gid=100 +input=cin +kvmInSE=false +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=0 +system=system +uid=100 +useArchPT=false + +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000000 + +[system.membus] +type=CoherentXBar +children=snoop_filter +clk_domain=system.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +forward_latency=4 +frontend_latency=3 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +point_of_coherency=true +power_model=Null +response_latency=2 +snoop_filter=system.membus.snoop_filter +snoop_response_latency=4 +system=system +use_default_range=false +width=16 +master=system.physmem.port +slave=system.system_port system.cpu.l2cache.mem_side + +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + +[system.physmem] +type=SimpleMemory +bandwidth=73.000000 +clk_domain=system.clk_domain +conf_table_reported=true +default_p_state=UNDEFINED +eventq_index=0 +in_addr_map=true +kvm_map=true +latency=30000 +latency_var=0 +null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +range=0:134217727:0:0:0:0 +port=system.membus.master[0] + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + diff --git a/tests/quick/se/00.hello/ref/riscv/linux/simple-timing/config.json b/tests/quick/se/00.hello/ref/riscv/linux/simple-timing/config.json new file mode 100644 index 000000000..0e161c12e --- /dev/null +++ b/tests/quick/se/00.hello/ref/riscv/linux/simple-timing/config.json @@ -0,0 +1,508 @@ +{ + "name": null, + "sim_quantum": 0, + "system": { + "kernel": "", + "mmap_using_noreserve": false, + "kernel_addr_check": true, + "membus": { + "point_of_coherency": true, + "system": "system", + "response_latency": 2, + "cxx_class": "CoherentXBar", + "forward_latency": 4, + "clk_domain": "system.clk_domain", + "width": 16, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "master": { + "peer": [ + "system.physmem.port" + ], + "role": "MASTER" + }, + "type": "CoherentXBar", + "frontend_latency": 3, + "slave": { + "peer": [ + "system.system_port", + "system.cpu.l2cache.mem_side" + ], + "role": "SLAVE" + }, + "p_state_clk_gate_min": 1000, + "snoop_filter": { + "name": "snoop_filter", + "system": "system", + "max_capacity": 8388608, + "eventq_index": 0, + "cxx_class": "SnoopFilter", + "path": "system.membus.snoop_filter", + "type": "SnoopFilter", + "lookup_latency": 1 + }, + "power_model": null, + "path": "system.membus", + "snoop_response_latency": 4, + "name": "membus", + "p_state_clk_gate_bins": 20, + "use_default_range": false + }, + "symbolfile": "", + "readfile": "", + "thermal_model": null, + "cxx_class": "System", + "work_begin_cpu_id_exit": -1, + "load_offset": 0, + "work_begin_exit_count": 0, + "p_state_clk_gate_min": 1000, + "memories": [ + "system.physmem" + ], + "work_begin_ckpt_count": 0, + "clk_domain": { + "name": "clk_domain", + "clock": [ + 1000 + ], + "init_perf_level": 0, + "voltage_domain": "system.voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "mem_ranges": [], + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "dvfs_handler": { + "enable": false, + "name": "dvfs_handler", + "sys_clk_domain": "system.clk_domain", + "transition_latency": 100000000, + "eventq_index": 0, + "cxx_class": "DVFSHandler", + "domains": [], + "path": "system.dvfs_handler", + "type": "DVFSHandler" + }, + "work_end_exit_count": 0, + "type": "System", + "voltage_domain": { + "name": "voltage_domain", + "eventq_index": 0, + "voltage": [ + "1.0" + ], + "cxx_class": "VoltageDomain", + "path": "system.voltage_domain", + "type": "VoltageDomain" + }, + "cache_line_size": 64, + "boot_osflags": "a", + "system_port": { + "peer": "system.membus.slave[0]", + "role": "MASTER" + }, + "physmem": { + "range": "0:134217727:0:0:0:0", + "latency": 30000, + "name": "physmem", + "p_state_clk_gate_min": 1000, + "eventq_index": 0, + "p_state_clk_gate_bins": 20, + "default_p_state": "UNDEFINED", + "kvm_map": true, + "clk_domain": "system.clk_domain", + "power_model": null, + "latency_var": 0, + "bandwidth": "73.000000", + "conf_table_reported": true, + "cxx_class": "SimpleMemory", + "p_state_clk_gate_max": 1000000000000, + "path": "system.physmem", + "null": false, + "type": "SimpleMemory", + "port": { + "peer": "system.membus.master[0]", + "role": "SLAVE" + }, + "in_addr_map": true + }, + "power_model": null, + "work_cpus_ckpt_count": 0, + "thermal_components": [], + "path": "system", + "cpu_clk_domain": { + "name": "cpu_clk_domain", + "clock": [ + 500 + ], + "init_perf_level": 0, + "voltage_domain": "system.voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.cpu_clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "work_end_ckpt_count": 0, + "mem_mode": "timing", + "name": "system", + "init_param": 0, + "p_state_clk_gate_bins": 20, + "load_addr_mask": 1099511627775, + "cpu": [ + { + "do_statistics_insts": true, + "numThreads": 1, + "itb": { + "name": "itb", + "eventq_index": 0, + "cxx_class": "RiscvISA::TLB", + "path": "system.cpu.itb", + "type": "RiscvTLB", + "size": 64 + }, + "system": "system", + "icache": { + "cpu_side": { + "peer": "system.cpu.icache_port", + "role": "SLAVE" + }, + "clusivity": "mostly_incl", + "prefetcher": null, + "system": "system", + "write_buffers": 8, + "response_latency": 2, + "cxx_class": "Cache", + "size": 131072, + "type": "Cache", + "clk_domain": "system.cpu_clk_domain", + "max_miss_count": 0, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "mem_side": { + "peer": "system.cpu.toL2Bus.slave[0]", + "role": "MASTER" + }, + "mshrs": 4, + "writeback_clean": true, + "p_state_clk_gate_min": 1000, + "tags": { + "size": 131072, + "tag_latency": 2, + "name": "tags", + "p_state_clk_gate_min": 1000, + "eventq_index": 0, + "p_state_clk_gate_bins": 20, + "default_p_state": "UNDEFINED", + "clk_domain": "system.cpu_clk_domain", + "power_model": null, + "sequential_access": false, + "assoc": 2, + "cxx_class": "LRU", + "p_state_clk_gate_max": 1000000000000, + "path": "system.cpu.icache.tags", + "block_size": 64, + "type": "LRU", + "data_latency": 2 + }, + "tgts_per_mshr": 20, + "demand_mshr_reserve": 1, + "power_model": null, + "addr_ranges": [ + "0:18446744073709551615:0:0:0:0" + ], + "is_read_only": true, + "prefetch_on_access": false, + "path": "system.cpu.icache", + "data_latency": 2, + "tag_latency": 2, + "name": "icache", + "p_state_clk_gate_bins": 20, + "sequential_access": false, + "assoc": 2 + }, + "function_trace": false, + "do_checkpoint_insts": true, + "cxx_class": "TimingSimpleCPU", + "max_loads_all_threads": 0, + "clk_domain": "system.cpu_clk_domain", + "function_trace_start": 0, + "cpu_id": 0, + "checker": null, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "toL2Bus": { + "point_of_coherency": false, + "system": "system", + "response_latency": 1, + "cxx_class": "CoherentXBar", + "forward_latency": 0, + "clk_domain": "system.cpu_clk_domain", + "width": 32, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "master": { + "peer": [ + "system.cpu.l2cache.cpu_side" + ], + "role": "MASTER" + }, + "type": "CoherentXBar", + "frontend_latency": 1, + "slave": { + "peer": [ + "system.cpu.icache.mem_side", + "system.cpu.dcache.mem_side" + ], + "role": "SLAVE" + }, + "p_state_clk_gate_min": 1000, + "snoop_filter": { + "name": "snoop_filter", + "system": "system", + "max_capacity": 8388608, + "eventq_index": 0, + "cxx_class": "SnoopFilter", + "path": "system.cpu.toL2Bus.snoop_filter", + "type": "SnoopFilter", + "lookup_latency": 0 + }, + "power_model": null, + "path": "system.cpu.toL2Bus", + "snoop_response_latency": 1, + "name": "toL2Bus", + "p_state_clk_gate_bins": 20, + "use_default_range": false + }, + "do_quiesce": true, + "type": "TimingSimpleCPU", + "profile": 0, + "icache_port": { + "peer": "system.cpu.icache.cpu_side", + "role": "MASTER" + }, + "p_state_clk_gate_bins": 20, + "p_state_clk_gate_min": 1000, + "interrupts": [ + { + "eventq_index": 0, + "path": "system.cpu.interrupts", + "type": "RiscvInterrupts", + "name": "interrupts", + "cxx_class": "RiscvISA::Interrupts" + } + ], + "dcache_port": { + "peer": "system.cpu.dcache.cpu_side", + "role": "MASTER" + }, + "socket_id": 0, + "power_model": null, + "max_insts_all_threads": 0, + "l2cache": { + "cpu_side": { + "peer": "system.cpu.toL2Bus.master[0]", + "role": "SLAVE" + }, + "clusivity": "mostly_incl", + "prefetcher": null, + "system": "system", + "write_buffers": 8, + "response_latency": 20, + "cxx_class": "Cache", + "size": 2097152, + "type": "Cache", + "clk_domain": "system.cpu_clk_domain", + "max_miss_count": 0, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "mem_side": { + "peer": "system.membus.slave[1]", + "role": "MASTER" + }, + "mshrs": 20, + "writeback_clean": false, + "p_state_clk_gate_min": 1000, + "tags": { + "size": 2097152, + "tag_latency": 20, + "name": "tags", + "p_state_clk_gate_min": 1000, + "eventq_index": 0, + "p_state_clk_gate_bins": 20, + "default_p_state": "UNDEFINED", + "clk_domain": "system.cpu_clk_domain", + "power_model": null, + "sequential_access": false, + "assoc": 8, + "cxx_class": "LRU", + "p_state_clk_gate_max": 1000000000000, + "path": "system.cpu.l2cache.tags", + "block_size": 64, + "type": "LRU", + "data_latency": 20 + }, + "tgts_per_mshr": 12, + "demand_mshr_reserve": 1, + "power_model": null, + "addr_ranges": [ + "0:18446744073709551615:0:0:0:0" + ], + "is_read_only": false, + "prefetch_on_access": false, + "path": "system.cpu.l2cache", + "data_latency": 20, + "tag_latency": 20, + "name": "l2cache", + "p_state_clk_gate_bins": 20, + "sequential_access": false, + "assoc": 8 + }, + "path": "system.cpu", + "max_loads_any_thread": 0, + "switched_out": false, + "workload": [ + { + "uid": 100, + "pid": 100, + "kvmInSE": false, + "cxx_class": "LiveProcess", + "executable": "/z/powerjg/gem5-upstream/tests/test-progs/hello/bin/riscv/linux/hello", + "drivers": [], + "system": "system", + "gid": 100, + "eventq_index": 0, + "env": [], + "input": "cin", + "ppid": 99, + "type": "LiveProcess", + "cwd": "", + "simpoint": 0, + "euid": 100, + "path": "system.cpu.workload", + "max_stack_size": 67108864, + "name": "workload", + "cmd": [ + "hello" + ], + "errout": "cerr", + "useArchPT": false, + "egid": 100, + "output": "cout" + } + ], + "name": "cpu", + "dtb": { + "name": "dtb", + "eventq_index": 0, + "cxx_class": "RiscvISA::TLB", + "path": "system.cpu.dtb", + "type": "RiscvTLB", + "size": 64 + }, + "simpoint_start_insts": [], + "max_insts_any_thread": 0, + "progress_interval": 0, + "branchPred": null, + "dcache": { + "cpu_side": { + "peer": "system.cpu.dcache_port", + "role": "SLAVE" + }, + "clusivity": "mostly_incl", + "prefetcher": null, + "system": "system", + "write_buffers": 8, + "response_latency": 2, + "cxx_class": "Cache", + "size": 262144, + "type": "Cache", + "clk_domain": "system.cpu_clk_domain", + "max_miss_count": 0, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "mem_side": { + "peer": "system.cpu.toL2Bus.slave[1]", + "role": "MASTER" + }, + "mshrs": 4, + "writeback_clean": false, + "p_state_clk_gate_min": 1000, + "tags": { + "size": 262144, + "tag_latency": 2, + "name": "tags", + "p_state_clk_gate_min": 1000, + "eventq_index": 0, + "p_state_clk_gate_bins": 20, + "default_p_state": "UNDEFINED", + "clk_domain": "system.cpu_clk_domain", + "power_model": null, + "sequential_access": false, + "assoc": 2, + "cxx_class": "LRU", + "p_state_clk_gate_max": 1000000000000, + "path": "system.cpu.dcache.tags", + "block_size": 64, + "type": "LRU", + "data_latency": 2 + }, + "tgts_per_mshr": 20, + "demand_mshr_reserve": 1, + "power_model": null, + "addr_ranges": [ + "0:18446744073709551615:0:0:0:0" + ], + "is_read_only": false, + "prefetch_on_access": false, + "path": "system.cpu.dcache", + "data_latency": 2, + "tag_latency": 2, + "name": "dcache", + "p_state_clk_gate_bins": 20, + "sequential_access": false, + "assoc": 2 + }, + "isa": [ + { + "eventq_index": 0, + "path": "system.cpu.isa", + "type": "RiscvISA", + "name": "isa", + "cxx_class": "RiscvISA::ISA" + } + ], + "tracer": { + "eventq_index": 0, + "path": "system.cpu.tracer", + "type": "ExeTracer", + "name": "tracer", + "cxx_class": "Trace::ExeTracer" + } + } + ], + "multi_thread": false, + "exit_on_work_items": false, + "work_item_id": -1, + "num_work_ids": 16 + }, + "time_sync_period": 100000000000, + "eventq_index": 0, + "time_sync_spin_threshold": 100000000, + "cxx_class": "Root", + "path": "root", + "time_sync_enable": false, + "type": "Root", + "full_system": false +}
\ No newline at end of file diff --git a/tests/quick/se/00.hello/ref/riscv/linux/simple-timing/simerr b/tests/quick/se/00.hello/ref/riscv/linux/simple-timing/simerr new file mode 100755 index 000000000..fd133b12b --- /dev/null +++ b/tests/quick/se/00.hello/ref/riscv/linux/simple-timing/simerr @@ -0,0 +1,3 @@ +warn: Unknown operating system; assuming Linux. +warn: Sockets disabled, not accepting gdb connections +warn: ClockedObject: More than one power state change request encountered within the same simulation tick diff --git a/tests/quick/se/00.hello/ref/riscv/linux/simple-timing/simout b/tests/quick/se/00.hello/ref/riscv/linux/simple-timing/simout new file mode 100755 index 000000000..b34519614 --- /dev/null +++ b/tests/quick/se/00.hello/ref/riscv/linux/simple-timing/simout @@ -0,0 +1,15 @@ +Redirecting stdout to build/RISCV/tests/opt/quick/se/00.hello/riscv/linux/simple-timing/simout +Redirecting stderr to build/RISCV/tests/opt/quick/se/00.hello/riscv/linux/simple-timing/simerr +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled Nov 30 2016 14:33:35 +gem5 started Nov 30 2016 16:18:29 +gem5 executing on zizzer, pid 34059 +command line: /z/powerjg/gem5-upstream/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/00.hello/riscv/linux/simple-timing -re /z/powerjg/gem5-upstream/tests/testing/../run.py quick/se/00.hello/riscv/linux/simple-timing + +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. +Hello world! +Exiting @ tick 11602500 because target called exit() diff --git a/tests/quick/se/00.hello/ref/riscv/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/riscv/linux/simple-timing/stats.txt new file mode 100644 index 000000000..bb8642e88 --- /dev/null +++ b/tests/quick/se/00.hello/ref/riscv/linux/simple-timing/stats.txt @@ -0,0 +1,511 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.000012 # Number of seconds simulated +sim_ticks 11602500 # Number of ticks simulated +final_tick 11602500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 36172 # Simulator instruction rate (inst/s) +host_op_rate 36155 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 264212858 # Simulator tick rate (ticks/s) +host_mem_usage 230876 # Number of bytes of host memory used +host_seconds 0.04 # Real time elapsed on the host +sim_insts 1587 # Number of instructions simulated +sim_ops 1587 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 11602500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 7808 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 1920 # Number of bytes read from this memory +system.physmem.bytes_read::total 9728 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 7808 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 7808 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 122 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 30 # Number of read requests responded to by this memory +system.physmem.num_reads::total 152 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 672958414 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 165481577 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 838439991 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 672958414 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 672958414 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 672958414 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 165481577 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 838439991 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 11602500 # Cumulative time (in ticks) in various power states +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 9 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 11602500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 23205 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 1587 # Number of instructions committed +system.cpu.committedOps 1587 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 1588 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses +system.cpu.num_func_calls 142 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 231 # number of instructions that are conditional controls +system.cpu.num_int_insts 1588 # number of integer instructions +system.cpu.num_fp_insts 0 # number of float instructions +system.cpu.num_int_register_reads 2062 # number of times the integer registers were read +system.cpu.num_int_register_writes 1077 # number of times the integer registers were written +system.cpu.num_fp_register_reads 0 # number of times the floating registers were read +system.cpu.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu.num_mem_refs 569 # number of memory refs +system.cpu.num_load_insts 289 # Number of load instructions +system.cpu.num_store_insts 280 # Number of store instructions +system.cpu.num_idle_cycles 0 # Number of idle cycles +system.cpu.num_busy_cycles 23205 # Number of busy cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.Branches 373 # Number of branches fetched +system.cpu.op_class::No_OpClass 9 0.56% 0.56% # Class of executed instruction +system.cpu.op_class::IntAlu 1019 63.81% 64.37% # Class of executed instruction +system.cpu.op_class::IntMult 0 0.00% 64.37% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 64.37% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 64.37% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 64.37% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 64.37% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 64.37% # Class of executed instruction +system.cpu.op_class::FloatMultAcc 0 0.00% 64.37% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 64.37% # Class of executed instruction +system.cpu.op_class::FloatMisc 0 0.00% 64.37% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 64.37% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 64.37% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 64.37% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 64.37% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 64.37% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 64.37% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 64.37% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 64.37% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 64.37% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 64.37% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 64.37% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 64.37% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 64.37% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 64.37% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 64.37% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 64.37% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 64.37% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 64.37% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 64.37% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 64.37% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 64.37% # Class of executed instruction +system.cpu.op_class::MemRead 289 18.10% 82.47% # Class of executed instruction +system.cpu.op_class::MemWrite 280 17.53% 100.00% # Class of executed instruction +system.cpu.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 1597 # Class of executed instruction +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 11602500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 0 # number of replacements +system.cpu.dcache.tags.tagsinuse 22.779229 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 537 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 31 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 17.322581 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 22.779229 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.005561 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.005561 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 31 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 22 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 9 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.007568 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 1167 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1167 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 11602500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 276 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 276 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 261 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 261 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 537 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 537 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 537 # number of overall hits +system.cpu.dcache.overall_hits::total 537 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 13 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 13 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 18 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 18 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 31 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 31 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 31 # number of overall misses +system.cpu.dcache.overall_misses::total 31 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 770000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 770000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 1134000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 1134000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 1904000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 1904000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 1904000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 1904000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 289 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 289 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 279 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 279 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 568 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 568 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 568 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 568 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.044983 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.044983 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.064516 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.064516 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.054577 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.054577 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.054577 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.054577 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 59230.769231 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 59230.769231 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 63000 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 61419.354839 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 61419.354839 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 61419.354839 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 61419.354839 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 13 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 13 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 18 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 18 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 31 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 31 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 31 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 31 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 757000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 757000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1116000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1116000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 1873000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 1873000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 1873000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 1873000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.044983 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.044983 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.064516 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.064516 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.054577 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.054577 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.054577 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.054577 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 58230.769231 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 58230.769231 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 62000 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 62000 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 60419.354839 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 60419.354839 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 60419.354839 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 60419.354839 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 11602500 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 0 # number of replacements +system.cpu.icache.tags.tagsinuse 56.912998 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 1476 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 122 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 12.098361 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 56.912998 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.027790 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.027790 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 122 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 109 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 13 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.059570 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 3318 # Number of tag accesses +system.cpu.icache.tags.data_accesses 3318 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 11602500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 1476 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1476 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1476 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1476 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1476 # number of overall hits +system.cpu.icache.overall_hits::total 1476 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 122 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 122 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 122 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 122 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 122 # number of overall misses +system.cpu.icache.overall_misses::total 122 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 7686500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 7686500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 7686500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 7686500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 7686500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 7686500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1598 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1598 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1598 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1598 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1598 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1598 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.076345 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.076345 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.076345 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.076345 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.076345 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.076345 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 63004.098361 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 63004.098361 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 63004.098361 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 63004.098361 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 63004.098361 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 63004.098361 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 122 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 122 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 122 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 122 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 122 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 122 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 7564500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 7564500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 7564500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 7564500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 7564500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 7564500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.076345 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.076345 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.076345 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.076345 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.076345 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.076345 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 62004.098361 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 62004.098361 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 62004.098361 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 62004.098361 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 62004.098361 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 62004.098361 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 11602500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.replacements 0 # number of replacements +system.cpu.l2cache.tags.tagsinuse 78.991344 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 152 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.006579 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::cpu.inst 57.023406 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 21.967939 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001740 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.000670 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.002411 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 152 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 130 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 22 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.004639 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 1376 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 1376 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 11602500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 1 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.data 1 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 1 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.data 1 # number of overall hits +system.cpu.l2cache.overall_hits::total 1 # number of overall hits +system.cpu.l2cache.ReadExReq_misses::cpu.data 18 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 18 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 122 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 122 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 12 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 12 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.inst 122 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 30 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 152 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 122 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 30 # number of overall misses +system.cpu.l2cache.overall_misses::total 152 # number of overall misses +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1089000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 1089000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 7381500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 7381500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 726000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 726000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 7381500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 1815000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 9196500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 7381500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 1815000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 9196500 # number of overall miss cycles +system.cpu.l2cache.ReadExReq_accesses::cpu.data 18 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 18 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 122 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 122 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 13 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 13 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 122 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 31 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 153 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 122 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 31 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 153 # number of overall (read+write) accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 1 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 1 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.923077 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.923077 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.967742 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.993464 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.967742 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.993464 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60500 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60500 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60504.098361 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60504.098361 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60500 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60500 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60504.098361 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60500 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 60503.289474 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60504.098361 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60500 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 60503.289474 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 18 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 18 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 122 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 122 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 12 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 12 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 122 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 30 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 152 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 122 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 30 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 152 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 909000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 909000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 6161500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 6161500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 606000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 606000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 6161500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1515000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 7676500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 6161500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1515000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 7676500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 1 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.923077 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.923077 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.967742 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.993464 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.967742 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.993464 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50504.098361 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50504.098361 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50504.098361 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50503.289474 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50504.098361 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50503.289474 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 153 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 1 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 11602500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 135 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 18 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 18 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 122 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 13 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 244 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 62 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 306 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 7808 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1984 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 9792 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 153 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.006536 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.080845 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 152 99.35% 99.35% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 1 0.65% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 153 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 76500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 183000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 1.6 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 46500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%) +system.membus.snoop_filter.tot_requests 152 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 11602500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 134 # Transaction distribution +system.membus.trans_dist::ReadExReq 18 # Transaction distribution +system.membus.trans_dist::ReadExResp 18 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 134 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 304 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 304 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 9728 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 9728 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoopTraffic 0 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 152 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 152 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 152 # Request fanout histogram +system.membus.reqLayer0.occupancy 152500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 1.3 # Layer utilization (%) +system.membus.respLayer1.occupancy 760000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 6.6 # Layer utilization (%) + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/config.ini index 774234af5..5809007c6 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/config.ini +++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/config.ini @@ -183,10 +183,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=false max_miss_count=0 mshrs=4 @@ -200,6 +200,7 @@ response_latency=2 sequential_access=false size=262144 system=system +tag_latency=2 tags=system.cpu.dcache.tags tgts_per_mshr=20 write_buffers=8 @@ -212,15 +213,16 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=262144 +tag_latency=2 [system.cpu.dtb] type=X86TLB @@ -313,10 +315,10 @@ pipelined=true [system.cpu.fuPool.FUList3] type=FUDesc -children=opList0 opList1 opList2 +children=opList0 opList1 opList2 opList3 opList4 count=2 eventq_index=0 -opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 +opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 system.cpu.fuPool.FUList3.opList3 system.cpu.fuPool.FUList3.opList4 [system.cpu.fuPool.FUList3.opList0] type=OpDesc @@ -328,11 +330,25 @@ pipelined=true [system.cpu.fuPool.FUList3.opList1] type=OpDesc eventq_index=0 +opClass=FloatMultAcc +opLat=5 +pipelined=true + +[system.cpu.fuPool.FUList3.opList2] +type=OpDesc +eventq_index=0 +opClass=FloatMisc +opLat=3 +pipelined=true + +[system.cpu.fuPool.FUList3.opList3] +type=OpDesc +eventq_index=0 opClass=FloatDiv opLat=12 pipelined=false -[system.cpu.fuPool.FUList3.opList2] +[system.cpu.fuPool.FUList3.opList4] type=OpDesc eventq_index=0 opClass=FloatSqrt @@ -341,18 +357,25 @@ pipelined=false [system.cpu.fuPool.FUList4] type=FUDesc -children=opList +children=opList0 opList1 count=0 eventq_index=0 -opList=system.cpu.fuPool.FUList4.opList +opList=system.cpu.fuPool.FUList4.opList0 system.cpu.fuPool.FUList4.opList1 -[system.cpu.fuPool.FUList4.opList] +[system.cpu.fuPool.FUList4.opList0] type=OpDesc eventq_index=0 opClass=MemRead opLat=1 pipelined=true +[system.cpu.fuPool.FUList4.opList1] +type=OpDesc +eventq_index=0 +opClass=FloatMemRead +opLat=1 +pipelined=true + [system.cpu.fuPool.FUList5] type=FUDesc children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 @@ -502,24 +525,31 @@ pipelined=true [system.cpu.fuPool.FUList6] type=FUDesc -children=opList +children=opList0 opList1 count=0 eventq_index=0 -opList=system.cpu.fuPool.FUList6.opList +opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1 -[system.cpu.fuPool.FUList6.opList] +[system.cpu.fuPool.FUList6.opList0] type=OpDesc eventq_index=0 opClass=MemWrite opLat=1 pipelined=true +[system.cpu.fuPool.FUList6.opList1] +type=OpDesc +eventq_index=0 +opClass=FloatMemWrite +opLat=1 +pipelined=true + [system.cpu.fuPool.FUList7] type=FUDesc -children=opList0 opList1 +children=opList0 opList1 opList2 opList3 count=4 eventq_index=0 -opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 +opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 system.cpu.fuPool.FUList7.opList2 system.cpu.fuPool.FUList7.opList3 [system.cpu.fuPool.FUList7.opList0] type=OpDesc @@ -535,6 +565,20 @@ opClass=MemWrite opLat=1 pipelined=true +[system.cpu.fuPool.FUList7.opList2] +type=OpDesc +eventq_index=0 +opClass=FloatMemRead +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList7.opList3] +type=OpDesc +eventq_index=0 +opClass=FloatMemWrite +opLat=1 +pipelined=true + [system.cpu.fuPool.FUList8] type=FUDesc children=opList @@ -556,10 +600,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=true max_miss_count=0 mshrs=4 @@ -573,6 +617,7 @@ response_latency=2 sequential_access=false size=131072 system=system +tag_latency=2 tags=system.cpu.icache.tags tgts_per_mshr=20 write_buffers=8 @@ -585,15 +630,16 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=131072 +tag_latency=2 [system.cpu.interrupts] type=X86LocalApic @@ -643,10 +689,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0 assoc=8 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=20 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=20 is_read_only=false max_miss_count=0 mshrs=20 @@ -660,6 +706,7 @@ response_latency=20 sequential_access=false size=2097152 system=system +tag_latency=20 tags=system.cpu.l2cache.tags tgts_per_mshr=12 write_buffers=8 @@ -672,15 +719,16 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=20 default_p_state=UNDEFINED eventq_index=0 -hit_latency=20 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=2097152 +tag_latency=20 [system.cpu.toL2Bus] type=CoherentXBar @@ -725,7 +773,7 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/test-progs/hello/bin/x86/linux/hello +executable=/dist/m5/regression/test-progs/hello/bin/x86/linux/hello gid=100 input=cin kvmInSE=false diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simout index ce4c9483b..5ab7e4cb5 100755 --- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simout +++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simout @@ -3,10 +3,10 @@ Redirecting stderr to build/X86/tests/opt/quick/se/00.hello/x86/linux/o3-timing/ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Oct 11 2016 00:00:58 -gem5 started Oct 13 2016 21:09:20 -gem5 executing on e108600-lin, pid 17644 -command line: /work/curdun01/gem5-external.hg/build/X86/gem5.opt -d build/X86/tests/opt/quick/se/00.hello/x86/linux/o3-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/00.hello/x86/linux/o3-timing +gem5 compiled Nov 29 2016 18:55:59 +gem5 started Nov 29 2016 18:56:21 +gem5 executing on zizzer, pid 719 +command line: /z/powerjg/gem5-upstream/build/X86/gem5.opt -d build/X86/tests/opt/quick/se/00.hello/x86/linux/o3-timing -re /z/powerjg/gem5-upstream/tests/testing/../run.py quick/se/00.hello/x86/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt index 7984b1b75..ff0e9261d 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000022 # Nu sim_ticks 22466500 # Number of ticks simulated final_tick 22466500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 70304 # Simulator instruction rate (inst/s) -host_op_rate 127350 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 293494415 # Simulator tick rate (ticks/s) -host_mem_usage 271256 # Number of bytes of host memory used -host_seconds 0.08 # Real time elapsed on the host +host_inst_rate 24766 # Simulator instruction rate (inst/s) +host_op_rate 44863 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 103395613 # Simulator tick rate (ticks/s) +host_mem_usage 253532 # Number of bytes of host memory used +host_seconds 0.22 # Real time elapsed on the host sim_insts 5380 # Number of instructions simulated sim_ops 9747 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -201,12 +201,12 @@ system.physmem.bytesPerActivate::768-895 2 2.11% 93.68% # By system.physmem.bytesPerActivate::896-1023 2 2.11% 95.79% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 4 4.21% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 95 # Bytes accessed per row activation -system.physmem.totQLat 6803250 # Total ticks spent queuing -system.physmem.totMemAccLat 14640750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 6799250 # Total ticks spent queuing +system.physmem.totMemAccLat 14636750 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 2090000 # Total ticks spent in databus transfers -system.physmem.avgQLat 16275.72 # Average queueing delay per DRAM burst +system.physmem.avgQLat 16266.15 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 35025.72 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 35016.15 # Average memory access latency per DRAM burst system.physmem.avgRdBW 1190.75 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 1190.75 # Average system read bandwidth in MiByte/s @@ -247,9 +247,9 @@ system.physmem_1.preEnergy 235290 # En system.physmem_1.readEnergy 1570800 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 1229280.000000 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 2963430 # Energy for active background per rank (pJ) +system.physmem_1.actBackEnergy 2962290 # Energy for active background per rank (pJ) system.physmem_1.preBackEnergy 82560 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 7182000 # Energy for active power-down per rank (pJ) +system.physmem_1.actPowerDownEnergy 7183140 # Energy for active power-down per rank (pJ) system.physmem_1.prePowerDownEnergy 1440 # Energy for precharge power-down per rank (pJ) system.physmem_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) system.physmem_1.totalEnergy 13750320 # Total energy per rank (pJ) @@ -354,13 +354,13 @@ system.cpu.iq.iqSquashedOperandsExamined 16553 # Nu system.cpu.iq.iqSquashedNonSpecRemoved 11 # Number of squashed non-spec instructions that were removed system.cpu.iq.issued_per_cycle::samples 24836 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::mean 0.729264 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.710819 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.710701 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 19691 79.28% 79.28% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1200 4.83% 84.12% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 866 3.49% 87.60% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 19689 79.28% 79.28% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1202 4.84% 84.12% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 867 3.49% 87.61% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::3 575 2.32% 89.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 815 3.28% 93.20% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 814 3.28% 93.20% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::5 575 2.32% 95.51% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 614 2.47% 97.99% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 364 1.47% 99.45% # Number of insts issued each cycle @@ -493,20 +493,20 @@ system.cpu.iew.exec_stores 1259 # Nu system.cpu.iew.exec_rate 0.379178 # Inst execution rate system.cpu.iew.wb_sent 16737 # cumulative count of insts sent to commit system.cpu.iew.wb_count 16422 # cumulative count of insts written-back -system.cpu.iew.wb_producers 11019 # num instructions producing a value -system.cpu.iew.wb_consumers 17148 # num instructions consuming a value +system.cpu.iew.wb_producers 11018 # num instructions producing a value +system.cpu.iew.wb_consumers 17146 # num instructions consuming a value system.cpu.iew.wb_rate 0.365469 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.642582 # average fanout of values written-back +system.cpu.iew.wb_fanout 0.642599 # average fanout of values written-back system.cpu.commit.commitSquashedInsts 12050 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 12 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 648 # The number of times a branch was mispredicted system.cpu.commit.committed_per_cycle::samples 22793 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::mean 0.427631 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.307645 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.307612 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 19538 85.72% 85.72% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1001 4.39% 90.11% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 566 2.48% 92.59% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 19537 85.71% 85.71% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1003 4.40% 90.12% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 565 2.48% 92.59% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::3 727 3.19% 95.78% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::4 384 1.68% 97.47% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::5 133 0.58% 98.05% # Number of insts commited each cycle @@ -586,12 +586,12 @@ system.cpu.misc_regfile_reads 7640 # nu system.cpu.misc_regfile_writes 1 # number of misc regfile writes system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 22466500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 81.537714 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 81.537314 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 2520 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 141 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 17.872340 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 81.537714 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 81.537314 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.019907 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.019907 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 141 # Occupied blocks per task id @@ -617,14 +617,14 @@ system.cpu.dcache.demand_misses::cpu.data 193 # n system.cpu.dcache.demand_misses::total 193 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 193 # number of overall misses system.cpu.dcache.overall_misses::total 193 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 10226000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 10226000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 7070500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 7070500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 17296500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 17296500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 17296500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 17296500 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 10224000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 10224000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 7069500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 7069500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 17293500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 17293500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 17293500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 17293500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 1778 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1778 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 935 # number of WriteReq accesses(hits+misses) @@ -641,14 +641,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.071139 system.cpu.dcache.demand_miss_rate::total 0.071139 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.071139 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.071139 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 87401.709402 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 87401.709402 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 93032.894737 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 93032.894737 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 89619.170984 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 89619.170984 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 89619.170984 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 89619.170984 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 87384.615385 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 87384.615385 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 93019.736842 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 93019.736842 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 89603.626943 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 89603.626943 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 89603.626943 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 89603.626943 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 132 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked @@ -669,14 +669,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 141 system.cpu.dcache.demand_mshr_misses::total 141 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 141 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 141 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6448000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 6448000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6994500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 6994500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13442500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 13442500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13442500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 13442500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6446000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 6446000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6993500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 6993500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13439500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 13439500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13439500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 13439500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.036558 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.036558 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.081283 # mshr miss rate for WriteReq accesses @@ -685,24 +685,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.051972 system.cpu.dcache.demand_mshr_miss_rate::total 0.051972 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.051972 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.051972 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 99200 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 99200 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 92032.894737 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 92032.894737 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 95336.879433 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 95336.879433 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 95336.879433 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 95336.879433 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 99169.230769 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 99169.230769 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 92019.736842 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 92019.736842 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 95315.602837 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 95315.602837 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 95315.602837 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 95315.602837 # average overall mshr miss latency system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 22466500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 130.260906 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 130.259615 # Cycle average of tags in use system.cpu.icache.tags.total_refs 1641 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 278 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 5.902878 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 130.260906 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.063604 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.063604 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 130.259615 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.063603 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.063603 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 278 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 140 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 138 # Occupied blocks per task id @@ -722,12 +722,12 @@ system.cpu.icache.demand_misses::cpu.inst 385 # n system.cpu.icache.demand_misses::total 385 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 385 # number of overall misses system.cpu.icache.overall_misses::total 385 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 30146000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 30146000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 30146000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 30146000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 30146000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 30146000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 30145000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 30145000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 30145000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 30145000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 30145000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 30145000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 2026 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 2026 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 2026 # number of demand (read+write) accesses @@ -740,12 +740,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.190030 system.cpu.icache.demand_miss_rate::total 0.190030 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.190030 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.190030 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 78301.298701 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 78301.298701 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 78301.298701 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 78301.298701 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 78301.298701 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 78301.298701 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 78298.701299 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 78298.701299 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 78298.701299 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 78298.701299 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 78298.701299 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 78298.701299 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 171 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 3 # number of cycles access was blocked @@ -764,33 +764,33 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 278 system.cpu.icache.demand_mshr_misses::total 278 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 278 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 278 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23206500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 23206500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23206500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 23206500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23206500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 23206500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23205500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 23205500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23205500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 23205500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23205500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 23205500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.137216 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.137216 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.137216 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.137216 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.137216 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.137216 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 83476.618705 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 83476.618705 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 83476.618705 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 83476.618705 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 83476.618705 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 83476.618705 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 83473.021583 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 83473.021583 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 83473.021583 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 83473.021583 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 83473.021583 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 83473.021583 # average overall mshr miss latency system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 22466500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 211.897546 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 211.895854 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 418 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.002392 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 130.293933 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 81.603612 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 130.292642 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 81.603212 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003976 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.002490 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.006467 # Average percentage of cache occupancy @@ -819,18 +819,18 @@ system.cpu.l2cache.demand_misses::total 418 # nu system.cpu.l2cache.overall_misses::cpu.inst 277 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 141 # number of overall misses system.cpu.l2cache.overall_misses::total 418 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6880500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 6880500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 22777500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 22777500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 6350000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 6350000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 22777500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 13230500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 36008000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 22777500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 13230500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 36008000 # number of overall miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6879500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 6879500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 22776500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 22776500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 6348000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 6348000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 22776500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 13227500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 36004000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 22776500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 13227500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 36004000 # number of overall miss cycles system.cpu.l2cache.ReadExReq_accesses::cpu.data 76 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 76 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 278 # number of ReadCleanReq accesses(hits+misses) @@ -855,18 +855,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.997613 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996403 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.997613 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 90532.894737 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 90532.894737 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 82229.241877 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 82229.241877 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 97692.307692 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 97692.307692 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82229.241877 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 93833.333333 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 86143.540670 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82229.241877 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 93833.333333 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 86143.540670 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 90519.736842 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 90519.736842 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 82225.631769 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 82225.631769 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 97661.538462 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 97661.538462 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82225.631769 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 93812.056738 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 86133.971292 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82225.631769 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 93812.056738 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 86133.971292 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -885,18 +885,18 @@ system.cpu.l2cache.demand_mshr_misses::total 418 system.cpu.l2cache.overall_mshr_misses::cpu.inst 277 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 141 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 418 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6120500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6120500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 20007500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 20007500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 5700000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 5700000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 20007500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11820500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 31828000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 20007500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11820500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 31828000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6119500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6119500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 20006500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 20006500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 5698000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 5698000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 20006500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11817500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 31824000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 20006500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11817500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 31824000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.996403 # mshr miss rate for ReadCleanReq accesses @@ -909,18 +909,18 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.997613 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996403 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.997613 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 80532.894737 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 80532.894737 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72229.241877 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72229.241877 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 87692.307692 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 87692.307692 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72229.241877 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 83833.333333 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 76143.540670 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72229.241877 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 83833.333333 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 76143.540670 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 80519.736842 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 80519.736842 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72225.631769 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72225.631769 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 87661.538462 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 87661.538462 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72225.631769 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 83812.056738 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 76133.971292 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72225.631769 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 83812.056738 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 76133.971292 # average overall mshr miss latency system.cpu.toL2Bus.snoop_filter.tot_requests 419 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 1 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. diff --git a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/config.ini b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/config.ini index 965e2a045..f716f7509 100644 --- a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/config.ini +++ b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/config.ini @@ -177,10 +177,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=false max_miss_count=0 mshrs=4 @@ -194,6 +194,7 @@ response_latency=2 sequential_access=false size=262144 system=system +tag_latency=2 tags=system.cpu.dcache.tags tgts_per_mshr=20 write_buffers=8 @@ -206,15 +207,16 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=262144 +tag_latency=2 [system.cpu.dtb] type=AlphaTLB @@ -292,10 +294,10 @@ pipelined=true [system.cpu.fuPool.FUList3] type=FUDesc -children=opList0 opList1 opList2 +children=opList0 opList1 opList2 opList3 opList4 count=2 eventq_index=0 -opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 +opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 system.cpu.fuPool.FUList3.opList3 system.cpu.fuPool.FUList3.opList4 [system.cpu.fuPool.FUList3.opList0] type=OpDesc @@ -307,11 +309,25 @@ pipelined=true [system.cpu.fuPool.FUList3.opList1] type=OpDesc eventq_index=0 +opClass=FloatMultAcc +opLat=5 +pipelined=true + +[system.cpu.fuPool.FUList3.opList2] +type=OpDesc +eventq_index=0 +opClass=FloatMisc +opLat=3 +pipelined=true + +[system.cpu.fuPool.FUList3.opList3] +type=OpDesc +eventq_index=0 opClass=FloatDiv opLat=12 pipelined=false -[system.cpu.fuPool.FUList3.opList2] +[system.cpu.fuPool.FUList3.opList4] type=OpDesc eventq_index=0 opClass=FloatSqrt @@ -320,18 +336,25 @@ pipelined=false [system.cpu.fuPool.FUList4] type=FUDesc -children=opList +children=opList0 opList1 count=0 eventq_index=0 -opList=system.cpu.fuPool.FUList4.opList +opList=system.cpu.fuPool.FUList4.opList0 system.cpu.fuPool.FUList4.opList1 -[system.cpu.fuPool.FUList4.opList] +[system.cpu.fuPool.FUList4.opList0] type=OpDesc eventq_index=0 opClass=MemRead opLat=1 pipelined=true +[system.cpu.fuPool.FUList4.opList1] +type=OpDesc +eventq_index=0 +opClass=FloatMemRead +opLat=1 +pipelined=true + [system.cpu.fuPool.FUList5] type=FUDesc children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 @@ -481,24 +504,31 @@ pipelined=true [system.cpu.fuPool.FUList6] type=FUDesc -children=opList +children=opList0 opList1 count=0 eventq_index=0 -opList=system.cpu.fuPool.FUList6.opList +opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1 -[system.cpu.fuPool.FUList6.opList] +[system.cpu.fuPool.FUList6.opList0] type=OpDesc eventq_index=0 opClass=MemWrite opLat=1 pipelined=true +[system.cpu.fuPool.FUList6.opList1] +type=OpDesc +eventq_index=0 +opClass=FloatMemWrite +opLat=1 +pipelined=true + [system.cpu.fuPool.FUList7] type=FUDesc -children=opList0 opList1 +children=opList0 opList1 opList2 opList3 count=4 eventq_index=0 -opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 +opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 system.cpu.fuPool.FUList7.opList2 system.cpu.fuPool.FUList7.opList3 [system.cpu.fuPool.FUList7.opList0] type=OpDesc @@ -514,6 +544,20 @@ opClass=MemWrite opLat=1 pipelined=true +[system.cpu.fuPool.FUList7.opList2] +type=OpDesc +eventq_index=0 +opClass=FloatMemRead +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList7.opList3] +type=OpDesc +eventq_index=0 +opClass=FloatMemWrite +opLat=1 +pipelined=true + [system.cpu.fuPool.FUList8] type=FUDesc children=opList @@ -535,10 +579,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=true max_miss_count=0 mshrs=4 @@ -552,6 +596,7 @@ response_latency=2 sequential_access=false size=131072 system=system +tag_latency=2 tags=system.cpu.icache.tags tgts_per_mshr=20 write_buffers=8 @@ -564,15 +609,16 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=131072 +tag_latency=2 [system.cpu.interrupts0] type=AlphaInterrupts @@ -604,10 +650,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0 assoc=8 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=20 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=20 is_read_only=false max_miss_count=0 mshrs=20 @@ -621,6 +667,7 @@ response_latency=20 sequential_access=false size=2097152 system=system +tag_latency=20 tags=system.cpu.l2cache.tags tgts_per_mshr=12 write_buffers=8 @@ -633,15 +680,16 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=20 default_p_state=UNDEFINED eventq_index=0 -hit_latency=20 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=2097152 +tag_latency=20 [system.cpu.toL2Bus] type=CoherentXBar @@ -686,7 +734,7 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/test-progs/hello/bin/alpha/linux/hello +executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello gid=100 input=cin kvmInSE=false @@ -709,7 +757,7 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/test-progs/hello/bin/alpha/linux/hello +executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello gid=100 input=cin kvmInSE=false diff --git a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/simout b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/simout index 237d01682..c8d7343f8 100755 --- a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/simout +++ b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/simout @@ -3,10 +3,10 @@ Redirecting stderr to build/ALPHA/tests/opt/quick/se/01.hello-2T-smt/alpha/linux gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Oct 11 2016 00:00:58 -gem5 started Oct 13 2016 20:19:48 -gem5 executing on e108600-lin, pid 28095 -command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/01.hello-2T-smt/alpha/linux/o3-timing-mt -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/01.hello-2T-smt/alpha/linux/o3-timing-mt +gem5 compiled Nov 29 2016 18:06:09 +gem5 started Nov 29 2016 18:06:32 +gem5 executing on zizzer, pid 27586 +command line: /z/powerjg/gem5-upstream/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/01.hello-2T-smt/alpha/linux/o3-timing-mt -re /z/powerjg/gem5-upstream/tests/testing/../run.py quick/se/01.hello-2T-smt/alpha/linux/o3-timing-mt Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/stats.txt b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/stats.txt index b7214d7d7..9b1a7b7c9 100644 --- a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/stats.txt +++ b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000027 # Nu sim_ticks 26661500 # Number of ticks simulated final_tick 26661500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 139098 # Simulator instruction rate (inst/s) -host_op_rate 139080 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 290337480 # Simulator tick rate (ticks/s) -host_mem_usage 255644 # Number of bytes of host memory used -host_seconds 0.09 # Real time elapsed on the host +host_inst_rate 29979 # Simulator instruction rate (inst/s) +host_op_rate 29977 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 62584510 # Simulator tick rate (ticks/s) +host_mem_usage 237004 # Number of bytes of host memory used +host_seconds 0.43 # Real time elapsed on the host sim_insts 12770 # Number of instructions simulated sim_ops 12770 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -201,12 +201,12 @@ system.physmem.bytesPerActivate::768-895 9 4.46% 91.58% # By system.physmem.bytesPerActivate::896-1023 3 1.49% 93.07% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 14 6.93% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 202 # Bytes accessed per row activation -system.physmem.totQLat 15942250 # Total ticks spent queuing -system.physmem.totMemAccLat 34092250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 15941250 # Total ticks spent queuing +system.physmem.totMemAccLat 34091250 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 4840000 # Total ticks spent in databus transfers -system.physmem.avgQLat 16469.27 # Average queueing delay per DRAM burst +system.physmem.avgQLat 16468.23 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 35219.27 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 35218.23 # Average memory access latency per DRAM burst system.physmem.avgRdBW 2323.65 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 2323.65 # Average system read bandwidth in MiByte/s @@ -228,9 +228,9 @@ system.physmem_0.preEnergy 436425 # En system.physmem_0.readEnergy 4191180 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 1843920.000000 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 6127500 # Energy for active background per rank (pJ) +system.physmem_0.actBackEnergy 6126930 # Energy for active background per rank (pJ) system.physmem_0.preBackEnergy 47520 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 5972460 # Energy for active power-down per rank (pJ) +system.physmem_0.actPowerDownEnergy 5973030 # Energy for active power-down per rank (pJ) system.physmem_0.prePowerDownEnergy 1440 # Energy for precharge power-down per rank (pJ) system.physmem_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) system.physmem_0.totalEnergy 19470105 # Total energy per rank (pJ) @@ -247,9 +247,9 @@ system.physmem_1.preEnergy 330165 # En system.physmem_1.readEnergy 2720340 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 1843920.000000 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 4612440 # Energy for active background per rank (pJ) +system.physmem_1.actBackEnergy 4611870 # Energy for active background per rank (pJ) system.physmem_1.preBackEnergy 162240 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 6908970 # Energy for active power-down per rank (pJ) +system.physmem_1.actPowerDownEnergy 6909540 # Energy for active power-down per rank (pJ) system.physmem_1.prePowerDownEnergy 373920 # Energy for precharge power-down per rank (pJ) system.physmem_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) system.physmem_1.totalEnergy 17623155 # Total energy per rank (pJ) @@ -280,18 +280,18 @@ system.cpu.dtb.fetch_hits 0 # IT system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 4130 # DTB read hits +system.cpu.dtb.read_hits 4131 # DTB read hits system.cpu.dtb.read_misses 76 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 4206 # DTB read accesses +system.cpu.dtb.read_accesses 4207 # DTB read accesses system.cpu.dtb.write_hits 2011 # DTB write hits system.cpu.dtb.write_misses 48 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations system.cpu.dtb.write_accesses 2059 # DTB write accesses -system.cpu.dtb.data_hits 6141 # DTB hits +system.cpu.dtb.data_hits 6142 # DTB hits system.cpu.dtb.data_misses 124 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 6265 # DTB accesses +system.cpu.dtb.data_accesses 6266 # DTB accesses system.cpu.itb.fetch_hits 3836 # ITB hits system.cpu.itb.fetch_misses 50 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv @@ -323,14 +323,14 @@ system.cpu.fetch.SquashCycles 875 # Nu system.cpu.fetch.MiscStallCycles 344 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.CacheLines 3836 # Number of cache lines fetched system.cpu.fetch.IcacheSquashes 566 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 26300 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.059658 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.449516 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::samples 26305 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.059456 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.449327 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 21275 80.89% 80.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 21280 80.90% 80.90% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::1 504 1.92% 82.81% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::2 391 1.49% 84.30% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 446 1.70% 85.99% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 446 1.70% 86.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::4 478 1.82% 87.81% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::5 367 1.40% 89.21% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::6 469 1.78% 90.99% # Number of instructions fetched each cycle (Total) @@ -339,28 +339,28 @@ system.cpu.fetch.rateDist::8 2094 7.96% 100.00% # Nu system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 26300 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 26305 # Number of instructions fetched each cycle (Total) system.cpu.fetch.branchRate 0.091216 # Number of branch fetches per cycle system.cpu.fetch.rate 0.522635 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 36528 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 10375 # Number of cycles decode is blocked +system.cpu.decode.IdleCycles 36539 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 10373 # Number of cycles decode is blocked system.cpu.decode.RunCycles 3958 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 495 # Number of cycles decode is unblocking +system.cpu.decode.UnblockCycles 496 # Number of cycles decode is unblocking system.cpu.decode.SquashCycles 725 # Number of cycles decode is squashing system.cpu.decode.BranchResolved 405 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 151 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 24583 # Number of instructions handled by decode +system.cpu.decode.DecodedInsts 24588 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 377 # Number of squashed instructions handled by decode system.cpu.rename.SquashCycles 725 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 36872 # Number of cycles rename is idle +system.cpu.rename.IdleCycles 36883 # Number of cycles rename is idle system.cpu.rename.BlockCycles 3499 # Number of cycles rename is blocking system.cpu.rename.serializeStallCycles 1435 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 4116 # Number of cycles rename is running +system.cpu.rename.RunCycles 4115 # Number of cycles rename is running system.cpu.rename.UnblockCycles 5434 # Number of cycles rename is unblocking system.cpu.rename.RenamedInsts 23584 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 36 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 223 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 328 # Number of times rename has blocked due to LQ full +system.cpu.rename.IQFullEvents 222 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 329 # Number of times rename has blocked due to LQ full system.cpu.rename.SQFullEvents 4703 # Number of times rename has blocked due to SQ full system.cpu.rename.RenamedOperands 17574 # Number of destination operands rename has renamed system.cpu.rename.RenameLookups 29532 # Number of register rename lookups that rename has made @@ -370,7 +370,7 @@ system.cpu.rename.CommittedMaps 9154 # Nu system.cpu.rename.UndoneMaps 8420 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 57 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 45 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 1621 # count of insts added to the skid buffer +system.cpu.rename.skidInsts 1617 # count of insts added to the skid buffer system.cpu.memDep0.insertedLoads 1925 # Number of loads inserted to the mem dependence unit. system.cpu.memDep0.insertedStores 1093 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 7 # Number of conflicting loads. @@ -381,105 +381,105 @@ system.cpu.memDep1.conflictingLoads 15 # Nu system.cpu.memDep1.conflictingStores 4 # Number of conflicting stores. system.cpu.iq.iqInstsAdded 21800 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 51 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 19296 # Number of instructions issued +system.cpu.iq.iqInstsIssued 19298 # Number of instructions issued system.cpu.iq.iqSquashedInstsIssued 51 # Number of squashed instructions issued system.cpu.iq.iqSquashedInstsExamined 9080 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 4753 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedOperandsExamined 4750 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 17 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 26300 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.733688 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.450617 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 26305 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.733625 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.450843 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 18970 72.13% 72.13% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 2362 8.98% 81.11% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 1626 6.18% 87.29% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 1294 4.92% 92.21% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 1061 4.03% 96.25% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 563 2.14% 98.39% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 18975 72.13% 72.13% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 2364 8.99% 81.12% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 1624 6.17% 87.30% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 1293 4.92% 92.21% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 1059 4.03% 96.24% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 566 2.15% 98.39% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 282 1.07% 99.46% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 87 0.33% 99.79% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 55 0.21% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 26300 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 26305 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 29 9.67% 9.67% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 9.67% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 9.67% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 9.67% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 9.67% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 9.67% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 9.67% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 9.67% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 9.67% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMisc 0 0.00% 9.67% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 9.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 9.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 9.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 9.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 9.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 9.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 9.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 9.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 9.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 9.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 9.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 9.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 9.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 9.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 9.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 9.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 9.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 9.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 9.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.67% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 191 63.67% 73.33% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 77 25.67% 99.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemRead 0 0.00% 99.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemWrite 3 1.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 29 9.60% 9.60% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 9.60% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 9.60% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 9.60% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 9.60% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 9.60% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 9.60% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 9.60% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 9.60% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 0 0.00% 9.60% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 9.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 9.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 9.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 9.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 9.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 9.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 9.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 9.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 9.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 9.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 9.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 9.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 9.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 9.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 9.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 9.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 9.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 9.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 9.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.60% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 193 63.91% 73.51% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 77 25.50% 99.01% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemRead 0 0.00% 99.01% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemWrite 3 0.99% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 5884 66.04% 66.06% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 1 0.01% 66.07% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 66.07% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 66.09% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.09% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.09% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.09% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 66.09% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.09% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 66.09% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.09% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 5886 66.05% 66.07% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 1 0.01% 66.08% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 66.08% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 66.10% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.10% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.10% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.10% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 66.10% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.10% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 66.10% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.10% # Type of FU issued system.cpu.iq.FU_type_0::MemRead 2014 22.60% 88.70% # Type of FU issued system.cpu.iq.FU_type_0::MemWrite 999 11.21% 99.91% # Type of FU issued system.cpu.iq.FU_type_0::FloatMemRead 1 0.01% 99.92% # Type of FU issued system.cpu.iq.FU_type_0::FloatMemWrite 7 0.08% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 8910 # Type of FU issued +system.cpu.iq.FU_type_0::total 8912 # Type of FU issued system.cpu.iq.FU_type_1::No_OpClass 2 0.02% 0.02% # Type of FU issued system.cpu.iq.FU_type_1::IntAlu 6849 65.94% 65.96% # Type of FU issued system.cpu.iq.FU_type_1::IntMult 1 0.01% 65.97% # Type of FU issued @@ -519,21 +519,21 @@ system.cpu.iq.FU_type_1::FloatMemWrite 7 0.07% 100.00% # Ty system.cpu.iq.FU_type_1::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_1::InstPrefetch 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_1::total 10386 # Type of FU issued -system.cpu.iq.FU_type::total 19296 0.00% 0.00% # Type of FU issued -system.cpu.iq.rate 0.361863 # Inst issue rate -system.cpu.iq.fu_busy_cnt::0 152 # FU busy when requested +system.cpu.iq.FU_type::total 19298 0.00% 0.00% # Type of FU issued +system.cpu.iq.rate 0.361901 # Inst issue rate +system.cpu.iq.fu_busy_cnt::0 154 # FU busy when requested system.cpu.iq.fu_busy_cnt::1 148 # FU busy when requested -system.cpu.iq.fu_busy_cnt::total 300 # FU busy when requested -system.cpu.iq.fu_busy_rate::0 0.007877 # FU busy rate (busy events/executed inst) -system.cpu.iq.fu_busy_rate::1 0.007670 # FU busy rate (busy events/executed inst) -system.cpu.iq.fu_busy_rate::total 0.015547 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 65200 # Number of integer instruction queue reads +system.cpu.iq.fu_busy_cnt::total 302 # FU busy when requested +system.cpu.iq.fu_busy_rate::0 0.007980 # FU busy rate (busy events/executed inst) +system.cpu.iq.fu_busy_rate::1 0.007669 # FU busy rate (busy events/executed inst) +system.cpu.iq.fu_busy_rate::total 0.015649 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 65211 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_writes 30942 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 17504 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_wakeup_accesses 17509 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 43 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 20 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 20 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 19569 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 19573 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 23 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 39 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address @@ -570,65 +570,65 @@ system.cpu.iew.memOrderViolationEvents 32 # Nu system.cpu.iew.predictedTakenIncorrect 134 # Number of branches that were predicted taken incorrectly system.cpu.iew.predictedNotTakenIncorrect 638 # Number of branches that were predicted not taken incorrectly system.cpu.iew.branchMispredicts 772 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 18585 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts::0 1945 # Number of load instructions executed +system.cpu.iew.iewExecutedInsts 18590 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts::0 1946 # Number of load instructions executed system.cpu.iew.iewExecLoadInsts::1 2264 # Number of load instructions executed -system.cpu.iew.iewExecLoadInsts::total 4209 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 711 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecLoadInsts::total 4210 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 708 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp::0 0 # number of swp insts executed system.cpu.iew.exec_swp::1 0 # number of swp insts executed system.cpu.iew.exec_swp::total 0 # number of swp insts executed system.cpu.iew.exec_nop::0 63 # number of nop insts executed system.cpu.iew.exec_nop::1 71 # number of nop insts executed system.cpu.iew.exec_nop::total 134 # number of nop insts executed -system.cpu.iew.exec_refs::0 2942 # number of memory reference insts executed +system.cpu.iew.exec_refs::0 2943 # number of memory reference insts executed system.cpu.iew.exec_refs::1 3338 # number of memory reference insts executed -system.cpu.iew.exec_refs::total 6280 # number of memory reference insts executed +system.cpu.iew.exec_refs::total 6281 # number of memory reference insts executed system.cpu.iew.exec_branches::0 1393 # Number of branches executed system.cpu.iew.exec_branches::1 1580 # Number of branches executed system.cpu.iew.exec_branches::total 2973 # Number of branches executed system.cpu.iew.exec_stores::0 997 # Number of stores executed system.cpu.iew.exec_stores::1 1074 # Number of stores executed system.cpu.iew.exec_stores::total 2071 # Number of stores executed -system.cpu.iew.exec_rate 0.348530 # Inst execution rate -system.cpu.iew.wb_sent::0 8281 # cumulative count of insts sent to commit +system.cpu.iew.exec_rate 0.348624 # Inst execution rate +system.cpu.iew.wb_sent::0 8287 # cumulative count of insts sent to commit system.cpu.iew.wb_sent::1 9496 # cumulative count of insts sent to commit -system.cpu.iew.wb_sent::total 17777 # cumulative count of insts sent to commit -system.cpu.iew.wb_count::0 8197 # cumulative count of insts written-back +system.cpu.iew.wb_sent::total 17783 # cumulative count of insts sent to commit +system.cpu.iew.wb_count::0 8202 # cumulative count of insts written-back system.cpu.iew.wb_count::1 9327 # cumulative count of insts written-back -system.cpu.iew.wb_count::total 17524 # cumulative count of insts written-back -system.cpu.iew.wb_producers::0 4340 # num instructions producing a value -system.cpu.iew.wb_producers::1 4919 # num instructions producing a value -system.cpu.iew.wb_producers::total 9259 # num instructions producing a value -system.cpu.iew.wb_consumers::0 5879 # num instructions consuming a value -system.cpu.iew.wb_consumers::1 6619 # num instructions consuming a value -system.cpu.iew.wb_consumers::total 12498 # num instructions consuming a value -system.cpu.iew.wb_rate::0 0.153721 # insts written-back per cycle +system.cpu.iew.wb_count::total 17529 # cumulative count of insts written-back +system.cpu.iew.wb_producers::0 4343 # num instructions producing a value +system.cpu.iew.wb_producers::1 4920 # num instructions producing a value +system.cpu.iew.wb_producers::total 9263 # num instructions producing a value +system.cpu.iew.wb_consumers::0 5887 # num instructions consuming a value +system.cpu.iew.wb_consumers::1 6620 # num instructions consuming a value +system.cpu.iew.wb_consumers::total 12507 # num instructions consuming a value +system.cpu.iew.wb_rate::0 0.153814 # insts written-back per cycle system.cpu.iew.wb_rate::1 0.174912 # insts written-back per cycle -system.cpu.iew.wb_rate::total 0.328633 # insts written-back per cycle -system.cpu.iew.wb_fanout::0 0.738221 # average fanout of values written-back -system.cpu.iew.wb_fanout::1 0.743164 # average fanout of values written-back -system.cpu.iew.wb_fanout::total 0.740839 # average fanout of values written-back +system.cpu.iew.wb_rate::total 0.328726 # insts written-back per cycle +system.cpu.iew.wb_fanout::0 0.737727 # average fanout of values written-back +system.cpu.iew.wb_fanout::1 0.743202 # average fanout of values written-back +system.cpu.iew.wb_fanout::total 0.740625 # average fanout of values written-back system.cpu.commit.commitSquashedInsts 9130 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 34 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 646 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 26282 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.487178 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.404713 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 26287 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.487085 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.404867 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 21298 81.04% 81.04% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 2499 9.51% 90.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 21303 81.04% 81.04% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 2500 9.51% 90.55% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::2 926 3.52% 94.07% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 403 1.53% 95.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 402 1.53% 95.60% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::4 249 0.95% 96.55% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 154 0.59% 97.13% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 215 0.82% 97.95% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 154 0.59% 97.14% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 214 0.81% 97.95% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::7 116 0.44% 98.39% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 422 1.61% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 423 1.61% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 26282 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 26287 # Number of insts commited each cycle system.cpu.commit.committedInsts::0 6402 # Number of instructions committed system.cpu.commit.committedInsts::1 6402 # Number of instructions committed system.cpu.commit.committedInsts::total 12804 # Number of instructions committed @@ -738,11 +738,11 @@ system.cpu.commit.op_class_1::IprAccess 0 0.00% 100.00% # Cl system.cpu.commit.op_class_1::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_1::total 6402 # Class of committed instruction system.cpu.commit.op_class::total 12804 0.00% 0.00% # Class of committed instruction -system.cpu.commit.bw_lim_events 422 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 113054 # The number of ROB reads +system.cpu.commit.bw_lim_events 423 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 113065 # The number of ROB reads system.cpu.rob.rob_writes 45570 # The number of ROB writes system.cpu.timesIdled 413 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 27024 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.idleCycles 27019 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts::0 6385 # Number of Instructions Simulated system.cpu.committedInsts::1 6385 # Number of Instructions Simulated system.cpu.committedInsts::total 12770 # Number of Instructions Simulated @@ -755,8 +755,8 @@ system.cpu.cpi_total 4.175724 # CP system.cpu.ipc::0 0.119740 # IPC: Instructions Per Cycle system.cpu.ipc::1 0.119740 # IPC: Instructions Per Cycle system.cpu.ipc_total 0.239479 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 23475 # number of integer regfile reads -system.cpu.int_regfile_writes 13132 # number of integer regfile writes +system.cpu.int_regfile_reads 23483 # number of integer regfile reads +system.cpu.int_regfile_writes 13138 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads system.cpu.fp_regfile_writes 4 # number of floating regfile writes system.cpu.misc_regfile_reads 2 # number of misc regfile reads @@ -765,29 +765,29 @@ system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 26661500 system.cpu.dcache.tags.replacements::0 0 # number of replacements system.cpu.dcache.tags.replacements::1 0 # number of replacements system.cpu.dcache.tags.replacements::total 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 216.020971 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 4236 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 216.020896 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 4237 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 342 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 12.385965 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 12.388889 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 216.020971 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 216.020896 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.052739 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.052739 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 342 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 72 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 270 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.083496 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 10868 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 10868 # Number of data accesses +system.cpu.dcache.tags.tag_accesses 10870 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 10870 # Number of data accesses system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 26661500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 3224 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 3224 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::cpu.data 3225 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 3225 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 1012 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 1012 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 4236 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 4236 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 4236 # number of overall hits -system.cpu.dcache.overall_hits::total 4236 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 4237 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 4237 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 4237 # number of overall hits +system.cpu.dcache.overall_hits::total 4237 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 309 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 309 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 718 # number of WriteReq misses @@ -804,22 +804,22 @@ system.cpu.dcache.demand_miss_latency::cpu.data 75346451 system.cpu.dcache.demand_miss_latency::total 75346451 # number of demand (read+write) miss cycles system.cpu.dcache.overall_miss_latency::cpu.data 75346451 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::total 75346451 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 3533 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 3533 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::cpu.data 3534 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 3534 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 1730 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 1730 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 5263 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 5263 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 5263 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 5263 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.087461 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.087461 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 5264 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 5264 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 5264 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 5264 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.087436 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.087436 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.415029 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.415029 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.195136 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.195136 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.195136 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.195136 # miss rate for overall accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.195099 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.195099 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.195099 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.195099 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 77721.682848 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 77721.682848 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 71490.878830 # average WriteReq miss latency @@ -858,14 +858,14 @@ system.cpu.dcache.demand_mshr_miss_latency::cpu.data 30306487 system.cpu.dcache.demand_mshr_miss_latency::total 30306487 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::cpu.data 30306487 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 30306487 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.056326 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.056326 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.056310 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.056310 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.083237 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.083237 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.065172 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.065172 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.065172 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.065172 # mshr miss rate for overall accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.065160 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.065160 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.065160 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.065160 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 89683.417085 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 89683.417085 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 86524.215278 # average WriteReq mshr miss latency @@ -878,12 +878,12 @@ system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 26661500 system.cpu.icache.tags.replacements::0 7 # number of replacements system.cpu.icache.tags.replacements::1 0 # number of replacements system.cpu.icache.tags.replacements::total 7 # number of replacements -system.cpu.icache.tags.tagsinuse 318.055053 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 318.054191 # Cycle average of tags in use system.cpu.icache.tags.total_refs 2937 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 628 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 4.676752 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 318.055053 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 318.054191 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.155300 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.155300 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 621 # Occupied blocks per task id @@ -905,12 +905,12 @@ system.cpu.icache.demand_misses::cpu.inst 895 # n system.cpu.icache.demand_misses::total 895 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 895 # number of overall misses system.cpu.icache.overall_misses::total 895 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 72806995 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 72806995 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 72806995 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 72806995 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 72806995 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 72806995 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 72804995 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 72804995 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 72804995 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 72804995 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 72804995 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 72804995 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 3832 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 3832 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 3832 # number of demand (read+write) accesses @@ -923,12 +923,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.233559 system.cpu.icache.demand_miss_rate::total 0.233559 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.233559 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.233559 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 81348.597765 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 81348.597765 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 81348.597765 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 81348.597765 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 81348.597765 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 81348.597765 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 81346.363128 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 81346.363128 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 81346.363128 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 81346.363128 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 81346.363128 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 81346.363128 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 3504 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 58 # number of cycles access was blocked @@ -949,35 +949,35 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 628 system.cpu.icache.demand_mshr_misses::total 628 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 628 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 628 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 54757996 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 54757996 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 54757996 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 54757996 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 54757996 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 54757996 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 54756996 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 54756996 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 54756996 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 54756996 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 54756996 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 54756996 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.163883 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.163883 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.163883 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.163883 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.163883 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.163883 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 87194.261146 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 87194.261146 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 87194.261146 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 87194.261146 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 87194.261146 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 87194.261146 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 87192.668790 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 87192.668790 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 87192.668790 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 87192.668790 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 87192.668790 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 87192.668790 # average overall mshr miss latency system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 26661500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements::0 0 # number of replacements system.cpu.l2cache.tags.replacements::1 0 # number of replacements system.cpu.l2cache.tags.replacements::total 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 534.674828 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 534.673891 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 10 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 967 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.010341 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 318.519168 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 216.155660 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 318.518306 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 216.155585 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::cpu.inst 0.009720 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.006597 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.016317 # Average percentage of cache occupancy @@ -1010,16 +1010,16 @@ system.cpu.l2cache.overall_misses::cpu.data 343 # system.cpu.l2cache.overall_misses::total 968 # number of overall misses system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 12308500 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 12308500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 53778000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 53778000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 53777000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 53777000 # number of ReadCleanReq miss cycles system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 17466000 # number of ReadSharedReq miss cycles system.cpu.l2cache.ReadSharedReq_miss_latency::total 17466000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 53778000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 53777000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.data 29774500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 83552500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 53778000 # number of overall miss cycles +system.cpu.l2cache.demand_miss_latency::total 83551500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 53777000 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.data 29774500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 83552500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 83551500 # number of overall miss cycles system.cpu.l2cache.WritebackClean_accesses::writebacks 7 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::total 7 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 145 # number of ReadExReq accesses(hits+misses) @@ -1048,16 +1048,16 @@ system.cpu.l2cache.overall_miss_rate::cpu.data 1 system.cpu.l2cache.overall_miss_rate::total 0.996910 # miss rate for overall accesses system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 84886.206897 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 84886.206897 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 86044.800000 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 86044.800000 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 86043.200000 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 86043.200000 # average ReadCleanReq miss latency system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 88212.121212 # average ReadSharedReq miss latency system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 88212.121212 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 86044.800000 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 86043.200000 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 86806.122449 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 86314.566116 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 86044.800000 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 86313.533058 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 86043.200000 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 86806.122449 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 86314.566116 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 86313.533058 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1078,16 +1078,16 @@ system.cpu.l2cache.overall_mshr_misses::cpu.data 343 system.cpu.l2cache.overall_mshr_misses::total 968 # number of overall MSHR misses system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 10858500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 10858500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 47528000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 47528000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 47527000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 47527000 # number of ReadCleanReq MSHR miss cycles system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 15496000 # number of ReadSharedReq MSHR miss cycles system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 15496000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 47528000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 47527000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 26354500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 73882500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 47528000 # number of overall MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 73881500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 47527000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 26354500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 73882500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 73881500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.995223 # mshr miss rate for ReadCleanReq accesses @@ -1102,16 +1102,16 @@ system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 system.cpu.l2cache.overall_mshr_miss_rate::total 0.996910 # mshr miss rate for overall accesses system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 74886.206897 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 74886.206897 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 76044.800000 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 76044.800000 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 76043.200000 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 76043.200000 # average ReadCleanReq mshr miss latency system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 78262.626263 # average ReadSharedReq mshr miss latency system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 78262.626263 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 76044.800000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 76043.200000 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 76835.276968 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 76324.896694 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 76044.800000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 76323.863636 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 76043.200000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 76835.276968 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 76324.896694 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 76323.863636 # average overall mshr miss latency system.cpu.toL2Bus.snoop_filter.tot_requests 978 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 9 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/minor-timing/config.ini b/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/minor-timing/config.ini new file mode 100644 index 000000000..ccd0e2b58 --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/minor-timing/config.ini @@ -0,0 +1,902 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain +boot_osflags=a +cache_line_size=64 +clk_domain=system.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +exit_on_work_items=false +init_param=0 +kernel= +kernel_addr_check=true +load_addr_mask=1099511627775 +load_offset=0 +mem_mode=timing +mem_ranges= +memories=system.physmem +mmap_using_noreserve=false +multi_thread=false +num_work_ids=16 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +readfile= +symbolfile= +thermal_components= +thermal_model=Null +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=MinorCPU +children=branchPred dcache dtb executeFuncUnits icache interrupts isa itb l2cache toL2Bus tracer workload +branchPred=system.cpu.branchPred +checker=Null +clk_domain=system.cpu_clk_domain +cpu_id=0 +decodeCycleInput=true +decodeInputBufferSize=3 +decodeInputWidth=2 +decodeToExecuteForwardDelay=1 +default_p_state=UNDEFINED +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +enableIdling=true +eventq_index=0 +executeAllowEarlyMemoryIssue=true +executeBranchDelay=1 +executeCommitLimit=2 +executeCycleInput=true +executeFuncUnits=system.cpu.executeFuncUnits +executeInputBufferSize=7 +executeInputWidth=2 +executeIssueLimit=2 +executeLSQMaxStoreBufferStoresPerCycle=2 +executeLSQRequestsQueueSize=1 +executeLSQStoreBufferSize=5 +executeLSQTransfersQueueSize=2 +executeMaxAccessesInMemory=2 +executeMemoryCommitLimit=1 +executeMemoryIssueLimit=1 +executeMemoryWidth=0 +executeSetTraceTimeOnCommit=true +executeSetTraceTimeOnIssue=false +fetch1FetchLimit=1 +fetch1LineSnapWidth=0 +fetch1LineWidth=0 +fetch1ToFetch2BackwardDelay=1 +fetch1ToFetch2ForwardDelay=1 +fetch2CycleInput=true +fetch2InputBufferSize=2 +fetch2ToDecodeForwardDelay=1 +function_trace=false +function_trace_start=0 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +profile=0 +progress_interval=0 +simpoint_start_insts= +socket_id=0 +switched_out=false +system=system +threadPolicy=RoundRobin +tracer=system.cpu.tracer +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.branchPred] +type=TournamentBP +BTBEntries=4096 +BTBTagSize=16 +RASSize=16 +choiceCtrBits=2 +choicePredictorSize=8192 +eventq_index=0 +globalCtrBits=2 +globalPredictorSize=8192 +indirectHashGHR=true +indirectHashTargets=true +indirectPathLength=3 +indirectSets=256 +indirectTagSize=16 +indirectWays=2 +instShiftAmt=2 +localCtrBits=2 +localHistoryTableSize=2048 +localPredictorSize=2048 +numThreads=1 +useIndirect=true + +[system.cpu.dcache] +type=Cache +children=tags +addr_ranges=0:18446744073709551615:0:0:0:0 +assoc=2 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +data_latency=2 +default_p_state=UNDEFINED +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=4 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=262144 +system=system +tag_latency=2 +tags=system.cpu.dcache.tags +tgts_per_mshr=20 +write_buffers=8 +writeback_clean=false +cpu_side=system.cpu.dcache_port +mem_side=system.cpu.toL2Bus.slave[1] + +[system.cpu.dcache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +data_latency=2 +default_p_state=UNDEFINED +eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +sequential_access=false +size=262144 +tag_latency=2 + +[system.cpu.dtb] +type=RiscvTLB +eventq_index=0 +size=64 + +[system.cpu.executeFuncUnits] +type=MinorFUPool +children=funcUnits0 funcUnits1 funcUnits2 funcUnits3 funcUnits4 funcUnits5 funcUnits6 +eventq_index=0 +funcUnits=system.cpu.executeFuncUnits.funcUnits0 system.cpu.executeFuncUnits.funcUnits1 system.cpu.executeFuncUnits.funcUnits2 system.cpu.executeFuncUnits.funcUnits3 system.cpu.executeFuncUnits.funcUnits4 system.cpu.executeFuncUnits.funcUnits5 system.cpu.executeFuncUnits.funcUnits6 + +[system.cpu.executeFuncUnits.funcUnits0] +type=MinorFU +children=opClasses timings +cantForwardFromFUIndices= +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses +opLat=3 +timings=system.cpu.executeFuncUnits.funcUnits0.timings + +[system.cpu.executeFuncUnits.funcUnits0.opClasses] +type=MinorOpClassSet +children=opClasses +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses + +[system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses] +type=MinorOpClass +eventq_index=0 +opClass=IntAlu + +[system.cpu.executeFuncUnits.funcUnits0.timings] +type=MinorFUTiming +children=opClasses +description=Int +eventq_index=0 +extraAssumedLat=0 +extraCommitLat=0 +extraCommitLatExpr=Null +mask=0 +match=0 +opClasses=system.cpu.executeFuncUnits.funcUnits0.timings.opClasses +srcRegsRelativeLats=2 +suppress=false + +[system.cpu.executeFuncUnits.funcUnits0.timings.opClasses] +type=MinorOpClassSet +eventq_index=0 +opClasses= + +[system.cpu.executeFuncUnits.funcUnits1] +type=MinorFU +children=opClasses timings +cantForwardFromFUIndices= +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses +opLat=3 +timings=system.cpu.executeFuncUnits.funcUnits1.timings + +[system.cpu.executeFuncUnits.funcUnits1.opClasses] +type=MinorOpClassSet +children=opClasses +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses + +[system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses] +type=MinorOpClass +eventq_index=0 +opClass=IntAlu + +[system.cpu.executeFuncUnits.funcUnits1.timings] +type=MinorFUTiming +children=opClasses +description=Int +eventq_index=0 +extraAssumedLat=0 +extraCommitLat=0 +extraCommitLatExpr=Null +mask=0 +match=0 +opClasses=system.cpu.executeFuncUnits.funcUnits1.timings.opClasses +srcRegsRelativeLats=2 +suppress=false + +[system.cpu.executeFuncUnits.funcUnits1.timings.opClasses] +type=MinorOpClassSet +eventq_index=0 +opClasses= + +[system.cpu.executeFuncUnits.funcUnits2] +type=MinorFU +children=opClasses timings +cantForwardFromFUIndices= +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits2.opClasses +opLat=3 +timings=system.cpu.executeFuncUnits.funcUnits2.timings + +[system.cpu.executeFuncUnits.funcUnits2.opClasses] +type=MinorOpClassSet +children=opClasses +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses + +[system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses] +type=MinorOpClass +eventq_index=0 +opClass=IntMult + +[system.cpu.executeFuncUnits.funcUnits2.timings] +type=MinorFUTiming +children=opClasses +description=Mul +eventq_index=0 +extraAssumedLat=0 +extraCommitLat=0 +extraCommitLatExpr=Null +mask=0 +match=0 +opClasses=system.cpu.executeFuncUnits.funcUnits2.timings.opClasses +srcRegsRelativeLats=0 +suppress=false + +[system.cpu.executeFuncUnits.funcUnits2.timings.opClasses] +type=MinorOpClassSet +eventq_index=0 +opClasses= + +[system.cpu.executeFuncUnits.funcUnits3] +type=MinorFU +children=opClasses +cantForwardFromFUIndices= +eventq_index=0 +issueLat=9 +opClasses=system.cpu.executeFuncUnits.funcUnits3.opClasses +opLat=9 +timings= + +[system.cpu.executeFuncUnits.funcUnits3.opClasses] +type=MinorOpClassSet +children=opClasses +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses + +[system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses] +type=MinorOpClass +eventq_index=0 +opClass=IntDiv + +[system.cpu.executeFuncUnits.funcUnits4] +type=MinorFU +children=opClasses timings +cantForwardFromFUIndices= +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses +opLat=6 +timings=system.cpu.executeFuncUnits.funcUnits4.timings + +[system.cpu.executeFuncUnits.funcUnits4.opClasses] +type=MinorOpClassSet +children=opClasses00 opClasses01 opClasses02 opClasses03 opClasses04 opClasses05 opClasses06 opClasses07 opClasses08 opClasses09 opClasses10 opClasses11 opClasses12 opClasses13 opClasses14 opClasses15 opClasses16 opClasses17 opClasses18 opClasses19 opClasses20 opClasses21 opClasses22 opClasses23 opClasses24 opClasses25 opClasses26 opClasses27 +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses26 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses27 + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00] +type=MinorOpClass +eventq_index=0 +opClass=FloatAdd + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01] +type=MinorOpClass +eventq_index=0 +opClass=FloatCmp + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02] +type=MinorOpClass +eventq_index=0 +opClass=FloatCvt + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03] +type=MinorOpClass +eventq_index=0 +opClass=FloatMisc + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04] +type=MinorOpClass +eventq_index=0 +opClass=FloatMult + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05] +type=MinorOpClass +eventq_index=0 +opClass=FloatMultAcc + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06] +type=MinorOpClass +eventq_index=0 +opClass=FloatDiv + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07] +type=MinorOpClass +eventq_index=0 +opClass=FloatSqrt + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08] +type=MinorOpClass +eventq_index=0 +opClass=SimdAdd + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09] +type=MinorOpClass +eventq_index=0 +opClass=SimdAddAcc + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10] +type=MinorOpClass +eventq_index=0 +opClass=SimdAlu + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11] +type=MinorOpClass +eventq_index=0 +opClass=SimdCmp + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12] +type=MinorOpClass +eventq_index=0 +opClass=SimdCvt + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13] +type=MinorOpClass +eventq_index=0 +opClass=SimdMisc + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14] +type=MinorOpClass +eventq_index=0 +opClass=SimdMult + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15] +type=MinorOpClass +eventq_index=0 +opClass=SimdMultAcc + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16] +type=MinorOpClass +eventq_index=0 +opClass=SimdShift + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17] +type=MinorOpClass +eventq_index=0 +opClass=SimdShiftAcc + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18] +type=MinorOpClass +eventq_index=0 +opClass=SimdSqrt + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatAdd + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatAlu + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatCmp + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatCvt + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatDiv + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatMisc + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatMult + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses26] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatMultAcc + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses27] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatSqrt + +[system.cpu.executeFuncUnits.funcUnits4.timings] +type=MinorFUTiming +children=opClasses +description=FloatSimd +eventq_index=0 +extraAssumedLat=0 +extraCommitLat=0 +extraCommitLatExpr=Null +mask=0 +match=0 +opClasses=system.cpu.executeFuncUnits.funcUnits4.timings.opClasses +srcRegsRelativeLats=2 +suppress=false + +[system.cpu.executeFuncUnits.funcUnits4.timings.opClasses] +type=MinorOpClassSet +eventq_index=0 +opClasses= + +[system.cpu.executeFuncUnits.funcUnits5] +type=MinorFU +children=opClasses timings +cantForwardFromFUIndices= +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses +opLat=1 +timings=system.cpu.executeFuncUnits.funcUnits5.timings + +[system.cpu.executeFuncUnits.funcUnits5.opClasses] +type=MinorOpClassSet +children=opClasses0 opClasses1 opClasses2 opClasses3 +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1 system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses2 system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses3 + +[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0] +type=MinorOpClass +eventq_index=0 +opClass=MemRead + +[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1] +type=MinorOpClass +eventq_index=0 +opClass=MemWrite + +[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses2] +type=MinorOpClass +eventq_index=0 +opClass=FloatMemRead + +[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses3] +type=MinorOpClass +eventq_index=0 +opClass=FloatMemWrite + +[system.cpu.executeFuncUnits.funcUnits5.timings] +type=MinorFUTiming +children=opClasses +description=Mem +eventq_index=0 +extraAssumedLat=2 +extraCommitLat=0 +extraCommitLatExpr=Null +mask=0 +match=0 +opClasses=system.cpu.executeFuncUnits.funcUnits5.timings.opClasses +srcRegsRelativeLats=1 +suppress=false + +[system.cpu.executeFuncUnits.funcUnits5.timings.opClasses] +type=MinorOpClassSet +eventq_index=0 +opClasses= + +[system.cpu.executeFuncUnits.funcUnits6] +type=MinorFU +children=opClasses +cantForwardFromFUIndices= +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses +opLat=1 +timings= + +[system.cpu.executeFuncUnits.funcUnits6.opClasses] +type=MinorOpClassSet +children=opClasses0 opClasses1 +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1 + +[system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0] +type=MinorOpClass +eventq_index=0 +opClass=IprAccess + +[system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1] +type=MinorOpClass +eventq_index=0 +opClass=InstPrefetch + +[system.cpu.icache] +type=Cache +children=tags +addr_ranges=0:18446744073709551615:0:0:0:0 +assoc=2 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +data_latency=2 +default_p_state=UNDEFINED +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=true +max_miss_count=0 +mshrs=4 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=131072 +system=system +tag_latency=2 +tags=system.cpu.icache.tags +tgts_per_mshr=20 +write_buffers=8 +writeback_clean=true +cpu_side=system.cpu.icache_port +mem_side=system.cpu.toL2Bus.slave[0] + +[system.cpu.icache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +data_latency=2 +default_p_state=UNDEFINED +eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +sequential_access=false +size=131072 +tag_latency=2 + +[system.cpu.interrupts] +type=RiscvInterrupts +eventq_index=0 + +[system.cpu.isa] +type=RiscvISA +eventq_index=0 + +[system.cpu.itb] +type=RiscvTLB +eventq_index=0 +size=64 + +[system.cpu.l2cache] +type=Cache +children=tags +addr_ranges=0:18446744073709551615:0:0:0:0 +assoc=8 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +data_latency=20 +default_p_state=UNDEFINED +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=20 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +prefetch_on_access=false +prefetcher=Null +response_latency=20 +sequential_access=false +size=2097152 +system=system +tag_latency=20 +tags=system.cpu.l2cache.tags +tgts_per_mshr=12 +write_buffers=8 +writeback_clean=false +cpu_side=system.cpu.toL2Bus.master[0] +mem_side=system.membus.slave[1] + +[system.cpu.l2cache.tags] +type=LRU +assoc=8 +block_size=64 +clk_domain=system.cpu_clk_domain +data_latency=20 +default_p_state=UNDEFINED +eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +sequential_access=false +size=2097152 +tag_latency=20 + +[system.cpu.toL2Bus] +type=CoherentXBar +children=snoop_filter +clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED +eventq_index=0 +forward_latency=0 +frontend_latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +point_of_coherency=false +power_model=Null +response_latency=1 +snoop_filter=system.cpu.toL2Bus.snoop_filter +snoop_response_latency=1 +system=system +use_default_range=false +width=32 +master=system.cpu.l2cache.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side + +[system.cpu.toL2Bus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=0 +max_capacity=8388608 +system=system + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=LiveProcess +cmd=insttest +cwd= +drivers= +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable=/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64a/insttest +gid=100 +input=cin +kvmInSE=false +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=0 +system=system +uid=100 +useArchPT=false + +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000000 + +[system.membus] +type=CoherentXBar +children=snoop_filter +clk_domain=system.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +forward_latency=4 +frontend_latency=3 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +point_of_coherency=true +power_model=Null +response_latency=2 +snoop_filter=system.membus.snoop_filter +snoop_response_latency=4 +system=system +use_default_range=false +width=16 +master=system.physmem.port +slave=system.system_port system.cpu.l2cache.mem_side + +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + +[system.physmem] +type=DRAMCtrl +IDD0=0.055000 +IDD02=0.000000 +IDD2N=0.032000 +IDD2N2=0.000000 +IDD2P0=0.000000 +IDD2P02=0.000000 +IDD2P1=0.032000 +IDD2P12=0.000000 +IDD3N=0.038000 +IDD3N2=0.000000 +IDD3P0=0.000000 +IDD3P02=0.000000 +IDD3P1=0.038000 +IDD3P12=0.000000 +IDD4R=0.157000 +IDD4R2=0.000000 +IDD4W=0.125000 +IDD4W2=0.000000 +IDD5=0.235000 +IDD52=0.000000 +IDD6=0.020000 +IDD62=0.000000 +VDD=1.500000 +VDD2=0.000000 +activation_limit=4 +addr_mapping=RoRaBaCoCh +bank_groups_per_rank=0 +banks_per_rank=8 +burst_length=8 +channels=1 +clk_domain=system.clk_domain +conf_table_reported=true +default_p_state=UNDEFINED +device_bus_width=8 +device_rowbuffer_size=1024 +device_size=536870912 +devices_per_rank=8 +dll=true +eventq_index=0 +in_addr_map=true +kvm_map=true +max_accesses_per_row=16 +mem_sched_policy=frfcfs +min_writes_per_switch=16 +null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +page_policy=open_adaptive +power_model=Null +range=0:134217727:0:0:0:0 +ranks_per_channel=2 +read_buffer_size=32 +static_backend_latency=10000 +static_frontend_latency=10000 +tBURST=5000 +tCCD_L=0 +tCK=1250 +tCL=13750 +tCS=2500 +tRAS=35000 +tRCD=13750 +tREFI=7800000 +tRFC=260000 +tRP=13750 +tRRD=6000 +tRRD_L=0 +tRTP=7500 +tRTW=2500 +tWR=15000 +tWTR=7500 +tXAW=30000 +tXP=6000 +tXPDLL=0 +tXS=270000 +tXSDLL=0 +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 +port=system.membus.master[0] + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/minor-timing/config.json b/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/minor-timing/config.json new file mode 100644 index 000000000..3a39a409a --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/minor-timing/config.json @@ -0,0 +1,1211 @@ +{ + "name": null, + "sim_quantum": 0, + "system": { + "kernel": "", + "mmap_using_noreserve": false, + "kernel_addr_check": true, + "membus": { + "point_of_coherency": true, + "system": "system", + "response_latency": 2, + "cxx_class": "CoherentXBar", + "forward_latency": 4, + "clk_domain": "system.clk_domain", + "width": 16, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "master": { + "peer": [ + "system.physmem.port" + ], + "role": "MASTER" + }, + "type": "CoherentXBar", + "frontend_latency": 3, + "slave": { + "peer": [ + "system.system_port", + "system.cpu.l2cache.mem_side" + ], + "role": "SLAVE" + }, + "p_state_clk_gate_min": 1000, + "snoop_filter": { + "name": "snoop_filter", + "system": "system", + "max_capacity": 8388608, + "eventq_index": 0, + "cxx_class": "SnoopFilter", + "path": "system.membus.snoop_filter", + "type": "SnoopFilter", + "lookup_latency": 1 + }, + "power_model": null, + "path": "system.membus", + "snoop_response_latency": 4, + "name": "membus", + "p_state_clk_gate_bins": 20, + "use_default_range": false + }, + "symbolfile": "", + "readfile": "", + "thermal_model": null, + "cxx_class": "System", + "work_begin_cpu_id_exit": -1, + "load_offset": 0, + "work_begin_exit_count": 0, + "p_state_clk_gate_min": 1000, + "memories": [ + "system.physmem" + ], + "work_begin_ckpt_count": 0, + "clk_domain": { + "name": "clk_domain", + "clock": [ + 1000 + ], + "init_perf_level": 0, + "voltage_domain": "system.voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "mem_ranges": [], + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "dvfs_handler": { + "enable": false, + "name": "dvfs_handler", + "sys_clk_domain": "system.clk_domain", + "transition_latency": 100000000, + "eventq_index": 0, + "cxx_class": "DVFSHandler", + "domains": [], + "path": "system.dvfs_handler", + "type": "DVFSHandler" + }, + "work_end_exit_count": 0, + "type": "System", + "voltage_domain": { + "name": "voltage_domain", + "eventq_index": 0, + "voltage": [ + "1.0" + ], + "cxx_class": "VoltageDomain", + "path": "system.voltage_domain", + "type": "VoltageDomain" + }, + "cache_line_size": 64, + "boot_osflags": "a", + "system_port": { + "peer": "system.membus.slave[0]", + "role": "MASTER" + }, + "physmem": { + "static_frontend_latency": 10000, + "tRFC": 260000, + "activation_limit": 4, + "in_addr_map": true, + "IDD3N2": "0.0", + "tWTR": 7500, + "IDD52": "0.0", + "clk_domain": "system.clk_domain", + "channels": 1, + "write_buffer_size": 64, + "device_bus_width": 8, + "VDD": "1.5", + "write_high_thresh_perc": 85, + "cxx_class": "DRAMCtrl", + "bank_groups_per_rank": 0, + "IDD2N2": "0.0", + "port": { + "peer": "system.membus.master[0]", + "role": "SLAVE" + }, + "tCCD_L": 0, + "IDD2N": "0.032", + "p_state_clk_gate_min": 1000, + "null": false, + "IDD2P1": "0.032", + "eventq_index": 0, + "tRRD": 6000, + "tRTW": 2500, + "IDD4R": "0.157", + "burst_length": 8, + "tRTP": 7500, + "IDD4W": "0.125", + "tWR": 15000, + "banks_per_rank": 8, + "devices_per_rank": 8, + "IDD2P02": "0.0", + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "IDD6": "0.02", + "IDD5": "0.235", + "tRCD": 13750, + "type": "DRAMCtrl", + "IDD3P02": "0.0", + "tRRD_L": 0, + "IDD0": "0.055", + "IDD62": "0.0", + "min_writes_per_switch": 16, + "mem_sched_policy": "frfcfs", + "IDD02": "0.0", + "IDD2P0": "0.0", + "ranks_per_channel": 2, + "page_policy": "open_adaptive", + "IDD4W2": "0.0", + "tCS": 2500, + "power_model": null, + "tCL": 13750, + "read_buffer_size": 32, + "conf_table_reported": true, + "tCK": 1250, + "tRAS": 35000, + "tRP": 13750, + "tBURST": 5000, + "path": "system.physmem", + "tXP": 6000, + "tXS": 270000, + "addr_mapping": "RoRaBaCoCh", + "IDD3P0": "0.0", + "IDD3P1": "0.038", + "IDD3N": "0.038", + "name": "physmem", + "tXSDLL": 0, + "device_size": 536870912, + "kvm_map": true, + "dll": true, + "tXAW": 30000, + "write_low_thresh_perc": 50, + "range": "0:134217727:0:0:0:0", + "VDD2": "0.0", + "IDD2P12": "0.0", + "p_state_clk_gate_bins": 20, + "tXPDLL": 0, + "IDD4R2": "0.0", + "device_rowbuffer_size": 1024, + "static_backend_latency": 10000, + "max_accesses_per_row": 16, + "IDD3P12": "0.0", + "tREFI": 7800000 + }, + "power_model": null, + "work_cpus_ckpt_count": 0, + "thermal_components": [], + "path": "system", + "cpu_clk_domain": { + "name": "cpu_clk_domain", + "clock": [ + 500 + ], + "init_perf_level": 0, + "voltage_domain": "system.voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.cpu_clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "work_end_ckpt_count": 0, + "mem_mode": "timing", + "name": "system", + "init_param": 0, + "p_state_clk_gate_bins": 20, + "load_addr_mask": 1099511627775, + "cpu": [ + { + "max_insts_any_thread": 0, + "do_statistics_insts": true, + "numThreads": 1, + "fetch1LineSnapWidth": 0, + "fetch1ToFetch2BackwardDelay": 1, + "fetch1FetchLimit": 1, + "executeIssueLimit": 2, + "system": "system", + "executeLSQMaxStoreBufferStoresPerCycle": 2, + "icache": { + "cpu_side": { + "peer": "system.cpu.icache_port", + "role": "SLAVE" + }, + "clusivity": "mostly_incl", + "prefetcher": null, + "system": "system", + "write_buffers": 8, + "response_latency": 2, + "cxx_class": "Cache", + "size": 131072, + "type": "Cache", + "clk_domain": "system.cpu_clk_domain", + "max_miss_count": 0, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "mem_side": { + "peer": "system.cpu.toL2Bus.slave[0]", + "role": "MASTER" + }, + "mshrs": 4, + "writeback_clean": true, + "p_state_clk_gate_min": 1000, + "tags": { + "size": 131072, + "tag_latency": 2, + "name": "tags", + "p_state_clk_gate_min": 1000, + "eventq_index": 0, + "p_state_clk_gate_bins": 20, + "default_p_state": "UNDEFINED", + "clk_domain": "system.cpu_clk_domain", + "power_model": null, + "sequential_access": false, + "assoc": 2, + "cxx_class": "LRU", + "p_state_clk_gate_max": 1000000000000, + "path": "system.cpu.icache.tags", + "block_size": 64, + "type": "LRU", + "data_latency": 2 + }, + "tgts_per_mshr": 20, + "demand_mshr_reserve": 1, + "power_model": null, + "addr_ranges": [ + "0:18446744073709551615:0:0:0:0" + ], + "is_read_only": true, + "prefetch_on_access": false, + "path": "system.cpu.icache", + "data_latency": 2, + "tag_latency": 2, + "name": "icache", + "p_state_clk_gate_bins": 20, + "sequential_access": false, + "assoc": 2 + }, + "function_trace": false, + "do_checkpoint_insts": true, + "decodeInputWidth": 2, + "cxx_class": "MinorCPU", + "max_loads_all_threads": 0, + "executeMemoryIssueLimit": 1, + "decodeCycleInput": true, + "max_loads_any_thread": 0, + "executeLSQTransfersQueueSize": 2, + "p_state_clk_gate_max": 1000000000000, + "clk_domain": "system.cpu_clk_domain", + "function_trace_start": 0, + "cpu_id": 0, + "checker": null, + "eventq_index": 0, + "executeMemoryWidth": 0, + "default_p_state": "UNDEFINED", + "executeBranchDelay": 1, + "executeMemoryCommitLimit": 1, + "l2cache": { + "cpu_side": { + "peer": "system.cpu.toL2Bus.master[0]", + "role": "SLAVE" + }, + "clusivity": "mostly_incl", + "prefetcher": null, + "system": "system", + "write_buffers": 8, + "response_latency": 20, + "cxx_class": "Cache", + "size": 2097152, + "type": "Cache", + "clk_domain": "system.cpu_clk_domain", + "max_miss_count": 0, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "mem_side": { + "peer": "system.membus.slave[1]", + "role": "MASTER" + }, + "mshrs": 20, + "writeback_clean": false, + "p_state_clk_gate_min": 1000, + "tags": { + "size": 2097152, + "tag_latency": 20, + "name": "tags", + "p_state_clk_gate_min": 1000, + "eventq_index": 0, + "p_state_clk_gate_bins": 20, + "default_p_state": "UNDEFINED", + "clk_domain": "system.cpu_clk_domain", + "power_model": null, + "sequential_access": false, + "assoc": 8, + "cxx_class": "LRU", + "p_state_clk_gate_max": 1000000000000, + "path": "system.cpu.l2cache.tags", + "block_size": 64, + "type": "LRU", + "data_latency": 20 + }, + "tgts_per_mshr": 12, + "demand_mshr_reserve": 1, + "power_model": null, + "addr_ranges": [ + "0:18446744073709551615:0:0:0:0" + ], + "is_read_only": false, + "prefetch_on_access": false, + "path": "system.cpu.l2cache", + "data_latency": 20, + "tag_latency": 20, + "name": "l2cache", + "p_state_clk_gate_bins": 20, + "sequential_access": false, + "assoc": 8 + }, + "do_quiesce": true, + "type": "MinorCPU", + "executeCycleInput": true, + "executeAllowEarlyMemoryIssue": true, + "executeInputBufferSize": 7, + "icache_port": { + "peer": "system.cpu.icache.cpu_side", + "role": "MASTER" + }, + "p_state_clk_gate_bins": 20, + "socket_id": 0, + "progress_interval": 0, + "p_state_clk_gate_min": 1000, + "toL2Bus": { + "point_of_coherency": false, + "system": "system", + "response_latency": 1, + "cxx_class": "CoherentXBar", + "forward_latency": 0, + "clk_domain": "system.cpu_clk_domain", + "width": 32, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "master": { + "peer": [ + "system.cpu.l2cache.cpu_side" + ], + "role": "MASTER" + }, + "type": "CoherentXBar", + "frontend_latency": 1, + "slave": { + "peer": [ + "system.cpu.icache.mem_side", + "system.cpu.dcache.mem_side" + ], + "role": "SLAVE" + }, + "p_state_clk_gate_min": 1000, + "snoop_filter": { + "name": "snoop_filter", + "system": "system", + "max_capacity": 8388608, + "eventq_index": 0, + "cxx_class": "SnoopFilter", + "path": "system.cpu.toL2Bus.snoop_filter", + "type": "SnoopFilter", + "lookup_latency": 0 + }, + "power_model": null, + "path": "system.cpu.toL2Bus", + "snoop_response_latency": 1, + "name": "toL2Bus", + "p_state_clk_gate_bins": 20, + "use_default_range": false + }, + "isa": [ + { + "eventq_index": 0, + "path": "system.cpu.isa", + "type": "RiscvISA", + "name": "isa", + "cxx_class": "RiscvISA::ISA" + } + ], + "itb": { + "name": "itb", + "eventq_index": 0, + "cxx_class": "RiscvISA::TLB", + "path": "system.cpu.itb", + "type": "RiscvTLB", + "size": 64 + }, + "interrupts": [ + { + "eventq_index": 0, + "path": "system.cpu.interrupts", + "type": "RiscvInterrupts", + "name": "interrupts", + "cxx_class": "RiscvISA::Interrupts" + } + ], + "dcache_port": { + "peer": "system.cpu.dcache.cpu_side", + "role": "MASTER" + }, + "executeFuncUnits": { + "name": "executeFuncUnits", + "eventq_index": 0, + "cxx_class": "MinorFUPool", + "path": "system.cpu.executeFuncUnits", + "funcUnits": [ + { + "issueLat": 1, + "opLat": 3, + "name": "funcUnits0", + "cantForwardFromFUIndices": [], + "opClasses": { + "name": "opClasses", + "opClasses": [ + { + "opClass": "IntAlu", + "name": "opClasses", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses", + "type": "MinorOpClass" + } + ], + "eventq_index": 0, + "cxx_class": "MinorOpClassSet", + "path": "system.cpu.executeFuncUnits.funcUnits0.opClasses", + "type": "MinorOpClassSet" + }, + "eventq_index": 0, + "timings": [ + { + "extraAssumedLat": 0, + "description": "Int", + "srcRegsRelativeLats": [ + 2 + ], + "suppress": false, + "mask": 0, + "extraCommitLat": 0, + "eventq_index": 0, + "opClasses": { + "name": "opClasses", + "opClasses": [], + "eventq_index": 0, + "cxx_class": "MinorOpClassSet", + "path": "system.cpu.executeFuncUnits.funcUnits0.timings.opClasses", + "type": "MinorOpClassSet" + }, + "cxx_class": "MinorFUTiming", + "path": "system.cpu.executeFuncUnits.funcUnits0.timings", + "extraCommitLatExpr": null, + "type": "MinorFUTiming", + "match": 0, + "name": "timings" + } + ], + "cxx_class": "MinorFU", + "path": "system.cpu.executeFuncUnits.funcUnits0", + "type": "MinorFU" + }, + { + "issueLat": 1, + "opLat": 3, + "name": "funcUnits1", + "cantForwardFromFUIndices": [], + "opClasses": { + "name": "opClasses", + "opClasses": [ + { + "opClass": "IntAlu", + "name": "opClasses", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses", + "type": "MinorOpClass" + } + ], + "eventq_index": 0, + "cxx_class": "MinorOpClassSet", + "path": "system.cpu.executeFuncUnits.funcUnits1.opClasses", + "type": "MinorOpClassSet" + }, + "eventq_index": 0, + "timings": [ + { + "extraAssumedLat": 0, + "description": "Int", + "srcRegsRelativeLats": [ + 2 + ], + "suppress": false, + "mask": 0, + "extraCommitLat": 0, + "eventq_index": 0, + "opClasses": { + "name": "opClasses", + "opClasses": [], + "eventq_index": 0, + "cxx_class": "MinorOpClassSet", + "path": "system.cpu.executeFuncUnits.funcUnits1.timings.opClasses", + "type": "MinorOpClassSet" + }, + "cxx_class": "MinorFUTiming", + "path": "system.cpu.executeFuncUnits.funcUnits1.timings", + "extraCommitLatExpr": null, + "type": "MinorFUTiming", + "match": 0, + "name": "timings" + } + ], + "cxx_class": "MinorFU", + "path": "system.cpu.executeFuncUnits.funcUnits1", + "type": "MinorFU" + }, + { + "issueLat": 1, + "opLat": 3, + "name": "funcUnits2", + "cantForwardFromFUIndices": [], + "opClasses": { + "name": "opClasses", + "opClasses": [ + { + "opClass": "IntMult", + "name": "opClasses", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses", + "type": "MinorOpClass" + } + ], + "eventq_index": 0, + "cxx_class": "MinorOpClassSet", + "path": "system.cpu.executeFuncUnits.funcUnits2.opClasses", + "type": "MinorOpClassSet" + }, + "eventq_index": 0, + "timings": [ + { + "extraAssumedLat": 0, + "description": "Mul", + "srcRegsRelativeLats": [ + 0 + ], + "suppress": false, + "mask": 0, + "extraCommitLat": 0, + "eventq_index": 0, + "opClasses": { + "name": "opClasses", + "opClasses": [], + "eventq_index": 0, + "cxx_class": "MinorOpClassSet", + "path": "system.cpu.executeFuncUnits.funcUnits2.timings.opClasses", + "type": "MinorOpClassSet" + }, + "cxx_class": "MinorFUTiming", + "path": "system.cpu.executeFuncUnits.funcUnits2.timings", + "extraCommitLatExpr": null, + "type": "MinorFUTiming", + "match": 0, + "name": "timings" + } + ], + "cxx_class": "MinorFU", + "path": "system.cpu.executeFuncUnits.funcUnits2", + "type": "MinorFU" + }, + { + "issueLat": 9, + "opLat": 9, + "name": "funcUnits3", + "cantForwardFromFUIndices": [], + "opClasses": { + "name": "opClasses", + "opClasses": [ + { + "opClass": "IntDiv", + "name": "opClasses", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses", + "type": "MinorOpClass" + } + ], + "eventq_index": 0, + "cxx_class": "MinorOpClassSet", + "path": "system.cpu.executeFuncUnits.funcUnits3.opClasses", + "type": "MinorOpClassSet" + }, + "eventq_index": 0, + "timings": [], + "cxx_class": "MinorFU", + "path": "system.cpu.executeFuncUnits.funcUnits3", + "type": "MinorFU" + }, + { + "issueLat": 1, + "opLat": 6, + "name": "funcUnits4", + "cantForwardFromFUIndices": [], + "opClasses": { + "name": "opClasses", + "opClasses": [ + { + "opClass": "FloatAdd", + "name": "opClasses00", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00", + "type": "MinorOpClass" + }, + { + "opClass": "FloatCmp", + "name": "opClasses01", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01", + "type": "MinorOpClass" + }, + { + "opClass": "FloatCvt", + "name": "opClasses02", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02", + "type": "MinorOpClass" + }, + { + "opClass": "FloatMisc", + "name": "opClasses03", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03", + "type": "MinorOpClass" + }, + { + "opClass": "FloatMult", + "name": "opClasses04", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04", + "type": "MinorOpClass" + }, + { + "opClass": "FloatMultAcc", + "name": "opClasses05", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05", + "type": "MinorOpClass" + }, + { + "opClass": "FloatDiv", + "name": "opClasses06", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06", + "type": "MinorOpClass" + }, + { + "opClass": "FloatSqrt", + "name": "opClasses07", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07", + "type": "MinorOpClass" + }, + { + "opClass": "SimdAdd", + "name": "opClasses08", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08", + "type": "MinorOpClass" + }, + { + "opClass": "SimdAddAcc", + "name": "opClasses09", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09", + "type": "MinorOpClass" + }, + { + "opClass": "SimdAlu", + "name": "opClasses10", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10", + "type": "MinorOpClass" + }, + { + "opClass": "SimdCmp", + "name": "opClasses11", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11", + "type": "MinorOpClass" + }, + { + "opClass": "SimdCvt", + "name": "opClasses12", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12", + "type": "MinorOpClass" + }, + { + "opClass": "SimdMisc", + "name": "opClasses13", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13", + "type": "MinorOpClass" + }, + { + "opClass": "SimdMult", + "name": "opClasses14", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14", + "type": "MinorOpClass" + }, + { + "opClass": "SimdMultAcc", + "name": "opClasses15", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15", + "type": "MinorOpClass" + }, + { + "opClass": "SimdShift", + "name": "opClasses16", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16", + "type": "MinorOpClass" + }, + { + "opClass": "SimdShiftAcc", + "name": "opClasses17", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17", + "type": "MinorOpClass" + }, + { + "opClass": "SimdSqrt", + "name": "opClasses18", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18", + "type": "MinorOpClass" + }, + { + "opClass": "SimdFloatAdd", + "name": "opClasses19", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19", + "type": "MinorOpClass" + }, + { + "opClass": "SimdFloatAlu", + "name": "opClasses20", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20", + "type": "MinorOpClass" + }, + { + "opClass": "SimdFloatCmp", + "name": "opClasses21", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21", + "type": "MinorOpClass" + }, + { + "opClass": "SimdFloatCvt", + "name": "opClasses22", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22", + "type": "MinorOpClass" + }, + { + "opClass": "SimdFloatDiv", + "name": "opClasses23", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23", + "type": "MinorOpClass" + }, + { + "opClass": "SimdFloatMisc", + "name": "opClasses24", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24", + "type": "MinorOpClass" + }, + { + "opClass": "SimdFloatMult", + "name": "opClasses25", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25", + "type": "MinorOpClass" + }, + { + "opClass": "SimdFloatMultAcc", + "name": "opClasses26", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses26", + "type": "MinorOpClass" + }, + { + "opClass": "SimdFloatSqrt", + "name": "opClasses27", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses27", + "type": "MinorOpClass" + } + ], + "eventq_index": 0, + "cxx_class": "MinorOpClassSet", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses", + "type": "MinorOpClassSet" + }, + "eventq_index": 0, + "timings": [ + { + "extraAssumedLat": 0, + "description": "FloatSimd", + "srcRegsRelativeLats": [ + 2 + ], + "suppress": false, + "mask": 0, + "extraCommitLat": 0, + "eventq_index": 0, + "opClasses": { + "name": "opClasses", + "opClasses": [], + "eventq_index": 0, + "cxx_class": "MinorOpClassSet", + "path": "system.cpu.executeFuncUnits.funcUnits4.timings.opClasses", + "type": "MinorOpClassSet" + }, + "cxx_class": "MinorFUTiming", + "path": "system.cpu.executeFuncUnits.funcUnits4.timings", + "extraCommitLatExpr": null, + "type": "MinorFUTiming", + "match": 0, + "name": "timings" + } + ], + "cxx_class": "MinorFU", + "path": "system.cpu.executeFuncUnits.funcUnits4", + "type": "MinorFU" + }, + { + "issueLat": 1, + "opLat": 1, + "name": "funcUnits5", + "cantForwardFromFUIndices": [], + "opClasses": { + "name": "opClasses", + "opClasses": [ + { + "opClass": "MemRead", + "name": "opClasses0", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0", + "type": "MinorOpClass" + }, + { + "opClass": "MemWrite", + "name": "opClasses1", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1", + "type": "MinorOpClass" + }, + { + "opClass": "FloatMemRead", + "name": "opClasses2", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses2", + "type": "MinorOpClass" + }, + { + "opClass": "FloatMemWrite", + "name": "opClasses3", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses3", + "type": "MinorOpClass" + } + ], + "eventq_index": 0, + "cxx_class": "MinorOpClassSet", + "path": "system.cpu.executeFuncUnits.funcUnits5.opClasses", + "type": "MinorOpClassSet" + }, + "eventq_index": 0, + "timings": [ + { + "extraAssumedLat": 2, + "description": "Mem", + "srcRegsRelativeLats": [ + 1 + ], + "suppress": false, + "mask": 0, + "extraCommitLat": 0, + "eventq_index": 0, + "opClasses": { + "name": "opClasses", + "opClasses": [], + "eventq_index": 0, + "cxx_class": "MinorOpClassSet", + "path": "system.cpu.executeFuncUnits.funcUnits5.timings.opClasses", + "type": "MinorOpClassSet" + }, + "cxx_class": "MinorFUTiming", + "path": "system.cpu.executeFuncUnits.funcUnits5.timings", + "extraCommitLatExpr": null, + "type": "MinorFUTiming", + "match": 0, + "name": "timings" + } + ], + "cxx_class": "MinorFU", + "path": "system.cpu.executeFuncUnits.funcUnits5", + "type": "MinorFU" + }, + { + "issueLat": 1, + "opLat": 1, + "name": "funcUnits6", + "cantForwardFromFUIndices": [], + "opClasses": { + "name": "opClasses", + "opClasses": [ + { + "opClass": "IprAccess", + "name": "opClasses0", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0", + "type": "MinorOpClass" + }, + { + "opClass": "InstPrefetch", + "name": "opClasses1", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1", + "type": "MinorOpClass" + } + ], + "eventq_index": 0, + "cxx_class": "MinorOpClassSet", + "path": "system.cpu.executeFuncUnits.funcUnits6.opClasses", + "type": "MinorOpClassSet" + }, + "eventq_index": 0, + "timings": [], + "cxx_class": "MinorFU", + "path": "system.cpu.executeFuncUnits.funcUnits6", + "type": "MinorFU" + } + ], + "type": "MinorFUPool" + }, + "switched_out": false, + "power_model": null, + "max_insts_all_threads": 0, + "executeSetTraceTimeOnIssue": false, + "fetch2InputBufferSize": 2, + "profile": 0, + "fetch2ToDecodeForwardDelay": 1, + "executeInputWidth": 2, + "decodeToExecuteForwardDelay": 1, + "executeLSQRequestsQueueSize": 1, + "fetch2CycleInput": true, + "executeMaxAccessesInMemory": 2, + "enableIdling": true, + "executeLSQStoreBufferSize": 5, + "workload": [ + { + "uid": 100, + "pid": 100, + "kvmInSE": false, + "cxx_class": "LiveProcess", + "executable": "/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64a/insttest", + "drivers": [], + "system": "system", + "gid": 100, + "eventq_index": 0, + "env": [], + "input": "cin", + "ppid": 99, + "type": "LiveProcess", + "cwd": "", + "simpoint": 0, + "euid": 100, + "path": "system.cpu.workload", + "max_stack_size": 67108864, + "name": "workload", + "cmd": [ + "insttest" + ], + "errout": "cerr", + "useArchPT": false, + "egid": 100, + "output": "cout" + } + ], + "name": "cpu", + "dtb": { + "name": "dtb", + "eventq_index": 0, + "cxx_class": "RiscvISA::TLB", + "path": "system.cpu.dtb", + "type": "RiscvTLB", + "size": 64 + }, + "simpoint_start_insts": [], + "executeSetTraceTimeOnCommit": true, + "tracer": { + "eventq_index": 0, + "path": "system.cpu.tracer", + "type": "ExeTracer", + "name": "tracer", + "cxx_class": "Trace::ExeTracer" + }, + "threadPolicy": "RoundRobin", + "executeCommitLimit": 2, + "fetch1LineWidth": 0, + "branchPred": { + "numThreads": 1, + "BTBEntries": 4096, + "cxx_class": "TournamentBP", + "indirectPathLength": 3, + "globalCtrBits": 2, + "choicePredictorSize": 8192, + "indirectHashGHR": true, + "eventq_index": 0, + "localHistoryTableSize": 2048, + "type": "TournamentBP", + "indirectSets": 256, + "indirectWays": 2, + "choiceCtrBits": 2, + "useIndirect": true, + "localCtrBits": 2, + "path": "system.cpu.branchPred", + "localPredictorSize": 2048, + "RASSize": 16, + "globalPredictorSize": 8192, + "name": "branchPred", + "indirectHashTargets": true, + "instShiftAmt": 2, + "indirectTagSize": 16, + "BTBTagSize": 16 + }, + "dcache": { + "cpu_side": { + "peer": "system.cpu.dcache_port", + "role": "SLAVE" + }, + "clusivity": "mostly_incl", + "prefetcher": null, + "system": "system", + "write_buffers": 8, + "response_latency": 2, + "cxx_class": "Cache", + "size": 262144, + "type": "Cache", + "clk_domain": "system.cpu_clk_domain", + "max_miss_count": 0, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "mem_side": { + "peer": "system.cpu.toL2Bus.slave[1]", + "role": "MASTER" + }, + "mshrs": 4, + "writeback_clean": false, + "p_state_clk_gate_min": 1000, + "tags": { + "size": 262144, + "tag_latency": 2, + "name": "tags", + "p_state_clk_gate_min": 1000, + "eventq_index": 0, + "p_state_clk_gate_bins": 20, + "default_p_state": "UNDEFINED", + "clk_domain": "system.cpu_clk_domain", + "power_model": null, + "sequential_access": false, + "assoc": 2, + "cxx_class": "LRU", + "p_state_clk_gate_max": 1000000000000, + "path": "system.cpu.dcache.tags", + "block_size": 64, + "type": "LRU", + "data_latency": 2 + }, + "tgts_per_mshr": 20, + "demand_mshr_reserve": 1, + "power_model": null, + "addr_ranges": [ + "0:18446744073709551615:0:0:0:0" + ], + "is_read_only": false, + "prefetch_on_access": false, + "path": "system.cpu.dcache", + "data_latency": 2, + "tag_latency": 2, + "name": "dcache", + "p_state_clk_gate_bins": 20, + "sequential_access": false, + "assoc": 2 + }, + "path": "system.cpu", + "fetch1ToFetch2ForwardDelay": 1, + "decodeInputBufferSize": 3 + } + ], + "multi_thread": false, + "exit_on_work_items": false, + "work_item_id": -1, + "num_work_ids": 16 + }, + "time_sync_period": 100000000000, + "eventq_index": 0, + "time_sync_spin_threshold": 100000000, + "cxx_class": "Root", + "path": "root", + "time_sync_enable": false, + "type": "Root", + "full_system": false +}
\ No newline at end of file diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/minor-timing/simerr b/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/minor-timing/simerr new file mode 100755 index 000000000..85a6a33ad --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/minor-timing/simerr @@ -0,0 +1,4 @@ +warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes) +warn: Unknown operating system; assuming Linux. +warn: Sockets disabled, not accepting gdb connections +warn: ClockedObject: More than one power state change request encountered within the same simulation tick diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/minor-timing/simout b/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/minor-timing/simout new file mode 100755 index 000000000..842600b45 --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/minor-timing/simout @@ -0,0 +1,49 @@ +Redirecting stdout to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64a/minor-timing/simout +Redirecting stderr to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64a/minor-timing/simerr +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled Nov 30 2016 14:33:35 +gem5 started Nov 30 2016 16:18:29 +gem5 executing on zizzer, pid 34061 +command line: /z/powerjg/gem5-upstream/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64a/minor-timing -re /z/powerjg/gem5-upstream/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64a/minor-timing + +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. +lr.w/sc.w: PASS +sc.w, no preceding lr.d: PASS +amoswap.w: PASS +amoswap.w, sign extend: PASS +amoswap.w, truncate: PASS +amoadd.w: PASS +amoadd.w, truncate/overflow: PASS +amoadd.w, sign extend: PASS +amoxor.w, truncate: PASS +amoxor.w, sign extend: PASS +amoand.w, truncate: PASS +amoand.w, sign extend: PASS +amoor.w, truncate: PASS +amoor.w, sign extend: PASS +amomin.w, truncate: PASS +amomin.w, sign extend: PASS +amomax.w, truncate: PASS +amomax.w, sign extend: PASS +amominu.w, truncate: PASS +amominu.w, sign extend: PASS +amomaxu.w, truncate: PASS +amomaxu.w, sign extend: PASS +lr.d/sc.d: PASS +sc.d, no preceding lr.d: PASS +amoswap.d: PASS +amoadd.d: PASS +amoadd.d, overflow: PASS +amoxor.d (1): PASS +amoxor.d (0): PASS +amoand.d: PASS +amoor.d: PASS +amomin.d: PASS +amomax.d: PASS +amominu.d: PASS +amomaxu.d: PASS +Exiting @ tick 167328500 because target called exit() diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/minor-timing/stats.txt b/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/minor-timing/stats.txt new file mode 100644 index 000000000..b23a2b88f --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/minor-timing/stats.txt @@ -0,0 +1,769 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.000167 # Number of seconds simulated +sim_ticks 167328500 # Number of ticks simulated +final_tick 167328500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 54302 # Simulator instruction rate (inst/s) +host_op_rate 54316 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 79708249 # Simulator tick rate (ticks/s) +host_mem_usage 244184 # Number of bytes of host memory used +host_seconds 2.10 # Real time elapsed on the host +sim_insts 113991 # Number of instructions simulated +sim_ops 114022 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 167328500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 52672 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 17088 # Number of bytes read from this memory +system.physmem.bytes_read::total 69760 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 52672 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 52672 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 823 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 267 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1090 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 314782001 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 102122472 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 416904472 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 314782001 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 314782001 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 314782001 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 102122472 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 416904472 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1090 # Number of read requests accepted +system.physmem.writeReqs 0 # Number of write requests accepted +system.physmem.readBursts 1090 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 69760 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue +system.physmem.bytesWritten 0 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 69760 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 110 # Per bank write bursts +system.physmem.perBankRdBursts::1 4 # Per bank write bursts +system.physmem.perBankRdBursts::2 9 # Per bank write bursts +system.physmem.perBankRdBursts::3 124 # Per bank write bursts +system.physmem.perBankRdBursts::4 62 # Per bank write bursts +system.physmem.perBankRdBursts::5 92 # Per bank write bursts +system.physmem.perBankRdBursts::6 88 # Per bank write bursts +system.physmem.perBankRdBursts::7 18 # Per bank write bursts +system.physmem.perBankRdBursts::8 55 # Per bank write bursts +system.physmem.perBankRdBursts::9 86 # Per bank write bursts +system.physmem.perBankRdBursts::10 90 # Per bank write bursts +system.physmem.perBankRdBursts::11 38 # Per bank write bursts +system.physmem.perBankRdBursts::12 113 # Per bank write bursts +system.physmem.perBankRdBursts::13 94 # Per bank write bursts +system.physmem.perBankRdBursts::14 101 # Per bank write bursts +system.physmem.perBankRdBursts::15 6 # Per bank write bursts +system.physmem.perBankWrBursts::0 0 # Per bank write bursts +system.physmem.perBankWrBursts::1 0 # Per bank write bursts +system.physmem.perBankWrBursts::2 0 # Per bank write bursts +system.physmem.perBankWrBursts::3 0 # Per bank write bursts +system.physmem.perBankWrBursts::4 0 # Per bank write bursts +system.physmem.perBankWrBursts::5 0 # Per bank write bursts +system.physmem.perBankWrBursts::6 0 # Per bank write bursts +system.physmem.perBankWrBursts::7 0 # Per bank write bursts +system.physmem.perBankWrBursts::8 0 # Per bank write bursts +system.physmem.perBankWrBursts::9 0 # Per bank write bursts +system.physmem.perBankWrBursts::10 0 # Per bank write bursts +system.physmem.perBankWrBursts::11 0 # Per bank write bursts +system.physmem.perBankWrBursts::12 0 # Per bank write bursts +system.physmem.perBankWrBursts::13 0 # Per bank write bursts +system.physmem.perBankWrBursts::14 0 # Per bank write bursts +system.physmem.perBankWrBursts::15 0 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 166995000 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 1090 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 0 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1032 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 53 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 5 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 207 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 327.729469 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 215.587083 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 297.390992 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 56 27.05% 27.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 46 22.22% 49.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 39 18.84% 68.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 16 7.73% 75.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 14 6.76% 82.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 7 3.38% 85.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 10 4.83% 90.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1 0.48% 91.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 18 8.70% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 207 # Bytes accessed per row activation +system.physmem.totQLat 15434500 # Total ticks spent queuing +system.physmem.totMemAccLat 35872000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 5450000 # Total ticks spent in databus transfers +system.physmem.avgQLat 14160.09 # Average queueing delay per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 32910.09 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 416.90 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 416.90 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.busUtil 3.26 # Data bus utilization in percentage +system.physmem.busUtilRead 3.26 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.04 # Average read queue length when enqueuing +system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing +system.physmem.readRowHits 874 # Number of row buffer hits during reads +system.physmem.writeRowHits 0 # Number of row buffer hits during writes +system.physmem.readRowHitRate 80.18 # Row buffer hit rate for reads +system.physmem.writeRowHitRate nan # Row buffer hit rate for writes +system.physmem.avgGap 153206.42 # Average gap between requests +system.physmem.pageHitRate 80.18 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 763980 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 387090 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 3619980 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 13522080.000000 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 9305250 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 493440 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 55143510 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 7150560 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 2565480 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 92951370 # Total energy per rank (pJ) +system.physmem_0.averagePower 555.501490 # Core power per rank (mW) +system.physmem_0.totalIdleTime 145131750 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 654000 # Time in different power states +system.physmem_0.memoryStateTime::REF 5732000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 6087000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 18616750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 15316500 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 120922250 # Time in different power states +system.physmem_1.actEnergy 778260 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 398475 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 4162620 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 12907440.000000 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 9798300 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 485280 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 44769510 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 12438720 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 4465980 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 90204585 # Total energy per rank (pJ) +system.physmem_1.averagePower 539.085991 # Core power per rank (mW) +system.physmem_1.totalIdleTime 144266000 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 729500 # Time in different power states +system.physmem_1.memoryStateTime::REF 5472000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 14006250 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 32390000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 16564250 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 98166500 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 167328500 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 31621 # Number of BP lookups +system.cpu.branchPred.condPredicted 20020 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 2186 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 28229 # Number of BTB lookups +system.cpu.branchPred.BTBHits 15507 # Number of BTB hits +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 54.932870 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 0 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 5663 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 3671 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 1992 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 1067 # Number of mispredicted indirect branches. +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 43 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 167328500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 334657 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 113991 # Number of instructions committed +system.cpu.committedOps 114022 # Number of ops (including micro ops) committed +system.cpu.discardedOps 5904 # Number of ops (including micro ops) which were discarded before commit +system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching +system.cpu.cpi 2.935819 # CPI: cycles per instruction +system.cpu.ipc 0.340620 # IPC: instructions per cycle +system.cpu.op_class_0::No_OpClass 43 0.04% 0.04% # Class of committed instruction +system.cpu.op_class_0::IntAlu 70180 61.55% 61.59% # Class of committed instruction +system.cpu.op_class_0::IntMult 105 0.09% 61.68% # Class of committed instruction +system.cpu.op_class_0::IntDiv 0 0.00% 61.68% # Class of committed instruction +system.cpu.op_class_0::FloatAdd 0 0.00% 61.68% # Class of committed instruction +system.cpu.op_class_0::FloatCmp 0 0.00% 61.68% # Class of committed instruction +system.cpu.op_class_0::FloatCvt 0 0.00% 61.68% # Class of committed instruction +system.cpu.op_class_0::FloatMult 0 0.00% 61.68% # Class of committed instruction +system.cpu.op_class_0::FloatMultAcc 0 0.00% 61.68% # Class of committed instruction +system.cpu.op_class_0::FloatDiv 0 0.00% 61.68% # Class of committed instruction +system.cpu.op_class_0::FloatMisc 0 0.00% 61.68% # Class of committed instruction +system.cpu.op_class_0::FloatSqrt 0 0.00% 61.68% # Class of committed instruction +system.cpu.op_class_0::SimdAdd 0 0.00% 61.68% # Class of committed instruction +system.cpu.op_class_0::SimdAddAcc 0 0.00% 61.68% # Class of committed instruction +system.cpu.op_class_0::SimdAlu 0 0.00% 61.68% # Class of committed instruction +system.cpu.op_class_0::SimdCmp 0 0.00% 61.68% # Class of committed instruction +system.cpu.op_class_0::SimdCvt 0 0.00% 61.68% # Class of committed instruction +system.cpu.op_class_0::SimdMisc 0 0.00% 61.68% # Class of committed instruction +system.cpu.op_class_0::SimdMult 0 0.00% 61.68% # Class of committed instruction +system.cpu.op_class_0::SimdMultAcc 0 0.00% 61.68% # Class of committed instruction +system.cpu.op_class_0::SimdShift 0 0.00% 61.68% # Class of committed instruction +system.cpu.op_class_0::SimdShiftAcc 0 0.00% 61.68% # Class of committed instruction +system.cpu.op_class_0::SimdSqrt 0 0.00% 61.68% # Class of committed instruction +system.cpu.op_class_0::SimdFloatAdd 0 0.00% 61.68% # Class of committed instruction +system.cpu.op_class_0::SimdFloatAlu 0 0.00% 61.68% # Class of committed instruction +system.cpu.op_class_0::SimdFloatCmp 0 0.00% 61.68% # Class of committed instruction +system.cpu.op_class_0::SimdFloatCvt 0 0.00% 61.68% # Class of committed instruction +system.cpu.op_class_0::SimdFloatDiv 0 0.00% 61.68% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMisc 0 0.00% 61.68% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMult 0 0.00% 61.68% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 61.68% # Class of committed instruction +system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 61.68% # Class of committed instruction +system.cpu.op_class_0::MemRead 23779 20.85% 82.53% # Class of committed instruction +system.cpu.op_class_0::MemWrite 19915 17.47% 100.00% # Class of committed instruction +system.cpu.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction +system.cpu.op_class_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction +system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.op_class_0::total 114022 # Class of committed instruction +system.cpu.tickCycles 171660 # Number of cycles that the object actually ticked +system.cpu.idleCycles 162997 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 167328500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 0 # number of replacements +system.cpu.dcache.tags.tagsinuse 215.204481 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 44066 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 268 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 164.425373 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 215.204481 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.052540 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.052540 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 268 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 4 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 61 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 203 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.065430 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 89318 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 89318 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 167328500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 24534 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 24534 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 19526 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 19526 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 2 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 2 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 4 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 4 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 44060 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 44060 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 44060 # number of overall hits +system.cpu.dcache.overall_hits::total 44060 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 75 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 75 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 384 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 384 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 459 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 459 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 459 # number of overall misses +system.cpu.dcache.overall_misses::total 459 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 8632000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 8632000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 30737000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 30737000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 39369000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 39369000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 39369000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 39369000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 24609 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 24609 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 19910 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 19910 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 2 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 2 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 4 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 4 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 44519 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 44519 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 44519 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 44519 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003048 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.003048 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.019287 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.019287 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.010310 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.010310 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.010310 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.010310 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 115093.333333 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 115093.333333 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 80044.270833 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 80044.270833 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 85771.241830 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 85771.241830 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 85771.241830 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 85771.241830 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 6 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 6 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 185 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 185 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 191 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 191 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 191 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 191 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 69 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 69 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 199 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 199 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 268 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 268 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 268 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 268 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7963000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 7963000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 15953500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 15953500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23916500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 23916500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23916500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 23916500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002804 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002804 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009995 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009995 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006020 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.006020 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006020 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.006020 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 115405.797101 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 115405.797101 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 80168.341709 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 80168.341709 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 89240.671642 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 89240.671642 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 89240.671642 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 89240.671642 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 167328500 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 18 # number of replacements +system.cpu.icache.tags.tagsinuse 401.761519 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 49677 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 823 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 60.360875 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 401.761519 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.196173 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.196173 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 805 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 47 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 518 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 240 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.393066 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 101823 # Number of tag accesses +system.cpu.icache.tags.data_accesses 101823 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 167328500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 49677 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 49677 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 49677 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 49677 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 49677 # number of overall hits +system.cpu.icache.overall_hits::total 49677 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 823 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 823 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 823 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 823 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 823 # number of overall misses +system.cpu.icache.overall_misses::total 823 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 69966000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 69966000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 69966000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 69966000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 69966000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 69966000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 50500 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 50500 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 50500 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 50500 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 50500 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 50500 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.016297 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.016297 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.016297 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.016297 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.016297 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.016297 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 85013.365735 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 85013.365735 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 85013.365735 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 85013.365735 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 85013.365735 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 85013.365735 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.icache.writebacks::writebacks 18 # number of writebacks +system.cpu.icache.writebacks::total 18 # number of writebacks +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 823 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 823 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 823 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 823 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 823 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 823 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 69143000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 69143000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 69143000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 69143000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 69143000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 69143000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.016297 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.016297 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.016297 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.016297 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.016297 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.016297 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 84013.365735 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 84013.365735 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 84013.365735 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 84013.365735 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 84013.365735 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 84013.365735 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 167328500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.replacements 0 # number of replacements +system.cpu.l2cache.tags.tagsinuse 622.728504 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 19 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 1090 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.017431 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::cpu.inst 407.968080 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 214.760424 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.012450 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.006554 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.019004 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 1090 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 585 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 454 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.033264 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 9962 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 9962 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 167328500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.WritebackClean_hits::writebacks 18 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 18 # number of WritebackClean hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 1 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.data 1 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 1 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.data 1 # number of overall hits +system.cpu.l2cache.overall_hits::total 1 # number of overall hits +system.cpu.l2cache.ReadExReq_misses::cpu.data 199 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 199 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 823 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 823 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 68 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 68 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.inst 823 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 267 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 1090 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 823 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 267 # number of overall misses +system.cpu.l2cache.overall_misses::total 1090 # number of overall misses +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 15654000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 15654000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 67908500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 67908500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 7847000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 7847000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 67908500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 23501000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 91409500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 67908500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 23501000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 91409500 # number of overall miss cycles +system.cpu.l2cache.WritebackClean_accesses::writebacks 18 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 18 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 199 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 199 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 823 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 823 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 69 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 69 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 823 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 268 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 1091 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 823 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 268 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 1091 # number of overall (read+write) accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 1 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 1 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.985507 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.985507 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.996269 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.999083 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.996269 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.999083 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78663.316583 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 78663.316583 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 82513.365735 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 82513.365735 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 115397.058824 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 115397.058824 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82513.365735 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 88018.726592 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 83861.926606 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82513.365735 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 88018.726592 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 83861.926606 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 199 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 199 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 823 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 823 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 68 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 68 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 823 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 267 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 1090 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 823 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 267 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 1090 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 13664000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 13664000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 59678500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 59678500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 7167000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 7167000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 59678500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 20831000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 80509500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 59678500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 20831000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 80509500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 1 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.985507 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.985507 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.996269 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.999083 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.996269 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.999083 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68663.316583 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68663.316583 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72513.365735 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72513.365735 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 105397.058824 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 105397.058824 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72513.365735 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 78018.726592 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 73861.926606 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72513.365735 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 78018.726592 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 73861.926606 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 1109 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 19 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 167328500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 892 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 18 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 199 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 199 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 823 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 69 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1664 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 536 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 2200 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 53824 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 17152 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 70976 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 1091 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.000917 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.030275 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 1090 99.91% 99.91% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 1 0.09% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 1091 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 572500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 1234500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.7 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 402000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) +system.membus.snoop_filter.tot_requests 1090 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 167328500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 891 # Transaction distribution +system.membus.trans_dist::ReadExReq 199 # Transaction distribution +system.membus.trans_dist::ReadExResp 199 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 891 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 2180 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 2180 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 69760 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 69760 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoopTraffic 0 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 1090 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 1090 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 1090 # Request fanout histogram +system.membus.reqLayer0.occupancy 1226500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.7 # Layer utilization (%) +system.membus.respLayer1.occupancy 5789000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 3.5 # Layer utilization (%) + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-atomic/config.ini b/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-atomic/config.ini new file mode 100644 index 000000000..b4b1de997 --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-atomic/config.ini @@ -0,0 +1,211 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain +boot_osflags=a +cache_line_size=64 +clk_domain=system.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +exit_on_work_items=false +init_param=0 +kernel= +kernel_addr_check=true +load_addr_mask=1099511627775 +load_offset=0 +mem_mode=atomic +mem_ranges= +memories=system.physmem +mmap_using_noreserve=false +multi_thread=false +num_work_ids=16 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +readfile= +symbolfile= +thermal_components= +thermal_model=Null +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=AtomicSimpleCPU +children=dtb interrupts isa itb tracer workload +branchPred=Null +checker=Null +clk_domain=system.cpu_clk_domain +cpu_id=0 +default_p_state=UNDEFINED +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +eventq_index=0 +fastmem=false +function_trace=false +function_trace_start=0 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +profile=0 +progress_interval=0 +simpoint_start_insts= +simulate_data_stalls=false +simulate_inst_stalls=false +socket_id=0 +switched_out=false +system=system +tracer=system.cpu.tracer +width=1 +workload=system.cpu.workload +dcache_port=system.membus.slave[2] +icache_port=system.membus.slave[1] + +[system.cpu.dtb] +type=RiscvTLB +eventq_index=0 +size=64 + +[system.cpu.interrupts] +type=RiscvInterrupts +eventq_index=0 + +[system.cpu.isa] +type=RiscvISA +eventq_index=0 + +[system.cpu.itb] +type=RiscvTLB +eventq_index=0 +size=64 + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=LiveProcess +cmd=insttest +cwd= +drivers= +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable=/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64a/insttest +gid=100 +input=cin +kvmInSE=false +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=0 +system=system +uid=100 +useArchPT=false + +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000000 + +[system.membus] +type=CoherentXBar +children=snoop_filter +clk_domain=system.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +forward_latency=4 +frontend_latency=3 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +point_of_coherency=true +power_model=Null +response_latency=2 +snoop_filter=system.membus.snoop_filter +snoop_response_latency=4 +system=system +use_default_range=false +width=16 +master=system.physmem.port +slave=system.system_port system.cpu.icache_port system.cpu.dcache_port + +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + +[system.physmem] +type=SimpleMemory +bandwidth=73.000000 +clk_domain=system.clk_domain +conf_table_reported=true +default_p_state=UNDEFINED +eventq_index=0 +in_addr_map=true +kvm_map=true +latency=30000 +latency_var=0 +null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +range=0:134217727:0:0:0:0 +port=system.membus.master[0] + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-atomic/config.json b/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-atomic/config.json new file mode 100644 index 000000000..3c887fa30 --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-atomic/config.json @@ -0,0 +1,289 @@ +{ + "name": null, + "sim_quantum": 0, + "system": { + "kernel": "", + "mmap_using_noreserve": false, + "kernel_addr_check": true, + "membus": { + "point_of_coherency": true, + "system": "system", + "response_latency": 2, + "cxx_class": "CoherentXBar", + "forward_latency": 4, + "clk_domain": "system.clk_domain", + "width": 16, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "master": { + "peer": [ + "system.physmem.port" + ], + "role": "MASTER" + }, + "type": "CoherentXBar", + "frontend_latency": 3, + "slave": { + "peer": [ + "system.system_port", + "system.cpu.icache_port", + "system.cpu.dcache_port" + ], + "role": "SLAVE" + }, + "p_state_clk_gate_min": 1000, + "snoop_filter": { + "name": "snoop_filter", + "system": "system", + "max_capacity": 8388608, + "eventq_index": 0, + "cxx_class": "SnoopFilter", + "path": "system.membus.snoop_filter", + "type": "SnoopFilter", + "lookup_latency": 1 + }, + "power_model": null, + "path": "system.membus", + "snoop_response_latency": 4, + "name": "membus", + "p_state_clk_gate_bins": 20, + "use_default_range": false + }, + "symbolfile": "", + "readfile": "", + "thermal_model": null, + "cxx_class": "System", + "work_begin_cpu_id_exit": -1, + "load_offset": 0, + "work_begin_exit_count": 0, + "p_state_clk_gate_min": 1000, + "memories": [ + "system.physmem" + ], + "work_begin_ckpt_count": 0, + "clk_domain": { + "name": "clk_domain", + "clock": [ + 1000 + ], + "init_perf_level": 0, + "voltage_domain": "system.voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "mem_ranges": [], + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "dvfs_handler": { + "enable": false, + "name": "dvfs_handler", + "sys_clk_domain": "system.clk_domain", + "transition_latency": 100000000, + "eventq_index": 0, + "cxx_class": "DVFSHandler", + "domains": [], + "path": "system.dvfs_handler", + "type": "DVFSHandler" + }, + "work_end_exit_count": 0, + "type": "System", + "voltage_domain": { + "name": "voltage_domain", + "eventq_index": 0, + "voltage": [ + "1.0" + ], + "cxx_class": "VoltageDomain", + "path": "system.voltage_domain", + "type": "VoltageDomain" + }, + "cache_line_size": 64, + "boot_osflags": "a", + "system_port": { + "peer": "system.membus.slave[0]", + "role": "MASTER" + }, + "physmem": { + "range": "0:134217727:0:0:0:0", + "latency": 30000, + "name": "physmem", + "p_state_clk_gate_min": 1000, + "eventq_index": 0, + "p_state_clk_gate_bins": 20, + "default_p_state": "UNDEFINED", + "kvm_map": true, + "clk_domain": "system.clk_domain", + "power_model": null, + "latency_var": 0, + "bandwidth": "73.000000", + "conf_table_reported": true, + "cxx_class": "SimpleMemory", + "p_state_clk_gate_max": 1000000000000, + "path": "system.physmem", + "null": false, + "type": "SimpleMemory", + "port": { + "peer": "system.membus.master[0]", + "role": "SLAVE" + }, + "in_addr_map": true + }, + "power_model": null, + "work_cpus_ckpt_count": 0, + "thermal_components": [], + "path": "system", + "cpu_clk_domain": { + "name": "cpu_clk_domain", + "clock": [ + 500 + ], + "init_perf_level": 0, + "voltage_domain": "system.voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.cpu_clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "work_end_ckpt_count": 0, + "mem_mode": "atomic", + "name": "system", + "init_param": 0, + "p_state_clk_gate_bins": 20, + "load_addr_mask": 1099511627775, + "cpu": [ + { + "do_statistics_insts": true, + "numThreads": 1, + "itb": { + "name": "itb", + "eventq_index": 0, + "cxx_class": "RiscvISA::TLB", + "path": "system.cpu.itb", + "type": "RiscvTLB", + "size": 64 + }, + "simulate_data_stalls": false, + "function_trace": false, + "do_checkpoint_insts": true, + "cxx_class": "AtomicSimpleCPU", + "max_loads_all_threads": 0, + "system": "system", + "clk_domain": "system.cpu_clk_domain", + "function_trace_start": 0, + "cpu_id": 0, + "width": 1, + "checker": null, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "do_quiesce": true, + "type": "AtomicSimpleCPU", + "fastmem": false, + "profile": 0, + "icache_port": { + "peer": "system.membus.slave[1]", + "role": "MASTER" + }, + "p_state_clk_gate_bins": 20, + "p_state_clk_gate_min": 1000, + "interrupts": [ + { + "eventq_index": 0, + "path": "system.cpu.interrupts", + "type": "RiscvInterrupts", + "name": "interrupts", + "cxx_class": "RiscvISA::Interrupts" + } + ], + "dcache_port": { + "peer": "system.membus.slave[2]", + "role": "MASTER" + }, + "socket_id": 0, + "power_model": null, + "max_insts_all_threads": 0, + "path": "system.cpu", + "max_loads_any_thread": 0, + "switched_out": false, + "workload": [ + { + "uid": 100, + "pid": 100, + "kvmInSE": false, + "cxx_class": "LiveProcess", + "executable": "/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64a/insttest", + "drivers": [], + "system": "system", + "gid": 100, + "eventq_index": 0, + "env": [], + "input": "cin", + "ppid": 99, + "type": "LiveProcess", + "cwd": "", + "simpoint": 0, + "euid": 100, + "path": "system.cpu.workload", + "max_stack_size": 67108864, + "name": "workload", + "cmd": [ + "insttest" + ], + "errout": "cerr", + "useArchPT": false, + "egid": 100, + "output": "cout" + } + ], + "name": "cpu", + "dtb": { + "name": "dtb", + "eventq_index": 0, + "cxx_class": "RiscvISA::TLB", + "path": "system.cpu.dtb", + "type": "RiscvTLB", + "size": 64 + }, + "simpoint_start_insts": [], + "max_insts_any_thread": 0, + "simulate_inst_stalls": false, + "progress_interval": 0, + "branchPred": null, + "isa": [ + { + "eventq_index": 0, + "path": "system.cpu.isa", + "type": "RiscvISA", + "name": "isa", + "cxx_class": "RiscvISA::ISA" + } + ], + "tracer": { + "eventq_index": 0, + "path": "system.cpu.tracer", + "type": "ExeTracer", + "name": "tracer", + "cxx_class": "Trace::ExeTracer" + } + } + ], + "multi_thread": false, + "exit_on_work_items": false, + "work_item_id": -1, + "num_work_ids": 16 + }, + "time_sync_period": 100000000000, + "eventq_index": 0, + "time_sync_spin_threshold": 100000000, + "cxx_class": "Root", + "path": "root", + "time_sync_enable": false, + "type": "Root", + "full_system": false +}
\ No newline at end of file diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-atomic/simerr b/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-atomic/simerr new file mode 100755 index 000000000..fd133b12b --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-atomic/simerr @@ -0,0 +1,3 @@ +warn: Unknown operating system; assuming Linux. +warn: Sockets disabled, not accepting gdb connections +warn: ClockedObject: More than one power state change request encountered within the same simulation tick diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-atomic/simout b/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-atomic/simout new file mode 100755 index 000000000..04963ca82 --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-atomic/simout @@ -0,0 +1,49 @@ +Redirecting stdout to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64a/simple-atomic/simout +Redirecting stderr to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64a/simple-atomic/simerr +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled Nov 30 2016 14:33:35 +gem5 started Nov 30 2016 16:18:29 +gem5 executing on zizzer, pid 34062 +command line: /z/powerjg/gem5-upstream/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64a/simple-atomic -re /z/powerjg/gem5-upstream/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64a/simple-atomic + +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. +lr.w/sc.w: PASS +sc.w, no preceding lr.d: PASS +amoswap.w: PASS +amoswap.w, sign extend: PASS +amoswap.w, truncate: PASS +amoadd.w: PASS +amoadd.w, truncate/overflow: PASS +amoadd.w, sign extend: PASS +amoxor.w, truncate: PASS +amoxor.w, sign extend: PASS +amoand.w, truncate: PASS +amoand.w, sign extend: PASS +amoor.w, truncate: PASS +amoor.w, sign extend: PASS +amomin.w, truncate: PASS +amomin.w, sign extend: PASS +amomax.w, truncate: PASS +amomax.w, sign extend: PASS +amominu.w, truncate: PASS +amominu.w, sign extend: PASS +amomaxu.w, truncate: PASS +amomaxu.w, sign extend: PASS +lr.d/sc.d: PASS +sc.d, no preceding lr.d: PASS +amoswap.d: PASS +amoadd.d: PASS +amoadd.d, overflow: PASS +amoxor.d (1): PASS +amoxor.d (0): PASS +amoand.d: PASS +amoor.d: PASS +amomin.d: PASS +amomax.d: PASS +amominu.d: PASS +amomaxu.d: PASS +Exiting @ tick 57010500 because target called exit() diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-atomic/stats.txt b/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-atomic/stats.txt new file mode 100644 index 000000000..07016a7d8 --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-atomic/stats.txt @@ -0,0 +1,156 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.000057 # Number of seconds simulated +sim_ticks 57010500 # Number of ticks simulated +final_tick 57010500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 83371 # Simulator instruction rate (inst/s) +host_op_rate 83392 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 41711101 # Simulator tick rate (ticks/s) +host_mem_usage 233576 # Number of bytes of host memory used +host_seconds 1.37 # Real time elapsed on the host +sim_insts 113947 # Number of instructions simulated +sim_ops 113978 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 57010500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 455964 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 156854 # Number of bytes read from this memory +system.physmem.bytes_read::total 612818 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 455964 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 455964 # Number of instructions bytes read from this memory +system.physmem.bytes_written::cpu.data 111519 # Number of bytes written to this memory +system.physmem.bytes_written::total 111519 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 113991 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 23779 # Number of read requests responded to by this memory +system.physmem.num_reads::total 137770 # Number of read requests responded to by this memory +system.physmem.num_writes::cpu.data 19912 # Number of write requests responded to by this memory +system.physmem.num_writes::total 19912 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 7997895125 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2751317740 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 10749212864 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 7997895125 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 7997895125 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1956113348 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1956113348 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 7997895125 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4707431087 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 12705326212 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 57010500 # Cumulative time (in ticks) in various power states +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 43 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 57010500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 114022 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 113947 # Number of instructions committed +system.cpu.committedOps 113978 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 113979 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses +system.cpu.num_func_calls 8601 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 17313 # number of instructions that are conditional controls +system.cpu.num_int_insts 113979 # number of integer instructions +system.cpu.num_fp_insts 0 # number of float instructions +system.cpu.num_int_register_reads 152039 # number of times the integer registers were read +system.cpu.num_int_register_writes 76786 # number of times the integer registers were written +system.cpu.num_fp_register_reads 0 # number of times the floating registers were read +system.cpu.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu.num_mem_refs 43694 # number of memory refs +system.cpu.num_load_insts 23779 # Number of load instructions +system.cpu.num_store_insts 19915 # Number of store instructions +system.cpu.num_idle_cycles 0 # Number of idle cycles +system.cpu.num_busy_cycles 114022 # Number of busy cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.Branches 25914 # Number of branches fetched +system.cpu.op_class::No_OpClass 43 0.04% 0.04% # Class of executed instruction +system.cpu.op_class::IntAlu 70180 61.55% 61.59% # Class of executed instruction +system.cpu.op_class::IntMult 105 0.09% 61.68% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 61.68% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 61.68% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 61.68% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 61.68% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 61.68% # Class of executed instruction +system.cpu.op_class::FloatMultAcc 0 0.00% 61.68% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 61.68% # Class of executed instruction +system.cpu.op_class::FloatMisc 0 0.00% 61.68% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 61.68% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 61.68% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 61.68% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 61.68% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 61.68% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 61.68% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 61.68% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 61.68% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 61.68% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 61.68% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 61.68% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 61.68% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 61.68% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 61.68% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 61.68% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 61.68% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 61.68% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 61.68% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 61.68% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 61.68% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 61.68% # Class of executed instruction +system.cpu.op_class::MemRead 23779 20.85% 82.53% # Class of executed instruction +system.cpu.op_class::MemWrite 19915 17.47% 100.00% # Class of executed instruction +system.cpu.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 114022 # Class of executed instruction +system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 57010500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadReq 137768 # Transaction distribution +system.membus.trans_dist::ReadResp 137770 # Transaction distribution +system.membus.trans_dist::WriteReq 19910 # Transaction distribution +system.membus.trans_dist::WriteResp 19910 # Transaction distribution +system.membus.trans_dist::LoadLockedReq 2 # Transaction distribution +system.membus.trans_dist::StoreCondReq 4 # Transaction distribution +system.membus.trans_dist::StoreCondResp 4 # Transaction distribution +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 227982 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 87386 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 315368 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 455964 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 268385 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 724349 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoopTraffic 0 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 157684 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 157684 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 157684 # Request fanout histogram + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing-ruby/config.ini b/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing-ruby/config.ini new file mode 100644 index 000000000..237a0f0d7 --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing-ruby/config.ini @@ -0,0 +1,1265 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000 +time_sync_spin_threshold=100000 + +[system] +type=System +children=clk_domain cpu dvfs_handler mem_ctrls ruby sys_port_proxy voltage_domain +boot_osflags=a +cache_line_size=64 +clk_domain=system.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +exit_on_work_items=false +init_param=0 +kernel= +kernel_addr_check=true +load_addr_mask=1099511627775 +load_offset=0 +mem_mode=timing +mem_ranges=0:268435455:0:0:0:0 +memories=system.mem_ctrls +mmap_using_noreserve=false +multi_thread=false +num_work_ids=16 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null +readfile= +symbolfile= +thermal_components= +thermal_model=Null +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.sys_port_proxy.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=TimingSimpleCPU +children=clk_domain dtb interrupts isa itb tracer workload +branchPred=Null +checker=Null +clk_domain=system.cpu.clk_domain +cpu_id=0 +default_p_state=UNDEFINED +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +eventq_index=0 +function_trace=false +function_trace_start=0 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null +profile=0 +progress_interval=0 +simpoint_start_insts= +socket_id=0 +switched_out=false +system=system +tracer=system.cpu.tracer +workload=system.cpu.workload +dcache_port=system.ruby.l1_cntrl0.sequencer.slave[1] +icache_port=system.ruby.l1_cntrl0.sequencer.slave[0] + +[system.cpu.clk_domain] +type=SrcClockDomain +clock=1 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu.dtb] +type=RiscvTLB +eventq_index=0 +size=64 + +[system.cpu.interrupts] +type=RiscvInterrupts +eventq_index=0 + +[system.cpu.isa] +type=RiscvISA +eventq_index=0 + +[system.cpu.itb] +type=RiscvTLB +eventq_index=0 +size=64 + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=LiveProcess +cmd=insttest +cwd= +drivers= +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable=/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64a/insttest +gid=100 +input=cin +kvmInSE=false +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=0 +system=system +uid=100 +useArchPT=false + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000 + +[system.mem_ctrls] +type=DRAMCtrl +IDD0=0.055000 +IDD02=0.000000 +IDD2N=0.032000 +IDD2N2=0.000000 +IDD2P0=0.000000 +IDD2P02=0.000000 +IDD2P1=0.032000 +IDD2P12=0.000000 +IDD3N=0.038000 +IDD3N2=0.000000 +IDD3P0=0.000000 +IDD3P02=0.000000 +IDD3P1=0.038000 +IDD3P12=0.000000 +IDD4R=0.157000 +IDD4R2=0.000000 +IDD4W=0.125000 +IDD4W2=0.000000 +IDD5=0.235000 +IDD52=0.000000 +IDD6=0.020000 +IDD62=0.000000 +VDD=1.500000 +VDD2=0.000000 +activation_limit=4 +addr_mapping=RoRaBaCoCh +bank_groups_per_rank=0 +banks_per_rank=8 +burst_length=8 +channels=1 +clk_domain=system.clk_domain +conf_table_reported=true +default_p_state=UNDEFINED +device_bus_width=8 +device_rowbuffer_size=1024 +device_size=536870912 +devices_per_rank=8 +dll=true +eventq_index=0 +in_addr_map=true +kvm_map=true +max_accesses_per_row=16 +mem_sched_policy=frfcfs +min_writes_per_switch=16 +null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +page_policy=open_adaptive +power_model=Null +range=0:268435455:5:19:0:0 +ranks_per_channel=2 +read_buffer_size=32 +static_backend_latency=10 +static_frontend_latency=10 +tBURST=5 +tCCD_L=0 +tCK=1 +tCL=14 +tCS=3 +tRAS=35 +tRCD=14 +tREFI=7800 +tRFC=260 +tRP=14 +tRRD=6 +tRRD_L=0 +tRTP=8 +tRTW=3 +tWR=15 +tWTR=8 +tXAW=30 +tXP=6 +tXPDLL=0 +tXS=270 +tXSDLL=0 +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 +port=system.ruby.dir_cntrl0.memory + +[system.ruby] +type=RubySystem +children=clk_domain dir_cntrl0 l1_cntrl0 memctrl_clk_domain network +access_backing_store=false +all_instructions=false +block_size_bytes=64 +clk_domain=system.ruby.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +hot_lines=false +memory_size_bits=48 +num_of_sequencers=1 +number_of_virtual_networks=5 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +phys_mem=Null +power_model=Null +randomization=false + +[system.ruby.clk_domain] +type=SrcClockDomain +clock=1 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.ruby.dir_cntrl0] +type=Directory_Controller +children=directory dmaRequestToDir dmaResponseFromDir forwardFromDir requestToDir responseFromDir responseFromMemory +buffer_size=0 +clk_domain=system.ruby.clk_domain +cluster_id=0 +default_p_state=UNDEFINED +directory=system.ruby.dir_cntrl0.directory +directory_latency=12 +dmaRequestToDir=system.ruby.dir_cntrl0.dmaRequestToDir +dmaResponseFromDir=system.ruby.dir_cntrl0.dmaResponseFromDir +eventq_index=0 +forwardFromDir=system.ruby.dir_cntrl0.forwardFromDir +number_of_TBEs=256 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null +recycle_latency=10 +requestToDir=system.ruby.dir_cntrl0.requestToDir +responseFromDir=system.ruby.dir_cntrl0.responseFromDir +responseFromMemory=system.ruby.dir_cntrl0.responseFromMemory +ruby_system=system.ruby +system=system +to_memory_controller_latency=1 +transitions_per_cycle=4 +version=0 +memory=system.mem_ctrls.port + +[system.ruby.dir_cntrl0.directory] +type=RubyDirectoryMemory +eventq_index=0 +numa_high_bit=5 +size=268435456 +version=0 + +[system.ruby.dir_cntrl0.dmaRequestToDir] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +slave=system.ruby.network.master[3] + +[system.ruby.dir_cntrl0.dmaResponseFromDir] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +master=system.ruby.network.slave[3] + +[system.ruby.dir_cntrl0.forwardFromDir] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=false +randomization=false +master=system.ruby.network.slave[4] + +[system.ruby.dir_cntrl0.requestToDir] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +slave=system.ruby.network.master[2] + +[system.ruby.dir_cntrl0.responseFromDir] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=false +randomization=false +master=system.ruby.network.slave[2] + +[system.ruby.dir_cntrl0.responseFromMemory] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=false +randomization=false + +[system.ruby.l1_cntrl0] +type=L1Cache_Controller +children=cacheMemory forwardToCache mandatoryQueue requestFromCache responseFromCache responseToCache sequencer +buffer_size=0 +cacheMemory=system.ruby.l1_cntrl0.cacheMemory +cache_response_latency=12 +clk_domain=system.cpu.clk_domain +cluster_id=0 +default_p_state=UNDEFINED +eventq_index=0 +forwardToCache=system.ruby.l1_cntrl0.forwardToCache +issue_latency=2 +mandatoryQueue=system.ruby.l1_cntrl0.mandatoryQueue +number_of_TBEs=256 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null +recycle_latency=10 +requestFromCache=system.ruby.l1_cntrl0.requestFromCache +responseFromCache=system.ruby.l1_cntrl0.responseFromCache +responseToCache=system.ruby.l1_cntrl0.responseToCache +ruby_system=system.ruby +send_evictions=false +sequencer=system.ruby.l1_cntrl0.sequencer +system=system +transitions_per_cycle=4 +version=0 + +[system.ruby.l1_cntrl0.cacheMemory] +type=RubyCache +children=replacement_policy +assoc=2 +block_size=0 +dataAccessLatency=1 +dataArrayBanks=1 +eventq_index=0 +is_icache=false +replacement_policy=system.ruby.l1_cntrl0.cacheMemory.replacement_policy +resourceStalls=false +ruby_system=system.ruby +size=256 +start_index_bit=6 +tagAccessLatency=1 +tagArrayBanks=1 + +[system.ruby.l1_cntrl0.cacheMemory.replacement_policy] +type=PseudoLRUReplacementPolicy +assoc=2 +block_size=64 +eventq_index=0 +size=256 + +[system.ruby.l1_cntrl0.forwardToCache] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +slave=system.ruby.network.master[0] + +[system.ruby.l1_cntrl0.mandatoryQueue] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=false +randomization=false + +[system.ruby.l1_cntrl0.requestFromCache] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +master=system.ruby.network.slave[0] + +[system.ruby.l1_cntrl0.responseFromCache] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +master=system.ruby.network.slave[1] + +[system.ruby.l1_cntrl0.responseToCache] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +slave=system.ruby.network.master[1] + +[system.ruby.l1_cntrl0.sequencer] +type=RubySequencer +clk_domain=system.cpu.clk_domain +coreid=99 +dcache=system.ruby.l1_cntrl0.cacheMemory +dcache_hit_latency=1 +deadlock_threshold=500000 +default_p_state=UNDEFINED +eventq_index=0 +garnet_standalone=false +icache=system.ruby.l1_cntrl0.cacheMemory +icache_hit_latency=1 +is_cpu_sequencer=true +max_outstanding_requests=16 +no_retry_on_stall=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null +ruby_system=system.ruby +support_data_reqs=true +support_inst_reqs=true +system=system +using_ruby_tester=false +version=0 +slave=system.cpu.icache_port system.cpu.dcache_port + +[system.ruby.memctrl_clk_domain] +type=DerivedClockDomain +clk_divider=3 +clk_domain=system.ruby.clk_domain +eventq_index=0 + +[system.ruby.network] +type=SimpleNetwork +children=ext_links0 ext_links1 int_link_buffers00 int_link_buffers01 int_link_buffers02 int_link_buffers03 int_link_buffers04 int_link_buffers05 int_link_buffers06 int_link_buffers07 int_link_buffers08 int_link_buffers09 int_link_buffers10 int_link_buffers11 int_link_buffers12 int_link_buffers13 int_link_buffers14 int_link_buffers15 int_link_buffers16 int_link_buffers17 int_link_buffers18 int_link_buffers19 int_link_buffers20 int_link_buffers21 int_link_buffers22 int_link_buffers23 int_link_buffers24 int_link_buffers25 int_link_buffers26 int_link_buffers27 int_link_buffers28 int_link_buffers29 int_link_buffers30 int_link_buffers31 int_link_buffers32 int_link_buffers33 int_link_buffers34 int_link_buffers35 int_link_buffers36 int_link_buffers37 int_link_buffers38 int_link_buffers39 int_links0 int_links1 int_links2 int_links3 routers0 routers1 routers2 +adaptive_routing=false +buffer_size=0 +clk_domain=system.ruby.clk_domain +control_msg_size=8 +default_p_state=UNDEFINED +endpoint_bandwidth=1000 +eventq_index=0 +ext_links=system.ruby.network.ext_links0 system.ruby.network.ext_links1 +int_link_buffers=system.ruby.network.int_link_buffers00 system.ruby.network.int_link_buffers01 system.ruby.network.int_link_buffers02 system.ruby.network.int_link_buffers03 system.ruby.network.int_link_buffers04 system.ruby.network.int_link_buffers05 system.ruby.network.int_link_buffers06 system.ruby.network.int_link_buffers07 system.ruby.network.int_link_buffers08 system.ruby.network.int_link_buffers09 system.ruby.network.int_link_buffers10 system.ruby.network.int_link_buffers11 system.ruby.network.int_link_buffers12 system.ruby.network.int_link_buffers13 system.ruby.network.int_link_buffers14 system.ruby.network.int_link_buffers15 system.ruby.network.int_link_buffers16 system.ruby.network.int_link_buffers17 system.ruby.network.int_link_buffers18 system.ruby.network.int_link_buffers19 system.ruby.network.int_link_buffers20 system.ruby.network.int_link_buffers21 system.ruby.network.int_link_buffers22 system.ruby.network.int_link_buffers23 system.ruby.network.int_link_buffers24 system.ruby.network.int_link_buffers25 system.ruby.network.int_link_buffers26 system.ruby.network.int_link_buffers27 system.ruby.network.int_link_buffers28 system.ruby.network.int_link_buffers29 system.ruby.network.int_link_buffers30 system.ruby.network.int_link_buffers31 system.ruby.network.int_link_buffers32 system.ruby.network.int_link_buffers33 system.ruby.network.int_link_buffers34 system.ruby.network.int_link_buffers35 system.ruby.network.int_link_buffers36 system.ruby.network.int_link_buffers37 system.ruby.network.int_link_buffers38 system.ruby.network.int_link_buffers39 +int_links=system.ruby.network.int_links0 system.ruby.network.int_links1 system.ruby.network.int_links2 system.ruby.network.int_links3 +netifs= +number_of_virtual_networks=5 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null +routers=system.ruby.network.routers0 system.ruby.network.routers1 system.ruby.network.routers2 +ruby_system=system.ruby +topology=Crossbar +master=system.ruby.l1_cntrl0.forwardToCache.slave system.ruby.l1_cntrl0.responseToCache.slave system.ruby.dir_cntrl0.requestToDir.slave system.ruby.dir_cntrl0.dmaRequestToDir.slave +slave=system.ruby.l1_cntrl0.requestFromCache.master system.ruby.l1_cntrl0.responseFromCache.master system.ruby.dir_cntrl0.responseFromDir.master system.ruby.dir_cntrl0.dmaResponseFromDir.master system.ruby.dir_cntrl0.forwardFromDir.master + +[system.ruby.network.ext_links0] +type=SimpleExtLink +bandwidth_factor=16 +eventq_index=0 +ext_node=system.ruby.l1_cntrl0 +int_node=system.ruby.network.routers0 +latency=1 +link_id=0 +weight=1 + +[system.ruby.network.ext_links1] +type=SimpleExtLink +bandwidth_factor=16 +eventq_index=0 +ext_node=system.ruby.dir_cntrl0 +int_node=system.ruby.network.routers1 +latency=1 +link_id=1 +weight=1 + +[system.ruby.network.int_link_buffers00] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers01] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers02] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers03] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers04] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers05] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers06] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers07] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers08] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers09] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers10] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers11] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers12] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers13] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers14] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers15] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers16] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers17] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers18] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers19] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers20] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers21] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers22] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers23] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers24] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers25] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers26] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers27] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers28] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers29] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers30] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers31] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers32] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers33] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers34] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers35] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers36] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers37] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers38] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers39] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_links0] +type=SimpleIntLink +bandwidth_factor=16 +dst_inport= +dst_node=system.ruby.network.routers2 +eventq_index=0 +latency=1 +link_id=2 +src_node=system.ruby.network.routers0 +src_outport= +weight=1 + +[system.ruby.network.int_links1] +type=SimpleIntLink +bandwidth_factor=16 +dst_inport= +dst_node=system.ruby.network.routers2 +eventq_index=0 +latency=1 +link_id=3 +src_node=system.ruby.network.routers1 +src_outport= +weight=1 + +[system.ruby.network.int_links2] +type=SimpleIntLink +bandwidth_factor=16 +dst_inport= +dst_node=system.ruby.network.routers0 +eventq_index=0 +latency=1 +link_id=4 +src_node=system.ruby.network.routers2 +src_outport= +weight=1 + +[system.ruby.network.int_links3] +type=SimpleIntLink +bandwidth_factor=16 +dst_inport= +dst_node=system.ruby.network.routers1 +eventq_index=0 +latency=1 +link_id=5 +src_node=system.ruby.network.routers2 +src_outport= +weight=1 + +[system.ruby.network.routers0] +type=Switch +children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14 +clk_domain=system.ruby.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +port_buffers=system.ruby.network.routers0.port_buffers00 system.ruby.network.routers0.port_buffers01 system.ruby.network.routers0.port_buffers02 system.ruby.network.routers0.port_buffers03 system.ruby.network.routers0.port_buffers04 system.ruby.network.routers0.port_buffers05 system.ruby.network.routers0.port_buffers06 system.ruby.network.routers0.port_buffers07 system.ruby.network.routers0.port_buffers08 system.ruby.network.routers0.port_buffers09 system.ruby.network.routers0.port_buffers10 system.ruby.network.routers0.port_buffers11 system.ruby.network.routers0.port_buffers12 system.ruby.network.routers0.port_buffers13 system.ruby.network.routers0.port_buffers14 +power_model=Null +router_id=0 +virt_nets=5 + +[system.ruby.network.routers0.port_buffers00] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers0.port_buffers01] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers0.port_buffers02] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers0.port_buffers03] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers0.port_buffers04] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers0.port_buffers05] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers0.port_buffers06] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers0.port_buffers07] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers0.port_buffers08] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers0.port_buffers09] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers0.port_buffers10] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers0.port_buffers11] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers0.port_buffers12] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers0.port_buffers13] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers0.port_buffers14] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers1] +type=Switch +children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14 +clk_domain=system.ruby.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +port_buffers=system.ruby.network.routers1.port_buffers00 system.ruby.network.routers1.port_buffers01 system.ruby.network.routers1.port_buffers02 system.ruby.network.routers1.port_buffers03 system.ruby.network.routers1.port_buffers04 system.ruby.network.routers1.port_buffers05 system.ruby.network.routers1.port_buffers06 system.ruby.network.routers1.port_buffers07 system.ruby.network.routers1.port_buffers08 system.ruby.network.routers1.port_buffers09 system.ruby.network.routers1.port_buffers10 system.ruby.network.routers1.port_buffers11 system.ruby.network.routers1.port_buffers12 system.ruby.network.routers1.port_buffers13 system.ruby.network.routers1.port_buffers14 +power_model=Null +router_id=1 +virt_nets=5 + +[system.ruby.network.routers1.port_buffers00] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers1.port_buffers01] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers1.port_buffers02] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers1.port_buffers03] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers1.port_buffers04] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers1.port_buffers05] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers1.port_buffers06] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers1.port_buffers07] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers1.port_buffers08] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers1.port_buffers09] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers1.port_buffers10] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers1.port_buffers11] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers1.port_buffers12] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers1.port_buffers13] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers1.port_buffers14] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2] +type=Switch +children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14 port_buffers15 port_buffers16 port_buffers17 port_buffers18 port_buffers19 +clk_domain=system.ruby.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +port_buffers=system.ruby.network.routers2.port_buffers00 system.ruby.network.routers2.port_buffers01 system.ruby.network.routers2.port_buffers02 system.ruby.network.routers2.port_buffers03 system.ruby.network.routers2.port_buffers04 system.ruby.network.routers2.port_buffers05 system.ruby.network.routers2.port_buffers06 system.ruby.network.routers2.port_buffers07 system.ruby.network.routers2.port_buffers08 system.ruby.network.routers2.port_buffers09 system.ruby.network.routers2.port_buffers10 system.ruby.network.routers2.port_buffers11 system.ruby.network.routers2.port_buffers12 system.ruby.network.routers2.port_buffers13 system.ruby.network.routers2.port_buffers14 system.ruby.network.routers2.port_buffers15 system.ruby.network.routers2.port_buffers16 system.ruby.network.routers2.port_buffers17 system.ruby.network.routers2.port_buffers18 system.ruby.network.routers2.port_buffers19 +power_model=Null +router_id=2 +virt_nets=5 + +[system.ruby.network.routers2.port_buffers00] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers01] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers02] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers03] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers04] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers05] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers06] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers07] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers08] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers09] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers10] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers11] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers12] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers13] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers14] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers15] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers16] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers17] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers18] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers19] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.sys_port_proxy] +type=RubyPortProxy +clk_domain=system.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +is_cpu_sequencer=true +no_retry_on_stall=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null +ruby_system=system.ruby +support_data_reqs=true +support_inst_reqs=true +system=system +using_ruby_tester=false +version=0 +slave=system.system_port + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing-ruby/config.json b/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing-ruby/config.json new file mode 100644 index 000000000..00786271a --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing-ruby/config.json @@ -0,0 +1,1734 @@ +{ + "name": null, + "sim_quantum": 0, + "system": { + "kernel": "", + "mmap_using_noreserve": false, + "kernel_addr_check": true, + "symbolfile": "", + "readfile": "", + "thermal_model": null, + "cxx_class": "System", + "work_begin_cpu_id_exit": -1, + "load_offset": 0, + "work_begin_exit_count": 0, + "p_state_clk_gate_min": 1, + "memories": [ + "system.mem_ctrls" + ], + "work_begin_ckpt_count": 0, + "clk_domain": { + "name": "clk_domain", + "clock": [ + 1 + ], + "init_perf_level": 0, + "voltage_domain": "system.voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "mem_ranges": [ + "0:268435455:0:0:0:0" + ], + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000, + "dvfs_handler": { + "enable": false, + "name": "dvfs_handler", + "sys_clk_domain": "system.clk_domain", + "transition_latency": 100000, + "eventq_index": 0, + "cxx_class": "DVFSHandler", + "domains": [], + "path": "system.dvfs_handler", + "type": "DVFSHandler" + }, + "work_end_exit_count": 0, + "type": "System", + "voltage_domain": { + "name": "voltage_domain", + "eventq_index": 0, + "voltage": [ + "1.0" + ], + "cxx_class": "VoltageDomain", + "path": "system.voltage_domain", + "type": "VoltageDomain" + }, + "cache_line_size": 64, + "boot_osflags": "a", + "system_port": { + "peer": "system.sys_port_proxy.slave[0]", + "role": "MASTER" + }, + "sys_port_proxy": { + "system": "system", + "support_inst_reqs": true, + "slave": { + "peer": [ + "system.system_port" + ], + "role": "SLAVE" + }, + "name": "sys_port_proxy", + "p_state_clk_gate_min": 1, + "no_retry_on_stall": false, + "p_state_clk_gate_bins": 20, + "support_data_reqs": true, + "cxx_class": "RubyPortProxy", + "clk_domain": "system.clk_domain", + "power_model": null, + "is_cpu_sequencer": true, + "version": 0, + "eventq_index": 0, + "using_ruby_tester": false, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000, + "path": "system.sys_port_proxy", + "type": "RubyPortProxy", + "ruby_system": "system.ruby" + }, + "power_model": null, + "work_cpus_ckpt_count": 0, + "thermal_components": [], + "path": "system", + "ruby": { + "all_instructions": false, + "memory_size_bits": 48, + "cxx_class": "RubySystem", + "l1_cntrl0": { + "requestFromCache": { + "ordered": true, + "name": "requestFromCache", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "master": { + "peer": "system.ruby.network.slave[0]", + "role": "MASTER" + }, + "buffer_size": 0, + "path": "system.ruby.l1_cntrl0.requestFromCache", + "type": "MessageBuffer" + }, + "cxx_class": "L1Cache_Controller", + "forwardToCache": { + "ordered": true, + "name": "forwardToCache", + "cxx_class": "MessageBuffer", + "slave": { + "peer": "system.ruby.network.master[0]", + "role": "SLAVE" + }, + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.l1_cntrl0.forwardToCache", + "type": "MessageBuffer" + }, + "system": "system", + "cluster_id": 0, + "sequencer": { + "no_retry_on_stall": false, + "deadlock_threshold": 500000, + "using_ruby_tester": false, + "system": "system", + "dcache": "system.ruby.l1_cntrl0.cacheMemory", + "cxx_class": "Sequencer", + "garnet_standalone": false, + "clk_domain": "system.cpu.clk_domain", + "icache_hit_latency": 1, + "version": 0, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000, + "type": "RubySequencer", + "icache": "system.ruby.l1_cntrl0.cacheMemory", + "slave": { + "peer": [ + "system.cpu.icache_port", + "system.cpu.dcache_port" + ], + "role": "SLAVE" + }, + "p_state_clk_gate_min": 1, + "power_model": null, + "coreid": 99, + "path": "system.ruby.l1_cntrl0.sequencer", + "ruby_system": "system.ruby", + "support_inst_reqs": true, + "name": "sequencer", + "max_outstanding_requests": 16, + "p_state_clk_gate_bins": 20, + "dcache_hit_latency": 1, + "support_data_reqs": true, + "is_cpu_sequencer": true + }, + "type": "L1Cache_Controller", + "issue_latency": 2, + "recycle_latency": 10, + "clk_domain": "system.cpu.clk_domain", + "version": 0, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000, + "number_of_TBEs": 256, + "p_state_clk_gate_min": 1, + "responseToCache": { + "ordered": true, + "name": "responseToCache", + "cxx_class": "MessageBuffer", + "slave": { + "peer": "system.ruby.network.master[1]", + "role": "SLAVE" + }, + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.l1_cntrl0.responseToCache", + "type": "MessageBuffer" + }, + "transitions_per_cycle": 4, + "responseFromCache": { + "ordered": true, + "name": "responseFromCache", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "master": { + "peer": "system.ruby.network.slave[1]", + "role": "MASTER" + }, + "buffer_size": 0, + "path": "system.ruby.l1_cntrl0.responseFromCache", + "type": "MessageBuffer" + }, + "power_model": null, + "cache_response_latency": 12, + "buffer_size": 0, + "send_evictions": false, + "cacheMemory": { + "size": 256, + "resourceStalls": false, + "is_icache": false, + "name": "cacheMemory", + "eventq_index": 0, + "dataAccessLatency": 1, + "tagArrayBanks": 1, + "tagAccessLatency": 1, + "replacement_policy": { + "name": "replacement_policy", + "eventq_index": 0, + "assoc": 2, + "cxx_class": "PseudoLRUPolicy", + "path": "system.ruby.l1_cntrl0.cacheMemory.replacement_policy", + "block_size": 64, + "type": "PseudoLRUReplacementPolicy", + "size": 256 + }, + "assoc": 2, + "start_index_bit": 6, + "cxx_class": "CacheMemory", + "path": "system.ruby.l1_cntrl0.cacheMemory", + "block_size": 0, + "type": "RubyCache", + "dataArrayBanks": 1, + "ruby_system": "system.ruby" + }, + "ruby_system": "system.ruby", + "name": "l1_cntrl0", + "p_state_clk_gate_bins": 20, + "mandatoryQueue": { + "ordered": false, + "name": "mandatoryQueue", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.l1_cntrl0.mandatoryQueue", + "type": "MessageBuffer" + }, + "path": "system.ruby.l1_cntrl0" + }, + "network": { + "int_link_buffers": [ + { + "ordered": true, + "name": "int_link_buffers00", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers00", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers01", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers01", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers02", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers02", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers03", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers03", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers04", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers04", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers05", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers05", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers06", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers06", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers07", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers07", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers08", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers08", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers09", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers09", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers10", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers10", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers11", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers11", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers12", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers12", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers13", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers13", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers14", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers14", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers15", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers15", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers16", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers16", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers17", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers17", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers18", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers18", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers19", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers19", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers20", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers20", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers21", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers21", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers22", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers22", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers23", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers23", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers24", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers24", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers25", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers25", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers26", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers26", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers27", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers27", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers28", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers28", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers29", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers29", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers30", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers30", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers31", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers31", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers32", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers32", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers33", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers33", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers34", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers34", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers35", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers35", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers36", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers36", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers37", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers37", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers38", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers38", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers39", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers39", + "type": "MessageBuffer" + } + ], + "cxx_class": "SimpleNetwork", + "clk_domain": "system.ruby.clk_domain", + "adaptive_routing": false, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000, + "master": { + "peer": [ + "system.ruby.l1_cntrl0.forwardToCache.slave", + "system.ruby.l1_cntrl0.responseToCache.slave", + "system.ruby.dir_cntrl0.requestToDir.slave", + "system.ruby.dir_cntrl0.dmaRequestToDir.slave" + ], + "role": "MASTER" + }, + "topology": "Crossbar", + "type": "SimpleNetwork", + "slave": { + "peer": [ + "system.ruby.l1_cntrl0.requestFromCache.master", + "system.ruby.l1_cntrl0.responseFromCache.master", + "system.ruby.dir_cntrl0.responseFromDir.master", + "system.ruby.dir_cntrl0.dmaResponseFromDir.master", + "system.ruby.dir_cntrl0.forwardFromDir.master" + ], + "role": "SLAVE" + }, + "p_state_clk_gate_min": 1, + "int_links": [ + { + "latency": 1, + "name": "int_links0", + "weight": 1, + "src_node": "system.ruby.network.routers0", + "dst_inport": "", + "link_id": 2, + "dst_node": "system.ruby.network.routers2", + "eventq_index": 0, + "src_outport": "", + "cxx_class": "SimpleIntLink", + "path": "system.ruby.network.int_links0", + "type": "SimpleIntLink", + "bandwidth_factor": 16 + }, + { + "latency": 1, + "name": "int_links1", + "weight": 1, + "src_node": "system.ruby.network.routers1", + "dst_inport": "", + "link_id": 3, + "dst_node": "system.ruby.network.routers2", + "eventq_index": 0, + "src_outport": "", + "cxx_class": "SimpleIntLink", + "path": "system.ruby.network.int_links1", + "type": "SimpleIntLink", + "bandwidth_factor": 16 + }, + { + "latency": 1, + "name": "int_links2", + "weight": 1, + "src_node": "system.ruby.network.routers2", + "dst_inport": "", + "link_id": 4, + "dst_node": "system.ruby.network.routers0", + "eventq_index": 0, + "src_outport": "", + "cxx_class": "SimpleIntLink", + "path": "system.ruby.network.int_links2", + "type": "SimpleIntLink", + "bandwidth_factor": 16 + }, + { + "latency": 1, + "name": "int_links3", + "weight": 1, + "src_node": "system.ruby.network.routers2", + "dst_inport": "", + "link_id": 5, + "dst_node": "system.ruby.network.routers1", + "eventq_index": 0, + "src_outport": "", + "cxx_class": "SimpleIntLink", + "path": "system.ruby.network.int_links3", + "type": "SimpleIntLink", + "bandwidth_factor": 16 + } + ], + "routers": [ + { + "router_id": 0, + "latency": 1, + "name": "routers0", + "p_state_clk_gate_min": 1, + "virt_nets": 5, + "p_state_clk_gate_bins": 20, + "cxx_class": "Switch", + "clk_domain": "system.ruby.clk_domain", + "power_model": null, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000, + "path": "system.ruby.network.routers0", + "type": "Switch", + "port_buffers": [ + { + "ordered": true, + "name": "port_buffers00", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers0.port_buffers00", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers01", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers0.port_buffers01", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers02", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers0.port_buffers02", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers03", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers0.port_buffers03", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers04", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers0.port_buffers04", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers05", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers0.port_buffers05", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers06", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers0.port_buffers06", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers07", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers0.port_buffers07", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers08", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers0.port_buffers08", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers09", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers0.port_buffers09", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers10", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers0.port_buffers10", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers11", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers0.port_buffers11", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers12", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers0.port_buffers12", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers13", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers0.port_buffers13", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers14", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers0.port_buffers14", + "type": "MessageBuffer" + } + ] + }, + { + "router_id": 1, + "latency": 1, + "name": "routers1", + "p_state_clk_gate_min": 1, + "virt_nets": 5, + "p_state_clk_gate_bins": 20, + "cxx_class": "Switch", + "clk_domain": "system.ruby.clk_domain", + "power_model": null, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000, + "path": "system.ruby.network.routers1", + "type": "Switch", + "port_buffers": [ + { + "ordered": true, + "name": "port_buffers00", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers1.port_buffers00", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers01", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers1.port_buffers01", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers02", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers1.port_buffers02", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers03", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers1.port_buffers03", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers04", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers1.port_buffers04", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers05", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers1.port_buffers05", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers06", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers1.port_buffers06", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers07", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers1.port_buffers07", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers08", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers1.port_buffers08", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers09", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers1.port_buffers09", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers10", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers1.port_buffers10", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers11", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers1.port_buffers11", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers12", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers1.port_buffers12", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers13", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers1.port_buffers13", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers14", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers1.port_buffers14", + "type": "MessageBuffer" + } + ] + }, + { + "router_id": 2, + "latency": 1, + "name": "routers2", + "p_state_clk_gate_min": 1, + "virt_nets": 5, + "p_state_clk_gate_bins": 20, + "cxx_class": "Switch", + "clk_domain": "system.ruby.clk_domain", + "power_model": null, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000, + "path": "system.ruby.network.routers2", + "type": "Switch", + "port_buffers": [ + { + "ordered": true, + "name": "port_buffers00", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers2.port_buffers00", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers01", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers2.port_buffers01", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers02", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers2.port_buffers02", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers03", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers2.port_buffers03", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers04", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers2.port_buffers04", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers05", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers2.port_buffers05", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers06", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers2.port_buffers06", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers07", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers2.port_buffers07", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers08", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers2.port_buffers08", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers09", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers2.port_buffers09", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers10", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers2.port_buffers10", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers11", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers2.port_buffers11", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers12", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers2.port_buffers12", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers13", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers2.port_buffers13", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers14", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers2.port_buffers14", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers15", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers2.port_buffers15", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers16", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers2.port_buffers16", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers17", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers2.port_buffers17", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers18", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers2.port_buffers18", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers19", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers2.port_buffers19", + "type": "MessageBuffer" + } + ] + } + ], + "power_model": null, + "netifs": [], + "control_msg_size": 8, + "buffer_size": 0, + "endpoint_bandwidth": 1000, + "ruby_system": "system.ruby", + "name": "network", + "p_state_clk_gate_bins": 20, + "ext_links": [ + { + "latency": 1, + "name": "ext_links0", + "weight": 1, + "ext_node": "system.ruby.l1_cntrl0", + "link_id": 0, + "eventq_index": 0, + "cxx_class": "SimpleExtLink", + "path": "system.ruby.network.ext_links0", + "int_node": "system.ruby.network.routers0", + "type": "SimpleExtLink", + "bandwidth_factor": 16 + }, + { + "latency": 1, + "name": "ext_links1", + "weight": 1, + "ext_node": "system.ruby.dir_cntrl0", + "link_id": 1, + "eventq_index": 0, + "cxx_class": "SimpleExtLink", + "path": "system.ruby.network.ext_links1", + "int_node": "system.ruby.network.routers1", + "type": "SimpleExtLink", + "bandwidth_factor": 16 + } + ], + "number_of_virtual_networks": 5, + "path": "system.ruby.network" + }, + "clk_domain": { + "name": "clk_domain", + "clock": [ + 1 + ], + "init_perf_level": 0, + "voltage_domain": "system.voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.ruby.clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "randomization": false, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000, + "phys_mem": null, + "type": "RubySystem", + "p_state_clk_gate_min": 1, + "hot_lines": false, + "power_model": null, + "path": "system.ruby", + "memctrl_clk_domain": { + "name": "memctrl_clk_domain", + "clk_domain": "system.ruby.clk_domain", + "eventq_index": 0, + "cxx_class": "DerivedClockDomain", + "path": "system.ruby.memctrl_clk_domain", + "type": "DerivedClockDomain", + "clk_divider": 3 + }, + "name": "ruby", + "p_state_clk_gate_bins": 20, + "block_size_bytes": 64, + "access_backing_store": false, + "number_of_virtual_networks": 5, + "num_of_sequencers": 1, + "dir_cntrl0": { + "system": "system", + "cluster_id": 0, + "responseFromMemory": { + "ordered": false, + "name": "responseFromMemory", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.dir_cntrl0.responseFromMemory", + "type": "MessageBuffer" + }, + "cxx_class": "Directory_Controller", + "forwardFromDir": { + "ordered": false, + "name": "forwardFromDir", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "master": { + "peer": "system.ruby.network.slave[4]", + "role": "MASTER" + }, + "buffer_size": 0, + "path": "system.ruby.dir_cntrl0.forwardFromDir", + "type": "MessageBuffer" + }, + "dmaRequestToDir": { + "ordered": true, + "name": "dmaRequestToDir", + "cxx_class": "MessageBuffer", + "slave": { + "peer": "system.ruby.network.master[3]", + "role": "SLAVE" + }, + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.dir_cntrl0.dmaRequestToDir", + "type": "MessageBuffer" + }, + "type": "Directory_Controller", + "recycle_latency": 10, + "clk_domain": "system.ruby.clk_domain", + "version": 0, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000, + "directory_latency": 12, + "number_of_TBEs": 256, + "to_memory_controller_latency": 1, + "p_state_clk_gate_min": 1, + "responseFromDir": { + "ordered": false, + "name": "responseFromDir", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "master": { + "peer": "system.ruby.network.slave[2]", + "role": "MASTER" + }, + "buffer_size": 0, + "path": "system.ruby.dir_cntrl0.responseFromDir", + "type": "MessageBuffer" + }, + "transitions_per_cycle": 4, + "memory": { + "peer": "system.mem_ctrls.port", + "role": "MASTER" + }, + "power_model": null, + "buffer_size": 0, + "ruby_system": "system.ruby", + "requestToDir": { + "ordered": true, + "name": "requestToDir", + "cxx_class": "MessageBuffer", + "slave": { + "peer": "system.ruby.network.master[2]", + "role": "SLAVE" + }, + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.dir_cntrl0.requestToDir", + "type": "MessageBuffer" + }, + "dmaResponseFromDir": { + "ordered": true, + "name": "dmaResponseFromDir", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "master": { + "peer": "system.ruby.network.slave[3]", + "role": "MASTER" + }, + "buffer_size": 0, + "path": "system.ruby.dir_cntrl0.dmaResponseFromDir", + "type": "MessageBuffer" + }, + "name": "dir_cntrl0", + "p_state_clk_gate_bins": 20, + "directory": { + "name": "directory", + "version": 0, + "eventq_index": 0, + "cxx_class": "DirectoryMemory", + "path": "system.ruby.dir_cntrl0.directory", + "type": "RubyDirectoryMemory", + "numa_high_bit": 5, + "size": 268435456 + }, + "path": "system.ruby.dir_cntrl0" + } + }, + "work_end_ckpt_count": 0, + "mem_mode": "timing", + "name": "system", + "init_param": 0, + "p_state_clk_gate_bins": 20, + "load_addr_mask": 1099511627775, + "cpu": { + "do_statistics_insts": true, + "numThreads": 1, + "itb": { + "name": "itb", + "eventq_index": 0, + "cxx_class": "RiscvISA::TLB", + "path": "system.cpu.itb", + "type": "RiscvTLB", + "size": 64 + }, + "system": "system", + "function_trace": false, + "do_checkpoint_insts": true, + "cxx_class": "TimingSimpleCPU", + "max_loads_all_threads": 0, + "clk_domain": { + "name": "clk_domain", + "clock": [ + 1 + ], + "init_perf_level": 0, + "voltage_domain": "system.voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.cpu.clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "function_trace_start": 0, + "cpu_id": 0, + "checker": null, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000, + "do_quiesce": true, + "type": "TimingSimpleCPU", + "profile": 0, + "icache_port": { + "peer": "system.ruby.l1_cntrl0.sequencer.slave[0]", + "role": "MASTER" + }, + "p_state_clk_gate_bins": 20, + "p_state_clk_gate_min": 1, + "interrupts": [ + { + "eventq_index": 0, + "path": "system.cpu.interrupts", + "type": "RiscvInterrupts", + "name": "interrupts", + "cxx_class": "RiscvISA::Interrupts" + } + ], + "dcache_port": { + "peer": "system.ruby.l1_cntrl0.sequencer.slave[1]", + "role": "MASTER" + }, + "socket_id": 0, + "power_model": null, + "max_insts_all_threads": 0, + "path": "system.cpu", + "max_loads_any_thread": 0, + "switched_out": false, + "workload": [ + { + "uid": 100, + "pid": 100, + "kvmInSE": false, + "cxx_class": "LiveProcess", + "executable": "/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64a/insttest", + "drivers": [], + "system": "system", + "gid": 100, + "eventq_index": 0, + "env": [], + "input": "cin", + "ppid": 99, + "type": "LiveProcess", + "cwd": "", + "simpoint": 0, + "euid": 100, + "path": "system.cpu.workload", + "max_stack_size": 67108864, + "name": "workload", + "cmd": [ + "insttest" + ], + "errout": "cerr", + "useArchPT": false, + "egid": 100, + "output": "cout" + } + ], + "name": "cpu", + "dtb": { + "name": "dtb", + "eventq_index": 0, + "cxx_class": "RiscvISA::TLB", + "path": "system.cpu.dtb", + "type": "RiscvTLB", + "size": 64 + }, + "simpoint_start_insts": [], + "max_insts_any_thread": 0, + "progress_interval": 0, + "branchPred": null, + "isa": [ + { + "eventq_index": 0, + "path": "system.cpu.isa", + "type": "RiscvISA", + "name": "isa", + "cxx_class": "RiscvISA::ISA" + } + ], + "tracer": { + "eventq_index": 0, + "path": "system.cpu.tracer", + "type": "ExeTracer", + "name": "tracer", + "cxx_class": "Trace::ExeTracer" + } + }, + "multi_thread": false, + "mem_ctrls": [ + { + "static_frontend_latency": 10, + "tRFC": 260, + "activation_limit": 4, + "in_addr_map": true, + "IDD3N2": "0.0", + "tWTR": 8, + "IDD52": "0.0", + "clk_domain": "system.clk_domain", + "channels": 1, + "write_buffer_size": 64, + "device_bus_width": 8, + "VDD": "1.5", + "write_high_thresh_perc": 85, + "cxx_class": "DRAMCtrl", + "bank_groups_per_rank": 0, + "IDD2N2": "0.0", + "port": { + "peer": "system.ruby.dir_cntrl0.memory", + "role": "SLAVE" + }, + "tCCD_L": 0, + "IDD2N": "0.032", + "p_state_clk_gate_min": 1, + "null": false, + "IDD2P1": "0.032", + "eventq_index": 0, + "tRRD": 6, + "tRTW": 3, + "IDD4R": "0.157", + "burst_length": 8, + "tRTP": 8, + "IDD4W": "0.125", + "tWR": 15, + "banks_per_rank": 8, + "devices_per_rank": 8, + "IDD2P02": "0.0", + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000, + "IDD6": "0.02", + "IDD5": "0.235", + "tRCD": 14, + "type": "DRAMCtrl", + "IDD3P02": "0.0", + "tRRD_L": 0, + "IDD0": "0.055", + "IDD62": "0.0", + "min_writes_per_switch": 16, + "mem_sched_policy": "frfcfs", + "IDD02": "0.0", + "IDD2P0": "0.0", + "ranks_per_channel": 2, + "page_policy": "open_adaptive", + "IDD4W2": "0.0", + "tCS": 3, + "power_model": null, + "tCL": 14, + "read_buffer_size": 32, + "conf_table_reported": true, + "tCK": 1, + "tRAS": 35, + "tRP": 14, + "tBURST": 5, + "path": "system.mem_ctrls", + "tXP": 6, + "tXS": 270, + "addr_mapping": "RoRaBaCoCh", + "IDD3P0": "0.0", + "IDD3P1": "0.038", + "IDD3N": "0.038", + "name": "mem_ctrls", + "tXSDLL": 0, + "device_size": 536870912, + "kvm_map": true, + "dll": true, + "tXAW": 30, + "write_low_thresh_perc": 50, + "range": "0:268435455:5:19:0:0", + "VDD2": "0.0", + "IDD2P12": "0.0", + "p_state_clk_gate_bins": 20, + "tXPDLL": 0, + "IDD4R2": "0.0", + "device_rowbuffer_size": 1024, + "static_backend_latency": 10, + "max_accesses_per_row": 16, + "IDD3P12": "0.0", + "tREFI": 7800 + } + ], + "exit_on_work_items": false, + "work_item_id": -1, + "num_work_ids": 16 + }, + "time_sync_period": 100000000, + "eventq_index": 0, + "time_sync_spin_threshold": 100000, + "cxx_class": "Root", + "path": "root", + "time_sync_enable": false, + "type": "Root", + "full_system": false +}
\ No newline at end of file diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing-ruby/simerr b/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing-ruby/simerr new file mode 100755 index 000000000..63b14556f --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing-ruby/simerr @@ -0,0 +1,11 @@ +warn: rounding error > tolerance + 1.250000 rounded to 1 +warn: rounding error > tolerance + 1.250000 rounded to 1 +warn: rounding error > tolerance + 1.250000 rounded to 1 +warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes) +warn: Unknown operating system; assuming Linux. +warn: Sockets disabled, not accepting gdb connections +warn: ClockedObject: More than one power state change request encountered within the same simulation tick +warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files! diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing-ruby/simout b/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing-ruby/simout new file mode 100755 index 000000000..e65840d6c --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing-ruby/simout @@ -0,0 +1,15 @@ +Redirecting stdout to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64a/simple-timing-ruby/simout +Redirecting stderr to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64a/simple-timing-ruby/simerr +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled Nov 30 2016 14:33:35 +gem5 started Nov 30 2016 16:18:31 +gem5 executing on zizzer, pid 34069 +command line: /z/powerjg/gem5-upstream/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64a/simple-timing-ruby -re /z/powerjg/gem5-upstream/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64a/simple-timing-ruby + +Global frequency set at 1000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. +lr.w/sc.w: [1;31mFAIL[0m (expected (-1, 0); found (-1, 1)) +Exiting @ tick 796036 because target called exit() diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing-ruby/stats.txt b/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing-ruby/stats.txt new file mode 100644 index 000000000..8b3036b08 --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing-ruby/stats.txt @@ -0,0 +1,659 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.000796 # Number of seconds simulated +sim_ticks 796036 # Number of ticks simulated +final_tick 796036 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000 # Frequency of simulated ticks +host_inst_rate 51863 # Simulator instruction rate (inst/s) +host_op_rate 51862 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 623875 # Simulator tick rate (ticks/s) +host_mem_usage 411084 # Number of bytes of host memory used +host_seconds 1.28 # Real time elapsed on the host +sim_insts 66173 # Number of instructions simulated +sim_ops 66173 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1 # Clock period in ticks +system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 796036 # Cumulative time (in ticks) in various power states +system.mem_ctrls.bytes_read::ruby.dir_cntrl0 899200 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::total 899200 # Number of bytes read from this memory +system.mem_ctrls.bytes_written::ruby.dir_cntrl0 898944 # Number of bytes written to this memory +system.mem_ctrls.bytes_written::total 898944 # Number of bytes written to this memory +system.mem_ctrls.num_reads::ruby.dir_cntrl0 14050 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::total 14050 # Number of read requests responded to by this memory +system.mem_ctrls.num_writes::ruby.dir_cntrl0 14046 # Number of write requests responded to by this memory +system.mem_ctrls.num_writes::total 14046 # Number of write requests responded to by this memory +system.mem_ctrls.bw_read::ruby.dir_cntrl0 1129597154 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::total 1129597154 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::ruby.dir_cntrl0 1129275560 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::total 1129275560 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_total::ruby.dir_cntrl0 2258872714 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::total 2258872714 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.readReqs 14050 # Number of read requests accepted +system.mem_ctrls.writeReqs 14046 # Number of write requests accepted +system.mem_ctrls.readBursts 14050 # Number of DRAM read bursts, including those serviced by the write queue +system.mem_ctrls.writeBursts 14046 # Number of DRAM write bursts, including those merged in the write queue +system.mem_ctrls.bytesReadDRAM 236096 # Total number of bytes read from DRAM +system.mem_ctrls.bytesReadWrQ 663104 # Total number of bytes read from write queue +system.mem_ctrls.bytesWritten 245056 # Total number of bytes written to DRAM +system.mem_ctrls.bytesReadSys 899200 # Total read bytes from the system interface side +system.mem_ctrls.bytesWrittenSys 898944 # Total written bytes from the system interface side +system.mem_ctrls.servicedByWrQ 10361 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrls.mergedWrBursts 10190 # Number of DRAM write bursts merged with an existing one +system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.mem_ctrls.perBankRdBursts::0 171 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::1 11 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::2 5 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::3 94 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::4 190 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::5 318 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::6 159 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::7 59 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::8 94 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::9 356 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::10 241 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::11 240 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::12 629 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::13 494 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::14 606 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::15 22 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::0 175 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::1 12 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::2 4 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::3 95 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::4 197 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::5 332 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::6 163 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::7 63 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::8 96 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::9 353 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::10 243 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::11 245 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::12 639 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::13 514 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::14 676 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::15 22 # Per bank write bursts +system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry +system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry +system.mem_ctrls.totGap 795950 # Total gap between requests +system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::6 14050 # Read request sizes (log2) +system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::6 14046 # Write request sizes (log2) +system.mem_ctrls.rdQLenPdf::0 3689 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::1 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::2 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::4 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::0 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::1 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::2 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::3 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::4 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::5 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::6 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::7 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::8 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::9 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::10 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::11 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::15 25 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::16 31 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::17 198 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::18 236 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::19 240 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::20 247 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::21 253 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::22 253 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::23 240 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::24 236 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::25 236 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::26 236 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::27 235 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::28 235 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::29 235 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::30 235 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::31 235 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::32 235 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.mem_ctrls.bytesPerActivate::samples 1249 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::mean 383.846277 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::gmean 248.755949 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::stdev 339.416055 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::0-127 261 20.90% 20.90% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::128-255 321 25.70% 46.60% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::256-383 184 14.73% 61.33% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::384-511 116 9.29% 70.62% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::512-639 64 5.12% 75.74% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::640-767 46 3.68% 79.42% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::768-895 41 3.28% 82.71% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::896-1023 34 2.72% 85.43% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::1024-1151 182 14.57% 100.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::total 1249 # Bytes accessed per row activation +system.mem_ctrls.rdPerTurnAround::samples 235 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::mean 15.651064 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::gmean 15.555359 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::stdev 1.947371 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::12-13 16 6.81% 6.81% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::14-15 98 41.70% 48.51% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::16-17 97 41.28% 89.79% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::18-19 21 8.94% 98.72% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::20-21 2 0.85% 99.57% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::36-37 1 0.43% 100.00% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::total 235 # Reads before turning the bus around for writes +system.mem_ctrls.wrPerTurnAround::samples 235 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::mean 16.293617 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::gmean 16.273674 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::stdev 0.844136 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::16 208 88.51% 88.51% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::18 14 5.96% 94.47% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::19 11 4.68% 99.15% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::20 2 0.85% 100.00% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::total 235 # Writes before turning the bus around for reads +system.mem_ctrls.totQLat 72649 # Total ticks spent queuing +system.mem_ctrls.totMemAccLat 142740 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.totBusLat 18445 # Total ticks spent in databus transfers +system.mem_ctrls.avgQLat 19.69 # Average queueing delay per DRAM burst +system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst +system.mem_ctrls.avgMemAccLat 38.69 # Average memory access latency per DRAM burst +system.mem_ctrls.avgRdBW 296.59 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrls.avgWrBW 307.85 # Average achieved write bandwidth in MiByte/s +system.mem_ctrls.avgRdBWSys 1129.60 # Average system read bandwidth in MiByte/s +system.mem_ctrls.avgWrBWSys 1129.28 # Average system write bandwidth in MiByte/s +system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.mem_ctrls.busUtil 4.72 # Data bus utilization in percentage +system.mem_ctrls.busUtilRead 2.32 # Data bus utilization in percentage for reads +system.mem_ctrls.busUtilWrite 2.41 # Data bus utilization in percentage for writes +system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing +system.mem_ctrls.avgWrQLen 25.57 # Average write queue length when enqueuing +system.mem_ctrls.readRowHits 2727 # Number of row buffer hits during reads +system.mem_ctrls.writeRowHits 3536 # Number of row buffer hits during writes +system.mem_ctrls.readRowHitRate 73.92 # Row buffer hit rate for reads +system.mem_ctrls.writeRowHitRate 91.70 # Row buffer hit rate for writes +system.mem_ctrls.avgGap 28.33 # Average gap between requests +system.mem_ctrls.pageHitRate 83.01 # Row buffer hit rate, read and write combined +system.mem_ctrls_0.actEnergy 3048780 # Energy for activate commands per rank (pJ) +system.mem_ctrls_0.preEnergy 1642200 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_0.readEnergy 11503968 # Energy for read commands per rank (pJ) +system.mem_ctrls_0.writeEnergy 8694432 # Energy for write commands per rank (pJ) +system.mem_ctrls_0.refreshEnergy 44868720.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_0.actBackEnergy 54752376 # Energy for active background per rank (pJ) +system.mem_ctrls_0.preBackEnergy 1331712 # Energy for precharge background per rank (pJ) +system.mem_ctrls_0.actPowerDownEnergy 160437216 # Energy for active power-down per rank (pJ) +system.mem_ctrls_0.prePowerDownEnergy 26780160 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls_0.selfRefreshEnergy 62430000 # Energy for self refresh per rank (pJ) +system.mem_ctrls_0.totalEnergy 375489564 # Total energy per rank (pJ) +system.mem_ctrls_0.averagePower 471.699225 # Core power per rank (mW) +system.mem_ctrls_0.totalIdleTime 672460 # Total Idle time Per DRAM Rank +system.mem_ctrls_0.memoryStateTime::IDLE 1456 # Time in different power states +system.mem_ctrls_0.memoryStateTime::REF 19004 # Time in different power states +system.mem_ctrls_0.memoryStateTime::SREF 250921 # Time in different power states +system.mem_ctrls_0.memoryStateTime::PRE_PDN 69740 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT 103079 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT_PDN 351836 # Time in different power states +system.mem_ctrls_1.actEnergy 5911920 # Energy for activate commands per rank (pJ) +system.mem_ctrls_1.preEnergy 3183936 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_1.readEnergy 30639168 # Energy for read commands per rank (pJ) +system.mem_ctrls_1.writeEnergy 23285376 # Energy for write commands per rank (pJ) +system.mem_ctrls_1.refreshEnergy 61464000.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_1.actBackEnergy 65872392 # Energy for active background per rank (pJ) +system.mem_ctrls_1.preBackEnergy 2049024 # Energy for precharge background per rank (pJ) +system.mem_ctrls_1.actPowerDownEnergy 210691152 # Energy for active power-down per rank (pJ) +system.mem_ctrls_1.prePowerDownEnergy 47203968 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls_1.selfRefreshEnergy 18571440 # Energy for self refresh per rank (pJ) +system.mem_ctrls_1.totalEnergy 468872376 # Total energy per rank (pJ) +system.mem_ctrls_1.averagePower 589.009010 # Core power per rank (mW) +system.mem_ctrls_1.totalIdleTime 646243 # Total Idle time Per DRAM Rank +system.mem_ctrls_1.memoryStateTime::IDLE 2396 # Time in different power states +system.mem_ctrls_1.memoryStateTime::REF 26042 # Time in different power states +system.mem_ctrls_1.memoryStateTime::SREF 61274 # Time in different power states +system.mem_ctrls_1.memoryStateTime::PRE_PDN 122927 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT 121355 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT_PDN 462042 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 796036 # Cumulative time (in ticks) in various power states +system.cpu.clk_domain.clock 1 # Clock period in ticks +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 9 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 796036 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 796036 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 66173 # Number of instructions committed +system.cpu.committedOps 66173 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 66174 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses +system.cpu.num_func_calls 5169 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 10311 # number of instructions that are conditional controls +system.cpu.num_int_insts 66174 # number of integer instructions +system.cpu.num_fp_insts 0 # number of float instructions +system.cpu.num_int_register_reads 89437 # number of times the integer registers were read +system.cpu.num_int_register_writes 43419 # number of times the integer registers were written +system.cpu.num_fp_register_reads 0 # number of times the floating registers were read +system.cpu.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu.num_mem_refs 24255 # number of memory refs +system.cpu.num_load_insts 11810 # Number of load instructions +system.cpu.num_store_insts 12445 # Number of store instructions +system.cpu.num_idle_cycles 0 # Number of idle cycles +system.cpu.num_busy_cycles 796036 # Number of busy cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.Branches 15480 # Number of branches fetched +system.cpu.op_class::No_OpClass 9 0.01% 0.01% # Class of executed instruction +system.cpu.op_class::IntAlu 41896 63.30% 63.32% # Class of executed instruction +system.cpu.op_class::IntMult 15 0.02% 63.34% # Class of executed instruction +system.cpu.op_class::IntDiv 8 0.01% 63.35% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 63.35% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 63.35% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 63.35% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 63.35% # Class of executed instruction +system.cpu.op_class::FloatMultAcc 0 0.00% 63.35% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 63.35% # Class of executed instruction +system.cpu.op_class::FloatMisc 0 0.00% 63.35% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 63.35% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 63.35% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 63.35% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 63.35% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 63.35% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 63.35% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 63.35% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 63.35% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 63.35% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 63.35% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 63.35% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 63.35% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 63.35% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 63.35% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 63.35% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 63.35% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 63.35% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 63.35% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 63.35% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.35% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.35% # Class of executed instruction +system.cpu.op_class::MemRead 11810 17.84% 81.20% # Class of executed instruction +system.cpu.op_class::MemWrite 12445 18.80% 100.00% # Class of executed instruction +system.cpu.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 66183 # Class of executed instruction +system.ruby.clk_domain.clock 1 # Clock period in ticks +system.ruby.pwrStateResidencyTicks::UNDEFINED 796036 # Cumulative time (in ticks) in various power states +system.ruby.delayHist::bucket_size 1 # delay histogram for all message +system.ruby.delayHist::max_bucket 9 # delay histogram for all message +system.ruby.delayHist::samples 28096 # delay histogram for all message +system.ruby.delayHist | 28096 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message +system.ruby.delayHist::total 28096 # delay histogram for all message +system.ruby.outstanding_req_hist_seqr::bucket_size 1 +system.ruby.outstanding_req_hist_seqr::max_bucket 9 +system.ruby.outstanding_req_hist_seqr::samples 90437 +system.ruby.outstanding_req_hist_seqr::mean 1 +system.ruby.outstanding_req_hist_seqr::gmean 1 +system.ruby.outstanding_req_hist_seqr | 0 0.00% 0.00% | 90437 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.outstanding_req_hist_seqr::total 90437 +system.ruby.latency_hist_seqr::bucket_size 64 +system.ruby.latency_hist_seqr::max_bucket 639 +system.ruby.latency_hist_seqr::samples 90436 +system.ruby.latency_hist_seqr::mean 7.802203 +system.ruby.latency_hist_seqr::gmean 1.774694 +system.ruby.latency_hist_seqr::stdev 20.056111 +system.ruby.latency_hist_seqr | 86872 96.06% 96.06% | 3313 3.66% 99.72% | 168 0.19% 99.91% | 27 0.03% 99.94% | 26 0.03% 99.97% | 19 0.02% 99.99% | 1 0.00% 99.99% | 1 0.00% 99.99% | 0 0.00% 99.99% | 9 0.01% 100.00% +system.ruby.latency_hist_seqr::total 90436 +system.ruby.hit_latency_hist_seqr::bucket_size 1 +system.ruby.hit_latency_hist_seqr::max_bucket 9 +system.ruby.hit_latency_hist_seqr::samples 76386 +system.ruby.hit_latency_hist_seqr::mean 1 +system.ruby.hit_latency_hist_seqr::gmean 1 +system.ruby.hit_latency_hist_seqr | 0 0.00% 0.00% | 76386 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.hit_latency_hist_seqr::total 76386 +system.ruby.miss_latency_hist_seqr::bucket_size 64 +system.ruby.miss_latency_hist_seqr::max_bucket 639 +system.ruby.miss_latency_hist_seqr::samples 14050 +system.ruby.miss_latency_hist_seqr::mean 44.783915 +system.ruby.miss_latency_hist_seqr::gmean 40.136483 +system.ruby.miss_latency_hist_seqr::stdev 31.144722 +system.ruby.miss_latency_hist_seqr | 10486 74.63% 74.63% | 3313 23.58% 98.21% | 168 1.20% 99.41% | 27 0.19% 99.60% | 26 0.19% 99.79% | 19 0.14% 99.92% | 1 0.01% 99.93% | 1 0.01% 99.94% | 0 0.00% 99.94% | 9 0.06% 100.00% +system.ruby.miss_latency_hist_seqr::total 14050 +system.ruby.Directory.incomplete_times_seqr 14049 +system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 796036 # Cumulative time (in ticks) in various power states +system.ruby.l1_cntrl0.cacheMemory.demand_hits 76386 # Number of cache demand hits +system.ruby.l1_cntrl0.cacheMemory.demand_misses 14050 # Number of cache demand misses +system.ruby.l1_cntrl0.cacheMemory.demand_accesses 90436 # Number of cache demand accesses +system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 796036 # Cumulative time (in ticks) in various power states +system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 796036 # Cumulative time (in ticks) in various power states +system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks +system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 796036 # Cumulative time (in ticks) in various power states +system.ruby.network.routers0.percent_links_utilized 8.823722 +system.ruby.network.routers0.msg_count.Control::2 14050 +system.ruby.network.routers0.msg_count.Data::2 14046 +system.ruby.network.routers0.msg_count.Response_Data::4 14050 +system.ruby.network.routers0.msg_count.Writeback_Control::3 14046 +system.ruby.network.routers0.msg_bytes.Control::2 112400 +system.ruby.network.routers0.msg_bytes.Data::2 1011312 +system.ruby.network.routers0.msg_bytes.Response_Data::4 1011600 +system.ruby.network.routers0.msg_bytes.Writeback_Control::3 112368 +system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 796036 # Cumulative time (in ticks) in various power states +system.ruby.network.routers1.percent_links_utilized 8.823722 +system.ruby.network.routers1.msg_count.Control::2 14050 +system.ruby.network.routers1.msg_count.Data::2 14046 +system.ruby.network.routers1.msg_count.Response_Data::4 14050 +system.ruby.network.routers1.msg_count.Writeback_Control::3 14046 +system.ruby.network.routers1.msg_bytes.Control::2 112400 +system.ruby.network.routers1.msg_bytes.Data::2 1011312 +system.ruby.network.routers1.msg_bytes.Response_Data::4 1011600 +system.ruby.network.routers1.msg_bytes.Writeback_Control::3 112368 +system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 796036 # Cumulative time (in ticks) in various power states +system.ruby.network.routers2.percent_links_utilized 8.823722 +system.ruby.network.routers2.msg_count.Control::2 14050 +system.ruby.network.routers2.msg_count.Data::2 14046 +system.ruby.network.routers2.msg_count.Response_Data::4 14050 +system.ruby.network.routers2.msg_count.Writeback_Control::3 14046 +system.ruby.network.routers2.msg_bytes.Control::2 112400 +system.ruby.network.routers2.msg_bytes.Data::2 1011312 +system.ruby.network.routers2.msg_bytes.Response_Data::4 1011600 +system.ruby.network.routers2.msg_bytes.Writeback_Control::3 112368 +system.ruby.network.pwrStateResidencyTicks::UNDEFINED 796036 # Cumulative time (in ticks) in various power states +system.ruby.network.msg_count.Control 42150 +system.ruby.network.msg_count.Data 42138 +system.ruby.network.msg_count.Response_Data 42150 +system.ruby.network.msg_count.Writeback_Control 42138 +system.ruby.network.msg_byte.Control 337200 +system.ruby.network.msg_byte.Data 3033936 +system.ruby.network.msg_byte.Response_Data 3034800 +system.ruby.network.msg_byte.Writeback_Control 337104 +system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 796036 # Cumulative time (in ticks) in various power states +system.ruby.network.routers0.throttle0.link_utilization 8.824727 +system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 14050 +system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 14046 +system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 1011600 +system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3 112368 +system.ruby.network.routers0.throttle1.link_utilization 8.822717 +system.ruby.network.routers0.throttle1.msg_count.Control::2 14050 +system.ruby.network.routers0.throttle1.msg_count.Data::2 14046 +system.ruby.network.routers0.throttle1.msg_bytes.Control::2 112400 +system.ruby.network.routers0.throttle1.msg_bytes.Data::2 1011312 +system.ruby.network.routers1.throttle0.link_utilization 8.822717 +system.ruby.network.routers1.throttle0.msg_count.Control::2 14050 +system.ruby.network.routers1.throttle0.msg_count.Data::2 14046 +system.ruby.network.routers1.throttle0.msg_bytes.Control::2 112400 +system.ruby.network.routers1.throttle0.msg_bytes.Data::2 1011312 +system.ruby.network.routers1.throttle1.link_utilization 8.824727 +system.ruby.network.routers1.throttle1.msg_count.Response_Data::4 14050 +system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::3 14046 +system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4 1011600 +system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::3 112368 +system.ruby.network.routers2.throttle0.link_utilization 8.824727 +system.ruby.network.routers2.throttle0.msg_count.Response_Data::4 14050 +system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3 14046 +system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4 1011600 +system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3 112368 +system.ruby.network.routers2.throttle1.link_utilization 8.822717 +system.ruby.network.routers2.throttle1.msg_count.Control::2 14050 +system.ruby.network.routers2.throttle1.msg_count.Data::2 14046 +system.ruby.network.routers2.throttle1.msg_bytes.Control::2 112400 +system.ruby.network.routers2.throttle1.msg_bytes.Data::2 1011312 +system.ruby.delayVCHist.vnet_1::bucket_size 1 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1::max_bucket 9 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1::samples 14050 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1 | 14050 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1::total 14050 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_2::bucket_size 1 # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2::max_bucket 9 # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2::samples 14046 # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2 | 14046 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2::total 14046 # delay histogram for vnet_2 +system.ruby.LD.latency_hist_seqr::bucket_size 64 +system.ruby.LD.latency_hist_seqr::max_bucket 639 +system.ruby.LD.latency_hist_seqr::samples 11809 +system.ruby.LD.latency_hist_seqr::mean 15.856719 +system.ruby.LD.latency_hist_seqr::gmean 3.539899 +system.ruby.LD.latency_hist_seqr::stdev 26.045304 +system.ruby.LD.latency_hist_seqr | 10771 91.21% 91.21% | 977 8.27% 99.48% | 43 0.36% 99.85% | 9 0.08% 99.92% | 5 0.04% 99.97% | 2 0.02% 99.98% | 0 0.00% 99.98% | 1 0.01% 99.99% | 0 0.00% 99.99% | 1 0.01% 100.00% +system.ruby.LD.latency_hist_seqr::total 11809 +system.ruby.LD.hit_latency_hist_seqr::bucket_size 1 +system.ruby.LD.hit_latency_hist_seqr::max_bucket 9 +system.ruby.LD.hit_latency_hist_seqr::samples 7768 +system.ruby.LD.hit_latency_hist_seqr::mean 1 +system.ruby.LD.hit_latency_hist_seqr::gmean 1 +system.ruby.LD.hit_latency_hist_seqr | 0 0.00% 0.00% | 7768 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.hit_latency_hist_seqr::total 7768 +system.ruby.LD.miss_latency_hist_seqr::bucket_size 64 +system.ruby.LD.miss_latency_hist_seqr::max_bucket 639 +system.ruby.LD.miss_latency_hist_seqr::samples 4041 +system.ruby.LD.miss_latency_hist_seqr::mean 44.415739 +system.ruby.LD.miss_latency_hist_seqr::gmean 40.208159 +system.ruby.LD.miss_latency_hist_seqr::stdev 27.248261 +system.ruby.LD.miss_latency_hist_seqr | 3003 74.31% 74.31% | 977 24.18% 98.49% | 43 1.06% 99.55% | 9 0.22% 99.78% | 5 0.12% 99.90% | 2 0.05% 99.95% | 0 0.00% 99.95% | 1 0.02% 99.98% | 0 0.00% 99.98% | 1 0.02% 100.00% +system.ruby.LD.miss_latency_hist_seqr::total 4041 +system.ruby.ST.latency_hist_seqr::bucket_size 64 +system.ruby.ST.latency_hist_seqr::max_bucket 639 +system.ruby.ST.latency_hist_seqr::samples 12443 +system.ruby.ST.latency_hist_seqr::mean 11.799164 +system.ruby.ST.latency_hist_seqr::gmean 2.546410 +system.ruby.ST.latency_hist_seqr::stdev 25.562634 +system.ruby.ST.latency_hist_seqr | 11787 94.73% 94.73% | 602 4.84% 99.57% | 31 0.25% 99.82% | 7 0.06% 99.87% | 4 0.03% 99.90% | 7 0.06% 99.96% | 0 0.00% 99.96% | 0 0.00% 99.96% | 0 0.00% 99.96% | 5 0.04% 100.00% +system.ruby.ST.latency_hist_seqr::total 12443 +system.ruby.ST.hit_latency_hist_seqr::bucket_size 1 +system.ruby.ST.hit_latency_hist_seqr::max_bucket 9 +system.ruby.ST.hit_latency_hist_seqr::samples 9259 +system.ruby.ST.hit_latency_hist_seqr::mean 1 +system.ruby.ST.hit_latency_hist_seqr::gmean 1 +system.ruby.ST.hit_latency_hist_seqr | 0 0.00% 0.00% | 9259 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.hit_latency_hist_seqr::total 9259 +system.ruby.ST.miss_latency_hist_seqr::bucket_size 64 +system.ruby.ST.miss_latency_hist_seqr::max_bucket 639 +system.ruby.ST.miss_latency_hist_seqr::samples 3184 +system.ruby.ST.miss_latency_hist_seqr::mean 43.202889 +system.ruby.ST.miss_latency_hist_seqr::gmean 38.579676 +system.ruby.ST.miss_latency_hist_seqr::stdev 35.050159 +system.ruby.ST.miss_latency_hist_seqr | 2528 79.40% 79.40% | 602 18.91% 98.30% | 31 0.97% 99.28% | 7 0.22% 99.50% | 4 0.13% 99.62% | 7 0.22% 99.84% | 0 0.00% 99.84% | 0 0.00% 99.84% | 0 0.00% 99.84% | 5 0.16% 100.00% +system.ruby.ST.miss_latency_hist_seqr::total 3184 +system.ruby.IFETCH.latency_hist_seqr::bucket_size 64 +system.ruby.IFETCH.latency_hist_seqr::max_bucket 639 +system.ruby.IFETCH.latency_hist_seqr::samples 66183 +system.ruby.IFETCH.latency_hist_seqr::mean 5.613677 +system.ruby.IFETCH.latency_hist_seqr::gmean 1.466025 +system.ruby.IFETCH.latency_hist_seqr::stdev 16.923600 +system.ruby.IFETCH.latency_hist_seqr | 64313 97.17% 97.17% | 1734 2.62% 99.79% | 94 0.14% 99.94% | 11 0.02% 99.95% | 17 0.03% 99.98% | 10 0.02% 99.99% | 1 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 3 0.00% 100.00% +system.ruby.IFETCH.latency_hist_seqr::total 66183 +system.ruby.IFETCH.hit_latency_hist_seqr::bucket_size 1 +system.ruby.IFETCH.hit_latency_hist_seqr::max_bucket 9 +system.ruby.IFETCH.hit_latency_hist_seqr::samples 59358 +system.ruby.IFETCH.hit_latency_hist_seqr::mean 1 +system.ruby.IFETCH.hit_latency_hist_seqr::gmean 1 +system.ruby.IFETCH.hit_latency_hist_seqr | 0 0.00% 0.00% | 59358 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.hit_latency_hist_seqr::total 59358 +system.ruby.IFETCH.miss_latency_hist_seqr::bucket_size 64 +system.ruby.IFETCH.miss_latency_hist_seqr::max_bucket 639 +system.ruby.IFETCH.miss_latency_hist_seqr::samples 6825 +system.ruby.IFETCH.miss_latency_hist_seqr::mean 45.739487 +system.ruby.IFETCH.miss_latency_hist_seqr::gmean 40.840935 +system.ruby.IFETCH.miss_latency_hist_seqr::stdev 31.340636 +system.ruby.IFETCH.miss_latency_hist_seqr | 4955 72.60% 72.60% | 1734 25.41% 98.01% | 94 1.38% 99.38% | 11 0.16% 99.55% | 17 0.25% 99.79% | 10 0.15% 99.94% | 1 0.01% 99.96% | 0 0.00% 99.96% | 0 0.00% 99.96% | 3 0.04% 100.00% +system.ruby.IFETCH.miss_latency_hist_seqr::total 6825 +system.ruby.Load_Linked.latency_hist_seqr::bucket_size 1 +system.ruby.Load_Linked.latency_hist_seqr::max_bucket 9 +system.ruby.Load_Linked.latency_hist_seqr::samples 1 +system.ruby.Load_Linked.latency_hist_seqr::mean 1 +system.ruby.Load_Linked.latency_hist_seqr::gmean 1 +system.ruby.Load_Linked.latency_hist_seqr::stdev nan +system.ruby.Load_Linked.latency_hist_seqr | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Load_Linked.latency_hist_seqr::total 1 +system.ruby.Load_Linked.hit_latency_hist_seqr::bucket_size 1 +system.ruby.Load_Linked.hit_latency_hist_seqr::max_bucket 9 +system.ruby.Load_Linked.hit_latency_hist_seqr::samples 1 +system.ruby.Load_Linked.hit_latency_hist_seqr::mean 1 +system.ruby.Load_Linked.hit_latency_hist_seqr::gmean 1 +system.ruby.Load_Linked.hit_latency_hist_seqr::stdev nan +system.ruby.Load_Linked.hit_latency_hist_seqr | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Load_Linked.hit_latency_hist_seqr::total 1 +system.ruby.Directory.miss_mach_latency_hist_seqr::bucket_size 64 +system.ruby.Directory.miss_mach_latency_hist_seqr::max_bucket 639 +system.ruby.Directory.miss_mach_latency_hist_seqr::samples 14050 +system.ruby.Directory.miss_mach_latency_hist_seqr::mean 44.783915 +system.ruby.Directory.miss_mach_latency_hist_seqr::gmean 40.136483 +system.ruby.Directory.miss_mach_latency_hist_seqr::stdev 31.144722 +system.ruby.Directory.miss_mach_latency_hist_seqr | 10486 74.63% 74.63% | 3313 23.58% 98.21% | 168 1.20% 99.41% | 27 0.19% 99.60% | 26 0.19% 99.79% | 19 0.14% 99.92% | 1 0.01% 99.93% | 1 0.01% 99.94% | 0 0.00% 99.94% | 9 0.06% 100.00% +system.ruby.Directory.miss_mach_latency_hist_seqr::total 14050 +system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::bucket_size 1 +system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::max_bucket 9 +system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::samples 1 +system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::stdev nan +system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::total 1 +system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::bucket_size 1 +system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::max_bucket 9 +system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::samples 1 +system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::stdev nan +system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::total 1 +system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::bucket_size 1 +system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::max_bucket 9 +system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::samples 1 +system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::stdev nan +system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::total 1 +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::bucket_size 8 +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::max_bucket 79 +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::samples 1 +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::mean 75 +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::gmean 75.000000 +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::stdev nan +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::total 1 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::samples 4041 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::mean 44.415739 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::gmean 40.208159 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::stdev 27.248261 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr | 3003 74.31% 74.31% | 977 24.18% 98.49% | 43 1.06% 99.55% | 9 0.22% 99.78% | 5 0.12% 99.90% | 2 0.05% 99.95% | 0 0.00% 99.95% | 1 0.02% 99.98% | 0 0.00% 99.98% | 1 0.02% 100.00% +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::total 4041 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::samples 3184 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::mean 43.202889 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::gmean 38.579676 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::stdev 35.050159 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr | 2528 79.40% 79.40% | 602 18.91% 98.30% | 31 0.97% 99.28% | 7 0.22% 99.50% | 4 0.13% 99.62% | 7 0.22% 99.84% | 0 0.00% 99.84% | 0 0.00% 99.84% | 0 0.00% 99.84% | 5 0.16% 100.00% +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::total 3184 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::samples 6825 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::mean 45.739487 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::gmean 40.840935 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::stdev 31.340636 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr | 4955 72.60% 72.60% | 1734 25.41% 98.01% | 94 1.38% 99.38% | 11 0.16% 99.55% | 17 0.25% 99.79% | 10 0.15% 99.94% | 1 0.01% 99.96% | 0 0.00% 99.96% | 0 0.00% 99.96% | 3 0.04% 100.00% +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::total 6825 +system.ruby.Directory_Controller.GETX 14050 0.00% 0.00% +system.ruby.Directory_Controller.PUTX 14046 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Data 14050 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Ack 14046 0.00% 0.00% +system.ruby.Directory_Controller.I.GETX 14050 0.00% 0.00% +system.ruby.Directory_Controller.M.PUTX 14046 0.00% 0.00% +system.ruby.Directory_Controller.IM.Memory_Data 14050 0.00% 0.00% +system.ruby.Directory_Controller.MI.Memory_Ack 14046 0.00% 0.00% +system.ruby.L1Cache_Controller.Load 11809 0.00% 0.00% +system.ruby.L1Cache_Controller.Ifetch 66183 0.00% 0.00% +system.ruby.L1Cache_Controller.Store 12444 0.00% 0.00% +system.ruby.L1Cache_Controller.Data 14050 0.00% 0.00% +system.ruby.L1Cache_Controller.Replacement 14046 0.00% 0.00% +system.ruby.L1Cache_Controller.Writeback_Ack 14046 0.00% 0.00% +system.ruby.L1Cache_Controller.I.Load 4041 0.00% 0.00% +system.ruby.L1Cache_Controller.I.Ifetch 6825 0.00% 0.00% +system.ruby.L1Cache_Controller.I.Store 3184 0.00% 0.00% +system.ruby.L1Cache_Controller.M.Load 7768 0.00% 0.00% +system.ruby.L1Cache_Controller.M.Ifetch 59358 0.00% 0.00% +system.ruby.L1Cache_Controller.M.Store 9260 0.00% 0.00% +system.ruby.L1Cache_Controller.M.Replacement 14046 0.00% 0.00% +system.ruby.L1Cache_Controller.MI.Writeback_Ack 14046 0.00% 0.00% +system.ruby.L1Cache_Controller.IS.Data 10866 0.00% 0.00% +system.ruby.L1Cache_Controller.IM.Data 3184 0.00% 0.00% + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing/config.ini b/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing/config.ini new file mode 100644 index 000000000..6c2c774c6 --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing/config.ini @@ -0,0 +1,380 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain +boot_osflags=a +cache_line_size=64 +clk_domain=system.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +exit_on_work_items=false +init_param=0 +kernel= +kernel_addr_check=true +load_addr_mask=1099511627775 +load_offset=0 +mem_mode=timing +mem_ranges= +memories=system.physmem +mmap_using_noreserve=false +multi_thread=false +num_work_ids=16 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +readfile= +symbolfile= +thermal_components= +thermal_model=Null +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=TimingSimpleCPU +children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload +branchPred=Null +checker=Null +clk_domain=system.cpu_clk_domain +cpu_id=0 +default_p_state=UNDEFINED +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +eventq_index=0 +function_trace=false +function_trace_start=0 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +profile=0 +progress_interval=0 +simpoint_start_insts= +socket_id=0 +switched_out=false +system=system +tracer=system.cpu.tracer +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.dcache] +type=Cache +children=tags +addr_ranges=0:18446744073709551615:0:0:0:0 +assoc=2 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +data_latency=2 +default_p_state=UNDEFINED +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=4 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=262144 +system=system +tag_latency=2 +tags=system.cpu.dcache.tags +tgts_per_mshr=20 +write_buffers=8 +writeback_clean=false +cpu_side=system.cpu.dcache_port +mem_side=system.cpu.toL2Bus.slave[1] + +[system.cpu.dcache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +data_latency=2 +default_p_state=UNDEFINED +eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +sequential_access=false +size=262144 +tag_latency=2 + +[system.cpu.dtb] +type=RiscvTLB +eventq_index=0 +size=64 + +[system.cpu.icache] +type=Cache +children=tags +addr_ranges=0:18446744073709551615:0:0:0:0 +assoc=2 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +data_latency=2 +default_p_state=UNDEFINED +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=true +max_miss_count=0 +mshrs=4 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=131072 +system=system +tag_latency=2 +tags=system.cpu.icache.tags +tgts_per_mshr=20 +write_buffers=8 +writeback_clean=true +cpu_side=system.cpu.icache_port +mem_side=system.cpu.toL2Bus.slave[0] + +[system.cpu.icache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +data_latency=2 +default_p_state=UNDEFINED +eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +sequential_access=false +size=131072 +tag_latency=2 + +[system.cpu.interrupts] +type=RiscvInterrupts +eventq_index=0 + +[system.cpu.isa] +type=RiscvISA +eventq_index=0 + +[system.cpu.itb] +type=RiscvTLB +eventq_index=0 +size=64 + +[system.cpu.l2cache] +type=Cache +children=tags +addr_ranges=0:18446744073709551615:0:0:0:0 +assoc=8 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +data_latency=20 +default_p_state=UNDEFINED +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=20 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +prefetch_on_access=false +prefetcher=Null +response_latency=20 +sequential_access=false +size=2097152 +system=system +tag_latency=20 +tags=system.cpu.l2cache.tags +tgts_per_mshr=12 +write_buffers=8 +writeback_clean=false +cpu_side=system.cpu.toL2Bus.master[0] +mem_side=system.membus.slave[1] + +[system.cpu.l2cache.tags] +type=LRU +assoc=8 +block_size=64 +clk_domain=system.cpu_clk_domain +data_latency=20 +default_p_state=UNDEFINED +eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +sequential_access=false +size=2097152 +tag_latency=20 + +[system.cpu.toL2Bus] +type=CoherentXBar +children=snoop_filter +clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED +eventq_index=0 +forward_latency=0 +frontend_latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +point_of_coherency=false +power_model=Null +response_latency=1 +snoop_filter=system.cpu.toL2Bus.snoop_filter +snoop_response_latency=1 +system=system +use_default_range=false +width=32 +master=system.cpu.l2cache.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side + +[system.cpu.toL2Bus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=0 +max_capacity=8388608 +system=system + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=LiveProcess +cmd=insttest +cwd= +drivers= +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable=/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64a/insttest +gid=100 +input=cin +kvmInSE=false +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=0 +system=system +uid=100 +useArchPT=false + +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000000 + +[system.membus] +type=CoherentXBar +children=snoop_filter +clk_domain=system.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +forward_latency=4 +frontend_latency=3 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +point_of_coherency=true +power_model=Null +response_latency=2 +snoop_filter=system.membus.snoop_filter +snoop_response_latency=4 +system=system +use_default_range=false +width=16 +master=system.physmem.port +slave=system.system_port system.cpu.l2cache.mem_side + +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + +[system.physmem] +type=SimpleMemory +bandwidth=73.000000 +clk_domain=system.clk_domain +conf_table_reported=true +default_p_state=UNDEFINED +eventq_index=0 +in_addr_map=true +kvm_map=true +latency=30000 +latency_var=0 +null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +range=0:134217727:0:0:0:0 +port=system.membus.master[0] + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing/config.json b/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing/config.json new file mode 100644 index 000000000..16fd9afa3 --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing/config.json @@ -0,0 +1,508 @@ +{ + "name": null, + "sim_quantum": 0, + "system": { + "kernel": "", + "mmap_using_noreserve": false, + "kernel_addr_check": true, + "membus": { + "point_of_coherency": true, + "system": "system", + "response_latency": 2, + "cxx_class": "CoherentXBar", + "forward_latency": 4, + "clk_domain": "system.clk_domain", + "width": 16, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "master": { + "peer": [ + "system.physmem.port" + ], + "role": "MASTER" + }, + "type": "CoherentXBar", + "frontend_latency": 3, + "slave": { + "peer": [ + "system.system_port", + "system.cpu.l2cache.mem_side" + ], + "role": "SLAVE" + }, + "p_state_clk_gate_min": 1000, + "snoop_filter": { + "name": "snoop_filter", + "system": "system", + "max_capacity": 8388608, + "eventq_index": 0, + "cxx_class": "SnoopFilter", + "path": "system.membus.snoop_filter", + "type": "SnoopFilter", + "lookup_latency": 1 + }, + "power_model": null, + "path": "system.membus", + "snoop_response_latency": 4, + "name": "membus", + "p_state_clk_gate_bins": 20, + "use_default_range": false + }, + "symbolfile": "", + "readfile": "", + "thermal_model": null, + "cxx_class": "System", + "work_begin_cpu_id_exit": -1, + "load_offset": 0, + "work_begin_exit_count": 0, + "p_state_clk_gate_min": 1000, + "memories": [ + "system.physmem" + ], + "work_begin_ckpt_count": 0, + "clk_domain": { + "name": "clk_domain", + "clock": [ + 1000 + ], + "init_perf_level": 0, + "voltage_domain": "system.voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "mem_ranges": [], + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "dvfs_handler": { + "enable": false, + "name": "dvfs_handler", + "sys_clk_domain": "system.clk_domain", + "transition_latency": 100000000, + "eventq_index": 0, + "cxx_class": "DVFSHandler", + "domains": [], + "path": "system.dvfs_handler", + "type": "DVFSHandler" + }, + "work_end_exit_count": 0, + "type": "System", + "voltage_domain": { + "name": "voltage_domain", + "eventq_index": 0, + "voltage": [ + "1.0" + ], + "cxx_class": "VoltageDomain", + "path": "system.voltage_domain", + "type": "VoltageDomain" + }, + "cache_line_size": 64, + "boot_osflags": "a", + "system_port": { + "peer": "system.membus.slave[0]", + "role": "MASTER" + }, + "physmem": { + "range": "0:134217727:0:0:0:0", + "latency": 30000, + "name": "physmem", + "p_state_clk_gate_min": 1000, + "eventq_index": 0, + "p_state_clk_gate_bins": 20, + "default_p_state": "UNDEFINED", + "kvm_map": true, + "clk_domain": "system.clk_domain", + "power_model": null, + "latency_var": 0, + "bandwidth": "73.000000", + "conf_table_reported": true, + "cxx_class": "SimpleMemory", + "p_state_clk_gate_max": 1000000000000, + "path": "system.physmem", + "null": false, + "type": "SimpleMemory", + "port": { + "peer": "system.membus.master[0]", + "role": "SLAVE" + }, + "in_addr_map": true + }, + "power_model": null, + "work_cpus_ckpt_count": 0, + "thermal_components": [], + "path": "system", + "cpu_clk_domain": { + "name": "cpu_clk_domain", + "clock": [ + 500 + ], + "init_perf_level": 0, + "voltage_domain": "system.voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.cpu_clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "work_end_ckpt_count": 0, + "mem_mode": "timing", + "name": "system", + "init_param": 0, + "p_state_clk_gate_bins": 20, + "load_addr_mask": 1099511627775, + "cpu": [ + { + "do_statistics_insts": true, + "numThreads": 1, + "itb": { + "name": "itb", + "eventq_index": 0, + "cxx_class": "RiscvISA::TLB", + "path": "system.cpu.itb", + "type": "RiscvTLB", + "size": 64 + }, + "system": "system", + "icache": { + "cpu_side": { + "peer": "system.cpu.icache_port", + "role": "SLAVE" + }, + "clusivity": "mostly_incl", + "prefetcher": null, + "system": "system", + "write_buffers": 8, + "response_latency": 2, + "cxx_class": "Cache", + "size": 131072, + "type": "Cache", + "clk_domain": "system.cpu_clk_domain", + "max_miss_count": 0, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "mem_side": { + "peer": "system.cpu.toL2Bus.slave[0]", + "role": "MASTER" + }, + "mshrs": 4, + "writeback_clean": true, + "p_state_clk_gate_min": 1000, + "tags": { + "size": 131072, + "tag_latency": 2, + "name": "tags", + "p_state_clk_gate_min": 1000, + "eventq_index": 0, + "p_state_clk_gate_bins": 20, + "default_p_state": "UNDEFINED", + "clk_domain": "system.cpu_clk_domain", + "power_model": null, + "sequential_access": false, + "assoc": 2, + "cxx_class": "LRU", + "p_state_clk_gate_max": 1000000000000, + "path": "system.cpu.icache.tags", + "block_size": 64, + "type": "LRU", + "data_latency": 2 + }, + "tgts_per_mshr": 20, + "demand_mshr_reserve": 1, + "power_model": null, + "addr_ranges": [ + "0:18446744073709551615:0:0:0:0" + ], + "is_read_only": true, + "prefetch_on_access": false, + "path": "system.cpu.icache", + "data_latency": 2, + "tag_latency": 2, + "name": "icache", + "p_state_clk_gate_bins": 20, + "sequential_access": false, + "assoc": 2 + }, + "function_trace": false, + "do_checkpoint_insts": true, + "cxx_class": "TimingSimpleCPU", + "max_loads_all_threads": 0, + "clk_domain": "system.cpu_clk_domain", + "function_trace_start": 0, + "cpu_id": 0, + "checker": null, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "toL2Bus": { + "point_of_coherency": false, + "system": "system", + "response_latency": 1, + "cxx_class": "CoherentXBar", + "forward_latency": 0, + "clk_domain": "system.cpu_clk_domain", + "width": 32, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "master": { + "peer": [ + "system.cpu.l2cache.cpu_side" + ], + "role": "MASTER" + }, + "type": "CoherentXBar", + "frontend_latency": 1, + "slave": { + "peer": [ + "system.cpu.icache.mem_side", + "system.cpu.dcache.mem_side" + ], + "role": "SLAVE" + }, + "p_state_clk_gate_min": 1000, + "snoop_filter": { + "name": "snoop_filter", + "system": "system", + "max_capacity": 8388608, + "eventq_index": 0, + "cxx_class": "SnoopFilter", + "path": "system.cpu.toL2Bus.snoop_filter", + "type": "SnoopFilter", + "lookup_latency": 0 + }, + "power_model": null, + "path": "system.cpu.toL2Bus", + "snoop_response_latency": 1, + "name": "toL2Bus", + "p_state_clk_gate_bins": 20, + "use_default_range": false + }, + "do_quiesce": true, + "type": "TimingSimpleCPU", + "profile": 0, + "icache_port": { + "peer": "system.cpu.icache.cpu_side", + "role": "MASTER" + }, + "p_state_clk_gate_bins": 20, + "p_state_clk_gate_min": 1000, + "interrupts": [ + { + "eventq_index": 0, + "path": "system.cpu.interrupts", + "type": "RiscvInterrupts", + "name": "interrupts", + "cxx_class": "RiscvISA::Interrupts" + } + ], + "dcache_port": { + "peer": "system.cpu.dcache.cpu_side", + "role": "MASTER" + }, + "socket_id": 0, + "power_model": null, + "max_insts_all_threads": 0, + "l2cache": { + "cpu_side": { + "peer": "system.cpu.toL2Bus.master[0]", + "role": "SLAVE" + }, + "clusivity": "mostly_incl", + "prefetcher": null, + "system": "system", + "write_buffers": 8, + "response_latency": 20, + "cxx_class": "Cache", + "size": 2097152, + "type": "Cache", + "clk_domain": "system.cpu_clk_domain", + "max_miss_count": 0, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "mem_side": { + "peer": "system.membus.slave[1]", + "role": "MASTER" + }, + "mshrs": 20, + "writeback_clean": false, + "p_state_clk_gate_min": 1000, + "tags": { + "size": 2097152, + "tag_latency": 20, + "name": "tags", + "p_state_clk_gate_min": 1000, + "eventq_index": 0, + "p_state_clk_gate_bins": 20, + "default_p_state": "UNDEFINED", + "clk_domain": "system.cpu_clk_domain", + "power_model": null, + "sequential_access": false, + "assoc": 8, + "cxx_class": "LRU", + "p_state_clk_gate_max": 1000000000000, + "path": "system.cpu.l2cache.tags", + "block_size": 64, + "type": "LRU", + "data_latency": 20 + }, + "tgts_per_mshr": 12, + "demand_mshr_reserve": 1, + "power_model": null, + "addr_ranges": [ + "0:18446744073709551615:0:0:0:0" + ], + "is_read_only": false, + "prefetch_on_access": false, + "path": "system.cpu.l2cache", + "data_latency": 20, + "tag_latency": 20, + "name": "l2cache", + "p_state_clk_gate_bins": 20, + "sequential_access": false, + "assoc": 8 + }, + "path": "system.cpu", + "max_loads_any_thread": 0, + "switched_out": false, + "workload": [ + { + "uid": 100, + "pid": 100, + "kvmInSE": false, + "cxx_class": "LiveProcess", + "executable": "/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64a/insttest", + "drivers": [], + "system": "system", + "gid": 100, + "eventq_index": 0, + "env": [], + "input": "cin", + "ppid": 99, + "type": "LiveProcess", + "cwd": "", + "simpoint": 0, + "euid": 100, + "path": "system.cpu.workload", + "max_stack_size": 67108864, + "name": "workload", + "cmd": [ + "insttest" + ], + "errout": "cerr", + "useArchPT": false, + "egid": 100, + "output": "cout" + } + ], + "name": "cpu", + "dtb": { + "name": "dtb", + "eventq_index": 0, + "cxx_class": "RiscvISA::TLB", + "path": "system.cpu.dtb", + "type": "RiscvTLB", + "size": 64 + }, + "simpoint_start_insts": [], + "max_insts_any_thread": 0, + "progress_interval": 0, + "branchPred": null, + "dcache": { + "cpu_side": { + "peer": "system.cpu.dcache_port", + "role": "SLAVE" + }, + "clusivity": "mostly_incl", + "prefetcher": null, + "system": "system", + "write_buffers": 8, + "response_latency": 2, + "cxx_class": "Cache", + "size": 262144, + "type": "Cache", + "clk_domain": "system.cpu_clk_domain", + "max_miss_count": 0, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "mem_side": { + "peer": "system.cpu.toL2Bus.slave[1]", + "role": "MASTER" + }, + "mshrs": 4, + "writeback_clean": false, + "p_state_clk_gate_min": 1000, + "tags": { + "size": 262144, + "tag_latency": 2, + "name": "tags", + "p_state_clk_gate_min": 1000, + "eventq_index": 0, + "p_state_clk_gate_bins": 20, + "default_p_state": "UNDEFINED", + "clk_domain": "system.cpu_clk_domain", + "power_model": null, + "sequential_access": false, + "assoc": 2, + "cxx_class": "LRU", + "p_state_clk_gate_max": 1000000000000, + "path": "system.cpu.dcache.tags", + "block_size": 64, + "type": "LRU", + "data_latency": 2 + }, + "tgts_per_mshr": 20, + "demand_mshr_reserve": 1, + "power_model": null, + "addr_ranges": [ + "0:18446744073709551615:0:0:0:0" + ], + "is_read_only": false, + "prefetch_on_access": false, + "path": "system.cpu.dcache", + "data_latency": 2, + "tag_latency": 2, + "name": "dcache", + "p_state_clk_gate_bins": 20, + "sequential_access": false, + "assoc": 2 + }, + "isa": [ + { + "eventq_index": 0, + "path": "system.cpu.isa", + "type": "RiscvISA", + "name": "isa", + "cxx_class": "RiscvISA::ISA" + } + ], + "tracer": { + "eventq_index": 0, + "path": "system.cpu.tracer", + "type": "ExeTracer", + "name": "tracer", + "cxx_class": "Trace::ExeTracer" + } + } + ], + "multi_thread": false, + "exit_on_work_items": false, + "work_item_id": -1, + "num_work_ids": 16 + }, + "time_sync_period": 100000000000, + "eventq_index": 0, + "time_sync_spin_threshold": 100000000, + "cxx_class": "Root", + "path": "root", + "time_sync_enable": false, + "type": "Root", + "full_system": false +}
\ No newline at end of file diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing/simerr b/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing/simerr new file mode 100755 index 000000000..fd133b12b --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing/simerr @@ -0,0 +1,3 @@ +warn: Unknown operating system; assuming Linux. +warn: Sockets disabled, not accepting gdb connections +warn: ClockedObject: More than one power state change request encountered within the same simulation tick diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing/simout b/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing/simout new file mode 100755 index 000000000..baa378d02 --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing/simout @@ -0,0 +1,15 @@ +Redirecting stdout to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64a/simple-timing/simout +Redirecting stderr to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64a/simple-timing/simerr +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled Nov 30 2016 14:33:35 +gem5 started Nov 30 2016 16:18:30 +gem5 executing on zizzer, pid 34063 +command line: /z/powerjg/gem5-upstream/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64a/simple-timing -re /z/powerjg/gem5-upstream/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64a/simple-timing + +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. +lr.w/sc.w: [1;31mFAIL[0m (expected (-1, 0); found (-1, 1)) +Exiting @ tick 138549500 because target called exit() diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing/stats.txt b/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing/stats.txt new file mode 100644 index 000000000..918afc87c --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing/stats.txt @@ -0,0 +1,519 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.000139 # Number of seconds simulated +sim_ticks 138549500 # Number of ticks simulated +final_tick 138549500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 338688 # Simulator instruction rate (inst/s) +host_op_rate 338651 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 708977788 # Simulator tick rate (ticks/s) +host_mem_usage 242940 # Number of bytes of host memory used +host_seconds 0.20 # Real time elapsed on the host +sim_insts 66173 # Number of instructions simulated +sim_ops 66173 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 138549500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 33600 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 16064 # Number of bytes read from this memory +system.physmem.bytes_read::total 49664 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 33600 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 33600 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 525 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 251 # Number of read requests responded to by this memory +system.physmem.num_reads::total 776 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 242512604 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 115944121 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 358456725 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 242512604 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 242512604 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 242512604 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 115944121 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 358456725 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 138549500 # Cumulative time (in ticks) in various power states +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 9 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 138549500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 277099 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 66173 # Number of instructions committed +system.cpu.committedOps 66173 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 66174 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses +system.cpu.num_func_calls 5169 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 10311 # number of instructions that are conditional controls +system.cpu.num_int_insts 66174 # number of integer instructions +system.cpu.num_fp_insts 0 # number of float instructions +system.cpu.num_int_register_reads 89437 # number of times the integer registers were read +system.cpu.num_int_register_writes 43419 # number of times the integer registers were written +system.cpu.num_fp_register_reads 0 # number of times the floating registers were read +system.cpu.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu.num_mem_refs 24255 # number of memory refs +system.cpu.num_load_insts 11810 # Number of load instructions +system.cpu.num_store_insts 12445 # Number of store instructions +system.cpu.num_idle_cycles 0 # Number of idle cycles +system.cpu.num_busy_cycles 277099 # Number of busy cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.Branches 15480 # Number of branches fetched +system.cpu.op_class::No_OpClass 9 0.01% 0.01% # Class of executed instruction +system.cpu.op_class::IntAlu 41896 63.30% 63.32% # Class of executed instruction +system.cpu.op_class::IntMult 15 0.02% 63.34% # Class of executed instruction +system.cpu.op_class::IntDiv 8 0.01% 63.35% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 63.35% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 63.35% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 63.35% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 63.35% # Class of executed instruction +system.cpu.op_class::FloatMultAcc 0 0.00% 63.35% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 63.35% # Class of executed instruction +system.cpu.op_class::FloatMisc 0 0.00% 63.35% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 63.35% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 63.35% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 63.35% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 63.35% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 63.35% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 63.35% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 63.35% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 63.35% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 63.35% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 63.35% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 63.35% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 63.35% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 63.35% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 63.35% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 63.35% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 63.35% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 63.35% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 63.35% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 63.35% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.35% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.35% # Class of executed instruction +system.cpu.op_class::MemRead 11810 17.84% 81.20% # Class of executed instruction +system.cpu.op_class::MemWrite 12445 18.80% 100.00% # Class of executed instruction +system.cpu.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 66183 # Class of executed instruction +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 138549500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 0 # number of replacements +system.cpu.dcache.tags.tagsinuse 195.060322 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 24002 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 251 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 95.625498 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 195.060322 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.047622 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.047622 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 251 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 4 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 52 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 195 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.061279 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 48757 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 48757 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 138549500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 11758 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 11758 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 12243 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 12243 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 1 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 1 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 24001 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 24001 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 24001 # number of overall hits +system.cpu.dcache.overall_hits::total 24001 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 51 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 51 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 200 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 200 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 251 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 251 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 251 # number of overall misses +system.cpu.dcache.overall_misses::total 251 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 3213000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 3213000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 12600000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 12600000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 15813000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 15813000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 15813000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 15813000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 11809 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 11809 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 12443 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 12443 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 1 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 24252 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 24252 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 24252 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 24252 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004319 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.004319 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.016073 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.016073 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.010350 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.010350 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.010350 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.010350 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63000 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 63000 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 63000 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 63000 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 63000 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 63000 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 63000 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 51 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 51 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 200 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 200 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 251 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 251 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 251 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 251 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3162000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 3162000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12400000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 12400000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 15562000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 15562000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 15562000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 15562000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.004319 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.004319 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.016073 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.016073 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.010350 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.010350 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.010350 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.010350 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 62000 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 62000 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 62000 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 62000 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 62000 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 62000 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 62000 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 62000 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 138549500 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 10 # number of replacements +system.cpu.icache.tags.tagsinuse 190.684855 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 65659 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 525 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 125.064762 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 190.684855 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.093108 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.093108 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 515 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 66 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 346 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 103 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.251465 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 132893 # Number of tag accesses +system.cpu.icache.tags.data_accesses 132893 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 138549500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 65659 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 65659 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 65659 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 65659 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 65659 # number of overall hits +system.cpu.icache.overall_hits::total 65659 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 525 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 525 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 525 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 525 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 525 # number of overall misses +system.cpu.icache.overall_misses::total 525 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 33076500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 33076500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 33076500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 33076500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 33076500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 33076500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 66184 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 66184 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 66184 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 66184 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 66184 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 66184 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.007932 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.007932 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.007932 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.007932 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.007932 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.007932 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 63002.857143 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 63002.857143 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 63002.857143 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 63002.857143 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 63002.857143 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 63002.857143 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.icache.writebacks::writebacks 10 # number of writebacks +system.cpu.icache.writebacks::total 10 # number of writebacks +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 525 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 525 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 525 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 525 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 525 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 525 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 32551500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 32551500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 32551500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 32551500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 32551500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 32551500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.007932 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.007932 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.007932 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.007932 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.007932 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.007932 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 62002.857143 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 62002.857143 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 62002.857143 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 62002.857143 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 62002.857143 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 62002.857143 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 138549500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.replacements 0 # number of replacements +system.cpu.l2cache.tags.tagsinuse 386.887852 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 10 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 776 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.012887 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::cpu.inst 191.808508 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 195.079344 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005854 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.005953 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.011807 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 776 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 70 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 405 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 301 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.023682 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 7064 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 7064 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 138549500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.WritebackClean_hits::writebacks 10 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 10 # number of WritebackClean hits +system.cpu.l2cache.ReadExReq_misses::cpu.data 200 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 200 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 525 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 525 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 51 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 51 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.inst 525 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 251 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 776 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 525 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 251 # number of overall misses +system.cpu.l2cache.overall_misses::total 776 # number of overall misses +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 12100000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 12100000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 31763500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 31763500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 3085500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 3085500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 31763500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 15185500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 46949000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 31763500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 15185500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 46949000 # number of overall miss cycles +system.cpu.l2cache.WritebackClean_accesses::writebacks 10 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 10 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 200 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 200 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 525 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 525 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 51 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 51 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 525 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 251 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 776 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 525 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 251 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 776 # number of overall (read+write) accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 1 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 1 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 1 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 1 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60500 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60500 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60501.904762 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60501.904762 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60500 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60500 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60501.904762 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60500 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 60501.288660 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60501.904762 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60500 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 60501.288660 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 200 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 200 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 525 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 525 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 51 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 51 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 525 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 251 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 776 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 525 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 251 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 776 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 10100000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 10100000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 26513500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 26513500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2575500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2575500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 26513500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 12675500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 39189000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 26513500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 12675500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 39189000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 1 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50501.904762 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50501.904762 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50501.904762 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50501.288660 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50501.904762 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50501.288660 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 786 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 10 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 138549500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 576 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 10 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 200 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 200 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 525 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 51 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1060 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 502 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 1562 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 34240 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 16064 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 50304 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 776 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 776 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 776 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 403000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 787500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.6 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 376500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.3 # Layer utilization (%) +system.membus.snoop_filter.tot_requests 776 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 138549500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 576 # Transaction distribution +system.membus.trans_dist::ReadExReq 200 # Transaction distribution +system.membus.trans_dist::ReadExResp 200 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 576 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1552 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1552 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 49664 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 49664 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoopTraffic 0 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 776 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 776 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 776 # Request fanout histogram +system.membus.reqLayer0.occupancy 777000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.6 # Layer utilization (%) +system.membus.respLayer1.occupancy 3880000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 2.8 # Layer utilization (%) + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/minor-timing/config.ini b/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/minor-timing/config.ini new file mode 100644 index 000000000..91d76ecd0 --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/minor-timing/config.ini @@ -0,0 +1,902 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain +boot_osflags=a +cache_line_size=64 +clk_domain=system.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +exit_on_work_items=false +init_param=0 +kernel= +kernel_addr_check=true +load_addr_mask=1099511627775 +load_offset=0 +mem_mode=timing +mem_ranges= +memories=system.physmem +mmap_using_noreserve=false +multi_thread=false +num_work_ids=16 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +readfile= +symbolfile= +thermal_components= +thermal_model=Null +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=MinorCPU +children=branchPred dcache dtb executeFuncUnits icache interrupts isa itb l2cache toL2Bus tracer workload +branchPred=system.cpu.branchPred +checker=Null +clk_domain=system.cpu_clk_domain +cpu_id=0 +decodeCycleInput=true +decodeInputBufferSize=3 +decodeInputWidth=2 +decodeToExecuteForwardDelay=1 +default_p_state=UNDEFINED +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +enableIdling=true +eventq_index=0 +executeAllowEarlyMemoryIssue=true +executeBranchDelay=1 +executeCommitLimit=2 +executeCycleInput=true +executeFuncUnits=system.cpu.executeFuncUnits +executeInputBufferSize=7 +executeInputWidth=2 +executeIssueLimit=2 +executeLSQMaxStoreBufferStoresPerCycle=2 +executeLSQRequestsQueueSize=1 +executeLSQStoreBufferSize=5 +executeLSQTransfersQueueSize=2 +executeMaxAccessesInMemory=2 +executeMemoryCommitLimit=1 +executeMemoryIssueLimit=1 +executeMemoryWidth=0 +executeSetTraceTimeOnCommit=true +executeSetTraceTimeOnIssue=false +fetch1FetchLimit=1 +fetch1LineSnapWidth=0 +fetch1LineWidth=0 +fetch1ToFetch2BackwardDelay=1 +fetch1ToFetch2ForwardDelay=1 +fetch2CycleInput=true +fetch2InputBufferSize=2 +fetch2ToDecodeForwardDelay=1 +function_trace=false +function_trace_start=0 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +profile=0 +progress_interval=0 +simpoint_start_insts= +socket_id=0 +switched_out=false +system=system +threadPolicy=RoundRobin +tracer=system.cpu.tracer +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.branchPred] +type=TournamentBP +BTBEntries=4096 +BTBTagSize=16 +RASSize=16 +choiceCtrBits=2 +choicePredictorSize=8192 +eventq_index=0 +globalCtrBits=2 +globalPredictorSize=8192 +indirectHashGHR=true +indirectHashTargets=true +indirectPathLength=3 +indirectSets=256 +indirectTagSize=16 +indirectWays=2 +instShiftAmt=2 +localCtrBits=2 +localHistoryTableSize=2048 +localPredictorSize=2048 +numThreads=1 +useIndirect=true + +[system.cpu.dcache] +type=Cache +children=tags +addr_ranges=0:18446744073709551615:0:0:0:0 +assoc=2 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +data_latency=2 +default_p_state=UNDEFINED +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=4 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=262144 +system=system +tag_latency=2 +tags=system.cpu.dcache.tags +tgts_per_mshr=20 +write_buffers=8 +writeback_clean=false +cpu_side=system.cpu.dcache_port +mem_side=system.cpu.toL2Bus.slave[1] + +[system.cpu.dcache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +data_latency=2 +default_p_state=UNDEFINED +eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +sequential_access=false +size=262144 +tag_latency=2 + +[system.cpu.dtb] +type=RiscvTLB +eventq_index=0 +size=64 + +[system.cpu.executeFuncUnits] +type=MinorFUPool +children=funcUnits0 funcUnits1 funcUnits2 funcUnits3 funcUnits4 funcUnits5 funcUnits6 +eventq_index=0 +funcUnits=system.cpu.executeFuncUnits.funcUnits0 system.cpu.executeFuncUnits.funcUnits1 system.cpu.executeFuncUnits.funcUnits2 system.cpu.executeFuncUnits.funcUnits3 system.cpu.executeFuncUnits.funcUnits4 system.cpu.executeFuncUnits.funcUnits5 system.cpu.executeFuncUnits.funcUnits6 + +[system.cpu.executeFuncUnits.funcUnits0] +type=MinorFU +children=opClasses timings +cantForwardFromFUIndices= +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses +opLat=3 +timings=system.cpu.executeFuncUnits.funcUnits0.timings + +[system.cpu.executeFuncUnits.funcUnits0.opClasses] +type=MinorOpClassSet +children=opClasses +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses + +[system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses] +type=MinorOpClass +eventq_index=0 +opClass=IntAlu + +[system.cpu.executeFuncUnits.funcUnits0.timings] +type=MinorFUTiming +children=opClasses +description=Int +eventq_index=0 +extraAssumedLat=0 +extraCommitLat=0 +extraCommitLatExpr=Null +mask=0 +match=0 +opClasses=system.cpu.executeFuncUnits.funcUnits0.timings.opClasses +srcRegsRelativeLats=2 +suppress=false + +[system.cpu.executeFuncUnits.funcUnits0.timings.opClasses] +type=MinorOpClassSet +eventq_index=0 +opClasses= + +[system.cpu.executeFuncUnits.funcUnits1] +type=MinorFU +children=opClasses timings +cantForwardFromFUIndices= +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses +opLat=3 +timings=system.cpu.executeFuncUnits.funcUnits1.timings + +[system.cpu.executeFuncUnits.funcUnits1.opClasses] +type=MinorOpClassSet +children=opClasses +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses + +[system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses] +type=MinorOpClass +eventq_index=0 +opClass=IntAlu + +[system.cpu.executeFuncUnits.funcUnits1.timings] +type=MinorFUTiming +children=opClasses +description=Int +eventq_index=0 +extraAssumedLat=0 +extraCommitLat=0 +extraCommitLatExpr=Null +mask=0 +match=0 +opClasses=system.cpu.executeFuncUnits.funcUnits1.timings.opClasses +srcRegsRelativeLats=2 +suppress=false + +[system.cpu.executeFuncUnits.funcUnits1.timings.opClasses] +type=MinorOpClassSet +eventq_index=0 +opClasses= + +[system.cpu.executeFuncUnits.funcUnits2] +type=MinorFU +children=opClasses timings +cantForwardFromFUIndices= +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits2.opClasses +opLat=3 +timings=system.cpu.executeFuncUnits.funcUnits2.timings + +[system.cpu.executeFuncUnits.funcUnits2.opClasses] +type=MinorOpClassSet +children=opClasses +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses + +[system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses] +type=MinorOpClass +eventq_index=0 +opClass=IntMult + +[system.cpu.executeFuncUnits.funcUnits2.timings] +type=MinorFUTiming +children=opClasses +description=Mul +eventq_index=0 +extraAssumedLat=0 +extraCommitLat=0 +extraCommitLatExpr=Null +mask=0 +match=0 +opClasses=system.cpu.executeFuncUnits.funcUnits2.timings.opClasses +srcRegsRelativeLats=0 +suppress=false + +[system.cpu.executeFuncUnits.funcUnits2.timings.opClasses] +type=MinorOpClassSet +eventq_index=0 +opClasses= + +[system.cpu.executeFuncUnits.funcUnits3] +type=MinorFU +children=opClasses +cantForwardFromFUIndices= +eventq_index=0 +issueLat=9 +opClasses=system.cpu.executeFuncUnits.funcUnits3.opClasses +opLat=9 +timings= + +[system.cpu.executeFuncUnits.funcUnits3.opClasses] +type=MinorOpClassSet +children=opClasses +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses + +[system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses] +type=MinorOpClass +eventq_index=0 +opClass=IntDiv + +[system.cpu.executeFuncUnits.funcUnits4] +type=MinorFU +children=opClasses timings +cantForwardFromFUIndices= +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses +opLat=6 +timings=system.cpu.executeFuncUnits.funcUnits4.timings + +[system.cpu.executeFuncUnits.funcUnits4.opClasses] +type=MinorOpClassSet +children=opClasses00 opClasses01 opClasses02 opClasses03 opClasses04 opClasses05 opClasses06 opClasses07 opClasses08 opClasses09 opClasses10 opClasses11 opClasses12 opClasses13 opClasses14 opClasses15 opClasses16 opClasses17 opClasses18 opClasses19 opClasses20 opClasses21 opClasses22 opClasses23 opClasses24 opClasses25 opClasses26 opClasses27 +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses26 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses27 + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00] +type=MinorOpClass +eventq_index=0 +opClass=FloatAdd + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01] +type=MinorOpClass +eventq_index=0 +opClass=FloatCmp + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02] +type=MinorOpClass +eventq_index=0 +opClass=FloatCvt + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03] +type=MinorOpClass +eventq_index=0 +opClass=FloatMisc + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04] +type=MinorOpClass +eventq_index=0 +opClass=FloatMult + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05] +type=MinorOpClass +eventq_index=0 +opClass=FloatMultAcc + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06] +type=MinorOpClass +eventq_index=0 +opClass=FloatDiv + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07] +type=MinorOpClass +eventq_index=0 +opClass=FloatSqrt + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08] +type=MinorOpClass +eventq_index=0 +opClass=SimdAdd + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09] +type=MinorOpClass +eventq_index=0 +opClass=SimdAddAcc + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10] +type=MinorOpClass +eventq_index=0 +opClass=SimdAlu + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11] +type=MinorOpClass +eventq_index=0 +opClass=SimdCmp + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12] +type=MinorOpClass +eventq_index=0 +opClass=SimdCvt + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13] +type=MinorOpClass +eventq_index=0 +opClass=SimdMisc + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14] +type=MinorOpClass +eventq_index=0 +opClass=SimdMult + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15] +type=MinorOpClass +eventq_index=0 +opClass=SimdMultAcc + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16] +type=MinorOpClass +eventq_index=0 +opClass=SimdShift + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17] +type=MinorOpClass +eventq_index=0 +opClass=SimdShiftAcc + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18] +type=MinorOpClass +eventq_index=0 +opClass=SimdSqrt + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatAdd + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatAlu + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatCmp + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatCvt + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatDiv + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatMisc + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatMult + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses26] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatMultAcc + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses27] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatSqrt + +[system.cpu.executeFuncUnits.funcUnits4.timings] +type=MinorFUTiming +children=opClasses +description=FloatSimd +eventq_index=0 +extraAssumedLat=0 +extraCommitLat=0 +extraCommitLatExpr=Null +mask=0 +match=0 +opClasses=system.cpu.executeFuncUnits.funcUnits4.timings.opClasses +srcRegsRelativeLats=2 +suppress=false + +[system.cpu.executeFuncUnits.funcUnits4.timings.opClasses] +type=MinorOpClassSet +eventq_index=0 +opClasses= + +[system.cpu.executeFuncUnits.funcUnits5] +type=MinorFU +children=opClasses timings +cantForwardFromFUIndices= +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses +opLat=1 +timings=system.cpu.executeFuncUnits.funcUnits5.timings + +[system.cpu.executeFuncUnits.funcUnits5.opClasses] +type=MinorOpClassSet +children=opClasses0 opClasses1 opClasses2 opClasses3 +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1 system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses2 system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses3 + +[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0] +type=MinorOpClass +eventq_index=0 +opClass=MemRead + +[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1] +type=MinorOpClass +eventq_index=0 +opClass=MemWrite + +[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses2] +type=MinorOpClass +eventq_index=0 +opClass=FloatMemRead + +[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses3] +type=MinorOpClass +eventq_index=0 +opClass=FloatMemWrite + +[system.cpu.executeFuncUnits.funcUnits5.timings] +type=MinorFUTiming +children=opClasses +description=Mem +eventq_index=0 +extraAssumedLat=2 +extraCommitLat=0 +extraCommitLatExpr=Null +mask=0 +match=0 +opClasses=system.cpu.executeFuncUnits.funcUnits5.timings.opClasses +srcRegsRelativeLats=1 +suppress=false + +[system.cpu.executeFuncUnits.funcUnits5.timings.opClasses] +type=MinorOpClassSet +eventq_index=0 +opClasses= + +[system.cpu.executeFuncUnits.funcUnits6] +type=MinorFU +children=opClasses +cantForwardFromFUIndices= +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses +opLat=1 +timings= + +[system.cpu.executeFuncUnits.funcUnits6.opClasses] +type=MinorOpClassSet +children=opClasses0 opClasses1 +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1 + +[system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0] +type=MinorOpClass +eventq_index=0 +opClass=IprAccess + +[system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1] +type=MinorOpClass +eventq_index=0 +opClass=InstPrefetch + +[system.cpu.icache] +type=Cache +children=tags +addr_ranges=0:18446744073709551615:0:0:0:0 +assoc=2 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +data_latency=2 +default_p_state=UNDEFINED +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=true +max_miss_count=0 +mshrs=4 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=131072 +system=system +tag_latency=2 +tags=system.cpu.icache.tags +tgts_per_mshr=20 +write_buffers=8 +writeback_clean=true +cpu_side=system.cpu.icache_port +mem_side=system.cpu.toL2Bus.slave[0] + +[system.cpu.icache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +data_latency=2 +default_p_state=UNDEFINED +eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +sequential_access=false +size=131072 +tag_latency=2 + +[system.cpu.interrupts] +type=RiscvInterrupts +eventq_index=0 + +[system.cpu.isa] +type=RiscvISA +eventq_index=0 + +[system.cpu.itb] +type=RiscvTLB +eventq_index=0 +size=64 + +[system.cpu.l2cache] +type=Cache +children=tags +addr_ranges=0:18446744073709551615:0:0:0:0 +assoc=8 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +data_latency=20 +default_p_state=UNDEFINED +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=20 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +prefetch_on_access=false +prefetcher=Null +response_latency=20 +sequential_access=false +size=2097152 +system=system +tag_latency=20 +tags=system.cpu.l2cache.tags +tgts_per_mshr=12 +write_buffers=8 +writeback_clean=false +cpu_side=system.cpu.toL2Bus.master[0] +mem_side=system.membus.slave[1] + +[system.cpu.l2cache.tags] +type=LRU +assoc=8 +block_size=64 +clk_domain=system.cpu_clk_domain +data_latency=20 +default_p_state=UNDEFINED +eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +sequential_access=false +size=2097152 +tag_latency=20 + +[system.cpu.toL2Bus] +type=CoherentXBar +children=snoop_filter +clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED +eventq_index=0 +forward_latency=0 +frontend_latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +point_of_coherency=false +power_model=Null +response_latency=1 +snoop_filter=system.cpu.toL2Bus.snoop_filter +snoop_response_latency=1 +system=system +use_default_range=false +width=32 +master=system.cpu.l2cache.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side + +[system.cpu.toL2Bus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=0 +max_capacity=8388608 +system=system + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=LiveProcess +cmd=insttest +cwd= +drivers= +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable=/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64d/insttest +gid=100 +input=cin +kvmInSE=false +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=0 +system=system +uid=100 +useArchPT=false + +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000000 + +[system.membus] +type=CoherentXBar +children=snoop_filter +clk_domain=system.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +forward_latency=4 +frontend_latency=3 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +point_of_coherency=true +power_model=Null +response_latency=2 +snoop_filter=system.membus.snoop_filter +snoop_response_latency=4 +system=system +use_default_range=false +width=16 +master=system.physmem.port +slave=system.system_port system.cpu.l2cache.mem_side + +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + +[system.physmem] +type=DRAMCtrl +IDD0=0.055000 +IDD02=0.000000 +IDD2N=0.032000 +IDD2N2=0.000000 +IDD2P0=0.000000 +IDD2P02=0.000000 +IDD2P1=0.032000 +IDD2P12=0.000000 +IDD3N=0.038000 +IDD3N2=0.000000 +IDD3P0=0.000000 +IDD3P02=0.000000 +IDD3P1=0.038000 +IDD3P12=0.000000 +IDD4R=0.157000 +IDD4R2=0.000000 +IDD4W=0.125000 +IDD4W2=0.000000 +IDD5=0.235000 +IDD52=0.000000 +IDD6=0.020000 +IDD62=0.000000 +VDD=1.500000 +VDD2=0.000000 +activation_limit=4 +addr_mapping=RoRaBaCoCh +bank_groups_per_rank=0 +banks_per_rank=8 +burst_length=8 +channels=1 +clk_domain=system.clk_domain +conf_table_reported=true +default_p_state=UNDEFINED +device_bus_width=8 +device_rowbuffer_size=1024 +device_size=536870912 +devices_per_rank=8 +dll=true +eventq_index=0 +in_addr_map=true +kvm_map=true +max_accesses_per_row=16 +mem_sched_policy=frfcfs +min_writes_per_switch=16 +null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +page_policy=open_adaptive +power_model=Null +range=0:134217727:0:0:0:0 +ranks_per_channel=2 +read_buffer_size=32 +static_backend_latency=10000 +static_frontend_latency=10000 +tBURST=5000 +tCCD_L=0 +tCK=1250 +tCL=13750 +tCS=2500 +tRAS=35000 +tRCD=13750 +tREFI=7800000 +tRFC=260000 +tRP=13750 +tRRD=6000 +tRRD_L=0 +tRTP=7500 +tRTW=2500 +tWR=15000 +tWTR=7500 +tXAW=30000 +tXP=6000 +tXPDLL=0 +tXS=270000 +tXSDLL=0 +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 +port=system.membus.master[0] + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/minor-timing/config.json b/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/minor-timing/config.json new file mode 100644 index 000000000..e97e6327e --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/minor-timing/config.json @@ -0,0 +1,1211 @@ +{ + "name": null, + "sim_quantum": 0, + "system": { + "kernel": "", + "mmap_using_noreserve": false, + "kernel_addr_check": true, + "membus": { + "point_of_coherency": true, + "system": "system", + "response_latency": 2, + "cxx_class": "CoherentXBar", + "forward_latency": 4, + "clk_domain": "system.clk_domain", + "width": 16, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "master": { + "peer": [ + "system.physmem.port" + ], + "role": "MASTER" + }, + "type": "CoherentXBar", + "frontend_latency": 3, + "slave": { + "peer": [ + "system.system_port", + "system.cpu.l2cache.mem_side" + ], + "role": "SLAVE" + }, + "p_state_clk_gate_min": 1000, + "snoop_filter": { + "name": "snoop_filter", + "system": "system", + "max_capacity": 8388608, + "eventq_index": 0, + "cxx_class": "SnoopFilter", + "path": "system.membus.snoop_filter", + "type": "SnoopFilter", + "lookup_latency": 1 + }, + "power_model": null, + "path": "system.membus", + "snoop_response_latency": 4, + "name": "membus", + "p_state_clk_gate_bins": 20, + "use_default_range": false + }, + "symbolfile": "", + "readfile": "", + "thermal_model": null, + "cxx_class": "System", + "work_begin_cpu_id_exit": -1, + "load_offset": 0, + "work_begin_exit_count": 0, + "p_state_clk_gate_min": 1000, + "memories": [ + "system.physmem" + ], + "work_begin_ckpt_count": 0, + "clk_domain": { + "name": "clk_domain", + "clock": [ + 1000 + ], + "init_perf_level": 0, + "voltage_domain": "system.voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "mem_ranges": [], + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "dvfs_handler": { + "enable": false, + "name": "dvfs_handler", + "sys_clk_domain": "system.clk_domain", + "transition_latency": 100000000, + "eventq_index": 0, + "cxx_class": "DVFSHandler", + "domains": [], + "path": "system.dvfs_handler", + "type": "DVFSHandler" + }, + "work_end_exit_count": 0, + "type": "System", + "voltage_domain": { + "name": "voltage_domain", + "eventq_index": 0, + "voltage": [ + "1.0" + ], + "cxx_class": "VoltageDomain", + "path": "system.voltage_domain", + "type": "VoltageDomain" + }, + "cache_line_size": 64, + "boot_osflags": "a", + "system_port": { + "peer": "system.membus.slave[0]", + "role": "MASTER" + }, + "physmem": { + "static_frontend_latency": 10000, + "tRFC": 260000, + "activation_limit": 4, + "in_addr_map": true, + "IDD3N2": "0.0", + "tWTR": 7500, + "IDD52": "0.0", + "clk_domain": "system.clk_domain", + "channels": 1, + "write_buffer_size": 64, + "device_bus_width": 8, + "VDD": "1.5", + "write_high_thresh_perc": 85, + "cxx_class": "DRAMCtrl", + "bank_groups_per_rank": 0, + "IDD2N2": "0.0", + "port": { + "peer": "system.membus.master[0]", + "role": "SLAVE" + }, + "tCCD_L": 0, + "IDD2N": "0.032", + "p_state_clk_gate_min": 1000, + "null": false, + "IDD2P1": "0.032", + "eventq_index": 0, + "tRRD": 6000, + "tRTW": 2500, + "IDD4R": "0.157", + "burst_length": 8, + "tRTP": 7500, + "IDD4W": "0.125", + "tWR": 15000, + "banks_per_rank": 8, + "devices_per_rank": 8, + "IDD2P02": "0.0", + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "IDD6": "0.02", + "IDD5": "0.235", + "tRCD": 13750, + "type": "DRAMCtrl", + "IDD3P02": "0.0", + "tRRD_L": 0, + "IDD0": "0.055", + "IDD62": "0.0", + "min_writes_per_switch": 16, + "mem_sched_policy": "frfcfs", + "IDD02": "0.0", + "IDD2P0": "0.0", + "ranks_per_channel": 2, + "page_policy": "open_adaptive", + "IDD4W2": "0.0", + "tCS": 2500, + "power_model": null, + "tCL": 13750, + "read_buffer_size": 32, + "conf_table_reported": true, + "tCK": 1250, + "tRAS": 35000, + "tRP": 13750, + "tBURST": 5000, + "path": "system.physmem", + "tXP": 6000, + "tXS": 270000, + "addr_mapping": "RoRaBaCoCh", + "IDD3P0": "0.0", + "IDD3P1": "0.038", + "IDD3N": "0.038", + "name": "physmem", + "tXSDLL": 0, + "device_size": 536870912, + "kvm_map": true, + "dll": true, + "tXAW": 30000, + "write_low_thresh_perc": 50, + "range": "0:134217727:0:0:0:0", + "VDD2": "0.0", + "IDD2P12": "0.0", + "p_state_clk_gate_bins": 20, + "tXPDLL": 0, + "IDD4R2": "0.0", + "device_rowbuffer_size": 1024, + "static_backend_latency": 10000, + "max_accesses_per_row": 16, + "IDD3P12": "0.0", + "tREFI": 7800000 + }, + "power_model": null, + "work_cpus_ckpt_count": 0, + "thermal_components": [], + "path": "system", + "cpu_clk_domain": { + "name": "cpu_clk_domain", + "clock": [ + 500 + ], + "init_perf_level": 0, + "voltage_domain": "system.voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.cpu_clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "work_end_ckpt_count": 0, + "mem_mode": "timing", + "name": "system", + "init_param": 0, + "p_state_clk_gate_bins": 20, + "load_addr_mask": 1099511627775, + "cpu": [ + { + "max_insts_any_thread": 0, + "do_statistics_insts": true, + "numThreads": 1, + "fetch1LineSnapWidth": 0, + "fetch1ToFetch2BackwardDelay": 1, + "fetch1FetchLimit": 1, + "executeIssueLimit": 2, + "system": "system", + "executeLSQMaxStoreBufferStoresPerCycle": 2, + "icache": { + "cpu_side": { + "peer": "system.cpu.icache_port", + "role": "SLAVE" + }, + "clusivity": "mostly_incl", + "prefetcher": null, + "system": "system", + "write_buffers": 8, + "response_latency": 2, + "cxx_class": "Cache", + "size": 131072, + "type": "Cache", + "clk_domain": "system.cpu_clk_domain", + "max_miss_count": 0, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "mem_side": { + "peer": "system.cpu.toL2Bus.slave[0]", + "role": "MASTER" + }, + "mshrs": 4, + "writeback_clean": true, + "p_state_clk_gate_min": 1000, + "tags": { + "size": 131072, + "tag_latency": 2, + "name": "tags", + "p_state_clk_gate_min": 1000, + "eventq_index": 0, + "p_state_clk_gate_bins": 20, + "default_p_state": "UNDEFINED", + "clk_domain": "system.cpu_clk_domain", + "power_model": null, + "sequential_access": false, + "assoc": 2, + "cxx_class": "LRU", + "p_state_clk_gate_max": 1000000000000, + "path": "system.cpu.icache.tags", + "block_size": 64, + "type": "LRU", + "data_latency": 2 + }, + "tgts_per_mshr": 20, + "demand_mshr_reserve": 1, + "power_model": null, + "addr_ranges": [ + "0:18446744073709551615:0:0:0:0" + ], + "is_read_only": true, + "prefetch_on_access": false, + "path": "system.cpu.icache", + "data_latency": 2, + "tag_latency": 2, + "name": "icache", + "p_state_clk_gate_bins": 20, + "sequential_access": false, + "assoc": 2 + }, + "function_trace": false, + "do_checkpoint_insts": true, + "decodeInputWidth": 2, + "cxx_class": "MinorCPU", + "max_loads_all_threads": 0, + "executeMemoryIssueLimit": 1, + "decodeCycleInput": true, + "max_loads_any_thread": 0, + "executeLSQTransfersQueueSize": 2, + "p_state_clk_gate_max": 1000000000000, + "clk_domain": "system.cpu_clk_domain", + "function_trace_start": 0, + "cpu_id": 0, + "checker": null, + "eventq_index": 0, + "executeMemoryWidth": 0, + "default_p_state": "UNDEFINED", + "executeBranchDelay": 1, + "executeMemoryCommitLimit": 1, + "l2cache": { + "cpu_side": { + "peer": "system.cpu.toL2Bus.master[0]", + "role": "SLAVE" + }, + "clusivity": "mostly_incl", + "prefetcher": null, + "system": "system", + "write_buffers": 8, + "response_latency": 20, + "cxx_class": "Cache", + "size": 2097152, + "type": "Cache", + "clk_domain": "system.cpu_clk_domain", + "max_miss_count": 0, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "mem_side": { + "peer": "system.membus.slave[1]", + "role": "MASTER" + }, + "mshrs": 20, + "writeback_clean": false, + "p_state_clk_gate_min": 1000, + "tags": { + "size": 2097152, + "tag_latency": 20, + "name": "tags", + "p_state_clk_gate_min": 1000, + "eventq_index": 0, + "p_state_clk_gate_bins": 20, + "default_p_state": "UNDEFINED", + "clk_domain": "system.cpu_clk_domain", + "power_model": null, + "sequential_access": false, + "assoc": 8, + "cxx_class": "LRU", + "p_state_clk_gate_max": 1000000000000, + "path": "system.cpu.l2cache.tags", + "block_size": 64, + "type": "LRU", + "data_latency": 20 + }, + "tgts_per_mshr": 12, + "demand_mshr_reserve": 1, + "power_model": null, + "addr_ranges": [ + "0:18446744073709551615:0:0:0:0" + ], + "is_read_only": false, + "prefetch_on_access": false, + "path": "system.cpu.l2cache", + "data_latency": 20, + "tag_latency": 20, + "name": "l2cache", + "p_state_clk_gate_bins": 20, + "sequential_access": false, + "assoc": 8 + }, + "do_quiesce": true, + "type": "MinorCPU", + "executeCycleInput": true, + "executeAllowEarlyMemoryIssue": true, + "executeInputBufferSize": 7, + "icache_port": { + "peer": "system.cpu.icache.cpu_side", + "role": "MASTER" + }, + "p_state_clk_gate_bins": 20, + "socket_id": 0, + "progress_interval": 0, + "p_state_clk_gate_min": 1000, + "toL2Bus": { + "point_of_coherency": false, + "system": "system", + "response_latency": 1, + "cxx_class": "CoherentXBar", + "forward_latency": 0, + "clk_domain": "system.cpu_clk_domain", + "width": 32, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "master": { + "peer": [ + "system.cpu.l2cache.cpu_side" + ], + "role": "MASTER" + }, + "type": "CoherentXBar", + "frontend_latency": 1, + "slave": { + "peer": [ + "system.cpu.icache.mem_side", + "system.cpu.dcache.mem_side" + ], + "role": "SLAVE" + }, + "p_state_clk_gate_min": 1000, + "snoop_filter": { + "name": "snoop_filter", + "system": "system", + "max_capacity": 8388608, + "eventq_index": 0, + "cxx_class": "SnoopFilter", + "path": "system.cpu.toL2Bus.snoop_filter", + "type": "SnoopFilter", + "lookup_latency": 0 + }, + "power_model": null, + "path": "system.cpu.toL2Bus", + "snoop_response_latency": 1, + "name": "toL2Bus", + "p_state_clk_gate_bins": 20, + "use_default_range": false + }, + "isa": [ + { + "eventq_index": 0, + "path": "system.cpu.isa", + "type": "RiscvISA", + "name": "isa", + "cxx_class": "RiscvISA::ISA" + } + ], + "itb": { + "name": "itb", + "eventq_index": 0, + "cxx_class": "RiscvISA::TLB", + "path": "system.cpu.itb", + "type": "RiscvTLB", + "size": 64 + }, + "interrupts": [ + { + "eventq_index": 0, + "path": "system.cpu.interrupts", + "type": "RiscvInterrupts", + "name": "interrupts", + "cxx_class": "RiscvISA::Interrupts" + } + ], + "dcache_port": { + "peer": "system.cpu.dcache.cpu_side", + "role": "MASTER" + }, + "executeFuncUnits": { + "name": "executeFuncUnits", + "eventq_index": 0, + "cxx_class": "MinorFUPool", + "path": "system.cpu.executeFuncUnits", + "funcUnits": [ + { + "issueLat": 1, + "opLat": 3, + "name": "funcUnits0", + "cantForwardFromFUIndices": [], + "opClasses": { + "name": "opClasses", + "opClasses": [ + { + "opClass": "IntAlu", + "name": "opClasses", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses", + "type": "MinorOpClass" + } + ], + "eventq_index": 0, + "cxx_class": "MinorOpClassSet", + "path": "system.cpu.executeFuncUnits.funcUnits0.opClasses", + "type": "MinorOpClassSet" + }, + "eventq_index": 0, + "timings": [ + { + "extraAssumedLat": 0, + "description": "Int", + "srcRegsRelativeLats": [ + 2 + ], + "suppress": false, + "mask": 0, + "extraCommitLat": 0, + "eventq_index": 0, + "opClasses": { + "name": "opClasses", + "opClasses": [], + "eventq_index": 0, + "cxx_class": "MinorOpClassSet", + "path": "system.cpu.executeFuncUnits.funcUnits0.timings.opClasses", + "type": "MinorOpClassSet" + }, + "cxx_class": "MinorFUTiming", + "path": "system.cpu.executeFuncUnits.funcUnits0.timings", + "extraCommitLatExpr": null, + "type": "MinorFUTiming", + "match": 0, + "name": "timings" + } + ], + "cxx_class": "MinorFU", + "path": "system.cpu.executeFuncUnits.funcUnits0", + "type": "MinorFU" + }, + { + "issueLat": 1, + "opLat": 3, + "name": "funcUnits1", + "cantForwardFromFUIndices": [], + "opClasses": { + "name": "opClasses", + "opClasses": [ + { + "opClass": "IntAlu", + "name": "opClasses", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses", + "type": "MinorOpClass" + } + ], + "eventq_index": 0, + "cxx_class": "MinorOpClassSet", + "path": "system.cpu.executeFuncUnits.funcUnits1.opClasses", + "type": "MinorOpClassSet" + }, + "eventq_index": 0, + "timings": [ + { + "extraAssumedLat": 0, + "description": "Int", + "srcRegsRelativeLats": [ + 2 + ], + "suppress": false, + "mask": 0, + "extraCommitLat": 0, + "eventq_index": 0, + "opClasses": { + "name": "opClasses", + "opClasses": [], + "eventq_index": 0, + "cxx_class": "MinorOpClassSet", + "path": "system.cpu.executeFuncUnits.funcUnits1.timings.opClasses", + "type": "MinorOpClassSet" + }, + "cxx_class": "MinorFUTiming", + "path": "system.cpu.executeFuncUnits.funcUnits1.timings", + "extraCommitLatExpr": null, + "type": "MinorFUTiming", + "match": 0, + "name": "timings" + } + ], + "cxx_class": "MinorFU", + "path": "system.cpu.executeFuncUnits.funcUnits1", + "type": "MinorFU" + }, + { + "issueLat": 1, + "opLat": 3, + "name": "funcUnits2", + "cantForwardFromFUIndices": [], + "opClasses": { + "name": "opClasses", + "opClasses": [ + { + "opClass": "IntMult", + "name": "opClasses", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses", + "type": "MinorOpClass" + } + ], + "eventq_index": 0, + "cxx_class": "MinorOpClassSet", + "path": "system.cpu.executeFuncUnits.funcUnits2.opClasses", + "type": "MinorOpClassSet" + }, + "eventq_index": 0, + "timings": [ + { + "extraAssumedLat": 0, + "description": "Mul", + "srcRegsRelativeLats": [ + 0 + ], + "suppress": false, + "mask": 0, + "extraCommitLat": 0, + "eventq_index": 0, + "opClasses": { + "name": "opClasses", + "opClasses": [], + "eventq_index": 0, + "cxx_class": "MinorOpClassSet", + "path": "system.cpu.executeFuncUnits.funcUnits2.timings.opClasses", + "type": "MinorOpClassSet" + }, + "cxx_class": "MinorFUTiming", + "path": "system.cpu.executeFuncUnits.funcUnits2.timings", + "extraCommitLatExpr": null, + "type": "MinorFUTiming", + "match": 0, + "name": "timings" + } + ], + "cxx_class": "MinorFU", + "path": "system.cpu.executeFuncUnits.funcUnits2", + "type": "MinorFU" + }, + { + "issueLat": 9, + "opLat": 9, + "name": "funcUnits3", + "cantForwardFromFUIndices": [], + "opClasses": { + "name": "opClasses", + "opClasses": [ + { + "opClass": "IntDiv", + "name": "opClasses", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses", + "type": "MinorOpClass" + } + ], + "eventq_index": 0, + "cxx_class": "MinorOpClassSet", + "path": "system.cpu.executeFuncUnits.funcUnits3.opClasses", + "type": "MinorOpClassSet" + }, + "eventq_index": 0, + "timings": [], + "cxx_class": "MinorFU", + "path": "system.cpu.executeFuncUnits.funcUnits3", + "type": "MinorFU" + }, + { + "issueLat": 1, + "opLat": 6, + "name": "funcUnits4", + "cantForwardFromFUIndices": [], + "opClasses": { + "name": "opClasses", + "opClasses": [ + { + "opClass": "FloatAdd", + "name": "opClasses00", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00", + "type": "MinorOpClass" + }, + { + "opClass": "FloatCmp", + "name": "opClasses01", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01", + "type": "MinorOpClass" + }, + { + "opClass": "FloatCvt", + "name": "opClasses02", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02", + "type": "MinorOpClass" + }, + { + "opClass": "FloatMisc", + "name": "opClasses03", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03", + "type": "MinorOpClass" + }, + { + "opClass": "FloatMult", + "name": "opClasses04", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04", + "type": "MinorOpClass" + }, + { + "opClass": "FloatMultAcc", + "name": "opClasses05", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05", + "type": "MinorOpClass" + }, + { + "opClass": "FloatDiv", + "name": "opClasses06", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06", + "type": "MinorOpClass" + }, + { + "opClass": "FloatSqrt", + "name": "opClasses07", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07", + "type": "MinorOpClass" + }, + { + "opClass": "SimdAdd", + "name": "opClasses08", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08", + "type": "MinorOpClass" + }, + { + "opClass": "SimdAddAcc", + "name": "opClasses09", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09", + "type": "MinorOpClass" + }, + { + "opClass": "SimdAlu", + "name": "opClasses10", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10", + "type": "MinorOpClass" + }, + { + "opClass": "SimdCmp", + "name": "opClasses11", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11", + "type": "MinorOpClass" + }, + { + "opClass": "SimdCvt", + "name": "opClasses12", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12", + "type": "MinorOpClass" + }, + { + "opClass": "SimdMisc", + "name": "opClasses13", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13", + "type": "MinorOpClass" + }, + { + "opClass": "SimdMult", + "name": "opClasses14", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14", + "type": "MinorOpClass" + }, + { + "opClass": "SimdMultAcc", + "name": "opClasses15", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15", + "type": "MinorOpClass" + }, + { + "opClass": "SimdShift", + "name": "opClasses16", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16", + "type": "MinorOpClass" + }, + { + "opClass": "SimdShiftAcc", + "name": "opClasses17", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17", + "type": "MinorOpClass" + }, + { + "opClass": "SimdSqrt", + "name": "opClasses18", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18", + "type": "MinorOpClass" + }, + { + "opClass": "SimdFloatAdd", + "name": "opClasses19", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19", + "type": "MinorOpClass" + }, + { + "opClass": "SimdFloatAlu", + "name": "opClasses20", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20", + "type": "MinorOpClass" + }, + { + "opClass": "SimdFloatCmp", + "name": "opClasses21", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21", + "type": "MinorOpClass" + }, + { + "opClass": "SimdFloatCvt", + "name": "opClasses22", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22", + "type": "MinorOpClass" + }, + { + "opClass": "SimdFloatDiv", + "name": "opClasses23", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23", + "type": "MinorOpClass" + }, + { + "opClass": "SimdFloatMisc", + "name": "opClasses24", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24", + "type": "MinorOpClass" + }, + { + "opClass": "SimdFloatMult", + "name": "opClasses25", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25", + "type": "MinorOpClass" + }, + { + "opClass": "SimdFloatMultAcc", + "name": "opClasses26", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses26", + "type": "MinorOpClass" + }, + { + "opClass": "SimdFloatSqrt", + "name": "opClasses27", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses27", + "type": "MinorOpClass" + } + ], + "eventq_index": 0, + "cxx_class": "MinorOpClassSet", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses", + "type": "MinorOpClassSet" + }, + "eventq_index": 0, + "timings": [ + { + "extraAssumedLat": 0, + "description": "FloatSimd", + "srcRegsRelativeLats": [ + 2 + ], + "suppress": false, + "mask": 0, + "extraCommitLat": 0, + "eventq_index": 0, + "opClasses": { + "name": "opClasses", + "opClasses": [], + "eventq_index": 0, + "cxx_class": "MinorOpClassSet", + "path": "system.cpu.executeFuncUnits.funcUnits4.timings.opClasses", + "type": "MinorOpClassSet" + }, + "cxx_class": "MinorFUTiming", + "path": "system.cpu.executeFuncUnits.funcUnits4.timings", + "extraCommitLatExpr": null, + "type": "MinorFUTiming", + "match": 0, + "name": "timings" + } + ], + "cxx_class": "MinorFU", + "path": "system.cpu.executeFuncUnits.funcUnits4", + "type": "MinorFU" + }, + { + "issueLat": 1, + "opLat": 1, + "name": "funcUnits5", + "cantForwardFromFUIndices": [], + "opClasses": { + "name": "opClasses", + "opClasses": [ + { + "opClass": "MemRead", + "name": "opClasses0", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0", + "type": "MinorOpClass" + }, + { + "opClass": "MemWrite", + "name": "opClasses1", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1", + "type": "MinorOpClass" + }, + { + "opClass": "FloatMemRead", + "name": "opClasses2", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses2", + "type": "MinorOpClass" + }, + { + "opClass": "FloatMemWrite", + "name": "opClasses3", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses3", + "type": "MinorOpClass" + } + ], + "eventq_index": 0, + "cxx_class": "MinorOpClassSet", + "path": "system.cpu.executeFuncUnits.funcUnits5.opClasses", + "type": "MinorOpClassSet" + }, + "eventq_index": 0, + "timings": [ + { + "extraAssumedLat": 2, + "description": "Mem", + "srcRegsRelativeLats": [ + 1 + ], + "suppress": false, + "mask": 0, + "extraCommitLat": 0, + "eventq_index": 0, + "opClasses": { + "name": "opClasses", + "opClasses": [], + "eventq_index": 0, + "cxx_class": "MinorOpClassSet", + "path": "system.cpu.executeFuncUnits.funcUnits5.timings.opClasses", + "type": "MinorOpClassSet" + }, + "cxx_class": "MinorFUTiming", + "path": "system.cpu.executeFuncUnits.funcUnits5.timings", + "extraCommitLatExpr": null, + "type": "MinorFUTiming", + "match": 0, + "name": "timings" + } + ], + "cxx_class": "MinorFU", + "path": "system.cpu.executeFuncUnits.funcUnits5", + "type": "MinorFU" + }, + { + "issueLat": 1, + "opLat": 1, + "name": "funcUnits6", + "cantForwardFromFUIndices": [], + "opClasses": { + "name": "opClasses", + "opClasses": [ + { + "opClass": "IprAccess", + "name": "opClasses0", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0", + "type": "MinorOpClass" + }, + { + "opClass": "InstPrefetch", + "name": "opClasses1", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1", + "type": "MinorOpClass" + } + ], + "eventq_index": 0, + "cxx_class": "MinorOpClassSet", + "path": "system.cpu.executeFuncUnits.funcUnits6.opClasses", + "type": "MinorOpClassSet" + }, + "eventq_index": 0, + "timings": [], + "cxx_class": "MinorFU", + "path": "system.cpu.executeFuncUnits.funcUnits6", + "type": "MinorFU" + } + ], + "type": "MinorFUPool" + }, + "switched_out": false, + "power_model": null, + "max_insts_all_threads": 0, + "executeSetTraceTimeOnIssue": false, + "fetch2InputBufferSize": 2, + "profile": 0, + "fetch2ToDecodeForwardDelay": 1, + "executeInputWidth": 2, + "decodeToExecuteForwardDelay": 1, + "executeLSQRequestsQueueSize": 1, + "fetch2CycleInput": true, + "executeMaxAccessesInMemory": 2, + "enableIdling": true, + "executeLSQStoreBufferSize": 5, + "workload": [ + { + "uid": 100, + "pid": 100, + "kvmInSE": false, + "cxx_class": "LiveProcess", + "executable": "/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64d/insttest", + "drivers": [], + "system": "system", + "gid": 100, + "eventq_index": 0, + "env": [], + "input": "cin", + "ppid": 99, + "type": "LiveProcess", + "cwd": "", + "simpoint": 0, + "euid": 100, + "path": "system.cpu.workload", + "max_stack_size": 67108864, + "name": "workload", + "cmd": [ + "insttest" + ], + "errout": "cerr", + "useArchPT": false, + "egid": 100, + "output": "cout" + } + ], + "name": "cpu", + "dtb": { + "name": "dtb", + "eventq_index": 0, + "cxx_class": "RiscvISA::TLB", + "path": "system.cpu.dtb", + "type": "RiscvTLB", + "size": 64 + }, + "simpoint_start_insts": [], + "executeSetTraceTimeOnCommit": true, + "tracer": { + "eventq_index": 0, + "path": "system.cpu.tracer", + "type": "ExeTracer", + "name": "tracer", + "cxx_class": "Trace::ExeTracer" + }, + "threadPolicy": "RoundRobin", + "executeCommitLimit": 2, + "fetch1LineWidth": 0, + "branchPred": { + "numThreads": 1, + "BTBEntries": 4096, + "cxx_class": "TournamentBP", + "indirectPathLength": 3, + "globalCtrBits": 2, + "choicePredictorSize": 8192, + "indirectHashGHR": true, + "eventq_index": 0, + "localHistoryTableSize": 2048, + "type": "TournamentBP", + "indirectSets": 256, + "indirectWays": 2, + "choiceCtrBits": 2, + "useIndirect": true, + "localCtrBits": 2, + "path": "system.cpu.branchPred", + "localPredictorSize": 2048, + "RASSize": 16, + "globalPredictorSize": 8192, + "name": "branchPred", + "indirectHashTargets": true, + "instShiftAmt": 2, + "indirectTagSize": 16, + "BTBTagSize": 16 + }, + "dcache": { + "cpu_side": { + "peer": "system.cpu.dcache_port", + "role": "SLAVE" + }, + "clusivity": "mostly_incl", + "prefetcher": null, + "system": "system", + "write_buffers": 8, + "response_latency": 2, + "cxx_class": "Cache", + "size": 262144, + "type": "Cache", + "clk_domain": "system.cpu_clk_domain", + "max_miss_count": 0, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "mem_side": { + "peer": "system.cpu.toL2Bus.slave[1]", + "role": "MASTER" + }, + "mshrs": 4, + "writeback_clean": false, + "p_state_clk_gate_min": 1000, + "tags": { + "size": 262144, + "tag_latency": 2, + "name": "tags", + "p_state_clk_gate_min": 1000, + "eventq_index": 0, + "p_state_clk_gate_bins": 20, + "default_p_state": "UNDEFINED", + "clk_domain": "system.cpu_clk_domain", + "power_model": null, + "sequential_access": false, + "assoc": 2, + "cxx_class": "LRU", + "p_state_clk_gate_max": 1000000000000, + "path": "system.cpu.dcache.tags", + "block_size": 64, + "type": "LRU", + "data_latency": 2 + }, + "tgts_per_mshr": 20, + "demand_mshr_reserve": 1, + "power_model": null, + "addr_ranges": [ + "0:18446744073709551615:0:0:0:0" + ], + "is_read_only": false, + "prefetch_on_access": false, + "path": "system.cpu.dcache", + "data_latency": 2, + "tag_latency": 2, + "name": "dcache", + "p_state_clk_gate_bins": 20, + "sequential_access": false, + "assoc": 2 + }, + "path": "system.cpu", + "fetch1ToFetch2ForwardDelay": 1, + "decodeInputBufferSize": 3 + } + ], + "multi_thread": false, + "exit_on_work_items": false, + "work_item_id": -1, + "num_work_ids": 16 + }, + "time_sync_period": 100000000000, + "eventq_index": 0, + "time_sync_spin_threshold": 100000000, + "cxx_class": "Root", + "path": "root", + "time_sync_enable": false, + "type": "Root", + "full_system": false +}
\ No newline at end of file diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/minor-timing/simerr b/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/minor-timing/simerr new file mode 100755 index 000000000..85a6a33ad --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/minor-timing/simerr @@ -0,0 +1,4 @@ +warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes) +warn: Unknown operating system; assuming Linux. +warn: Sockets disabled, not accepting gdb connections +warn: ClockedObject: More than one power state change request encountered within the same simulation tick diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/minor-timing/simout b/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/minor-timing/simout new file mode 100755 index 000000000..fa339d512 --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/minor-timing/simout @@ -0,0 +1,168 @@ +Redirecting stdout to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64d/minor-timing/simout +Redirecting stderr to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64d/minor-timing/simerr +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled Nov 30 2016 14:33:35 +gem5 started Nov 30 2016 16:18:31 +gem5 executing on zizzer, pid 34070 +command line: /z/powerjg/gem5-upstream/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64d/minor-timing -re /z/powerjg/gem5-upstream/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64d/minor-timing + +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. +fld: PASS +fsd: PASS +fmadd.d: PASS +fmadd.d, quiet NaN: PASS +fmadd.d, signaling NaN: PASS +fmadd.d, infinity: PASS +fmadd.d, -infinity: PASS +fmsub.d: PASS +fmsub.d, quiet NaN: PASS +fmsub.d, signaling NaN: PASS +fmsub.d, infinity: PASS +fmsub.d, -infinity: PASS +fmsub.d, subtract infinity: PASS +fnmsub.d: PASS +fnmsub.d, quiet NaN: PASS +fnmsub.d, signaling NaN: PASS +fnmsub.d, infinity: PASS +fnmsub.d, -infinity: PASS +fnmsub.d, subtract infinity: PASS +fnmadd.d: PASS +fnmadd.d, quiet NaN: PASS +fnmadd.d, signaling NaN: PASS +fnmadd.d, infinity: PASS +fnmadd.d, -infinity: PASS +fadd.d: PASS +fadd.d, quiet NaN: PASS +fadd.d, signaling NaN: PASS +fadd.d, infinity: PASS +fadd.d, -infinity: PASS +fsub.d: PASS +fsub.d, quiet NaN: PASS +fsub.d, signaling NaN: PASS +fsub.d, infinity: PASS +fsub.d, -infinity: PASS +fsub.d, subtract infinity: PASS +fmul.d: PASS +fmul.d, quiet NaN: PASS +fmul.d, signaling NaN: PASS +fmul.d, infinity: PASS +fmul.d, -infinity: PASS +fmul.d, 0*infinity: PASS +fmul.d, overflow: PASS +fmul.d, underflow: PASS +fdiv.d: PASS +fdiv.d, quiet NaN: PASS +fdiv.d, signaling NaN: PASS +fdiv.d/0: PASS +fdiv.d/infinity: PASS +fdiv.d, infinity/infinity: PASS +fdiv.d, 0/0: PASS +fdiv.d, infinity/0: PASS +fdiv.d, 0/infinity: PASS +fdiv.d, underflow: PASS +fdiv.d, overflow: PASS +fsqrt.d: PASS +fsqrt.d, NaN: PASS +fsqrt.d, quiet NaN: PASS +fsqrt.d, signaling NaN: PASS +fsqrt.d, infinity: PASS +fsgnj.d, ++: PASS +fsgnj.d, +-: PASS +fsgnj.d, -+: PASS +fsgnj.d, --: PASS +fsgnj.d, quiet NaN: PASS +fsgnj.d, signaling NaN: PASS +fsgnj.d, inject NaN: PASS +fsgnj.d, inject -NaN: PASS +fsgnjn.d, ++: PASS +fsgnjn.d, +-: PASS +fsgnjn.d, -+: PASS +fsgnjn.d, --: PASS +fsgnjn.d, quiet NaN: PASS +fsgnjn.d, signaling NaN: PASS +fsgnjn.d, inject NaN: PASS +fsgnjn.d, inject NaN: PASS +fsgnjx.d, ++: PASS +fsgnjx.d, +-: PASS +fsgnjx.d, -+: PASS +fsgnjx.d, --: PASS +fsgnjx.d, quiet NaN: PASS +fsgnjx.d, signaling NaN: PASS +fsgnjx.d, inject NaN: PASS +fsgnjx.d, inject NaN: PASS +fmin.d: PASS +fmin.d, -infinity: PASS +fmin.d, infinity: PASS +fmin.d, quiet NaN first: PASS +fmin.d, quiet NaN second: PASS +fmin.d, quiet NaN both: PASS +fmin.d, signaling NaN first: PASS +fmin.d, signaling NaN second: PASS +fmin.d, signaling NaN both: PASS +fmax.d: PASS +fmax.d, -infinity: PASS +fmax.d, infinity: PASS +fmax.d, quiet NaN first: PASS +fmax.d, quiet NaN second: PASS +fmax.d, quiet NaN both: PASS +fmax.d, signaling NaN first: PASS +fmax.d, signaling NaN second: PASS +fmax.d, signaling NaN both: PASS +fcvt.s.d: PASS +fcvt.s.d, quiet NaN: PASS +fcvt.s.d, signaling NaN: PASS +fcvt.s.d, infinity: PASS +fcvt.s.d, overflow: PASS +fcvt.s.d, underflow: PASS +fcvt.d.s: PASS +fcvt.d.s, quiet NaN: PASS +fcvt.d.s, signaling NaN: PASS +fcvt.d.s, infinity: PASS +feq.d, equal: PASS +feq.d, not equal: PASS +feq.d, 0 == -0: PASS +feq.d, quiet NaN first: PASS +feq.d, quiet NaN second: PASS +feq.d, quiet NaN both: PASS +feq.d, signaling NaN first: PASS +feq.d, signaling NaN second: PASS +feq.d, signaling NaN both: PASS +flt.d, equal: PASS +flt.d, less: PASS +flt.d, greater: PASS +flt.d, quiet NaN first: PASS +flt.d, quiet NaN second: PASS +flt.d, quiet NaN both: PASS +flt.d, signaling NaN first: PASS +flt.d, signaling NaN second: PASS +flt.d, signaling NaN both: PASS +fle.d, equal: PASS +fle.d, less: PASS +fle.d, greater: PASS +fle.d, 0 == -0: PASS +fle.d, quiet NaN first: PASS +fle.d, quiet NaN second: PASS +fle.d, quiet NaN both: PASS +fle.d, signaling NaN first: PASS +fle.d, signaling NaN second: PASS +fle.d, signaling NaN both: PASS +fclass.d, -infinity: PASS +fclass.d, -normal: PASS +fclass.d, -subnormal: PASS +fclass.d, -0.0: PASS +fclass.d, 0.0: PASS +fclass.d, subnormal: PASS +fclass.d, normal: PASS +fclass.d, infinity: PASS +fclass.d, signaling NaN: PASS +fclass.s, quiet NaN: PASS +fcvt.w.d, truncate positive: PASS +fcvt.w.d, truncate negative: PASS +fcvt.w.d, 0.0: PASS +fcvt.w.d, -0.0: PASS +fcvt.w.d, overflow: [1;31mFAIL[0m (expected 2147483647; found -2147483648) +Exiting @ tick 339160000 because target called exit() diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/minor-timing/stats.txt b/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/minor-timing/stats.txt new file mode 100644 index 000000000..c2cf1b21c --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/minor-timing/stats.txt @@ -0,0 +1,763 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.000339 # Number of seconds simulated +sim_ticks 339160000 # Number of ticks simulated +final_tick 339160000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 25032 # Simulator instruction rate (inst/s) +host_op_rate 25032 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 28360795 # Simulator tick rate (ticks/s) +host_mem_usage 244952 # Number of bytes of host memory used +host_seconds 11.96 # Real time elapsed on the host +sim_insts 299354 # Number of instructions simulated +sim_ops 299354 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 339160000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 74688 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 20352 # Number of bytes read from this memory +system.physmem.bytes_read::total 95040 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 74688 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 74688 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 1167 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 318 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1485 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 220214648 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 60007076 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 280221724 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 220214648 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 220214648 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 220214648 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 60007076 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 280221724 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1485 # Number of read requests accepted +system.physmem.writeReqs 0 # Number of write requests accepted +system.physmem.readBursts 1485 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 95040 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue +system.physmem.bytesWritten 0 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 95040 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 175 # Per bank write bursts +system.physmem.perBankRdBursts::1 68 # Per bank write bursts +system.physmem.perBankRdBursts::2 18 # Per bank write bursts +system.physmem.perBankRdBursts::3 72 # Per bank write bursts +system.physmem.perBankRdBursts::4 169 # Per bank write bursts +system.physmem.perBankRdBursts::5 291 # Per bank write bursts +system.physmem.perBankRdBursts::6 95 # Per bank write bursts +system.physmem.perBankRdBursts::7 4 # Per bank write bursts +system.physmem.perBankRdBursts::8 9 # Per bank write bursts +system.physmem.perBankRdBursts::9 115 # Per bank write bursts +system.physmem.perBankRdBursts::10 155 # Per bank write bursts +system.physmem.perBankRdBursts::11 169 # Per bank write bursts +system.physmem.perBankRdBursts::12 48 # Per bank write bursts +system.physmem.perBankRdBursts::13 55 # Per bank write bursts +system.physmem.perBankRdBursts::14 15 # Per bank write bursts +system.physmem.perBankRdBursts::15 27 # Per bank write bursts +system.physmem.perBankWrBursts::0 0 # Per bank write bursts +system.physmem.perBankWrBursts::1 0 # Per bank write bursts +system.physmem.perBankWrBursts::2 0 # Per bank write bursts +system.physmem.perBankWrBursts::3 0 # Per bank write bursts +system.physmem.perBankWrBursts::4 0 # Per bank write bursts +system.physmem.perBankWrBursts::5 0 # Per bank write bursts +system.physmem.perBankWrBursts::6 0 # Per bank write bursts +system.physmem.perBankWrBursts::7 0 # Per bank write bursts +system.physmem.perBankWrBursts::8 0 # Per bank write bursts +system.physmem.perBankWrBursts::9 0 # Per bank write bursts +system.physmem.perBankWrBursts::10 0 # Per bank write bursts +system.physmem.perBankWrBursts::11 0 # Per bank write bursts +system.physmem.perBankWrBursts::12 0 # Per bank write bursts +system.physmem.perBankWrBursts::13 0 # Per bank write bursts +system.physmem.perBankWrBursts::14 0 # Per bank write bursts +system.physmem.perBankWrBursts::15 0 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 338943500 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 1485 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 0 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1419 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 63 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 285 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 327.859649 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 221.469651 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 283.652997 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 67 23.51% 23.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 73 25.61% 49.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 39 13.68% 62.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 33 11.58% 74.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 28 9.82% 84.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 15 5.26% 89.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 7 2.46% 91.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 2 0.70% 92.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 21 7.37% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 285 # Bytes accessed per row activation +system.physmem.totQLat 19805250 # Total ticks spent queuing +system.physmem.totMemAccLat 47649000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 7425000 # Total ticks spent in databus transfers +system.physmem.avgQLat 13336.87 # Average queueing delay per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 32086.87 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 280.22 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 280.22 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.busUtil 2.19 # Data bus utilization in percentage +system.physmem.busUtilRead 2.19 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing +system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing +system.physmem.readRowHits 1195 # Number of row buffer hits during reads +system.physmem.writeRowHits 0 # Number of row buffer hits during writes +system.physmem.readRowHitRate 80.47 # Row buffer hit rate for reads +system.physmem.writeRowHitRate nan # Row buffer hit rate for writes +system.physmem.avgGap 228244.78 # Average gap between requests +system.physmem.pageHitRate 80.47 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 1106700 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 576840 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 6368880 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 27044160.000000 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 16006740 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 700320 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 122840700 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 12504960 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 619740.000000 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 187769040 # Total energy per rank (pJ) +system.physmem_0.averagePower 553.629673 # Core power per rank (mW) +system.physmem_0.totalIdleTime 301401000 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 546000 # Time in different power states +system.physmem_0.memoryStateTime::REF 11446000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 280750 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 32576500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 24926250 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 269384500 # Time in different power states +system.physmem_1.actEnergy 963900 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 504735 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 4234020 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 27044160.000000 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 12901950 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 3644640 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 106370550 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 25587360 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 905640.000000 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 182156955 # Total energy per rank (pJ) +system.physmem_1.averagePower 537.082660 # Core power per rank (mW) +system.physmem_1.totalIdleTime 301148500 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 8278250 # Time in different power states +system.physmem_1.memoryStateTime::REF 11446000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 1471750 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 66617000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 18107500 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 233239500 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 339160000 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 80709 # Number of BP lookups +system.cpu.branchPred.condPredicted 51944 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 5835 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 64346 # Number of BTB lookups +system.cpu.branchPred.BTBHits 38294 # Number of BTB hits +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 59.512635 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 0 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 13164 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 7506 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 5658 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 3210 # Number of mispredicted indirect branches. +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 162 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 339160000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 678320 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 299354 # Number of instructions committed +system.cpu.committedOps 299354 # Number of ops (including micro ops) committed +system.cpu.discardedOps 13959 # Number of ops (including micro ops) which were discarded before commit +system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching +system.cpu.cpi 2.265946 # CPI: cycles per instruction +system.cpu.ipc 0.441317 # IPC: instructions per cycle +system.cpu.op_class_0::No_OpClass 162 0.05% 0.05% # Class of committed instruction +system.cpu.op_class_0::IntAlu 179913 60.10% 60.15% # Class of committed instruction +system.cpu.op_class_0::IntMult 466 0.16% 60.31% # Class of committed instruction +system.cpu.op_class_0::IntDiv 40 0.01% 60.32% # Class of committed instruction +system.cpu.op_class_0::FloatAdd 120 0.04% 60.36% # Class of committed instruction +system.cpu.op_class_0::FloatCmp 157 0.05% 60.42% # Class of committed instruction +system.cpu.op_class_0::FloatCvt 60 0.02% 60.44% # Class of committed instruction +system.cpu.op_class_0::FloatMult 30 0.01% 60.45% # Class of committed instruction +system.cpu.op_class_0::FloatMultAcc 0 0.00% 60.45% # Class of committed instruction +system.cpu.op_class_0::FloatDiv 11 0.00% 60.45% # Class of committed instruction +system.cpu.op_class_0::FloatMisc 0 0.00% 60.45% # Class of committed instruction +system.cpu.op_class_0::FloatSqrt 5 0.00% 60.45% # Class of committed instruction +system.cpu.op_class_0::SimdAdd 0 0.00% 60.45% # Class of committed instruction +system.cpu.op_class_0::SimdAddAcc 0 0.00% 60.45% # Class of committed instruction +system.cpu.op_class_0::SimdAlu 0 0.00% 60.45% # Class of committed instruction +system.cpu.op_class_0::SimdCmp 0 0.00% 60.45% # Class of committed instruction +system.cpu.op_class_0::SimdCvt 0 0.00% 60.45% # Class of committed instruction +system.cpu.op_class_0::SimdMisc 0 0.00% 60.45% # Class of committed instruction +system.cpu.op_class_0::SimdMult 0 0.00% 60.45% # Class of committed instruction +system.cpu.op_class_0::SimdMultAcc 0 0.00% 60.45% # Class of committed instruction +system.cpu.op_class_0::SimdShift 0 0.00% 60.45% # Class of committed instruction +system.cpu.op_class_0::SimdShiftAcc 0 0.00% 60.45% # Class of committed instruction +system.cpu.op_class_0::SimdSqrt 0 0.00% 60.45% # Class of committed instruction +system.cpu.op_class_0::SimdFloatAdd 0 0.00% 60.45% # Class of committed instruction +system.cpu.op_class_0::SimdFloatAlu 0 0.00% 60.45% # Class of committed instruction +system.cpu.op_class_0::SimdFloatCmp 0 0.00% 60.45% # Class of committed instruction +system.cpu.op_class_0::SimdFloatCvt 0 0.00% 60.45% # Class of committed instruction +system.cpu.op_class_0::SimdFloatDiv 0 0.00% 60.45% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMisc 0 0.00% 60.45% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMult 0 0.00% 60.45% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 60.45% # Class of committed instruction +system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 60.45% # Class of committed instruction +system.cpu.op_class_0::MemRead 69348 23.17% 83.62% # Class of committed instruction +system.cpu.op_class_0::MemWrite 48400 16.17% 99.79% # Class of committed instruction +system.cpu.op_class_0::FloatMemRead 495 0.17% 99.95% # Class of committed instruction +system.cpu.op_class_0::FloatMemWrite 147 0.05% 100.00% # Class of committed instruction +system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.op_class_0::total 299354 # Class of committed instruction +system.cpu.tickCycles 449536 # Number of cycles that the object actually ticked +system.cpu.idleCycles 228784 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 339160000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 0 # number of replacements +system.cpu.dcache.tags.tagsinuse 254.196505 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 119907 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 320 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 374.709375 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 254.196505 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.062060 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.062060 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 320 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 6 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 26 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 288 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.078125 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 241156 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 241156 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 339160000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 71754 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 71754 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 48153 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 48153 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 119907 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 119907 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 119907 # number of overall hits +system.cpu.dcache.overall_hits::total 119907 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 118 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 118 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 393 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 393 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 511 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 511 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 511 # number of overall misses +system.cpu.dcache.overall_misses::total 511 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 10963000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 10963000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 31520500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 31520500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 42483500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 42483500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 42483500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 42483500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 71872 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 71872 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 48546 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 48546 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 120418 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 120418 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 120418 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 120418 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.001642 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.001642 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.008095 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.008095 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.004244 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.004244 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.004244 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.004244 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 92906.779661 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 92906.779661 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 80204.834606 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 80204.834606 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 83137.964775 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 83137.964775 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 83137.964775 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 83137.964775 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 191 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 191 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 191 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 191 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 191 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 191 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 118 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 118 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 202 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 202 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 320 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 320 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 320 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 320 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10845000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 10845000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 16122000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 16122000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26967000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 26967000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26967000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 26967000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001642 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001642 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.004161 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.004161 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002657 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.002657 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002657 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.002657 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 91906.779661 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 91906.779661 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79811.881188 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79811.881188 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 84271.875000 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 84271.875000 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 84271.875000 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 84271.875000 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 339160000 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 80 # number of replacements +system.cpu.icache.tags.tagsinuse 640.869470 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 135081 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1178 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 114.669779 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 640.869470 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.312925 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.312925 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1098 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 70 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 182 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 846 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.536133 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 273696 # Number of tag accesses +system.cpu.icache.tags.data_accesses 273696 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 339160000 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 135081 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 135081 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 135081 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 135081 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 135081 # number of overall hits +system.cpu.icache.overall_hits::total 135081 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1178 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1178 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1178 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1178 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1178 # number of overall misses +system.cpu.icache.overall_misses::total 1178 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 99945500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 99945500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 99945500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 99945500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 99945500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 99945500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 136259 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 136259 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 136259 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 136259 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 136259 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 136259 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.008645 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.008645 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.008645 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.008645 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.008645 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.008645 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 84843.378608 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 84843.378608 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 84843.378608 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 84843.378608 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 84843.378608 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 84843.378608 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.icache.writebacks::writebacks 80 # number of writebacks +system.cpu.icache.writebacks::total 80 # number of writebacks +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1178 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1178 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1178 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1178 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1178 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1178 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 98767500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 98767500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 98767500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 98767500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 98767500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 98767500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.008645 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.008645 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.008645 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.008645 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.008645 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.008645 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 83843.378608 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 83843.378608 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 83843.378608 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 83843.378608 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 83843.378608 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 83843.378608 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 339160000 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.replacements 0 # number of replacements +system.cpu.l2cache.tags.tagsinuse 923.863116 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 93 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 1485 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.062626 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::cpu.inst 671.109849 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 252.753267 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.020481 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.007713 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.028194 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 1485 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 76 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 208 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1201 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.045319 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 14109 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 14109 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 339160000 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.WritebackClean_hits::writebacks 80 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 80 # number of WritebackClean hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 11 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 11 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 2 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 2 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.inst 11 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 2 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 13 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 11 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 2 # number of overall hits +system.cpu.l2cache.overall_hits::total 13 # number of overall hits +system.cpu.l2cache.ReadExReq_misses::cpu.data 202 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 202 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 1167 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 1167 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 116 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 116 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.inst 1167 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 318 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 1485 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 1167 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 318 # number of overall misses +system.cpu.l2cache.overall_misses::total 1485 # number of overall misses +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 15818500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 15818500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 96885000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 96885000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 10642000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 10642000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 96885000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 26460500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 123345500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 96885000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 26460500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 123345500 # number of overall miss cycles +system.cpu.l2cache.WritebackClean_accesses::writebacks 80 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 80 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 202 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 202 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1178 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 1178 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 118 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 118 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 1178 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 320 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 1498 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 1178 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 320 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 1498 # number of overall (read+write) accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.990662 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.990662 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.983051 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.983051 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.990662 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.993750 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.991322 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.990662 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.993750 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.991322 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78309.405941 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 78309.405941 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 83020.565553 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 83020.565553 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 91741.379310 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 91741.379310 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 83020.565553 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 83209.119497 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 83060.942761 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 83020.565553 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 83209.119497 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 83060.942761 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 202 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 202 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 1167 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 1167 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 116 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 116 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 1167 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 318 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 1485 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 1167 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 318 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 1485 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 13798500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 13798500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 85215000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 85215000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 9482000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 9482000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 85215000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 23280500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 108495500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 85215000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 23280500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 108495500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.990662 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.990662 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.983051 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.983051 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.990662 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.993750 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.991322 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.990662 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.993750 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.991322 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68309.405941 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68309.405941 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 73020.565553 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 73020.565553 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 81741.379310 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 81741.379310 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 73020.565553 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73209.119497 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 73060.942761 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 73020.565553 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73209.119497 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 73060.942761 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 1578 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 82 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 339160000 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 1296 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 80 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 202 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 202 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 1178 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 118 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2436 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 640 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 3076 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 80512 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 20480 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 100992 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 1498 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.001335 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.036527 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 1496 99.87% 99.87% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 2 0.13% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 1498 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 869000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 1767000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.5 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 480000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) +system.membus.snoop_filter.tot_requests 1485 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 339160000 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 1283 # Transaction distribution +system.membus.trans_dist::ReadExReq 202 # Transaction distribution +system.membus.trans_dist::ReadExResp 202 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 1283 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 2970 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 2970 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 95040 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 95040 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoopTraffic 0 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 1485 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 1485 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 1485 # Request fanout histogram +system.membus.reqLayer0.occupancy 1720000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.5 # Layer utilization (%) +system.membus.respLayer1.occupancy 7877750 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 2.3 # Layer utilization (%) + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-atomic/config.ini b/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-atomic/config.ini new file mode 100644 index 000000000..287aed562 --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-atomic/config.ini @@ -0,0 +1,211 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain +boot_osflags=a +cache_line_size=64 +clk_domain=system.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +exit_on_work_items=false +init_param=0 +kernel= +kernel_addr_check=true +load_addr_mask=1099511627775 +load_offset=0 +mem_mode=atomic +mem_ranges= +memories=system.physmem +mmap_using_noreserve=false +multi_thread=false +num_work_ids=16 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +readfile= +symbolfile= +thermal_components= +thermal_model=Null +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=AtomicSimpleCPU +children=dtb interrupts isa itb tracer workload +branchPred=Null +checker=Null +clk_domain=system.cpu_clk_domain +cpu_id=0 +default_p_state=UNDEFINED +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +eventq_index=0 +fastmem=false +function_trace=false +function_trace_start=0 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +profile=0 +progress_interval=0 +simpoint_start_insts= +simulate_data_stalls=false +simulate_inst_stalls=false +socket_id=0 +switched_out=false +system=system +tracer=system.cpu.tracer +width=1 +workload=system.cpu.workload +dcache_port=system.membus.slave[2] +icache_port=system.membus.slave[1] + +[system.cpu.dtb] +type=RiscvTLB +eventq_index=0 +size=64 + +[system.cpu.interrupts] +type=RiscvInterrupts +eventq_index=0 + +[system.cpu.isa] +type=RiscvISA +eventq_index=0 + +[system.cpu.itb] +type=RiscvTLB +eventq_index=0 +size=64 + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=LiveProcess +cmd=insttest +cwd= +drivers= +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable=/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64d/insttest +gid=100 +input=cin +kvmInSE=false +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=0 +system=system +uid=100 +useArchPT=false + +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000000 + +[system.membus] +type=CoherentXBar +children=snoop_filter +clk_domain=system.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +forward_latency=4 +frontend_latency=3 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +point_of_coherency=true +power_model=Null +response_latency=2 +snoop_filter=system.membus.snoop_filter +snoop_response_latency=4 +system=system +use_default_range=false +width=16 +master=system.physmem.port +slave=system.system_port system.cpu.icache_port system.cpu.dcache_port + +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + +[system.physmem] +type=SimpleMemory +bandwidth=73.000000 +clk_domain=system.clk_domain +conf_table_reported=true +default_p_state=UNDEFINED +eventq_index=0 +in_addr_map=true +kvm_map=true +latency=30000 +latency_var=0 +null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +range=0:134217727:0:0:0:0 +port=system.membus.master[0] + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-atomic/config.json b/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-atomic/config.json new file mode 100644 index 000000000..f654bdba2 --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-atomic/config.json @@ -0,0 +1,289 @@ +{ + "name": null, + "sim_quantum": 0, + "system": { + "kernel": "", + "mmap_using_noreserve": false, + "kernel_addr_check": true, + "membus": { + "point_of_coherency": true, + "system": "system", + "response_latency": 2, + "cxx_class": "CoherentXBar", + "forward_latency": 4, + "clk_domain": "system.clk_domain", + "width": 16, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "master": { + "peer": [ + "system.physmem.port" + ], + "role": "MASTER" + }, + "type": "CoherentXBar", + "frontend_latency": 3, + "slave": { + "peer": [ + "system.system_port", + "system.cpu.icache_port", + "system.cpu.dcache_port" + ], + "role": "SLAVE" + }, + "p_state_clk_gate_min": 1000, + "snoop_filter": { + "name": "snoop_filter", + "system": "system", + "max_capacity": 8388608, + "eventq_index": 0, + "cxx_class": "SnoopFilter", + "path": "system.membus.snoop_filter", + "type": "SnoopFilter", + "lookup_latency": 1 + }, + "power_model": null, + "path": "system.membus", + "snoop_response_latency": 4, + "name": "membus", + "p_state_clk_gate_bins": 20, + "use_default_range": false + }, + "symbolfile": "", + "readfile": "", + "thermal_model": null, + "cxx_class": "System", + "work_begin_cpu_id_exit": -1, + "load_offset": 0, + "work_begin_exit_count": 0, + "p_state_clk_gate_min": 1000, + "memories": [ + "system.physmem" + ], + "work_begin_ckpt_count": 0, + "clk_domain": { + "name": "clk_domain", + "clock": [ + 1000 + ], + "init_perf_level": 0, + "voltage_domain": "system.voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "mem_ranges": [], + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "dvfs_handler": { + "enable": false, + "name": "dvfs_handler", + "sys_clk_domain": "system.clk_domain", + "transition_latency": 100000000, + "eventq_index": 0, + "cxx_class": "DVFSHandler", + "domains": [], + "path": "system.dvfs_handler", + "type": "DVFSHandler" + }, + "work_end_exit_count": 0, + "type": "System", + "voltage_domain": { + "name": "voltage_domain", + "eventq_index": 0, + "voltage": [ + "1.0" + ], + "cxx_class": "VoltageDomain", + "path": "system.voltage_domain", + "type": "VoltageDomain" + }, + "cache_line_size": 64, + "boot_osflags": "a", + "system_port": { + "peer": "system.membus.slave[0]", + "role": "MASTER" + }, + "physmem": { + "range": "0:134217727:0:0:0:0", + "latency": 30000, + "name": "physmem", + "p_state_clk_gate_min": 1000, + "eventq_index": 0, + "p_state_clk_gate_bins": 20, + "default_p_state": "UNDEFINED", + "kvm_map": true, + "clk_domain": "system.clk_domain", + "power_model": null, + "latency_var": 0, + "bandwidth": "73.000000", + "conf_table_reported": true, + "cxx_class": "SimpleMemory", + "p_state_clk_gate_max": 1000000000000, + "path": "system.physmem", + "null": false, + "type": "SimpleMemory", + "port": { + "peer": "system.membus.master[0]", + "role": "SLAVE" + }, + "in_addr_map": true + }, + "power_model": null, + "work_cpus_ckpt_count": 0, + "thermal_components": [], + "path": "system", + "cpu_clk_domain": { + "name": "cpu_clk_domain", + "clock": [ + 500 + ], + "init_perf_level": 0, + "voltage_domain": "system.voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.cpu_clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "work_end_ckpt_count": 0, + "mem_mode": "atomic", + "name": "system", + "init_param": 0, + "p_state_clk_gate_bins": 20, + "load_addr_mask": 1099511627775, + "cpu": [ + { + "do_statistics_insts": true, + "numThreads": 1, + "itb": { + "name": "itb", + "eventq_index": 0, + "cxx_class": "RiscvISA::TLB", + "path": "system.cpu.itb", + "type": "RiscvTLB", + "size": 64 + }, + "simulate_data_stalls": false, + "function_trace": false, + "do_checkpoint_insts": true, + "cxx_class": "AtomicSimpleCPU", + "max_loads_all_threads": 0, + "system": "system", + "clk_domain": "system.cpu_clk_domain", + "function_trace_start": 0, + "cpu_id": 0, + "width": 1, + "checker": null, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "do_quiesce": true, + "type": "AtomicSimpleCPU", + "fastmem": false, + "profile": 0, + "icache_port": { + "peer": "system.membus.slave[1]", + "role": "MASTER" + }, + "p_state_clk_gate_bins": 20, + "p_state_clk_gate_min": 1000, + "interrupts": [ + { + "eventq_index": 0, + "path": "system.cpu.interrupts", + "type": "RiscvInterrupts", + "name": "interrupts", + "cxx_class": "RiscvISA::Interrupts" + } + ], + "dcache_port": { + "peer": "system.membus.slave[2]", + "role": "MASTER" + }, + "socket_id": 0, + "power_model": null, + "max_insts_all_threads": 0, + "path": "system.cpu", + "max_loads_any_thread": 0, + "switched_out": false, + "workload": [ + { + "uid": 100, + "pid": 100, + "kvmInSE": false, + "cxx_class": "LiveProcess", + "executable": "/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64d/insttest", + "drivers": [], + "system": "system", + "gid": 100, + "eventq_index": 0, + "env": [], + "input": "cin", + "ppid": 99, + "type": "LiveProcess", + "cwd": "", + "simpoint": 0, + "euid": 100, + "path": "system.cpu.workload", + "max_stack_size": 67108864, + "name": "workload", + "cmd": [ + "insttest" + ], + "errout": "cerr", + "useArchPT": false, + "egid": 100, + "output": "cout" + } + ], + "name": "cpu", + "dtb": { + "name": "dtb", + "eventq_index": 0, + "cxx_class": "RiscvISA::TLB", + "path": "system.cpu.dtb", + "type": "RiscvTLB", + "size": 64 + }, + "simpoint_start_insts": [], + "max_insts_any_thread": 0, + "simulate_inst_stalls": false, + "progress_interval": 0, + "branchPred": null, + "isa": [ + { + "eventq_index": 0, + "path": "system.cpu.isa", + "type": "RiscvISA", + "name": "isa", + "cxx_class": "RiscvISA::ISA" + } + ], + "tracer": { + "eventq_index": 0, + "path": "system.cpu.tracer", + "type": "ExeTracer", + "name": "tracer", + "cxx_class": "Trace::ExeTracer" + } + } + ], + "multi_thread": false, + "exit_on_work_items": false, + "work_item_id": -1, + "num_work_ids": 16 + }, + "time_sync_period": 100000000000, + "eventq_index": 0, + "time_sync_spin_threshold": 100000000, + "cxx_class": "Root", + "path": "root", + "time_sync_enable": false, + "type": "Root", + "full_system": false +}
\ No newline at end of file diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-atomic/simerr b/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-atomic/simerr new file mode 100755 index 000000000..fd133b12b --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-atomic/simerr @@ -0,0 +1,3 @@ +warn: Unknown operating system; assuming Linux. +warn: Sockets disabled, not accepting gdb connections +warn: ClockedObject: More than one power state change request encountered within the same simulation tick diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-atomic/simout b/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-atomic/simout new file mode 100755 index 000000000..0379b0893 --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-atomic/simout @@ -0,0 +1,168 @@ +Redirecting stdout to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64d/simple-atomic/simout +Redirecting stderr to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64d/simple-atomic/simerr +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled Nov 30 2016 14:33:35 +gem5 started Nov 30 2016 16:18:31 +gem5 executing on zizzer, pid 34072 +command line: /z/powerjg/gem5-upstream/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64d/simple-atomic -re /z/powerjg/gem5-upstream/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64d/simple-atomic + +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. +fld: PASS +fsd: PASS +fmadd.d: PASS +fmadd.d, quiet NaN: PASS +fmadd.d, signaling NaN: PASS +fmadd.d, infinity: PASS +fmadd.d, -infinity: PASS +fmsub.d: PASS +fmsub.d, quiet NaN: PASS +fmsub.d, signaling NaN: PASS +fmsub.d, infinity: PASS +fmsub.d, -infinity: PASS +fmsub.d, subtract infinity: PASS +fnmsub.d: PASS +fnmsub.d, quiet NaN: PASS +fnmsub.d, signaling NaN: PASS +fnmsub.d, infinity: PASS +fnmsub.d, -infinity: PASS +fnmsub.d, subtract infinity: PASS +fnmadd.d: PASS +fnmadd.d, quiet NaN: PASS +fnmadd.d, signaling NaN: PASS +fnmadd.d, infinity: PASS +fnmadd.d, -infinity: PASS +fadd.d: PASS +fadd.d, quiet NaN: PASS +fadd.d, signaling NaN: PASS +fadd.d, infinity: PASS +fadd.d, -infinity: PASS +fsub.d: PASS +fsub.d, quiet NaN: PASS +fsub.d, signaling NaN: PASS +fsub.d, infinity: PASS +fsub.d, -infinity: PASS +fsub.d, subtract infinity: PASS +fmul.d: PASS +fmul.d, quiet NaN: PASS +fmul.d, signaling NaN: PASS +fmul.d, infinity: PASS +fmul.d, -infinity: PASS +fmul.d, 0*infinity: PASS +fmul.d, overflow: PASS +fmul.d, underflow: PASS +fdiv.d: PASS +fdiv.d, quiet NaN: PASS +fdiv.d, signaling NaN: PASS +fdiv.d/0: PASS +fdiv.d/infinity: PASS +fdiv.d, infinity/infinity: PASS +fdiv.d, 0/0: PASS +fdiv.d, infinity/0: PASS +fdiv.d, 0/infinity: PASS +fdiv.d, underflow: PASS +fdiv.d, overflow: PASS +fsqrt.d: PASS +fsqrt.d, NaN: PASS +fsqrt.d, quiet NaN: PASS +fsqrt.d, signaling NaN: PASS +fsqrt.d, infinity: PASS +fsgnj.d, ++: PASS +fsgnj.d, +-: PASS +fsgnj.d, -+: PASS +fsgnj.d, --: PASS +fsgnj.d, quiet NaN: PASS +fsgnj.d, signaling NaN: PASS +fsgnj.d, inject NaN: PASS +fsgnj.d, inject -NaN: PASS +fsgnjn.d, ++: PASS +fsgnjn.d, +-: PASS +fsgnjn.d, -+: PASS +fsgnjn.d, --: PASS +fsgnjn.d, quiet NaN: PASS +fsgnjn.d, signaling NaN: PASS +fsgnjn.d, inject NaN: PASS +fsgnjn.d, inject NaN: PASS +fsgnjx.d, ++: PASS +fsgnjx.d, +-: PASS +fsgnjx.d, -+: PASS +fsgnjx.d, --: PASS +fsgnjx.d, quiet NaN: PASS +fsgnjx.d, signaling NaN: PASS +fsgnjx.d, inject NaN: PASS +fsgnjx.d, inject NaN: PASS +fmin.d: PASS +fmin.d, -infinity: PASS +fmin.d, infinity: PASS +fmin.d, quiet NaN first: PASS +fmin.d, quiet NaN second: PASS +fmin.d, quiet NaN both: PASS +fmin.d, signaling NaN first: PASS +fmin.d, signaling NaN second: PASS +fmin.d, signaling NaN both: PASS +fmax.d: PASS +fmax.d, -infinity: PASS +fmax.d, infinity: PASS +fmax.d, quiet NaN first: PASS +fmax.d, quiet NaN second: PASS +fmax.d, quiet NaN both: PASS +fmax.d, signaling NaN first: PASS +fmax.d, signaling NaN second: PASS +fmax.d, signaling NaN both: PASS +fcvt.s.d: PASS +fcvt.s.d, quiet NaN: PASS +fcvt.s.d, signaling NaN: PASS +fcvt.s.d, infinity: PASS +fcvt.s.d, overflow: PASS +fcvt.s.d, underflow: PASS +fcvt.d.s: PASS +fcvt.d.s, quiet NaN: PASS +fcvt.d.s, signaling NaN: PASS +fcvt.d.s, infinity: PASS +feq.d, equal: PASS +feq.d, not equal: PASS +feq.d, 0 == -0: PASS +feq.d, quiet NaN first: PASS +feq.d, quiet NaN second: PASS +feq.d, quiet NaN both: PASS +feq.d, signaling NaN first: PASS +feq.d, signaling NaN second: PASS +feq.d, signaling NaN both: PASS +flt.d, equal: PASS +flt.d, less: PASS +flt.d, greater: PASS +flt.d, quiet NaN first: PASS +flt.d, quiet NaN second: PASS +flt.d, quiet NaN both: PASS +flt.d, signaling NaN first: PASS +flt.d, signaling NaN second: PASS +flt.d, signaling NaN both: PASS +fle.d, equal: PASS +fle.d, less: PASS +fle.d, greater: PASS +fle.d, 0 == -0: PASS +fle.d, quiet NaN first: PASS +fle.d, quiet NaN second: PASS +fle.d, quiet NaN both: PASS +fle.d, signaling NaN first: PASS +fle.d, signaling NaN second: PASS +fle.d, signaling NaN both: PASS +fclass.d, -infinity: PASS +fclass.d, -normal: PASS +fclass.d, -subnormal: PASS +fclass.d, -0.0: PASS +fclass.d, 0.0: PASS +fclass.d, subnormal: PASS +fclass.d, normal: PASS +fclass.d, infinity: PASS +fclass.d, signaling NaN: PASS +fclass.s, quiet NaN: PASS +fcvt.w.d, truncate positive: PASS +fcvt.w.d, truncate negative: PASS +fcvt.w.d, 0.0: PASS +fcvt.w.d, -0.0: PASS +fcvt.w.d, overflow: [1;31mFAIL[0m (expected 2147483647; found -2147483648) +Exiting @ tick 149676500 because target called exit() diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-atomic/stats.txt b/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-atomic/stats.txt new file mode 100644 index 000000000..3ddd316d7 --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-atomic/stats.txt @@ -0,0 +1,153 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.000150 # Number of seconds simulated +sim_ticks 149676500 # Number of ticks simulated +final_tick 149676500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 28553 # Simulator instruction rate (inst/s) +host_op_rate 28553 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 14284274 # Simulator tick rate (ticks/s) +host_mem_usage 234416 # Number of bytes of host memory used +host_seconds 10.48 # Real time elapsed on the host +sim_insts 299191 # Number of instructions simulated +sim_ops 299191 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 149676500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 1197416 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 459717 # Number of bytes read from this memory +system.physmem.bytes_read::total 1657133 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1197416 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1197416 # Number of instructions bytes read from this memory +system.physmem.bytes_written::cpu.data 301409 # Number of bytes written to this memory +system.physmem.bytes_written::total 301409 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 299354 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 69843 # Number of read requests responded to by this memory +system.physmem.num_reads::total 369197 # Number of read requests responded to by this memory +system.physmem.num_writes::cpu.data 48546 # Number of write requests responded to by this memory +system.physmem.num_writes::total 48546 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 8000026724 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3071403995 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 11071430719 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 8000026724 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 8000026724 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 2013736291 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2013736291 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 8000026724 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 5085140286 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 13085167010 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 149676500 # Cumulative time (in ticks) in various power states +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 162 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 149676500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 299354 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 299191 # Number of instructions committed +system.cpu.committedOps 299191 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 299008 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 1025 # Number of float alu accesses +system.cpu.num_func_calls 21816 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 44561 # number of instructions that are conditional controls +system.cpu.num_int_insts 299008 # number of integer instructions +system.cpu.num_fp_insts 1025 # number of float instructions +system.cpu.num_int_register_reads 394163 # number of times the integer registers were read +system.cpu.num_int_register_writes 205779 # number of times the integer registers were written +system.cpu.num_fp_register_reads 851 # number of times the floating registers were read +system.cpu.num_fp_register_writes 688 # number of times the floating registers were written +system.cpu.num_mem_refs 118390 # number of memory refs +system.cpu.num_load_insts 69843 # Number of load instructions +system.cpu.num_store_insts 48547 # Number of store instructions +system.cpu.num_idle_cycles 0 # Number of idle cycles +system.cpu.num_busy_cycles 299354 # Number of busy cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.Branches 66377 # Number of branches fetched +system.cpu.op_class::No_OpClass 162 0.05% 0.05% # Class of executed instruction +system.cpu.op_class::IntAlu 179913 60.10% 60.15% # Class of executed instruction +system.cpu.op_class::IntMult 466 0.16% 60.31% # Class of executed instruction +system.cpu.op_class::IntDiv 40 0.01% 60.32% # Class of executed instruction +system.cpu.op_class::FloatAdd 120 0.04% 60.36% # Class of executed instruction +system.cpu.op_class::FloatCmp 157 0.05% 60.42% # Class of executed instruction +system.cpu.op_class::FloatCvt 60 0.02% 60.44% # Class of executed instruction +system.cpu.op_class::FloatMult 30 0.01% 60.45% # Class of executed instruction +system.cpu.op_class::FloatMultAcc 0 0.00% 60.45% # Class of executed instruction +system.cpu.op_class::FloatDiv 11 0.00% 60.45% # Class of executed instruction +system.cpu.op_class::FloatMisc 0 0.00% 60.45% # Class of executed instruction +system.cpu.op_class::FloatSqrt 5 0.00% 60.45% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 60.45% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 60.45% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 60.45% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 60.45% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 60.45% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 60.45% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 60.45% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 60.45% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 60.45% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 60.45% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 60.45% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 60.45% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 60.45% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 60.45% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 60.45% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 60.45% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 60.45% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 60.45% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 60.45% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 60.45% # Class of executed instruction +system.cpu.op_class::MemRead 69348 23.17% 83.62% # Class of executed instruction +system.cpu.op_class::MemWrite 48400 16.17% 99.79% # Class of executed instruction +system.cpu.op_class::FloatMemRead 495 0.17% 99.95% # Class of executed instruction +system.cpu.op_class::FloatMemWrite 147 0.05% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 299354 # Class of executed instruction +system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 149676500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadReq 369197 # Transaction distribution +system.membus.trans_dist::ReadResp 369197 # Transaction distribution +system.membus.trans_dist::WriteReq 48546 # Transaction distribution +system.membus.trans_dist::WriteResp 48546 # Transaction distribution +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 598708 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 236778 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 835486 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 1197416 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 761126 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 1958542 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoopTraffic 0 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 417743 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 417743 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 417743 # Request fanout histogram + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-timing-ruby/config.ini b/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-timing-ruby/config.ini new file mode 100644 index 000000000..0a11055d6 --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-timing-ruby/config.ini @@ -0,0 +1,1265 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000 +time_sync_spin_threshold=100000 + +[system] +type=System +children=clk_domain cpu dvfs_handler mem_ctrls ruby sys_port_proxy voltage_domain +boot_osflags=a +cache_line_size=64 +clk_domain=system.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +exit_on_work_items=false +init_param=0 +kernel= +kernel_addr_check=true +load_addr_mask=1099511627775 +load_offset=0 +mem_mode=timing +mem_ranges=0:268435455:0:0:0:0 +memories=system.mem_ctrls +mmap_using_noreserve=false +multi_thread=false +num_work_ids=16 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null +readfile= +symbolfile= +thermal_components= +thermal_model=Null +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.sys_port_proxy.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=TimingSimpleCPU +children=clk_domain dtb interrupts isa itb tracer workload +branchPred=Null +checker=Null +clk_domain=system.cpu.clk_domain +cpu_id=0 +default_p_state=UNDEFINED +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +eventq_index=0 +function_trace=false +function_trace_start=0 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null +profile=0 +progress_interval=0 +simpoint_start_insts= +socket_id=0 +switched_out=false +system=system +tracer=system.cpu.tracer +workload=system.cpu.workload +dcache_port=system.ruby.l1_cntrl0.sequencer.slave[1] +icache_port=system.ruby.l1_cntrl0.sequencer.slave[0] + +[system.cpu.clk_domain] +type=SrcClockDomain +clock=1 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu.dtb] +type=RiscvTLB +eventq_index=0 +size=64 + +[system.cpu.interrupts] +type=RiscvInterrupts +eventq_index=0 + +[system.cpu.isa] +type=RiscvISA +eventq_index=0 + +[system.cpu.itb] +type=RiscvTLB +eventq_index=0 +size=64 + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=LiveProcess +cmd=insttest +cwd= +drivers= +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable=/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64d/insttest +gid=100 +input=cin +kvmInSE=false +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=0 +system=system +uid=100 +useArchPT=false + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000 + +[system.mem_ctrls] +type=DRAMCtrl +IDD0=0.055000 +IDD02=0.000000 +IDD2N=0.032000 +IDD2N2=0.000000 +IDD2P0=0.000000 +IDD2P02=0.000000 +IDD2P1=0.032000 +IDD2P12=0.000000 +IDD3N=0.038000 +IDD3N2=0.000000 +IDD3P0=0.000000 +IDD3P02=0.000000 +IDD3P1=0.038000 +IDD3P12=0.000000 +IDD4R=0.157000 +IDD4R2=0.000000 +IDD4W=0.125000 +IDD4W2=0.000000 +IDD5=0.235000 +IDD52=0.000000 +IDD6=0.020000 +IDD62=0.000000 +VDD=1.500000 +VDD2=0.000000 +activation_limit=4 +addr_mapping=RoRaBaCoCh +bank_groups_per_rank=0 +banks_per_rank=8 +burst_length=8 +channels=1 +clk_domain=system.clk_domain +conf_table_reported=true +default_p_state=UNDEFINED +device_bus_width=8 +device_rowbuffer_size=1024 +device_size=536870912 +devices_per_rank=8 +dll=true +eventq_index=0 +in_addr_map=true +kvm_map=true +max_accesses_per_row=16 +mem_sched_policy=frfcfs +min_writes_per_switch=16 +null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +page_policy=open_adaptive +power_model=Null +range=0:268435455:5:19:0:0 +ranks_per_channel=2 +read_buffer_size=32 +static_backend_latency=10 +static_frontend_latency=10 +tBURST=5 +tCCD_L=0 +tCK=1 +tCL=14 +tCS=3 +tRAS=35 +tRCD=14 +tREFI=7800 +tRFC=260 +tRP=14 +tRRD=6 +tRRD_L=0 +tRTP=8 +tRTW=3 +tWR=15 +tWTR=8 +tXAW=30 +tXP=6 +tXPDLL=0 +tXS=270 +tXSDLL=0 +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 +port=system.ruby.dir_cntrl0.memory + +[system.ruby] +type=RubySystem +children=clk_domain dir_cntrl0 l1_cntrl0 memctrl_clk_domain network +access_backing_store=false +all_instructions=false +block_size_bytes=64 +clk_domain=system.ruby.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +hot_lines=false +memory_size_bits=48 +num_of_sequencers=1 +number_of_virtual_networks=5 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +phys_mem=Null +power_model=Null +randomization=false + +[system.ruby.clk_domain] +type=SrcClockDomain +clock=1 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.ruby.dir_cntrl0] +type=Directory_Controller +children=directory dmaRequestToDir dmaResponseFromDir forwardFromDir requestToDir responseFromDir responseFromMemory +buffer_size=0 +clk_domain=system.ruby.clk_domain +cluster_id=0 +default_p_state=UNDEFINED +directory=system.ruby.dir_cntrl0.directory +directory_latency=12 +dmaRequestToDir=system.ruby.dir_cntrl0.dmaRequestToDir +dmaResponseFromDir=system.ruby.dir_cntrl0.dmaResponseFromDir +eventq_index=0 +forwardFromDir=system.ruby.dir_cntrl0.forwardFromDir +number_of_TBEs=256 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null +recycle_latency=10 +requestToDir=system.ruby.dir_cntrl0.requestToDir +responseFromDir=system.ruby.dir_cntrl0.responseFromDir +responseFromMemory=system.ruby.dir_cntrl0.responseFromMemory +ruby_system=system.ruby +system=system +to_memory_controller_latency=1 +transitions_per_cycle=4 +version=0 +memory=system.mem_ctrls.port + +[system.ruby.dir_cntrl0.directory] +type=RubyDirectoryMemory +eventq_index=0 +numa_high_bit=5 +size=268435456 +version=0 + +[system.ruby.dir_cntrl0.dmaRequestToDir] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +slave=system.ruby.network.master[3] + +[system.ruby.dir_cntrl0.dmaResponseFromDir] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +master=system.ruby.network.slave[3] + +[system.ruby.dir_cntrl0.forwardFromDir] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=false +randomization=false +master=system.ruby.network.slave[4] + +[system.ruby.dir_cntrl0.requestToDir] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +slave=system.ruby.network.master[2] + +[system.ruby.dir_cntrl0.responseFromDir] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=false +randomization=false +master=system.ruby.network.slave[2] + +[system.ruby.dir_cntrl0.responseFromMemory] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=false +randomization=false + +[system.ruby.l1_cntrl0] +type=L1Cache_Controller +children=cacheMemory forwardToCache mandatoryQueue requestFromCache responseFromCache responseToCache sequencer +buffer_size=0 +cacheMemory=system.ruby.l1_cntrl0.cacheMemory +cache_response_latency=12 +clk_domain=system.cpu.clk_domain +cluster_id=0 +default_p_state=UNDEFINED +eventq_index=0 +forwardToCache=system.ruby.l1_cntrl0.forwardToCache +issue_latency=2 +mandatoryQueue=system.ruby.l1_cntrl0.mandatoryQueue +number_of_TBEs=256 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null +recycle_latency=10 +requestFromCache=system.ruby.l1_cntrl0.requestFromCache +responseFromCache=system.ruby.l1_cntrl0.responseFromCache +responseToCache=system.ruby.l1_cntrl0.responseToCache +ruby_system=system.ruby +send_evictions=false +sequencer=system.ruby.l1_cntrl0.sequencer +system=system +transitions_per_cycle=4 +version=0 + +[system.ruby.l1_cntrl0.cacheMemory] +type=RubyCache +children=replacement_policy +assoc=2 +block_size=0 +dataAccessLatency=1 +dataArrayBanks=1 +eventq_index=0 +is_icache=false +replacement_policy=system.ruby.l1_cntrl0.cacheMemory.replacement_policy +resourceStalls=false +ruby_system=system.ruby +size=256 +start_index_bit=6 +tagAccessLatency=1 +tagArrayBanks=1 + +[system.ruby.l1_cntrl0.cacheMemory.replacement_policy] +type=PseudoLRUReplacementPolicy +assoc=2 +block_size=64 +eventq_index=0 +size=256 + +[system.ruby.l1_cntrl0.forwardToCache] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +slave=system.ruby.network.master[0] + +[system.ruby.l1_cntrl0.mandatoryQueue] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=false +randomization=false + +[system.ruby.l1_cntrl0.requestFromCache] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +master=system.ruby.network.slave[0] + +[system.ruby.l1_cntrl0.responseFromCache] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +master=system.ruby.network.slave[1] + +[system.ruby.l1_cntrl0.responseToCache] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +slave=system.ruby.network.master[1] + +[system.ruby.l1_cntrl0.sequencer] +type=RubySequencer +clk_domain=system.cpu.clk_domain +coreid=99 +dcache=system.ruby.l1_cntrl0.cacheMemory +dcache_hit_latency=1 +deadlock_threshold=500000 +default_p_state=UNDEFINED +eventq_index=0 +garnet_standalone=false +icache=system.ruby.l1_cntrl0.cacheMemory +icache_hit_latency=1 +is_cpu_sequencer=true +max_outstanding_requests=16 +no_retry_on_stall=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null +ruby_system=system.ruby +support_data_reqs=true +support_inst_reqs=true +system=system +using_ruby_tester=false +version=0 +slave=system.cpu.icache_port system.cpu.dcache_port + +[system.ruby.memctrl_clk_domain] +type=DerivedClockDomain +clk_divider=3 +clk_domain=system.ruby.clk_domain +eventq_index=0 + +[system.ruby.network] +type=SimpleNetwork +children=ext_links0 ext_links1 int_link_buffers00 int_link_buffers01 int_link_buffers02 int_link_buffers03 int_link_buffers04 int_link_buffers05 int_link_buffers06 int_link_buffers07 int_link_buffers08 int_link_buffers09 int_link_buffers10 int_link_buffers11 int_link_buffers12 int_link_buffers13 int_link_buffers14 int_link_buffers15 int_link_buffers16 int_link_buffers17 int_link_buffers18 int_link_buffers19 int_link_buffers20 int_link_buffers21 int_link_buffers22 int_link_buffers23 int_link_buffers24 int_link_buffers25 int_link_buffers26 int_link_buffers27 int_link_buffers28 int_link_buffers29 int_link_buffers30 int_link_buffers31 int_link_buffers32 int_link_buffers33 int_link_buffers34 int_link_buffers35 int_link_buffers36 int_link_buffers37 int_link_buffers38 int_link_buffers39 int_links0 int_links1 int_links2 int_links3 routers0 routers1 routers2 +adaptive_routing=false +buffer_size=0 +clk_domain=system.ruby.clk_domain +control_msg_size=8 +default_p_state=UNDEFINED +endpoint_bandwidth=1000 +eventq_index=0 +ext_links=system.ruby.network.ext_links0 system.ruby.network.ext_links1 +int_link_buffers=system.ruby.network.int_link_buffers00 system.ruby.network.int_link_buffers01 system.ruby.network.int_link_buffers02 system.ruby.network.int_link_buffers03 system.ruby.network.int_link_buffers04 system.ruby.network.int_link_buffers05 system.ruby.network.int_link_buffers06 system.ruby.network.int_link_buffers07 system.ruby.network.int_link_buffers08 system.ruby.network.int_link_buffers09 system.ruby.network.int_link_buffers10 system.ruby.network.int_link_buffers11 system.ruby.network.int_link_buffers12 system.ruby.network.int_link_buffers13 system.ruby.network.int_link_buffers14 system.ruby.network.int_link_buffers15 system.ruby.network.int_link_buffers16 system.ruby.network.int_link_buffers17 system.ruby.network.int_link_buffers18 system.ruby.network.int_link_buffers19 system.ruby.network.int_link_buffers20 system.ruby.network.int_link_buffers21 system.ruby.network.int_link_buffers22 system.ruby.network.int_link_buffers23 system.ruby.network.int_link_buffers24 system.ruby.network.int_link_buffers25 system.ruby.network.int_link_buffers26 system.ruby.network.int_link_buffers27 system.ruby.network.int_link_buffers28 system.ruby.network.int_link_buffers29 system.ruby.network.int_link_buffers30 system.ruby.network.int_link_buffers31 system.ruby.network.int_link_buffers32 system.ruby.network.int_link_buffers33 system.ruby.network.int_link_buffers34 system.ruby.network.int_link_buffers35 system.ruby.network.int_link_buffers36 system.ruby.network.int_link_buffers37 system.ruby.network.int_link_buffers38 system.ruby.network.int_link_buffers39 +int_links=system.ruby.network.int_links0 system.ruby.network.int_links1 system.ruby.network.int_links2 system.ruby.network.int_links3 +netifs= +number_of_virtual_networks=5 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null +routers=system.ruby.network.routers0 system.ruby.network.routers1 system.ruby.network.routers2 +ruby_system=system.ruby +topology=Crossbar +master=system.ruby.l1_cntrl0.forwardToCache.slave system.ruby.l1_cntrl0.responseToCache.slave system.ruby.dir_cntrl0.requestToDir.slave system.ruby.dir_cntrl0.dmaRequestToDir.slave +slave=system.ruby.l1_cntrl0.requestFromCache.master system.ruby.l1_cntrl0.responseFromCache.master system.ruby.dir_cntrl0.responseFromDir.master system.ruby.dir_cntrl0.dmaResponseFromDir.master system.ruby.dir_cntrl0.forwardFromDir.master + +[system.ruby.network.ext_links0] +type=SimpleExtLink +bandwidth_factor=16 +eventq_index=0 +ext_node=system.ruby.l1_cntrl0 +int_node=system.ruby.network.routers0 +latency=1 +link_id=0 +weight=1 + +[system.ruby.network.ext_links1] +type=SimpleExtLink +bandwidth_factor=16 +eventq_index=0 +ext_node=system.ruby.dir_cntrl0 +int_node=system.ruby.network.routers1 +latency=1 +link_id=1 +weight=1 + +[system.ruby.network.int_link_buffers00] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers01] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers02] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers03] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers04] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers05] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers06] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers07] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers08] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers09] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers10] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers11] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers12] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers13] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers14] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers15] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers16] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers17] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers18] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers19] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers20] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers21] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers22] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers23] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers24] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers25] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers26] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers27] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers28] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers29] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers30] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers31] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers32] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers33] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers34] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers35] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers36] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers37] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers38] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers39] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_links0] +type=SimpleIntLink +bandwidth_factor=16 +dst_inport= +dst_node=system.ruby.network.routers2 +eventq_index=0 +latency=1 +link_id=2 +src_node=system.ruby.network.routers0 +src_outport= +weight=1 + +[system.ruby.network.int_links1] +type=SimpleIntLink +bandwidth_factor=16 +dst_inport= +dst_node=system.ruby.network.routers2 +eventq_index=0 +latency=1 +link_id=3 +src_node=system.ruby.network.routers1 +src_outport= +weight=1 + +[system.ruby.network.int_links2] +type=SimpleIntLink +bandwidth_factor=16 +dst_inport= +dst_node=system.ruby.network.routers0 +eventq_index=0 +latency=1 +link_id=4 +src_node=system.ruby.network.routers2 +src_outport= +weight=1 + +[system.ruby.network.int_links3] +type=SimpleIntLink +bandwidth_factor=16 +dst_inport= +dst_node=system.ruby.network.routers1 +eventq_index=0 +latency=1 +link_id=5 +src_node=system.ruby.network.routers2 +src_outport= +weight=1 + +[system.ruby.network.routers0] +type=Switch +children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14 +clk_domain=system.ruby.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +port_buffers=system.ruby.network.routers0.port_buffers00 system.ruby.network.routers0.port_buffers01 system.ruby.network.routers0.port_buffers02 system.ruby.network.routers0.port_buffers03 system.ruby.network.routers0.port_buffers04 system.ruby.network.routers0.port_buffers05 system.ruby.network.routers0.port_buffers06 system.ruby.network.routers0.port_buffers07 system.ruby.network.routers0.port_buffers08 system.ruby.network.routers0.port_buffers09 system.ruby.network.routers0.port_buffers10 system.ruby.network.routers0.port_buffers11 system.ruby.network.routers0.port_buffers12 system.ruby.network.routers0.port_buffers13 system.ruby.network.routers0.port_buffers14 +power_model=Null +router_id=0 +virt_nets=5 + +[system.ruby.network.routers0.port_buffers00] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers0.port_buffers01] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers0.port_buffers02] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers0.port_buffers03] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers0.port_buffers04] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers0.port_buffers05] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers0.port_buffers06] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers0.port_buffers07] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers0.port_buffers08] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers0.port_buffers09] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers0.port_buffers10] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers0.port_buffers11] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers0.port_buffers12] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers0.port_buffers13] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers0.port_buffers14] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers1] +type=Switch +children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14 +clk_domain=system.ruby.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +port_buffers=system.ruby.network.routers1.port_buffers00 system.ruby.network.routers1.port_buffers01 system.ruby.network.routers1.port_buffers02 system.ruby.network.routers1.port_buffers03 system.ruby.network.routers1.port_buffers04 system.ruby.network.routers1.port_buffers05 system.ruby.network.routers1.port_buffers06 system.ruby.network.routers1.port_buffers07 system.ruby.network.routers1.port_buffers08 system.ruby.network.routers1.port_buffers09 system.ruby.network.routers1.port_buffers10 system.ruby.network.routers1.port_buffers11 system.ruby.network.routers1.port_buffers12 system.ruby.network.routers1.port_buffers13 system.ruby.network.routers1.port_buffers14 +power_model=Null +router_id=1 +virt_nets=5 + +[system.ruby.network.routers1.port_buffers00] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers1.port_buffers01] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers1.port_buffers02] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers1.port_buffers03] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers1.port_buffers04] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers1.port_buffers05] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers1.port_buffers06] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers1.port_buffers07] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers1.port_buffers08] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers1.port_buffers09] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers1.port_buffers10] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers1.port_buffers11] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers1.port_buffers12] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers1.port_buffers13] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers1.port_buffers14] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2] +type=Switch +children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14 port_buffers15 port_buffers16 port_buffers17 port_buffers18 port_buffers19 +clk_domain=system.ruby.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +port_buffers=system.ruby.network.routers2.port_buffers00 system.ruby.network.routers2.port_buffers01 system.ruby.network.routers2.port_buffers02 system.ruby.network.routers2.port_buffers03 system.ruby.network.routers2.port_buffers04 system.ruby.network.routers2.port_buffers05 system.ruby.network.routers2.port_buffers06 system.ruby.network.routers2.port_buffers07 system.ruby.network.routers2.port_buffers08 system.ruby.network.routers2.port_buffers09 system.ruby.network.routers2.port_buffers10 system.ruby.network.routers2.port_buffers11 system.ruby.network.routers2.port_buffers12 system.ruby.network.routers2.port_buffers13 system.ruby.network.routers2.port_buffers14 system.ruby.network.routers2.port_buffers15 system.ruby.network.routers2.port_buffers16 system.ruby.network.routers2.port_buffers17 system.ruby.network.routers2.port_buffers18 system.ruby.network.routers2.port_buffers19 +power_model=Null +router_id=2 +virt_nets=5 + +[system.ruby.network.routers2.port_buffers00] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers01] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers02] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers03] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers04] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers05] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers06] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers07] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers08] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers09] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers10] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers11] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers12] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers13] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers14] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers15] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers16] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers17] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers18] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers19] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.sys_port_proxy] +type=RubyPortProxy +clk_domain=system.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +is_cpu_sequencer=true +no_retry_on_stall=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null +ruby_system=system.ruby +support_data_reqs=true +support_inst_reqs=true +system=system +using_ruby_tester=false +version=0 +slave=system.system_port + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-timing-ruby/config.json b/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-timing-ruby/config.json new file mode 100644 index 000000000..e041cd07a --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-timing-ruby/config.json @@ -0,0 +1,1734 @@ +{ + "name": null, + "sim_quantum": 0, + "system": { + "kernel": "", + "mmap_using_noreserve": false, + "kernel_addr_check": true, + "symbolfile": "", + "readfile": "", + "thermal_model": null, + "cxx_class": "System", + "work_begin_cpu_id_exit": -1, + "load_offset": 0, + "work_begin_exit_count": 0, + "p_state_clk_gate_min": 1, + "memories": [ + "system.mem_ctrls" + ], + "work_begin_ckpt_count": 0, + "clk_domain": { + "name": "clk_domain", + "clock": [ + 1 + ], + "init_perf_level": 0, + "voltage_domain": "system.voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "mem_ranges": [ + "0:268435455:0:0:0:0" + ], + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000, + "dvfs_handler": { + "enable": false, + "name": "dvfs_handler", + "sys_clk_domain": "system.clk_domain", + "transition_latency": 100000, + "eventq_index": 0, + "cxx_class": "DVFSHandler", + "domains": [], + "path": "system.dvfs_handler", + "type": "DVFSHandler" + }, + "work_end_exit_count": 0, + "type": "System", + "voltage_domain": { + "name": "voltage_domain", + "eventq_index": 0, + "voltage": [ + "1.0" + ], + "cxx_class": "VoltageDomain", + "path": "system.voltage_domain", + "type": "VoltageDomain" + }, + "cache_line_size": 64, + "boot_osflags": "a", + "system_port": { + "peer": "system.sys_port_proxy.slave[0]", + "role": "MASTER" + }, + "sys_port_proxy": { + "system": "system", + "support_inst_reqs": true, + "slave": { + "peer": [ + "system.system_port" + ], + "role": "SLAVE" + }, + "name": "sys_port_proxy", + "p_state_clk_gate_min": 1, + "no_retry_on_stall": false, + "p_state_clk_gate_bins": 20, + "support_data_reqs": true, + "cxx_class": "RubyPortProxy", + "clk_domain": "system.clk_domain", + "power_model": null, + "is_cpu_sequencer": true, + "version": 0, + "eventq_index": 0, + "using_ruby_tester": false, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000, + "path": "system.sys_port_proxy", + "type": "RubyPortProxy", + "ruby_system": "system.ruby" + }, + "power_model": null, + "work_cpus_ckpt_count": 0, + "thermal_components": [], + "path": "system", + "ruby": { + "all_instructions": false, + "memory_size_bits": 48, + "cxx_class": "RubySystem", + "l1_cntrl0": { + "requestFromCache": { + "ordered": true, + "name": "requestFromCache", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "master": { + "peer": "system.ruby.network.slave[0]", + "role": "MASTER" + }, + "buffer_size": 0, + "path": "system.ruby.l1_cntrl0.requestFromCache", + "type": "MessageBuffer" + }, + "cxx_class": "L1Cache_Controller", + "forwardToCache": { + "ordered": true, + "name": "forwardToCache", + "cxx_class": "MessageBuffer", + "slave": { + "peer": "system.ruby.network.master[0]", + "role": "SLAVE" + }, + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.l1_cntrl0.forwardToCache", + "type": "MessageBuffer" + }, + "system": "system", + "cluster_id": 0, + "sequencer": { + "no_retry_on_stall": false, + "deadlock_threshold": 500000, + "using_ruby_tester": false, + "system": "system", + "dcache": "system.ruby.l1_cntrl0.cacheMemory", + "cxx_class": "Sequencer", + "garnet_standalone": false, + "clk_domain": "system.cpu.clk_domain", + "icache_hit_latency": 1, + "version": 0, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000, + "type": "RubySequencer", + "icache": "system.ruby.l1_cntrl0.cacheMemory", + "slave": { + "peer": [ + "system.cpu.icache_port", + "system.cpu.dcache_port" + ], + "role": "SLAVE" + }, + "p_state_clk_gate_min": 1, + "power_model": null, + "coreid": 99, + "path": "system.ruby.l1_cntrl0.sequencer", + "ruby_system": "system.ruby", + "support_inst_reqs": true, + "name": "sequencer", + "max_outstanding_requests": 16, + "p_state_clk_gate_bins": 20, + "dcache_hit_latency": 1, + "support_data_reqs": true, + "is_cpu_sequencer": true + }, + "type": "L1Cache_Controller", + "issue_latency": 2, + "recycle_latency": 10, + "clk_domain": "system.cpu.clk_domain", + "version": 0, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000, + "number_of_TBEs": 256, + "p_state_clk_gate_min": 1, + "responseToCache": { + "ordered": true, + "name": "responseToCache", + "cxx_class": "MessageBuffer", + "slave": { + "peer": "system.ruby.network.master[1]", + "role": "SLAVE" + }, + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.l1_cntrl0.responseToCache", + "type": "MessageBuffer" + }, + "transitions_per_cycle": 4, + "responseFromCache": { + "ordered": true, + "name": "responseFromCache", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "master": { + "peer": "system.ruby.network.slave[1]", + "role": "MASTER" + }, + "buffer_size": 0, + "path": "system.ruby.l1_cntrl0.responseFromCache", + "type": "MessageBuffer" + }, + "power_model": null, + "cache_response_latency": 12, + "buffer_size": 0, + "send_evictions": false, + "cacheMemory": { + "size": 256, + "resourceStalls": false, + "is_icache": false, + "name": "cacheMemory", + "eventq_index": 0, + "dataAccessLatency": 1, + "tagArrayBanks": 1, + "tagAccessLatency": 1, + "replacement_policy": { + "name": "replacement_policy", + "eventq_index": 0, + "assoc": 2, + "cxx_class": "PseudoLRUPolicy", + "path": "system.ruby.l1_cntrl0.cacheMemory.replacement_policy", + "block_size": 64, + "type": "PseudoLRUReplacementPolicy", + "size": 256 + }, + "assoc": 2, + "start_index_bit": 6, + "cxx_class": "CacheMemory", + "path": "system.ruby.l1_cntrl0.cacheMemory", + "block_size": 0, + "type": "RubyCache", + "dataArrayBanks": 1, + "ruby_system": "system.ruby" + }, + "ruby_system": "system.ruby", + "name": "l1_cntrl0", + "p_state_clk_gate_bins": 20, + "mandatoryQueue": { + "ordered": false, + "name": "mandatoryQueue", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.l1_cntrl0.mandatoryQueue", + "type": "MessageBuffer" + }, + "path": "system.ruby.l1_cntrl0" + }, + "network": { + "int_link_buffers": [ + { + "ordered": true, + "name": "int_link_buffers00", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers00", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers01", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers01", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers02", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers02", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers03", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers03", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers04", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers04", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers05", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers05", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers06", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers06", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers07", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers07", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers08", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers08", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers09", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers09", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers10", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers10", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers11", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers11", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers12", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers12", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers13", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers13", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers14", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers14", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers15", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers15", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers16", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers16", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers17", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers17", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers18", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers18", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers19", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers19", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers20", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers20", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers21", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers21", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers22", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers22", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers23", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers23", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers24", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers24", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers25", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers25", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers26", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers26", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers27", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers27", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers28", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers28", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers29", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers29", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers30", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers30", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers31", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers31", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers32", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers32", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers33", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers33", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers34", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers34", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers35", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers35", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers36", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers36", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers37", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers37", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers38", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers38", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers39", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers39", + "type": "MessageBuffer" + } + ], + "cxx_class": "SimpleNetwork", + "clk_domain": "system.ruby.clk_domain", + "adaptive_routing": false, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000, + "master": { + "peer": [ + "system.ruby.l1_cntrl0.forwardToCache.slave", + "system.ruby.l1_cntrl0.responseToCache.slave", + "system.ruby.dir_cntrl0.requestToDir.slave", + "system.ruby.dir_cntrl0.dmaRequestToDir.slave" + ], + "role": "MASTER" + }, + "topology": "Crossbar", + "type": "SimpleNetwork", + "slave": { + "peer": [ + "system.ruby.l1_cntrl0.requestFromCache.master", + "system.ruby.l1_cntrl0.responseFromCache.master", + "system.ruby.dir_cntrl0.responseFromDir.master", + "system.ruby.dir_cntrl0.dmaResponseFromDir.master", + "system.ruby.dir_cntrl0.forwardFromDir.master" + ], + "role": "SLAVE" + }, + "p_state_clk_gate_min": 1, + "int_links": [ + { + "latency": 1, + "name": "int_links0", + "weight": 1, + "src_node": "system.ruby.network.routers0", + "dst_inport": "", + "link_id": 2, + "dst_node": "system.ruby.network.routers2", + "eventq_index": 0, + "src_outport": "", + "cxx_class": "SimpleIntLink", + "path": "system.ruby.network.int_links0", + "type": "SimpleIntLink", + "bandwidth_factor": 16 + }, + { + "latency": 1, + "name": "int_links1", + "weight": 1, + "src_node": "system.ruby.network.routers1", + "dst_inport": "", + "link_id": 3, + "dst_node": "system.ruby.network.routers2", + "eventq_index": 0, + "src_outport": "", + "cxx_class": "SimpleIntLink", + "path": "system.ruby.network.int_links1", + "type": "SimpleIntLink", + "bandwidth_factor": 16 + }, + { + "latency": 1, + "name": "int_links2", + "weight": 1, + "src_node": "system.ruby.network.routers2", + "dst_inport": "", + "link_id": 4, + "dst_node": "system.ruby.network.routers0", + "eventq_index": 0, + "src_outport": "", + "cxx_class": "SimpleIntLink", + "path": "system.ruby.network.int_links2", + "type": "SimpleIntLink", + "bandwidth_factor": 16 + }, + { + "latency": 1, + "name": "int_links3", + "weight": 1, + "src_node": "system.ruby.network.routers2", + "dst_inport": "", + "link_id": 5, + "dst_node": "system.ruby.network.routers1", + "eventq_index": 0, + "src_outport": "", + "cxx_class": "SimpleIntLink", + "path": "system.ruby.network.int_links3", + "type": "SimpleIntLink", + "bandwidth_factor": 16 + } + ], + "routers": [ + { + "router_id": 0, + "latency": 1, + "name": "routers0", + "p_state_clk_gate_min": 1, + "virt_nets": 5, + "p_state_clk_gate_bins": 20, + "cxx_class": "Switch", + "clk_domain": "system.ruby.clk_domain", + "power_model": null, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000, + "path": "system.ruby.network.routers0", + "type": "Switch", + "port_buffers": [ + { + "ordered": true, + "name": "port_buffers00", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers0.port_buffers00", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers01", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers0.port_buffers01", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers02", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers0.port_buffers02", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers03", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers0.port_buffers03", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers04", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers0.port_buffers04", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers05", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers0.port_buffers05", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers06", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers0.port_buffers06", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers07", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers0.port_buffers07", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers08", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers0.port_buffers08", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers09", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers0.port_buffers09", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers10", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers0.port_buffers10", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers11", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers0.port_buffers11", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers12", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers0.port_buffers12", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers13", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers0.port_buffers13", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers14", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers0.port_buffers14", + "type": "MessageBuffer" + } + ] + }, + { + "router_id": 1, + "latency": 1, + "name": "routers1", + "p_state_clk_gate_min": 1, + "virt_nets": 5, + "p_state_clk_gate_bins": 20, + "cxx_class": "Switch", + "clk_domain": "system.ruby.clk_domain", + "power_model": null, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000, + "path": "system.ruby.network.routers1", + "type": "Switch", + "port_buffers": [ + { + "ordered": true, + "name": "port_buffers00", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers1.port_buffers00", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers01", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers1.port_buffers01", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers02", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers1.port_buffers02", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers03", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers1.port_buffers03", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers04", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers1.port_buffers04", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers05", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers1.port_buffers05", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers06", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers1.port_buffers06", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers07", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers1.port_buffers07", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers08", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers1.port_buffers08", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers09", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers1.port_buffers09", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers10", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers1.port_buffers10", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers11", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers1.port_buffers11", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers12", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers1.port_buffers12", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers13", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers1.port_buffers13", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers14", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers1.port_buffers14", + "type": "MessageBuffer" + } + ] + }, + { + "router_id": 2, + "latency": 1, + "name": "routers2", + "p_state_clk_gate_min": 1, + "virt_nets": 5, + "p_state_clk_gate_bins": 20, + "cxx_class": "Switch", + "clk_domain": "system.ruby.clk_domain", + "power_model": null, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000, + "path": "system.ruby.network.routers2", + "type": "Switch", + "port_buffers": [ + { + "ordered": true, + "name": "port_buffers00", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers2.port_buffers00", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers01", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers2.port_buffers01", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers02", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers2.port_buffers02", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers03", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers2.port_buffers03", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers04", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers2.port_buffers04", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers05", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers2.port_buffers05", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers06", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers2.port_buffers06", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers07", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers2.port_buffers07", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers08", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers2.port_buffers08", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers09", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers2.port_buffers09", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers10", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers2.port_buffers10", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers11", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers2.port_buffers11", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers12", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers2.port_buffers12", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers13", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers2.port_buffers13", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers14", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers2.port_buffers14", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers15", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers2.port_buffers15", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers16", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers2.port_buffers16", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers17", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers2.port_buffers17", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers18", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers2.port_buffers18", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers19", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers2.port_buffers19", + "type": "MessageBuffer" + } + ] + } + ], + "power_model": null, + "netifs": [], + "control_msg_size": 8, + "buffer_size": 0, + "endpoint_bandwidth": 1000, + "ruby_system": "system.ruby", + "name": "network", + "p_state_clk_gate_bins": 20, + "ext_links": [ + { + "latency": 1, + "name": "ext_links0", + "weight": 1, + "ext_node": "system.ruby.l1_cntrl0", + "link_id": 0, + "eventq_index": 0, + "cxx_class": "SimpleExtLink", + "path": "system.ruby.network.ext_links0", + "int_node": "system.ruby.network.routers0", + "type": "SimpleExtLink", + "bandwidth_factor": 16 + }, + { + "latency": 1, + "name": "ext_links1", + "weight": 1, + "ext_node": "system.ruby.dir_cntrl0", + "link_id": 1, + "eventq_index": 0, + "cxx_class": "SimpleExtLink", + "path": "system.ruby.network.ext_links1", + "int_node": "system.ruby.network.routers1", + "type": "SimpleExtLink", + "bandwidth_factor": 16 + } + ], + "number_of_virtual_networks": 5, + "path": "system.ruby.network" + }, + "clk_domain": { + "name": "clk_domain", + "clock": [ + 1 + ], + "init_perf_level": 0, + "voltage_domain": "system.voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.ruby.clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "randomization": false, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000, + "phys_mem": null, + "type": "RubySystem", + "p_state_clk_gate_min": 1, + "hot_lines": false, + "power_model": null, + "path": "system.ruby", + "memctrl_clk_domain": { + "name": "memctrl_clk_domain", + "clk_domain": "system.ruby.clk_domain", + "eventq_index": 0, + "cxx_class": "DerivedClockDomain", + "path": "system.ruby.memctrl_clk_domain", + "type": "DerivedClockDomain", + "clk_divider": 3 + }, + "name": "ruby", + "p_state_clk_gate_bins": 20, + "block_size_bytes": 64, + "access_backing_store": false, + "number_of_virtual_networks": 5, + "num_of_sequencers": 1, + "dir_cntrl0": { + "system": "system", + "cluster_id": 0, + "responseFromMemory": { + "ordered": false, + "name": "responseFromMemory", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.dir_cntrl0.responseFromMemory", + "type": "MessageBuffer" + }, + "cxx_class": "Directory_Controller", + "forwardFromDir": { + "ordered": false, + "name": "forwardFromDir", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "master": { + "peer": "system.ruby.network.slave[4]", + "role": "MASTER" + }, + "buffer_size": 0, + "path": "system.ruby.dir_cntrl0.forwardFromDir", + "type": "MessageBuffer" + }, + "dmaRequestToDir": { + "ordered": true, + "name": "dmaRequestToDir", + "cxx_class": "MessageBuffer", + "slave": { + "peer": "system.ruby.network.master[3]", + "role": "SLAVE" + }, + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.dir_cntrl0.dmaRequestToDir", + "type": "MessageBuffer" + }, + "type": "Directory_Controller", + "recycle_latency": 10, + "clk_domain": "system.ruby.clk_domain", + "version": 0, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000, + "directory_latency": 12, + "number_of_TBEs": 256, + "to_memory_controller_latency": 1, + "p_state_clk_gate_min": 1, + "responseFromDir": { + "ordered": false, + "name": "responseFromDir", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "master": { + "peer": "system.ruby.network.slave[2]", + "role": "MASTER" + }, + "buffer_size": 0, + "path": "system.ruby.dir_cntrl0.responseFromDir", + "type": "MessageBuffer" + }, + "transitions_per_cycle": 4, + "memory": { + "peer": "system.mem_ctrls.port", + "role": "MASTER" + }, + "power_model": null, + "buffer_size": 0, + "ruby_system": "system.ruby", + "requestToDir": { + "ordered": true, + "name": "requestToDir", + "cxx_class": "MessageBuffer", + "slave": { + "peer": "system.ruby.network.master[2]", + "role": "SLAVE" + }, + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.dir_cntrl0.requestToDir", + "type": "MessageBuffer" + }, + "dmaResponseFromDir": { + "ordered": true, + "name": "dmaResponseFromDir", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "master": { + "peer": "system.ruby.network.slave[3]", + "role": "MASTER" + }, + "buffer_size": 0, + "path": "system.ruby.dir_cntrl0.dmaResponseFromDir", + "type": "MessageBuffer" + }, + "name": "dir_cntrl0", + "p_state_clk_gate_bins": 20, + "directory": { + "name": "directory", + "version": 0, + "eventq_index": 0, + "cxx_class": "DirectoryMemory", + "path": "system.ruby.dir_cntrl0.directory", + "type": "RubyDirectoryMemory", + "numa_high_bit": 5, + "size": 268435456 + }, + "path": "system.ruby.dir_cntrl0" + } + }, + "work_end_ckpt_count": 0, + "mem_mode": "timing", + "name": "system", + "init_param": 0, + "p_state_clk_gate_bins": 20, + "load_addr_mask": 1099511627775, + "cpu": { + "do_statistics_insts": true, + "numThreads": 1, + "itb": { + "name": "itb", + "eventq_index": 0, + "cxx_class": "RiscvISA::TLB", + "path": "system.cpu.itb", + "type": "RiscvTLB", + "size": 64 + }, + "system": "system", + "function_trace": false, + "do_checkpoint_insts": true, + "cxx_class": "TimingSimpleCPU", + "max_loads_all_threads": 0, + "clk_domain": { + "name": "clk_domain", + "clock": [ + 1 + ], + "init_perf_level": 0, + "voltage_domain": "system.voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.cpu.clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "function_trace_start": 0, + "cpu_id": 0, + "checker": null, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000, + "do_quiesce": true, + "type": "TimingSimpleCPU", + "profile": 0, + "icache_port": { + "peer": "system.ruby.l1_cntrl0.sequencer.slave[0]", + "role": "MASTER" + }, + "p_state_clk_gate_bins": 20, + "p_state_clk_gate_min": 1, + "interrupts": [ + { + "eventq_index": 0, + "path": "system.cpu.interrupts", + "type": "RiscvInterrupts", + "name": "interrupts", + "cxx_class": "RiscvISA::Interrupts" + } + ], + "dcache_port": { + "peer": "system.ruby.l1_cntrl0.sequencer.slave[1]", + "role": "MASTER" + }, + "socket_id": 0, + "power_model": null, + "max_insts_all_threads": 0, + "path": "system.cpu", + "max_loads_any_thread": 0, + "switched_out": false, + "workload": [ + { + "uid": 100, + "pid": 100, + "kvmInSE": false, + "cxx_class": "LiveProcess", + "executable": "/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64d/insttest", + "drivers": [], + "system": "system", + "gid": 100, + "eventq_index": 0, + "env": [], + "input": "cin", + "ppid": 99, + "type": "LiveProcess", + "cwd": "", + "simpoint": 0, + "euid": 100, + "path": "system.cpu.workload", + "max_stack_size": 67108864, + "name": "workload", + "cmd": [ + "insttest" + ], + "errout": "cerr", + "useArchPT": false, + "egid": 100, + "output": "cout" + } + ], + "name": "cpu", + "dtb": { + "name": "dtb", + "eventq_index": 0, + "cxx_class": "RiscvISA::TLB", + "path": "system.cpu.dtb", + "type": "RiscvTLB", + "size": 64 + }, + "simpoint_start_insts": [], + "max_insts_any_thread": 0, + "progress_interval": 0, + "branchPred": null, + "isa": [ + { + "eventq_index": 0, + "path": "system.cpu.isa", + "type": "RiscvISA", + "name": "isa", + "cxx_class": "RiscvISA::ISA" + } + ], + "tracer": { + "eventq_index": 0, + "path": "system.cpu.tracer", + "type": "ExeTracer", + "name": "tracer", + "cxx_class": "Trace::ExeTracer" + } + }, + "multi_thread": false, + "mem_ctrls": [ + { + "static_frontend_latency": 10, + "tRFC": 260, + "activation_limit": 4, + "in_addr_map": true, + "IDD3N2": "0.0", + "tWTR": 8, + "IDD52": "0.0", + "clk_domain": "system.clk_domain", + "channels": 1, + "write_buffer_size": 64, + "device_bus_width": 8, + "VDD": "1.5", + "write_high_thresh_perc": 85, + "cxx_class": "DRAMCtrl", + "bank_groups_per_rank": 0, + "IDD2N2": "0.0", + "port": { + "peer": "system.ruby.dir_cntrl0.memory", + "role": "SLAVE" + }, + "tCCD_L": 0, + "IDD2N": "0.032", + "p_state_clk_gate_min": 1, + "null": false, + "IDD2P1": "0.032", + "eventq_index": 0, + "tRRD": 6, + "tRTW": 3, + "IDD4R": "0.157", + "burst_length": 8, + "tRTP": 8, + "IDD4W": "0.125", + "tWR": 15, + "banks_per_rank": 8, + "devices_per_rank": 8, + "IDD2P02": "0.0", + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000, + "IDD6": "0.02", + "IDD5": "0.235", + "tRCD": 14, + "type": "DRAMCtrl", + "IDD3P02": "0.0", + "tRRD_L": 0, + "IDD0": "0.055", + "IDD62": "0.0", + "min_writes_per_switch": 16, + "mem_sched_policy": "frfcfs", + "IDD02": "0.0", + "IDD2P0": "0.0", + "ranks_per_channel": 2, + "page_policy": "open_adaptive", + "IDD4W2": "0.0", + "tCS": 3, + "power_model": null, + "tCL": 14, + "read_buffer_size": 32, + "conf_table_reported": true, + "tCK": 1, + "tRAS": 35, + "tRP": 14, + "tBURST": 5, + "path": "system.mem_ctrls", + "tXP": 6, + "tXS": 270, + "addr_mapping": "RoRaBaCoCh", + "IDD3P0": "0.0", + "IDD3P1": "0.038", + "IDD3N": "0.038", + "name": "mem_ctrls", + "tXSDLL": 0, + "device_size": 536870912, + "kvm_map": true, + "dll": true, + "tXAW": 30, + "write_low_thresh_perc": 50, + "range": "0:268435455:5:19:0:0", + "VDD2": "0.0", + "IDD2P12": "0.0", + "p_state_clk_gate_bins": 20, + "tXPDLL": 0, + "IDD4R2": "0.0", + "device_rowbuffer_size": 1024, + "static_backend_latency": 10, + "max_accesses_per_row": 16, + "IDD3P12": "0.0", + "tREFI": 7800 + } + ], + "exit_on_work_items": false, + "work_item_id": -1, + "num_work_ids": 16 + }, + "time_sync_period": 100000000, + "eventq_index": 0, + "time_sync_spin_threshold": 100000, + "cxx_class": "Root", + "path": "root", + "time_sync_enable": false, + "type": "Root", + "full_system": false +}
\ No newline at end of file diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-timing-ruby/simerr b/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-timing-ruby/simerr new file mode 100755 index 000000000..63b14556f --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-timing-ruby/simerr @@ -0,0 +1,11 @@ +warn: rounding error > tolerance + 1.250000 rounded to 1 +warn: rounding error > tolerance + 1.250000 rounded to 1 +warn: rounding error > tolerance + 1.250000 rounded to 1 +warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes) +warn: Unknown operating system; assuming Linux. +warn: Sockets disabled, not accepting gdb connections +warn: ClockedObject: More than one power state change request encountered within the same simulation tick +warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files! diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-timing-ruby/simout b/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-timing-ruby/simout new file mode 100755 index 000000000..6698d57dd --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-timing-ruby/simout @@ -0,0 +1,168 @@ +Redirecting stdout to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64d/simple-timing-ruby/simout +Redirecting stderr to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64d/simple-timing-ruby/simerr +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled Nov 30 2016 14:33:35 +gem5 started Nov 30 2016 16:18:32 +gem5 executing on zizzer, pid 34074 +command line: /z/powerjg/gem5-upstream/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64d/simple-timing-ruby -re /z/powerjg/gem5-upstream/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64d/simple-timing-ruby + +Global frequency set at 1000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. +fld: PASS +fsd: PASS +fmadd.d: PASS +fmadd.d, quiet NaN: PASS +fmadd.d, signaling NaN: PASS +fmadd.d, infinity: PASS +fmadd.d, -infinity: PASS +fmsub.d: PASS +fmsub.d, quiet NaN: PASS +fmsub.d, signaling NaN: PASS +fmsub.d, infinity: PASS +fmsub.d, -infinity: PASS +fmsub.d, subtract infinity: PASS +fnmsub.d: PASS +fnmsub.d, quiet NaN: PASS +fnmsub.d, signaling NaN: PASS +fnmsub.d, infinity: PASS +fnmsub.d, -infinity: PASS +fnmsub.d, subtract infinity: PASS +fnmadd.d: PASS +fnmadd.d, quiet NaN: PASS +fnmadd.d, signaling NaN: PASS +fnmadd.d, infinity: PASS +fnmadd.d, -infinity: PASS +fadd.d: PASS +fadd.d, quiet NaN: PASS +fadd.d, signaling NaN: PASS +fadd.d, infinity: PASS +fadd.d, -infinity: PASS +fsub.d: PASS +fsub.d, quiet NaN: PASS +fsub.d, signaling NaN: PASS +fsub.d, infinity: PASS +fsub.d, -infinity: PASS +fsub.d, subtract infinity: PASS +fmul.d: PASS +fmul.d, quiet NaN: PASS +fmul.d, signaling NaN: PASS +fmul.d, infinity: PASS +fmul.d, -infinity: PASS +fmul.d, 0*infinity: PASS +fmul.d, overflow: PASS +fmul.d, underflow: PASS +fdiv.d: PASS +fdiv.d, quiet NaN: PASS +fdiv.d, signaling NaN: PASS +fdiv.d/0: PASS +fdiv.d/infinity: PASS +fdiv.d, infinity/infinity: PASS +fdiv.d, 0/0: PASS +fdiv.d, infinity/0: PASS +fdiv.d, 0/infinity: PASS +fdiv.d, underflow: PASS +fdiv.d, overflow: PASS +fsqrt.d: PASS +fsqrt.d, NaN: PASS +fsqrt.d, quiet NaN: PASS +fsqrt.d, signaling NaN: PASS +fsqrt.d, infinity: PASS +fsgnj.d, ++: PASS +fsgnj.d, +-: PASS +fsgnj.d, -+: PASS +fsgnj.d, --: PASS +fsgnj.d, quiet NaN: PASS +fsgnj.d, signaling NaN: PASS +fsgnj.d, inject NaN: PASS +fsgnj.d, inject -NaN: PASS +fsgnjn.d, ++: PASS +fsgnjn.d, +-: PASS +fsgnjn.d, -+: PASS +fsgnjn.d, --: PASS +fsgnjn.d, quiet NaN: PASS +fsgnjn.d, signaling NaN: PASS +fsgnjn.d, inject NaN: PASS +fsgnjn.d, inject NaN: PASS +fsgnjx.d, ++: PASS +fsgnjx.d, +-: PASS +fsgnjx.d, -+: PASS +fsgnjx.d, --: PASS +fsgnjx.d, quiet NaN: PASS +fsgnjx.d, signaling NaN: PASS +fsgnjx.d, inject NaN: PASS +fsgnjx.d, inject NaN: PASS +fmin.d: PASS +fmin.d, -infinity: PASS +fmin.d, infinity: PASS +fmin.d, quiet NaN first: PASS +fmin.d, quiet NaN second: PASS +fmin.d, quiet NaN both: PASS +fmin.d, signaling NaN first: PASS +fmin.d, signaling NaN second: PASS +fmin.d, signaling NaN both: PASS +fmax.d: PASS +fmax.d, -infinity: PASS +fmax.d, infinity: PASS +fmax.d, quiet NaN first: PASS +fmax.d, quiet NaN second: PASS +fmax.d, quiet NaN both: PASS +fmax.d, signaling NaN first: PASS +fmax.d, signaling NaN second: PASS +fmax.d, signaling NaN both: PASS +fcvt.s.d: PASS +fcvt.s.d, quiet NaN: PASS +fcvt.s.d, signaling NaN: PASS +fcvt.s.d, infinity: PASS +fcvt.s.d, overflow: PASS +fcvt.s.d, underflow: PASS +fcvt.d.s: PASS +fcvt.d.s, quiet NaN: PASS +fcvt.d.s, signaling NaN: PASS +fcvt.d.s, infinity: PASS +feq.d, equal: PASS +feq.d, not equal: PASS +feq.d, 0 == -0: PASS +feq.d, quiet NaN first: PASS +feq.d, quiet NaN second: PASS +feq.d, quiet NaN both: PASS +feq.d, signaling NaN first: PASS +feq.d, signaling NaN second: PASS +feq.d, signaling NaN both: PASS +flt.d, equal: PASS +flt.d, less: PASS +flt.d, greater: PASS +flt.d, quiet NaN first: PASS +flt.d, quiet NaN second: PASS +flt.d, quiet NaN both: PASS +flt.d, signaling NaN first: PASS +flt.d, signaling NaN second: PASS +flt.d, signaling NaN both: PASS +fle.d, equal: PASS +fle.d, less: PASS +fle.d, greater: PASS +fle.d, 0 == -0: PASS +fle.d, quiet NaN first: PASS +fle.d, quiet NaN second: PASS +fle.d, quiet NaN both: PASS +fle.d, signaling NaN first: PASS +fle.d, signaling NaN second: PASS +fle.d, signaling NaN both: PASS +fclass.d, -infinity: PASS +fclass.d, -normal: PASS +fclass.d, -subnormal: PASS +fclass.d, -0.0: PASS +fclass.d, 0.0: PASS +fclass.d, subnormal: PASS +fclass.d, normal: PASS +fclass.d, infinity: PASS +fclass.d, signaling NaN: PASS +fclass.s, quiet NaN: PASS +fcvt.w.d, truncate positive: PASS +fcvt.w.d, truncate negative: PASS +fcvt.w.d, 0.0: PASS +fcvt.w.d, -0.0: PASS +fcvt.w.d, overflow: [1;31mFAIL[0m (expected 2147483647; found -2147483648) +Exiting @ tick 6393532 because target called exit() diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-timing-ruby/stats.txt b/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-timing-ruby/stats.txt new file mode 100644 index 000000000..fef27ae57 --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-timing-ruby/stats.txt @@ -0,0 +1,645 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.006394 # Number of seconds simulated +sim_ticks 6393532 # Number of ticks simulated +final_tick 6393532 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000 # Frequency of simulated ticks +host_inst_rate 13428 # Simulator instruction rate (inst/s) +host_op_rate 13428 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 286950 # Simulator tick rate (ticks/s) +host_mem_usage 412476 # Number of bytes of host memory used +host_seconds 22.28 # Real time elapsed on the host +sim_insts 299191 # Number of instructions simulated +sim_ops 299191 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1 # Clock period in ticks +system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 6393532 # Cumulative time (in ticks) in various power states +system.mem_ctrls.bytes_read::ruby.dir_cntrl0 6256640 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::total 6256640 # Number of bytes read from this memory +system.mem_ctrls.bytes_written::ruby.dir_cntrl0 6256384 # Number of bytes written to this memory +system.mem_ctrls.bytes_written::total 6256384 # Number of bytes written to this memory +system.mem_ctrls.num_reads::ruby.dir_cntrl0 97760 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::total 97760 # Number of read requests responded to by this memory +system.mem_ctrls.num_writes::ruby.dir_cntrl0 97756 # Number of write requests responded to by this memory +system.mem_ctrls.num_writes::total 97756 # Number of write requests responded to by this memory +system.mem_ctrls.bw_read::ruby.dir_cntrl0 978588986 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::total 978588986 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::ruby.dir_cntrl0 978548946 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::total 978548946 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_total::ruby.dir_cntrl0 1957137933 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::total 1957137933 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.readReqs 97760 # Number of read requests accepted +system.mem_ctrls.writeReqs 97756 # Number of write requests accepted +system.mem_ctrls.readBursts 97760 # Number of DRAM read bursts, including those serviced by the write queue +system.mem_ctrls.writeBursts 97756 # Number of DRAM write bursts, including those merged in the write queue +system.mem_ctrls.bytesReadDRAM 3295040 # Total number of bytes read from DRAM +system.mem_ctrls.bytesReadWrQ 2961600 # Total number of bytes read from write queue +system.mem_ctrls.bytesWritten 3443712 # Total number of bytes written to DRAM +system.mem_ctrls.bytesReadSys 6256640 # Total read bytes from the system interface side +system.mem_ctrls.bytesWrittenSys 6256384 # Total written bytes from the system interface side +system.mem_ctrls.servicedByWrQ 46275 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrls.mergedWrBursts 43917 # Number of DRAM write bursts merged with an existing one +system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.mem_ctrls.perBankRdBursts::0 352 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::1 1012 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::2 26 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::3 3288 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::4 5256 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::5 9431 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::6 7439 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::7 1368 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::8 225 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::9 1039 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::10 2533 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::11 14031 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::12 3005 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::13 1537 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::14 25 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::15 918 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::0 359 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::1 1066 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::2 34 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::3 3555 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::4 5446 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::5 9633 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::6 8466 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::7 1431 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::8 225 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::9 1069 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::10 2579 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::11 14351 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::12 3053 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::13 1590 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::14 28 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::15 923 # Per bank write bursts +system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry +system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry +system.mem_ctrls.totGap 6393460 # Total gap between requests +system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::6 97760 # Read request sizes (log2) +system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::6 97756 # Write request sizes (log2) +system.mem_ctrls.rdQLenPdf::0 51485 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::1 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::2 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::4 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::0 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::1 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::2 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::3 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::4 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::5 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::6 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::7 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::8 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::9 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::10 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::11 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::15 306 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::16 334 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::17 2779 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::18 3333 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::19 3383 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::20 3473 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::21 3559 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::22 3516 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::23 3321 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::24 3315 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::25 3314 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::26 3314 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::27 3314 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::28 3313 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::29 3313 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::30 3313 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::31 3312 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::32 3312 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.mem_ctrls.bytesPerActivate::samples 20661 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::mean 326.074440 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::gmean 208.715959 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::stdev 320.266569 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::0-127 5014 24.27% 24.27% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::128-255 6296 30.47% 54.74% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::256-383 3457 16.73% 71.47% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::384-511 1315 6.36% 77.84% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::512-639 736 3.56% 81.40% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::640-767 594 2.87% 84.27% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::768-895 389 1.88% 86.16% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::896-1023 293 1.42% 87.58% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::1024-1151 2567 12.42% 100.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::total 20661 # Bytes accessed per row activation +system.mem_ctrls.rdPerTurnAround::samples 3312 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::mean 15.540459 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::gmean 15.485552 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::stdev 1.332467 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::12-13 139 4.20% 4.20% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::14-15 1517 45.80% 50.00% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::16-17 1421 42.90% 92.90% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::18-19 229 6.91% 99.82% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::20-21 5 0.15% 99.97% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::36-37 1 0.03% 100.00% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::total 3312 # Reads before turning the bus around for writes +system.mem_ctrls.wrPerTurnAround::samples 3312 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::mean 16.246377 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::gmean 16.229566 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::stdev 0.773105 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::16 2986 90.16% 90.16% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::17 14 0.42% 90.58% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::18 147 4.44% 95.02% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::19 153 4.62% 99.64% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::20 11 0.33% 99.97% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::21 1 0.03% 100.00% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::total 3312 # Writes before turning the bus around for reads +system.mem_ctrls.totQLat 1034437 # Total ticks spent queuing +system.mem_ctrls.totMemAccLat 2012652 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.totBusLat 257425 # Total ticks spent in databus transfers +system.mem_ctrls.avgQLat 20.09 # Average queueing delay per DRAM burst +system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst +system.mem_ctrls.avgMemAccLat 39.09 # Average memory access latency per DRAM burst +system.mem_ctrls.avgRdBW 515.37 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrls.avgWrBW 538.62 # Average achieved write bandwidth in MiByte/s +system.mem_ctrls.avgRdBWSys 978.59 # Average system read bandwidth in MiByte/s +system.mem_ctrls.avgWrBWSys 978.55 # Average system write bandwidth in MiByte/s +system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.mem_ctrls.busUtil 8.23 # Data bus utilization in percentage +system.mem_ctrls.busUtilRead 4.03 # Data bus utilization in percentage for reads +system.mem_ctrls.busUtilWrite 4.21 # Data bus utilization in percentage for writes +system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing +system.mem_ctrls.avgWrQLen 25.90 # Average write queue length when enqueuing +system.mem_ctrls.readRowHits 36136 # Number of row buffer hits during reads +system.mem_ctrls.writeRowHits 48490 # Number of row buffer hits during writes +system.mem_ctrls.readRowHitRate 70.19 # Row buffer hit rate for reads +system.mem_ctrls.writeRowHitRate 90.06 # Row buffer hit rate for writes +system.mem_ctrls.avgGap 32.70 # Average gap between requests +system.mem_ctrls.pageHitRate 80.35 # Row buffer hit rate, read and write combined +system.mem_ctrls_0.actEnergy 95226180 # Energy for activate commands per rank (pJ) +system.mem_ctrls_0.preEnergy 51522576 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_0.readEnergy 321836928 # Energy for read commands per rank (pJ) +system.mem_ctrls_0.writeEnergy 250476480 # Energy for write commands per rank (pJ) +system.mem_ctrls_0.refreshEnergy 501546240.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_0.actBackEnergy 829542432 # Energy for active background per rank (pJ) +system.mem_ctrls_0.preBackEnergy 11702016 # Energy for precharge background per rank (pJ) +system.mem_ctrls_0.actPowerDownEnergy 1925180016 # Energy for active power-down per rank (pJ) +system.mem_ctrls_0.prePowerDownEnergy 78745728 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls_0.selfRefreshEnergy 34138560 # Energy for self refresh per rank (pJ) +system.mem_ctrls_0.totalEnergy 4099917156 # Total energy per rank (pJ) +system.mem_ctrls_0.averagePower 641.260129 # Core power per rank (mW) +system.mem_ctrls_0.totalIdleTime 4543849 # Total Idle time Per DRAM Rank +system.mem_ctrls_0.memoryStateTime::IDLE 6758 # Time in different power states +system.mem_ctrls_0.memoryStateTime::REF 212226 # Time in different power states +system.mem_ctrls_0.memoryStateTime::SREF 116933 # Time in different power states +system.mem_ctrls_0.memoryStateTime::PRE_PDN 205067 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT 1630662 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT_PDN 4221886 # Time in different power states +system.mem_ctrls_1.actEnergy 52336200 # Energy for activate commands per rank (pJ) +system.mem_ctrls_1.preEnergy 28311528 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_1.readEnergy 266327712 # Energy for read commands per rank (pJ) +system.mem_ctrls_1.writeEnergy 198927936 # Energy for write commands per rank (pJ) +system.mem_ctrls_1.refreshEnergy 482492400.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_1.actBackEnergy 818266464 # Energy for active background per rank (pJ) +system.mem_ctrls_1.preBackEnergy 13925376 # Energy for precharge background per rank (pJ) +system.mem_ctrls_1.actPowerDownEnergy 1847919480 # Energy for active power-down per rank (pJ) +system.mem_ctrls_1.prePowerDownEnergy 72638976 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls_1.selfRefreshEnergy 80402640 # Energy for self refresh per rank (pJ) +system.mem_ctrls_1.totalEnergy 3861548712 # Total energy per rank (pJ) +system.mem_ctrls_1.averagePower 603.977381 # Core power per rank (mW) +system.mem_ctrls_1.totalIdleTime 4562502 # Total Idle time Per DRAM Rank +system.mem_ctrls_1.memoryStateTime::IDLE 13661 # Time in different power states +system.mem_ctrls_1.memoryStateTime::REF 204136 # Time in different power states +system.mem_ctrls_1.memoryStateTime::SREF 321205 # Time in different power states +system.mem_ctrls_1.memoryStateTime::PRE_PDN 189164 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT 1612911 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT_PDN 4052455 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 6393532 # Cumulative time (in ticks) in various power states +system.cpu.clk_domain.clock 1 # Clock period in ticks +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 162 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 6393532 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 6393532 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 299191 # Number of instructions committed +system.cpu.committedOps 299191 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 299008 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 1025 # Number of float alu accesses +system.cpu.num_func_calls 21816 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 44561 # number of instructions that are conditional controls +system.cpu.num_int_insts 299008 # number of integer instructions +system.cpu.num_fp_insts 1025 # number of float instructions +system.cpu.num_int_register_reads 394163 # number of times the integer registers were read +system.cpu.num_int_register_writes 205779 # number of times the integer registers were written +system.cpu.num_fp_register_reads 851 # number of times the floating registers were read +system.cpu.num_fp_register_writes 688 # number of times the floating registers were written +system.cpu.num_mem_refs 118390 # number of memory refs +system.cpu.num_load_insts 69843 # Number of load instructions +system.cpu.num_store_insts 48547 # Number of store instructions +system.cpu.num_idle_cycles 0 # Number of idle cycles +system.cpu.num_busy_cycles 6393532 # Number of busy cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.Branches 66377 # Number of branches fetched +system.cpu.op_class::No_OpClass 162 0.05% 0.05% # Class of executed instruction +system.cpu.op_class::IntAlu 179913 60.10% 60.15% # Class of executed instruction +system.cpu.op_class::IntMult 466 0.16% 60.31% # Class of executed instruction +system.cpu.op_class::IntDiv 40 0.01% 60.32% # Class of executed instruction +system.cpu.op_class::FloatAdd 120 0.04% 60.36% # Class of executed instruction +system.cpu.op_class::FloatCmp 157 0.05% 60.42% # Class of executed instruction +system.cpu.op_class::FloatCvt 60 0.02% 60.44% # Class of executed instruction +system.cpu.op_class::FloatMult 30 0.01% 60.45% # Class of executed instruction +system.cpu.op_class::FloatMultAcc 0 0.00% 60.45% # Class of executed instruction +system.cpu.op_class::FloatDiv 11 0.00% 60.45% # Class of executed instruction +system.cpu.op_class::FloatMisc 0 0.00% 60.45% # Class of executed instruction +system.cpu.op_class::FloatSqrt 5 0.00% 60.45% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 60.45% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 60.45% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 60.45% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 60.45% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 60.45% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 60.45% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 60.45% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 60.45% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 60.45% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 60.45% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 60.45% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 60.45% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 60.45% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 60.45% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 60.45% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 60.45% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 60.45% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 60.45% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 60.45% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 60.45% # Class of executed instruction +system.cpu.op_class::MemRead 69348 23.17% 83.62% # Class of executed instruction +system.cpu.op_class::MemWrite 48400 16.17% 99.79% # Class of executed instruction +system.cpu.op_class::FloatMemRead 495 0.17% 99.95% # Class of executed instruction +system.cpu.op_class::FloatMemWrite 147 0.05% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 299354 # Class of executed instruction +system.ruby.clk_domain.clock 1 # Clock period in ticks +system.ruby.pwrStateResidencyTicks::UNDEFINED 6393532 # Cumulative time (in ticks) in various power states +system.ruby.delayHist::bucket_size 1 # delay histogram for all message +system.ruby.delayHist::max_bucket 9 # delay histogram for all message +system.ruby.delayHist::samples 195516 # delay histogram for all message +system.ruby.delayHist | 195516 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message +system.ruby.delayHist::total 195516 # delay histogram for all message +system.ruby.outstanding_req_hist_seqr::bucket_size 1 +system.ruby.outstanding_req_hist_seqr::max_bucket 9 +system.ruby.outstanding_req_hist_seqr::samples 417744 +system.ruby.outstanding_req_hist_seqr::mean 1 +system.ruby.outstanding_req_hist_seqr::gmean 1 +system.ruby.outstanding_req_hist_seqr | 0 0.00% 0.00% | 417744 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.outstanding_req_hist_seqr::total 417744 +system.ruby.latency_hist_seqr::bucket_size 64 +system.ruby.latency_hist_seqr::max_bucket 639 +system.ruby.latency_hist_seqr::samples 417743 +system.ruby.latency_hist_seqr::mean 14.304941 +system.ruby.latency_hist_seqr::gmean 2.506373 +system.ruby.latency_hist_seqr::stdev 29.993401 +system.ruby.latency_hist_seqr | 367877 88.06% 88.06% | 46330 11.09% 99.15% | 2431 0.58% 99.74% | 380 0.09% 99.83% | 382 0.09% 99.92% | 309 0.07% 99.99% | 15 0.00% 100.00% | 3 0.00% 100.00% | 0 0.00% 100.00% | 16 0.00% 100.00% +system.ruby.latency_hist_seqr::total 417743 +system.ruby.hit_latency_hist_seqr::bucket_size 1 +system.ruby.hit_latency_hist_seqr::max_bucket 9 +system.ruby.hit_latency_hist_seqr::samples 319983 +system.ruby.hit_latency_hist_seqr::mean 1 +system.ruby.hit_latency_hist_seqr::gmean 1 +system.ruby.hit_latency_hist_seqr | 0 0.00% 0.00% | 319983 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.hit_latency_hist_seqr::total 319983 +system.ruby.miss_latency_hist_seqr::bucket_size 64 +system.ruby.miss_latency_hist_seqr::max_bucket 639 +system.ruby.miss_latency_hist_seqr::samples 97760 +system.ruby.miss_latency_hist_seqr::mean 57.853989 +system.ruby.miss_latency_hist_seqr::gmean 50.720255 +system.ruby.miss_latency_hist_seqr::stdev 36.989317 +system.ruby.miss_latency_hist_seqr | 47894 48.99% 48.99% | 46330 47.39% 96.38% | 2431 2.49% 98.87% | 380 0.39% 99.26% | 382 0.39% 99.65% | 309 0.32% 99.97% | 15 0.02% 99.98% | 3 0.00% 99.98% | 0 0.00% 99.98% | 16 0.02% 100.00% +system.ruby.miss_latency_hist_seqr::total 97760 +system.ruby.Directory.incomplete_times_seqr 97759 +system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 6393532 # Cumulative time (in ticks) in various power states +system.ruby.l1_cntrl0.cacheMemory.demand_hits 319983 # Number of cache demand hits +system.ruby.l1_cntrl0.cacheMemory.demand_misses 97760 # Number of cache demand misses +system.ruby.l1_cntrl0.cacheMemory.demand_accesses 417743 # Number of cache demand accesses +system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 6393532 # Cumulative time (in ticks) in various power states +system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 6393532 # Cumulative time (in ticks) in various power states +system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks +system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 6393532 # Cumulative time (in ticks) in various power states +system.ruby.network.routers0.percent_links_utilized 7.645070 +system.ruby.network.routers0.msg_count.Control::2 97760 +system.ruby.network.routers0.msg_count.Data::2 97756 +system.ruby.network.routers0.msg_count.Response_Data::4 97760 +system.ruby.network.routers0.msg_count.Writeback_Control::3 97756 +system.ruby.network.routers0.msg_bytes.Control::2 782080 +system.ruby.network.routers0.msg_bytes.Data::2 7038432 +system.ruby.network.routers0.msg_bytes.Response_Data::4 7038720 +system.ruby.network.routers0.msg_bytes.Writeback_Control::3 782048 +system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 6393532 # Cumulative time (in ticks) in various power states +system.ruby.network.routers1.percent_links_utilized 7.645070 +system.ruby.network.routers1.msg_count.Control::2 97760 +system.ruby.network.routers1.msg_count.Data::2 97756 +system.ruby.network.routers1.msg_count.Response_Data::4 97760 +system.ruby.network.routers1.msg_count.Writeback_Control::3 97756 +system.ruby.network.routers1.msg_bytes.Control::2 782080 +system.ruby.network.routers1.msg_bytes.Data::2 7038432 +system.ruby.network.routers1.msg_bytes.Response_Data::4 7038720 +system.ruby.network.routers1.msg_bytes.Writeback_Control::3 782048 +system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 6393532 # Cumulative time (in ticks) in various power states +system.ruby.network.routers2.percent_links_utilized 7.645070 +system.ruby.network.routers2.msg_count.Control::2 97760 +system.ruby.network.routers2.msg_count.Data::2 97756 +system.ruby.network.routers2.msg_count.Response_Data::4 97760 +system.ruby.network.routers2.msg_count.Writeback_Control::3 97756 +system.ruby.network.routers2.msg_bytes.Control::2 782080 +system.ruby.network.routers2.msg_bytes.Data::2 7038432 +system.ruby.network.routers2.msg_bytes.Response_Data::4 7038720 +system.ruby.network.routers2.msg_bytes.Writeback_Control::3 782048 +system.ruby.network.pwrStateResidencyTicks::UNDEFINED 6393532 # Cumulative time (in ticks) in various power states +system.ruby.network.msg_count.Control 293280 +system.ruby.network.msg_count.Data 293268 +system.ruby.network.msg_count.Response_Data 293280 +system.ruby.network.msg_count.Writeback_Control 293268 +system.ruby.network.msg_byte.Control 2346240 +system.ruby.network.msg_byte.Data 21115296 +system.ruby.network.msg_byte.Response_Data 21116160 +system.ruby.network.msg_byte.Writeback_Control 2346144 +system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 6393532 # Cumulative time (in ticks) in various power states +system.ruby.network.routers0.throttle0.link_utilization 7.645195 +system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 97760 +system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 97756 +system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 7038720 +system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3 782048 +system.ruby.network.routers0.throttle1.link_utilization 7.644945 +system.ruby.network.routers0.throttle1.msg_count.Control::2 97760 +system.ruby.network.routers0.throttle1.msg_count.Data::2 97756 +system.ruby.network.routers0.throttle1.msg_bytes.Control::2 782080 +system.ruby.network.routers0.throttle1.msg_bytes.Data::2 7038432 +system.ruby.network.routers1.throttle0.link_utilization 7.644945 +system.ruby.network.routers1.throttle0.msg_count.Control::2 97760 +system.ruby.network.routers1.throttle0.msg_count.Data::2 97756 +system.ruby.network.routers1.throttle0.msg_bytes.Control::2 782080 +system.ruby.network.routers1.throttle0.msg_bytes.Data::2 7038432 +system.ruby.network.routers1.throttle1.link_utilization 7.645195 +system.ruby.network.routers1.throttle1.msg_count.Response_Data::4 97760 +system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::3 97756 +system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4 7038720 +system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::3 782048 +system.ruby.network.routers2.throttle0.link_utilization 7.645195 +system.ruby.network.routers2.throttle0.msg_count.Response_Data::4 97760 +system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3 97756 +system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4 7038720 +system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3 782048 +system.ruby.network.routers2.throttle1.link_utilization 7.644945 +system.ruby.network.routers2.throttle1.msg_count.Control::2 97760 +system.ruby.network.routers2.throttle1.msg_count.Data::2 97756 +system.ruby.network.routers2.throttle1.msg_bytes.Control::2 782080 +system.ruby.network.routers2.throttle1.msg_bytes.Data::2 7038432 +system.ruby.delayVCHist.vnet_1::bucket_size 1 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1::max_bucket 9 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1::samples 97760 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1 | 97760 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1::total 97760 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_2::bucket_size 1 # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2::max_bucket 9 # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2::samples 97756 # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2 | 97756 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2::total 97756 # delay histogram for vnet_2 +system.ruby.LD.latency_hist_seqr::bucket_size 64 +system.ruby.LD.latency_hist_seqr::max_bucket 639 +system.ruby.LD.latency_hist_seqr::samples 69843 +system.ruby.LD.latency_hist_seqr::mean 28.322194 +system.ruby.LD.latency_hist_seqr::gmean 7.510857 +system.ruby.LD.latency_hist_seqr::stdev 36.108227 +system.ruby.LD.latency_hist_seqr | 55897 80.03% 80.03% | 12888 18.45% 98.49% | 741 1.06% 99.55% | 131 0.19% 99.73% | 105 0.15% 99.88% | 76 0.11% 99.99% | 4 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 1 0.00% 100.00% +system.ruby.LD.latency_hist_seqr::total 69843 +system.ruby.LD.hit_latency_hist_seqr::bucket_size 1 +system.ruby.LD.hit_latency_hist_seqr::max_bucket 9 +system.ruby.LD.hit_latency_hist_seqr::samples 33083 +system.ruby.LD.hit_latency_hist_seqr::mean 1 +system.ruby.LD.hit_latency_hist_seqr::gmean 1 +system.ruby.LD.hit_latency_hist_seqr | 0 0.00% 0.00% | 33083 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.hit_latency_hist_seqr::total 33083 +system.ruby.LD.miss_latency_hist_seqr::bucket_size 64 +system.ruby.LD.miss_latency_hist_seqr::max_bucket 639 +system.ruby.LD.miss_latency_hist_seqr::samples 36760 +system.ruby.LD.miss_latency_hist_seqr::mean 52.911425 +system.ruby.LD.miss_latency_hist_seqr::gmean 46.109058 +system.ruby.LD.miss_latency_hist_seqr::stdev 34.651513 +system.ruby.LD.miss_latency_hist_seqr | 22814 62.06% 62.06% | 12888 35.06% 97.12% | 741 2.02% 99.14% | 131 0.36% 99.49% | 105 0.29% 99.78% | 76 0.21% 99.99% | 4 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 1 0.00% 100.00% +system.ruby.LD.miss_latency_hist_seqr::total 36760 +system.ruby.ST.latency_hist_seqr::bucket_size 64 +system.ruby.ST.latency_hist_seqr::max_bucket 639 +system.ruby.ST.latency_hist_seqr::samples 48546 +system.ruby.ST.latency_hist_seqr::mean 14.735838 +system.ruby.ST.latency_hist_seqr::gmean 3.058930 +system.ruby.ST.latency_hist_seqr::stdev 27.657147 +system.ruby.ST.latency_hist_seqr | 44298 91.25% 91.25% | 3958 8.15% 99.40% | 180 0.37% 99.77% | 35 0.07% 99.85% | 42 0.09% 99.93% | 23 0.05% 99.98% | 0 0.00% 99.98% | 0 0.00% 99.98% | 0 0.00% 99.98% | 10 0.02% 100.00% +system.ruby.ST.latency_hist_seqr::total 48546 +system.ruby.ST.hit_latency_hist_seqr::bucket_size 1 +system.ruby.ST.hit_latency_hist_seqr::max_bucket 9 +system.ruby.ST.hit_latency_hist_seqr::samples 33996 +system.ruby.ST.hit_latency_hist_seqr::mean 1 +system.ruby.ST.hit_latency_hist_seqr::gmean 1 +system.ruby.ST.hit_latency_hist_seqr | 0 0.00% 0.00% | 33996 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.hit_latency_hist_seqr::total 33996 +system.ruby.ST.miss_latency_hist_seqr::bucket_size 64 +system.ruby.ST.miss_latency_hist_seqr::max_bucket 639 +system.ruby.ST.miss_latency_hist_seqr::samples 14550 +system.ruby.ST.miss_latency_hist_seqr::mean 46.829553 +system.ruby.ST.miss_latency_hist_seqr::gmean 41.696554 +system.ruby.ST.miss_latency_hist_seqr::stdev 32.883513 +system.ruby.ST.miss_latency_hist_seqr | 10302 70.80% 70.80% | 3958 27.20% 98.01% | 180 1.24% 99.24% | 35 0.24% 99.48% | 42 0.29% 99.77% | 23 0.16% 99.93% | 0 0.00% 99.93% | 0 0.00% 99.93% | 0 0.00% 99.93% | 10 0.07% 100.00% +system.ruby.ST.miss_latency_hist_seqr::total 14550 +system.ruby.IFETCH.latency_hist_seqr::bucket_size 64 +system.ruby.IFETCH.latency_hist_seqr::max_bucket 639 +system.ruby.IFETCH.latency_hist_seqr::samples 299354 +system.ruby.IFETCH.latency_hist_seqr::mean 10.964664 +system.ruby.IFETCH.latency_hist_seqr::gmean 1.878483 +system.ruby.IFETCH.latency_hist_seqr::stdev 27.751002 +system.ruby.IFETCH.latency_hist_seqr | 267682 89.42% 89.42% | 29484 9.85% 99.27% | 1510 0.50% 99.77% | 214 0.07% 99.84% | 235 0.08% 99.92% | 210 0.07% 99.99% | 11 0.00% 100.00% | 3 0.00% 100.00% | 0 0.00% 100.00% | 5 0.00% 100.00% +system.ruby.IFETCH.latency_hist_seqr::total 299354 +system.ruby.IFETCH.hit_latency_hist_seqr::bucket_size 1 +system.ruby.IFETCH.hit_latency_hist_seqr::max_bucket 9 +system.ruby.IFETCH.hit_latency_hist_seqr::samples 252904 +system.ruby.IFETCH.hit_latency_hist_seqr::mean 1 +system.ruby.IFETCH.hit_latency_hist_seqr::gmean 1 +system.ruby.IFETCH.hit_latency_hist_seqr | 0 0.00% 0.00% | 252904 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.hit_latency_hist_seqr::total 252904 +system.ruby.IFETCH.miss_latency_hist_seqr::bucket_size 64 +system.ruby.IFETCH.miss_latency_hist_seqr::max_bucket 639 +system.ruby.IFETCH.miss_latency_hist_seqr::samples 46450 +system.ruby.IFETCH.miss_latency_hist_seqr::mean 65.218773 +system.ruby.IFETCH.miss_latency_hist_seqr::gmean 58.155656 +system.ruby.IFETCH.miss_latency_hist_seqr::stdev 38.458091 +system.ruby.IFETCH.miss_latency_hist_seqr | 14778 31.81% 31.81% | 29484 63.47% 95.29% | 1510 3.25% 98.54% | 214 0.46% 99.00% | 235 0.51% 99.51% | 210 0.45% 99.96% | 11 0.02% 99.98% | 3 0.01% 99.99% | 0 0.00% 99.99% | 5 0.01% 100.00% +system.ruby.IFETCH.miss_latency_hist_seqr::total 46450 +system.ruby.Directory.miss_mach_latency_hist_seqr::bucket_size 64 +system.ruby.Directory.miss_mach_latency_hist_seqr::max_bucket 639 +system.ruby.Directory.miss_mach_latency_hist_seqr::samples 97760 +system.ruby.Directory.miss_mach_latency_hist_seqr::mean 57.853989 +system.ruby.Directory.miss_mach_latency_hist_seqr::gmean 50.720255 +system.ruby.Directory.miss_mach_latency_hist_seqr::stdev 36.989317 +system.ruby.Directory.miss_mach_latency_hist_seqr | 47894 48.99% 48.99% | 46330 47.39% 96.38% | 2431 2.49% 98.87% | 380 0.39% 99.26% | 382 0.39% 99.65% | 309 0.32% 99.97% | 15 0.02% 99.98% | 3 0.00% 99.98% | 0 0.00% 99.98% | 16 0.02% 100.00% +system.ruby.Directory.miss_mach_latency_hist_seqr::total 97760 +system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::bucket_size 1 +system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::max_bucket 9 +system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::samples 1 +system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::stdev nan +system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::total 1 +system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::bucket_size 1 +system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::max_bucket 9 +system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::samples 1 +system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::stdev nan +system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::total 1 +system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::bucket_size 1 +system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::max_bucket 9 +system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::samples 1 +system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::stdev nan +system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::total 1 +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::bucket_size 8 +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::max_bucket 79 +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::samples 1 +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::mean 75 +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::gmean 75.000000 +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::stdev nan +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::total 1 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::samples 36760 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::mean 52.911425 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::gmean 46.109058 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::stdev 34.651513 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr | 22814 62.06% 62.06% | 12888 35.06% 97.12% | 741 2.02% 99.14% | 131 0.36% 99.49% | 105 0.29% 99.78% | 76 0.21% 99.99% | 4 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 1 0.00% 100.00% +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::total 36760 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::samples 14550 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::mean 46.829553 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::gmean 41.696554 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::stdev 32.883513 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr | 10302 70.80% 70.80% | 3958 27.20% 98.01% | 180 1.24% 99.24% | 35 0.24% 99.48% | 42 0.29% 99.77% | 23 0.16% 99.93% | 0 0.00% 99.93% | 0 0.00% 99.93% | 0 0.00% 99.93% | 10 0.07% 100.00% +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::total 14550 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::samples 46450 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::mean 65.218773 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::gmean 58.155656 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::stdev 38.458091 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr | 14778 31.81% 31.81% | 29484 63.47% 95.29% | 1510 3.25% 98.54% | 214 0.46% 99.00% | 235 0.51% 99.51% | 210 0.45% 99.96% | 11 0.02% 99.98% | 3 0.01% 99.99% | 0 0.00% 99.99% | 5 0.01% 100.00% +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::total 46450 +system.ruby.Directory_Controller.GETX 97760 0.00% 0.00% +system.ruby.Directory_Controller.PUTX 97756 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Data 97760 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Ack 97756 0.00% 0.00% +system.ruby.Directory_Controller.I.GETX 97760 0.00% 0.00% +system.ruby.Directory_Controller.M.PUTX 97756 0.00% 0.00% +system.ruby.Directory_Controller.IM.Memory_Data 97760 0.00% 0.00% +system.ruby.Directory_Controller.MI.Memory_Ack 97756 0.00% 0.00% +system.ruby.L1Cache_Controller.Load 69843 0.00% 0.00% +system.ruby.L1Cache_Controller.Ifetch 299354 0.00% 0.00% +system.ruby.L1Cache_Controller.Store 48546 0.00% 0.00% +system.ruby.L1Cache_Controller.Data 97760 0.00% 0.00% +system.ruby.L1Cache_Controller.Replacement 97756 0.00% 0.00% +system.ruby.L1Cache_Controller.Writeback_Ack 97756 0.00% 0.00% +system.ruby.L1Cache_Controller.I.Load 36760 0.00% 0.00% +system.ruby.L1Cache_Controller.I.Ifetch 46450 0.00% 0.00% +system.ruby.L1Cache_Controller.I.Store 14550 0.00% 0.00% +system.ruby.L1Cache_Controller.M.Load 33083 0.00% 0.00% +system.ruby.L1Cache_Controller.M.Ifetch 252904 0.00% 0.00% +system.ruby.L1Cache_Controller.M.Store 33996 0.00% 0.00% +system.ruby.L1Cache_Controller.M.Replacement 97756 0.00% 0.00% +system.ruby.L1Cache_Controller.MI.Writeback_Ack 97756 0.00% 0.00% +system.ruby.L1Cache_Controller.IS.Data 83210 0.00% 0.00% +system.ruby.L1Cache_Controller.IM.Data 14550 0.00% 0.00% + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-timing/config.ini b/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-timing/config.ini new file mode 100644 index 000000000..be13c3ba9 --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-timing/config.ini @@ -0,0 +1,380 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain +boot_osflags=a +cache_line_size=64 +clk_domain=system.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +exit_on_work_items=false +init_param=0 +kernel= +kernel_addr_check=true +load_addr_mask=1099511627775 +load_offset=0 +mem_mode=timing +mem_ranges= +memories=system.physmem +mmap_using_noreserve=false +multi_thread=false +num_work_ids=16 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +readfile= +symbolfile= +thermal_components= +thermal_model=Null +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=TimingSimpleCPU +children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload +branchPred=Null +checker=Null +clk_domain=system.cpu_clk_domain +cpu_id=0 +default_p_state=UNDEFINED +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +eventq_index=0 +function_trace=false +function_trace_start=0 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +profile=0 +progress_interval=0 +simpoint_start_insts= +socket_id=0 +switched_out=false +system=system +tracer=system.cpu.tracer +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.dcache] +type=Cache +children=tags +addr_ranges=0:18446744073709551615:0:0:0:0 +assoc=2 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +data_latency=2 +default_p_state=UNDEFINED +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=4 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=262144 +system=system +tag_latency=2 +tags=system.cpu.dcache.tags +tgts_per_mshr=20 +write_buffers=8 +writeback_clean=false +cpu_side=system.cpu.dcache_port +mem_side=system.cpu.toL2Bus.slave[1] + +[system.cpu.dcache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +data_latency=2 +default_p_state=UNDEFINED +eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +sequential_access=false +size=262144 +tag_latency=2 + +[system.cpu.dtb] +type=RiscvTLB +eventq_index=0 +size=64 + +[system.cpu.icache] +type=Cache +children=tags +addr_ranges=0:18446744073709551615:0:0:0:0 +assoc=2 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +data_latency=2 +default_p_state=UNDEFINED +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=true +max_miss_count=0 +mshrs=4 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=131072 +system=system +tag_latency=2 +tags=system.cpu.icache.tags +tgts_per_mshr=20 +write_buffers=8 +writeback_clean=true +cpu_side=system.cpu.icache_port +mem_side=system.cpu.toL2Bus.slave[0] + +[system.cpu.icache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +data_latency=2 +default_p_state=UNDEFINED +eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +sequential_access=false +size=131072 +tag_latency=2 + +[system.cpu.interrupts] +type=RiscvInterrupts +eventq_index=0 + +[system.cpu.isa] +type=RiscvISA +eventq_index=0 + +[system.cpu.itb] +type=RiscvTLB +eventq_index=0 +size=64 + +[system.cpu.l2cache] +type=Cache +children=tags +addr_ranges=0:18446744073709551615:0:0:0:0 +assoc=8 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +data_latency=20 +default_p_state=UNDEFINED +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=20 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +prefetch_on_access=false +prefetcher=Null +response_latency=20 +sequential_access=false +size=2097152 +system=system +tag_latency=20 +tags=system.cpu.l2cache.tags +tgts_per_mshr=12 +write_buffers=8 +writeback_clean=false +cpu_side=system.cpu.toL2Bus.master[0] +mem_side=system.membus.slave[1] + +[system.cpu.l2cache.tags] +type=LRU +assoc=8 +block_size=64 +clk_domain=system.cpu_clk_domain +data_latency=20 +default_p_state=UNDEFINED +eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +sequential_access=false +size=2097152 +tag_latency=20 + +[system.cpu.toL2Bus] +type=CoherentXBar +children=snoop_filter +clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED +eventq_index=0 +forward_latency=0 +frontend_latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +point_of_coherency=false +power_model=Null +response_latency=1 +snoop_filter=system.cpu.toL2Bus.snoop_filter +snoop_response_latency=1 +system=system +use_default_range=false +width=32 +master=system.cpu.l2cache.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side + +[system.cpu.toL2Bus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=0 +max_capacity=8388608 +system=system + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=LiveProcess +cmd=insttest +cwd= +drivers= +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable=/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64d/insttest +gid=100 +input=cin +kvmInSE=false +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=0 +system=system +uid=100 +useArchPT=false + +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000000 + +[system.membus] +type=CoherentXBar +children=snoop_filter +clk_domain=system.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +forward_latency=4 +frontend_latency=3 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +point_of_coherency=true +power_model=Null +response_latency=2 +snoop_filter=system.membus.snoop_filter +snoop_response_latency=4 +system=system +use_default_range=false +width=16 +master=system.physmem.port +slave=system.system_port system.cpu.l2cache.mem_side + +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + +[system.physmem] +type=SimpleMemory +bandwidth=73.000000 +clk_domain=system.clk_domain +conf_table_reported=true +default_p_state=UNDEFINED +eventq_index=0 +in_addr_map=true +kvm_map=true +latency=30000 +latency_var=0 +null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +range=0:134217727:0:0:0:0 +port=system.membus.master[0] + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-timing/config.json b/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-timing/config.json new file mode 100644 index 000000000..382338e98 --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-timing/config.json @@ -0,0 +1,508 @@ +{ + "name": null, + "sim_quantum": 0, + "system": { + "kernel": "", + "mmap_using_noreserve": false, + "kernel_addr_check": true, + "membus": { + "point_of_coherency": true, + "system": "system", + "response_latency": 2, + "cxx_class": "CoherentXBar", + "forward_latency": 4, + "clk_domain": "system.clk_domain", + "width": 16, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "master": { + "peer": [ + "system.physmem.port" + ], + "role": "MASTER" + }, + "type": "CoherentXBar", + "frontend_latency": 3, + "slave": { + "peer": [ + "system.system_port", + "system.cpu.l2cache.mem_side" + ], + "role": "SLAVE" + }, + "p_state_clk_gate_min": 1000, + "snoop_filter": { + "name": "snoop_filter", + "system": "system", + "max_capacity": 8388608, + "eventq_index": 0, + "cxx_class": "SnoopFilter", + "path": "system.membus.snoop_filter", + "type": "SnoopFilter", + "lookup_latency": 1 + }, + "power_model": null, + "path": "system.membus", + "snoop_response_latency": 4, + "name": "membus", + "p_state_clk_gate_bins": 20, + "use_default_range": false + }, + "symbolfile": "", + "readfile": "", + "thermal_model": null, + "cxx_class": "System", + "work_begin_cpu_id_exit": -1, + "load_offset": 0, + "work_begin_exit_count": 0, + "p_state_clk_gate_min": 1000, + "memories": [ + "system.physmem" + ], + "work_begin_ckpt_count": 0, + "clk_domain": { + "name": "clk_domain", + "clock": [ + 1000 + ], + "init_perf_level": 0, + "voltage_domain": "system.voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "mem_ranges": [], + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "dvfs_handler": { + "enable": false, + "name": "dvfs_handler", + "sys_clk_domain": "system.clk_domain", + "transition_latency": 100000000, + "eventq_index": 0, + "cxx_class": "DVFSHandler", + "domains": [], + "path": "system.dvfs_handler", + "type": "DVFSHandler" + }, + "work_end_exit_count": 0, + "type": "System", + "voltage_domain": { + "name": "voltage_domain", + "eventq_index": 0, + "voltage": [ + "1.0" + ], + "cxx_class": "VoltageDomain", + "path": "system.voltage_domain", + "type": "VoltageDomain" + }, + "cache_line_size": 64, + "boot_osflags": "a", + "system_port": { + "peer": "system.membus.slave[0]", + "role": "MASTER" + }, + "physmem": { + "range": "0:134217727:0:0:0:0", + "latency": 30000, + "name": "physmem", + "p_state_clk_gate_min": 1000, + "eventq_index": 0, + "p_state_clk_gate_bins": 20, + "default_p_state": "UNDEFINED", + "kvm_map": true, + "clk_domain": "system.clk_domain", + "power_model": null, + "latency_var": 0, + "bandwidth": "73.000000", + "conf_table_reported": true, + "cxx_class": "SimpleMemory", + "p_state_clk_gate_max": 1000000000000, + "path": "system.physmem", + "null": false, + "type": "SimpleMemory", + "port": { + "peer": "system.membus.master[0]", + "role": "SLAVE" + }, + "in_addr_map": true + }, + "power_model": null, + "work_cpus_ckpt_count": 0, + "thermal_components": [], + "path": "system", + "cpu_clk_domain": { + "name": "cpu_clk_domain", + "clock": [ + 500 + ], + "init_perf_level": 0, + "voltage_domain": "system.voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.cpu_clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "work_end_ckpt_count": 0, + "mem_mode": "timing", + "name": "system", + "init_param": 0, + "p_state_clk_gate_bins": 20, + "load_addr_mask": 1099511627775, + "cpu": [ + { + "do_statistics_insts": true, + "numThreads": 1, + "itb": { + "name": "itb", + "eventq_index": 0, + "cxx_class": "RiscvISA::TLB", + "path": "system.cpu.itb", + "type": "RiscvTLB", + "size": 64 + }, + "system": "system", + "icache": { + "cpu_side": { + "peer": "system.cpu.icache_port", + "role": "SLAVE" + }, + "clusivity": "mostly_incl", + "prefetcher": null, + "system": "system", + "write_buffers": 8, + "response_latency": 2, + "cxx_class": "Cache", + "size": 131072, + "type": "Cache", + "clk_domain": "system.cpu_clk_domain", + "max_miss_count": 0, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "mem_side": { + "peer": "system.cpu.toL2Bus.slave[0]", + "role": "MASTER" + }, + "mshrs": 4, + "writeback_clean": true, + "p_state_clk_gate_min": 1000, + "tags": { + "size": 131072, + "tag_latency": 2, + "name": "tags", + "p_state_clk_gate_min": 1000, + "eventq_index": 0, + "p_state_clk_gate_bins": 20, + "default_p_state": "UNDEFINED", + "clk_domain": "system.cpu_clk_domain", + "power_model": null, + "sequential_access": false, + "assoc": 2, + "cxx_class": "LRU", + "p_state_clk_gate_max": 1000000000000, + "path": "system.cpu.icache.tags", + "block_size": 64, + "type": "LRU", + "data_latency": 2 + }, + "tgts_per_mshr": 20, + "demand_mshr_reserve": 1, + "power_model": null, + "addr_ranges": [ + "0:18446744073709551615:0:0:0:0" + ], + "is_read_only": true, + "prefetch_on_access": false, + "path": "system.cpu.icache", + "data_latency": 2, + "tag_latency": 2, + "name": "icache", + "p_state_clk_gate_bins": 20, + "sequential_access": false, + "assoc": 2 + }, + "function_trace": false, + "do_checkpoint_insts": true, + "cxx_class": "TimingSimpleCPU", + "max_loads_all_threads": 0, + "clk_domain": "system.cpu_clk_domain", + "function_trace_start": 0, + "cpu_id": 0, + "checker": null, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "toL2Bus": { + "point_of_coherency": false, + "system": "system", + "response_latency": 1, + "cxx_class": "CoherentXBar", + "forward_latency": 0, + "clk_domain": "system.cpu_clk_domain", + "width": 32, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "master": { + "peer": [ + "system.cpu.l2cache.cpu_side" + ], + "role": "MASTER" + }, + "type": "CoherentXBar", + "frontend_latency": 1, + "slave": { + "peer": [ + "system.cpu.icache.mem_side", + "system.cpu.dcache.mem_side" + ], + "role": "SLAVE" + }, + "p_state_clk_gate_min": 1000, + "snoop_filter": { + "name": "snoop_filter", + "system": "system", + "max_capacity": 8388608, + "eventq_index": 0, + "cxx_class": "SnoopFilter", + "path": "system.cpu.toL2Bus.snoop_filter", + "type": "SnoopFilter", + "lookup_latency": 0 + }, + "power_model": null, + "path": "system.cpu.toL2Bus", + "snoop_response_latency": 1, + "name": "toL2Bus", + "p_state_clk_gate_bins": 20, + "use_default_range": false + }, + "do_quiesce": true, + "type": "TimingSimpleCPU", + "profile": 0, + "icache_port": { + "peer": "system.cpu.icache.cpu_side", + "role": "MASTER" + }, + "p_state_clk_gate_bins": 20, + "p_state_clk_gate_min": 1000, + "interrupts": [ + { + "eventq_index": 0, + "path": "system.cpu.interrupts", + "type": "RiscvInterrupts", + "name": "interrupts", + "cxx_class": "RiscvISA::Interrupts" + } + ], + "dcache_port": { + "peer": "system.cpu.dcache.cpu_side", + "role": "MASTER" + }, + "socket_id": 0, + "power_model": null, + "max_insts_all_threads": 0, + "l2cache": { + "cpu_side": { + "peer": "system.cpu.toL2Bus.master[0]", + "role": "SLAVE" + }, + "clusivity": "mostly_incl", + "prefetcher": null, + "system": "system", + "write_buffers": 8, + "response_latency": 20, + "cxx_class": "Cache", + "size": 2097152, + "type": "Cache", + "clk_domain": "system.cpu_clk_domain", + "max_miss_count": 0, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "mem_side": { + "peer": "system.membus.slave[1]", + "role": "MASTER" + }, + "mshrs": 20, + "writeback_clean": false, + "p_state_clk_gate_min": 1000, + "tags": { + "size": 2097152, + "tag_latency": 20, + "name": "tags", + "p_state_clk_gate_min": 1000, + "eventq_index": 0, + "p_state_clk_gate_bins": 20, + "default_p_state": "UNDEFINED", + "clk_domain": "system.cpu_clk_domain", + "power_model": null, + "sequential_access": false, + "assoc": 8, + "cxx_class": "LRU", + "p_state_clk_gate_max": 1000000000000, + "path": "system.cpu.l2cache.tags", + "block_size": 64, + "type": "LRU", + "data_latency": 20 + }, + "tgts_per_mshr": 12, + "demand_mshr_reserve": 1, + "power_model": null, + "addr_ranges": [ + "0:18446744073709551615:0:0:0:0" + ], + "is_read_only": false, + "prefetch_on_access": false, + "path": "system.cpu.l2cache", + "data_latency": 20, + "tag_latency": 20, + "name": "l2cache", + "p_state_clk_gate_bins": 20, + "sequential_access": false, + "assoc": 8 + }, + "path": "system.cpu", + "max_loads_any_thread": 0, + "switched_out": false, + "workload": [ + { + "uid": 100, + "pid": 100, + "kvmInSE": false, + "cxx_class": "LiveProcess", + "executable": "/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64d/insttest", + "drivers": [], + "system": "system", + "gid": 100, + "eventq_index": 0, + "env": [], + "input": "cin", + "ppid": 99, + "type": "LiveProcess", + "cwd": "", + "simpoint": 0, + "euid": 100, + "path": "system.cpu.workload", + "max_stack_size": 67108864, + "name": "workload", + "cmd": [ + "insttest" + ], + "errout": "cerr", + "useArchPT": false, + "egid": 100, + "output": "cout" + } + ], + "name": "cpu", + "dtb": { + "name": "dtb", + "eventq_index": 0, + "cxx_class": "RiscvISA::TLB", + "path": "system.cpu.dtb", + "type": "RiscvTLB", + "size": 64 + }, + "simpoint_start_insts": [], + "max_insts_any_thread": 0, + "progress_interval": 0, + "branchPred": null, + "dcache": { + "cpu_side": { + "peer": "system.cpu.dcache_port", + "role": "SLAVE" + }, + "clusivity": "mostly_incl", + "prefetcher": null, + "system": "system", + "write_buffers": 8, + "response_latency": 2, + "cxx_class": "Cache", + "size": 262144, + "type": "Cache", + "clk_domain": "system.cpu_clk_domain", + "max_miss_count": 0, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "mem_side": { + "peer": "system.cpu.toL2Bus.slave[1]", + "role": "MASTER" + }, + "mshrs": 4, + "writeback_clean": false, + "p_state_clk_gate_min": 1000, + "tags": { + "size": 262144, + "tag_latency": 2, + "name": "tags", + "p_state_clk_gate_min": 1000, + "eventq_index": 0, + "p_state_clk_gate_bins": 20, + "default_p_state": "UNDEFINED", + "clk_domain": "system.cpu_clk_domain", + "power_model": null, + "sequential_access": false, + "assoc": 2, + "cxx_class": "LRU", + "p_state_clk_gate_max": 1000000000000, + "path": "system.cpu.dcache.tags", + "block_size": 64, + "type": "LRU", + "data_latency": 2 + }, + "tgts_per_mshr": 20, + "demand_mshr_reserve": 1, + "power_model": null, + "addr_ranges": [ + "0:18446744073709551615:0:0:0:0" + ], + "is_read_only": false, + "prefetch_on_access": false, + "path": "system.cpu.dcache", + "data_latency": 2, + "tag_latency": 2, + "name": "dcache", + "p_state_clk_gate_bins": 20, + "sequential_access": false, + "assoc": 2 + }, + "isa": [ + { + "eventq_index": 0, + "path": "system.cpu.isa", + "type": "RiscvISA", + "name": "isa", + "cxx_class": "RiscvISA::ISA" + } + ], + "tracer": { + "eventq_index": 0, + "path": "system.cpu.tracer", + "type": "ExeTracer", + "name": "tracer", + "cxx_class": "Trace::ExeTracer" + } + } + ], + "multi_thread": false, + "exit_on_work_items": false, + "work_item_id": -1, + "num_work_ids": 16 + }, + "time_sync_period": 100000000000, + "eventq_index": 0, + "time_sync_spin_threshold": 100000000, + "cxx_class": "Root", + "path": "root", + "time_sync_enable": false, + "type": "Root", + "full_system": false +}
\ No newline at end of file diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-timing/simerr b/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-timing/simerr new file mode 100755 index 000000000..fd133b12b --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-timing/simerr @@ -0,0 +1,3 @@ +warn: Unknown operating system; assuming Linux. +warn: Sockets disabled, not accepting gdb connections +warn: ClockedObject: More than one power state change request encountered within the same simulation tick diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-timing/simout b/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-timing/simout new file mode 100755 index 000000000..709d5c6f6 --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-timing/simout @@ -0,0 +1,168 @@ +Redirecting stdout to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64d/simple-timing/simout +Redirecting stderr to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64d/simple-timing/simerr +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled Nov 30 2016 14:33:35 +gem5 started Nov 30 2016 16:18:31 +gem5 executing on zizzer, pid 34073 +command line: /z/powerjg/gem5-upstream/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64d/simple-timing -re /z/powerjg/gem5-upstream/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64d/simple-timing + +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. +fld: PASS +fsd: PASS +fmadd.d: PASS +fmadd.d, quiet NaN: PASS +fmadd.d, signaling NaN: PASS +fmadd.d, infinity: PASS +fmadd.d, -infinity: PASS +fmsub.d: PASS +fmsub.d, quiet NaN: PASS +fmsub.d, signaling NaN: PASS +fmsub.d, infinity: PASS +fmsub.d, -infinity: PASS +fmsub.d, subtract infinity: PASS +fnmsub.d: PASS +fnmsub.d, quiet NaN: PASS +fnmsub.d, signaling NaN: PASS +fnmsub.d, infinity: PASS +fnmsub.d, -infinity: PASS +fnmsub.d, subtract infinity: PASS +fnmadd.d: PASS +fnmadd.d, quiet NaN: PASS +fnmadd.d, signaling NaN: PASS +fnmadd.d, infinity: PASS +fnmadd.d, -infinity: PASS +fadd.d: PASS +fadd.d, quiet NaN: PASS +fadd.d, signaling NaN: PASS +fadd.d, infinity: PASS +fadd.d, -infinity: PASS +fsub.d: PASS +fsub.d, quiet NaN: PASS +fsub.d, signaling NaN: PASS +fsub.d, infinity: PASS +fsub.d, -infinity: PASS +fsub.d, subtract infinity: PASS +fmul.d: PASS +fmul.d, quiet NaN: PASS +fmul.d, signaling NaN: PASS +fmul.d, infinity: PASS +fmul.d, -infinity: PASS +fmul.d, 0*infinity: PASS +fmul.d, overflow: PASS +fmul.d, underflow: PASS +fdiv.d: PASS +fdiv.d, quiet NaN: PASS +fdiv.d, signaling NaN: PASS +fdiv.d/0: PASS +fdiv.d/infinity: PASS +fdiv.d, infinity/infinity: PASS +fdiv.d, 0/0: PASS +fdiv.d, infinity/0: PASS +fdiv.d, 0/infinity: PASS +fdiv.d, underflow: PASS +fdiv.d, overflow: PASS +fsqrt.d: PASS +fsqrt.d, NaN: PASS +fsqrt.d, quiet NaN: PASS +fsqrt.d, signaling NaN: PASS +fsqrt.d, infinity: PASS +fsgnj.d, ++: PASS +fsgnj.d, +-: PASS +fsgnj.d, -+: PASS +fsgnj.d, --: PASS +fsgnj.d, quiet NaN: PASS +fsgnj.d, signaling NaN: PASS +fsgnj.d, inject NaN: PASS +fsgnj.d, inject -NaN: PASS +fsgnjn.d, ++: PASS +fsgnjn.d, +-: PASS +fsgnjn.d, -+: PASS +fsgnjn.d, --: PASS +fsgnjn.d, quiet NaN: PASS +fsgnjn.d, signaling NaN: PASS +fsgnjn.d, inject NaN: PASS +fsgnjn.d, inject NaN: PASS +fsgnjx.d, ++: PASS +fsgnjx.d, +-: PASS +fsgnjx.d, -+: PASS +fsgnjx.d, --: PASS +fsgnjx.d, quiet NaN: PASS +fsgnjx.d, signaling NaN: PASS +fsgnjx.d, inject NaN: PASS +fsgnjx.d, inject NaN: PASS +fmin.d: PASS +fmin.d, -infinity: PASS +fmin.d, infinity: PASS +fmin.d, quiet NaN first: PASS +fmin.d, quiet NaN second: PASS +fmin.d, quiet NaN both: PASS +fmin.d, signaling NaN first: PASS +fmin.d, signaling NaN second: PASS +fmin.d, signaling NaN both: PASS +fmax.d: PASS +fmax.d, -infinity: PASS +fmax.d, infinity: PASS +fmax.d, quiet NaN first: PASS +fmax.d, quiet NaN second: PASS +fmax.d, quiet NaN both: PASS +fmax.d, signaling NaN first: PASS +fmax.d, signaling NaN second: PASS +fmax.d, signaling NaN both: PASS +fcvt.s.d: PASS +fcvt.s.d, quiet NaN: PASS +fcvt.s.d, signaling NaN: PASS +fcvt.s.d, infinity: PASS +fcvt.s.d, overflow: PASS +fcvt.s.d, underflow: PASS +fcvt.d.s: PASS +fcvt.d.s, quiet NaN: PASS +fcvt.d.s, signaling NaN: PASS +fcvt.d.s, infinity: PASS +feq.d, equal: PASS +feq.d, not equal: PASS +feq.d, 0 == -0: PASS +feq.d, quiet NaN first: PASS +feq.d, quiet NaN second: PASS +feq.d, quiet NaN both: PASS +feq.d, signaling NaN first: PASS +feq.d, signaling NaN second: PASS +feq.d, signaling NaN both: PASS +flt.d, equal: PASS +flt.d, less: PASS +flt.d, greater: PASS +flt.d, quiet NaN first: PASS +flt.d, quiet NaN second: PASS +flt.d, quiet NaN both: PASS +flt.d, signaling NaN first: PASS +flt.d, signaling NaN second: PASS +flt.d, signaling NaN both: PASS +fle.d, equal: PASS +fle.d, less: PASS +fle.d, greater: PASS +fle.d, 0 == -0: PASS +fle.d, quiet NaN first: PASS +fle.d, quiet NaN second: PASS +fle.d, quiet NaN both: PASS +fle.d, signaling NaN first: PASS +fle.d, signaling NaN second: PASS +fle.d, signaling NaN both: PASS +fclass.d, -infinity: PASS +fclass.d, -normal: PASS +fclass.d, -subnormal: PASS +fclass.d, -0.0: PASS +fclass.d, 0.0: PASS +fclass.d, subnormal: PASS +fclass.d, normal: PASS +fclass.d, infinity: PASS +fclass.d, signaling NaN: PASS +fclass.s, quiet NaN: PASS +fcvt.w.d, truncate positive: PASS +fcvt.w.d, truncate negative: PASS +fcvt.w.d, 0.0: PASS +fcvt.w.d, -0.0: PASS +fcvt.w.d, overflow: [1;31mFAIL[0m (expected 2147483647; found -2147483648) +Exiting @ tick 497165500 because target called exit() diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-timing/stats.txt b/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-timing/stats.txt new file mode 100644 index 000000000..13b031fa9 --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-timing/stats.txt @@ -0,0 +1,515 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.000497 # Number of seconds simulated +sim_ticks 497165500 # Number of ticks simulated +final_tick 497165500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 27513 # Simulator instruction rate (inst/s) +host_op_rate 27513 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 45717681 # Simulator tick rate (ticks/s) +host_mem_usage 243824 # Number of bytes of host memory used +host_seconds 10.87 # Real time elapsed on the host +sim_insts 299191 # Number of instructions simulated +sim_ops 299191 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 497165500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 61760 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 20224 # Number of bytes read from this memory +system.physmem.bytes_read::total 81984 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 61760 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 61760 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 965 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 316 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1281 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 124224227 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 40678607 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 164902834 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 124224227 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 124224227 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 124224227 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 40678607 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 164902834 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 497165500 # Cumulative time (in ticks) in various power states +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 162 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 497165500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 994331 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 299191 # Number of instructions committed +system.cpu.committedOps 299191 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 299008 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 1025 # Number of float alu accesses +system.cpu.num_func_calls 21816 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 44561 # number of instructions that are conditional controls +system.cpu.num_int_insts 299008 # number of integer instructions +system.cpu.num_fp_insts 1025 # number of float instructions +system.cpu.num_int_register_reads 394163 # number of times the integer registers were read +system.cpu.num_int_register_writes 205779 # number of times the integer registers were written +system.cpu.num_fp_register_reads 851 # number of times the floating registers were read +system.cpu.num_fp_register_writes 688 # number of times the floating registers were written +system.cpu.num_mem_refs 118390 # number of memory refs +system.cpu.num_load_insts 69843 # Number of load instructions +system.cpu.num_store_insts 48547 # Number of store instructions +system.cpu.num_idle_cycles 0 # Number of idle cycles +system.cpu.num_busy_cycles 994331 # Number of busy cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.Branches 66377 # Number of branches fetched +system.cpu.op_class::No_OpClass 162 0.05% 0.05% # Class of executed instruction +system.cpu.op_class::IntAlu 179913 60.10% 60.15% # Class of executed instruction +system.cpu.op_class::IntMult 466 0.16% 60.31% # Class of executed instruction +system.cpu.op_class::IntDiv 40 0.01% 60.32% # Class of executed instruction +system.cpu.op_class::FloatAdd 120 0.04% 60.36% # Class of executed instruction +system.cpu.op_class::FloatCmp 157 0.05% 60.42% # Class of executed instruction +system.cpu.op_class::FloatCvt 60 0.02% 60.44% # Class of executed instruction +system.cpu.op_class::FloatMult 30 0.01% 60.45% # Class of executed instruction +system.cpu.op_class::FloatMultAcc 0 0.00% 60.45% # Class of executed instruction +system.cpu.op_class::FloatDiv 11 0.00% 60.45% # Class of executed instruction +system.cpu.op_class::FloatMisc 0 0.00% 60.45% # Class of executed instruction +system.cpu.op_class::FloatSqrt 5 0.00% 60.45% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 60.45% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 60.45% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 60.45% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 60.45% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 60.45% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 60.45% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 60.45% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 60.45% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 60.45% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 60.45% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 60.45% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 60.45% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 60.45% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 60.45% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 60.45% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 60.45% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 60.45% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 60.45% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 60.45% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 60.45% # Class of executed instruction +system.cpu.op_class::MemRead 69348 23.17% 83.62% # Class of executed instruction +system.cpu.op_class::MemWrite 48400 16.17% 99.79% # Class of executed instruction +system.cpu.op_class::FloatMemRead 495 0.17% 99.95% # Class of executed instruction +system.cpu.op_class::FloatMemWrite 147 0.05% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 299354 # Class of executed instruction +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 497165500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 0 # number of replacements +system.cpu.dcache.tags.tagsinuse 258.453748 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 118073 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 316 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 373.648734 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 258.453748 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.063099 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.063099 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 316 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 5 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 15 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 296 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.077148 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 237094 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 237094 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 497165500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 69732 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 69732 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 48341 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 48341 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 118073 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 118073 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 118073 # number of overall hits +system.cpu.dcache.overall_hits::total 118073 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 111 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 111 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 205 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 205 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 316 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 316 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 316 # number of overall misses +system.cpu.dcache.overall_misses::total 316 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 6993000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 6993000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 12915000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 12915000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 19908000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 19908000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 19908000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 19908000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 69843 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 69843 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 48546 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 48546 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 118389 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 118389 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 118389 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 118389 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.001589 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.001589 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.004223 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.004223 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.002669 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.002669 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.002669 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.002669 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63000 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 63000 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 63000 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 63000 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 63000 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 63000 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 63000 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 111 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 111 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 205 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 205 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 316 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 316 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 316 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 316 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6882000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 6882000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12710000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 12710000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 19592000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 19592000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 19592000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 19592000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001589 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001589 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.004223 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.004223 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002669 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.002669 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002669 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.002669 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 62000 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 62000 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 62000 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 62000 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 62000 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 62000 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 62000 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 62000 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 497165500 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 26 # number of replacements +system.cpu.icache.tags.tagsinuse 551.353598 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 298390 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 965 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 309.212435 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 551.353598 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.269216 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.269216 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 939 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 61 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 104 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 774 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.458496 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 599675 # Number of tag accesses +system.cpu.icache.tags.data_accesses 599675 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 497165500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 298390 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 298390 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 298390 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 298390 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 298390 # number of overall hits +system.cpu.icache.overall_hits::total 298390 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 965 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 965 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 965 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 965 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 965 # number of overall misses +system.cpu.icache.overall_misses::total 965 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 60795500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 60795500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 60795500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 60795500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 60795500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 60795500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 299355 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 299355 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 299355 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 299355 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 299355 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 299355 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.003224 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.003224 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.003224 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.003224 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.003224 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.003224 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 63000.518135 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 63000.518135 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 63000.518135 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 63000.518135 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 63000.518135 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 63000.518135 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.icache.writebacks::writebacks 26 # number of writebacks +system.cpu.icache.writebacks::total 26 # number of writebacks +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 965 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 965 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 965 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 965 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 965 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 965 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 59830500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 59830500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 59830500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 59830500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 59830500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 59830500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.003224 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.003224 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.003224 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.003224 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.003224 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.003224 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 62000.518135 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 62000.518135 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 62000.518135 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 62000.518135 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 62000.518135 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 62000.518135 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 497165500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.replacements 0 # number of replacements +system.cpu.l2cache.tags.tagsinuse 821.156872 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 26 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 1281 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.020297 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::cpu.inst 562.696450 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 258.460422 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.017172 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.007888 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.025060 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 1281 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 66 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 119 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1096 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.039093 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 11737 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 11737 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 497165500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.WritebackClean_hits::writebacks 26 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 26 # number of WritebackClean hits +system.cpu.l2cache.ReadExReq_misses::cpu.data 205 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 205 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 965 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 965 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 111 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 111 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.inst 965 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 316 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 1281 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 965 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 316 # number of overall misses +system.cpu.l2cache.overall_misses::total 1281 # number of overall misses +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 12402500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 12402500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 58383000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 58383000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 6715500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 6715500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 58383000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 19118000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 77501000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 58383000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 19118000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 77501000 # number of overall miss cycles +system.cpu.l2cache.WritebackClean_accesses::writebacks 26 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 26 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 205 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 205 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 965 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 965 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 111 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 111 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 965 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 316 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 1281 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 965 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 316 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 1281 # number of overall (read+write) accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 1 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 1 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 1 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 1 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60500 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60500 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60500.518135 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60500.518135 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60500 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60500 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60500.518135 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60500 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 60500.390320 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60500.518135 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60500 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 60500.390320 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 205 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 205 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 965 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 965 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 111 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 111 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 965 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 316 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 1281 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 965 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 316 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 1281 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 10352500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 10352500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 48733000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 48733000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 5605500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 5605500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 48733000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 15958000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 64691000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 48733000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 15958000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 64691000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 1 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50500.518135 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50500.518135 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50500.518135 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50500.390320 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50500.518135 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50500.390320 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 1307 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 26 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 497165500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 1076 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 26 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 205 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 205 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 965 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 111 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1956 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 632 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 2588 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 63424 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 20224 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 83648 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 1281 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 1281 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 1281 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 679500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 1447500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.3 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 474000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) +system.membus.snoop_filter.tot_requests 1281 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 497165500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 1076 # Transaction distribution +system.membus.trans_dist::ReadExReq 205 # Transaction distribution +system.membus.trans_dist::ReadExResp 205 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 1076 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 2562 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 2562 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 81984 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 81984 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoopTraffic 0 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 1281 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 1281 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 1281 # Request fanout histogram +system.membus.reqLayer0.occupancy 1281500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.3 # Layer utilization (%) +system.membus.respLayer1.occupancy 6405000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 1.3 # Layer utilization (%) + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/minor-timing/config.ini b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/minor-timing/config.ini new file mode 100644 index 000000000..4631a10f3 --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/minor-timing/config.ini @@ -0,0 +1,902 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain +boot_osflags=a +cache_line_size=64 +clk_domain=system.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +exit_on_work_items=false +init_param=0 +kernel= +kernel_addr_check=true +load_addr_mask=1099511627775 +load_offset=0 +mem_mode=timing +mem_ranges= +memories=system.physmem +mmap_using_noreserve=false +multi_thread=false +num_work_ids=16 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +readfile= +symbolfile= +thermal_components= +thermal_model=Null +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=MinorCPU +children=branchPred dcache dtb executeFuncUnits icache interrupts isa itb l2cache toL2Bus tracer workload +branchPred=system.cpu.branchPred +checker=Null +clk_domain=system.cpu_clk_domain +cpu_id=0 +decodeCycleInput=true +decodeInputBufferSize=3 +decodeInputWidth=2 +decodeToExecuteForwardDelay=1 +default_p_state=UNDEFINED +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +enableIdling=true +eventq_index=0 +executeAllowEarlyMemoryIssue=true +executeBranchDelay=1 +executeCommitLimit=2 +executeCycleInput=true +executeFuncUnits=system.cpu.executeFuncUnits +executeInputBufferSize=7 +executeInputWidth=2 +executeIssueLimit=2 +executeLSQMaxStoreBufferStoresPerCycle=2 +executeLSQRequestsQueueSize=1 +executeLSQStoreBufferSize=5 +executeLSQTransfersQueueSize=2 +executeMaxAccessesInMemory=2 +executeMemoryCommitLimit=1 +executeMemoryIssueLimit=1 +executeMemoryWidth=0 +executeSetTraceTimeOnCommit=true +executeSetTraceTimeOnIssue=false +fetch1FetchLimit=1 +fetch1LineSnapWidth=0 +fetch1LineWidth=0 +fetch1ToFetch2BackwardDelay=1 +fetch1ToFetch2ForwardDelay=1 +fetch2CycleInput=true +fetch2InputBufferSize=2 +fetch2ToDecodeForwardDelay=1 +function_trace=false +function_trace_start=0 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +profile=0 +progress_interval=0 +simpoint_start_insts= +socket_id=0 +switched_out=false +system=system +threadPolicy=RoundRobin +tracer=system.cpu.tracer +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.branchPred] +type=TournamentBP +BTBEntries=4096 +BTBTagSize=16 +RASSize=16 +choiceCtrBits=2 +choicePredictorSize=8192 +eventq_index=0 +globalCtrBits=2 +globalPredictorSize=8192 +indirectHashGHR=true +indirectHashTargets=true +indirectPathLength=3 +indirectSets=256 +indirectTagSize=16 +indirectWays=2 +instShiftAmt=2 +localCtrBits=2 +localHistoryTableSize=2048 +localPredictorSize=2048 +numThreads=1 +useIndirect=true + +[system.cpu.dcache] +type=Cache +children=tags +addr_ranges=0:18446744073709551615:0:0:0:0 +assoc=2 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +data_latency=2 +default_p_state=UNDEFINED +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=4 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=262144 +system=system +tag_latency=2 +tags=system.cpu.dcache.tags +tgts_per_mshr=20 +write_buffers=8 +writeback_clean=false +cpu_side=system.cpu.dcache_port +mem_side=system.cpu.toL2Bus.slave[1] + +[system.cpu.dcache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +data_latency=2 +default_p_state=UNDEFINED +eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +sequential_access=false +size=262144 +tag_latency=2 + +[system.cpu.dtb] +type=RiscvTLB +eventq_index=0 +size=64 + +[system.cpu.executeFuncUnits] +type=MinorFUPool +children=funcUnits0 funcUnits1 funcUnits2 funcUnits3 funcUnits4 funcUnits5 funcUnits6 +eventq_index=0 +funcUnits=system.cpu.executeFuncUnits.funcUnits0 system.cpu.executeFuncUnits.funcUnits1 system.cpu.executeFuncUnits.funcUnits2 system.cpu.executeFuncUnits.funcUnits3 system.cpu.executeFuncUnits.funcUnits4 system.cpu.executeFuncUnits.funcUnits5 system.cpu.executeFuncUnits.funcUnits6 + +[system.cpu.executeFuncUnits.funcUnits0] +type=MinorFU +children=opClasses timings +cantForwardFromFUIndices= +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses +opLat=3 +timings=system.cpu.executeFuncUnits.funcUnits0.timings + +[system.cpu.executeFuncUnits.funcUnits0.opClasses] +type=MinorOpClassSet +children=opClasses +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses + +[system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses] +type=MinorOpClass +eventq_index=0 +opClass=IntAlu + +[system.cpu.executeFuncUnits.funcUnits0.timings] +type=MinorFUTiming +children=opClasses +description=Int +eventq_index=0 +extraAssumedLat=0 +extraCommitLat=0 +extraCommitLatExpr=Null +mask=0 +match=0 +opClasses=system.cpu.executeFuncUnits.funcUnits0.timings.opClasses +srcRegsRelativeLats=2 +suppress=false + +[system.cpu.executeFuncUnits.funcUnits0.timings.opClasses] +type=MinorOpClassSet +eventq_index=0 +opClasses= + +[system.cpu.executeFuncUnits.funcUnits1] +type=MinorFU +children=opClasses timings +cantForwardFromFUIndices= +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses +opLat=3 +timings=system.cpu.executeFuncUnits.funcUnits1.timings + +[system.cpu.executeFuncUnits.funcUnits1.opClasses] +type=MinorOpClassSet +children=opClasses +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses + +[system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses] +type=MinorOpClass +eventq_index=0 +opClass=IntAlu + +[system.cpu.executeFuncUnits.funcUnits1.timings] +type=MinorFUTiming +children=opClasses +description=Int +eventq_index=0 +extraAssumedLat=0 +extraCommitLat=0 +extraCommitLatExpr=Null +mask=0 +match=0 +opClasses=system.cpu.executeFuncUnits.funcUnits1.timings.opClasses +srcRegsRelativeLats=2 +suppress=false + +[system.cpu.executeFuncUnits.funcUnits1.timings.opClasses] +type=MinorOpClassSet +eventq_index=0 +opClasses= + +[system.cpu.executeFuncUnits.funcUnits2] +type=MinorFU +children=opClasses timings +cantForwardFromFUIndices= +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits2.opClasses +opLat=3 +timings=system.cpu.executeFuncUnits.funcUnits2.timings + +[system.cpu.executeFuncUnits.funcUnits2.opClasses] +type=MinorOpClassSet +children=opClasses +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses + +[system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses] +type=MinorOpClass +eventq_index=0 +opClass=IntMult + +[system.cpu.executeFuncUnits.funcUnits2.timings] +type=MinorFUTiming +children=opClasses +description=Mul +eventq_index=0 +extraAssumedLat=0 +extraCommitLat=0 +extraCommitLatExpr=Null +mask=0 +match=0 +opClasses=system.cpu.executeFuncUnits.funcUnits2.timings.opClasses +srcRegsRelativeLats=0 +suppress=false + +[system.cpu.executeFuncUnits.funcUnits2.timings.opClasses] +type=MinorOpClassSet +eventq_index=0 +opClasses= + +[system.cpu.executeFuncUnits.funcUnits3] +type=MinorFU +children=opClasses +cantForwardFromFUIndices= +eventq_index=0 +issueLat=9 +opClasses=system.cpu.executeFuncUnits.funcUnits3.opClasses +opLat=9 +timings= + +[system.cpu.executeFuncUnits.funcUnits3.opClasses] +type=MinorOpClassSet +children=opClasses +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses + +[system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses] +type=MinorOpClass +eventq_index=0 +opClass=IntDiv + +[system.cpu.executeFuncUnits.funcUnits4] +type=MinorFU +children=opClasses timings +cantForwardFromFUIndices= +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses +opLat=6 +timings=system.cpu.executeFuncUnits.funcUnits4.timings + +[system.cpu.executeFuncUnits.funcUnits4.opClasses] +type=MinorOpClassSet +children=opClasses00 opClasses01 opClasses02 opClasses03 opClasses04 opClasses05 opClasses06 opClasses07 opClasses08 opClasses09 opClasses10 opClasses11 opClasses12 opClasses13 opClasses14 opClasses15 opClasses16 opClasses17 opClasses18 opClasses19 opClasses20 opClasses21 opClasses22 opClasses23 opClasses24 opClasses25 opClasses26 opClasses27 +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses26 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses27 + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00] +type=MinorOpClass +eventq_index=0 +opClass=FloatAdd + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01] +type=MinorOpClass +eventq_index=0 +opClass=FloatCmp + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02] +type=MinorOpClass +eventq_index=0 +opClass=FloatCvt + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03] +type=MinorOpClass +eventq_index=0 +opClass=FloatMisc + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04] +type=MinorOpClass +eventq_index=0 +opClass=FloatMult + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05] +type=MinorOpClass +eventq_index=0 +opClass=FloatMultAcc + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06] +type=MinorOpClass +eventq_index=0 +opClass=FloatDiv + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07] +type=MinorOpClass +eventq_index=0 +opClass=FloatSqrt + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08] +type=MinorOpClass +eventq_index=0 +opClass=SimdAdd + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09] +type=MinorOpClass +eventq_index=0 +opClass=SimdAddAcc + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10] +type=MinorOpClass +eventq_index=0 +opClass=SimdAlu + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11] +type=MinorOpClass +eventq_index=0 +opClass=SimdCmp + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12] +type=MinorOpClass +eventq_index=0 +opClass=SimdCvt + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13] +type=MinorOpClass +eventq_index=0 +opClass=SimdMisc + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14] +type=MinorOpClass +eventq_index=0 +opClass=SimdMult + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15] +type=MinorOpClass +eventq_index=0 +opClass=SimdMultAcc + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16] +type=MinorOpClass +eventq_index=0 +opClass=SimdShift + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17] +type=MinorOpClass +eventq_index=0 +opClass=SimdShiftAcc + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18] +type=MinorOpClass +eventq_index=0 +opClass=SimdSqrt + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatAdd + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatAlu + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatCmp + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatCvt + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatDiv + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatMisc + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatMult + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses26] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatMultAcc + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses27] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatSqrt + +[system.cpu.executeFuncUnits.funcUnits4.timings] +type=MinorFUTiming +children=opClasses +description=FloatSimd +eventq_index=0 +extraAssumedLat=0 +extraCommitLat=0 +extraCommitLatExpr=Null +mask=0 +match=0 +opClasses=system.cpu.executeFuncUnits.funcUnits4.timings.opClasses +srcRegsRelativeLats=2 +suppress=false + +[system.cpu.executeFuncUnits.funcUnits4.timings.opClasses] +type=MinorOpClassSet +eventq_index=0 +opClasses= + +[system.cpu.executeFuncUnits.funcUnits5] +type=MinorFU +children=opClasses timings +cantForwardFromFUIndices= +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses +opLat=1 +timings=system.cpu.executeFuncUnits.funcUnits5.timings + +[system.cpu.executeFuncUnits.funcUnits5.opClasses] +type=MinorOpClassSet +children=opClasses0 opClasses1 opClasses2 opClasses3 +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1 system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses2 system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses3 + +[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0] +type=MinorOpClass +eventq_index=0 +opClass=MemRead + +[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1] +type=MinorOpClass +eventq_index=0 +opClass=MemWrite + +[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses2] +type=MinorOpClass +eventq_index=0 +opClass=FloatMemRead + +[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses3] +type=MinorOpClass +eventq_index=0 +opClass=FloatMemWrite + +[system.cpu.executeFuncUnits.funcUnits5.timings] +type=MinorFUTiming +children=opClasses +description=Mem +eventq_index=0 +extraAssumedLat=2 +extraCommitLat=0 +extraCommitLatExpr=Null +mask=0 +match=0 +opClasses=system.cpu.executeFuncUnits.funcUnits5.timings.opClasses +srcRegsRelativeLats=1 +suppress=false + +[system.cpu.executeFuncUnits.funcUnits5.timings.opClasses] +type=MinorOpClassSet +eventq_index=0 +opClasses= + +[system.cpu.executeFuncUnits.funcUnits6] +type=MinorFU +children=opClasses +cantForwardFromFUIndices= +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses +opLat=1 +timings= + +[system.cpu.executeFuncUnits.funcUnits6.opClasses] +type=MinorOpClassSet +children=opClasses0 opClasses1 +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1 + +[system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0] +type=MinorOpClass +eventq_index=0 +opClass=IprAccess + +[system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1] +type=MinorOpClass +eventq_index=0 +opClass=InstPrefetch + +[system.cpu.icache] +type=Cache +children=tags +addr_ranges=0:18446744073709551615:0:0:0:0 +assoc=2 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +data_latency=2 +default_p_state=UNDEFINED +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=true +max_miss_count=0 +mshrs=4 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=131072 +system=system +tag_latency=2 +tags=system.cpu.icache.tags +tgts_per_mshr=20 +write_buffers=8 +writeback_clean=true +cpu_side=system.cpu.icache_port +mem_side=system.cpu.toL2Bus.slave[0] + +[system.cpu.icache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +data_latency=2 +default_p_state=UNDEFINED +eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +sequential_access=false +size=131072 +tag_latency=2 + +[system.cpu.interrupts] +type=RiscvInterrupts +eventq_index=0 + +[system.cpu.isa] +type=RiscvISA +eventq_index=0 + +[system.cpu.itb] +type=RiscvTLB +eventq_index=0 +size=64 + +[system.cpu.l2cache] +type=Cache +children=tags +addr_ranges=0:18446744073709551615:0:0:0:0 +assoc=8 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +data_latency=20 +default_p_state=UNDEFINED +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=20 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +prefetch_on_access=false +prefetcher=Null +response_latency=20 +sequential_access=false +size=2097152 +system=system +tag_latency=20 +tags=system.cpu.l2cache.tags +tgts_per_mshr=12 +write_buffers=8 +writeback_clean=false +cpu_side=system.cpu.toL2Bus.master[0] +mem_side=system.membus.slave[1] + +[system.cpu.l2cache.tags] +type=LRU +assoc=8 +block_size=64 +clk_domain=system.cpu_clk_domain +data_latency=20 +default_p_state=UNDEFINED +eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +sequential_access=false +size=2097152 +tag_latency=20 + +[system.cpu.toL2Bus] +type=CoherentXBar +children=snoop_filter +clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED +eventq_index=0 +forward_latency=0 +frontend_latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +point_of_coherency=false +power_model=Null +response_latency=1 +snoop_filter=system.cpu.toL2Bus.snoop_filter +snoop_response_latency=1 +system=system +use_default_range=false +width=32 +master=system.cpu.l2cache.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side + +[system.cpu.toL2Bus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=0 +max_capacity=8388608 +system=system + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=LiveProcess +cmd=insttest +cwd= +drivers= +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable=/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64f/insttest +gid=100 +input=cin +kvmInSE=false +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=0 +system=system +uid=100 +useArchPT=false + +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000000 + +[system.membus] +type=CoherentXBar +children=snoop_filter +clk_domain=system.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +forward_latency=4 +frontend_latency=3 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +point_of_coherency=true +power_model=Null +response_latency=2 +snoop_filter=system.membus.snoop_filter +snoop_response_latency=4 +system=system +use_default_range=false +width=16 +master=system.physmem.port +slave=system.system_port system.cpu.l2cache.mem_side + +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + +[system.physmem] +type=DRAMCtrl +IDD0=0.055000 +IDD02=0.000000 +IDD2N=0.032000 +IDD2N2=0.000000 +IDD2P0=0.000000 +IDD2P02=0.000000 +IDD2P1=0.032000 +IDD2P12=0.000000 +IDD3N=0.038000 +IDD3N2=0.000000 +IDD3P0=0.000000 +IDD3P02=0.000000 +IDD3P1=0.038000 +IDD3P12=0.000000 +IDD4R=0.157000 +IDD4R2=0.000000 +IDD4W=0.125000 +IDD4W2=0.000000 +IDD5=0.235000 +IDD52=0.000000 +IDD6=0.020000 +IDD62=0.000000 +VDD=1.500000 +VDD2=0.000000 +activation_limit=4 +addr_mapping=RoRaBaCoCh +bank_groups_per_rank=0 +banks_per_rank=8 +burst_length=8 +channels=1 +clk_domain=system.clk_domain +conf_table_reported=true +default_p_state=UNDEFINED +device_bus_width=8 +device_rowbuffer_size=1024 +device_size=536870912 +devices_per_rank=8 +dll=true +eventq_index=0 +in_addr_map=true +kvm_map=true +max_accesses_per_row=16 +mem_sched_policy=frfcfs +min_writes_per_switch=16 +null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +page_policy=open_adaptive +power_model=Null +range=0:134217727:0:0:0:0 +ranks_per_channel=2 +read_buffer_size=32 +static_backend_latency=10000 +static_frontend_latency=10000 +tBURST=5000 +tCCD_L=0 +tCK=1250 +tCL=13750 +tCS=2500 +tRAS=35000 +tRCD=13750 +tREFI=7800000 +tRFC=260000 +tRP=13750 +tRRD=6000 +tRRD_L=0 +tRTP=7500 +tRTW=2500 +tWR=15000 +tWTR=7500 +tXAW=30000 +tXP=6000 +tXPDLL=0 +tXS=270000 +tXSDLL=0 +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 +port=system.membus.master[0] + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/minor-timing/config.json b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/minor-timing/config.json new file mode 100644 index 000000000..0a349ce2a --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/minor-timing/config.json @@ -0,0 +1,1211 @@ +{ + "name": null, + "sim_quantum": 0, + "system": { + "kernel": "", + "mmap_using_noreserve": false, + "kernel_addr_check": true, + "membus": { + "point_of_coherency": true, + "system": "system", + "response_latency": 2, + "cxx_class": "CoherentXBar", + "forward_latency": 4, + "clk_domain": "system.clk_domain", + "width": 16, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "master": { + "peer": [ + "system.physmem.port" + ], + "role": "MASTER" + }, + "type": "CoherentXBar", + "frontend_latency": 3, + "slave": { + "peer": [ + "system.system_port", + "system.cpu.l2cache.mem_side" + ], + "role": "SLAVE" + }, + "p_state_clk_gate_min": 1000, + "snoop_filter": { + "name": "snoop_filter", + "system": "system", + "max_capacity": 8388608, + "eventq_index": 0, + "cxx_class": "SnoopFilter", + "path": "system.membus.snoop_filter", + "type": "SnoopFilter", + "lookup_latency": 1 + }, + "power_model": null, + "path": "system.membus", + "snoop_response_latency": 4, + "name": "membus", + "p_state_clk_gate_bins": 20, + "use_default_range": false + }, + "symbolfile": "", + "readfile": "", + "thermal_model": null, + "cxx_class": "System", + "work_begin_cpu_id_exit": -1, + "load_offset": 0, + "work_begin_exit_count": 0, + "p_state_clk_gate_min": 1000, + "memories": [ + "system.physmem" + ], + "work_begin_ckpt_count": 0, + "clk_domain": { + "name": "clk_domain", + "clock": [ + 1000 + ], + "init_perf_level": 0, + "voltage_domain": "system.voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "mem_ranges": [], + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "dvfs_handler": { + "enable": false, + "name": "dvfs_handler", + "sys_clk_domain": "system.clk_domain", + "transition_latency": 100000000, + "eventq_index": 0, + "cxx_class": "DVFSHandler", + "domains": [], + "path": "system.dvfs_handler", + "type": "DVFSHandler" + }, + "work_end_exit_count": 0, + "type": "System", + "voltage_domain": { + "name": "voltage_domain", + "eventq_index": 0, + "voltage": [ + "1.0" + ], + "cxx_class": "VoltageDomain", + "path": "system.voltage_domain", + "type": "VoltageDomain" + }, + "cache_line_size": 64, + "boot_osflags": "a", + "system_port": { + "peer": "system.membus.slave[0]", + "role": "MASTER" + }, + "physmem": { + "static_frontend_latency": 10000, + "tRFC": 260000, + "activation_limit": 4, + "in_addr_map": true, + "IDD3N2": "0.0", + "tWTR": 7500, + "IDD52": "0.0", + "clk_domain": "system.clk_domain", + "channels": 1, + "write_buffer_size": 64, + "device_bus_width": 8, + "VDD": "1.5", + "write_high_thresh_perc": 85, + "cxx_class": "DRAMCtrl", + "bank_groups_per_rank": 0, + "IDD2N2": "0.0", + "port": { + "peer": "system.membus.master[0]", + "role": "SLAVE" + }, + "tCCD_L": 0, + "IDD2N": "0.032", + "p_state_clk_gate_min": 1000, + "null": false, + "IDD2P1": "0.032", + "eventq_index": 0, + "tRRD": 6000, + "tRTW": 2500, + "IDD4R": "0.157", + "burst_length": 8, + "tRTP": 7500, + "IDD4W": "0.125", + "tWR": 15000, + "banks_per_rank": 8, + "devices_per_rank": 8, + "IDD2P02": "0.0", + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "IDD6": "0.02", + "IDD5": "0.235", + "tRCD": 13750, + "type": "DRAMCtrl", + "IDD3P02": "0.0", + "tRRD_L": 0, + "IDD0": "0.055", + "IDD62": "0.0", + "min_writes_per_switch": 16, + "mem_sched_policy": "frfcfs", + "IDD02": "0.0", + "IDD2P0": "0.0", + "ranks_per_channel": 2, + "page_policy": "open_adaptive", + "IDD4W2": "0.0", + "tCS": 2500, + "power_model": null, + "tCL": 13750, + "read_buffer_size": 32, + "conf_table_reported": true, + "tCK": 1250, + "tRAS": 35000, + "tRP": 13750, + "tBURST": 5000, + "path": "system.physmem", + "tXP": 6000, + "tXS": 270000, + "addr_mapping": "RoRaBaCoCh", + "IDD3P0": "0.0", + "IDD3P1": "0.038", + "IDD3N": "0.038", + "name": "physmem", + "tXSDLL": 0, + "device_size": 536870912, + "kvm_map": true, + "dll": true, + "tXAW": 30000, + "write_low_thresh_perc": 50, + "range": "0:134217727:0:0:0:0", + "VDD2": "0.0", + "IDD2P12": "0.0", + "p_state_clk_gate_bins": 20, + "tXPDLL": 0, + "IDD4R2": "0.0", + "device_rowbuffer_size": 1024, + "static_backend_latency": 10000, + "max_accesses_per_row": 16, + "IDD3P12": "0.0", + "tREFI": 7800000 + }, + "power_model": null, + "work_cpus_ckpt_count": 0, + "thermal_components": [], + "path": "system", + "cpu_clk_domain": { + "name": "cpu_clk_domain", + "clock": [ + 500 + ], + "init_perf_level": 0, + "voltage_domain": "system.voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.cpu_clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "work_end_ckpt_count": 0, + "mem_mode": "timing", + "name": "system", + "init_param": 0, + "p_state_clk_gate_bins": 20, + "load_addr_mask": 1099511627775, + "cpu": [ + { + "max_insts_any_thread": 0, + "do_statistics_insts": true, + "numThreads": 1, + "fetch1LineSnapWidth": 0, + "fetch1ToFetch2BackwardDelay": 1, + "fetch1FetchLimit": 1, + "executeIssueLimit": 2, + "system": "system", + "executeLSQMaxStoreBufferStoresPerCycle": 2, + "icache": { + "cpu_side": { + "peer": "system.cpu.icache_port", + "role": "SLAVE" + }, + "clusivity": "mostly_incl", + "prefetcher": null, + "system": "system", + "write_buffers": 8, + "response_latency": 2, + "cxx_class": "Cache", + "size": 131072, + "type": "Cache", + "clk_domain": "system.cpu_clk_domain", + "max_miss_count": 0, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "mem_side": { + "peer": "system.cpu.toL2Bus.slave[0]", + "role": "MASTER" + }, + "mshrs": 4, + "writeback_clean": true, + "p_state_clk_gate_min": 1000, + "tags": { + "size": 131072, + "tag_latency": 2, + "name": "tags", + "p_state_clk_gate_min": 1000, + "eventq_index": 0, + "p_state_clk_gate_bins": 20, + "default_p_state": "UNDEFINED", + "clk_domain": "system.cpu_clk_domain", + "power_model": null, + "sequential_access": false, + "assoc": 2, + "cxx_class": "LRU", + "p_state_clk_gate_max": 1000000000000, + "path": "system.cpu.icache.tags", + "block_size": 64, + "type": "LRU", + "data_latency": 2 + }, + "tgts_per_mshr": 20, + "demand_mshr_reserve": 1, + "power_model": null, + "addr_ranges": [ + "0:18446744073709551615:0:0:0:0" + ], + "is_read_only": true, + "prefetch_on_access": false, + "path": "system.cpu.icache", + "data_latency": 2, + "tag_latency": 2, + "name": "icache", + "p_state_clk_gate_bins": 20, + "sequential_access": false, + "assoc": 2 + }, + "function_trace": false, + "do_checkpoint_insts": true, + "decodeInputWidth": 2, + "cxx_class": "MinorCPU", + "max_loads_all_threads": 0, + "executeMemoryIssueLimit": 1, + "decodeCycleInput": true, + "max_loads_any_thread": 0, + "executeLSQTransfersQueueSize": 2, + "p_state_clk_gate_max": 1000000000000, + "clk_domain": "system.cpu_clk_domain", + "function_trace_start": 0, + "cpu_id": 0, + "checker": null, + "eventq_index": 0, + "executeMemoryWidth": 0, + "default_p_state": "UNDEFINED", + "executeBranchDelay": 1, + "executeMemoryCommitLimit": 1, + "l2cache": { + "cpu_side": { + "peer": "system.cpu.toL2Bus.master[0]", + "role": "SLAVE" + }, + "clusivity": "mostly_incl", + "prefetcher": null, + "system": "system", + "write_buffers": 8, + "response_latency": 20, + "cxx_class": "Cache", + "size": 2097152, + "type": "Cache", + "clk_domain": "system.cpu_clk_domain", + "max_miss_count": 0, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "mem_side": { + "peer": "system.membus.slave[1]", + "role": "MASTER" + }, + "mshrs": 20, + "writeback_clean": false, + "p_state_clk_gate_min": 1000, + "tags": { + "size": 2097152, + "tag_latency": 20, + "name": "tags", + "p_state_clk_gate_min": 1000, + "eventq_index": 0, + "p_state_clk_gate_bins": 20, + "default_p_state": "UNDEFINED", + "clk_domain": "system.cpu_clk_domain", + "power_model": null, + "sequential_access": false, + "assoc": 8, + "cxx_class": "LRU", + "p_state_clk_gate_max": 1000000000000, + "path": "system.cpu.l2cache.tags", + "block_size": 64, + "type": "LRU", + "data_latency": 20 + }, + "tgts_per_mshr": 12, + "demand_mshr_reserve": 1, + "power_model": null, + "addr_ranges": [ + "0:18446744073709551615:0:0:0:0" + ], + "is_read_only": false, + "prefetch_on_access": false, + "path": "system.cpu.l2cache", + "data_latency": 20, + "tag_latency": 20, + "name": "l2cache", + "p_state_clk_gate_bins": 20, + "sequential_access": false, + "assoc": 8 + }, + "do_quiesce": true, + "type": "MinorCPU", + "executeCycleInput": true, + "executeAllowEarlyMemoryIssue": true, + "executeInputBufferSize": 7, + "icache_port": { + "peer": "system.cpu.icache.cpu_side", + "role": "MASTER" + }, + "p_state_clk_gate_bins": 20, + "socket_id": 0, + "progress_interval": 0, + "p_state_clk_gate_min": 1000, + "toL2Bus": { + "point_of_coherency": false, + "system": "system", + "response_latency": 1, + "cxx_class": "CoherentXBar", + "forward_latency": 0, + "clk_domain": "system.cpu_clk_domain", + "width": 32, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "master": { + "peer": [ + "system.cpu.l2cache.cpu_side" + ], + "role": "MASTER" + }, + "type": "CoherentXBar", + "frontend_latency": 1, + "slave": { + "peer": [ + "system.cpu.icache.mem_side", + "system.cpu.dcache.mem_side" + ], + "role": "SLAVE" + }, + "p_state_clk_gate_min": 1000, + "snoop_filter": { + "name": "snoop_filter", + "system": "system", + "max_capacity": 8388608, + "eventq_index": 0, + "cxx_class": "SnoopFilter", + "path": "system.cpu.toL2Bus.snoop_filter", + "type": "SnoopFilter", + "lookup_latency": 0 + }, + "power_model": null, + "path": "system.cpu.toL2Bus", + "snoop_response_latency": 1, + "name": "toL2Bus", + "p_state_clk_gate_bins": 20, + "use_default_range": false + }, + "isa": [ + { + "eventq_index": 0, + "path": "system.cpu.isa", + "type": "RiscvISA", + "name": "isa", + "cxx_class": "RiscvISA::ISA" + } + ], + "itb": { + "name": "itb", + "eventq_index": 0, + "cxx_class": "RiscvISA::TLB", + "path": "system.cpu.itb", + "type": "RiscvTLB", + "size": 64 + }, + "interrupts": [ + { + "eventq_index": 0, + "path": "system.cpu.interrupts", + "type": "RiscvInterrupts", + "name": "interrupts", + "cxx_class": "RiscvISA::Interrupts" + } + ], + "dcache_port": { + "peer": "system.cpu.dcache.cpu_side", + "role": "MASTER" + }, + "executeFuncUnits": { + "name": "executeFuncUnits", + "eventq_index": 0, + "cxx_class": "MinorFUPool", + "path": "system.cpu.executeFuncUnits", + "funcUnits": [ + { + "issueLat": 1, + "opLat": 3, + "name": "funcUnits0", + "cantForwardFromFUIndices": [], + "opClasses": { + "name": "opClasses", + "opClasses": [ + { + "opClass": "IntAlu", + "name": "opClasses", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses", + "type": "MinorOpClass" + } + ], + "eventq_index": 0, + "cxx_class": "MinorOpClassSet", + "path": "system.cpu.executeFuncUnits.funcUnits0.opClasses", + "type": "MinorOpClassSet" + }, + "eventq_index": 0, + "timings": [ + { + "extraAssumedLat": 0, + "description": "Int", + "srcRegsRelativeLats": [ + 2 + ], + "suppress": false, + "mask": 0, + "extraCommitLat": 0, + "eventq_index": 0, + "opClasses": { + "name": "opClasses", + "opClasses": [], + "eventq_index": 0, + "cxx_class": "MinorOpClassSet", + "path": "system.cpu.executeFuncUnits.funcUnits0.timings.opClasses", + "type": "MinorOpClassSet" + }, + "cxx_class": "MinorFUTiming", + "path": "system.cpu.executeFuncUnits.funcUnits0.timings", + "extraCommitLatExpr": null, + "type": "MinorFUTiming", + "match": 0, + "name": "timings" + } + ], + "cxx_class": "MinorFU", + "path": "system.cpu.executeFuncUnits.funcUnits0", + "type": "MinorFU" + }, + { + "issueLat": 1, + "opLat": 3, + "name": "funcUnits1", + "cantForwardFromFUIndices": [], + "opClasses": { + "name": "opClasses", + "opClasses": [ + { + "opClass": "IntAlu", + "name": "opClasses", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses", + "type": "MinorOpClass" + } + ], + "eventq_index": 0, + "cxx_class": "MinorOpClassSet", + "path": "system.cpu.executeFuncUnits.funcUnits1.opClasses", + "type": "MinorOpClassSet" + }, + "eventq_index": 0, + "timings": [ + { + "extraAssumedLat": 0, + "description": "Int", + "srcRegsRelativeLats": [ + 2 + ], + "suppress": false, + "mask": 0, + "extraCommitLat": 0, + "eventq_index": 0, + "opClasses": { + "name": "opClasses", + "opClasses": [], + "eventq_index": 0, + "cxx_class": "MinorOpClassSet", + "path": "system.cpu.executeFuncUnits.funcUnits1.timings.opClasses", + "type": "MinorOpClassSet" + }, + "cxx_class": "MinorFUTiming", + "path": "system.cpu.executeFuncUnits.funcUnits1.timings", + "extraCommitLatExpr": null, + "type": "MinorFUTiming", + "match": 0, + "name": "timings" + } + ], + "cxx_class": "MinorFU", + "path": "system.cpu.executeFuncUnits.funcUnits1", + "type": "MinorFU" + }, + { + "issueLat": 1, + "opLat": 3, + "name": "funcUnits2", + "cantForwardFromFUIndices": [], + "opClasses": { + "name": "opClasses", + "opClasses": [ + { + "opClass": "IntMult", + "name": "opClasses", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses", + "type": "MinorOpClass" + } + ], + "eventq_index": 0, + "cxx_class": "MinorOpClassSet", + "path": "system.cpu.executeFuncUnits.funcUnits2.opClasses", + "type": "MinorOpClassSet" + }, + "eventq_index": 0, + "timings": [ + { + "extraAssumedLat": 0, + "description": "Mul", + "srcRegsRelativeLats": [ + 0 + ], + "suppress": false, + "mask": 0, + "extraCommitLat": 0, + "eventq_index": 0, + "opClasses": { + "name": "opClasses", + "opClasses": [], + "eventq_index": 0, + "cxx_class": "MinorOpClassSet", + "path": "system.cpu.executeFuncUnits.funcUnits2.timings.opClasses", + "type": "MinorOpClassSet" + }, + "cxx_class": "MinorFUTiming", + "path": "system.cpu.executeFuncUnits.funcUnits2.timings", + "extraCommitLatExpr": null, + "type": "MinorFUTiming", + "match": 0, + "name": "timings" + } + ], + "cxx_class": "MinorFU", + "path": "system.cpu.executeFuncUnits.funcUnits2", + "type": "MinorFU" + }, + { + "issueLat": 9, + "opLat": 9, + "name": "funcUnits3", + "cantForwardFromFUIndices": [], + "opClasses": { + "name": "opClasses", + "opClasses": [ + { + "opClass": "IntDiv", + "name": "opClasses", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses", + "type": "MinorOpClass" + } + ], + "eventq_index": 0, + "cxx_class": "MinorOpClassSet", + "path": "system.cpu.executeFuncUnits.funcUnits3.opClasses", + "type": "MinorOpClassSet" + }, + "eventq_index": 0, + "timings": [], + "cxx_class": "MinorFU", + "path": "system.cpu.executeFuncUnits.funcUnits3", + "type": "MinorFU" + }, + { + "issueLat": 1, + "opLat": 6, + "name": "funcUnits4", + "cantForwardFromFUIndices": [], + "opClasses": { + "name": "opClasses", + "opClasses": [ + { + "opClass": "FloatAdd", + "name": "opClasses00", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00", + "type": "MinorOpClass" + }, + { + "opClass": "FloatCmp", + "name": "opClasses01", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01", + "type": "MinorOpClass" + }, + { + "opClass": "FloatCvt", + "name": "opClasses02", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02", + "type": "MinorOpClass" + }, + { + "opClass": "FloatMisc", + "name": "opClasses03", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03", + "type": "MinorOpClass" + }, + { + "opClass": "FloatMult", + "name": "opClasses04", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04", + "type": "MinorOpClass" + }, + { + "opClass": "FloatMultAcc", + "name": "opClasses05", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05", + "type": "MinorOpClass" + }, + { + "opClass": "FloatDiv", + "name": "opClasses06", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06", + "type": "MinorOpClass" + }, + { + "opClass": "FloatSqrt", + "name": "opClasses07", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07", + "type": "MinorOpClass" + }, + { + "opClass": "SimdAdd", + "name": "opClasses08", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08", + "type": "MinorOpClass" + }, + { + "opClass": "SimdAddAcc", + "name": "opClasses09", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09", + "type": "MinorOpClass" + }, + { + "opClass": "SimdAlu", + "name": "opClasses10", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10", + "type": "MinorOpClass" + }, + { + "opClass": "SimdCmp", + "name": "opClasses11", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11", + "type": "MinorOpClass" + }, + { + "opClass": "SimdCvt", + "name": "opClasses12", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12", + "type": "MinorOpClass" + }, + { + "opClass": "SimdMisc", + "name": "opClasses13", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13", + "type": "MinorOpClass" + }, + { + "opClass": "SimdMult", + "name": "opClasses14", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14", + "type": "MinorOpClass" + }, + { + "opClass": "SimdMultAcc", + "name": "opClasses15", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15", + "type": "MinorOpClass" + }, + { + "opClass": "SimdShift", + "name": "opClasses16", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16", + "type": "MinorOpClass" + }, + { + "opClass": "SimdShiftAcc", + "name": "opClasses17", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17", + "type": "MinorOpClass" + }, + { + "opClass": "SimdSqrt", + "name": "opClasses18", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18", + "type": "MinorOpClass" + }, + { + "opClass": "SimdFloatAdd", + "name": "opClasses19", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19", + "type": "MinorOpClass" + }, + { + "opClass": "SimdFloatAlu", + "name": "opClasses20", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20", + "type": "MinorOpClass" + }, + { + "opClass": "SimdFloatCmp", + "name": "opClasses21", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21", + "type": "MinorOpClass" + }, + { + "opClass": "SimdFloatCvt", + "name": "opClasses22", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22", + "type": "MinorOpClass" + }, + { + "opClass": "SimdFloatDiv", + "name": "opClasses23", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23", + "type": "MinorOpClass" + }, + { + "opClass": "SimdFloatMisc", + "name": "opClasses24", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24", + "type": "MinorOpClass" + }, + { + "opClass": "SimdFloatMult", + "name": "opClasses25", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25", + "type": "MinorOpClass" + }, + { + "opClass": "SimdFloatMultAcc", + "name": "opClasses26", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses26", + "type": "MinorOpClass" + }, + { + "opClass": "SimdFloatSqrt", + "name": "opClasses27", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses27", + "type": "MinorOpClass" + } + ], + "eventq_index": 0, + "cxx_class": "MinorOpClassSet", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses", + "type": "MinorOpClassSet" + }, + "eventq_index": 0, + "timings": [ + { + "extraAssumedLat": 0, + "description": "FloatSimd", + "srcRegsRelativeLats": [ + 2 + ], + "suppress": false, + "mask": 0, + "extraCommitLat": 0, + "eventq_index": 0, + "opClasses": { + "name": "opClasses", + "opClasses": [], + "eventq_index": 0, + "cxx_class": "MinorOpClassSet", + "path": "system.cpu.executeFuncUnits.funcUnits4.timings.opClasses", + "type": "MinorOpClassSet" + }, + "cxx_class": "MinorFUTiming", + "path": "system.cpu.executeFuncUnits.funcUnits4.timings", + "extraCommitLatExpr": null, + "type": "MinorFUTiming", + "match": 0, + "name": "timings" + } + ], + "cxx_class": "MinorFU", + "path": "system.cpu.executeFuncUnits.funcUnits4", + "type": "MinorFU" + }, + { + "issueLat": 1, + "opLat": 1, + "name": "funcUnits5", + "cantForwardFromFUIndices": [], + "opClasses": { + "name": "opClasses", + "opClasses": [ + { + "opClass": "MemRead", + "name": "opClasses0", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0", + "type": "MinorOpClass" + }, + { + "opClass": "MemWrite", + "name": "opClasses1", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1", + "type": "MinorOpClass" + }, + { + "opClass": "FloatMemRead", + "name": "opClasses2", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses2", + "type": "MinorOpClass" + }, + { + "opClass": "FloatMemWrite", + "name": "opClasses3", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses3", + "type": "MinorOpClass" + } + ], + "eventq_index": 0, + "cxx_class": "MinorOpClassSet", + "path": "system.cpu.executeFuncUnits.funcUnits5.opClasses", + "type": "MinorOpClassSet" + }, + "eventq_index": 0, + "timings": [ + { + "extraAssumedLat": 2, + "description": "Mem", + "srcRegsRelativeLats": [ + 1 + ], + "suppress": false, + "mask": 0, + "extraCommitLat": 0, + "eventq_index": 0, + "opClasses": { + "name": "opClasses", + "opClasses": [], + "eventq_index": 0, + "cxx_class": "MinorOpClassSet", + "path": "system.cpu.executeFuncUnits.funcUnits5.timings.opClasses", + "type": "MinorOpClassSet" + }, + "cxx_class": "MinorFUTiming", + "path": "system.cpu.executeFuncUnits.funcUnits5.timings", + "extraCommitLatExpr": null, + "type": "MinorFUTiming", + "match": 0, + "name": "timings" + } + ], + "cxx_class": "MinorFU", + "path": "system.cpu.executeFuncUnits.funcUnits5", + "type": "MinorFU" + }, + { + "issueLat": 1, + "opLat": 1, + "name": "funcUnits6", + "cantForwardFromFUIndices": [], + "opClasses": { + "name": "opClasses", + "opClasses": [ + { + "opClass": "IprAccess", + "name": "opClasses0", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0", + "type": "MinorOpClass" + }, + { + "opClass": "InstPrefetch", + "name": "opClasses1", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1", + "type": "MinorOpClass" + } + ], + "eventq_index": 0, + "cxx_class": "MinorOpClassSet", + "path": "system.cpu.executeFuncUnits.funcUnits6.opClasses", + "type": "MinorOpClassSet" + }, + "eventq_index": 0, + "timings": [], + "cxx_class": "MinorFU", + "path": "system.cpu.executeFuncUnits.funcUnits6", + "type": "MinorFU" + } + ], + "type": "MinorFUPool" + }, + "switched_out": false, + "power_model": null, + "max_insts_all_threads": 0, + "executeSetTraceTimeOnIssue": false, + "fetch2InputBufferSize": 2, + "profile": 0, + "fetch2ToDecodeForwardDelay": 1, + "executeInputWidth": 2, + "decodeToExecuteForwardDelay": 1, + "executeLSQRequestsQueueSize": 1, + "fetch2CycleInput": true, + "executeMaxAccessesInMemory": 2, + "enableIdling": true, + "executeLSQStoreBufferSize": 5, + "workload": [ + { + "uid": 100, + "pid": 100, + "kvmInSE": false, + "cxx_class": "LiveProcess", + "executable": "/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64f/insttest", + "drivers": [], + "system": "system", + "gid": 100, + "eventq_index": 0, + "env": [], + "input": "cin", + "ppid": 99, + "type": "LiveProcess", + "cwd": "", + "simpoint": 0, + "euid": 100, + "path": "system.cpu.workload", + "max_stack_size": 67108864, + "name": "workload", + "cmd": [ + "insttest" + ], + "errout": "cerr", + "useArchPT": false, + "egid": 100, + "output": "cout" + } + ], + "name": "cpu", + "dtb": { + "name": "dtb", + "eventq_index": 0, + "cxx_class": "RiscvISA::TLB", + "path": "system.cpu.dtb", + "type": "RiscvTLB", + "size": 64 + }, + "simpoint_start_insts": [], + "executeSetTraceTimeOnCommit": true, + "tracer": { + "eventq_index": 0, + "path": "system.cpu.tracer", + "type": "ExeTracer", + "name": "tracer", + "cxx_class": "Trace::ExeTracer" + }, + "threadPolicy": "RoundRobin", + "executeCommitLimit": 2, + "fetch1LineWidth": 0, + "branchPred": { + "numThreads": 1, + "BTBEntries": 4096, + "cxx_class": "TournamentBP", + "indirectPathLength": 3, + "globalCtrBits": 2, + "choicePredictorSize": 8192, + "indirectHashGHR": true, + "eventq_index": 0, + "localHistoryTableSize": 2048, + "type": "TournamentBP", + "indirectSets": 256, + "indirectWays": 2, + "choiceCtrBits": 2, + "useIndirect": true, + "localCtrBits": 2, + "path": "system.cpu.branchPred", + "localPredictorSize": 2048, + "RASSize": 16, + "globalPredictorSize": 8192, + "name": "branchPred", + "indirectHashTargets": true, + "instShiftAmt": 2, + "indirectTagSize": 16, + "BTBTagSize": 16 + }, + "dcache": { + "cpu_side": { + "peer": "system.cpu.dcache_port", + "role": "SLAVE" + }, + "clusivity": "mostly_incl", + "prefetcher": null, + "system": "system", + "write_buffers": 8, + "response_latency": 2, + "cxx_class": "Cache", + "size": 262144, + "type": "Cache", + "clk_domain": "system.cpu_clk_domain", + "max_miss_count": 0, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "mem_side": { + "peer": "system.cpu.toL2Bus.slave[1]", + "role": "MASTER" + }, + "mshrs": 4, + "writeback_clean": false, + "p_state_clk_gate_min": 1000, + "tags": { + "size": 262144, + "tag_latency": 2, + "name": "tags", + "p_state_clk_gate_min": 1000, + "eventq_index": 0, + "p_state_clk_gate_bins": 20, + "default_p_state": "UNDEFINED", + "clk_domain": "system.cpu_clk_domain", + "power_model": null, + "sequential_access": false, + "assoc": 2, + "cxx_class": "LRU", + "p_state_clk_gate_max": 1000000000000, + "path": "system.cpu.dcache.tags", + "block_size": 64, + "type": "LRU", + "data_latency": 2 + }, + "tgts_per_mshr": 20, + "demand_mshr_reserve": 1, + "power_model": null, + "addr_ranges": [ + "0:18446744073709551615:0:0:0:0" + ], + "is_read_only": false, + "prefetch_on_access": false, + "path": "system.cpu.dcache", + "data_latency": 2, + "tag_latency": 2, + "name": "dcache", + "p_state_clk_gate_bins": 20, + "sequential_access": false, + "assoc": 2 + }, + "path": "system.cpu", + "fetch1ToFetch2ForwardDelay": 1, + "decodeInputBufferSize": 3 + } + ], + "multi_thread": false, + "exit_on_work_items": false, + "work_item_id": -1, + "num_work_ids": 16 + }, + "time_sync_period": 100000000000, + "eventq_index": 0, + "time_sync_spin_threshold": 100000000, + "cxx_class": "Root", + "path": "root", + "time_sync_enable": false, + "type": "Root", + "full_system": false +}
\ No newline at end of file diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/minor-timing/simerr b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/minor-timing/simerr new file mode 100755 index 000000000..85a6a33ad --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/minor-timing/simerr @@ -0,0 +1,4 @@ +warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes) +warn: Unknown operating system; assuming Linux. +warn: Sockets disabled, not accepting gdb connections +warn: ClockedObject: More than one power state change request encountered within the same simulation tick diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/minor-timing/simout b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/minor-timing/simout new file mode 100755 index 000000000..695544b14 --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/minor-timing/simout @@ -0,0 +1,121 @@ +Redirecting stdout to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64f/minor-timing/simout +Redirecting stderr to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64f/minor-timing/simerr +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled Nov 30 2016 14:33:35 +gem5 started Nov 30 2016 16:18:32 +gem5 executing on zizzer, pid 34076 +command line: /z/powerjg/gem5-upstream/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64f/minor-timing -re /z/powerjg/gem5-upstream/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64f/minor-timing + +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. +clear fsflags: PASS +flw: PASS +fsw: PASS +fmadd.s: PASS +fmadd.s, quiet NaN: PASS +fmadd.s, signaling NaN: PASS +fmadd.s, infinity: PASS +fmadd.s, -infinity: PASS +fmsub.s: PASS +fmsub.s, quiet NaN: PASS +fmsub.s, signaling NaN: PASS +fmsub.s, infinity: PASS +fmsub.s, -infinity: PASS +fmsub.s, subtract infinity: PASS +fnmsub.s: PASS +fnmsub.s, quiet NaN: PASS +fnmsub.s, signaling NaN: PASS +fnmsub.s, infinity: PASS +fnmsub.s, -infinity: PASS +fnmsub.s, subtract infinity: PASS +fnmadd.s: PASS +fnmadd.s, quiet NaN: PASS +fnmadd.s, signaling NaN: PASS +fnmadd.s, infinity: PASS +fnmadd.s, -infinity: PASS +fadd.s: PASS +fadd.s, quiet NaN: PASS +fadd.s, signaling NaN: PASS +fadd.s, infinity: PASS +fadd.s, -infinity: PASS +fsub.s: PASS +fsub.s, quiet NaN: PASS +fsub.s, signaling NaN: PASS +fsub.s, infinity: PASS +fsub.s, -infinity: PASS +fsub.s, subtract infinity: PASS +fmul.s: PASS +fmul.s, quiet NaN: PASS +fmul.s, signaling NaN: PASS +fmul.s, infinity: PASS +fmul.s, -infinity: PASS +fmul.s, 0*infinity: PASS +fmul.s, overflow: PASS +fmul.s, underflow: PASS +fdiv.s: PASS +fdiv.s, quiet NaN: PASS +fdiv.s, signaling NaN: PASS +fdiv.s/0: PASS +fdiv.s/infinity: PASS +fdiv.s, infinity/infinity: PASS +fdiv.s, 0/0: PASS +fdiv.s, infinity/0: PASS +fdiv.s, 0/infinity: PASS +fdiv.s, underflow: PASS +fdiv.s, overflow: PASS +fsqrt.s: PASS +fsqrt.s, NaN: PASS +fsqrt.s, quiet NaN: PASS +fsqrt.s, signaling NaN: PASS +fsqrt.s, infinity: PASS +fsgnj.s, ++: PASS +fsgnj.s, +-: PASS +fsgnj.s, -+: PASS +fsgnj.s, --: PASS +fsgnj.s, quiet NaN: PASS +fsgnj.s, signaling NaN: PASS +fsgnj.s, inject NaN: PASS +fsgnj.s, inject -NaN: PASS +fsgnjn.s, ++: PASS +fsgnjn.s, +-: PASS +fsgnjn.s, -+: PASS +fsgnjn.s, --: PASS +fsgnjn.s, quiet NaN: PASS +fsgnjn.s, signaling NaN: PASS +fsgnjn.s, inject NaN: PASS +fsgnjn.s, inject NaN: PASS +fsgnjx.s, ++: PASS +fsgnjx.s, +-: PASS +fsgnjx.s, -+: PASS +fsgnjx.s, --: PASS +fsgnjx.s, quiet NaN: PASS +fsgnjx.s, signaling NaN: PASS +fsgnjx.s, inject NaN: PASS +fsgnjx.s, inject -NaN: PASS +fmin.s: PASS +fmin.s, -infinity: PASS +fmin.s, infinity: PASS +fmin.s, quiet NaN first: PASS +fmin.s, quiet NaN second: PASS +fmin.s, quiet NaN both: PASS +fmin.s, signaling NaN first: PASS +fmin.s, signaling NaN second: PASS +fmin.s, signaling NaN both: PASS +fmax.s: PASS +fmax.s, -infinity: PASS +fmax.s, infinity: PASS +fmax.s, quiet NaN first: PASS +fmax.s, quiet NaN second: PASS +fmax.s, quiet NaN both: PASS +fmax.s, signaling NaN first: PASS +fmax.s, signaling NaN second: PASS +fmax.s, signaling NaN both: PASS +fcvt.w.s, truncate positive: PASS +fcvt.w.s, truncate negative: PASS +fcvt.w.s, 0.0: PASS +fcvt.w.s, -0.0: PASS +fcvt.w.s, overflow: [1;31mFAIL[0m (expected 2147483647; found -2147483648) +Exiting @ tick 270200000 because target called exit() diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/minor-timing/stats.txt b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/minor-timing/stats.txt new file mode 100644 index 000000000..a1e10e23b --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/minor-timing/stats.txt @@ -0,0 +1,765 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.000270 # Number of seconds simulated +sim_ticks 270200000 # Number of ticks simulated +final_tick 270200000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 24805 # Simulator instruction rate (inst/s) +host_op_rate 24804 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 29619482 # Simulator tick rate (ticks/s) +host_mem_usage 244928 # Number of bytes of host memory used +host_seconds 9.12 # Real time elapsed on the host +sim_insts 226275 # Number of instructions simulated +sim_ops 226275 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 270200000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 67072 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 19264 # Number of bytes read from this memory +system.physmem.bytes_read::total 86336 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 67072 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 67072 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 1048 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 301 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1349 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 248230940 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 71295337 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 319526277 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 248230940 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 248230940 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 248230940 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 71295337 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 319526277 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1349 # Number of read requests accepted +system.physmem.writeReqs 0 # Number of write requests accepted +system.physmem.readBursts 1349 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 86336 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue +system.physmem.bytesWritten 0 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 86336 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 173 # Per bank write bursts +system.physmem.perBankRdBursts::1 19 # Per bank write bursts +system.physmem.perBankRdBursts::2 18 # Per bank write bursts +system.physmem.perBankRdBursts::3 76 # Per bank write bursts +system.physmem.perBankRdBursts::4 196 # Per bank write bursts +system.physmem.perBankRdBursts::5 259 # Per bank write bursts +system.physmem.perBankRdBursts::6 19 # Per bank write bursts +system.physmem.perBankRdBursts::7 4 # Per bank write bursts +system.physmem.perBankRdBursts::8 26 # Per bank write bursts +system.physmem.perBankRdBursts::9 99 # Per bank write bursts +system.physmem.perBankRdBursts::10 157 # Per bank write bursts +system.physmem.perBankRdBursts::11 158 # Per bank write bursts +system.physmem.perBankRdBursts::12 48 # Per bank write bursts +system.physmem.perBankRdBursts::13 47 # Per bank write bursts +system.physmem.perBankRdBursts::14 17 # Per bank write bursts +system.physmem.perBankRdBursts::15 33 # Per bank write bursts +system.physmem.perBankWrBursts::0 0 # Per bank write bursts +system.physmem.perBankWrBursts::1 0 # Per bank write bursts +system.physmem.perBankWrBursts::2 0 # Per bank write bursts +system.physmem.perBankWrBursts::3 0 # Per bank write bursts +system.physmem.perBankWrBursts::4 0 # Per bank write bursts +system.physmem.perBankWrBursts::5 0 # Per bank write bursts +system.physmem.perBankWrBursts::6 0 # Per bank write bursts +system.physmem.perBankWrBursts::7 0 # Per bank write bursts +system.physmem.perBankWrBursts::8 0 # Per bank write bursts +system.physmem.perBankWrBursts::9 0 # Per bank write bursts +system.physmem.perBankWrBursts::10 0 # Per bank write bursts +system.physmem.perBankWrBursts::11 0 # Per bank write bursts +system.physmem.perBankWrBursts::12 0 # Per bank write bursts +system.physmem.perBankWrBursts::13 0 # Per bank write bursts +system.physmem.perBankWrBursts::14 0 # Per bank write bursts +system.physmem.perBankWrBursts::15 0 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 269959000 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 1349 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 0 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1287 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 59 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 239 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 351.330544 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 238.583723 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 292.748127 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 53 22.18% 22.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 57 23.85% 46.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 30 12.55% 58.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 35 14.64% 73.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 21 8.79% 82.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 16 6.69% 88.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 4 1.67% 90.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 3 1.26% 91.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 20 8.37% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 239 # Bytes accessed per row activation +system.physmem.totQLat 15283750 # Total ticks spent queuing +system.physmem.totMemAccLat 40577500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 6745000 # Total ticks spent in databus transfers +system.physmem.avgQLat 11329.69 # Average queueing delay per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 30079.69 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 319.53 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 319.53 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.busUtil 2.50 # Data bus utilization in percentage +system.physmem.busUtilRead 2.50 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing +system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing +system.physmem.readRowHits 1101 # Number of row buffer hits during reads +system.physmem.writeRowHits 0 # Number of row buffer hits during writes +system.physmem.readRowHitRate 81.62 # Row buffer hit rate for reads +system.physmem.writeRowHitRate nan # Row buffer hit rate for writes +system.physmem.avgGap 200117.87 # Average gap between requests +system.physmem.pageHitRate 81.62 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 899640 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 462990 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 5454960 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 20897760.000000 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 13396710 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 455520 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 92913420 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 13776960 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 148257960 # Total energy per rank (pJ) +system.physmem_0.averagePower 548.697113 # Core power per rank (mW) +system.physmem_0.totalIdleTime 238953500 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 216000 # Time in different power states +system.physmem_0.memoryStateTime::REF 8840000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 0 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 35871500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 21502750 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 203769750 # Time in different power states +system.physmem_1.actEnergy 871080 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 444015 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 4176900 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 21512400.000000 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 11664480 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 3533280 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 82867740 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 20352000 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 718140.000000 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 146140035 # Total energy per rank (pJ) +system.physmem_1.averagePower 540.858753 # Core power per rank (mW) +system.physmem_1.totalIdleTime 235236750 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 8236250 # Time in different power states +system.physmem_1.memoryStateTime::REF 9106000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 690750 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 53009000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 17416750 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 181741250 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 270200000 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 61485 # Number of BP lookups +system.cpu.branchPred.condPredicted 39320 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 4384 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 51667 # Number of BTB lookups +system.cpu.branchPred.BTBHits 29457 # Number of BTB hits +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 57.013181 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 0 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 10264 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 6105 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 4159 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 2365 # Number of mispredicted indirect branches. +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 115 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 270200000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 540400 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 226275 # Number of instructions committed +system.cpu.committedOps 226275 # Number of ops (including micro ops) committed +system.cpu.discardedOps 10623 # Number of ops (including micro ops) which were discarded before commit +system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching +system.cpu.cpi 2.388244 # CPI: cycles per instruction +system.cpu.ipc 0.418718 # IPC: instructions per cycle +system.cpu.op_class_0::No_OpClass 117 0.05% 0.05% # Class of committed instruction +system.cpu.op_class_0::IntAlu 136540 60.34% 60.39% # Class of committed instruction +system.cpu.op_class_0::IntMult 325 0.14% 60.54% # Class of committed instruction +system.cpu.op_class_0::IntDiv 40 0.02% 60.56% # Class of committed instruction +system.cpu.op_class_0::FloatAdd 104 0.05% 60.60% # Class of committed instruction +system.cpu.op_class_0::FloatCmp 119 0.05% 60.65% # Class of committed instruction +system.cpu.op_class_0::FloatCvt 43 0.02% 60.67% # Class of committed instruction +system.cpu.op_class_0::FloatMult 30 0.01% 60.69% # Class of committed instruction +system.cpu.op_class_0::FloatMultAcc 0 0.00% 60.69% # Class of committed instruction +system.cpu.op_class_0::FloatDiv 11 0.00% 60.69% # Class of committed instruction +system.cpu.op_class_0::FloatMisc 0 0.00% 60.69% # Class of committed instruction +system.cpu.op_class_0::FloatSqrt 5 0.00% 60.69% # Class of committed instruction +system.cpu.op_class_0::SimdAdd 0 0.00% 60.69% # Class of committed instruction +system.cpu.op_class_0::SimdAddAcc 0 0.00% 60.69% # Class of committed instruction +system.cpu.op_class_0::SimdAlu 0 0.00% 60.69% # Class of committed instruction +system.cpu.op_class_0::SimdCmp 0 0.00% 60.69% # Class of committed instruction +system.cpu.op_class_0::SimdCvt 0 0.00% 60.69% # Class of committed instruction +system.cpu.op_class_0::SimdMisc 0 0.00% 60.69% # Class of committed instruction +system.cpu.op_class_0::SimdMult 0 0.00% 60.69% # Class of committed instruction +system.cpu.op_class_0::SimdMultAcc 0 0.00% 60.69% # Class of committed instruction +system.cpu.op_class_0::SimdShift 0 0.00% 60.69% # Class of committed instruction +system.cpu.op_class_0::SimdShiftAcc 0 0.00% 60.69% # Class of committed instruction +system.cpu.op_class_0::SimdSqrt 0 0.00% 60.69% # Class of committed instruction +system.cpu.op_class_0::SimdFloatAdd 0 0.00% 60.69% # Class of committed instruction +system.cpu.op_class_0::SimdFloatAlu 0 0.00% 60.69% # Class of committed instruction +system.cpu.op_class_0::SimdFloatCmp 0 0.00% 60.69% # Class of committed instruction +system.cpu.op_class_0::SimdFloatCvt 0 0.00% 60.69% # Class of committed instruction +system.cpu.op_class_0::SimdFloatDiv 0 0.00% 60.69% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMisc 0 0.00% 60.69% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMult 0 0.00% 60.69% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 60.69% # Class of committed instruction +system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 60.69% # Class of committed instruction +system.cpu.op_class_0::MemRead 51297 22.67% 83.36% # Class of committed instruction +system.cpu.op_class_0::MemWrite 37094 16.39% 99.76% # Class of committed instruction +system.cpu.op_class_0::FloatMemRead 414 0.18% 99.94% # Class of committed instruction +system.cpu.op_class_0::FloatMemWrite 136 0.06% 100.00% # Class of committed instruction +system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.op_class_0::total 226275 # Class of committed instruction +system.cpu.tickCycles 340080 # Number of cycles that the object actually ticked +system.cpu.idleCycles 200320 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 270200000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 0 # number of replacements +system.cpu.dcache.tags.tagsinuse 242.026814 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 90015 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 302 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 298.062914 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 242.026814 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.059089 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.059089 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 302 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 5 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 25 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 272 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.073730 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 181330 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 181330 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 270200000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 53182 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 53182 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 36833 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 36833 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 90015 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 90015 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 90015 # number of overall hits +system.cpu.dcache.overall_hits::total 90015 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 103 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 103 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 396 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 396 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 499 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 499 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 499 # number of overall misses +system.cpu.dcache.overall_misses::total 499 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 9494000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 9494000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 31678500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 31678500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 41172500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 41172500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 41172500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 41172500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 53285 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 53285 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 37229 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 37229 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 90514 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 90514 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 90514 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 90514 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.001933 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.001933 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.010637 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.010637 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.005513 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.005513 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.005513 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.005513 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 92174.757282 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 92174.757282 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 79996.212121 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 79996.212121 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 82510.020040 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 82510.020040 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 82510.020040 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 82510.020040 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 6 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 6 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 191 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 191 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 197 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 197 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 197 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 197 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 97 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 97 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 205 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 205 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 302 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 302 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 302 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 302 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 8881000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 8881000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 16356000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 16356000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 25237000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 25237000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 25237000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 25237000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001820 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001820 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005506 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005506 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003337 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.003337 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003337 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.003337 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 91556.701031 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 91556.701031 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79785.365854 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79785.365854 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 83566.225166 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 83566.225166 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 83566.225166 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 83566.225166 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 270200000 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 69 # number of replacements +system.cpu.icache.tags.tagsinuse 555.532163 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 101722 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1051 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 96.785918 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 555.532163 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.271256 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.271256 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 982 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 69 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 189 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 724 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.479492 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 206597 # Number of tag accesses +system.cpu.icache.tags.data_accesses 206597 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 270200000 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 101722 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 101722 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 101722 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 101722 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 101722 # number of overall hits +system.cpu.icache.overall_hits::total 101722 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1051 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1051 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1051 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1051 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1051 # number of overall misses +system.cpu.icache.overall_misses::total 1051 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 87209500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 87209500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 87209500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 87209500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 87209500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 87209500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 102773 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 102773 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 102773 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 102773 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 102773 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 102773 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.010226 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.010226 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.010226 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.010226 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.010226 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.010226 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 82977.640343 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 82977.640343 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 82977.640343 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 82977.640343 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 82977.640343 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 82977.640343 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.icache.writebacks::writebacks 69 # number of writebacks +system.cpu.icache.writebacks::total 69 # number of writebacks +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1051 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1051 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1051 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1051 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1051 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1051 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 86158500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 86158500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 86158500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 86158500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 86158500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 86158500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.010226 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.010226 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.010226 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.010226 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.010226 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.010226 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 81977.640343 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 81977.640343 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 81977.640343 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 81977.640343 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 81977.640343 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 81977.640343 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 270200000 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.replacements 0 # number of replacements +system.cpu.l2cache.tags.tagsinuse 827.037841 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 73 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 1349 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.054114 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::cpu.inst 585.656330 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 241.381510 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.017873 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.007366 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.025239 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 1349 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 74 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 215 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1060 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.041168 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 12725 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 12725 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 270200000 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.WritebackClean_hits::writebacks 69 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 69 # number of WritebackClean hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 3 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 3 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 1 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.inst 3 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 1 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 4 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 3 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 1 # number of overall hits +system.cpu.l2cache.overall_hits::total 4 # number of overall hits +system.cpu.l2cache.ReadExReq_misses::cpu.data 205 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 205 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 1048 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 1048 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 96 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 96 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.inst 1048 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 301 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 1349 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 1048 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 301 # number of overall misses +system.cpu.l2cache.overall_misses::total 1349 # number of overall misses +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 16048500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 16048500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 84550500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 84550500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 8723000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 8723000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 84550500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 24771500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 109322000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 84550500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 24771500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 109322000 # number of overall miss cycles +system.cpu.l2cache.WritebackClean_accesses::writebacks 69 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 69 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 205 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 205 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1051 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 1051 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 97 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 97 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 1051 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 302 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 1353 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 1051 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 302 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 1353 # number of overall (read+write) accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.997146 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.997146 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.989691 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.989691 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.997146 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.996689 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.997044 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.997146 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.996689 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.997044 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78285.365854 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 78285.365854 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 80677.958015 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 80677.958015 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 90864.583333 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 90864.583333 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80677.958015 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 82297.342193 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 81039.288362 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80677.958015 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 82297.342193 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 81039.288362 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 205 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 205 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 1048 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 1048 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 96 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 96 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 1048 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 301 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 1349 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 1048 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 301 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 1349 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 13998500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 13998500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 74070500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 74070500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 7763000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 7763000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 74070500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 21761500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 95832000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 74070500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 21761500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 95832000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.997146 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.997146 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.989691 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.989691 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.997146 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.996689 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.997044 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.997146 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.996689 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.997044 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68285.365854 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68285.365854 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 70677.958015 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 70677.958015 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 80864.583333 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 80864.583333 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70677.958015 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 72297.342193 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71039.288362 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70677.958015 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72297.342193 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71039.288362 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 1422 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 70 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 270200000 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 1148 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 69 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 205 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 205 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 1051 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 97 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2171 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 604 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 2775 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 71680 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 19328 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 91008 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 1353 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.000739 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.027186 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 1352 99.93% 99.93% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 1 0.07% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 1353 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 780000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 1576500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.6 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 453000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) +system.membus.snoop_filter.tot_requests 1349 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 270200000 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 1144 # Transaction distribution +system.membus.trans_dist::ReadExReq 205 # Transaction distribution +system.membus.trans_dist::ReadExResp 205 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 1144 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 2698 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 2698 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 86336 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 86336 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoopTraffic 0 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 1349 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 1349 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 1349 # Request fanout histogram +system.membus.reqLayer0.occupancy 1554000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.6 # Layer utilization (%) +system.membus.respLayer1.occupancy 7151000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 2.6 # Layer utilization (%) + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/o3-timing/config.ini b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/o3-timing/config.ini new file mode 100644 index 000000000..22d4ff3c2 --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/o3-timing/config.ini @@ -0,0 +1,872 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain +boot_osflags=a +cache_line_size=64 +clk_domain=system.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +exit_on_work_items=false +init_param=0 +kernel= +kernel_addr_check=true +load_addr_mask=1099511627775 +load_offset=0 +mem_mode=timing +mem_ranges= +memories=system.physmem +mmap_using_noreserve=false +multi_thread=false +num_work_ids=16 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +readfile= +symbolfile= +thermal_components= +thermal_model=Null +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=DerivO3CPU +children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload +LFSTSize=1024 +LQEntries=32 +LSQCheckLoads=true +LSQDepCheckShift=4 +SQEntries=32 +SSITSize=1024 +activity=0 +backComSize=5 +branchPred=system.cpu.branchPred +cachePorts=200 +checker=Null +clk_domain=system.cpu_clk_domain +commitToDecodeDelay=1 +commitToFetchDelay=1 +commitToIEWDelay=1 +commitToRenameDelay=1 +commitWidth=8 +cpu_id=0 +decodeToFetchDelay=1 +decodeToRenameDelay=1 +decodeWidth=8 +default_p_state=UNDEFINED +dispatchWidth=8 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +eventq_index=0 +fetchBufferSize=64 +fetchQueueSize=32 +fetchToDecodeDelay=1 +fetchTrapLatency=1 +fetchWidth=8 +forwardComSize=5 +fuPool=system.cpu.fuPool +function_trace=false +function_trace_start=0 +iewToCommitDelay=1 +iewToDecodeDelay=1 +iewToFetchDelay=1 +iewToRenameDelay=1 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +issueToExecuteDelay=1 +issueWidth=8 +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +needsTSO=false +numIQEntries=64 +numPhysCCRegs=0 +numPhysFloatRegs=256 +numPhysIntRegs=256 +numROBEntries=192 +numRobs=1 +numThreads=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +profile=0 +progress_interval=0 +renameToDecodeDelay=1 +renameToFetchDelay=1 +renameToIEWDelay=2 +renameToROBDelay=1 +renameWidth=8 +simpoint_start_insts= +smtCommitPolicy=RoundRobin +smtFetchPolicy=SingleThread +smtIQPolicy=Partitioned +smtIQThreshold=100 +smtLSQPolicy=Partitioned +smtLSQThreshold=100 +smtNumFetchingThreads=1 +smtROBPolicy=Partitioned +smtROBThreshold=100 +socket_id=0 +squashWidth=8 +store_set_clear_period=250000 +switched_out=false +system=system +tracer=system.cpu.tracer +trapLatency=13 +wbWidth=8 +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.branchPred] +type=TournamentBP +BTBEntries=4096 +BTBTagSize=16 +RASSize=16 +choiceCtrBits=2 +choicePredictorSize=8192 +eventq_index=0 +globalCtrBits=2 +globalPredictorSize=8192 +indirectHashGHR=true +indirectHashTargets=true +indirectPathLength=3 +indirectSets=256 +indirectTagSize=16 +indirectWays=2 +instShiftAmt=2 +localCtrBits=2 +localHistoryTableSize=2048 +localPredictorSize=2048 +numThreads=1 +useIndirect=true + +[system.cpu.dcache] +type=Cache +children=tags +addr_ranges=0:18446744073709551615:0:0:0:0 +assoc=2 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +data_latency=2 +default_p_state=UNDEFINED +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=4 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=262144 +system=system +tag_latency=2 +tags=system.cpu.dcache.tags +tgts_per_mshr=20 +write_buffers=8 +writeback_clean=false +cpu_side=system.cpu.dcache_port +mem_side=system.cpu.toL2Bus.slave[1] + +[system.cpu.dcache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +data_latency=2 +default_p_state=UNDEFINED +eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +sequential_access=false +size=262144 +tag_latency=2 + +[system.cpu.dtb] +type=RiscvTLB +eventq_index=0 +size=64 + +[system.cpu.fuPool] +type=FUPool +children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 +FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 +eventq_index=0 + +[system.cpu.fuPool.FUList0] +type=FUDesc +children=opList +count=6 +eventq_index=0 +opList=system.cpu.fuPool.FUList0.opList + +[system.cpu.fuPool.FUList0.opList] +type=OpDesc +eventq_index=0 +opClass=IntAlu +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList1] +type=FUDesc +children=opList0 opList1 +count=2 +eventq_index=0 +opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 + +[system.cpu.fuPool.FUList1.opList0] +type=OpDesc +eventq_index=0 +opClass=IntMult +opLat=3 +pipelined=true + +[system.cpu.fuPool.FUList1.opList1] +type=OpDesc +eventq_index=0 +opClass=IntDiv +opLat=20 +pipelined=false + +[system.cpu.fuPool.FUList2] +type=FUDesc +children=opList0 opList1 opList2 +count=4 +eventq_index=0 +opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 + +[system.cpu.fuPool.FUList2.opList0] +type=OpDesc +eventq_index=0 +opClass=FloatAdd +opLat=2 +pipelined=true + +[system.cpu.fuPool.FUList2.opList1] +type=OpDesc +eventq_index=0 +opClass=FloatCmp +opLat=2 +pipelined=true + +[system.cpu.fuPool.FUList2.opList2] +type=OpDesc +eventq_index=0 +opClass=FloatCvt +opLat=2 +pipelined=true + +[system.cpu.fuPool.FUList3] +type=FUDesc +children=opList0 opList1 opList2 opList3 opList4 +count=2 +eventq_index=0 +opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 system.cpu.fuPool.FUList3.opList3 system.cpu.fuPool.FUList3.opList4 + +[system.cpu.fuPool.FUList3.opList0] +type=OpDesc +eventq_index=0 +opClass=FloatMult +opLat=4 +pipelined=true + +[system.cpu.fuPool.FUList3.opList1] +type=OpDesc +eventq_index=0 +opClass=FloatMultAcc +opLat=5 +pipelined=true + +[system.cpu.fuPool.FUList3.opList2] +type=OpDesc +eventq_index=0 +opClass=FloatMisc +opLat=3 +pipelined=true + +[system.cpu.fuPool.FUList3.opList3] +type=OpDesc +eventq_index=0 +opClass=FloatDiv +opLat=12 +pipelined=false + +[system.cpu.fuPool.FUList3.opList4] +type=OpDesc +eventq_index=0 +opClass=FloatSqrt +opLat=24 +pipelined=false + +[system.cpu.fuPool.FUList4] +type=FUDesc +children=opList0 opList1 +count=0 +eventq_index=0 +opList=system.cpu.fuPool.FUList4.opList0 system.cpu.fuPool.FUList4.opList1 + +[system.cpu.fuPool.FUList4.opList0] +type=OpDesc +eventq_index=0 +opClass=MemRead +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList4.opList1] +type=OpDesc +eventq_index=0 +opClass=FloatMemRead +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5] +type=FUDesc +children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 +count=4 +eventq_index=0 +opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 + +[system.cpu.fuPool.FUList5.opList00] +type=OpDesc +eventq_index=0 +opClass=SimdAdd +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList01] +type=OpDesc +eventq_index=0 +opClass=SimdAddAcc +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList02] +type=OpDesc +eventq_index=0 +opClass=SimdAlu +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList03] +type=OpDesc +eventq_index=0 +opClass=SimdCmp +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList04] +type=OpDesc +eventq_index=0 +opClass=SimdCvt +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList05] +type=OpDesc +eventq_index=0 +opClass=SimdMisc +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList06] +type=OpDesc +eventq_index=0 +opClass=SimdMult +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList07] +type=OpDesc +eventq_index=0 +opClass=SimdMultAcc +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList08] +type=OpDesc +eventq_index=0 +opClass=SimdShift +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList09] +type=OpDesc +eventq_index=0 +opClass=SimdShiftAcc +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList10] +type=OpDesc +eventq_index=0 +opClass=SimdSqrt +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList11] +type=OpDesc +eventq_index=0 +opClass=SimdFloatAdd +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList12] +type=OpDesc +eventq_index=0 +opClass=SimdFloatAlu +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList13] +type=OpDesc +eventq_index=0 +opClass=SimdFloatCmp +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList14] +type=OpDesc +eventq_index=0 +opClass=SimdFloatCvt +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList15] +type=OpDesc +eventq_index=0 +opClass=SimdFloatDiv +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList16] +type=OpDesc +eventq_index=0 +opClass=SimdFloatMisc +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList17] +type=OpDesc +eventq_index=0 +opClass=SimdFloatMult +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList18] +type=OpDesc +eventq_index=0 +opClass=SimdFloatMultAcc +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList19] +type=OpDesc +eventq_index=0 +opClass=SimdFloatSqrt +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList6] +type=FUDesc +children=opList0 opList1 +count=0 +eventq_index=0 +opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1 + +[system.cpu.fuPool.FUList6.opList0] +type=OpDesc +eventq_index=0 +opClass=MemWrite +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList6.opList1] +type=OpDesc +eventq_index=0 +opClass=FloatMemWrite +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList7] +type=FUDesc +children=opList0 opList1 opList2 opList3 +count=4 +eventq_index=0 +opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 system.cpu.fuPool.FUList7.opList2 system.cpu.fuPool.FUList7.opList3 + +[system.cpu.fuPool.FUList7.opList0] +type=OpDesc +eventq_index=0 +opClass=MemRead +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList7.opList1] +type=OpDesc +eventq_index=0 +opClass=MemWrite +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList7.opList2] +type=OpDesc +eventq_index=0 +opClass=FloatMemRead +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList7.opList3] +type=OpDesc +eventq_index=0 +opClass=FloatMemWrite +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList8] +type=FUDesc +children=opList +count=1 +eventq_index=0 +opList=system.cpu.fuPool.FUList8.opList + +[system.cpu.fuPool.FUList8.opList] +type=OpDesc +eventq_index=0 +opClass=IprAccess +opLat=3 +pipelined=false + +[system.cpu.icache] +type=Cache +children=tags +addr_ranges=0:18446744073709551615:0:0:0:0 +assoc=2 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +data_latency=2 +default_p_state=UNDEFINED +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=true +max_miss_count=0 +mshrs=4 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=131072 +system=system +tag_latency=2 +tags=system.cpu.icache.tags +tgts_per_mshr=20 +write_buffers=8 +writeback_clean=true +cpu_side=system.cpu.icache_port +mem_side=system.cpu.toL2Bus.slave[0] + +[system.cpu.icache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +data_latency=2 +default_p_state=UNDEFINED +eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +sequential_access=false +size=131072 +tag_latency=2 + +[system.cpu.interrupts] +type=RiscvInterrupts +eventq_index=0 + +[system.cpu.isa] +type=RiscvISA +eventq_index=0 + +[system.cpu.itb] +type=RiscvTLB +eventq_index=0 +size=64 + +[system.cpu.l2cache] +type=Cache +children=tags +addr_ranges=0:18446744073709551615:0:0:0:0 +assoc=8 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +data_latency=20 +default_p_state=UNDEFINED +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=20 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +prefetch_on_access=false +prefetcher=Null +response_latency=20 +sequential_access=false +size=2097152 +system=system +tag_latency=20 +tags=system.cpu.l2cache.tags +tgts_per_mshr=12 +write_buffers=8 +writeback_clean=false +cpu_side=system.cpu.toL2Bus.master[0] +mem_side=system.membus.slave[1] + +[system.cpu.l2cache.tags] +type=LRU +assoc=8 +block_size=64 +clk_domain=system.cpu_clk_domain +data_latency=20 +default_p_state=UNDEFINED +eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +sequential_access=false +size=2097152 +tag_latency=20 + +[system.cpu.toL2Bus] +type=CoherentXBar +children=snoop_filter +clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED +eventq_index=0 +forward_latency=0 +frontend_latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +point_of_coherency=false +power_model=Null +response_latency=1 +snoop_filter=system.cpu.toL2Bus.snoop_filter +snoop_response_latency=1 +system=system +use_default_range=false +width=32 +master=system.cpu.l2cache.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side + +[system.cpu.toL2Bus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=0 +max_capacity=8388608 +system=system + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=LiveProcess +cmd=insttest +cwd= +drivers= +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable=/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64f/insttest +gid=100 +input=cin +kvmInSE=false +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=0 +system=system +uid=100 +useArchPT=false + +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000000 + +[system.membus] +type=CoherentXBar +children=snoop_filter +clk_domain=system.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +forward_latency=4 +frontend_latency=3 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +point_of_coherency=true +power_model=Null +response_latency=2 +snoop_filter=system.membus.snoop_filter +snoop_response_latency=4 +system=system +use_default_range=false +width=16 +master=system.physmem.port +slave=system.system_port system.cpu.l2cache.mem_side + +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + +[system.physmem] +type=DRAMCtrl +IDD0=0.055000 +IDD02=0.000000 +IDD2N=0.032000 +IDD2N2=0.000000 +IDD2P0=0.000000 +IDD2P02=0.000000 +IDD2P1=0.032000 +IDD2P12=0.000000 +IDD3N=0.038000 +IDD3N2=0.000000 +IDD3P0=0.000000 +IDD3P02=0.000000 +IDD3P1=0.038000 +IDD3P12=0.000000 +IDD4R=0.157000 +IDD4R2=0.000000 +IDD4W=0.125000 +IDD4W2=0.000000 +IDD5=0.235000 +IDD52=0.000000 +IDD6=0.020000 +IDD62=0.000000 +VDD=1.500000 +VDD2=0.000000 +activation_limit=4 +addr_mapping=RoRaBaCoCh +bank_groups_per_rank=0 +banks_per_rank=8 +burst_length=8 +channels=1 +clk_domain=system.clk_domain +conf_table_reported=true +default_p_state=UNDEFINED +device_bus_width=8 +device_rowbuffer_size=1024 +device_size=536870912 +devices_per_rank=8 +dll=true +eventq_index=0 +in_addr_map=true +kvm_map=true +max_accesses_per_row=16 +mem_sched_policy=frfcfs +min_writes_per_switch=16 +null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +page_policy=open_adaptive +power_model=Null +range=0:134217727:0:0:0:0 +ranks_per_channel=2 +read_buffer_size=32 +static_backend_latency=10000 +static_frontend_latency=10000 +tBURST=5000 +tCCD_L=0 +tCK=1250 +tCL=13750 +tCS=2500 +tRAS=35000 +tRCD=13750 +tREFI=7800000 +tRFC=260000 +tRP=13750 +tRRD=6000 +tRRD_L=0 +tRTP=7500 +tRTW=2500 +tWR=15000 +tWTR=7500 +tXAW=30000 +tXP=6000 +tXPDLL=0 +tXS=270000 +tXSDLL=0 +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 +port=system.membus.master[0] + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/o3-timing/config.json b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/o3-timing/config.json new file mode 100644 index 000000000..2675fc23a --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/o3-timing/config.json @@ -0,0 +1,1151 @@ +{ + "name": null, + "sim_quantum": 0, + "system": { + "kernel": "", + "mmap_using_noreserve": false, + "kernel_addr_check": true, + "membus": { + "point_of_coherency": true, + "system": "system", + "response_latency": 2, + "cxx_class": "CoherentXBar", + "forward_latency": 4, + "clk_domain": "system.clk_domain", + "width": 16, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "master": { + "peer": [ + "system.physmem.port" + ], + "role": "MASTER" + }, + "type": "CoherentXBar", + "frontend_latency": 3, + "slave": { + "peer": [ + "system.system_port", + "system.cpu.l2cache.mem_side" + ], + "role": "SLAVE" + }, + "p_state_clk_gate_min": 1000, + "snoop_filter": { + "name": "snoop_filter", + "system": "system", + "max_capacity": 8388608, + "eventq_index": 0, + "cxx_class": "SnoopFilter", + "path": "system.membus.snoop_filter", + "type": "SnoopFilter", + "lookup_latency": 1 + }, + "power_model": null, + "path": "system.membus", + "snoop_response_latency": 4, + "name": "membus", + "p_state_clk_gate_bins": 20, + "use_default_range": false + }, + "symbolfile": "", + "readfile": "", + "thermal_model": null, + "cxx_class": "System", + "work_begin_cpu_id_exit": -1, + "load_offset": 0, + "work_begin_exit_count": 0, + "p_state_clk_gate_min": 1000, + "memories": [ + "system.physmem" + ], + "work_begin_ckpt_count": 0, + "clk_domain": { + "name": "clk_domain", + "clock": [ + 1000 + ], + "init_perf_level": 0, + "voltage_domain": "system.voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "mem_ranges": [], + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "dvfs_handler": { + "enable": false, + "name": "dvfs_handler", + "sys_clk_domain": "system.clk_domain", + "transition_latency": 100000000, + "eventq_index": 0, + "cxx_class": "DVFSHandler", + "domains": [], + "path": "system.dvfs_handler", + "type": "DVFSHandler" + }, + "work_end_exit_count": 0, + "type": "System", + "voltage_domain": { + "name": "voltage_domain", + "eventq_index": 0, + "voltage": [ + "1.0" + ], + "cxx_class": "VoltageDomain", + "path": "system.voltage_domain", + "type": "VoltageDomain" + }, + "cache_line_size": 64, + "boot_osflags": "a", + "system_port": { + "peer": "system.membus.slave[0]", + "role": "MASTER" + }, + "physmem": { + "static_frontend_latency": 10000, + "tRFC": 260000, + "activation_limit": 4, + "in_addr_map": true, + "IDD3N2": "0.0", + "tWTR": 7500, + "IDD52": "0.0", + "clk_domain": "system.clk_domain", + "channels": 1, + "write_buffer_size": 64, + "device_bus_width": 8, + "VDD": "1.5", + "write_high_thresh_perc": 85, + "cxx_class": "DRAMCtrl", + "bank_groups_per_rank": 0, + "IDD2N2": "0.0", + "port": { + "peer": "system.membus.master[0]", + "role": "SLAVE" + }, + "tCCD_L": 0, + "IDD2N": "0.032", + "p_state_clk_gate_min": 1000, + "null": false, + "IDD2P1": "0.032", + "eventq_index": 0, + "tRRD": 6000, + "tRTW": 2500, + "IDD4R": "0.157", + "burst_length": 8, + "tRTP": 7500, + "IDD4W": "0.125", + "tWR": 15000, + "banks_per_rank": 8, + "devices_per_rank": 8, + "IDD2P02": "0.0", + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "IDD6": "0.02", + "IDD5": "0.235", + "tRCD": 13750, + "type": "DRAMCtrl", + "IDD3P02": "0.0", + "tRRD_L": 0, + "IDD0": "0.055", + "IDD62": "0.0", + "min_writes_per_switch": 16, + "mem_sched_policy": "frfcfs", + "IDD02": "0.0", + "IDD2P0": "0.0", + "ranks_per_channel": 2, + "page_policy": "open_adaptive", + "IDD4W2": "0.0", + "tCS": 2500, + "power_model": null, + "tCL": 13750, + "read_buffer_size": 32, + "conf_table_reported": true, + "tCK": 1250, + "tRAS": 35000, + "tRP": 13750, + "tBURST": 5000, + "path": "system.physmem", + "tXP": 6000, + "tXS": 270000, + "addr_mapping": "RoRaBaCoCh", + "IDD3P0": "0.0", + "IDD3P1": "0.038", + "IDD3N": "0.038", + "name": "physmem", + "tXSDLL": 0, + "device_size": 536870912, + "kvm_map": true, + "dll": true, + "tXAW": 30000, + "write_low_thresh_perc": 50, + "range": "0:134217727:0:0:0:0", + "VDD2": "0.0", + "IDD2P12": "0.0", + "p_state_clk_gate_bins": 20, + "tXPDLL": 0, + "IDD4R2": "0.0", + "device_rowbuffer_size": 1024, + "static_backend_latency": 10000, + "max_accesses_per_row": 16, + "IDD3P12": "0.0", + "tREFI": 7800000 + }, + "power_model": null, + "work_cpus_ckpt_count": 0, + "thermal_components": [], + "path": "system", + "cpu_clk_domain": { + "name": "cpu_clk_domain", + "clock": [ + 500 + ], + "init_perf_level": 0, + "voltage_domain": "system.voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.cpu_clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "work_end_ckpt_count": 0, + "mem_mode": "timing", + "name": "system", + "init_param": 0, + "p_state_clk_gate_bins": 20, + "load_addr_mask": 1099511627775, + "cpu": [ + { + "SQEntries": 32, + "smtLSQThreshold": 100, + "fetchTrapLatency": 1, + "iewToRenameDelay": 1, + "l2cache": { + "cpu_side": { + "peer": "system.cpu.toL2Bus.master[0]", + "role": "SLAVE" + }, + "clusivity": "mostly_incl", + "prefetcher": null, + "system": "system", + "write_buffers": 8, + "response_latency": 20, + "cxx_class": "Cache", + "size": 2097152, + "type": "Cache", + "clk_domain": "system.cpu_clk_domain", + "max_miss_count": 0, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "mem_side": { + "peer": "system.membus.slave[1]", + "role": "MASTER" + }, + "mshrs": 20, + "writeback_clean": false, + "p_state_clk_gate_min": 1000, + "tags": { + "size": 2097152, + "tag_latency": 20, + "name": "tags", + "p_state_clk_gate_min": 1000, + "eventq_index": 0, + "p_state_clk_gate_bins": 20, + "default_p_state": "UNDEFINED", + "clk_domain": "system.cpu_clk_domain", + "power_model": null, + "sequential_access": false, + "assoc": 8, + "cxx_class": "LRU", + "p_state_clk_gate_max": 1000000000000, + "path": "system.cpu.l2cache.tags", + "block_size": 64, + "type": "LRU", + "data_latency": 20 + }, + "tgts_per_mshr": 12, + "demand_mshr_reserve": 1, + "power_model": null, + "addr_ranges": [ + "0:18446744073709551615:0:0:0:0" + ], + "is_read_only": false, + "prefetch_on_access": false, + "path": "system.cpu.l2cache", + "data_latency": 20, + "tag_latency": 20, + "name": "l2cache", + "p_state_clk_gate_bins": 20, + "sequential_access": false, + "assoc": 8 + }, + "itb": { + "name": "itb", + "eventq_index": 0, + "cxx_class": "RiscvISA::TLB", + "path": "system.cpu.itb", + "type": "RiscvTLB", + "size": 64 + }, + "fetchWidth": 8, + "max_loads_all_threads": 0, + "cpu_id": 0, + "fetchToDecodeDelay": 1, + "renameToDecodeDelay": 1, + "do_quiesce": true, + "renameToROBDelay": 1, + "power_model": null, + "max_insts_all_threads": 0, + "decodeWidth": 8, + "commitToFetchDelay": 1, + "needsTSO": false, + "smtIQThreshold": 100, + "workload": [ + { + "uid": 100, + "pid": 100, + "kvmInSE": false, + "cxx_class": "LiveProcess", + "executable": "/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64f/insttest", + "drivers": [], + "system": "system", + "gid": 100, + "eventq_index": 0, + "env": [], + "input": "cin", + "ppid": 99, + "type": "LiveProcess", + "cwd": "", + "simpoint": 0, + "euid": 100, + "path": "system.cpu.workload", + "max_stack_size": 67108864, + "name": "workload", + "cmd": [ + "insttest" + ], + "errout": "cerr", + "useArchPT": false, + "egid": 100, + "output": "cout" + } + ], + "name": "cpu", + "SSITSize": 1024, + "activity": 0, + "max_loads_any_thread": 0, + "tracer": { + "eventq_index": 0, + "path": "system.cpu.tracer", + "type": "ExeTracer", + "name": "tracer", + "cxx_class": "Trace::ExeTracer" + }, + "decodeToFetchDelay": 1, + "renameWidth": 8, + "numThreads": 1, + "squashWidth": 8, + "function_trace": false, + "backComSize": 5, + "decodeToRenameDelay": 1, + "store_set_clear_period": 250000, + "numPhysIntRegs": 256, + "p_state_clk_gate_max": 1000000000000, + "toL2Bus": { + "point_of_coherency": false, + "system": "system", + "response_latency": 1, + "cxx_class": "CoherentXBar", + "forward_latency": 0, + "clk_domain": "system.cpu_clk_domain", + "width": 32, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "master": { + "peer": [ + "system.cpu.l2cache.cpu_side" + ], + "role": "MASTER" + }, + "type": "CoherentXBar", + "frontend_latency": 1, + "slave": { + "peer": [ + "system.cpu.icache.mem_side", + "system.cpu.dcache.mem_side" + ], + "role": "SLAVE" + }, + "p_state_clk_gate_min": 1000, + "snoop_filter": { + "name": "snoop_filter", + "system": "system", + "max_capacity": 8388608, + "eventq_index": 0, + "cxx_class": "SnoopFilter", + "path": "system.cpu.toL2Bus.snoop_filter", + "type": "SnoopFilter", + "lookup_latency": 0 + }, + "power_model": null, + "path": "system.cpu.toL2Bus", + "snoop_response_latency": 1, + "name": "toL2Bus", + "p_state_clk_gate_bins": 20, + "use_default_range": false + }, + "p_state_clk_gate_min": 1000, + "fuPool": { + "name": "fuPool", + "FUList": [ + { + "count": 6, + "opList": [ + { + "opClass": "IntAlu", + "opLat": 1, + "name": "opList", + "pipelined": true, + "eventq_index": 0, + "cxx_class": "OpDesc", + "path": "system.cpu.fuPool.FUList0.opList", + "type": "OpDesc" + } + ], + "name": "FUList0", + "eventq_index": 0, + "cxx_class": "FUDesc", + "path": "system.cpu.fuPool.FUList0", + "type": "FUDesc" + }, + { + "count": 2, + "opList": [ + { + "opClass": "IntMult", + "opLat": 3, + "name": "opList0", + "pipelined": true, + "eventq_index": 0, + "cxx_class": "OpDesc", + "path": "system.cpu.fuPool.FUList1.opList0", + "type": "OpDesc" + }, + { + "opClass": "IntDiv", + "opLat": 20, + "name": "opList1", + "pipelined": false, + "eventq_index": 0, + "cxx_class": "OpDesc", + "path": "system.cpu.fuPool.FUList1.opList1", + "type": "OpDesc" + } + ], + "name": "FUList1", + "eventq_index": 0, + "cxx_class": "FUDesc", + "path": "system.cpu.fuPool.FUList1", + "type": "FUDesc" + }, + { + "count": 4, + "opList": [ + { + "opClass": "FloatAdd", + "opLat": 2, + "name": "opList0", + "pipelined": true, + "eventq_index": 0, + "cxx_class": "OpDesc", + "path": "system.cpu.fuPool.FUList2.opList0", + "type": "OpDesc" + }, + { + "opClass": "FloatCmp", + "opLat": 2, + "name": "opList1", + "pipelined": true, + "eventq_index": 0, + "cxx_class": "OpDesc", + "path": "system.cpu.fuPool.FUList2.opList1", + "type": "OpDesc" + }, + { + "opClass": "FloatCvt", + "opLat": 2, + "name": "opList2", + "pipelined": true, + "eventq_index": 0, + "cxx_class": "OpDesc", + "path": "system.cpu.fuPool.FUList2.opList2", + "type": "OpDesc" + } + ], + "name": "FUList2", + "eventq_index": 0, + "cxx_class": "FUDesc", + "path": "system.cpu.fuPool.FUList2", + "type": "FUDesc" + }, + { + "count": 2, + "opList": [ + { + "opClass": "FloatMult", + "opLat": 4, + "name": "opList0", + "pipelined": true, + "eventq_index": 0, + "cxx_class": "OpDesc", + "path": "system.cpu.fuPool.FUList3.opList0", + "type": "OpDesc" + }, + { + "opClass": "FloatMultAcc", + "opLat": 5, + "name": "opList1", + "pipelined": true, + "eventq_index": 0, + "cxx_class": "OpDesc", + "path": "system.cpu.fuPool.FUList3.opList1", + "type": "OpDesc" + }, + { + "opClass": "FloatMisc", + "opLat": 3, + "name": "opList2", + "pipelined": true, + "eventq_index": 0, + "cxx_class": "OpDesc", + "path": "system.cpu.fuPool.FUList3.opList2", + "type": "OpDesc" + }, + { + "opClass": "FloatDiv", + "opLat": 12, + "name": "opList3", + "pipelined": false, + "eventq_index": 0, + "cxx_class": "OpDesc", + "path": "system.cpu.fuPool.FUList3.opList3", + "type": "OpDesc" + }, + { + "opClass": "FloatSqrt", + "opLat": 24, + "name": "opList4", + "pipelined": false, + "eventq_index": 0, + "cxx_class": "OpDesc", + "path": "system.cpu.fuPool.FUList3.opList4", + "type": "OpDesc" + } + ], + "name": "FUList3", + "eventq_index": 0, + "cxx_class": "FUDesc", + "path": "system.cpu.fuPool.FUList3", + "type": "FUDesc" + }, + { + "count": 0, + "opList": [ + { + "opClass": "MemRead", + "opLat": 1, + "name": "opList0", + "pipelined": true, + "eventq_index": 0, + "cxx_class": "OpDesc", + "path": "system.cpu.fuPool.FUList4.opList0", + "type": "OpDesc" + }, + { + "opClass": "FloatMemRead", + "opLat": 1, + "name": "opList1", + "pipelined": true, + "eventq_index": 0, + "cxx_class": "OpDesc", + "path": "system.cpu.fuPool.FUList4.opList1", + "type": "OpDesc" + } + ], + "name": "FUList4", + "eventq_index": 0, + "cxx_class": "FUDesc", + "path": "system.cpu.fuPool.FUList4", + "type": "FUDesc" + }, + { + "count": 4, + "opList": [ + { + "opClass": "SimdAdd", + "opLat": 1, + "name": "opList00", + "pipelined": true, + "eventq_index": 0, + "cxx_class": "OpDesc", + "path": "system.cpu.fuPool.FUList5.opList00", + "type": "OpDesc" + }, + { + "opClass": "SimdAddAcc", + "opLat": 1, + "name": "opList01", + "pipelined": true, + "eventq_index": 0, + "cxx_class": "OpDesc", + "path": "system.cpu.fuPool.FUList5.opList01", + "type": "OpDesc" + }, + { + "opClass": "SimdAlu", + "opLat": 1, + "name": "opList02", + "pipelined": true, + "eventq_index": 0, + "cxx_class": "OpDesc", + "path": "system.cpu.fuPool.FUList5.opList02", + "type": "OpDesc" + }, + { + "opClass": "SimdCmp", + "opLat": 1, + "name": "opList03", + "pipelined": true, + "eventq_index": 0, + "cxx_class": "OpDesc", + "path": "system.cpu.fuPool.FUList5.opList03", + "type": "OpDesc" + }, + { + "opClass": "SimdCvt", + "opLat": 1, + "name": "opList04", + "pipelined": true, + "eventq_index": 0, + "cxx_class": "OpDesc", + "path": "system.cpu.fuPool.FUList5.opList04", + "type": "OpDesc" + }, + { + "opClass": "SimdMisc", + "opLat": 1, + "name": "opList05", + "pipelined": true, + "eventq_index": 0, + "cxx_class": "OpDesc", + "path": "system.cpu.fuPool.FUList5.opList05", + "type": "OpDesc" + }, + { + "opClass": "SimdMult", + "opLat": 1, + "name": "opList06", + "pipelined": true, + "eventq_index": 0, + "cxx_class": "OpDesc", + "path": "system.cpu.fuPool.FUList5.opList06", + "type": "OpDesc" + }, + { + "opClass": "SimdMultAcc", + "opLat": 1, + "name": "opList07", + "pipelined": true, + "eventq_index": 0, + "cxx_class": "OpDesc", + "path": "system.cpu.fuPool.FUList5.opList07", + "type": "OpDesc" + }, + { + "opClass": "SimdShift", + "opLat": 1, + "name": "opList08", + "pipelined": true, + "eventq_index": 0, + "cxx_class": "OpDesc", + "path": "system.cpu.fuPool.FUList5.opList08", + "type": "OpDesc" + }, + { + "opClass": "SimdShiftAcc", + "opLat": 1, + "name": "opList09", + "pipelined": true, + "eventq_index": 0, + "cxx_class": "OpDesc", + "path": "system.cpu.fuPool.FUList5.opList09", + "type": "OpDesc" + }, + { + "opClass": "SimdSqrt", + "opLat": 1, + "name": "opList10", + "pipelined": true, + "eventq_index": 0, + "cxx_class": "OpDesc", + "path": "system.cpu.fuPool.FUList5.opList10", + "type": "OpDesc" + }, + { + "opClass": "SimdFloatAdd", + "opLat": 1, + "name": "opList11", + "pipelined": true, + "eventq_index": 0, + "cxx_class": "OpDesc", + "path": "system.cpu.fuPool.FUList5.opList11", + "type": "OpDesc" + }, + { + "opClass": "SimdFloatAlu", + "opLat": 1, + "name": "opList12", + "pipelined": true, + "eventq_index": 0, + "cxx_class": "OpDesc", + "path": "system.cpu.fuPool.FUList5.opList12", + "type": "OpDesc" + }, + { + "opClass": "SimdFloatCmp", + "opLat": 1, + "name": "opList13", + "pipelined": true, + "eventq_index": 0, + "cxx_class": "OpDesc", + "path": "system.cpu.fuPool.FUList5.opList13", + "type": "OpDesc" + }, + { + "opClass": "SimdFloatCvt", + "opLat": 1, + "name": "opList14", + "pipelined": true, + "eventq_index": 0, + "cxx_class": "OpDesc", + "path": "system.cpu.fuPool.FUList5.opList14", + "type": "OpDesc" + }, + { + "opClass": "SimdFloatDiv", + "opLat": 1, + "name": "opList15", + "pipelined": true, + "eventq_index": 0, + "cxx_class": "OpDesc", + "path": "system.cpu.fuPool.FUList5.opList15", + "type": "OpDesc" + }, + { + "opClass": "SimdFloatMisc", + "opLat": 1, + "name": "opList16", + "pipelined": true, + "eventq_index": 0, + "cxx_class": "OpDesc", + "path": "system.cpu.fuPool.FUList5.opList16", + "type": "OpDesc" + }, + { + "opClass": "SimdFloatMult", + "opLat": 1, + "name": "opList17", + "pipelined": true, + "eventq_index": 0, + "cxx_class": "OpDesc", + "path": "system.cpu.fuPool.FUList5.opList17", + "type": "OpDesc" + }, + { + "opClass": "SimdFloatMultAcc", + "opLat": 1, + "name": "opList18", + "pipelined": true, + "eventq_index": 0, + "cxx_class": "OpDesc", + "path": "system.cpu.fuPool.FUList5.opList18", + "type": "OpDesc" + }, + { + "opClass": "SimdFloatSqrt", + "opLat": 1, + "name": "opList19", + "pipelined": true, + "eventq_index": 0, + "cxx_class": "OpDesc", + "path": "system.cpu.fuPool.FUList5.opList19", + "type": "OpDesc" + } + ], + "name": "FUList5", + "eventq_index": 0, + "cxx_class": "FUDesc", + "path": "system.cpu.fuPool.FUList5", + "type": "FUDesc" + }, + { + "count": 0, + "opList": [ + { + "opClass": "MemWrite", + "opLat": 1, + "name": "opList0", + "pipelined": true, + "eventq_index": 0, + "cxx_class": "OpDesc", + "path": "system.cpu.fuPool.FUList6.opList0", + "type": "OpDesc" + }, + { + "opClass": "FloatMemWrite", + "opLat": 1, + "name": "opList1", + "pipelined": true, + "eventq_index": 0, + "cxx_class": "OpDesc", + "path": "system.cpu.fuPool.FUList6.opList1", + "type": "OpDesc" + } + ], + "name": "FUList6", + "eventq_index": 0, + "cxx_class": "FUDesc", + "path": "system.cpu.fuPool.FUList6", + "type": "FUDesc" + }, + { + "count": 4, + "opList": [ + { + "opClass": "MemRead", + "opLat": 1, + "name": "opList0", + "pipelined": true, + "eventq_index": 0, + "cxx_class": "OpDesc", + "path": "system.cpu.fuPool.FUList7.opList0", + "type": "OpDesc" + }, + { + "opClass": "MemWrite", + "opLat": 1, + "name": "opList1", + "pipelined": true, + "eventq_index": 0, + "cxx_class": "OpDesc", + "path": "system.cpu.fuPool.FUList7.opList1", + "type": "OpDesc" + }, + { + "opClass": "FloatMemRead", + "opLat": 1, + "name": "opList2", + "pipelined": true, + "eventq_index": 0, + "cxx_class": "OpDesc", + "path": "system.cpu.fuPool.FUList7.opList2", + "type": "OpDesc" + }, + { + "opClass": "FloatMemWrite", + "opLat": 1, + "name": "opList3", + "pipelined": true, + "eventq_index": 0, + "cxx_class": "OpDesc", + "path": "system.cpu.fuPool.FUList7.opList3", + "type": "OpDesc" + } + ], + "name": "FUList7", + "eventq_index": 0, + "cxx_class": "FUDesc", + "path": "system.cpu.fuPool.FUList7", + "type": "FUDesc" + }, + { + "count": 1, + "opList": [ + { + "opClass": "IprAccess", + "opLat": 3, + "name": "opList", + "pipelined": false, + "eventq_index": 0, + "cxx_class": "OpDesc", + "path": "system.cpu.fuPool.FUList8.opList", + "type": "OpDesc" + } + ], + "name": "FUList8", + "eventq_index": 0, + "cxx_class": "FUDesc", + "path": "system.cpu.fuPool.FUList8", + "type": "FUDesc" + } + ], + "eventq_index": 0, + "cxx_class": "FUPool", + "path": "system.cpu.fuPool", + "type": "FUPool" + }, + "socket_id": 0, + "renameToFetchDelay": 1, + "icache": { + "cpu_side": { + "peer": "system.cpu.icache_port", + "role": "SLAVE" + }, + "clusivity": "mostly_incl", + "prefetcher": null, + "system": "system", + "write_buffers": 8, + "response_latency": 2, + "cxx_class": "Cache", + "size": 131072, + "type": "Cache", + "clk_domain": "system.cpu_clk_domain", + "max_miss_count": 0, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "mem_side": { + "peer": "system.cpu.toL2Bus.slave[0]", + "role": "MASTER" + }, + "mshrs": 4, + "writeback_clean": true, + "p_state_clk_gate_min": 1000, + "tags": { + "size": 131072, + "tag_latency": 2, + "name": "tags", + "p_state_clk_gate_min": 1000, + "eventq_index": 0, + "p_state_clk_gate_bins": 20, + "default_p_state": "UNDEFINED", + "clk_domain": "system.cpu_clk_domain", + "power_model": null, + "sequential_access": false, + "assoc": 2, + "cxx_class": "LRU", + "p_state_clk_gate_max": 1000000000000, + "path": "system.cpu.icache.tags", + "block_size": 64, + "type": "LRU", + "data_latency": 2 + }, + "tgts_per_mshr": 20, + "demand_mshr_reserve": 1, + "power_model": null, + "addr_ranges": [ + "0:18446744073709551615:0:0:0:0" + ], + "is_read_only": true, + "prefetch_on_access": false, + "path": "system.cpu.icache", + "data_latency": 2, + "tag_latency": 2, + "name": "icache", + "p_state_clk_gate_bins": 20, + "sequential_access": false, + "assoc": 2 + }, + "path": "system.cpu", + "numRobs": 1, + "switched_out": false, + "smtLSQPolicy": "Partitioned", + "fetchBufferSize": 64, + "simpoint_start_insts": [], + "max_insts_any_thread": 0, + "smtROBThreshold": 100, + "numIQEntries": 64, + "branchPred": { + "numThreads": 1, + "BTBEntries": 4096, + "cxx_class": "TournamentBP", + "indirectPathLength": 3, + "globalCtrBits": 2, + "choicePredictorSize": 8192, + "indirectHashGHR": true, + "eventq_index": 0, + "localHistoryTableSize": 2048, + "type": "TournamentBP", + "indirectSets": 256, + "indirectWays": 2, + "choiceCtrBits": 2, + "useIndirect": true, + "localCtrBits": 2, + "path": "system.cpu.branchPred", + "localPredictorSize": 2048, + "RASSize": 16, + "globalPredictorSize": 8192, + "name": "branchPred", + "indirectHashTargets": true, + "instShiftAmt": 2, + "indirectTagSize": 16, + "BTBTagSize": 16 + }, + "LFSTSize": 1024, + "isa": [ + { + "eventq_index": 0, + "path": "system.cpu.isa", + "type": "RiscvISA", + "name": "isa", + "cxx_class": "RiscvISA::ISA" + } + ], + "smtROBPolicy": "Partitioned", + "iewToFetchDelay": 1, + "do_statistics_insts": true, + "dispatchWidth": 8, + "dcache": { + "cpu_side": { + "peer": "system.cpu.dcache_port", + "role": "SLAVE" + }, + "clusivity": "mostly_incl", + "prefetcher": null, + "system": "system", + "write_buffers": 8, + "response_latency": 2, + "cxx_class": "Cache", + "size": 262144, + "type": "Cache", + "clk_domain": "system.cpu_clk_domain", + "max_miss_count": 0, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "mem_side": { + "peer": "system.cpu.toL2Bus.slave[1]", + "role": "MASTER" + }, + "mshrs": 4, + "writeback_clean": false, + "p_state_clk_gate_min": 1000, + "tags": { + "size": 262144, + "tag_latency": 2, + "name": "tags", + "p_state_clk_gate_min": 1000, + "eventq_index": 0, + "p_state_clk_gate_bins": 20, + "default_p_state": "UNDEFINED", + "clk_domain": "system.cpu_clk_domain", + "power_model": null, + "sequential_access": false, + "assoc": 2, + "cxx_class": "LRU", + "p_state_clk_gate_max": 1000000000000, + "path": "system.cpu.dcache.tags", + "block_size": 64, + "type": "LRU", + "data_latency": 2 + }, + "tgts_per_mshr": 20, + "demand_mshr_reserve": 1, + "power_model": null, + "addr_ranges": [ + "0:18446744073709551615:0:0:0:0" + ], + "is_read_only": false, + "prefetch_on_access": false, + "path": "system.cpu.dcache", + "data_latency": 2, + "tag_latency": 2, + "name": "dcache", + "p_state_clk_gate_bins": 20, + "sequential_access": false, + "assoc": 2 + }, + "commitToDecodeDelay": 1, + "smtIQPolicy": "Partitioned", + "issueWidth": 8, + "LSQCheckLoads": true, + "commitToRenameDelay": 1, + "cachePorts": 200, + "system": "system", + "checker": null, + "numPhysFloatRegs": 256, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "type": "DerivO3CPU", + "wbWidth": 8, + "interrupts": [ + { + "eventq_index": 0, + "path": "system.cpu.interrupts", + "type": "RiscvInterrupts", + "name": "interrupts", + "cxx_class": "RiscvISA::Interrupts" + } + ], + "smtCommitPolicy": "RoundRobin", + "issueToExecuteDelay": 1, + "dtb": { + "name": "dtb", + "eventq_index": 0, + "cxx_class": "RiscvISA::TLB", + "path": "system.cpu.dtb", + "type": "RiscvTLB", + "size": 64 + }, + "numROBEntries": 192, + "fetchQueueSize": 32, + "iewToCommitDelay": 1, + "smtNumFetchingThreads": 1, + "forwardComSize": 5, + "do_checkpoint_insts": true, + "cxx_class": "DerivO3CPU", + "commitToIEWDelay": 1, + "commitWidth": 8, + "clk_domain": "system.cpu_clk_domain", + "function_trace_start": 0, + "smtFetchPolicy": "SingleThread", + "profile": 0, + "icache_port": { + "peer": "system.cpu.icache.cpu_side", + "role": "MASTER" + }, + "dcache_port": { + "peer": "system.cpu.dcache.cpu_side", + "role": "MASTER" + }, + "LSQDepCheckShift": 4, + "trapLatency": 13, + "iewToDecodeDelay": 1, + "numPhysCCRegs": 0, + "renameToIEWDelay": 2, + "p_state_clk_gate_bins": 20, + "progress_interval": 0, + "LQEntries": 32 + } + ], + "multi_thread": false, + "exit_on_work_items": false, + "work_item_id": -1, + "num_work_ids": 16 + }, + "time_sync_period": 100000000000, + "eventq_index": 0, + "time_sync_spin_threshold": 100000000, + "cxx_class": "Root", + "path": "root", + "time_sync_enable": false, + "type": "Root", + "full_system": false +}
\ No newline at end of file diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/o3-timing/simerr b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/o3-timing/simerr new file mode 100755 index 000000000..85a6a33ad --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/o3-timing/simerr @@ -0,0 +1,4 @@ +warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes) +warn: Unknown operating system; assuming Linux. +warn: Sockets disabled, not accepting gdb connections +warn: ClockedObject: More than one power state change request encountered within the same simulation tick diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/o3-timing/simout b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/o3-timing/simout new file mode 100755 index 000000000..44893f204 --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/o3-timing/simout @@ -0,0 +1,121 @@ +Redirecting stdout to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64f/o3-timing/simout +Redirecting stderr to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64f/o3-timing/simerr +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled Nov 30 2016 14:33:35 +gem5 started Nov 30 2016 16:18:32 +gem5 executing on zizzer, pid 34077 +command line: /z/powerjg/gem5-upstream/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64f/o3-timing -re /z/powerjg/gem5-upstream/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64f/o3-timing + +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. +clear fsflags: PASS +flw: PASS +fsw: PASS +fmadd.s: PASS +fmadd.s, quiet NaN: PASS +fmadd.s, signaling NaN: PASS +fmadd.s, infinity: PASS +fmadd.s, -infinity: PASS +fmsub.s: PASS +fmsub.s, quiet NaN: PASS +fmsub.s, signaling NaN: PASS +fmsub.s, infinity: PASS +fmsub.s, -infinity: PASS +fmsub.s, subtract infinity: PASS +fnmsub.s: PASS +fnmsub.s, quiet NaN: PASS +fnmsub.s, signaling NaN: PASS +fnmsub.s, infinity: PASS +fnmsub.s, -infinity: PASS +fnmsub.s, subtract infinity: PASS +fnmadd.s: PASS +fnmadd.s, quiet NaN: PASS +fnmadd.s, signaling NaN: PASS +fnmadd.s, infinity: PASS +fnmadd.s, -infinity: PASS +fadd.s: PASS +fadd.s, quiet NaN: PASS +fadd.s, signaling NaN: PASS +fadd.s, infinity: PASS +fadd.s, -infinity: PASS +fsub.s: PASS +fsub.s, quiet NaN: PASS +fsub.s, signaling NaN: PASS +fsub.s, infinity: PASS +fsub.s, -infinity: PASS +fsub.s, subtract infinity: PASS +fmul.s: PASS +fmul.s, quiet NaN: PASS +fmul.s, signaling NaN: PASS +fmul.s, infinity: PASS +fmul.s, -infinity: PASS +fmul.s, 0*infinity: PASS +fmul.s, overflow: PASS +fmul.s, underflow: PASS +fdiv.s: PASS +fdiv.s, quiet NaN: PASS +fdiv.s, signaling NaN: PASS +fdiv.s/0: PASS +fdiv.s/infinity: PASS +fdiv.s, infinity/infinity: PASS +fdiv.s, 0/0: PASS +fdiv.s, infinity/0: PASS +fdiv.s, 0/infinity: PASS +fdiv.s, underflow: PASS +fdiv.s, overflow: PASS +fsqrt.s: PASS +fsqrt.s, NaN: PASS +fsqrt.s, quiet NaN: PASS +fsqrt.s, signaling NaN: PASS +fsqrt.s, infinity: PASS +fsgnj.s, ++: PASS +fsgnj.s, +-: PASS +fsgnj.s, -+: PASS +fsgnj.s, --: PASS +fsgnj.s, quiet NaN: PASS +fsgnj.s, signaling NaN: PASS +fsgnj.s, inject NaN: PASS +fsgnj.s, inject -NaN: PASS +fsgnjn.s, ++: PASS +fsgnjn.s, +-: PASS +fsgnjn.s, -+: PASS +fsgnjn.s, --: PASS +fsgnjn.s, quiet NaN: PASS +fsgnjn.s, signaling NaN: PASS +fsgnjn.s, inject NaN: PASS +fsgnjn.s, inject NaN: PASS +fsgnjx.s, ++: PASS +fsgnjx.s, +-: PASS +fsgnjx.s, -+: PASS +fsgnjx.s, --: PASS +fsgnjx.s, quiet NaN: PASS +fsgnjx.s, signaling NaN: PASS +fsgnjx.s, inject NaN: PASS +fsgnjx.s, inject -NaN: PASS +fmin.s: PASS +fmin.s, -infinity: PASS +fmin.s, infinity: PASS +fmin.s, quiet NaN first: PASS +fmin.s, quiet NaN second: PASS +fmin.s, quiet NaN both: PASS +fmin.s, signaling NaN first: PASS +fmin.s, signaling NaN second: PASS +fmin.s, signaling NaN both: PASS +fmax.s: PASS +fmax.s, -infinity: PASS +fmax.s, infinity: PASS +fmax.s, quiet NaN first: PASS +fmax.s, quiet NaN second: PASS +fmax.s, quiet NaN both: PASS +fmax.s, signaling NaN first: PASS +fmax.s, signaling NaN second: PASS +fmax.s, signaling NaN both: PASS +fcvt.w.s, truncate positive: PASS +fcvt.w.s, truncate negative: PASS +fcvt.w.s, 0.0: PASS +fcvt.w.s, -0.0: PASS +fcvt.w.s, overflow: [1;31mFAIL[0m (expected 2147483647; found -2147483648) +Exiting @ tick 113397000 because target called exit() diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/o3-timing/stats.txt b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/o3-timing/stats.txt new file mode 100644 index 000000000..7007d9f9a --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/o3-timing/stats.txt @@ -0,0 +1,1020 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.000113 # Number of seconds simulated +sim_ticks 113397000 # Number of ticks simulated +final_tick 113397000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 22733 # Simulator instruction rate (inst/s) +host_op_rate 22733 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 11398414 # Simulator tick rate (ticks/s) +host_mem_usage 246096 # Number of bytes of host memory used +host_seconds 9.95 # Real time elapsed on the host +sim_insts 226159 # Number of instructions simulated +sim_ops 226159 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 113397000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 65856 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 19264 # Number of bytes read from this memory +system.physmem.bytes_read::total 85120 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 65856 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 65856 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 1029 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 301 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1330 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 580756105 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 169881037 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 750637142 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 580756105 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 580756105 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 580756105 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 169881037 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 750637142 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1330 # Number of read requests accepted +system.physmem.writeReqs 0 # Number of write requests accepted +system.physmem.readBursts 1330 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 85120 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue +system.physmem.bytesWritten 0 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 85120 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 174 # Per bank write bursts +system.physmem.perBankRdBursts::1 18 # Per bank write bursts +system.physmem.perBankRdBursts::2 15 # Per bank write bursts +system.physmem.perBankRdBursts::3 82 # Per bank write bursts +system.physmem.perBankRdBursts::4 195 # Per bank write bursts +system.physmem.perBankRdBursts::5 254 # Per bank write bursts +system.physmem.perBankRdBursts::6 22 # Per bank write bursts +system.physmem.perBankRdBursts::7 4 # Per bank write bursts +system.physmem.perBankRdBursts::8 25 # Per bank write bursts +system.physmem.perBankRdBursts::9 103 # Per bank write bursts +system.physmem.perBankRdBursts::10 149 # Per bank write bursts +system.physmem.perBankRdBursts::11 145 # Per bank write bursts +system.physmem.perBankRdBursts::12 50 # Per bank write bursts +system.physmem.perBankRdBursts::13 51 # Per bank write bursts +system.physmem.perBankRdBursts::14 14 # Per bank write bursts +system.physmem.perBankRdBursts::15 29 # Per bank write bursts +system.physmem.perBankWrBursts::0 0 # Per bank write bursts +system.physmem.perBankWrBursts::1 0 # Per bank write bursts +system.physmem.perBankWrBursts::2 0 # Per bank write bursts +system.physmem.perBankWrBursts::3 0 # Per bank write bursts +system.physmem.perBankWrBursts::4 0 # Per bank write bursts +system.physmem.perBankWrBursts::5 0 # Per bank write bursts +system.physmem.perBankWrBursts::6 0 # Per bank write bursts +system.physmem.perBankWrBursts::7 0 # Per bank write bursts +system.physmem.perBankWrBursts::8 0 # Per bank write bursts +system.physmem.perBankWrBursts::9 0 # Per bank write bursts +system.physmem.perBankWrBursts::10 0 # Per bank write bursts +system.physmem.perBankWrBursts::11 0 # Per bank write bursts +system.physmem.perBankWrBursts::12 0 # Per bank write bursts +system.physmem.perBankWrBursts::13 0 # Per bank write bursts +system.physmem.perBankWrBursts::14 0 # Per bank write bursts +system.physmem.perBankWrBursts::15 0 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 113291000 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 1330 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 0 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 807 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 369 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 107 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 43 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 210 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 393.752381 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 254.589157 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 342.600882 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 48 22.86% 22.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 44 20.95% 43.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 35 16.67% 60.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 18 8.57% 69.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 13 6.19% 75.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 10 4.76% 80.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 5 2.38% 82.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 5 2.38% 84.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 32 15.24% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 210 # Bytes accessed per row activation +system.physmem.totQLat 16749000 # Total ticks spent queuing +system.physmem.totMemAccLat 41686500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 6650000 # Total ticks spent in databus transfers +system.physmem.avgQLat 12593.23 # Average queueing delay per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 31343.23 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 750.64 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 750.64 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.busUtil 5.86 # Data bus utilization in percentage +system.physmem.busUtilRead 5.86 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.57 # Average read queue length when enqueuing +system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing +system.physmem.readRowHits 1108 # Number of row buffer hits during reads +system.physmem.writeRowHits 0 # Number of row buffer hits during writes +system.physmem.readRowHitRate 83.31 # Row buffer hit rate for reads +system.physmem.writeRowHitRate nan # Row buffer hit rate for writes +system.physmem.avgGap 85181.20 # Average gap between requests +system.physmem.pageHitRate 83.31 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 763980 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 387090 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 5454960 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 8604960.000000 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 9828510 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 194400 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 40216350 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 1207200 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 66657450 # Total energy per rank (pJ) +system.physmem_0.averagePower 587.821160 # Core power per rank (mW) +system.physmem_0.totalIdleTime 91041000 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 89500 # Time in different power states +system.physmem_0.memoryStateTime::REF 3640000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 0 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 3144500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 18326750 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 88196250 # Time in different power states +system.physmem_1.actEnergy 821100 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 409860 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 4041240 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 8604960.000000 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 7868280 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 220800 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 41251470 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 1959840 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 65177550 # Total energy per rank (pJ) +system.physmem_1.averagePower 574.770608 # Core power per rank (mW) +system.physmem_1.totalIdleTime 95505000 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 174500 # Time in different power states +system.physmem_1.memoryStateTime::REF 3640000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 0 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 5102500 # Time in different power states +system.physmem_1.memoryStateTime::ACT 14007750 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 90472250 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 113397000 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 78040 # Number of BP lookups +system.cpu.branchPred.condPredicted 47825 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 4968 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 59525 # Number of BTB lookups +system.cpu.branchPred.BTBHits 36023 # Number of BTB hits +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 60.517430 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 0 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 14832 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 6672 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 8160 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 2577 # Number of mispredicted indirect branches. +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 115 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 113397000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 226795 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.fetch.icacheStallCycles 73757 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 336548 # Number of instructions fetch has processed +system.cpu.fetch.Branches 78040 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 42695 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 87262 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 10228 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 401 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.IcacheWaitRetryStallCycles 192 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 60631 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 2398 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 166726 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.018569 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.822541 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 89937 53.94% 53.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 11784 7.07% 61.01% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 13843 8.30% 69.31% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 11668 7.00% 76.31% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 5791 3.47% 79.79% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 6797 4.08% 83.86% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 2856 1.71% 85.58% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 4611 2.77% 88.34% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 19439 11.66% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 166726 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.344099 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.483930 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 72653 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 18351 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 70165 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1269 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 4288 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 13538 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 899 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 310274 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 2536 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 4288 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 75144 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 7711 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 3158 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 68795 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 7630 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 298982 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 168 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 64 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 782 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 6500 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 208109 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 389749 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 387389 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 2360 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 155141 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 52968 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 133 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 133 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 3030 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 62164 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 43440 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1172 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 335 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 273555 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 154 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 261697 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 610 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 47545 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 26182 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 33 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 166726 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.569623 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.886679 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 67362 40.40% 40.40% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 36208 21.72% 62.12% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 23951 14.37% 76.49% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 10817 6.49% 82.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 10352 6.21% 89.18% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 8029 4.82% 94.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 7579 4.55% 98.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1315 0.79% 99.33% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 1113 0.67% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 166726 # Number of insts issued each cycle +system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 704 10.43% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 0 0.00% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 2989 44.27% 54.69% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 2970 43.99% 98.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemRead 88 1.30% 99.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemWrite 1 0.01% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.FU_type_0::No_OpClass 117 0.04% 0.04% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 159679 61.02% 61.06% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 326 0.12% 61.19% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 44 0.02% 61.20% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 172 0.07% 61.27% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 120 0.05% 61.31% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 58 0.02% 61.34% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 30 0.01% 61.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 61.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 12 0.00% 61.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 61.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 5 0.00% 61.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 61.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 61.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.35% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 59286 22.65% 84.01% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 40948 15.65% 99.66% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemRead 721 0.28% 99.93% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemWrite 179 0.07% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::total 261697 # Type of FU issued +system.cpu.iq.rate 1.153892 # Inst issue rate +system.cpu.iq.fu_busy_cnt 6752 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.025801 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 694798 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 318360 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 249994 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 2684 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 2938 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 1006 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 266946 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 1386 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 5628 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread0.squashedLoads 10453 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 28 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 40 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 6211 # Number of stores squashed +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread0.rescheduledLoads 10 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 117 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu.iew.iewSquashCycles 4288 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 4913 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 272 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 273705 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 3278 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 62164 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 43440 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 150 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 1 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 265 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 40 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1281 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 3469 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 4750 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 254156 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 58399 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 7541 # Number of squashed instructions skipped in execute +system.cpu.iew.exec_swp 0 # number of swp insts executed +system.cpu.iew.exec_nop 0 # number of nop insts executed +system.cpu.iew.exec_refs 98174 # number of memory reference insts executed +system.cpu.iew.exec_branches 57098 # Number of branches executed +system.cpu.iew.exec_stores 39775 # Number of stores executed +system.cpu.iew.exec_rate 1.120642 # Inst execution rate +system.cpu.iew.wb_sent 252228 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 251000 # cumulative count of insts written-back +system.cpu.iew.wb_producers 95690 # num instructions producing a value +system.cpu.iew.wb_consumers 132115 # num instructions consuming a value +system.cpu.iew.wb_rate 1.106726 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.724293 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 47577 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 117 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 4142 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 157673 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.434355 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.158076 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 82961 52.62% 52.62% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 25849 16.39% 69.01% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 14396 9.13% 78.14% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 11000 6.98% 85.12% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 5848 3.71% 88.83% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 5974 3.79% 92.61% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 3323 2.11% 94.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1258 0.80% 95.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 7064 4.48% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 157673 # Number of insts commited each cycle +system.cpu.commit.committedInsts 226159 # Number of instructions committed +system.cpu.commit.committedOps 226159 # Number of ops (including micro ops) committed +system.cpu.commit.swp_count 0 # Number of s/w prefetches committed +system.cpu.commit.refs 88940 # Number of memory references committed +system.cpu.commit.loads 51711 # Number of loads committed +system.cpu.commit.membars 0 # Number of memory barriers committed +system.cpu.commit.branches 50405 # Number of branches committed +system.cpu.commit.fp_insts 862 # Number of committed floating point instructions. +system.cpu.commit.int_insts 225991 # Number of committed integer instructions. +system.cpu.commit.function_calls 16616 # Number of function calls committed. +system.cpu.commit.op_class_0::No_OpClass 2 0.00% 0.00% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 136540 60.37% 60.37% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 325 0.14% 60.52% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 40 0.02% 60.54% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 104 0.05% 60.58% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 119 0.05% 60.63% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 43 0.02% 60.65% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 30 0.01% 60.67% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 60.67% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 11 0.00% 60.67% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMisc 0 0.00% 60.67% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 5 0.00% 60.67% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 0 0.00% 60.67% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 60.67% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 0 0.00% 60.67% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 0 0.00% 60.67% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 60.67% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 0 0.00% 60.67% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 60.67% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 60.67% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 60.67% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 60.67% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 60.67% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 60.67% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 60.67% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 60.67% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 60.67% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 60.67% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 60.67% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 60.67% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 60.67% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 60.67% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 51297 22.68% 83.36% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 37093 16.40% 99.76% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemRead 414 0.18% 99.94% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemWrite 136 0.06% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::total 226159 # Class of committed instruction +system.cpu.commit.bw_lim_events 7064 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 422850 # The number of ROB reads +system.cpu.rob.rob_writes 556608 # The number of ROB writes +system.cpu.timesIdled 458 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 60069 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 226159 # Number of Instructions Simulated +system.cpu.committedOps 226159 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 1.002812 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.002812 # CPI: Total CPI of All Threads +system.cpu.ipc 0.997196 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.997196 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 329004 # number of integer regfile reads +system.cpu.int_regfile_writes 174767 # number of integer regfile writes +system.cpu.fp_regfile_reads 880 # number of floating regfile reads +system.cpu.fp_regfile_writes 753 # number of floating regfile writes +system.cpu.misc_regfile_reads 448 # number of misc regfile reads +system.cpu.misc_regfile_writes 313 # number of misc regfile writes +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 113397000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 0 # number of replacements +system.cpu.dcache.tags.tagsinuse 244.736374 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 87597 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 301 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 291.019934 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 244.736374 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.059750 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.059750 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 301 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 7 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 100 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 194 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.073486 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 179361 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 179361 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 113397000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 51858 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 51858 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 35739 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 35739 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 87597 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 87597 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 87597 # number of overall hits +system.cpu.dcache.overall_hits::total 87597 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 443 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 443 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1490 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1490 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 1933 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1933 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1933 # number of overall misses +system.cpu.dcache.overall_misses::total 1933 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 36817500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 36817500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 96718425 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 96718425 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 133535925 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 133535925 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 133535925 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 133535925 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 52301 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 52301 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 37229 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 37229 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 89530 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 89530 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 89530 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 89530 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.008470 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.008470 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.040023 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.040023 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.021591 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.021591 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.021591 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.021591 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 83109.480813 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 83109.480813 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64911.694631 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 64911.694631 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 69082.216762 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 69082.216762 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 69082.216762 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 69082.216762 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 5513 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 79 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 69.784810 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 346 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 346 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1286 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1286 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1632 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1632 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1632 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1632 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 97 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 97 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 204 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 204 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 301 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 301 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 301 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 301 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 8757000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 8757000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 16055500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 16055500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 24812500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 24812500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 24812500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 24812500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001855 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001855 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005480 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005480 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003362 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.003362 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003362 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.003362 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 90278.350515 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 90278.350515 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 78703.431373 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 78703.431373 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 82433.554817 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 82433.554817 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 82433.554817 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 82433.554817 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 113397000 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 69 # number of replacements +system.cpu.icache.tags.tagsinuse 535.650396 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 59273 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1034 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 57.323985 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 535.650396 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.261548 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.261548 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 965 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 107 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 738 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 120 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.471191 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 122286 # Number of tag accesses +system.cpu.icache.tags.data_accesses 122286 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 113397000 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 59273 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 59273 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 59273 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 59273 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 59273 # number of overall hits +system.cpu.icache.overall_hits::total 59273 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1353 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1353 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1353 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1353 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1353 # number of overall misses +system.cpu.icache.overall_misses::total 1353 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 109130497 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 109130497 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 109130497 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 109130497 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 109130497 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 109130497 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 60626 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 60626 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 60626 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 60626 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 60626 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 60626 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.022317 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.022317 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.022317 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.022317 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.022317 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.022317 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 80658.164819 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 80658.164819 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 80658.164819 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 80658.164819 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 80658.164819 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 80658.164819 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 2365 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 33 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 71.666667 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.icache.writebacks::writebacks 69 # number of writebacks +system.cpu.icache.writebacks::total 69 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 319 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 319 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 319 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 319 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 319 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 319 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1034 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1034 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1034 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1034 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1034 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1034 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 86838997 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 86838997 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 86838997 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 86838997 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 86838997 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 86838997 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.017055 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.017055 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.017055 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.017055 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.017055 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.017055 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 83983.556093 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 83983.556093 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 83983.556093 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 83983.556093 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 83983.556093 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 83983.556093 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 113397000 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.replacements 0 # number of replacements +system.cpu.l2cache.tags.tagsinuse 808.401303 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 71 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 1330 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.053383 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::cpu.inst 563.637058 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 244.764245 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.017201 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.007470 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.024670 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 1330 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 114 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 879 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 337 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.040588 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 12538 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 12538 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 113397000 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.WritebackClean_hits::writebacks 69 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 69 # number of WritebackClean hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 2 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 2 # number of ReadCleanReq hits +system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 2 # number of overall hits +system.cpu.l2cache.overall_hits::total 2 # number of overall hits +system.cpu.l2cache.ReadExReq_misses::cpu.data 204 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 204 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 1029 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 1029 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 97 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 97 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.inst 1029 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 301 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 1330 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 1029 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 301 # number of overall misses +system.cpu.l2cache.overall_misses::total 1330 # number of overall misses +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 15749000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 15749000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 85256500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 85256500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 8611500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 8611500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 85256500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 24360500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 109617000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 85256500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 24360500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 109617000 # number of overall miss cycles +system.cpu.l2cache.WritebackClean_accesses::writebacks 69 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 69 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 204 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 204 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1031 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 1031 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 97 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 97 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 1031 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 301 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 1332 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 1031 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 301 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 1332 # number of overall (read+write) accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.998060 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.998060 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.998060 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.998498 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.998060 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.998498 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77200.980392 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 77200.980392 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 82853.741497 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 82853.741497 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 88778.350515 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 88778.350515 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82853.741497 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 80931.893688 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 82418.796992 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82853.741497 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 80931.893688 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 82418.796992 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 204 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 204 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 1029 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 1029 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 97 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 97 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 1029 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 301 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 1330 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 1029 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 301 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 1330 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 13709000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 13709000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 74966500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 74966500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 7641500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 7641500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 74966500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 21350500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 96317000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 74966500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 21350500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 96317000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.998060 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.998060 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.998060 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.998498 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.998060 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.998498 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67200.980392 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67200.980392 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72853.741497 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72853.741497 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 78778.350515 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 78778.350515 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72853.741497 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70931.893688 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72418.796992 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72853.741497 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70931.893688 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72418.796992 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 1404 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 72 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 113397000 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 1131 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 69 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 204 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 204 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 1034 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 97 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2134 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 602 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 2736 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 70400 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 19264 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 89664 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 3 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 192 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 1335 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.002247 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.047369 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 1332 99.78% 99.78% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 3 0.22% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 1335 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 771000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 1551000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 1.4 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 451500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%) +system.membus.snoop_filter.tot_requests 1330 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 113397000 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 1126 # Transaction distribution +system.membus.trans_dist::ReadExReq 204 # Transaction distribution +system.membus.trans_dist::ReadExResp 204 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 1126 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 2660 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 2660 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 85120 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 85120 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoopTraffic 0 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 1330 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 1330 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 1330 # Request fanout histogram +system.membus.reqLayer0.occupancy 1627500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 1.4 # Layer utilization (%) +system.membus.respLayer1.occupancy 7008750 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 6.2 # Layer utilization (%) + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-atomic/config.ini b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-atomic/config.ini new file mode 100644 index 000000000..50ff7280f --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-atomic/config.ini @@ -0,0 +1,211 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain +boot_osflags=a +cache_line_size=64 +clk_domain=system.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +exit_on_work_items=false +init_param=0 +kernel= +kernel_addr_check=true +load_addr_mask=1099511627775 +load_offset=0 +mem_mode=atomic +mem_ranges= +memories=system.physmem +mmap_using_noreserve=false +multi_thread=false +num_work_ids=16 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +readfile= +symbolfile= +thermal_components= +thermal_model=Null +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=AtomicSimpleCPU +children=dtb interrupts isa itb tracer workload +branchPred=Null +checker=Null +clk_domain=system.cpu_clk_domain +cpu_id=0 +default_p_state=UNDEFINED +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +eventq_index=0 +fastmem=false +function_trace=false +function_trace_start=0 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +profile=0 +progress_interval=0 +simpoint_start_insts= +simulate_data_stalls=false +simulate_inst_stalls=false +socket_id=0 +switched_out=false +system=system +tracer=system.cpu.tracer +width=1 +workload=system.cpu.workload +dcache_port=system.membus.slave[2] +icache_port=system.membus.slave[1] + +[system.cpu.dtb] +type=RiscvTLB +eventq_index=0 +size=64 + +[system.cpu.interrupts] +type=RiscvInterrupts +eventq_index=0 + +[system.cpu.isa] +type=RiscvISA +eventq_index=0 + +[system.cpu.itb] +type=RiscvTLB +eventq_index=0 +size=64 + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=LiveProcess +cmd=insttest +cwd= +drivers= +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable=/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64f/insttest +gid=100 +input=cin +kvmInSE=false +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=0 +system=system +uid=100 +useArchPT=false + +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000000 + +[system.membus] +type=CoherentXBar +children=snoop_filter +clk_domain=system.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +forward_latency=4 +frontend_latency=3 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +point_of_coherency=true +power_model=Null +response_latency=2 +snoop_filter=system.membus.snoop_filter +snoop_response_latency=4 +system=system +use_default_range=false +width=16 +master=system.physmem.port +slave=system.system_port system.cpu.icache_port system.cpu.dcache_port + +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + +[system.physmem] +type=SimpleMemory +bandwidth=73.000000 +clk_domain=system.clk_domain +conf_table_reported=true +default_p_state=UNDEFINED +eventq_index=0 +in_addr_map=true +kvm_map=true +latency=30000 +latency_var=0 +null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +range=0:134217727:0:0:0:0 +port=system.membus.master[0] + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-atomic/config.json b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-atomic/config.json new file mode 100644 index 000000000..ecd3e1c52 --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-atomic/config.json @@ -0,0 +1,289 @@ +{ + "name": null, + "sim_quantum": 0, + "system": { + "kernel": "", + "mmap_using_noreserve": false, + "kernel_addr_check": true, + "membus": { + "point_of_coherency": true, + "system": "system", + "response_latency": 2, + "cxx_class": "CoherentXBar", + "forward_latency": 4, + "clk_domain": "system.clk_domain", + "width": 16, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "master": { + "peer": [ + "system.physmem.port" + ], + "role": "MASTER" + }, + "type": "CoherentXBar", + "frontend_latency": 3, + "slave": { + "peer": [ + "system.system_port", + "system.cpu.icache_port", + "system.cpu.dcache_port" + ], + "role": "SLAVE" + }, + "p_state_clk_gate_min": 1000, + "snoop_filter": { + "name": "snoop_filter", + "system": "system", + "max_capacity": 8388608, + "eventq_index": 0, + "cxx_class": "SnoopFilter", + "path": "system.membus.snoop_filter", + "type": "SnoopFilter", + "lookup_latency": 1 + }, + "power_model": null, + "path": "system.membus", + "snoop_response_latency": 4, + "name": "membus", + "p_state_clk_gate_bins": 20, + "use_default_range": false + }, + "symbolfile": "", + "readfile": "", + "thermal_model": null, + "cxx_class": "System", + "work_begin_cpu_id_exit": -1, + "load_offset": 0, + "work_begin_exit_count": 0, + "p_state_clk_gate_min": 1000, + "memories": [ + "system.physmem" + ], + "work_begin_ckpt_count": 0, + "clk_domain": { + "name": "clk_domain", + "clock": [ + 1000 + ], + "init_perf_level": 0, + "voltage_domain": "system.voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "mem_ranges": [], + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "dvfs_handler": { + "enable": false, + "name": "dvfs_handler", + "sys_clk_domain": "system.clk_domain", + "transition_latency": 100000000, + "eventq_index": 0, + "cxx_class": "DVFSHandler", + "domains": [], + "path": "system.dvfs_handler", + "type": "DVFSHandler" + }, + "work_end_exit_count": 0, + "type": "System", + "voltage_domain": { + "name": "voltage_domain", + "eventq_index": 0, + "voltage": [ + "1.0" + ], + "cxx_class": "VoltageDomain", + "path": "system.voltage_domain", + "type": "VoltageDomain" + }, + "cache_line_size": 64, + "boot_osflags": "a", + "system_port": { + "peer": "system.membus.slave[0]", + "role": "MASTER" + }, + "physmem": { + "range": "0:134217727:0:0:0:0", + "latency": 30000, + "name": "physmem", + "p_state_clk_gate_min": 1000, + "eventq_index": 0, + "p_state_clk_gate_bins": 20, + "default_p_state": "UNDEFINED", + "kvm_map": true, + "clk_domain": "system.clk_domain", + "power_model": null, + "latency_var": 0, + "bandwidth": "73.000000", + "conf_table_reported": true, + "cxx_class": "SimpleMemory", + "p_state_clk_gate_max": 1000000000000, + "path": "system.physmem", + "null": false, + "type": "SimpleMemory", + "port": { + "peer": "system.membus.master[0]", + "role": "SLAVE" + }, + "in_addr_map": true + }, + "power_model": null, + "work_cpus_ckpt_count": 0, + "thermal_components": [], + "path": "system", + "cpu_clk_domain": { + "name": "cpu_clk_domain", + "clock": [ + 500 + ], + "init_perf_level": 0, + "voltage_domain": "system.voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.cpu_clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "work_end_ckpt_count": 0, + "mem_mode": "atomic", + "name": "system", + "init_param": 0, + "p_state_clk_gate_bins": 20, + "load_addr_mask": 1099511627775, + "cpu": [ + { + "do_statistics_insts": true, + "numThreads": 1, + "itb": { + "name": "itb", + "eventq_index": 0, + "cxx_class": "RiscvISA::TLB", + "path": "system.cpu.itb", + "type": "RiscvTLB", + "size": 64 + }, + "simulate_data_stalls": false, + "function_trace": false, + "do_checkpoint_insts": true, + "cxx_class": "AtomicSimpleCPU", + "max_loads_all_threads": 0, + "system": "system", + "clk_domain": "system.cpu_clk_domain", + "function_trace_start": 0, + "cpu_id": 0, + "width": 1, + "checker": null, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "do_quiesce": true, + "type": "AtomicSimpleCPU", + "fastmem": false, + "profile": 0, + "icache_port": { + "peer": "system.membus.slave[1]", + "role": "MASTER" + }, + "p_state_clk_gate_bins": 20, + "p_state_clk_gate_min": 1000, + "interrupts": [ + { + "eventq_index": 0, + "path": "system.cpu.interrupts", + "type": "RiscvInterrupts", + "name": "interrupts", + "cxx_class": "RiscvISA::Interrupts" + } + ], + "dcache_port": { + "peer": "system.membus.slave[2]", + "role": "MASTER" + }, + "socket_id": 0, + "power_model": null, + "max_insts_all_threads": 0, + "path": "system.cpu", + "max_loads_any_thread": 0, + "switched_out": false, + "workload": [ + { + "uid": 100, + "pid": 100, + "kvmInSE": false, + "cxx_class": "LiveProcess", + "executable": "/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64f/insttest", + "drivers": [], + "system": "system", + "gid": 100, + "eventq_index": 0, + "env": [], + "input": "cin", + "ppid": 99, + "type": "LiveProcess", + "cwd": "", + "simpoint": 0, + "euid": 100, + "path": "system.cpu.workload", + "max_stack_size": 67108864, + "name": "workload", + "cmd": [ + "insttest" + ], + "errout": "cerr", + "useArchPT": false, + "egid": 100, + "output": "cout" + } + ], + "name": "cpu", + "dtb": { + "name": "dtb", + "eventq_index": 0, + "cxx_class": "RiscvISA::TLB", + "path": "system.cpu.dtb", + "type": "RiscvTLB", + "size": 64 + }, + "simpoint_start_insts": [], + "max_insts_any_thread": 0, + "simulate_inst_stalls": false, + "progress_interval": 0, + "branchPred": null, + "isa": [ + { + "eventq_index": 0, + "path": "system.cpu.isa", + "type": "RiscvISA", + "name": "isa", + "cxx_class": "RiscvISA::ISA" + } + ], + "tracer": { + "eventq_index": 0, + "path": "system.cpu.tracer", + "type": "ExeTracer", + "name": "tracer", + "cxx_class": "Trace::ExeTracer" + } + } + ], + "multi_thread": false, + "exit_on_work_items": false, + "work_item_id": -1, + "num_work_ids": 16 + }, + "time_sync_period": 100000000000, + "eventq_index": 0, + "time_sync_spin_threshold": 100000000, + "cxx_class": "Root", + "path": "root", + "time_sync_enable": false, + "type": "Root", + "full_system": false +}
\ No newline at end of file diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-atomic/simerr b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-atomic/simerr new file mode 100755 index 000000000..fd133b12b --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-atomic/simerr @@ -0,0 +1,3 @@ +warn: Unknown operating system; assuming Linux. +warn: Sockets disabled, not accepting gdb connections +warn: ClockedObject: More than one power state change request encountered within the same simulation tick diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-atomic/simout b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-atomic/simout new file mode 100755 index 000000000..1aedc7412 --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-atomic/simout @@ -0,0 +1,121 @@ +Redirecting stdout to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64f/simple-atomic/simout +Redirecting stderr to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64f/simple-atomic/simerr +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled Nov 30 2016 14:33:35 +gem5 started Nov 30 2016 16:18:33 +gem5 executing on zizzer, pid 34079 +command line: /z/powerjg/gem5-upstream/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64f/simple-atomic -re /z/powerjg/gem5-upstream/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64f/simple-atomic + +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. +clear fsflags: PASS +flw: PASS +fsw: PASS +fmadd.s: PASS +fmadd.s, quiet NaN: PASS +fmadd.s, signaling NaN: PASS +fmadd.s, infinity: PASS +fmadd.s, -infinity: PASS +fmsub.s: PASS +fmsub.s, quiet NaN: PASS +fmsub.s, signaling NaN: PASS +fmsub.s, infinity: PASS +fmsub.s, -infinity: PASS +fmsub.s, subtract infinity: PASS +fnmsub.s: PASS +fnmsub.s, quiet NaN: PASS +fnmsub.s, signaling NaN: PASS +fnmsub.s, infinity: PASS +fnmsub.s, -infinity: PASS +fnmsub.s, subtract infinity: PASS +fnmadd.s: PASS +fnmadd.s, quiet NaN: PASS +fnmadd.s, signaling NaN: PASS +fnmadd.s, infinity: PASS +fnmadd.s, -infinity: PASS +fadd.s: PASS +fadd.s, quiet NaN: PASS +fadd.s, signaling NaN: PASS +fadd.s, infinity: PASS +fadd.s, -infinity: PASS +fsub.s: PASS +fsub.s, quiet NaN: PASS +fsub.s, signaling NaN: PASS +fsub.s, infinity: PASS +fsub.s, -infinity: PASS +fsub.s, subtract infinity: PASS +fmul.s: PASS +fmul.s, quiet NaN: PASS +fmul.s, signaling NaN: PASS +fmul.s, infinity: PASS +fmul.s, -infinity: PASS +fmul.s, 0*infinity: PASS +fmul.s, overflow: PASS +fmul.s, underflow: PASS +fdiv.s: PASS +fdiv.s, quiet NaN: PASS +fdiv.s, signaling NaN: PASS +fdiv.s/0: PASS +fdiv.s/infinity: PASS +fdiv.s, infinity/infinity: PASS +fdiv.s, 0/0: PASS +fdiv.s, infinity/0: PASS +fdiv.s, 0/infinity: PASS +fdiv.s, underflow: PASS +fdiv.s, overflow: PASS +fsqrt.s: PASS +fsqrt.s, NaN: PASS +fsqrt.s, quiet NaN: PASS +fsqrt.s, signaling NaN: PASS +fsqrt.s, infinity: PASS +fsgnj.s, ++: PASS +fsgnj.s, +-: PASS +fsgnj.s, -+: PASS +fsgnj.s, --: PASS +fsgnj.s, quiet NaN: PASS +fsgnj.s, signaling NaN: PASS +fsgnj.s, inject NaN: PASS +fsgnj.s, inject -NaN: PASS +fsgnjn.s, ++: PASS +fsgnjn.s, +-: PASS +fsgnjn.s, -+: PASS +fsgnjn.s, --: PASS +fsgnjn.s, quiet NaN: PASS +fsgnjn.s, signaling NaN: PASS +fsgnjn.s, inject NaN: PASS +fsgnjn.s, inject NaN: PASS +fsgnjx.s, ++: PASS +fsgnjx.s, +-: PASS +fsgnjx.s, -+: PASS +fsgnjx.s, --: PASS +fsgnjx.s, quiet NaN: PASS +fsgnjx.s, signaling NaN: PASS +fsgnjx.s, inject NaN: PASS +fsgnjx.s, inject -NaN: PASS +fmin.s: PASS +fmin.s, -infinity: PASS +fmin.s, infinity: PASS +fmin.s, quiet NaN first: PASS +fmin.s, quiet NaN second: PASS +fmin.s, quiet NaN both: PASS +fmin.s, signaling NaN first: PASS +fmin.s, signaling NaN second: PASS +fmin.s, signaling NaN both: PASS +fmax.s: PASS +fmax.s, -infinity: PASS +fmax.s, infinity: PASS +fmax.s, quiet NaN first: PASS +fmax.s, quiet NaN second: PASS +fmax.s, quiet NaN both: PASS +fmax.s, signaling NaN first: PASS +fmax.s, signaling NaN second: PASS +fmax.s, signaling NaN both: PASS +fcvt.w.s, truncate positive: PASS +fcvt.w.s, truncate negative: PASS +fcvt.w.s, 0.0: PASS +fcvt.w.s, -0.0: PASS +fcvt.w.s, overflow: [1;31mFAIL[0m (expected 2147483647; found -2147483648) +Exiting @ tick 113137000 because target called exit() diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-atomic/stats.txt b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-atomic/stats.txt new file mode 100644 index 000000000..9a7a22440 --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-atomic/stats.txt @@ -0,0 +1,153 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.000113 # Number of seconds simulated +sim_ticks 113137000 # Number of ticks simulated +final_tick 113137000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 28615 # Simulator instruction rate (inst/s) +host_op_rate 28615 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 14314809 # Simulator tick rate (ticks/s) +host_mem_usage 234404 # Number of bytes of host memory used +host_seconds 7.90 # Real time elapsed on the host +sim_insts 226159 # Number of instructions simulated +sim_ops 226159 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 113137000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 905100 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 339455 # Number of bytes read from this memory +system.physmem.bytes_read::total 1244555 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 905100 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 905100 # Number of instructions bytes read from this memory +system.physmem.bytes_written::cpu.data 226262 # Number of bytes written to this memory +system.physmem.bytes_written::total 226262 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 226275 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 51711 # Number of read requests responded to by this memory +system.physmem.num_reads::total 277986 # Number of read requests responded to by this memory +system.physmem.num_writes::cpu.data 37229 # Number of write requests responded to by this memory +system.physmem.num_writes::total 37229 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 8000035355 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3000388909 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 11000424264 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 8000035355 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 8000035355 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1999893934 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1999893934 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 8000035355 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 5000282843 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 13000318198 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 113137000 # Cumulative time (in ticks) in various power states +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 115 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 113137000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 226275 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 226159 # Number of instructions committed +system.cpu.committedOps 226159 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 225992 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 862 # Number of float alu accesses +system.cpu.num_func_calls 16616 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 33789 # number of instructions that are conditional controls +system.cpu.num_int_insts 225992 # number of integer instructions +system.cpu.num_fp_insts 862 # number of float instructions +system.cpu.num_int_register_reads 298589 # number of times the integer registers were read +system.cpu.num_int_register_writes 154866 # number of times the integer registers were written +system.cpu.num_fp_register_reads 733 # number of times the floating registers were read +system.cpu.num_fp_register_writes 588 # number of times the floating registers were written +system.cpu.num_mem_refs 88941 # number of memory refs +system.cpu.num_load_insts 51711 # Number of load instructions +system.cpu.num_store_insts 37230 # Number of store instructions +system.cpu.num_idle_cycles 0 # Number of idle cycles +system.cpu.num_busy_cycles 226275 # Number of busy cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.Branches 50405 # Number of branches fetched +system.cpu.op_class::No_OpClass 117 0.05% 0.05% # Class of executed instruction +system.cpu.op_class::IntAlu 136540 60.34% 60.39% # Class of executed instruction +system.cpu.op_class::IntMult 325 0.14% 60.54% # Class of executed instruction +system.cpu.op_class::IntDiv 40 0.02% 60.56% # Class of executed instruction +system.cpu.op_class::FloatAdd 104 0.05% 60.60% # Class of executed instruction +system.cpu.op_class::FloatCmp 119 0.05% 60.65% # Class of executed instruction +system.cpu.op_class::FloatCvt 43 0.02% 60.67% # Class of executed instruction +system.cpu.op_class::FloatMult 30 0.01% 60.69% # Class of executed instruction +system.cpu.op_class::FloatMultAcc 0 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::FloatDiv 11 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::FloatMisc 0 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::FloatSqrt 5 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::MemRead 51297 22.67% 83.36% # Class of executed instruction +system.cpu.op_class::MemWrite 37094 16.39% 99.76% # Class of executed instruction +system.cpu.op_class::FloatMemRead 414 0.18% 99.94% # Class of executed instruction +system.cpu.op_class::FloatMemWrite 136 0.06% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 226275 # Class of executed instruction +system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 113137000 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadReq 277986 # Transaction distribution +system.membus.trans_dist::ReadResp 277986 # Transaction distribution +system.membus.trans_dist::WriteReq 37229 # Transaction distribution +system.membus.trans_dist::WriteResp 37229 # Transaction distribution +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 452550 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 177880 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 630430 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 905100 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 565717 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 1470817 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoopTraffic 0 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 315215 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 315215 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 315215 # Request fanout histogram + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-timing-ruby/config.ini b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-timing-ruby/config.ini new file mode 100644 index 000000000..eb91af64f --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-timing-ruby/config.ini @@ -0,0 +1,1265 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000 +time_sync_spin_threshold=100000 + +[system] +type=System +children=clk_domain cpu dvfs_handler mem_ctrls ruby sys_port_proxy voltage_domain +boot_osflags=a +cache_line_size=64 +clk_domain=system.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +exit_on_work_items=false +init_param=0 +kernel= +kernel_addr_check=true +load_addr_mask=1099511627775 +load_offset=0 +mem_mode=timing +mem_ranges=0:268435455:0:0:0:0 +memories=system.mem_ctrls +mmap_using_noreserve=false +multi_thread=false +num_work_ids=16 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null +readfile= +symbolfile= +thermal_components= +thermal_model=Null +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.sys_port_proxy.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=TimingSimpleCPU +children=clk_domain dtb interrupts isa itb tracer workload +branchPred=Null +checker=Null +clk_domain=system.cpu.clk_domain +cpu_id=0 +default_p_state=UNDEFINED +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +eventq_index=0 +function_trace=false +function_trace_start=0 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null +profile=0 +progress_interval=0 +simpoint_start_insts= +socket_id=0 +switched_out=false +system=system +tracer=system.cpu.tracer +workload=system.cpu.workload +dcache_port=system.ruby.l1_cntrl0.sequencer.slave[1] +icache_port=system.ruby.l1_cntrl0.sequencer.slave[0] + +[system.cpu.clk_domain] +type=SrcClockDomain +clock=1 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu.dtb] +type=RiscvTLB +eventq_index=0 +size=64 + +[system.cpu.interrupts] +type=RiscvInterrupts +eventq_index=0 + +[system.cpu.isa] +type=RiscvISA +eventq_index=0 + +[system.cpu.itb] +type=RiscvTLB +eventq_index=0 +size=64 + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=LiveProcess +cmd=insttest +cwd= +drivers= +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable=/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64f/insttest +gid=100 +input=cin +kvmInSE=false +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=0 +system=system +uid=100 +useArchPT=false + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000 + +[system.mem_ctrls] +type=DRAMCtrl +IDD0=0.055000 +IDD02=0.000000 +IDD2N=0.032000 +IDD2N2=0.000000 +IDD2P0=0.000000 +IDD2P02=0.000000 +IDD2P1=0.032000 +IDD2P12=0.000000 +IDD3N=0.038000 +IDD3N2=0.000000 +IDD3P0=0.000000 +IDD3P02=0.000000 +IDD3P1=0.038000 +IDD3P12=0.000000 +IDD4R=0.157000 +IDD4R2=0.000000 +IDD4W=0.125000 +IDD4W2=0.000000 +IDD5=0.235000 +IDD52=0.000000 +IDD6=0.020000 +IDD62=0.000000 +VDD=1.500000 +VDD2=0.000000 +activation_limit=4 +addr_mapping=RoRaBaCoCh +bank_groups_per_rank=0 +banks_per_rank=8 +burst_length=8 +channels=1 +clk_domain=system.clk_domain +conf_table_reported=true +default_p_state=UNDEFINED +device_bus_width=8 +device_rowbuffer_size=1024 +device_size=536870912 +devices_per_rank=8 +dll=true +eventq_index=0 +in_addr_map=true +kvm_map=true +max_accesses_per_row=16 +mem_sched_policy=frfcfs +min_writes_per_switch=16 +null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +page_policy=open_adaptive +power_model=Null +range=0:268435455:5:19:0:0 +ranks_per_channel=2 +read_buffer_size=32 +static_backend_latency=10 +static_frontend_latency=10 +tBURST=5 +tCCD_L=0 +tCK=1 +tCL=14 +tCS=3 +tRAS=35 +tRCD=14 +tREFI=7800 +tRFC=260 +tRP=14 +tRRD=6 +tRRD_L=0 +tRTP=8 +tRTW=3 +tWR=15 +tWTR=8 +tXAW=30 +tXP=6 +tXPDLL=0 +tXS=270 +tXSDLL=0 +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 +port=system.ruby.dir_cntrl0.memory + +[system.ruby] +type=RubySystem +children=clk_domain dir_cntrl0 l1_cntrl0 memctrl_clk_domain network +access_backing_store=false +all_instructions=false +block_size_bytes=64 +clk_domain=system.ruby.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +hot_lines=false +memory_size_bits=48 +num_of_sequencers=1 +number_of_virtual_networks=5 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +phys_mem=Null +power_model=Null +randomization=false + +[system.ruby.clk_domain] +type=SrcClockDomain +clock=1 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.ruby.dir_cntrl0] +type=Directory_Controller +children=directory dmaRequestToDir dmaResponseFromDir forwardFromDir requestToDir responseFromDir responseFromMemory +buffer_size=0 +clk_domain=system.ruby.clk_domain +cluster_id=0 +default_p_state=UNDEFINED +directory=system.ruby.dir_cntrl0.directory +directory_latency=12 +dmaRequestToDir=system.ruby.dir_cntrl0.dmaRequestToDir +dmaResponseFromDir=system.ruby.dir_cntrl0.dmaResponseFromDir +eventq_index=0 +forwardFromDir=system.ruby.dir_cntrl0.forwardFromDir +number_of_TBEs=256 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null +recycle_latency=10 +requestToDir=system.ruby.dir_cntrl0.requestToDir +responseFromDir=system.ruby.dir_cntrl0.responseFromDir +responseFromMemory=system.ruby.dir_cntrl0.responseFromMemory +ruby_system=system.ruby +system=system +to_memory_controller_latency=1 +transitions_per_cycle=4 +version=0 +memory=system.mem_ctrls.port + +[system.ruby.dir_cntrl0.directory] +type=RubyDirectoryMemory +eventq_index=0 +numa_high_bit=5 +size=268435456 +version=0 + +[system.ruby.dir_cntrl0.dmaRequestToDir] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +slave=system.ruby.network.master[3] + +[system.ruby.dir_cntrl0.dmaResponseFromDir] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +master=system.ruby.network.slave[3] + +[system.ruby.dir_cntrl0.forwardFromDir] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=false +randomization=false +master=system.ruby.network.slave[4] + +[system.ruby.dir_cntrl0.requestToDir] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +slave=system.ruby.network.master[2] + +[system.ruby.dir_cntrl0.responseFromDir] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=false +randomization=false +master=system.ruby.network.slave[2] + +[system.ruby.dir_cntrl0.responseFromMemory] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=false +randomization=false + +[system.ruby.l1_cntrl0] +type=L1Cache_Controller +children=cacheMemory forwardToCache mandatoryQueue requestFromCache responseFromCache responseToCache sequencer +buffer_size=0 +cacheMemory=system.ruby.l1_cntrl0.cacheMemory +cache_response_latency=12 +clk_domain=system.cpu.clk_domain +cluster_id=0 +default_p_state=UNDEFINED +eventq_index=0 +forwardToCache=system.ruby.l1_cntrl0.forwardToCache +issue_latency=2 +mandatoryQueue=system.ruby.l1_cntrl0.mandatoryQueue +number_of_TBEs=256 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null +recycle_latency=10 +requestFromCache=system.ruby.l1_cntrl0.requestFromCache +responseFromCache=system.ruby.l1_cntrl0.responseFromCache +responseToCache=system.ruby.l1_cntrl0.responseToCache +ruby_system=system.ruby +send_evictions=false +sequencer=system.ruby.l1_cntrl0.sequencer +system=system +transitions_per_cycle=4 +version=0 + +[system.ruby.l1_cntrl0.cacheMemory] +type=RubyCache +children=replacement_policy +assoc=2 +block_size=0 +dataAccessLatency=1 +dataArrayBanks=1 +eventq_index=0 +is_icache=false +replacement_policy=system.ruby.l1_cntrl0.cacheMemory.replacement_policy +resourceStalls=false +ruby_system=system.ruby +size=256 +start_index_bit=6 +tagAccessLatency=1 +tagArrayBanks=1 + +[system.ruby.l1_cntrl0.cacheMemory.replacement_policy] +type=PseudoLRUReplacementPolicy +assoc=2 +block_size=64 +eventq_index=0 +size=256 + +[system.ruby.l1_cntrl0.forwardToCache] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +slave=system.ruby.network.master[0] + +[system.ruby.l1_cntrl0.mandatoryQueue] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=false +randomization=false + +[system.ruby.l1_cntrl0.requestFromCache] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +master=system.ruby.network.slave[0] + +[system.ruby.l1_cntrl0.responseFromCache] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +master=system.ruby.network.slave[1] + +[system.ruby.l1_cntrl0.responseToCache] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +slave=system.ruby.network.master[1] + +[system.ruby.l1_cntrl0.sequencer] +type=RubySequencer +clk_domain=system.cpu.clk_domain +coreid=99 +dcache=system.ruby.l1_cntrl0.cacheMemory +dcache_hit_latency=1 +deadlock_threshold=500000 +default_p_state=UNDEFINED +eventq_index=0 +garnet_standalone=false +icache=system.ruby.l1_cntrl0.cacheMemory +icache_hit_latency=1 +is_cpu_sequencer=true +max_outstanding_requests=16 +no_retry_on_stall=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null +ruby_system=system.ruby +support_data_reqs=true +support_inst_reqs=true +system=system +using_ruby_tester=false +version=0 +slave=system.cpu.icache_port system.cpu.dcache_port + +[system.ruby.memctrl_clk_domain] +type=DerivedClockDomain +clk_divider=3 +clk_domain=system.ruby.clk_domain +eventq_index=0 + +[system.ruby.network] +type=SimpleNetwork +children=ext_links0 ext_links1 int_link_buffers00 int_link_buffers01 int_link_buffers02 int_link_buffers03 int_link_buffers04 int_link_buffers05 int_link_buffers06 int_link_buffers07 int_link_buffers08 int_link_buffers09 int_link_buffers10 int_link_buffers11 int_link_buffers12 int_link_buffers13 int_link_buffers14 int_link_buffers15 int_link_buffers16 int_link_buffers17 int_link_buffers18 int_link_buffers19 int_link_buffers20 int_link_buffers21 int_link_buffers22 int_link_buffers23 int_link_buffers24 int_link_buffers25 int_link_buffers26 int_link_buffers27 int_link_buffers28 int_link_buffers29 int_link_buffers30 int_link_buffers31 int_link_buffers32 int_link_buffers33 int_link_buffers34 int_link_buffers35 int_link_buffers36 int_link_buffers37 int_link_buffers38 int_link_buffers39 int_links0 int_links1 int_links2 int_links3 routers0 routers1 routers2 +adaptive_routing=false +buffer_size=0 +clk_domain=system.ruby.clk_domain +control_msg_size=8 +default_p_state=UNDEFINED +endpoint_bandwidth=1000 +eventq_index=0 +ext_links=system.ruby.network.ext_links0 system.ruby.network.ext_links1 +int_link_buffers=system.ruby.network.int_link_buffers00 system.ruby.network.int_link_buffers01 system.ruby.network.int_link_buffers02 system.ruby.network.int_link_buffers03 system.ruby.network.int_link_buffers04 system.ruby.network.int_link_buffers05 system.ruby.network.int_link_buffers06 system.ruby.network.int_link_buffers07 system.ruby.network.int_link_buffers08 system.ruby.network.int_link_buffers09 system.ruby.network.int_link_buffers10 system.ruby.network.int_link_buffers11 system.ruby.network.int_link_buffers12 system.ruby.network.int_link_buffers13 system.ruby.network.int_link_buffers14 system.ruby.network.int_link_buffers15 system.ruby.network.int_link_buffers16 system.ruby.network.int_link_buffers17 system.ruby.network.int_link_buffers18 system.ruby.network.int_link_buffers19 system.ruby.network.int_link_buffers20 system.ruby.network.int_link_buffers21 system.ruby.network.int_link_buffers22 system.ruby.network.int_link_buffers23 system.ruby.network.int_link_buffers24 system.ruby.network.int_link_buffers25 system.ruby.network.int_link_buffers26 system.ruby.network.int_link_buffers27 system.ruby.network.int_link_buffers28 system.ruby.network.int_link_buffers29 system.ruby.network.int_link_buffers30 system.ruby.network.int_link_buffers31 system.ruby.network.int_link_buffers32 system.ruby.network.int_link_buffers33 system.ruby.network.int_link_buffers34 system.ruby.network.int_link_buffers35 system.ruby.network.int_link_buffers36 system.ruby.network.int_link_buffers37 system.ruby.network.int_link_buffers38 system.ruby.network.int_link_buffers39 +int_links=system.ruby.network.int_links0 system.ruby.network.int_links1 system.ruby.network.int_links2 system.ruby.network.int_links3 +netifs= +number_of_virtual_networks=5 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null +routers=system.ruby.network.routers0 system.ruby.network.routers1 system.ruby.network.routers2 +ruby_system=system.ruby +topology=Crossbar +master=system.ruby.l1_cntrl0.forwardToCache.slave system.ruby.l1_cntrl0.responseToCache.slave system.ruby.dir_cntrl0.requestToDir.slave system.ruby.dir_cntrl0.dmaRequestToDir.slave +slave=system.ruby.l1_cntrl0.requestFromCache.master system.ruby.l1_cntrl0.responseFromCache.master system.ruby.dir_cntrl0.responseFromDir.master system.ruby.dir_cntrl0.dmaResponseFromDir.master system.ruby.dir_cntrl0.forwardFromDir.master + +[system.ruby.network.ext_links0] +type=SimpleExtLink +bandwidth_factor=16 +eventq_index=0 +ext_node=system.ruby.l1_cntrl0 +int_node=system.ruby.network.routers0 +latency=1 +link_id=0 +weight=1 + +[system.ruby.network.ext_links1] +type=SimpleExtLink +bandwidth_factor=16 +eventq_index=0 +ext_node=system.ruby.dir_cntrl0 +int_node=system.ruby.network.routers1 +latency=1 +link_id=1 +weight=1 + +[system.ruby.network.int_link_buffers00] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers01] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers02] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers03] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers04] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers05] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers06] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers07] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers08] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers09] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers10] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers11] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers12] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers13] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers14] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers15] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers16] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers17] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers18] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers19] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers20] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers21] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers22] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers23] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers24] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers25] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers26] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers27] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers28] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers29] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers30] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers31] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers32] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers33] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers34] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers35] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers36] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers37] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers38] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers39] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_links0] +type=SimpleIntLink +bandwidth_factor=16 +dst_inport= +dst_node=system.ruby.network.routers2 +eventq_index=0 +latency=1 +link_id=2 +src_node=system.ruby.network.routers0 +src_outport= +weight=1 + +[system.ruby.network.int_links1] +type=SimpleIntLink +bandwidth_factor=16 +dst_inport= +dst_node=system.ruby.network.routers2 +eventq_index=0 +latency=1 +link_id=3 +src_node=system.ruby.network.routers1 +src_outport= +weight=1 + +[system.ruby.network.int_links2] +type=SimpleIntLink +bandwidth_factor=16 +dst_inport= +dst_node=system.ruby.network.routers0 +eventq_index=0 +latency=1 +link_id=4 +src_node=system.ruby.network.routers2 +src_outport= +weight=1 + +[system.ruby.network.int_links3] +type=SimpleIntLink +bandwidth_factor=16 +dst_inport= +dst_node=system.ruby.network.routers1 +eventq_index=0 +latency=1 +link_id=5 +src_node=system.ruby.network.routers2 +src_outport= +weight=1 + +[system.ruby.network.routers0] +type=Switch +children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14 +clk_domain=system.ruby.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +port_buffers=system.ruby.network.routers0.port_buffers00 system.ruby.network.routers0.port_buffers01 system.ruby.network.routers0.port_buffers02 system.ruby.network.routers0.port_buffers03 system.ruby.network.routers0.port_buffers04 system.ruby.network.routers0.port_buffers05 system.ruby.network.routers0.port_buffers06 system.ruby.network.routers0.port_buffers07 system.ruby.network.routers0.port_buffers08 system.ruby.network.routers0.port_buffers09 system.ruby.network.routers0.port_buffers10 system.ruby.network.routers0.port_buffers11 system.ruby.network.routers0.port_buffers12 system.ruby.network.routers0.port_buffers13 system.ruby.network.routers0.port_buffers14 +power_model=Null +router_id=0 +virt_nets=5 + +[system.ruby.network.routers0.port_buffers00] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers0.port_buffers01] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers0.port_buffers02] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers0.port_buffers03] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers0.port_buffers04] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers0.port_buffers05] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers0.port_buffers06] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers0.port_buffers07] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers0.port_buffers08] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers0.port_buffers09] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers0.port_buffers10] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers0.port_buffers11] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers0.port_buffers12] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers0.port_buffers13] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers0.port_buffers14] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers1] +type=Switch +children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14 +clk_domain=system.ruby.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +port_buffers=system.ruby.network.routers1.port_buffers00 system.ruby.network.routers1.port_buffers01 system.ruby.network.routers1.port_buffers02 system.ruby.network.routers1.port_buffers03 system.ruby.network.routers1.port_buffers04 system.ruby.network.routers1.port_buffers05 system.ruby.network.routers1.port_buffers06 system.ruby.network.routers1.port_buffers07 system.ruby.network.routers1.port_buffers08 system.ruby.network.routers1.port_buffers09 system.ruby.network.routers1.port_buffers10 system.ruby.network.routers1.port_buffers11 system.ruby.network.routers1.port_buffers12 system.ruby.network.routers1.port_buffers13 system.ruby.network.routers1.port_buffers14 +power_model=Null +router_id=1 +virt_nets=5 + +[system.ruby.network.routers1.port_buffers00] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers1.port_buffers01] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers1.port_buffers02] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers1.port_buffers03] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers1.port_buffers04] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers1.port_buffers05] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers1.port_buffers06] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers1.port_buffers07] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers1.port_buffers08] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers1.port_buffers09] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers1.port_buffers10] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers1.port_buffers11] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers1.port_buffers12] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers1.port_buffers13] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers1.port_buffers14] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2] +type=Switch +children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14 port_buffers15 port_buffers16 port_buffers17 port_buffers18 port_buffers19 +clk_domain=system.ruby.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +port_buffers=system.ruby.network.routers2.port_buffers00 system.ruby.network.routers2.port_buffers01 system.ruby.network.routers2.port_buffers02 system.ruby.network.routers2.port_buffers03 system.ruby.network.routers2.port_buffers04 system.ruby.network.routers2.port_buffers05 system.ruby.network.routers2.port_buffers06 system.ruby.network.routers2.port_buffers07 system.ruby.network.routers2.port_buffers08 system.ruby.network.routers2.port_buffers09 system.ruby.network.routers2.port_buffers10 system.ruby.network.routers2.port_buffers11 system.ruby.network.routers2.port_buffers12 system.ruby.network.routers2.port_buffers13 system.ruby.network.routers2.port_buffers14 system.ruby.network.routers2.port_buffers15 system.ruby.network.routers2.port_buffers16 system.ruby.network.routers2.port_buffers17 system.ruby.network.routers2.port_buffers18 system.ruby.network.routers2.port_buffers19 +power_model=Null +router_id=2 +virt_nets=5 + +[system.ruby.network.routers2.port_buffers00] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers01] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers02] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers03] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers04] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers05] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers06] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers07] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers08] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers09] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers10] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers11] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers12] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers13] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers14] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers15] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers16] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers17] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers18] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers19] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.sys_port_proxy] +type=RubyPortProxy +clk_domain=system.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +is_cpu_sequencer=true +no_retry_on_stall=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null +ruby_system=system.ruby +support_data_reqs=true +support_inst_reqs=true +system=system +using_ruby_tester=false +version=0 +slave=system.system_port + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-timing-ruby/config.json b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-timing-ruby/config.json new file mode 100644 index 000000000..10ddc0f69 --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-timing-ruby/config.json @@ -0,0 +1,1734 @@ +{ + "name": null, + "sim_quantum": 0, + "system": { + "kernel": "", + "mmap_using_noreserve": false, + "kernel_addr_check": true, + "symbolfile": "", + "readfile": "", + "thermal_model": null, + "cxx_class": "System", + "work_begin_cpu_id_exit": -1, + "load_offset": 0, + "work_begin_exit_count": 0, + "p_state_clk_gate_min": 1, + "memories": [ + "system.mem_ctrls" + ], + "work_begin_ckpt_count": 0, + "clk_domain": { + "name": "clk_domain", + "clock": [ + 1 + ], + "init_perf_level": 0, + "voltage_domain": "system.voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "mem_ranges": [ + "0:268435455:0:0:0:0" + ], + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000, + "dvfs_handler": { + "enable": false, + "name": "dvfs_handler", + "sys_clk_domain": "system.clk_domain", + "transition_latency": 100000, + "eventq_index": 0, + "cxx_class": "DVFSHandler", + "domains": [], + "path": "system.dvfs_handler", + "type": "DVFSHandler" + }, + "work_end_exit_count": 0, + "type": "System", + "voltage_domain": { + "name": "voltage_domain", + "eventq_index": 0, + "voltage": [ + "1.0" + ], + "cxx_class": "VoltageDomain", + "path": "system.voltage_domain", + "type": "VoltageDomain" + }, + "cache_line_size": 64, + "boot_osflags": "a", + "system_port": { + "peer": "system.sys_port_proxy.slave[0]", + "role": "MASTER" + }, + "sys_port_proxy": { + "system": "system", + "support_inst_reqs": true, + "slave": { + "peer": [ + "system.system_port" + ], + "role": "SLAVE" + }, + "name": "sys_port_proxy", + "p_state_clk_gate_min": 1, + "no_retry_on_stall": false, + "p_state_clk_gate_bins": 20, + "support_data_reqs": true, + "cxx_class": "RubyPortProxy", + "clk_domain": "system.clk_domain", + "power_model": null, + "is_cpu_sequencer": true, + "version": 0, + "eventq_index": 0, + "using_ruby_tester": false, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000, + "path": "system.sys_port_proxy", + "type": "RubyPortProxy", + "ruby_system": "system.ruby" + }, + "power_model": null, + "work_cpus_ckpt_count": 0, + "thermal_components": [], + "path": "system", + "ruby": { + "all_instructions": false, + "memory_size_bits": 48, + "cxx_class": "RubySystem", + "l1_cntrl0": { + "requestFromCache": { + "ordered": true, + "name": "requestFromCache", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "master": { + "peer": "system.ruby.network.slave[0]", + "role": "MASTER" + }, + "buffer_size": 0, + "path": "system.ruby.l1_cntrl0.requestFromCache", + "type": "MessageBuffer" + }, + "cxx_class": "L1Cache_Controller", + "forwardToCache": { + "ordered": true, + "name": "forwardToCache", + "cxx_class": "MessageBuffer", + "slave": { + "peer": "system.ruby.network.master[0]", + "role": "SLAVE" + }, + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.l1_cntrl0.forwardToCache", + "type": "MessageBuffer" + }, + "system": "system", + "cluster_id": 0, + "sequencer": { + "no_retry_on_stall": false, + "deadlock_threshold": 500000, + "using_ruby_tester": false, + "system": "system", + "dcache": "system.ruby.l1_cntrl0.cacheMemory", + "cxx_class": "Sequencer", + "garnet_standalone": false, + "clk_domain": "system.cpu.clk_domain", + "icache_hit_latency": 1, + "version": 0, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000, + "type": "RubySequencer", + "icache": "system.ruby.l1_cntrl0.cacheMemory", + "slave": { + "peer": [ + "system.cpu.icache_port", + "system.cpu.dcache_port" + ], + "role": "SLAVE" + }, + "p_state_clk_gate_min": 1, + "power_model": null, + "coreid": 99, + "path": "system.ruby.l1_cntrl0.sequencer", + "ruby_system": "system.ruby", + "support_inst_reqs": true, + "name": "sequencer", + "max_outstanding_requests": 16, + "p_state_clk_gate_bins": 20, + "dcache_hit_latency": 1, + "support_data_reqs": true, + "is_cpu_sequencer": true + }, + "type": "L1Cache_Controller", + "issue_latency": 2, + "recycle_latency": 10, + "clk_domain": "system.cpu.clk_domain", + "version": 0, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000, + "number_of_TBEs": 256, + "p_state_clk_gate_min": 1, + "responseToCache": { + "ordered": true, + "name": "responseToCache", + "cxx_class": "MessageBuffer", + "slave": { + "peer": "system.ruby.network.master[1]", + "role": "SLAVE" + }, + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.l1_cntrl0.responseToCache", + "type": "MessageBuffer" + }, + "transitions_per_cycle": 4, + "responseFromCache": { + "ordered": true, + "name": "responseFromCache", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "master": { + "peer": "system.ruby.network.slave[1]", + "role": "MASTER" + }, + "buffer_size": 0, + "path": "system.ruby.l1_cntrl0.responseFromCache", + "type": "MessageBuffer" + }, + "power_model": null, + "cache_response_latency": 12, + "buffer_size": 0, + "send_evictions": false, + "cacheMemory": { + "size": 256, + "resourceStalls": false, + "is_icache": false, + "name": "cacheMemory", + "eventq_index": 0, + "dataAccessLatency": 1, + "tagArrayBanks": 1, + "tagAccessLatency": 1, + "replacement_policy": { + "name": "replacement_policy", + "eventq_index": 0, + "assoc": 2, + "cxx_class": "PseudoLRUPolicy", + "path": "system.ruby.l1_cntrl0.cacheMemory.replacement_policy", + "block_size": 64, + "type": "PseudoLRUReplacementPolicy", + "size": 256 + }, + "assoc": 2, + "start_index_bit": 6, + "cxx_class": "CacheMemory", + "path": "system.ruby.l1_cntrl0.cacheMemory", + "block_size": 0, + "type": "RubyCache", + "dataArrayBanks": 1, + "ruby_system": "system.ruby" + }, + "ruby_system": "system.ruby", + "name": "l1_cntrl0", + "p_state_clk_gate_bins": 20, + "mandatoryQueue": { + "ordered": false, + "name": "mandatoryQueue", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.l1_cntrl0.mandatoryQueue", + "type": "MessageBuffer" + }, + "path": "system.ruby.l1_cntrl0" + }, + "network": { + "int_link_buffers": [ + { + "ordered": true, + "name": "int_link_buffers00", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers00", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers01", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers01", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers02", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers02", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers03", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers03", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers04", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers04", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers05", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers05", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers06", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers06", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers07", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers07", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers08", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers08", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers09", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers09", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers10", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers10", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers11", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers11", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers12", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers12", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers13", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers13", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers14", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers14", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers15", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers15", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers16", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers16", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers17", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers17", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers18", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers18", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers19", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers19", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers20", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers20", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers21", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers21", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers22", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers22", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers23", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers23", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers24", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers24", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers25", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers25", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers26", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers26", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers27", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers27", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers28", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers28", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers29", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers29", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers30", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers30", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers31", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers31", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers32", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers32", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers33", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers33", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers34", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers34", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers35", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers35", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers36", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers36", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers37", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers37", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers38", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers38", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers39", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers39", + "type": "MessageBuffer" + } + ], + "cxx_class": "SimpleNetwork", + "clk_domain": "system.ruby.clk_domain", + "adaptive_routing": false, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000, + "master": { + "peer": [ + "system.ruby.l1_cntrl0.forwardToCache.slave", + "system.ruby.l1_cntrl0.responseToCache.slave", + "system.ruby.dir_cntrl0.requestToDir.slave", + "system.ruby.dir_cntrl0.dmaRequestToDir.slave" + ], + "role": "MASTER" + }, + "topology": "Crossbar", + "type": "SimpleNetwork", + "slave": { + "peer": [ + "system.ruby.l1_cntrl0.requestFromCache.master", + "system.ruby.l1_cntrl0.responseFromCache.master", + "system.ruby.dir_cntrl0.responseFromDir.master", + "system.ruby.dir_cntrl0.dmaResponseFromDir.master", + "system.ruby.dir_cntrl0.forwardFromDir.master" + ], + "role": "SLAVE" + }, + "p_state_clk_gate_min": 1, + "int_links": [ + { + "latency": 1, + "name": "int_links0", + "weight": 1, + "src_node": "system.ruby.network.routers0", + "dst_inport": "", + "link_id": 2, + "dst_node": "system.ruby.network.routers2", + "eventq_index": 0, + "src_outport": "", + "cxx_class": "SimpleIntLink", + "path": "system.ruby.network.int_links0", + "type": "SimpleIntLink", + "bandwidth_factor": 16 + }, + { + "latency": 1, + "name": "int_links1", + "weight": 1, + "src_node": "system.ruby.network.routers1", + "dst_inport": "", + "link_id": 3, + "dst_node": "system.ruby.network.routers2", + "eventq_index": 0, + "src_outport": "", + "cxx_class": "SimpleIntLink", + "path": "system.ruby.network.int_links1", + "type": "SimpleIntLink", + "bandwidth_factor": 16 + }, + { + "latency": 1, + "name": "int_links2", + "weight": 1, + "src_node": "system.ruby.network.routers2", + "dst_inport": "", + "link_id": 4, + "dst_node": "system.ruby.network.routers0", + "eventq_index": 0, + "src_outport": "", + "cxx_class": "SimpleIntLink", + "path": "system.ruby.network.int_links2", + "type": "SimpleIntLink", + "bandwidth_factor": 16 + }, + { + "latency": 1, + "name": "int_links3", + "weight": 1, + "src_node": "system.ruby.network.routers2", + "dst_inport": "", + "link_id": 5, + "dst_node": "system.ruby.network.routers1", + "eventq_index": 0, + "src_outport": "", + "cxx_class": "SimpleIntLink", + "path": "system.ruby.network.int_links3", + "type": "SimpleIntLink", + "bandwidth_factor": 16 + } + ], + "routers": [ + { + "router_id": 0, + "latency": 1, + "name": "routers0", + "p_state_clk_gate_min": 1, + "virt_nets": 5, + "p_state_clk_gate_bins": 20, + "cxx_class": "Switch", + "clk_domain": "system.ruby.clk_domain", + "power_model": null, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000, + "path": "system.ruby.network.routers0", + "type": "Switch", + "port_buffers": [ + { + "ordered": true, + "name": "port_buffers00", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers0.port_buffers00", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers01", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers0.port_buffers01", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers02", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers0.port_buffers02", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers03", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers0.port_buffers03", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers04", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers0.port_buffers04", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers05", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers0.port_buffers05", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers06", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers0.port_buffers06", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers07", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers0.port_buffers07", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers08", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers0.port_buffers08", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers09", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers0.port_buffers09", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers10", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers0.port_buffers10", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers11", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers0.port_buffers11", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers12", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers0.port_buffers12", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers13", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers0.port_buffers13", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers14", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers0.port_buffers14", + "type": "MessageBuffer" + } + ] + }, + { + "router_id": 1, + "latency": 1, + "name": "routers1", + "p_state_clk_gate_min": 1, + "virt_nets": 5, + "p_state_clk_gate_bins": 20, + "cxx_class": "Switch", + "clk_domain": "system.ruby.clk_domain", + "power_model": null, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000, + "path": "system.ruby.network.routers1", + "type": "Switch", + "port_buffers": [ + { + "ordered": true, + "name": "port_buffers00", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers1.port_buffers00", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers01", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers1.port_buffers01", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers02", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers1.port_buffers02", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers03", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers1.port_buffers03", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers04", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers1.port_buffers04", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers05", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers1.port_buffers05", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers06", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers1.port_buffers06", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers07", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers1.port_buffers07", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers08", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers1.port_buffers08", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers09", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers1.port_buffers09", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers10", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers1.port_buffers10", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers11", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers1.port_buffers11", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers12", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers1.port_buffers12", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers13", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers1.port_buffers13", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers14", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers1.port_buffers14", + "type": "MessageBuffer" + } + ] + }, + { + "router_id": 2, + "latency": 1, + "name": "routers2", + "p_state_clk_gate_min": 1, + "virt_nets": 5, + "p_state_clk_gate_bins": 20, + "cxx_class": "Switch", + "clk_domain": "system.ruby.clk_domain", + "power_model": null, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000, + "path": "system.ruby.network.routers2", + "type": "Switch", + "port_buffers": [ + { + "ordered": true, + "name": "port_buffers00", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers2.port_buffers00", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers01", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers2.port_buffers01", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers02", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers2.port_buffers02", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers03", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers2.port_buffers03", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers04", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers2.port_buffers04", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers05", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers2.port_buffers05", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers06", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers2.port_buffers06", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers07", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers2.port_buffers07", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers08", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers2.port_buffers08", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers09", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers2.port_buffers09", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers10", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers2.port_buffers10", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers11", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers2.port_buffers11", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers12", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers2.port_buffers12", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers13", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers2.port_buffers13", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers14", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers2.port_buffers14", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers15", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers2.port_buffers15", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers16", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers2.port_buffers16", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers17", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers2.port_buffers17", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers18", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers2.port_buffers18", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers19", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers2.port_buffers19", + "type": "MessageBuffer" + } + ] + } + ], + "power_model": null, + "netifs": [], + "control_msg_size": 8, + "buffer_size": 0, + "endpoint_bandwidth": 1000, + "ruby_system": "system.ruby", + "name": "network", + "p_state_clk_gate_bins": 20, + "ext_links": [ + { + "latency": 1, + "name": "ext_links0", + "weight": 1, + "ext_node": "system.ruby.l1_cntrl0", + "link_id": 0, + "eventq_index": 0, + "cxx_class": "SimpleExtLink", + "path": "system.ruby.network.ext_links0", + "int_node": "system.ruby.network.routers0", + "type": "SimpleExtLink", + "bandwidth_factor": 16 + }, + { + "latency": 1, + "name": "ext_links1", + "weight": 1, + "ext_node": "system.ruby.dir_cntrl0", + "link_id": 1, + "eventq_index": 0, + "cxx_class": "SimpleExtLink", + "path": "system.ruby.network.ext_links1", + "int_node": "system.ruby.network.routers1", + "type": "SimpleExtLink", + "bandwidth_factor": 16 + } + ], + "number_of_virtual_networks": 5, + "path": "system.ruby.network" + }, + "clk_domain": { + "name": "clk_domain", + "clock": [ + 1 + ], + "init_perf_level": 0, + "voltage_domain": "system.voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.ruby.clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "randomization": false, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000, + "phys_mem": null, + "type": "RubySystem", + "p_state_clk_gate_min": 1, + "hot_lines": false, + "power_model": null, + "path": "system.ruby", + "memctrl_clk_domain": { + "name": "memctrl_clk_domain", + "clk_domain": "system.ruby.clk_domain", + "eventq_index": 0, + "cxx_class": "DerivedClockDomain", + "path": "system.ruby.memctrl_clk_domain", + "type": "DerivedClockDomain", + "clk_divider": 3 + }, + "name": "ruby", + "p_state_clk_gate_bins": 20, + "block_size_bytes": 64, + "access_backing_store": false, + "number_of_virtual_networks": 5, + "num_of_sequencers": 1, + "dir_cntrl0": { + "system": "system", + "cluster_id": 0, + "responseFromMemory": { + "ordered": false, + "name": "responseFromMemory", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.dir_cntrl0.responseFromMemory", + "type": "MessageBuffer" + }, + "cxx_class": "Directory_Controller", + "forwardFromDir": { + "ordered": false, + "name": "forwardFromDir", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "master": { + "peer": "system.ruby.network.slave[4]", + "role": "MASTER" + }, + "buffer_size": 0, + "path": "system.ruby.dir_cntrl0.forwardFromDir", + "type": "MessageBuffer" + }, + "dmaRequestToDir": { + "ordered": true, + "name": "dmaRequestToDir", + "cxx_class": "MessageBuffer", + "slave": { + "peer": "system.ruby.network.master[3]", + "role": "SLAVE" + }, + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.dir_cntrl0.dmaRequestToDir", + "type": "MessageBuffer" + }, + "type": "Directory_Controller", + "recycle_latency": 10, + "clk_domain": "system.ruby.clk_domain", + "version": 0, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000, + "directory_latency": 12, + "number_of_TBEs": 256, + "to_memory_controller_latency": 1, + "p_state_clk_gate_min": 1, + "responseFromDir": { + "ordered": false, + "name": "responseFromDir", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "master": { + "peer": "system.ruby.network.slave[2]", + "role": "MASTER" + }, + "buffer_size": 0, + "path": "system.ruby.dir_cntrl0.responseFromDir", + "type": "MessageBuffer" + }, + "transitions_per_cycle": 4, + "memory": { + "peer": "system.mem_ctrls.port", + "role": "MASTER" + }, + "power_model": null, + "buffer_size": 0, + "ruby_system": "system.ruby", + "requestToDir": { + "ordered": true, + "name": "requestToDir", + "cxx_class": "MessageBuffer", + "slave": { + "peer": "system.ruby.network.master[2]", + "role": "SLAVE" + }, + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.dir_cntrl0.requestToDir", + "type": "MessageBuffer" + }, + "dmaResponseFromDir": { + "ordered": true, + "name": "dmaResponseFromDir", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "master": { + "peer": "system.ruby.network.slave[3]", + "role": "MASTER" + }, + "buffer_size": 0, + "path": "system.ruby.dir_cntrl0.dmaResponseFromDir", + "type": "MessageBuffer" + }, + "name": "dir_cntrl0", + "p_state_clk_gate_bins": 20, + "directory": { + "name": "directory", + "version": 0, + "eventq_index": 0, + "cxx_class": "DirectoryMemory", + "path": "system.ruby.dir_cntrl0.directory", + "type": "RubyDirectoryMemory", + "numa_high_bit": 5, + "size": 268435456 + }, + "path": "system.ruby.dir_cntrl0" + } + }, + "work_end_ckpt_count": 0, + "mem_mode": "timing", + "name": "system", + "init_param": 0, + "p_state_clk_gate_bins": 20, + "load_addr_mask": 1099511627775, + "cpu": { + "do_statistics_insts": true, + "numThreads": 1, + "itb": { + "name": "itb", + "eventq_index": 0, + "cxx_class": "RiscvISA::TLB", + "path": "system.cpu.itb", + "type": "RiscvTLB", + "size": 64 + }, + "system": "system", + "function_trace": false, + "do_checkpoint_insts": true, + "cxx_class": "TimingSimpleCPU", + "max_loads_all_threads": 0, + "clk_domain": { + "name": "clk_domain", + "clock": [ + 1 + ], + "init_perf_level": 0, + "voltage_domain": "system.voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.cpu.clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "function_trace_start": 0, + "cpu_id": 0, + "checker": null, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000, + "do_quiesce": true, + "type": "TimingSimpleCPU", + "profile": 0, + "icache_port": { + "peer": "system.ruby.l1_cntrl0.sequencer.slave[0]", + "role": "MASTER" + }, + "p_state_clk_gate_bins": 20, + "p_state_clk_gate_min": 1, + "interrupts": [ + { + "eventq_index": 0, + "path": "system.cpu.interrupts", + "type": "RiscvInterrupts", + "name": "interrupts", + "cxx_class": "RiscvISA::Interrupts" + } + ], + "dcache_port": { + "peer": "system.ruby.l1_cntrl0.sequencer.slave[1]", + "role": "MASTER" + }, + "socket_id": 0, + "power_model": null, + "max_insts_all_threads": 0, + "path": "system.cpu", + "max_loads_any_thread": 0, + "switched_out": false, + "workload": [ + { + "uid": 100, + "pid": 100, + "kvmInSE": false, + "cxx_class": "LiveProcess", + "executable": "/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64f/insttest", + "drivers": [], + "system": "system", + "gid": 100, + "eventq_index": 0, + "env": [], + "input": "cin", + "ppid": 99, + "type": "LiveProcess", + "cwd": "", + "simpoint": 0, + "euid": 100, + "path": "system.cpu.workload", + "max_stack_size": 67108864, + "name": "workload", + "cmd": [ + "insttest" + ], + "errout": "cerr", + "useArchPT": false, + "egid": 100, + "output": "cout" + } + ], + "name": "cpu", + "dtb": { + "name": "dtb", + "eventq_index": 0, + "cxx_class": "RiscvISA::TLB", + "path": "system.cpu.dtb", + "type": "RiscvTLB", + "size": 64 + }, + "simpoint_start_insts": [], + "max_insts_any_thread": 0, + "progress_interval": 0, + "branchPred": null, + "isa": [ + { + "eventq_index": 0, + "path": "system.cpu.isa", + "type": "RiscvISA", + "name": "isa", + "cxx_class": "RiscvISA::ISA" + } + ], + "tracer": { + "eventq_index": 0, + "path": "system.cpu.tracer", + "type": "ExeTracer", + "name": "tracer", + "cxx_class": "Trace::ExeTracer" + } + }, + "multi_thread": false, + "mem_ctrls": [ + { + "static_frontend_latency": 10, + "tRFC": 260, + "activation_limit": 4, + "in_addr_map": true, + "IDD3N2": "0.0", + "tWTR": 8, + "IDD52": "0.0", + "clk_domain": "system.clk_domain", + "channels": 1, + "write_buffer_size": 64, + "device_bus_width": 8, + "VDD": "1.5", + "write_high_thresh_perc": 85, + "cxx_class": "DRAMCtrl", + "bank_groups_per_rank": 0, + "IDD2N2": "0.0", + "port": { + "peer": "system.ruby.dir_cntrl0.memory", + "role": "SLAVE" + }, + "tCCD_L": 0, + "IDD2N": "0.032", + "p_state_clk_gate_min": 1, + "null": false, + "IDD2P1": "0.032", + "eventq_index": 0, + "tRRD": 6, + "tRTW": 3, + "IDD4R": "0.157", + "burst_length": 8, + "tRTP": 8, + "IDD4W": "0.125", + "tWR": 15, + "banks_per_rank": 8, + "devices_per_rank": 8, + "IDD2P02": "0.0", + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000, + "IDD6": "0.02", + "IDD5": "0.235", + "tRCD": 14, + "type": "DRAMCtrl", + "IDD3P02": "0.0", + "tRRD_L": 0, + "IDD0": "0.055", + "IDD62": "0.0", + "min_writes_per_switch": 16, + "mem_sched_policy": "frfcfs", + "IDD02": "0.0", + "IDD2P0": "0.0", + "ranks_per_channel": 2, + "page_policy": "open_adaptive", + "IDD4W2": "0.0", + "tCS": 3, + "power_model": null, + "tCL": 14, + "read_buffer_size": 32, + "conf_table_reported": true, + "tCK": 1, + "tRAS": 35, + "tRP": 14, + "tBURST": 5, + "path": "system.mem_ctrls", + "tXP": 6, + "tXS": 270, + "addr_mapping": "RoRaBaCoCh", + "IDD3P0": "0.0", + "IDD3P1": "0.038", + "IDD3N": "0.038", + "name": "mem_ctrls", + "tXSDLL": 0, + "device_size": 536870912, + "kvm_map": true, + "dll": true, + "tXAW": 30, + "write_low_thresh_perc": 50, + "range": "0:268435455:5:19:0:0", + "VDD2": "0.0", + "IDD2P12": "0.0", + "p_state_clk_gate_bins": 20, + "tXPDLL": 0, + "IDD4R2": "0.0", + "device_rowbuffer_size": 1024, + "static_backend_latency": 10, + "max_accesses_per_row": 16, + "IDD3P12": "0.0", + "tREFI": 7800 + } + ], + "exit_on_work_items": false, + "work_item_id": -1, + "num_work_ids": 16 + }, + "time_sync_period": 100000000, + "eventq_index": 0, + "time_sync_spin_threshold": 100000, + "cxx_class": "Root", + "path": "root", + "time_sync_enable": false, + "type": "Root", + "full_system": false +}
\ No newline at end of file diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-timing-ruby/simerr b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-timing-ruby/simerr new file mode 100755 index 000000000..63b14556f --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-timing-ruby/simerr @@ -0,0 +1,11 @@ +warn: rounding error > tolerance + 1.250000 rounded to 1 +warn: rounding error > tolerance + 1.250000 rounded to 1 +warn: rounding error > tolerance + 1.250000 rounded to 1 +warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes) +warn: Unknown operating system; assuming Linux. +warn: Sockets disabled, not accepting gdb connections +warn: ClockedObject: More than one power state change request encountered within the same simulation tick +warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files! diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-timing-ruby/simout b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-timing-ruby/simout new file mode 100755 index 000000000..5fb7ec2e1 --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-timing-ruby/simout @@ -0,0 +1,121 @@ +Redirecting stdout to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64f/simple-timing-ruby/simout +Redirecting stderr to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64f/simple-timing-ruby/simerr +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled Nov 30 2016 14:33:35 +gem5 started Nov 30 2016 16:18:42 +gem5 executing on zizzer, pid 34083 +command line: /z/powerjg/gem5-upstream/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64f/simple-timing-ruby -re /z/powerjg/gem5-upstream/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64f/simple-timing-ruby + +Global frequency set at 1000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. +clear fsflags: PASS +flw: PASS +fsw: PASS +fmadd.s: PASS +fmadd.s, quiet NaN: PASS +fmadd.s, signaling NaN: PASS +fmadd.s, infinity: PASS +fmadd.s, -infinity: PASS +fmsub.s: PASS +fmsub.s, quiet NaN: PASS +fmsub.s, signaling NaN: PASS +fmsub.s, infinity: PASS +fmsub.s, -infinity: PASS +fmsub.s, subtract infinity: PASS +fnmsub.s: PASS +fnmsub.s, quiet NaN: PASS +fnmsub.s, signaling NaN: PASS +fnmsub.s, infinity: PASS +fnmsub.s, -infinity: PASS +fnmsub.s, subtract infinity: PASS +fnmadd.s: PASS +fnmadd.s, quiet NaN: PASS +fnmadd.s, signaling NaN: PASS +fnmadd.s, infinity: PASS +fnmadd.s, -infinity: PASS +fadd.s: PASS +fadd.s, quiet NaN: PASS +fadd.s, signaling NaN: PASS +fadd.s, infinity: PASS +fadd.s, -infinity: PASS +fsub.s: PASS +fsub.s, quiet NaN: PASS +fsub.s, signaling NaN: PASS +fsub.s, infinity: PASS +fsub.s, -infinity: PASS +fsub.s, subtract infinity: PASS +fmul.s: PASS +fmul.s, quiet NaN: PASS +fmul.s, signaling NaN: PASS +fmul.s, infinity: PASS +fmul.s, -infinity: PASS +fmul.s, 0*infinity: PASS +fmul.s, overflow: PASS +fmul.s, underflow: PASS +fdiv.s: PASS +fdiv.s, quiet NaN: PASS +fdiv.s, signaling NaN: PASS +fdiv.s/0: PASS +fdiv.s/infinity: PASS +fdiv.s, infinity/infinity: PASS +fdiv.s, 0/0: PASS +fdiv.s, infinity/0: PASS +fdiv.s, 0/infinity: PASS +fdiv.s, underflow: PASS +fdiv.s, overflow: PASS +fsqrt.s: PASS +fsqrt.s, NaN: PASS +fsqrt.s, quiet NaN: PASS +fsqrt.s, signaling NaN: PASS +fsqrt.s, infinity: PASS +fsgnj.s, ++: PASS +fsgnj.s, +-: PASS +fsgnj.s, -+: PASS +fsgnj.s, --: PASS +fsgnj.s, quiet NaN: PASS +fsgnj.s, signaling NaN: PASS +fsgnj.s, inject NaN: PASS +fsgnj.s, inject -NaN: PASS +fsgnjn.s, ++: PASS +fsgnjn.s, +-: PASS +fsgnjn.s, -+: PASS +fsgnjn.s, --: PASS +fsgnjn.s, quiet NaN: PASS +fsgnjn.s, signaling NaN: PASS +fsgnjn.s, inject NaN: PASS +fsgnjn.s, inject NaN: PASS +fsgnjx.s, ++: PASS +fsgnjx.s, +-: PASS +fsgnjx.s, -+: PASS +fsgnjx.s, --: PASS +fsgnjx.s, quiet NaN: PASS +fsgnjx.s, signaling NaN: PASS +fsgnjx.s, inject NaN: PASS +fsgnjx.s, inject -NaN: PASS +fmin.s: PASS +fmin.s, -infinity: PASS +fmin.s, infinity: PASS +fmin.s, quiet NaN first: PASS +fmin.s, quiet NaN second: PASS +fmin.s, quiet NaN both: PASS +fmin.s, signaling NaN first: PASS +fmin.s, signaling NaN second: PASS +fmin.s, signaling NaN both: PASS +fmax.s: PASS +fmax.s, -infinity: PASS +fmax.s, infinity: PASS +fmax.s, quiet NaN first: PASS +fmax.s, quiet NaN second: PASS +fmax.s, quiet NaN both: PASS +fmax.s, signaling NaN first: PASS +fmax.s, signaling NaN second: PASS +fmax.s, signaling NaN both: PASS +fcvt.w.s, truncate positive: PASS +fcvt.w.s, truncate negative: PASS +fcvt.w.s, 0.0: PASS +fcvt.w.s, -0.0: PASS +fcvt.w.s, overflow: [1;31mFAIL[0m (expected 2147483647; found -2147483648) +Exiting @ tick 4665394 because target called exit() diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-timing-ruby/stats.txt b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-timing-ruby/stats.txt new file mode 100644 index 000000000..2726406d4 --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-timing-ruby/stats.txt @@ -0,0 +1,644 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.004665 # Number of seconds simulated +sim_ticks 4665394 # Number of ticks simulated +final_tick 4665394 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000 # Frequency of simulated ticks +host_inst_rate 17585 # Simulator instruction rate (inst/s) +host_op_rate 17585 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 362753 # Simulator tick rate (ticks/s) +host_mem_usage 412420 # Number of bytes of host memory used +host_seconds 12.86 # Real time elapsed on the host +sim_insts 226159 # Number of instructions simulated +sim_ops 226159 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1 # Clock period in ticks +system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 4665394 # Cumulative time (in ticks) in various power states +system.mem_ctrls.bytes_read::ruby.dir_cntrl0 4623808 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::total 4623808 # Number of bytes read from this memory +system.mem_ctrls.bytes_written::ruby.dir_cntrl0 4623552 # Number of bytes written to this memory +system.mem_ctrls.bytes_written::total 4623552 # Number of bytes written to this memory +system.mem_ctrls.num_reads::ruby.dir_cntrl0 72247 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::total 72247 # Number of read requests responded to by this memory +system.mem_ctrls.num_writes::ruby.dir_cntrl0 72243 # Number of write requests responded to by this memory +system.mem_ctrls.num_writes::total 72243 # Number of write requests responded to by this memory +system.mem_ctrls.bw_read::ruby.dir_cntrl0 991086283 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::total 991086283 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::ruby.dir_cntrl0 991031411 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::total 991031411 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_total::ruby.dir_cntrl0 1982117695 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::total 1982117695 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.readReqs 72247 # Number of read requests accepted +system.mem_ctrls.writeReqs 72243 # Number of write requests accepted +system.mem_ctrls.readBursts 72247 # Number of DRAM read bursts, including those serviced by the write queue +system.mem_ctrls.writeBursts 72243 # Number of DRAM write bursts, including those merged in the write queue +system.mem_ctrls.bytesReadDRAM 2375168 # Total number of bytes read from DRAM +system.mem_ctrls.bytesReadWrQ 2248640 # Total number of bytes read from write queue +system.mem_ctrls.bytesWritten 2474112 # Total number of bytes written to DRAM +system.mem_ctrls.bytesReadSys 4623808 # Total read bytes from the system interface side +system.mem_ctrls.bytesWrittenSys 4623552 # Total written bytes from the system interface side +system.mem_ctrls.servicedByWrQ 35135 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrls.mergedWrBursts 33568 # Number of DRAM write bursts merged with an existing one +system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.mem_ctrls.perBankRdBursts::0 360 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::1 641 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::2 33 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::3 2702 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::4 5567 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::5 5413 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::6 5211 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::7 1018 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::8 201 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::9 679 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::10 1777 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::11 10251 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::12 1439 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::13 1161 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::14 39 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::15 620 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::0 374 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::1 689 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::2 35 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::3 2847 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::4 5733 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::5 5572 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::6 5809 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::7 1085 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::8 201 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::9 742 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::10 1831 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::11 10392 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::12 1454 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::13 1229 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::14 39 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::15 626 # Per bank write bursts +system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry +system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry +system.mem_ctrls.totGap 4665243 # Total gap between requests +system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::6 72247 # Read request sizes (log2) +system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::6 72243 # Write request sizes (log2) +system.mem_ctrls.rdQLenPdf::0 37112 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::1 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::2 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::4 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::0 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::1 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::2 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::3 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::4 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::5 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::6 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::7 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::8 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::9 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::10 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::11 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::15 208 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::16 255 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::17 2030 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::18 2392 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::19 2414 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::20 2512 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::21 2548 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::22 2499 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::23 2385 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::24 2380 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::25 2383 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::26 2379 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::27 2380 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::28 2379 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::29 2379 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::30 2379 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::31 2379 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::32 2379 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.mem_ctrls.bytesPerActivate::samples 13232 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::mean 366.340992 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::gmean 230.810737 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::stdev 342.245951 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::0-127 3082 23.29% 23.29% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::128-255 3681 27.82% 51.11% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::256-383 1764 13.33% 64.44% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::384-511 976 7.38% 71.82% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::512-639 696 5.26% 77.08% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::640-767 455 3.44% 80.52% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::768-895 307 2.32% 82.84% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::896-1023 275 2.08% 84.92% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::1024-1151 1996 15.08% 100.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::total 13232 # Bytes accessed per row activation +system.mem_ctrls.rdPerTurnAround::samples 2379 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::mean 15.599412 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::gmean 15.547106 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::stdev 1.309736 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::12-13 94 3.95% 3.95% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::14-15 1021 42.92% 46.87% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::16-17 1131 47.54% 94.41% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::18-19 122 5.13% 99.54% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::20-21 10 0.42% 99.96% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::36-37 1 0.04% 100.00% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::total 2379 # Reads before turning the bus around for writes +system.mem_ctrls.wrPerTurnAround::samples 2379 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::mean 16.249685 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::gmean 16.232515 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::stdev 0.782399 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::16 2139 89.91% 89.91% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::17 18 0.76% 90.67% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::18 109 4.58% 95.25% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::19 94 3.95% 99.20% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::20 19 0.80% 100.00% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::total 2379 # Writes before turning the bus around for reads +system.mem_ctrls.totQLat 719075 # Total ticks spent queuing +system.mem_ctrls.totMemAccLat 1424203 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.totBusLat 185560 # Total ticks spent in databus transfers +system.mem_ctrls.avgQLat 19.38 # Average queueing delay per DRAM burst +system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst +system.mem_ctrls.avgMemAccLat 38.38 # Average memory access latency per DRAM burst +system.mem_ctrls.avgRdBW 509.10 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrls.avgWrBW 530.31 # Average achieved write bandwidth in MiByte/s +system.mem_ctrls.avgRdBWSys 991.09 # Average system read bandwidth in MiByte/s +system.mem_ctrls.avgWrBWSys 991.03 # Average system write bandwidth in MiByte/s +system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.mem_ctrls.busUtil 8.12 # Data bus utilization in percentage +system.mem_ctrls.busUtilRead 3.98 # Data bus utilization in percentage for reads +system.mem_ctrls.busUtilWrite 4.14 # Data bus utilization in percentage for writes +system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing +system.mem_ctrls.avgWrQLen 25.97 # Average write queue length when enqueuing +system.mem_ctrls.readRowHits 27462 # Number of row buffer hits during reads +system.mem_ctrls.writeRowHits 35070 # Number of row buffer hits during writes +system.mem_ctrls.readRowHitRate 74.00 # Row buffer hit rate for reads +system.mem_ctrls.writeRowHitRate 90.68 # Row buffer hit rate for writes +system.mem_ctrls.avgGap 32.29 # Average gap between requests +system.mem_ctrls.pageHitRate 82.51 # Row buffer hit rate, read and write combined +system.mem_ctrls_0.actEnergy 60632880 # Energy for activate commands per rank (pJ) +system.mem_ctrls_0.preEnergy 32801496 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_0.readEnergy 239275680 # Energy for read commands per rank (pJ) +system.mem_ctrls_0.writeEnergy 184946688 # Energy for write commands per rank (pJ) +system.mem_ctrls_0.refreshEnergy 366325440.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_0.actBackEnergy 608748144 # Energy for active background per rank (pJ) +system.mem_ctrls_0.preBackEnergy 8669568 # Energy for precharge background per rank (pJ) +system.mem_ctrls_0.actPowerDownEnergy 1381360344 # Energy for active power-down per rank (pJ) +system.mem_ctrls_0.prePowerDownEnergy 69824640 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls_0.selfRefreshEnergy 28732560 # Energy for self refresh per rank (pJ) +system.mem_ctrls_0.totalEnergy 2981317440 # Total energy per rank (pJ) +system.mem_ctrls_0.averagePower 639.028009 # Core power per rank (mW) +system.mem_ctrls_0.totalIdleTime 3307806 # Total Idle time Per DRAM Rank +system.mem_ctrls_0.memoryStateTime::IDLE 5774 # Time in different power states +system.mem_ctrls_0.memoryStateTime::REF 155020 # Time in different power states +system.mem_ctrls_0.memoryStateTime::SREF 96709 # Time in different power states +system.mem_ctrls_0.memoryStateTime::PRE_PDN 181835 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT 1196757 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT_PDN 3029299 # Time in different power states +system.mem_ctrls_1.actEnergy 33886440 # Energy for activate commands per rank (pJ) +system.mem_ctrls_1.preEnergy 18326952 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_1.readEnergy 184691808 # Energy for read commands per rank (pJ) +system.mem_ctrls_1.writeEnergy 137924928 # Energy for write commands per rank (pJ) +system.mem_ctrls_1.refreshEnergy 348500880.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_1.actBackEnergy 590211744 # Energy for active background per rank (pJ) +system.mem_ctrls_1.preBackEnergy 11048832 # Energy for precharge background per rank (pJ) +system.mem_ctrls_1.actPowerDownEnergy 1320078504 # Energy for active power-down per rank (pJ) +system.mem_ctrls_1.prePowerDownEnergy 60484992 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls_1.selfRefreshEnergy 72883440 # Energy for self refresh per rank (pJ) +system.mem_ctrls_1.totalEnergy 2778038520 # Total energy per rank (pJ) +system.mem_ctrls_1.averagePower 595.456358 # Core power per rank (mW) +system.mem_ctrls_1.totalIdleTime 3342297 # Total Idle time Per DRAM Rank +system.mem_ctrls_1.memoryStateTime::IDLE 12341 # Time in different power states +system.mem_ctrls_1.memoryStateTime::REF 147456 # Time in different power states +system.mem_ctrls_1.memoryStateTime::SREF 289875 # Time in different power states +system.mem_ctrls_1.memoryStateTime::PRE_PDN 157513 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT 1163300 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT_PDN 2894909 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 4665394 # Cumulative time (in ticks) in various power states +system.cpu.clk_domain.clock 1 # Clock period in ticks +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 115 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 4665394 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 4665394 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 226159 # Number of instructions committed +system.cpu.committedOps 226159 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 225992 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 862 # Number of float alu accesses +system.cpu.num_func_calls 16616 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 33789 # number of instructions that are conditional controls +system.cpu.num_int_insts 225992 # number of integer instructions +system.cpu.num_fp_insts 862 # number of float instructions +system.cpu.num_int_register_reads 298589 # number of times the integer registers were read +system.cpu.num_int_register_writes 154866 # number of times the integer registers were written +system.cpu.num_fp_register_reads 733 # number of times the floating registers were read +system.cpu.num_fp_register_writes 588 # number of times the floating registers were written +system.cpu.num_mem_refs 88941 # number of memory refs +system.cpu.num_load_insts 51711 # Number of load instructions +system.cpu.num_store_insts 37230 # Number of store instructions +system.cpu.num_idle_cycles 0 # Number of idle cycles +system.cpu.num_busy_cycles 4665394 # Number of busy cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.Branches 50405 # Number of branches fetched +system.cpu.op_class::No_OpClass 117 0.05% 0.05% # Class of executed instruction +system.cpu.op_class::IntAlu 136540 60.34% 60.39% # Class of executed instruction +system.cpu.op_class::IntMult 325 0.14% 60.54% # Class of executed instruction +system.cpu.op_class::IntDiv 40 0.02% 60.56% # Class of executed instruction +system.cpu.op_class::FloatAdd 104 0.05% 60.60% # Class of executed instruction +system.cpu.op_class::FloatCmp 119 0.05% 60.65% # Class of executed instruction +system.cpu.op_class::FloatCvt 43 0.02% 60.67% # Class of executed instruction +system.cpu.op_class::FloatMult 30 0.01% 60.69% # Class of executed instruction +system.cpu.op_class::FloatMultAcc 0 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::FloatDiv 11 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::FloatMisc 0 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::FloatSqrt 5 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::MemRead 51297 22.67% 83.36% # Class of executed instruction +system.cpu.op_class::MemWrite 37094 16.39% 99.76% # Class of executed instruction +system.cpu.op_class::FloatMemRead 414 0.18% 99.94% # Class of executed instruction +system.cpu.op_class::FloatMemWrite 136 0.06% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 226275 # Class of executed instruction +system.ruby.clk_domain.clock 1 # Clock period in ticks +system.ruby.pwrStateResidencyTicks::UNDEFINED 4665394 # Cumulative time (in ticks) in various power states +system.ruby.delayHist::bucket_size 1 # delay histogram for all message +system.ruby.delayHist::max_bucket 9 # delay histogram for all message +system.ruby.delayHist::samples 144490 # delay histogram for all message +system.ruby.delayHist | 144490 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message +system.ruby.delayHist::total 144490 # delay histogram for all message +system.ruby.outstanding_req_hist_seqr::bucket_size 1 +system.ruby.outstanding_req_hist_seqr::max_bucket 9 +system.ruby.outstanding_req_hist_seqr::samples 315216 +system.ruby.outstanding_req_hist_seqr::mean 1 +system.ruby.outstanding_req_hist_seqr::gmean 1 +system.ruby.outstanding_req_hist_seqr | 0 0.00% 0.00% | 315216 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.outstanding_req_hist_seqr::total 315216 +system.ruby.latency_hist_seqr::bucket_size 64 +system.ruby.latency_hist_seqr::max_bucket 639 +system.ruby.latency_hist_seqr::samples 315215 +system.ruby.latency_hist_seqr::mean 13.800673 +system.ruby.latency_hist_seqr::gmean 2.449814 +system.ruby.latency_hist_seqr::stdev 29.448647 +system.ruby.latency_hist_seqr | 279385 88.63% 88.63% | 33252 10.55% 99.18% | 1716 0.54% 99.73% | 307 0.10% 99.82% | 278 0.09% 99.91% | 236 0.07% 99.99% | 20 0.01% 99.99% | 8 0.00% 100.00% | 0 0.00% 100.00% | 13 0.00% 100.00% +system.ruby.latency_hist_seqr::total 315215 +system.ruby.hit_latency_hist_seqr::bucket_size 1 +system.ruby.hit_latency_hist_seqr::max_bucket 9 +system.ruby.hit_latency_hist_seqr::samples 242968 +system.ruby.hit_latency_hist_seqr::mean 1 +system.ruby.hit_latency_hist_seqr::gmean 1 +system.ruby.hit_latency_hist_seqr | 0 0.00% 0.00% | 242968 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.hit_latency_hist_seqr::total 242968 +system.ruby.miss_latency_hist_seqr::bucket_size 64 +system.ruby.miss_latency_hist_seqr::max_bucket 639 +system.ruby.miss_latency_hist_seqr::samples 72247 +system.ruby.miss_latency_hist_seqr::mean 56.849572 +system.ruby.miss_latency_hist_seqr::gmean 49.864909 +system.ruby.miss_latency_hist_seqr::stdev 37.140999 +system.ruby.miss_latency_hist_seqr | 36417 50.41% 50.41% | 33252 46.03% 96.43% | 1716 2.38% 98.81% | 307 0.42% 99.23% | 278 0.38% 99.62% | 236 0.33% 99.94% | 20 0.03% 99.97% | 8 0.01% 99.98% | 0 0.00% 99.98% | 13 0.02% 100.00% +system.ruby.miss_latency_hist_seqr::total 72247 +system.ruby.Directory.incomplete_times_seqr 72246 +system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 4665394 # Cumulative time (in ticks) in various power states +system.ruby.l1_cntrl0.cacheMemory.demand_hits 242968 # Number of cache demand hits +system.ruby.l1_cntrl0.cacheMemory.demand_misses 72247 # Number of cache demand misses +system.ruby.l1_cntrl0.cacheMemory.demand_accesses 315215 # Number of cache demand accesses +system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 4665394 # Cumulative time (in ticks) in various power states +system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 4665394 # Cumulative time (in ticks) in various power states +system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks +system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 4665394 # Cumulative time (in ticks) in various power states +system.ruby.network.routers0.percent_links_utilized 7.742647 +system.ruby.network.routers0.msg_count.Control::2 72247 +system.ruby.network.routers0.msg_count.Data::2 72243 +system.ruby.network.routers0.msg_count.Response_Data::4 72247 +system.ruby.network.routers0.msg_count.Writeback_Control::3 72243 +system.ruby.network.routers0.msg_bytes.Control::2 577976 +system.ruby.network.routers0.msg_bytes.Data::2 5201496 +system.ruby.network.routers0.msg_bytes.Response_Data::4 5201784 +system.ruby.network.routers0.msg_bytes.Writeback_Control::3 577944 +system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 4665394 # Cumulative time (in ticks) in various power states +system.ruby.network.routers1.percent_links_utilized 7.742647 +system.ruby.network.routers1.msg_count.Control::2 72247 +system.ruby.network.routers1.msg_count.Data::2 72243 +system.ruby.network.routers1.msg_count.Response_Data::4 72247 +system.ruby.network.routers1.msg_count.Writeback_Control::3 72243 +system.ruby.network.routers1.msg_bytes.Control::2 577976 +system.ruby.network.routers1.msg_bytes.Data::2 5201496 +system.ruby.network.routers1.msg_bytes.Response_Data::4 5201784 +system.ruby.network.routers1.msg_bytes.Writeback_Control::3 577944 +system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 4665394 # Cumulative time (in ticks) in various power states +system.ruby.network.routers2.percent_links_utilized 7.742647 +system.ruby.network.routers2.msg_count.Control::2 72247 +system.ruby.network.routers2.msg_count.Data::2 72243 +system.ruby.network.routers2.msg_count.Response_Data::4 72247 +system.ruby.network.routers2.msg_count.Writeback_Control::3 72243 +system.ruby.network.routers2.msg_bytes.Control::2 577976 +system.ruby.network.routers2.msg_bytes.Data::2 5201496 +system.ruby.network.routers2.msg_bytes.Response_Data::4 5201784 +system.ruby.network.routers2.msg_bytes.Writeback_Control::3 577944 +system.ruby.network.pwrStateResidencyTicks::UNDEFINED 4665394 # Cumulative time (in ticks) in various power states +system.ruby.network.msg_count.Control 216741 +system.ruby.network.msg_count.Data 216729 +system.ruby.network.msg_count.Response_Data 216741 +system.ruby.network.msg_count.Writeback_Control 216729 +system.ruby.network.msg_byte.Control 1733928 +system.ruby.network.msg_byte.Data 15604488 +system.ruby.network.msg_byte.Response_Data 15605352 +system.ruby.network.msg_byte.Writeback_Control 1733832 +system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 4665394 # Cumulative time (in ticks) in various power states +system.ruby.network.routers0.throttle0.link_utilization 7.742819 +system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 72247 +system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 72243 +system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 5201784 +system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3 577944 +system.ruby.network.routers0.throttle1.link_utilization 7.742476 +system.ruby.network.routers0.throttle1.msg_count.Control::2 72247 +system.ruby.network.routers0.throttle1.msg_count.Data::2 72243 +system.ruby.network.routers0.throttle1.msg_bytes.Control::2 577976 +system.ruby.network.routers0.throttle1.msg_bytes.Data::2 5201496 +system.ruby.network.routers1.throttle0.link_utilization 7.742476 +system.ruby.network.routers1.throttle0.msg_count.Control::2 72247 +system.ruby.network.routers1.throttle0.msg_count.Data::2 72243 +system.ruby.network.routers1.throttle0.msg_bytes.Control::2 577976 +system.ruby.network.routers1.throttle0.msg_bytes.Data::2 5201496 +system.ruby.network.routers1.throttle1.link_utilization 7.742819 +system.ruby.network.routers1.throttle1.msg_count.Response_Data::4 72247 +system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::3 72243 +system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4 5201784 +system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::3 577944 +system.ruby.network.routers2.throttle0.link_utilization 7.742819 +system.ruby.network.routers2.throttle0.msg_count.Response_Data::4 72247 +system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3 72243 +system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4 5201784 +system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3 577944 +system.ruby.network.routers2.throttle1.link_utilization 7.742476 +system.ruby.network.routers2.throttle1.msg_count.Control::2 72247 +system.ruby.network.routers2.throttle1.msg_count.Data::2 72243 +system.ruby.network.routers2.throttle1.msg_bytes.Control::2 577976 +system.ruby.network.routers2.throttle1.msg_bytes.Data::2 5201496 +system.ruby.delayVCHist.vnet_1::bucket_size 1 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1::max_bucket 9 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1::samples 72247 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1 | 72247 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1::total 72247 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_2::bucket_size 1 # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2::max_bucket 9 # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2::samples 72243 # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2 | 72243 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2::total 72243 # delay histogram for vnet_2 +system.ruby.LD.latency_hist_seqr::bucket_size 64 +system.ruby.LD.latency_hist_seqr::max_bucket 639 +system.ruby.LD.latency_hist_seqr::samples 51711 +system.ruby.LD.latency_hist_seqr::mean 28.269208 +system.ruby.LD.latency_hist_seqr::gmean 7.619512 +system.ruby.LD.latency_hist_seqr::stdev 36.060908 +system.ruby.LD.latency_hist_seqr | 41177 79.63% 79.63% | 9735 18.83% 98.45% | 541 1.05% 99.50% | 99 0.19% 99.69% | 79 0.15% 99.85% | 70 0.14% 99.98% | 7 0.01% 99.99% | 2 0.00% 100.00% | 0 0.00% 100.00% | 1 0.00% 100.00% +system.ruby.LD.latency_hist_seqr::total 51711 +system.ruby.LD.hit_latency_hist_seqr::bucket_size 1 +system.ruby.LD.hit_latency_hist_seqr::max_bucket 9 +system.ruby.LD.hit_latency_hist_seqr::samples 24257 +system.ruby.LD.hit_latency_hist_seqr::mean 1 +system.ruby.LD.hit_latency_hist_seqr::gmean 1 +system.ruby.LD.hit_latency_hist_seqr | 0 0.00% 0.00% | 24257 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.hit_latency_hist_seqr::total 24257 +system.ruby.LD.miss_latency_hist_seqr::bucket_size 64 +system.ruby.LD.miss_latency_hist_seqr::max_bucket 639 +system.ruby.LD.miss_latency_hist_seqr::samples 27454 +system.ruby.LD.miss_latency_hist_seqr::mean 52.362934 +system.ruby.LD.miss_latency_hist_seqr::gmean 45.830488 +system.ruby.LD.miss_latency_hist_seqr::stdev 34.811219 +system.ruby.LD.miss_latency_hist_seqr | 16920 61.63% 61.63% | 9735 35.46% 97.09% | 541 1.97% 99.06% | 99 0.36% 99.42% | 79 0.29% 99.71% | 70 0.25% 99.96% | 7 0.03% 99.99% | 2 0.01% 100.00% | 0 0.00% 100.00% | 1 0.00% 100.00% +system.ruby.LD.miss_latency_hist_seqr::total 27454 +system.ruby.ST.latency_hist_seqr::bucket_size 64 +system.ruby.ST.latency_hist_seqr::max_bucket 639 +system.ruby.ST.latency_hist_seqr::samples 37229 +system.ruby.ST.latency_hist_seqr::mean 15.219587 +system.ruby.ST.latency_hist_seqr::gmean 3.175846 +system.ruby.ST.latency_hist_seqr::stdev 28.311515 +system.ruby.ST.latency_hist_seqr | 33814 90.83% 90.83% | 3147 8.45% 99.28% | 181 0.49% 99.77% | 30 0.08% 99.85% | 22 0.06% 99.91% | 24 0.06% 99.97% | 1 0.00% 99.97% | 1 0.00% 99.98% | 0 0.00% 99.98% | 9 0.02% 100.00% +system.ruby.ST.latency_hist_seqr::total 37229 +system.ruby.ST.hit_latency_hist_seqr::bucket_size 1 +system.ruby.ST.hit_latency_hist_seqr::max_bucket 9 +system.ruby.ST.hit_latency_hist_seqr::samples 25699 +system.ruby.ST.hit_latency_hist_seqr::mean 1 +system.ruby.ST.hit_latency_hist_seqr::gmean 1 +system.ruby.ST.hit_latency_hist_seqr | 0 0.00% 0.00% | 25699 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.hit_latency_hist_seqr::total 25699 +system.ruby.ST.miss_latency_hist_seqr::bucket_size 64 +system.ruby.ST.miss_latency_hist_seqr::max_bucket 639 +system.ruby.ST.miss_latency_hist_seqr::samples 11530 +system.ruby.ST.miss_latency_hist_seqr::mean 46.913356 +system.ruby.ST.miss_latency_hist_seqr::gmean 41.729617 +system.ruby.ST.miss_latency_hist_seqr::stdev 33.659248 +system.ruby.ST.miss_latency_hist_seqr | 8115 70.38% 70.38% | 3147 27.29% 97.68% | 181 1.57% 99.25% | 30 0.26% 99.51% | 22 0.19% 99.70% | 24 0.21% 99.90% | 1 0.01% 99.91% | 1 0.01% 99.92% | 0 0.00% 99.92% | 9 0.08% 100.00% +system.ruby.ST.miss_latency_hist_seqr::total 11530 +system.ruby.IFETCH.latency_hist_seqr::bucket_size 64 +system.ruby.IFETCH.latency_hist_seqr::max_bucket 639 +system.ruby.IFETCH.latency_hist_seqr::samples 226275 +system.ruby.IFETCH.latency_hist_seqr::mean 10.260700 +system.ruby.IFETCH.latency_hist_seqr::gmean 1.811203 +system.ruby.IFETCH.latency_hist_seqr::stdev 26.801914 +system.ruby.IFETCH.latency_hist_seqr | 204394 90.33% 90.33% | 20370 9.00% 99.33% | 994 0.44% 99.77% | 178 0.08% 99.85% | 177 0.08% 99.93% | 142 0.06% 99.99% | 12 0.01% 100.00% | 5 0.00% 100.00% | 0 0.00% 100.00% | 3 0.00% 100.00% +system.ruby.IFETCH.latency_hist_seqr::total 226275 +system.ruby.IFETCH.hit_latency_hist_seqr::bucket_size 1 +system.ruby.IFETCH.hit_latency_hist_seqr::max_bucket 9 +system.ruby.IFETCH.hit_latency_hist_seqr::samples 193012 +system.ruby.IFETCH.hit_latency_hist_seqr::mean 1 +system.ruby.IFETCH.hit_latency_hist_seqr::gmean 1 +system.ruby.IFETCH.hit_latency_hist_seqr | 0 0.00% 0.00% | 193012 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.hit_latency_hist_seqr::total 193012 +system.ruby.IFETCH.miss_latency_hist_seqr::bucket_size 64 +system.ruby.IFETCH.miss_latency_hist_seqr::max_bucket 639 +system.ruby.IFETCH.miss_latency_hist_seqr::samples 33263 +system.ruby.IFETCH.miss_latency_hist_seqr::mean 63.996873 +system.ruby.IFETCH.miss_latency_hist_seqr::gmean 56.865504 +system.ruby.IFETCH.miss_latency_hist_seqr::stdev 38.748066 +system.ruby.IFETCH.miss_latency_hist_seqr | 11382 34.22% 34.22% | 20370 61.24% 95.46% | 994 2.99% 98.45% | 178 0.54% 98.98% | 177 0.53% 99.51% | 142 0.43% 99.94% | 12 0.04% 99.98% | 5 0.02% 99.99% | 0 0.00% 99.99% | 3 0.01% 100.00% +system.ruby.IFETCH.miss_latency_hist_seqr::total 33263 +system.ruby.Directory.miss_mach_latency_hist_seqr::bucket_size 64 +system.ruby.Directory.miss_mach_latency_hist_seqr::max_bucket 639 +system.ruby.Directory.miss_mach_latency_hist_seqr::samples 72247 +system.ruby.Directory.miss_mach_latency_hist_seqr::mean 56.849572 +system.ruby.Directory.miss_mach_latency_hist_seqr::gmean 49.864909 +system.ruby.Directory.miss_mach_latency_hist_seqr::stdev 37.140999 +system.ruby.Directory.miss_mach_latency_hist_seqr | 36417 50.41% 50.41% | 33252 46.03% 96.43% | 1716 2.38% 98.81% | 307 0.42% 99.23% | 278 0.38% 99.62% | 236 0.33% 99.94% | 20 0.03% 99.97% | 8 0.01% 99.98% | 0 0.00% 99.98% | 13 0.02% 100.00% +system.ruby.Directory.miss_mach_latency_hist_seqr::total 72247 +system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::bucket_size 1 +system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::max_bucket 9 +system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::samples 1 +system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::stdev nan +system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::total 1 +system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::bucket_size 1 +system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::max_bucket 9 +system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::samples 1 +system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::stdev nan +system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::total 1 +system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::bucket_size 1 +system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::max_bucket 9 +system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::samples 1 +system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::stdev nan +system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::total 1 +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::bucket_size 8 +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::max_bucket 79 +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::samples 1 +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::mean 75 +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::gmean 75.000000 +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::stdev nan +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::total 1 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::samples 27454 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::mean 52.362934 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::gmean 45.830488 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::stdev 34.811219 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr | 16920 61.63% 61.63% | 9735 35.46% 97.09% | 541 1.97% 99.06% | 99 0.36% 99.42% | 79 0.29% 99.71% | 70 0.25% 99.96% | 7 0.03% 99.99% | 2 0.01% 100.00% | 0 0.00% 100.00% | 1 0.00% 100.00% +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::total 27454 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::samples 11530 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::mean 46.913356 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::gmean 41.729617 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::stdev 33.659248 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr | 8115 70.38% 70.38% | 3147 27.29% 97.68% | 181 1.57% 99.25% | 30 0.26% 99.51% | 22 0.19% 99.70% | 24 0.21% 99.90% | 1 0.01% 99.91% | 1 0.01% 99.92% | 0 0.00% 99.92% | 9 0.08% 100.00% +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::total 11530 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::samples 33263 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::mean 63.996873 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::gmean 56.865504 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::stdev 38.748066 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr | 11382 34.22% 34.22% | 20370 61.24% 95.46% | 994 2.99% 98.45% | 178 0.54% 98.98% | 177 0.53% 99.51% | 142 0.43% 99.94% | 12 0.04% 99.98% | 5 0.02% 99.99% | 0 0.00% 99.99% | 3 0.01% 100.00% +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::total 33263 +system.ruby.Directory_Controller.GETX 72247 0.00% 0.00% +system.ruby.Directory_Controller.PUTX 72243 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Data 72247 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Ack 72243 0.00% 0.00% +system.ruby.Directory_Controller.I.GETX 72247 0.00% 0.00% +system.ruby.Directory_Controller.M.PUTX 72243 0.00% 0.00% +system.ruby.Directory_Controller.IM.Memory_Data 72247 0.00% 0.00% +system.ruby.Directory_Controller.MI.Memory_Ack 72243 0.00% 0.00% +system.ruby.L1Cache_Controller.Load 51711 0.00% 0.00% +system.ruby.L1Cache_Controller.Ifetch 226275 0.00% 0.00% +system.ruby.L1Cache_Controller.Store 37229 0.00% 0.00% +system.ruby.L1Cache_Controller.Data 72247 0.00% 0.00% +system.ruby.L1Cache_Controller.Replacement 72243 0.00% 0.00% +system.ruby.L1Cache_Controller.Writeback_Ack 72243 0.00% 0.00% +system.ruby.L1Cache_Controller.I.Load 27454 0.00% 0.00% +system.ruby.L1Cache_Controller.I.Ifetch 33263 0.00% 0.00% +system.ruby.L1Cache_Controller.I.Store 11530 0.00% 0.00% +system.ruby.L1Cache_Controller.M.Load 24257 0.00% 0.00% +system.ruby.L1Cache_Controller.M.Ifetch 193012 0.00% 0.00% +system.ruby.L1Cache_Controller.M.Store 25699 0.00% 0.00% +system.ruby.L1Cache_Controller.M.Replacement 72243 0.00% 0.00% +system.ruby.L1Cache_Controller.MI.Writeback_Ack 72243 0.00% 0.00% +system.ruby.L1Cache_Controller.IS.Data 60717 0.00% 0.00% +system.ruby.L1Cache_Controller.IM.Data 11530 0.00% 0.00% + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-timing/config.ini b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-timing/config.ini new file mode 100644 index 000000000..47eb7a125 --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-timing/config.ini @@ -0,0 +1,380 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain +boot_osflags=a +cache_line_size=64 +clk_domain=system.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +exit_on_work_items=false +init_param=0 +kernel= +kernel_addr_check=true +load_addr_mask=1099511627775 +load_offset=0 +mem_mode=timing +mem_ranges= +memories=system.physmem +mmap_using_noreserve=false +multi_thread=false +num_work_ids=16 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +readfile= +symbolfile= +thermal_components= +thermal_model=Null +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=TimingSimpleCPU +children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload +branchPred=Null +checker=Null +clk_domain=system.cpu_clk_domain +cpu_id=0 +default_p_state=UNDEFINED +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +eventq_index=0 +function_trace=false +function_trace_start=0 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +profile=0 +progress_interval=0 +simpoint_start_insts= +socket_id=0 +switched_out=false +system=system +tracer=system.cpu.tracer +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.dcache] +type=Cache +children=tags +addr_ranges=0:18446744073709551615:0:0:0:0 +assoc=2 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +data_latency=2 +default_p_state=UNDEFINED +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=4 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=262144 +system=system +tag_latency=2 +tags=system.cpu.dcache.tags +tgts_per_mshr=20 +write_buffers=8 +writeback_clean=false +cpu_side=system.cpu.dcache_port +mem_side=system.cpu.toL2Bus.slave[1] + +[system.cpu.dcache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +data_latency=2 +default_p_state=UNDEFINED +eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +sequential_access=false +size=262144 +tag_latency=2 + +[system.cpu.dtb] +type=RiscvTLB +eventq_index=0 +size=64 + +[system.cpu.icache] +type=Cache +children=tags +addr_ranges=0:18446744073709551615:0:0:0:0 +assoc=2 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +data_latency=2 +default_p_state=UNDEFINED +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=true +max_miss_count=0 +mshrs=4 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=131072 +system=system +tag_latency=2 +tags=system.cpu.icache.tags +tgts_per_mshr=20 +write_buffers=8 +writeback_clean=true +cpu_side=system.cpu.icache_port +mem_side=system.cpu.toL2Bus.slave[0] + +[system.cpu.icache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +data_latency=2 +default_p_state=UNDEFINED +eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +sequential_access=false +size=131072 +tag_latency=2 + +[system.cpu.interrupts] +type=RiscvInterrupts +eventq_index=0 + +[system.cpu.isa] +type=RiscvISA +eventq_index=0 + +[system.cpu.itb] +type=RiscvTLB +eventq_index=0 +size=64 + +[system.cpu.l2cache] +type=Cache +children=tags +addr_ranges=0:18446744073709551615:0:0:0:0 +assoc=8 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +data_latency=20 +default_p_state=UNDEFINED +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=20 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +prefetch_on_access=false +prefetcher=Null +response_latency=20 +sequential_access=false +size=2097152 +system=system +tag_latency=20 +tags=system.cpu.l2cache.tags +tgts_per_mshr=12 +write_buffers=8 +writeback_clean=false +cpu_side=system.cpu.toL2Bus.master[0] +mem_side=system.membus.slave[1] + +[system.cpu.l2cache.tags] +type=LRU +assoc=8 +block_size=64 +clk_domain=system.cpu_clk_domain +data_latency=20 +default_p_state=UNDEFINED +eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +sequential_access=false +size=2097152 +tag_latency=20 + +[system.cpu.toL2Bus] +type=CoherentXBar +children=snoop_filter +clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED +eventq_index=0 +forward_latency=0 +frontend_latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +point_of_coherency=false +power_model=Null +response_latency=1 +snoop_filter=system.cpu.toL2Bus.snoop_filter +snoop_response_latency=1 +system=system +use_default_range=false +width=32 +master=system.cpu.l2cache.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side + +[system.cpu.toL2Bus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=0 +max_capacity=8388608 +system=system + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=LiveProcess +cmd=insttest +cwd= +drivers= +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable=/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64f/insttest +gid=100 +input=cin +kvmInSE=false +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=0 +system=system +uid=100 +useArchPT=false + +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000000 + +[system.membus] +type=CoherentXBar +children=snoop_filter +clk_domain=system.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +forward_latency=4 +frontend_latency=3 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +point_of_coherency=true +power_model=Null +response_latency=2 +snoop_filter=system.membus.snoop_filter +snoop_response_latency=4 +system=system +use_default_range=false +width=16 +master=system.physmem.port +slave=system.system_port system.cpu.l2cache.mem_side + +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + +[system.physmem] +type=SimpleMemory +bandwidth=73.000000 +clk_domain=system.clk_domain +conf_table_reported=true +default_p_state=UNDEFINED +eventq_index=0 +in_addr_map=true +kvm_map=true +latency=30000 +latency_var=0 +null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +range=0:134217727:0:0:0:0 +port=system.membus.master[0] + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-timing/config.json b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-timing/config.json new file mode 100644 index 000000000..58b36202f --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-timing/config.json @@ -0,0 +1,508 @@ +{ + "name": null, + "sim_quantum": 0, + "system": { + "kernel": "", + "mmap_using_noreserve": false, + "kernel_addr_check": true, + "membus": { + "point_of_coherency": true, + "system": "system", + "response_latency": 2, + "cxx_class": "CoherentXBar", + "forward_latency": 4, + "clk_domain": "system.clk_domain", + "width": 16, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "master": { + "peer": [ + "system.physmem.port" + ], + "role": "MASTER" + }, + "type": "CoherentXBar", + "frontend_latency": 3, + "slave": { + "peer": [ + "system.system_port", + "system.cpu.l2cache.mem_side" + ], + "role": "SLAVE" + }, + "p_state_clk_gate_min": 1000, + "snoop_filter": { + "name": "snoop_filter", + "system": "system", + "max_capacity": 8388608, + "eventq_index": 0, + "cxx_class": "SnoopFilter", + "path": "system.membus.snoop_filter", + "type": "SnoopFilter", + "lookup_latency": 1 + }, + "power_model": null, + "path": "system.membus", + "snoop_response_latency": 4, + "name": "membus", + "p_state_clk_gate_bins": 20, + "use_default_range": false + }, + "symbolfile": "", + "readfile": "", + "thermal_model": null, + "cxx_class": "System", + "work_begin_cpu_id_exit": -1, + "load_offset": 0, + "work_begin_exit_count": 0, + "p_state_clk_gate_min": 1000, + "memories": [ + "system.physmem" + ], + "work_begin_ckpt_count": 0, + "clk_domain": { + "name": "clk_domain", + "clock": [ + 1000 + ], + "init_perf_level": 0, + "voltage_domain": "system.voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "mem_ranges": [], + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "dvfs_handler": { + "enable": false, + "name": "dvfs_handler", + "sys_clk_domain": "system.clk_domain", + "transition_latency": 100000000, + "eventq_index": 0, + "cxx_class": "DVFSHandler", + "domains": [], + "path": "system.dvfs_handler", + "type": "DVFSHandler" + }, + "work_end_exit_count": 0, + "type": "System", + "voltage_domain": { + "name": "voltage_domain", + "eventq_index": 0, + "voltage": [ + "1.0" + ], + "cxx_class": "VoltageDomain", + "path": "system.voltage_domain", + "type": "VoltageDomain" + }, + "cache_line_size": 64, + "boot_osflags": "a", + "system_port": { + "peer": "system.membus.slave[0]", + "role": "MASTER" + }, + "physmem": { + "range": "0:134217727:0:0:0:0", + "latency": 30000, + "name": "physmem", + "p_state_clk_gate_min": 1000, + "eventq_index": 0, + "p_state_clk_gate_bins": 20, + "default_p_state": "UNDEFINED", + "kvm_map": true, + "clk_domain": "system.clk_domain", + "power_model": null, + "latency_var": 0, + "bandwidth": "73.000000", + "conf_table_reported": true, + "cxx_class": "SimpleMemory", + "p_state_clk_gate_max": 1000000000000, + "path": "system.physmem", + "null": false, + "type": "SimpleMemory", + "port": { + "peer": "system.membus.master[0]", + "role": "SLAVE" + }, + "in_addr_map": true + }, + "power_model": null, + "work_cpus_ckpt_count": 0, + "thermal_components": [], + "path": "system", + "cpu_clk_domain": { + "name": "cpu_clk_domain", + "clock": [ + 500 + ], + "init_perf_level": 0, + "voltage_domain": "system.voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.cpu_clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "work_end_ckpt_count": 0, + "mem_mode": "timing", + "name": "system", + "init_param": 0, + "p_state_clk_gate_bins": 20, + "load_addr_mask": 1099511627775, + "cpu": [ + { + "do_statistics_insts": true, + "numThreads": 1, + "itb": { + "name": "itb", + "eventq_index": 0, + "cxx_class": "RiscvISA::TLB", + "path": "system.cpu.itb", + "type": "RiscvTLB", + "size": 64 + }, + "system": "system", + "icache": { + "cpu_side": { + "peer": "system.cpu.icache_port", + "role": "SLAVE" + }, + "clusivity": "mostly_incl", + "prefetcher": null, + "system": "system", + "write_buffers": 8, + "response_latency": 2, + "cxx_class": "Cache", + "size": 131072, + "type": "Cache", + "clk_domain": "system.cpu_clk_domain", + "max_miss_count": 0, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "mem_side": { + "peer": "system.cpu.toL2Bus.slave[0]", + "role": "MASTER" + }, + "mshrs": 4, + "writeback_clean": true, + "p_state_clk_gate_min": 1000, + "tags": { + "size": 131072, + "tag_latency": 2, + "name": "tags", + "p_state_clk_gate_min": 1000, + "eventq_index": 0, + "p_state_clk_gate_bins": 20, + "default_p_state": "UNDEFINED", + "clk_domain": "system.cpu_clk_domain", + "power_model": null, + "sequential_access": false, + "assoc": 2, + "cxx_class": "LRU", + "p_state_clk_gate_max": 1000000000000, + "path": "system.cpu.icache.tags", + "block_size": 64, + "type": "LRU", + "data_latency": 2 + }, + "tgts_per_mshr": 20, + "demand_mshr_reserve": 1, + "power_model": null, + "addr_ranges": [ + "0:18446744073709551615:0:0:0:0" + ], + "is_read_only": true, + "prefetch_on_access": false, + "path": "system.cpu.icache", + "data_latency": 2, + "tag_latency": 2, + "name": "icache", + "p_state_clk_gate_bins": 20, + "sequential_access": false, + "assoc": 2 + }, + "function_trace": false, + "do_checkpoint_insts": true, + "cxx_class": "TimingSimpleCPU", + "max_loads_all_threads": 0, + "clk_domain": "system.cpu_clk_domain", + "function_trace_start": 0, + "cpu_id": 0, + "checker": null, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "toL2Bus": { + "point_of_coherency": false, + "system": "system", + "response_latency": 1, + "cxx_class": "CoherentXBar", + "forward_latency": 0, + "clk_domain": "system.cpu_clk_domain", + "width": 32, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "master": { + "peer": [ + "system.cpu.l2cache.cpu_side" + ], + "role": "MASTER" + }, + "type": "CoherentXBar", + "frontend_latency": 1, + "slave": { + "peer": [ + "system.cpu.icache.mem_side", + "system.cpu.dcache.mem_side" + ], + "role": "SLAVE" + }, + "p_state_clk_gate_min": 1000, + "snoop_filter": { + "name": "snoop_filter", + "system": "system", + "max_capacity": 8388608, + "eventq_index": 0, + "cxx_class": "SnoopFilter", + "path": "system.cpu.toL2Bus.snoop_filter", + "type": "SnoopFilter", + "lookup_latency": 0 + }, + "power_model": null, + "path": "system.cpu.toL2Bus", + "snoop_response_latency": 1, + "name": "toL2Bus", + "p_state_clk_gate_bins": 20, + "use_default_range": false + }, + "do_quiesce": true, + "type": "TimingSimpleCPU", + "profile": 0, + "icache_port": { + "peer": "system.cpu.icache.cpu_side", + "role": "MASTER" + }, + "p_state_clk_gate_bins": 20, + "p_state_clk_gate_min": 1000, + "interrupts": [ + { + "eventq_index": 0, + "path": "system.cpu.interrupts", + "type": "RiscvInterrupts", + "name": "interrupts", + "cxx_class": "RiscvISA::Interrupts" + } + ], + "dcache_port": { + "peer": "system.cpu.dcache.cpu_side", + "role": "MASTER" + }, + "socket_id": 0, + "power_model": null, + "max_insts_all_threads": 0, + "l2cache": { + "cpu_side": { + "peer": "system.cpu.toL2Bus.master[0]", + "role": "SLAVE" + }, + "clusivity": "mostly_incl", + "prefetcher": null, + "system": "system", + "write_buffers": 8, + "response_latency": 20, + "cxx_class": "Cache", + "size": 2097152, + "type": "Cache", + "clk_domain": "system.cpu_clk_domain", + "max_miss_count": 0, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "mem_side": { + "peer": "system.membus.slave[1]", + "role": "MASTER" + }, + "mshrs": 20, + "writeback_clean": false, + "p_state_clk_gate_min": 1000, + "tags": { + "size": 2097152, + "tag_latency": 20, + "name": "tags", + "p_state_clk_gate_min": 1000, + "eventq_index": 0, + "p_state_clk_gate_bins": 20, + "default_p_state": "UNDEFINED", + "clk_domain": "system.cpu_clk_domain", + "power_model": null, + "sequential_access": false, + "assoc": 8, + "cxx_class": "LRU", + "p_state_clk_gate_max": 1000000000000, + "path": "system.cpu.l2cache.tags", + "block_size": 64, + "type": "LRU", + "data_latency": 20 + }, + "tgts_per_mshr": 12, + "demand_mshr_reserve": 1, + "power_model": null, + "addr_ranges": [ + "0:18446744073709551615:0:0:0:0" + ], + "is_read_only": false, + "prefetch_on_access": false, + "path": "system.cpu.l2cache", + "data_latency": 20, + "tag_latency": 20, + "name": "l2cache", + "p_state_clk_gate_bins": 20, + "sequential_access": false, + "assoc": 8 + }, + "path": "system.cpu", + "max_loads_any_thread": 0, + "switched_out": false, + "workload": [ + { + "uid": 100, + "pid": 100, + "kvmInSE": false, + "cxx_class": "LiveProcess", + "executable": "/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64f/insttest", + "drivers": [], + "system": "system", + "gid": 100, + "eventq_index": 0, + "env": [], + "input": "cin", + "ppid": 99, + "type": "LiveProcess", + "cwd": "", + "simpoint": 0, + "euid": 100, + "path": "system.cpu.workload", + "max_stack_size": 67108864, + "name": "workload", + "cmd": [ + "insttest" + ], + "errout": "cerr", + "useArchPT": false, + "egid": 100, + "output": "cout" + } + ], + "name": "cpu", + "dtb": { + "name": "dtb", + "eventq_index": 0, + "cxx_class": "RiscvISA::TLB", + "path": "system.cpu.dtb", + "type": "RiscvTLB", + "size": 64 + }, + "simpoint_start_insts": [], + "max_insts_any_thread": 0, + "progress_interval": 0, + "branchPred": null, + "dcache": { + "cpu_side": { + "peer": "system.cpu.dcache_port", + "role": "SLAVE" + }, + "clusivity": "mostly_incl", + "prefetcher": null, + "system": "system", + "write_buffers": 8, + "response_latency": 2, + "cxx_class": "Cache", + "size": 262144, + "type": "Cache", + "clk_domain": "system.cpu_clk_domain", + "max_miss_count": 0, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "mem_side": { + "peer": "system.cpu.toL2Bus.slave[1]", + "role": "MASTER" + }, + "mshrs": 4, + "writeback_clean": false, + "p_state_clk_gate_min": 1000, + "tags": { + "size": 262144, + "tag_latency": 2, + "name": "tags", + "p_state_clk_gate_min": 1000, + "eventq_index": 0, + "p_state_clk_gate_bins": 20, + "default_p_state": "UNDEFINED", + "clk_domain": "system.cpu_clk_domain", + "power_model": null, + "sequential_access": false, + "assoc": 2, + "cxx_class": "LRU", + "p_state_clk_gate_max": 1000000000000, + "path": "system.cpu.dcache.tags", + "block_size": 64, + "type": "LRU", + "data_latency": 2 + }, + "tgts_per_mshr": 20, + "demand_mshr_reserve": 1, + "power_model": null, + "addr_ranges": [ + "0:18446744073709551615:0:0:0:0" + ], + "is_read_only": false, + "prefetch_on_access": false, + "path": "system.cpu.dcache", + "data_latency": 2, + "tag_latency": 2, + "name": "dcache", + "p_state_clk_gate_bins": 20, + "sequential_access": false, + "assoc": 2 + }, + "isa": [ + { + "eventq_index": 0, + "path": "system.cpu.isa", + "type": "RiscvISA", + "name": "isa", + "cxx_class": "RiscvISA::ISA" + } + ], + "tracer": { + "eventq_index": 0, + "path": "system.cpu.tracer", + "type": "ExeTracer", + "name": "tracer", + "cxx_class": "Trace::ExeTracer" + } + } + ], + "multi_thread": false, + "exit_on_work_items": false, + "work_item_id": -1, + "num_work_ids": 16 + }, + "time_sync_period": 100000000000, + "eventq_index": 0, + "time_sync_spin_threshold": 100000000, + "cxx_class": "Root", + "path": "root", + "time_sync_enable": false, + "type": "Root", + "full_system": false +}
\ No newline at end of file diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-timing/simerr b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-timing/simerr new file mode 100755 index 000000000..fd133b12b --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-timing/simerr @@ -0,0 +1,3 @@ +warn: Unknown operating system; assuming Linux. +warn: Sockets disabled, not accepting gdb connections +warn: ClockedObject: More than one power state change request encountered within the same simulation tick diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-timing/simout b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-timing/simout new file mode 100755 index 000000000..5080c6704 --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-timing/simout @@ -0,0 +1,121 @@ +Redirecting stdout to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64f/simple-timing/simout +Redirecting stderr to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64f/simple-timing/simerr +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled Nov 30 2016 14:33:35 +gem5 started Nov 30 2016 16:18:33 +gem5 executing on zizzer, pid 34081 +command line: /z/powerjg/gem5-upstream/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64f/simple-timing -re /z/powerjg/gem5-upstream/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64f/simple-timing + +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. +clear fsflags: PASS +flw: PASS +fsw: PASS +fmadd.s: PASS +fmadd.s, quiet NaN: PASS +fmadd.s, signaling NaN: PASS +fmadd.s, infinity: PASS +fmadd.s, -infinity: PASS +fmsub.s: PASS +fmsub.s, quiet NaN: PASS +fmsub.s, signaling NaN: PASS +fmsub.s, infinity: PASS +fmsub.s, -infinity: PASS +fmsub.s, subtract infinity: PASS +fnmsub.s: PASS +fnmsub.s, quiet NaN: PASS +fnmsub.s, signaling NaN: PASS +fnmsub.s, infinity: PASS +fnmsub.s, -infinity: PASS +fnmsub.s, subtract infinity: PASS +fnmadd.s: PASS +fnmadd.s, quiet NaN: PASS +fnmadd.s, signaling NaN: PASS +fnmadd.s, infinity: PASS +fnmadd.s, -infinity: PASS +fadd.s: PASS +fadd.s, quiet NaN: PASS +fadd.s, signaling NaN: PASS +fadd.s, infinity: PASS +fadd.s, -infinity: PASS +fsub.s: PASS +fsub.s, quiet NaN: PASS +fsub.s, signaling NaN: PASS +fsub.s, infinity: PASS +fsub.s, -infinity: PASS +fsub.s, subtract infinity: PASS +fmul.s: PASS +fmul.s, quiet NaN: PASS +fmul.s, signaling NaN: PASS +fmul.s, infinity: PASS +fmul.s, -infinity: PASS +fmul.s, 0*infinity: PASS +fmul.s, overflow: PASS +fmul.s, underflow: PASS +fdiv.s: PASS +fdiv.s, quiet NaN: PASS +fdiv.s, signaling NaN: PASS +fdiv.s/0: PASS +fdiv.s/infinity: PASS +fdiv.s, infinity/infinity: PASS +fdiv.s, 0/0: PASS +fdiv.s, infinity/0: PASS +fdiv.s, 0/infinity: PASS +fdiv.s, underflow: PASS +fdiv.s, overflow: PASS +fsqrt.s: PASS +fsqrt.s, NaN: PASS +fsqrt.s, quiet NaN: PASS +fsqrt.s, signaling NaN: PASS +fsqrt.s, infinity: PASS +fsgnj.s, ++: PASS +fsgnj.s, +-: PASS +fsgnj.s, -+: PASS +fsgnj.s, --: PASS +fsgnj.s, quiet NaN: PASS +fsgnj.s, signaling NaN: PASS +fsgnj.s, inject NaN: PASS +fsgnj.s, inject -NaN: PASS +fsgnjn.s, ++: PASS +fsgnjn.s, +-: PASS +fsgnjn.s, -+: PASS +fsgnjn.s, --: PASS +fsgnjn.s, quiet NaN: PASS +fsgnjn.s, signaling NaN: PASS +fsgnjn.s, inject NaN: PASS +fsgnjn.s, inject NaN: PASS +fsgnjx.s, ++: PASS +fsgnjx.s, +-: PASS +fsgnjx.s, -+: PASS +fsgnjx.s, --: PASS +fsgnjx.s, quiet NaN: PASS +fsgnjx.s, signaling NaN: PASS +fsgnjx.s, inject NaN: PASS +fsgnjx.s, inject -NaN: PASS +fmin.s: PASS +fmin.s, -infinity: PASS +fmin.s, infinity: PASS +fmin.s, quiet NaN first: PASS +fmin.s, quiet NaN second: PASS +fmin.s, quiet NaN both: PASS +fmin.s, signaling NaN first: PASS +fmin.s, signaling NaN second: PASS +fmin.s, signaling NaN both: PASS +fmax.s: PASS +fmax.s, -infinity: PASS +fmax.s, infinity: PASS +fmax.s, quiet NaN first: PASS +fmax.s, quiet NaN second: PASS +fmax.s, quiet NaN both: PASS +fmax.s, signaling NaN first: PASS +fmax.s, signaling NaN second: PASS +fmax.s, signaling NaN both: PASS +fcvt.w.s, truncate positive: PASS +fcvt.w.s, truncate negative: PASS +fcvt.w.s, 0.0: PASS +fcvt.w.s, -0.0: PASS +fcvt.w.s, overflow: [1;31mFAIL[0m (expected 2147483647; found -2147483648) +Exiting @ tick 385535500 because target called exit() diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-timing/stats.txt b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-timing/stats.txt new file mode 100644 index 000000000..b9ee4135f --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-timing/stats.txt @@ -0,0 +1,521 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.000386 # Number of seconds simulated +sim_ticks 385535500 # Number of ticks simulated +final_tick 385535500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 27855 # Simulator instruction rate (inst/s) +host_op_rate 27855 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 47485128 # Simulator tick rate (ticks/s) +host_mem_usage 243704 # Number of bytes of host memory used +host_seconds 8.12 # Real time elapsed on the host +sim_insts 226159 # Number of instructions simulated +sim_ops 226159 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 385535500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 53632 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 18944 # Number of bytes read from this memory +system.physmem.bytes_read::total 72576 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 53632 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 53632 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 838 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 296 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1134 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 139110406 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 49136850 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 188247256 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 139110406 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 139110406 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 139110406 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 49136850 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 188247256 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 385535500 # Cumulative time (in ticks) in various power states +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 115 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 385535500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 771071 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 226159 # Number of instructions committed +system.cpu.committedOps 226159 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 225992 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 862 # Number of float alu accesses +system.cpu.num_func_calls 16616 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 33789 # number of instructions that are conditional controls +system.cpu.num_int_insts 225992 # number of integer instructions +system.cpu.num_fp_insts 862 # number of float instructions +system.cpu.num_int_register_reads 298589 # number of times the integer registers were read +system.cpu.num_int_register_writes 154866 # number of times the integer registers were written +system.cpu.num_fp_register_reads 733 # number of times the floating registers were read +system.cpu.num_fp_register_writes 588 # number of times the floating registers were written +system.cpu.num_mem_refs 88941 # number of memory refs +system.cpu.num_load_insts 51711 # Number of load instructions +system.cpu.num_store_insts 37230 # Number of store instructions +system.cpu.num_idle_cycles 0 # Number of idle cycles +system.cpu.num_busy_cycles 771071 # Number of busy cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.Branches 50405 # Number of branches fetched +system.cpu.op_class::No_OpClass 117 0.05% 0.05% # Class of executed instruction +system.cpu.op_class::IntAlu 136540 60.34% 60.39% # Class of executed instruction +system.cpu.op_class::IntMult 325 0.14% 60.54% # Class of executed instruction +system.cpu.op_class::IntDiv 40 0.02% 60.56% # Class of executed instruction +system.cpu.op_class::FloatAdd 104 0.05% 60.60% # Class of executed instruction +system.cpu.op_class::FloatCmp 119 0.05% 60.65% # Class of executed instruction +system.cpu.op_class::FloatCvt 43 0.02% 60.67% # Class of executed instruction +system.cpu.op_class::FloatMult 30 0.01% 60.69% # Class of executed instruction +system.cpu.op_class::FloatMultAcc 0 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::FloatDiv 11 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::FloatMisc 0 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::FloatSqrt 5 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 60.69% # Class of executed instruction +system.cpu.op_class::MemRead 51297 22.67% 83.36% # Class of executed instruction +system.cpu.op_class::MemWrite 37094 16.39% 99.76% # Class of executed instruction +system.cpu.op_class::FloatMemRead 414 0.18% 99.94% # Class of executed instruction +system.cpu.op_class::FloatMemWrite 136 0.06% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 226275 # Class of executed instruction +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 385535500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 0 # number of replacements +system.cpu.dcache.tags.tagsinuse 246.215915 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 88644 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 296 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 299.472973 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 246.215915 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.060111 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.060111 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 296 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 4 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 14 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 278 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.072266 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 178176 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 178176 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 385535500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 51622 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 51622 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 37022 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 37022 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 88644 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 88644 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 88644 # number of overall hits +system.cpu.dcache.overall_hits::total 88644 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 89 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 89 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 207 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 207 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 296 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 296 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 296 # number of overall misses +system.cpu.dcache.overall_misses::total 296 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5607000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5607000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 13041000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 13041000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 18648000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 18648000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 18648000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 18648000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 51711 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 51711 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 37229 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 37229 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 88940 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 88940 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 88940 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 88940 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.001721 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.001721 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005560 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.005560 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.003328 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.003328 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.003328 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.003328 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63000 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 63000 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 63000 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 63000 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 63000 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 63000 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 63000 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 89 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 89 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 207 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 207 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 296 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 296 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 296 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 296 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5518000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 5518000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12834000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 12834000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 18352000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 18352000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 18352000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 18352000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001721 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001721 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005560 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005560 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003328 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.003328 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003328 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.003328 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 62000 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 62000 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 62000 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 62000 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 62000 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 62000 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 62000 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 62000 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 385535500 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 31 # number of replacements +system.cpu.icache.tags.tagsinuse 467.546782 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 225437 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 839 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 268.697259 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 467.546782 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.228294 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.228294 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 808 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 60 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 106 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 642 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.394531 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 453391 # Number of tag accesses +system.cpu.icache.tags.data_accesses 453391 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 385535500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 225437 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 225437 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 225437 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 225437 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 225437 # number of overall hits +system.cpu.icache.overall_hits::total 225437 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 839 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 839 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 839 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 839 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 839 # number of overall misses +system.cpu.icache.overall_misses::total 839 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 52807500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 52807500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 52807500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 52807500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 52807500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 52807500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 226276 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 226276 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 226276 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 226276 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 226276 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 226276 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.003708 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.003708 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.003708 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.003708 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.003708 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.003708 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 62941.001192 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 62941.001192 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 62941.001192 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 62941.001192 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 62941.001192 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 62941.001192 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.icache.writebacks::writebacks 31 # number of writebacks +system.cpu.icache.writebacks::total 31 # number of writebacks +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 839 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 839 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 839 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 839 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 839 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 839 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 51968500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 51968500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 51968500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 51968500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 51968500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 51968500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.003708 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.003708 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.003708 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.003708 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.003708 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.003708 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 61941.001192 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 61941.001192 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 61941.001192 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 61941.001192 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 61941.001192 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 61941.001192 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 385535500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.replacements 0 # number of replacements +system.cpu.l2cache.tags.tagsinuse 727.343781 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 32 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 1134 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.028219 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::cpu.inst 481.119804 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 246.223977 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.014683 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.007514 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.022197 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 1134 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 64 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 120 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 950 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.034607 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 10462 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 10462 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 385535500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.WritebackClean_hits::writebacks 31 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 31 # number of WritebackClean hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 1 # number of ReadCleanReq hits +system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 1 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits +system.cpu.l2cache.overall_hits::total 1 # number of overall hits +system.cpu.l2cache.ReadExReq_misses::cpu.data 207 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 207 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 838 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 838 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 89 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 89 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.inst 838 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 296 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 1134 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 838 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 296 # number of overall misses +system.cpu.l2cache.overall_misses::total 1134 # number of overall misses +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 12523500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 12523500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 50699500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 50699500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 5384500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 5384500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 50699500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 17908000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 68607500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 50699500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 17908000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 68607500 # number of overall miss cycles +system.cpu.l2cache.WritebackClean_accesses::writebacks 31 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 31 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 207 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 207 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 839 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 839 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 89 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 89 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 839 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 296 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 1135 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 839 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 296 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 1135 # number of overall (read+write) accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.998808 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.998808 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.998808 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.999119 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.998808 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.999119 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60500 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60500 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60500.596659 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60500.596659 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60500 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60500 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60500.596659 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60500 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 60500.440917 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60500.596659 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60500 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 60500.440917 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 207 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 207 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 838 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 838 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 89 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 89 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 838 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 296 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 1134 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 838 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 296 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 1134 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 10453500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 10453500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 42319500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 42319500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4494500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4494500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 42319500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 14948000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 57267500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 42319500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 14948000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 57267500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.998808 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.998808 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.998808 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.999119 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.998808 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.999119 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50500.596659 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50500.596659 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50500.596659 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50500.440917 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50500.596659 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50500.440917 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 1166 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 31 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 385535500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 928 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 31 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 207 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 207 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 839 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 89 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1709 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 592 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 2301 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 55680 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18944 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 74624 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 1135 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 1135 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 1135 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 614000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 1258500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.3 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 444000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) +system.membus.snoop_filter.tot_requests 1134 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 385535500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 927 # Transaction distribution +system.membus.trans_dist::ReadExReq 207 # Transaction distribution +system.membus.trans_dist::ReadExResp 207 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 927 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 2268 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 2268 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 72576 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 72576 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoopTraffic 0 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 1134 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 1134 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 1134 # Request fanout histogram +system.membus.reqLayer0.occupancy 1134500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.3 # Layer utilization (%) +system.membus.respLayer1.occupancy 5670000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 1.5 # Layer utilization (%) + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/minor-timing/config.ini b/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/minor-timing/config.ini new file mode 100644 index 000000000..8ba8fdf37 --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/minor-timing/config.ini @@ -0,0 +1,902 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain +boot_osflags=a +cache_line_size=64 +clk_domain=system.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +exit_on_work_items=false +init_param=0 +kernel= +kernel_addr_check=true +load_addr_mask=1099511627775 +load_offset=0 +mem_mode=timing +mem_ranges= +memories=system.physmem +mmap_using_noreserve=false +multi_thread=false +num_work_ids=16 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +readfile= +symbolfile= +thermal_components= +thermal_model=Null +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=MinorCPU +children=branchPred dcache dtb executeFuncUnits icache interrupts isa itb l2cache toL2Bus tracer workload +branchPred=system.cpu.branchPred +checker=Null +clk_domain=system.cpu_clk_domain +cpu_id=0 +decodeCycleInput=true +decodeInputBufferSize=3 +decodeInputWidth=2 +decodeToExecuteForwardDelay=1 +default_p_state=UNDEFINED +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +enableIdling=true +eventq_index=0 +executeAllowEarlyMemoryIssue=true +executeBranchDelay=1 +executeCommitLimit=2 +executeCycleInput=true +executeFuncUnits=system.cpu.executeFuncUnits +executeInputBufferSize=7 +executeInputWidth=2 +executeIssueLimit=2 +executeLSQMaxStoreBufferStoresPerCycle=2 +executeLSQRequestsQueueSize=1 +executeLSQStoreBufferSize=5 +executeLSQTransfersQueueSize=2 +executeMaxAccessesInMemory=2 +executeMemoryCommitLimit=1 +executeMemoryIssueLimit=1 +executeMemoryWidth=0 +executeSetTraceTimeOnCommit=true +executeSetTraceTimeOnIssue=false +fetch1FetchLimit=1 +fetch1LineSnapWidth=0 +fetch1LineWidth=0 +fetch1ToFetch2BackwardDelay=1 +fetch1ToFetch2ForwardDelay=1 +fetch2CycleInput=true +fetch2InputBufferSize=2 +fetch2ToDecodeForwardDelay=1 +function_trace=false +function_trace_start=0 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +profile=0 +progress_interval=0 +simpoint_start_insts= +socket_id=0 +switched_out=false +system=system +threadPolicy=RoundRobin +tracer=system.cpu.tracer +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.branchPred] +type=TournamentBP +BTBEntries=4096 +BTBTagSize=16 +RASSize=16 +choiceCtrBits=2 +choicePredictorSize=8192 +eventq_index=0 +globalCtrBits=2 +globalPredictorSize=8192 +indirectHashGHR=true +indirectHashTargets=true +indirectPathLength=3 +indirectSets=256 +indirectTagSize=16 +indirectWays=2 +instShiftAmt=2 +localCtrBits=2 +localHistoryTableSize=2048 +localPredictorSize=2048 +numThreads=1 +useIndirect=true + +[system.cpu.dcache] +type=Cache +children=tags +addr_ranges=0:18446744073709551615:0:0:0:0 +assoc=2 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +data_latency=2 +default_p_state=UNDEFINED +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=4 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=262144 +system=system +tag_latency=2 +tags=system.cpu.dcache.tags +tgts_per_mshr=20 +write_buffers=8 +writeback_clean=false +cpu_side=system.cpu.dcache_port +mem_side=system.cpu.toL2Bus.slave[1] + +[system.cpu.dcache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +data_latency=2 +default_p_state=UNDEFINED +eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +sequential_access=false +size=262144 +tag_latency=2 + +[system.cpu.dtb] +type=RiscvTLB +eventq_index=0 +size=64 + +[system.cpu.executeFuncUnits] +type=MinorFUPool +children=funcUnits0 funcUnits1 funcUnits2 funcUnits3 funcUnits4 funcUnits5 funcUnits6 +eventq_index=0 +funcUnits=system.cpu.executeFuncUnits.funcUnits0 system.cpu.executeFuncUnits.funcUnits1 system.cpu.executeFuncUnits.funcUnits2 system.cpu.executeFuncUnits.funcUnits3 system.cpu.executeFuncUnits.funcUnits4 system.cpu.executeFuncUnits.funcUnits5 system.cpu.executeFuncUnits.funcUnits6 + +[system.cpu.executeFuncUnits.funcUnits0] +type=MinorFU +children=opClasses timings +cantForwardFromFUIndices= +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses +opLat=3 +timings=system.cpu.executeFuncUnits.funcUnits0.timings + +[system.cpu.executeFuncUnits.funcUnits0.opClasses] +type=MinorOpClassSet +children=opClasses +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses + +[system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses] +type=MinorOpClass +eventq_index=0 +opClass=IntAlu + +[system.cpu.executeFuncUnits.funcUnits0.timings] +type=MinorFUTiming +children=opClasses +description=Int +eventq_index=0 +extraAssumedLat=0 +extraCommitLat=0 +extraCommitLatExpr=Null +mask=0 +match=0 +opClasses=system.cpu.executeFuncUnits.funcUnits0.timings.opClasses +srcRegsRelativeLats=2 +suppress=false + +[system.cpu.executeFuncUnits.funcUnits0.timings.opClasses] +type=MinorOpClassSet +eventq_index=0 +opClasses= + +[system.cpu.executeFuncUnits.funcUnits1] +type=MinorFU +children=opClasses timings +cantForwardFromFUIndices= +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses +opLat=3 +timings=system.cpu.executeFuncUnits.funcUnits1.timings + +[system.cpu.executeFuncUnits.funcUnits1.opClasses] +type=MinorOpClassSet +children=opClasses +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses + +[system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses] +type=MinorOpClass +eventq_index=0 +opClass=IntAlu + +[system.cpu.executeFuncUnits.funcUnits1.timings] +type=MinorFUTiming +children=opClasses +description=Int +eventq_index=0 +extraAssumedLat=0 +extraCommitLat=0 +extraCommitLatExpr=Null +mask=0 +match=0 +opClasses=system.cpu.executeFuncUnits.funcUnits1.timings.opClasses +srcRegsRelativeLats=2 +suppress=false + +[system.cpu.executeFuncUnits.funcUnits1.timings.opClasses] +type=MinorOpClassSet +eventq_index=0 +opClasses= + +[system.cpu.executeFuncUnits.funcUnits2] +type=MinorFU +children=opClasses timings +cantForwardFromFUIndices= +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits2.opClasses +opLat=3 +timings=system.cpu.executeFuncUnits.funcUnits2.timings + +[system.cpu.executeFuncUnits.funcUnits2.opClasses] +type=MinorOpClassSet +children=opClasses +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses + +[system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses] +type=MinorOpClass +eventq_index=0 +opClass=IntMult + +[system.cpu.executeFuncUnits.funcUnits2.timings] +type=MinorFUTiming +children=opClasses +description=Mul +eventq_index=0 +extraAssumedLat=0 +extraCommitLat=0 +extraCommitLatExpr=Null +mask=0 +match=0 +opClasses=system.cpu.executeFuncUnits.funcUnits2.timings.opClasses +srcRegsRelativeLats=0 +suppress=false + +[system.cpu.executeFuncUnits.funcUnits2.timings.opClasses] +type=MinorOpClassSet +eventq_index=0 +opClasses= + +[system.cpu.executeFuncUnits.funcUnits3] +type=MinorFU +children=opClasses +cantForwardFromFUIndices= +eventq_index=0 +issueLat=9 +opClasses=system.cpu.executeFuncUnits.funcUnits3.opClasses +opLat=9 +timings= + +[system.cpu.executeFuncUnits.funcUnits3.opClasses] +type=MinorOpClassSet +children=opClasses +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses + +[system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses] +type=MinorOpClass +eventq_index=0 +opClass=IntDiv + +[system.cpu.executeFuncUnits.funcUnits4] +type=MinorFU +children=opClasses timings +cantForwardFromFUIndices= +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses +opLat=6 +timings=system.cpu.executeFuncUnits.funcUnits4.timings + +[system.cpu.executeFuncUnits.funcUnits4.opClasses] +type=MinorOpClassSet +children=opClasses00 opClasses01 opClasses02 opClasses03 opClasses04 opClasses05 opClasses06 opClasses07 opClasses08 opClasses09 opClasses10 opClasses11 opClasses12 opClasses13 opClasses14 opClasses15 opClasses16 opClasses17 opClasses18 opClasses19 opClasses20 opClasses21 opClasses22 opClasses23 opClasses24 opClasses25 opClasses26 opClasses27 +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses26 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses27 + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00] +type=MinorOpClass +eventq_index=0 +opClass=FloatAdd + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01] +type=MinorOpClass +eventq_index=0 +opClass=FloatCmp + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02] +type=MinorOpClass +eventq_index=0 +opClass=FloatCvt + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03] +type=MinorOpClass +eventq_index=0 +opClass=FloatMisc + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04] +type=MinorOpClass +eventq_index=0 +opClass=FloatMult + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05] +type=MinorOpClass +eventq_index=0 +opClass=FloatMultAcc + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06] +type=MinorOpClass +eventq_index=0 +opClass=FloatDiv + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07] +type=MinorOpClass +eventq_index=0 +opClass=FloatSqrt + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08] +type=MinorOpClass +eventq_index=0 +opClass=SimdAdd + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09] +type=MinorOpClass +eventq_index=0 +opClass=SimdAddAcc + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10] +type=MinorOpClass +eventq_index=0 +opClass=SimdAlu + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11] +type=MinorOpClass +eventq_index=0 +opClass=SimdCmp + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12] +type=MinorOpClass +eventq_index=0 +opClass=SimdCvt + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13] +type=MinorOpClass +eventq_index=0 +opClass=SimdMisc + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14] +type=MinorOpClass +eventq_index=0 +opClass=SimdMult + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15] +type=MinorOpClass +eventq_index=0 +opClass=SimdMultAcc + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16] +type=MinorOpClass +eventq_index=0 +opClass=SimdShift + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17] +type=MinorOpClass +eventq_index=0 +opClass=SimdShiftAcc + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18] +type=MinorOpClass +eventq_index=0 +opClass=SimdSqrt + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatAdd + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatAlu + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatCmp + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatCvt + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatDiv + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatMisc + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatMult + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses26] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatMultAcc + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses27] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatSqrt + +[system.cpu.executeFuncUnits.funcUnits4.timings] +type=MinorFUTiming +children=opClasses +description=FloatSimd +eventq_index=0 +extraAssumedLat=0 +extraCommitLat=0 +extraCommitLatExpr=Null +mask=0 +match=0 +opClasses=system.cpu.executeFuncUnits.funcUnits4.timings.opClasses +srcRegsRelativeLats=2 +suppress=false + +[system.cpu.executeFuncUnits.funcUnits4.timings.opClasses] +type=MinorOpClassSet +eventq_index=0 +opClasses= + +[system.cpu.executeFuncUnits.funcUnits5] +type=MinorFU +children=opClasses timings +cantForwardFromFUIndices= +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses +opLat=1 +timings=system.cpu.executeFuncUnits.funcUnits5.timings + +[system.cpu.executeFuncUnits.funcUnits5.opClasses] +type=MinorOpClassSet +children=opClasses0 opClasses1 opClasses2 opClasses3 +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1 system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses2 system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses3 + +[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0] +type=MinorOpClass +eventq_index=0 +opClass=MemRead + +[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1] +type=MinorOpClass +eventq_index=0 +opClass=MemWrite + +[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses2] +type=MinorOpClass +eventq_index=0 +opClass=FloatMemRead + +[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses3] +type=MinorOpClass +eventq_index=0 +opClass=FloatMemWrite + +[system.cpu.executeFuncUnits.funcUnits5.timings] +type=MinorFUTiming +children=opClasses +description=Mem +eventq_index=0 +extraAssumedLat=2 +extraCommitLat=0 +extraCommitLatExpr=Null +mask=0 +match=0 +opClasses=system.cpu.executeFuncUnits.funcUnits5.timings.opClasses +srcRegsRelativeLats=1 +suppress=false + +[system.cpu.executeFuncUnits.funcUnits5.timings.opClasses] +type=MinorOpClassSet +eventq_index=0 +opClasses= + +[system.cpu.executeFuncUnits.funcUnits6] +type=MinorFU +children=opClasses +cantForwardFromFUIndices= +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses +opLat=1 +timings= + +[system.cpu.executeFuncUnits.funcUnits6.opClasses] +type=MinorOpClassSet +children=opClasses0 opClasses1 +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1 + +[system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0] +type=MinorOpClass +eventq_index=0 +opClass=IprAccess + +[system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1] +type=MinorOpClass +eventq_index=0 +opClass=InstPrefetch + +[system.cpu.icache] +type=Cache +children=tags +addr_ranges=0:18446744073709551615:0:0:0:0 +assoc=2 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +data_latency=2 +default_p_state=UNDEFINED +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=true +max_miss_count=0 +mshrs=4 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=131072 +system=system +tag_latency=2 +tags=system.cpu.icache.tags +tgts_per_mshr=20 +write_buffers=8 +writeback_clean=true +cpu_side=system.cpu.icache_port +mem_side=system.cpu.toL2Bus.slave[0] + +[system.cpu.icache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +data_latency=2 +default_p_state=UNDEFINED +eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +sequential_access=false +size=131072 +tag_latency=2 + +[system.cpu.interrupts] +type=RiscvInterrupts +eventq_index=0 + +[system.cpu.isa] +type=RiscvISA +eventq_index=0 + +[system.cpu.itb] +type=RiscvTLB +eventq_index=0 +size=64 + +[system.cpu.l2cache] +type=Cache +children=tags +addr_ranges=0:18446744073709551615:0:0:0:0 +assoc=8 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +data_latency=20 +default_p_state=UNDEFINED +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=20 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +prefetch_on_access=false +prefetcher=Null +response_latency=20 +sequential_access=false +size=2097152 +system=system +tag_latency=20 +tags=system.cpu.l2cache.tags +tgts_per_mshr=12 +write_buffers=8 +writeback_clean=false +cpu_side=system.cpu.toL2Bus.master[0] +mem_side=system.membus.slave[1] + +[system.cpu.l2cache.tags] +type=LRU +assoc=8 +block_size=64 +clk_domain=system.cpu_clk_domain +data_latency=20 +default_p_state=UNDEFINED +eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +sequential_access=false +size=2097152 +tag_latency=20 + +[system.cpu.toL2Bus] +type=CoherentXBar +children=snoop_filter +clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED +eventq_index=0 +forward_latency=0 +frontend_latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +point_of_coherency=false +power_model=Null +response_latency=1 +snoop_filter=system.cpu.toL2Bus.snoop_filter +snoop_response_latency=1 +system=system +use_default_range=false +width=32 +master=system.cpu.l2cache.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side + +[system.cpu.toL2Bus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=0 +max_capacity=8388608 +system=system + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=LiveProcess +cmd=insttest +cwd= +drivers= +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable=/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64i/insttest +gid=100 +input=cin +kvmInSE=false +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=0 +system=system +uid=100 +useArchPT=false + +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000000 + +[system.membus] +type=CoherentXBar +children=snoop_filter +clk_domain=system.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +forward_latency=4 +frontend_latency=3 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +point_of_coherency=true +power_model=Null +response_latency=2 +snoop_filter=system.membus.snoop_filter +snoop_response_latency=4 +system=system +use_default_range=false +width=16 +master=system.physmem.port +slave=system.system_port system.cpu.l2cache.mem_side + +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + +[system.physmem] +type=DRAMCtrl +IDD0=0.055000 +IDD02=0.000000 +IDD2N=0.032000 +IDD2N2=0.000000 +IDD2P0=0.000000 +IDD2P02=0.000000 +IDD2P1=0.032000 +IDD2P12=0.000000 +IDD3N=0.038000 +IDD3N2=0.000000 +IDD3P0=0.000000 +IDD3P02=0.000000 +IDD3P1=0.038000 +IDD3P12=0.000000 +IDD4R=0.157000 +IDD4R2=0.000000 +IDD4W=0.125000 +IDD4W2=0.000000 +IDD5=0.235000 +IDD52=0.000000 +IDD6=0.020000 +IDD62=0.000000 +VDD=1.500000 +VDD2=0.000000 +activation_limit=4 +addr_mapping=RoRaBaCoCh +bank_groups_per_rank=0 +banks_per_rank=8 +burst_length=8 +channels=1 +clk_domain=system.clk_domain +conf_table_reported=true +default_p_state=UNDEFINED +device_bus_width=8 +device_rowbuffer_size=1024 +device_size=536870912 +devices_per_rank=8 +dll=true +eventq_index=0 +in_addr_map=true +kvm_map=true +max_accesses_per_row=16 +mem_sched_policy=frfcfs +min_writes_per_switch=16 +null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +page_policy=open_adaptive +power_model=Null +range=0:134217727:0:0:0:0 +ranks_per_channel=2 +read_buffer_size=32 +static_backend_latency=10000 +static_frontend_latency=10000 +tBURST=5000 +tCCD_L=0 +tCK=1250 +tCL=13750 +tCS=2500 +tRAS=35000 +tRCD=13750 +tREFI=7800000 +tRFC=260000 +tRP=13750 +tRRD=6000 +tRRD_L=0 +tRTP=7500 +tRTW=2500 +tWR=15000 +tWTR=7500 +tXAW=30000 +tXP=6000 +tXPDLL=0 +tXS=270000 +tXSDLL=0 +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 +port=system.membus.master[0] + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/minor-timing/config.json b/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/minor-timing/config.json new file mode 100644 index 000000000..5ab2c4281 --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/minor-timing/config.json @@ -0,0 +1,1211 @@ +{ + "name": null, + "sim_quantum": 0, + "system": { + "kernel": "", + "mmap_using_noreserve": false, + "kernel_addr_check": true, + "membus": { + "point_of_coherency": true, + "system": "system", + "response_latency": 2, + "cxx_class": "CoherentXBar", + "forward_latency": 4, + "clk_domain": "system.clk_domain", + "width": 16, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "master": { + "peer": [ + "system.physmem.port" + ], + "role": "MASTER" + }, + "type": "CoherentXBar", + "frontend_latency": 3, + "slave": { + "peer": [ + "system.system_port", + "system.cpu.l2cache.mem_side" + ], + "role": "SLAVE" + }, + "p_state_clk_gate_min": 1000, + "snoop_filter": { + "name": "snoop_filter", + "system": "system", + "max_capacity": 8388608, + "eventq_index": 0, + "cxx_class": "SnoopFilter", + "path": "system.membus.snoop_filter", + "type": "SnoopFilter", + "lookup_latency": 1 + }, + "power_model": null, + "path": "system.membus", + "snoop_response_latency": 4, + "name": "membus", + "p_state_clk_gate_bins": 20, + "use_default_range": false + }, + "symbolfile": "", + "readfile": "", + "thermal_model": null, + "cxx_class": "System", + "work_begin_cpu_id_exit": -1, + "load_offset": 0, + "work_begin_exit_count": 0, + "p_state_clk_gate_min": 1000, + "memories": [ + "system.physmem" + ], + "work_begin_ckpt_count": 0, + "clk_domain": { + "name": "clk_domain", + "clock": [ + 1000 + ], + "init_perf_level": 0, + "voltage_domain": "system.voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "mem_ranges": [], + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "dvfs_handler": { + "enable": false, + "name": "dvfs_handler", + "sys_clk_domain": "system.clk_domain", + "transition_latency": 100000000, + "eventq_index": 0, + "cxx_class": "DVFSHandler", + "domains": [], + "path": "system.dvfs_handler", + "type": "DVFSHandler" + }, + "work_end_exit_count": 0, + "type": "System", + "voltage_domain": { + "name": "voltage_domain", + "eventq_index": 0, + "voltage": [ + "1.0" + ], + "cxx_class": "VoltageDomain", + "path": "system.voltage_domain", + "type": "VoltageDomain" + }, + "cache_line_size": 64, + "boot_osflags": "a", + "system_port": { + "peer": "system.membus.slave[0]", + "role": "MASTER" + }, + "physmem": { + "static_frontend_latency": 10000, + "tRFC": 260000, + "activation_limit": 4, + "in_addr_map": true, + "IDD3N2": "0.0", + "tWTR": 7500, + "IDD52": "0.0", + "clk_domain": "system.clk_domain", + "channels": 1, + "write_buffer_size": 64, + "device_bus_width": 8, + "VDD": "1.5", + "write_high_thresh_perc": 85, + "cxx_class": "DRAMCtrl", + "bank_groups_per_rank": 0, + "IDD2N2": "0.0", + "port": { + "peer": "system.membus.master[0]", + "role": "SLAVE" + }, + "tCCD_L": 0, + "IDD2N": "0.032", + "p_state_clk_gate_min": 1000, + "null": false, + "IDD2P1": "0.032", + "eventq_index": 0, + "tRRD": 6000, + "tRTW": 2500, + "IDD4R": "0.157", + "burst_length": 8, + "tRTP": 7500, + "IDD4W": "0.125", + "tWR": 15000, + "banks_per_rank": 8, + "devices_per_rank": 8, + "IDD2P02": "0.0", + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "IDD6": "0.02", + "IDD5": "0.235", + "tRCD": 13750, + "type": "DRAMCtrl", + "IDD3P02": "0.0", + "tRRD_L": 0, + "IDD0": "0.055", + "IDD62": "0.0", + "min_writes_per_switch": 16, + "mem_sched_policy": "frfcfs", + "IDD02": "0.0", + "IDD2P0": "0.0", + "ranks_per_channel": 2, + "page_policy": "open_adaptive", + "IDD4W2": "0.0", + "tCS": 2500, + "power_model": null, + "tCL": 13750, + "read_buffer_size": 32, + "conf_table_reported": true, + "tCK": 1250, + "tRAS": 35000, + "tRP": 13750, + "tBURST": 5000, + "path": "system.physmem", + "tXP": 6000, + "tXS": 270000, + "addr_mapping": "RoRaBaCoCh", + "IDD3P0": "0.0", + "IDD3P1": "0.038", + "IDD3N": "0.038", + "name": "physmem", + "tXSDLL": 0, + "device_size": 536870912, + "kvm_map": true, + "dll": true, + "tXAW": 30000, + "write_low_thresh_perc": 50, + "range": "0:134217727:0:0:0:0", + "VDD2": "0.0", + "IDD2P12": "0.0", + "p_state_clk_gate_bins": 20, + "tXPDLL": 0, + "IDD4R2": "0.0", + "device_rowbuffer_size": 1024, + "static_backend_latency": 10000, + "max_accesses_per_row": 16, + "IDD3P12": "0.0", + "tREFI": 7800000 + }, + "power_model": null, + "work_cpus_ckpt_count": 0, + "thermal_components": [], + "path": "system", + "cpu_clk_domain": { + "name": "cpu_clk_domain", + "clock": [ + 500 + ], + "init_perf_level": 0, + "voltage_domain": "system.voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.cpu_clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "work_end_ckpt_count": 0, + "mem_mode": "timing", + "name": "system", + "init_param": 0, + "p_state_clk_gate_bins": 20, + "load_addr_mask": 1099511627775, + "cpu": [ + { + "max_insts_any_thread": 0, + "do_statistics_insts": true, + "numThreads": 1, + "fetch1LineSnapWidth": 0, + "fetch1ToFetch2BackwardDelay": 1, + "fetch1FetchLimit": 1, + "executeIssueLimit": 2, + "system": "system", + "executeLSQMaxStoreBufferStoresPerCycle": 2, + "icache": { + "cpu_side": { + "peer": "system.cpu.icache_port", + "role": "SLAVE" + }, + "clusivity": "mostly_incl", + "prefetcher": null, + "system": "system", + "write_buffers": 8, + "response_latency": 2, + "cxx_class": "Cache", + "size": 131072, + "type": "Cache", + "clk_domain": "system.cpu_clk_domain", + "max_miss_count": 0, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "mem_side": { + "peer": "system.cpu.toL2Bus.slave[0]", + "role": "MASTER" + }, + "mshrs": 4, + "writeback_clean": true, + "p_state_clk_gate_min": 1000, + "tags": { + "size": 131072, + "tag_latency": 2, + "name": "tags", + "p_state_clk_gate_min": 1000, + "eventq_index": 0, + "p_state_clk_gate_bins": 20, + "default_p_state": "UNDEFINED", + "clk_domain": "system.cpu_clk_domain", + "power_model": null, + "sequential_access": false, + "assoc": 2, + "cxx_class": "LRU", + "p_state_clk_gate_max": 1000000000000, + "path": "system.cpu.icache.tags", + "block_size": 64, + "type": "LRU", + "data_latency": 2 + }, + "tgts_per_mshr": 20, + "demand_mshr_reserve": 1, + "power_model": null, + "addr_ranges": [ + "0:18446744073709551615:0:0:0:0" + ], + "is_read_only": true, + "prefetch_on_access": false, + "path": "system.cpu.icache", + "data_latency": 2, + "tag_latency": 2, + "name": "icache", + "p_state_clk_gate_bins": 20, + "sequential_access": false, + "assoc": 2 + }, + "function_trace": false, + "do_checkpoint_insts": true, + "decodeInputWidth": 2, + "cxx_class": "MinorCPU", + "max_loads_all_threads": 0, + "executeMemoryIssueLimit": 1, + "decodeCycleInput": true, + "max_loads_any_thread": 0, + "executeLSQTransfersQueueSize": 2, + "p_state_clk_gate_max": 1000000000000, + "clk_domain": "system.cpu_clk_domain", + "function_trace_start": 0, + "cpu_id": 0, + "checker": null, + "eventq_index": 0, + "executeMemoryWidth": 0, + "default_p_state": "UNDEFINED", + "executeBranchDelay": 1, + "executeMemoryCommitLimit": 1, + "l2cache": { + "cpu_side": { + "peer": "system.cpu.toL2Bus.master[0]", + "role": "SLAVE" + }, + "clusivity": "mostly_incl", + "prefetcher": null, + "system": "system", + "write_buffers": 8, + "response_latency": 20, + "cxx_class": "Cache", + "size": 2097152, + "type": "Cache", + "clk_domain": "system.cpu_clk_domain", + "max_miss_count": 0, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "mem_side": { + "peer": "system.membus.slave[1]", + "role": "MASTER" + }, + "mshrs": 20, + "writeback_clean": false, + "p_state_clk_gate_min": 1000, + "tags": { + "size": 2097152, + "tag_latency": 20, + "name": "tags", + "p_state_clk_gate_min": 1000, + "eventq_index": 0, + "p_state_clk_gate_bins": 20, + "default_p_state": "UNDEFINED", + "clk_domain": "system.cpu_clk_domain", + "power_model": null, + "sequential_access": false, + "assoc": 8, + "cxx_class": "LRU", + "p_state_clk_gate_max": 1000000000000, + "path": "system.cpu.l2cache.tags", + "block_size": 64, + "type": "LRU", + "data_latency": 20 + }, + "tgts_per_mshr": 12, + "demand_mshr_reserve": 1, + "power_model": null, + "addr_ranges": [ + "0:18446744073709551615:0:0:0:0" + ], + "is_read_only": false, + "prefetch_on_access": false, + "path": "system.cpu.l2cache", + "data_latency": 20, + "tag_latency": 20, + "name": "l2cache", + "p_state_clk_gate_bins": 20, + "sequential_access": false, + "assoc": 8 + }, + "do_quiesce": true, + "type": "MinorCPU", + "executeCycleInput": true, + "executeAllowEarlyMemoryIssue": true, + "executeInputBufferSize": 7, + "icache_port": { + "peer": "system.cpu.icache.cpu_side", + "role": "MASTER" + }, + "p_state_clk_gate_bins": 20, + "socket_id": 0, + "progress_interval": 0, + "p_state_clk_gate_min": 1000, + "toL2Bus": { + "point_of_coherency": false, + "system": "system", + "response_latency": 1, + "cxx_class": "CoherentXBar", + "forward_latency": 0, + "clk_domain": "system.cpu_clk_domain", + "width": 32, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "master": { + "peer": [ + "system.cpu.l2cache.cpu_side" + ], + "role": "MASTER" + }, + "type": "CoherentXBar", + "frontend_latency": 1, + "slave": { + "peer": [ + "system.cpu.icache.mem_side", + "system.cpu.dcache.mem_side" + ], + "role": "SLAVE" + }, + "p_state_clk_gate_min": 1000, + "snoop_filter": { + "name": "snoop_filter", + "system": "system", + "max_capacity": 8388608, + "eventq_index": 0, + "cxx_class": "SnoopFilter", + "path": "system.cpu.toL2Bus.snoop_filter", + "type": "SnoopFilter", + "lookup_latency": 0 + }, + "power_model": null, + "path": "system.cpu.toL2Bus", + "snoop_response_latency": 1, + "name": "toL2Bus", + "p_state_clk_gate_bins": 20, + "use_default_range": false + }, + "isa": [ + { + "eventq_index": 0, + "path": "system.cpu.isa", + "type": "RiscvISA", + "name": "isa", + "cxx_class": "RiscvISA::ISA" + } + ], + "itb": { + "name": "itb", + "eventq_index": 0, + "cxx_class": "RiscvISA::TLB", + "path": "system.cpu.itb", + "type": "RiscvTLB", + "size": 64 + }, + "interrupts": [ + { + "eventq_index": 0, + "path": "system.cpu.interrupts", + "type": "RiscvInterrupts", + "name": "interrupts", + "cxx_class": "RiscvISA::Interrupts" + } + ], + "dcache_port": { + "peer": "system.cpu.dcache.cpu_side", + "role": "MASTER" + }, + "executeFuncUnits": { + "name": "executeFuncUnits", + "eventq_index": 0, + "cxx_class": "MinorFUPool", + "path": "system.cpu.executeFuncUnits", + "funcUnits": [ + { + "issueLat": 1, + "opLat": 3, + "name": "funcUnits0", + "cantForwardFromFUIndices": [], + "opClasses": { + "name": "opClasses", + "opClasses": [ + { + "opClass": "IntAlu", + "name": "opClasses", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses", + "type": "MinorOpClass" + } + ], + "eventq_index": 0, + "cxx_class": "MinorOpClassSet", + "path": "system.cpu.executeFuncUnits.funcUnits0.opClasses", + "type": "MinorOpClassSet" + }, + "eventq_index": 0, + "timings": [ + { + "extraAssumedLat": 0, + "description": "Int", + "srcRegsRelativeLats": [ + 2 + ], + "suppress": false, + "mask": 0, + "extraCommitLat": 0, + "eventq_index": 0, + "opClasses": { + "name": "opClasses", + "opClasses": [], + "eventq_index": 0, + "cxx_class": "MinorOpClassSet", + "path": "system.cpu.executeFuncUnits.funcUnits0.timings.opClasses", + "type": "MinorOpClassSet" + }, + "cxx_class": "MinorFUTiming", + "path": "system.cpu.executeFuncUnits.funcUnits0.timings", + "extraCommitLatExpr": null, + "type": "MinorFUTiming", + "match": 0, + "name": "timings" + } + ], + "cxx_class": "MinorFU", + "path": "system.cpu.executeFuncUnits.funcUnits0", + "type": "MinorFU" + }, + { + "issueLat": 1, + "opLat": 3, + "name": "funcUnits1", + "cantForwardFromFUIndices": [], + "opClasses": { + "name": "opClasses", + "opClasses": [ + { + "opClass": "IntAlu", + "name": "opClasses", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses", + "type": "MinorOpClass" + } + ], + "eventq_index": 0, + "cxx_class": "MinorOpClassSet", + "path": "system.cpu.executeFuncUnits.funcUnits1.opClasses", + "type": "MinorOpClassSet" + }, + "eventq_index": 0, + "timings": [ + { + "extraAssumedLat": 0, + "description": "Int", + "srcRegsRelativeLats": [ + 2 + ], + "suppress": false, + "mask": 0, + "extraCommitLat": 0, + "eventq_index": 0, + "opClasses": { + "name": "opClasses", + "opClasses": [], + "eventq_index": 0, + "cxx_class": "MinorOpClassSet", + "path": "system.cpu.executeFuncUnits.funcUnits1.timings.opClasses", + "type": "MinorOpClassSet" + }, + "cxx_class": "MinorFUTiming", + "path": "system.cpu.executeFuncUnits.funcUnits1.timings", + "extraCommitLatExpr": null, + "type": "MinorFUTiming", + "match": 0, + "name": "timings" + } + ], + "cxx_class": "MinorFU", + "path": "system.cpu.executeFuncUnits.funcUnits1", + "type": "MinorFU" + }, + { + "issueLat": 1, + "opLat": 3, + "name": "funcUnits2", + "cantForwardFromFUIndices": [], + "opClasses": { + "name": "opClasses", + "opClasses": [ + { + "opClass": "IntMult", + "name": "opClasses", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses", + "type": "MinorOpClass" + } + ], + "eventq_index": 0, + "cxx_class": "MinorOpClassSet", + "path": "system.cpu.executeFuncUnits.funcUnits2.opClasses", + "type": "MinorOpClassSet" + }, + "eventq_index": 0, + "timings": [ + { + "extraAssumedLat": 0, + "description": "Mul", + "srcRegsRelativeLats": [ + 0 + ], + "suppress": false, + "mask": 0, + "extraCommitLat": 0, + "eventq_index": 0, + "opClasses": { + "name": "opClasses", + "opClasses": [], + "eventq_index": 0, + "cxx_class": "MinorOpClassSet", + "path": "system.cpu.executeFuncUnits.funcUnits2.timings.opClasses", + "type": "MinorOpClassSet" + }, + "cxx_class": "MinorFUTiming", + "path": "system.cpu.executeFuncUnits.funcUnits2.timings", + "extraCommitLatExpr": null, + "type": "MinorFUTiming", + "match": 0, + "name": "timings" + } + ], + "cxx_class": "MinorFU", + "path": "system.cpu.executeFuncUnits.funcUnits2", + "type": "MinorFU" + }, + { + "issueLat": 9, + "opLat": 9, + "name": "funcUnits3", + "cantForwardFromFUIndices": [], + "opClasses": { + "name": "opClasses", + "opClasses": [ + { + "opClass": "IntDiv", + "name": "opClasses", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses", + "type": "MinorOpClass" + } + ], + "eventq_index": 0, + "cxx_class": "MinorOpClassSet", + "path": "system.cpu.executeFuncUnits.funcUnits3.opClasses", + "type": "MinorOpClassSet" + }, + "eventq_index": 0, + "timings": [], + "cxx_class": "MinorFU", + "path": "system.cpu.executeFuncUnits.funcUnits3", + "type": "MinorFU" + }, + { + "issueLat": 1, + "opLat": 6, + "name": "funcUnits4", + "cantForwardFromFUIndices": [], + "opClasses": { + "name": "opClasses", + "opClasses": [ + { + "opClass": "FloatAdd", + "name": "opClasses00", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00", + "type": "MinorOpClass" + }, + { + "opClass": "FloatCmp", + "name": "opClasses01", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01", + "type": "MinorOpClass" + }, + { + "opClass": "FloatCvt", + "name": "opClasses02", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02", + "type": "MinorOpClass" + }, + { + "opClass": "FloatMisc", + "name": "opClasses03", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03", + "type": "MinorOpClass" + }, + { + "opClass": "FloatMult", + "name": "opClasses04", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04", + "type": "MinorOpClass" + }, + { + "opClass": "FloatMultAcc", + "name": "opClasses05", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05", + "type": "MinorOpClass" + }, + { + "opClass": "FloatDiv", + "name": "opClasses06", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06", + "type": "MinorOpClass" + }, + { + "opClass": "FloatSqrt", + "name": "opClasses07", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07", + "type": "MinorOpClass" + }, + { + "opClass": "SimdAdd", + "name": "opClasses08", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08", + "type": "MinorOpClass" + }, + { + "opClass": "SimdAddAcc", + "name": "opClasses09", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09", + "type": "MinorOpClass" + }, + { + "opClass": "SimdAlu", + "name": "opClasses10", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10", + "type": "MinorOpClass" + }, + { + "opClass": "SimdCmp", + "name": "opClasses11", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11", + "type": "MinorOpClass" + }, + { + "opClass": "SimdCvt", + "name": "opClasses12", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12", + "type": "MinorOpClass" + }, + { + "opClass": "SimdMisc", + "name": "opClasses13", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13", + "type": "MinorOpClass" + }, + { + "opClass": "SimdMult", + "name": "opClasses14", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14", + "type": "MinorOpClass" + }, + { + "opClass": "SimdMultAcc", + "name": "opClasses15", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15", + "type": "MinorOpClass" + }, + { + "opClass": "SimdShift", + "name": "opClasses16", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16", + "type": "MinorOpClass" + }, + { + "opClass": "SimdShiftAcc", + "name": "opClasses17", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17", + "type": "MinorOpClass" + }, + { + "opClass": "SimdSqrt", + "name": "opClasses18", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18", + "type": "MinorOpClass" + }, + { + "opClass": "SimdFloatAdd", + "name": "opClasses19", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19", + "type": "MinorOpClass" + }, + { + "opClass": "SimdFloatAlu", + "name": "opClasses20", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20", + "type": "MinorOpClass" + }, + { + "opClass": "SimdFloatCmp", + "name": "opClasses21", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21", + "type": "MinorOpClass" + }, + { + "opClass": "SimdFloatCvt", + "name": "opClasses22", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22", + "type": "MinorOpClass" + }, + { + "opClass": "SimdFloatDiv", + "name": "opClasses23", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23", + "type": "MinorOpClass" + }, + { + "opClass": "SimdFloatMisc", + "name": "opClasses24", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24", + "type": "MinorOpClass" + }, + { + "opClass": "SimdFloatMult", + "name": "opClasses25", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25", + "type": "MinorOpClass" + }, + { + "opClass": "SimdFloatMultAcc", + "name": "opClasses26", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses26", + "type": "MinorOpClass" + }, + { + "opClass": "SimdFloatSqrt", + "name": "opClasses27", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses27", + "type": "MinorOpClass" + } + ], + "eventq_index": 0, + "cxx_class": "MinorOpClassSet", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses", + "type": "MinorOpClassSet" + }, + "eventq_index": 0, + "timings": [ + { + "extraAssumedLat": 0, + "description": "FloatSimd", + "srcRegsRelativeLats": [ + 2 + ], + "suppress": false, + "mask": 0, + "extraCommitLat": 0, + "eventq_index": 0, + "opClasses": { + "name": "opClasses", + "opClasses": [], + "eventq_index": 0, + "cxx_class": "MinorOpClassSet", + "path": "system.cpu.executeFuncUnits.funcUnits4.timings.opClasses", + "type": "MinorOpClassSet" + }, + "cxx_class": "MinorFUTiming", + "path": "system.cpu.executeFuncUnits.funcUnits4.timings", + "extraCommitLatExpr": null, + "type": "MinorFUTiming", + "match": 0, + "name": "timings" + } + ], + "cxx_class": "MinorFU", + "path": "system.cpu.executeFuncUnits.funcUnits4", + "type": "MinorFU" + }, + { + "issueLat": 1, + "opLat": 1, + "name": "funcUnits5", + "cantForwardFromFUIndices": [], + "opClasses": { + "name": "opClasses", + "opClasses": [ + { + "opClass": "MemRead", + "name": "opClasses0", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0", + "type": "MinorOpClass" + }, + { + "opClass": "MemWrite", + "name": "opClasses1", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1", + "type": "MinorOpClass" + }, + { + "opClass": "FloatMemRead", + "name": "opClasses2", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses2", + "type": "MinorOpClass" + }, + { + "opClass": "FloatMemWrite", + "name": "opClasses3", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses3", + "type": "MinorOpClass" + } + ], + "eventq_index": 0, + "cxx_class": "MinorOpClassSet", + "path": "system.cpu.executeFuncUnits.funcUnits5.opClasses", + "type": "MinorOpClassSet" + }, + "eventq_index": 0, + "timings": [ + { + "extraAssumedLat": 2, + "description": "Mem", + "srcRegsRelativeLats": [ + 1 + ], + "suppress": false, + "mask": 0, + "extraCommitLat": 0, + "eventq_index": 0, + "opClasses": { + "name": "opClasses", + "opClasses": [], + "eventq_index": 0, + "cxx_class": "MinorOpClassSet", + "path": "system.cpu.executeFuncUnits.funcUnits5.timings.opClasses", + "type": "MinorOpClassSet" + }, + "cxx_class": "MinorFUTiming", + "path": "system.cpu.executeFuncUnits.funcUnits5.timings", + "extraCommitLatExpr": null, + "type": "MinorFUTiming", + "match": 0, + "name": "timings" + } + ], + "cxx_class": "MinorFU", + "path": "system.cpu.executeFuncUnits.funcUnits5", + "type": "MinorFU" + }, + { + "issueLat": 1, + "opLat": 1, + "name": "funcUnits6", + "cantForwardFromFUIndices": [], + "opClasses": { + "name": "opClasses", + "opClasses": [ + { + "opClass": "IprAccess", + "name": "opClasses0", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0", + "type": "MinorOpClass" + }, + { + "opClass": "InstPrefetch", + "name": "opClasses1", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1", + "type": "MinorOpClass" + } + ], + "eventq_index": 0, + "cxx_class": "MinorOpClassSet", + "path": "system.cpu.executeFuncUnits.funcUnits6.opClasses", + "type": "MinorOpClassSet" + }, + "eventq_index": 0, + "timings": [], + "cxx_class": "MinorFU", + "path": "system.cpu.executeFuncUnits.funcUnits6", + "type": "MinorFU" + } + ], + "type": "MinorFUPool" + }, + "switched_out": false, + "power_model": null, + "max_insts_all_threads": 0, + "executeSetTraceTimeOnIssue": false, + "fetch2InputBufferSize": 2, + "profile": 0, + "fetch2ToDecodeForwardDelay": 1, + "executeInputWidth": 2, + "decodeToExecuteForwardDelay": 1, + "executeLSQRequestsQueueSize": 1, + "fetch2CycleInput": true, + "executeMaxAccessesInMemory": 2, + "enableIdling": true, + "executeLSQStoreBufferSize": 5, + "workload": [ + { + "uid": 100, + "pid": 100, + "kvmInSE": false, + "cxx_class": "LiveProcess", + "executable": "/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64i/insttest", + "drivers": [], + "system": "system", + "gid": 100, + "eventq_index": 0, + "env": [], + "input": "cin", + "ppid": 99, + "type": "LiveProcess", + "cwd": "", + "simpoint": 0, + "euid": 100, + "path": "system.cpu.workload", + "max_stack_size": 67108864, + "name": "workload", + "cmd": [ + "insttest" + ], + "errout": "cerr", + "useArchPT": false, + "egid": 100, + "output": "cout" + } + ], + "name": "cpu", + "dtb": { + "name": "dtb", + "eventq_index": 0, + "cxx_class": "RiscvISA::TLB", + "path": "system.cpu.dtb", + "type": "RiscvTLB", + "size": 64 + }, + "simpoint_start_insts": [], + "executeSetTraceTimeOnCommit": true, + "tracer": { + "eventq_index": 0, + "path": "system.cpu.tracer", + "type": "ExeTracer", + "name": "tracer", + "cxx_class": "Trace::ExeTracer" + }, + "threadPolicy": "RoundRobin", + "executeCommitLimit": 2, + "fetch1LineWidth": 0, + "branchPred": { + "numThreads": 1, + "BTBEntries": 4096, + "cxx_class": "TournamentBP", + "indirectPathLength": 3, + "globalCtrBits": 2, + "choicePredictorSize": 8192, + "indirectHashGHR": true, + "eventq_index": 0, + "localHistoryTableSize": 2048, + "type": "TournamentBP", + "indirectSets": 256, + "indirectWays": 2, + "choiceCtrBits": 2, + "useIndirect": true, + "localCtrBits": 2, + "path": "system.cpu.branchPred", + "localPredictorSize": 2048, + "RASSize": 16, + "globalPredictorSize": 8192, + "name": "branchPred", + "indirectHashTargets": true, + "instShiftAmt": 2, + "indirectTagSize": 16, + "BTBTagSize": 16 + }, + "dcache": { + "cpu_side": { + "peer": "system.cpu.dcache_port", + "role": "SLAVE" + }, + "clusivity": "mostly_incl", + "prefetcher": null, + "system": "system", + "write_buffers": 8, + "response_latency": 2, + "cxx_class": "Cache", + "size": 262144, + "type": "Cache", + "clk_domain": "system.cpu_clk_domain", + "max_miss_count": 0, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "mem_side": { + "peer": "system.cpu.toL2Bus.slave[1]", + "role": "MASTER" + }, + "mshrs": 4, + "writeback_clean": false, + "p_state_clk_gate_min": 1000, + "tags": { + "size": 262144, + "tag_latency": 2, + "name": "tags", + "p_state_clk_gate_min": 1000, + "eventq_index": 0, + "p_state_clk_gate_bins": 20, + "default_p_state": "UNDEFINED", + "clk_domain": "system.cpu_clk_domain", + "power_model": null, + "sequential_access": false, + "assoc": 2, + "cxx_class": "LRU", + "p_state_clk_gate_max": 1000000000000, + "path": "system.cpu.dcache.tags", + "block_size": 64, + "type": "LRU", + "data_latency": 2 + }, + "tgts_per_mshr": 20, + "demand_mshr_reserve": 1, + "power_model": null, + "addr_ranges": [ + "0:18446744073709551615:0:0:0:0" + ], + "is_read_only": false, + "prefetch_on_access": false, + "path": "system.cpu.dcache", + "data_latency": 2, + "tag_latency": 2, + "name": "dcache", + "p_state_clk_gate_bins": 20, + "sequential_access": false, + "assoc": 2 + }, + "path": "system.cpu", + "fetch1ToFetch2ForwardDelay": 1, + "decodeInputBufferSize": 3 + } + ], + "multi_thread": false, + "exit_on_work_items": false, + "work_item_id": -1, + "num_work_ids": 16 + }, + "time_sync_period": 100000000000, + "eventq_index": 0, + "time_sync_spin_threshold": 100000000, + "cxx_class": "Root", + "path": "root", + "time_sync_enable": false, + "type": "Root", + "full_system": false +}
\ No newline at end of file diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/minor-timing/simerr b/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/minor-timing/simerr new file mode 100755 index 000000000..85a6a33ad --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/minor-timing/simerr @@ -0,0 +1,4 @@ +warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes) +warn: Unknown operating system; assuming Linux. +warn: Sockets disabled, not accepting gdb connections +warn: ClockedObject: More than one power state change request encountered within the same simulation tick diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/minor-timing/simout b/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/minor-timing/simout new file mode 100755 index 000000000..5f73fd76b --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/minor-timing/simout @@ -0,0 +1,121 @@ +Redirecting stdout to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64i/minor-timing/simout +Redirecting stderr to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64i/minor-timing/simerr +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled Nov 30 2016 14:33:35 +gem5 started Nov 30 2016 16:18:43 +gem5 executing on zizzer, pid 34087 +command line: /z/powerjg/gem5-upstream/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64i/minor-timing -re /z/powerjg/gem5-upstream/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64i/minor-timing + +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. +lui: PASS +lui, negative: PASS +auipc: 0x157E0 +auipc: PASS +jal: PASS +jalr: PASS +beq, equal: PASS +beq, not equal: PASS +bne, equal: PASS +bne, not equal: PASS +blt, less: PASS +blt, equal: PASS +blt, greater: PASS +bge, less: PASS +bge, equal: PASS +bge, greater: PASS +bltu, greater: PASS +bltu, equal: PASS +bltu, less: PASS +bgeu, greater: PASS +bgeu, equal: PASS +bgeu, less: PASS +lb, positive: PASS +lb, negative: PASS +lh, positive: PASS +lh, negative: PASS +lw, positive: PASS +lw, negative: PASS +lbu: PASS +lhu: PASS +sb: PASS +sh: PASS +sw: PASS +addi: PASS +addi, overflow: PASS +slti, true: PASS +slti, false: PASS +sltiu, false: PASS +sltiu, true: PASS +xori (1): PASS +xori (0): PASS +ori (1): PASS +ori (A): PASS +andi (0): PASS +andi (1): PASS +slli, general: PASS +slli, erase: PASS +srli, general: PASS +srli, erase: PASS +srli, negative: PASS +srai, general: PASS +srai, erase: PASS +srai, negative: PASS +add: PASS +add, overflow: PASS +sub: PASS +sub, "overflow": PASS +sll, general: PASS +sll, erase: PASS +slt, true: PASS +slt, false: PASS +sltu, false: PASS +sltu, true: PASS +xor (1): PASS +xor (0): PASS +srl, general: PASS +srl, erase: PASS +srl, negative: PASS +sra, general: PASS +sra, erase: PASS +sra, negative: PASS +or (1): PASS +or (A): PASS +and (0): PASS +and (-1): PASS +Bytes written: 15 +open, write: PASS +access F_OK: PASS +access R_OK: PASS +access W_OK: PASS +access X_OK: PASS +stat: + st_dev = 2054 + st_ino = 55451710 + st_mode = 33188 + st_nlink = 1 + st_uid = 1004 + st_gid = 1007 + st_rdev = 0 + st_size = 0 + st_blksize = 0 + st_blocks = 1480540730 +fstat: + st_dev = 2054 + st_ino = 55451710 + st_mode = 33188 + st_nlink = 1 + st_uid = 1004 + st_gid = 1007 + st_rdev = 0 + st_size = 0 + st_blksize = 0 + st_blocks = 1480540730 +open, stat: PASS +Bytes read: 1 +String read: +open, read, unlink: [1;31mFAIL[0m (expected 1; found 0) +Exiting @ tick 257396500 because target called exit() diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/minor-timing/stats.txt b/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/minor-timing/stats.txt new file mode 100644 index 000000000..b9db11c0c --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/minor-timing/stats.txt @@ -0,0 +1,761 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.000257 # Number of seconds simulated +sim_ticks 257396500 # Number of ticks simulated +final_tick 257396500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 23064 # Simulator instruction rate (inst/s) +host_op_rate 23064 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 29446323 # Simulator tick rate (ticks/s) +host_mem_usage 244684 # Number of bytes of host memory used +host_seconds 8.74 # Real time elapsed on the host +sim_insts 201609 # Number of instructions simulated +sim_ops 201609 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 257396500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 70720 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 18880 # Number of bytes read from this memory +system.physmem.bytes_read::total 89600 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 70720 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 70720 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 1105 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 295 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1400 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 274751211 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 73349871 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 348101081 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 274751211 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 274751211 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 274751211 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 73349871 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 348101081 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1400 # Number of read requests accepted +system.physmem.writeReqs 0 # Number of write requests accepted +system.physmem.readBursts 1400 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 89600 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue +system.physmem.bytesWritten 0 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 89600 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 195 # Per bank write bursts +system.physmem.perBankRdBursts::1 221 # Per bank write bursts +system.physmem.perBankRdBursts::2 35 # Per bank write bursts +system.physmem.perBankRdBursts::3 87 # Per bank write bursts +system.physmem.perBankRdBursts::4 141 # Per bank write bursts +system.physmem.perBankRdBursts::5 86 # Per bank write bursts +system.physmem.perBankRdBursts::6 5 # Per bank write bursts +system.physmem.perBankRdBursts::7 106 # Per bank write bursts +system.physmem.perBankRdBursts::8 78 # Per bank write bursts +system.physmem.perBankRdBursts::9 96 # Per bank write bursts +system.physmem.perBankRdBursts::10 80 # Per bank write bursts +system.physmem.perBankRdBursts::11 128 # Per bank write bursts +system.physmem.perBankRdBursts::12 40 # Per bank write bursts +system.physmem.perBankRdBursts::13 27 # Per bank write bursts +system.physmem.perBankRdBursts::14 51 # Per bank write bursts +system.physmem.perBankRdBursts::15 24 # Per bank write bursts +system.physmem.perBankWrBursts::0 0 # Per bank write bursts +system.physmem.perBankWrBursts::1 0 # Per bank write bursts +system.physmem.perBankWrBursts::2 0 # Per bank write bursts +system.physmem.perBankWrBursts::3 0 # Per bank write bursts +system.physmem.perBankWrBursts::4 0 # Per bank write bursts +system.physmem.perBankWrBursts::5 0 # Per bank write bursts +system.physmem.perBankWrBursts::6 0 # Per bank write bursts +system.physmem.perBankWrBursts::7 0 # Per bank write bursts +system.physmem.perBankWrBursts::8 0 # Per bank write bursts +system.physmem.perBankWrBursts::9 0 # Per bank write bursts +system.physmem.perBankWrBursts::10 0 # Per bank write bursts +system.physmem.perBankWrBursts::11 0 # Per bank write bursts +system.physmem.perBankWrBursts::12 0 # Per bank write bursts +system.physmem.perBankWrBursts::13 0 # Per bank write bursts +system.physmem.perBankWrBursts::14 0 # Per bank write bursts +system.physmem.perBankWrBursts::15 0 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 257156500 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 1400 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 0 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1337 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 60 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 274 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 323.270073 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 216.910663 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 283.246990 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 71 25.91% 25.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 59 21.53% 47.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 52 18.98% 66.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 26 9.49% 75.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 14 5.11% 81.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 23 8.39% 89.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 8 2.92% 92.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 3 1.09% 93.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 18 6.57% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 274 # Bytes accessed per row activation +system.physmem.totQLat 19864500 # Total ticks spent queuing +system.physmem.totMemAccLat 46114500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 7000000 # Total ticks spent in databus transfers +system.physmem.avgQLat 14188.93 # Average queueing delay per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 32938.93 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 348.10 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 348.10 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.busUtil 2.72 # Data bus utilization in percentage +system.physmem.busUtilRead 2.72 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing +system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing +system.physmem.readRowHits 1124 # Number of row buffer hits during reads +system.physmem.writeRowHits 0 # Number of row buffer hits during writes +system.physmem.readRowHitRate 80.29 # Row buffer hit rate for reads +system.physmem.writeRowHitRate nan # Row buffer hit rate for writes +system.physmem.avgGap 183683.21 # Average gap between requests +system.physmem.pageHitRate 80.29 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 1299480 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 690690 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 6254640 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 20283120.000000 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 14953950 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 477120 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 94483770 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 6205440 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 144648210 # Total energy per rank (pJ) +system.physmem_0.averagePower 561.964316 # Core power per rank (mW) +system.physmem_0.totalIdleTime 223185500 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 210000 # Time in different power states +system.physmem_0.memoryStateTime::REF 8580000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 0 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 16154500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 25250500 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 207201500 # Time in different power states +system.physmem_1.actEnergy 671160 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 349140 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 3741360 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 14751360.000000 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 9433500 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 3408960 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 53834790 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 13144800 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 18682440 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 118017510 # Total energy per rank (pJ) +system.physmem_1.averagePower 458.502938 # Core power per rank (mW) +system.physmem_1.totalIdleTime 227632750 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 8194250 # Time in different power states +system.physmem_1.memoryStateTime::REF 6246000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 75541750 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 34227000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 15120250 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 118067250 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 257396500 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 58095 # Number of BP lookups +system.cpu.branchPred.condPredicted 37339 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 4808 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 47628 # Number of BTB lookups +system.cpu.branchPred.BTBHits 25748 # Number of BTB hits +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 54.060637 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 0 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 9498 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 5462 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 4036 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 2282 # Number of mispredicted indirect branches. +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 130 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 257396500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 514793 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 201609 # Number of instructions committed +system.cpu.committedOps 201609 # Number of ops (including micro ops) committed +system.cpu.discardedOps 12686 # Number of ops (including micro ops) which were discarded before commit +system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching +system.cpu.cpi 2.553423 # CPI: cycles per instruction +system.cpu.ipc 0.391631 # IPC: instructions per cycle +system.cpu.op_class_0::No_OpClass 132 0.07% 0.07% # Class of committed instruction +system.cpu.op_class_0::IntAlu 120936 59.99% 60.05% # Class of committed instruction +system.cpu.op_class_0::IntMult 297 0.15% 60.20% # Class of committed instruction +system.cpu.op_class_0::IntDiv 166 0.08% 60.28% # Class of committed instruction +system.cpu.op_class_0::FloatAdd 0 0.00% 60.28% # Class of committed instruction +system.cpu.op_class_0::FloatCmp 0 0.00% 60.28% # Class of committed instruction +system.cpu.op_class_0::FloatCvt 0 0.00% 60.28% # Class of committed instruction +system.cpu.op_class_0::FloatMult 0 0.00% 60.28% # Class of committed instruction +system.cpu.op_class_0::FloatMultAcc 0 0.00% 60.28% # Class of committed instruction +system.cpu.op_class_0::FloatDiv 0 0.00% 60.28% # Class of committed instruction +system.cpu.op_class_0::FloatMisc 0 0.00% 60.28% # Class of committed instruction +system.cpu.op_class_0::FloatSqrt 0 0.00% 60.28% # Class of committed instruction +system.cpu.op_class_0::SimdAdd 0 0.00% 60.28% # Class of committed instruction +system.cpu.op_class_0::SimdAddAcc 0 0.00% 60.28% # Class of committed instruction +system.cpu.op_class_0::SimdAlu 0 0.00% 60.28% # Class of committed instruction +system.cpu.op_class_0::SimdCmp 0 0.00% 60.28% # Class of committed instruction +system.cpu.op_class_0::SimdCvt 0 0.00% 60.28% # Class of committed instruction +system.cpu.op_class_0::SimdMisc 0 0.00% 60.28% # Class of committed instruction +system.cpu.op_class_0::SimdMult 0 0.00% 60.28% # Class of committed instruction +system.cpu.op_class_0::SimdMultAcc 0 0.00% 60.28% # Class of committed instruction +system.cpu.op_class_0::SimdShift 0 0.00% 60.28% # Class of committed instruction +system.cpu.op_class_0::SimdShiftAcc 0 0.00% 60.28% # Class of committed instruction +system.cpu.op_class_0::SimdSqrt 0 0.00% 60.28% # Class of committed instruction +system.cpu.op_class_0::SimdFloatAdd 0 0.00% 60.28% # Class of committed instruction +system.cpu.op_class_0::SimdFloatAlu 0 0.00% 60.28% # Class of committed instruction +system.cpu.op_class_0::SimdFloatCmp 0 0.00% 60.28% # Class of committed instruction +system.cpu.op_class_0::SimdFloatCvt 0 0.00% 60.28% # Class of committed instruction +system.cpu.op_class_0::SimdFloatDiv 0 0.00% 60.28% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMisc 0 0.00% 60.28% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMult 0 0.00% 60.28% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 60.28% # Class of committed instruction +system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 60.28% # Class of committed instruction +system.cpu.op_class_0::MemRead 46389 23.01% 83.29% # Class of committed instruction +system.cpu.op_class_0::MemWrite 33689 16.71% 100.00% # Class of committed instruction +system.cpu.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction +system.cpu.op_class_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction +system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.op_class_0::total 201609 # Class of committed instruction +system.cpu.tickCycles 299839 # Number of cycles that the object actually ticked +system.cpu.idleCycles 214954 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 257396500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 0 # number of replacements +system.cpu.dcache.tags.tagsinuse 237.251323 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 81600 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 296 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 275.675676 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 237.251323 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.057923 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.057923 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 296 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 7 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 25 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 264 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.072266 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 164496 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 164496 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 257396500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 48321 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 48321 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 33279 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 33279 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 81600 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 81600 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 81600 # number of overall hits +system.cpu.dcache.overall_hits::total 81600 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 91 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 91 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 409 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 409 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 500 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 500 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 500 # number of overall misses +system.cpu.dcache.overall_misses::total 500 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 8843000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 8843000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 32769500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 32769500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 41612500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 41612500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 41612500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 41612500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 48412 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 48412 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 33688 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 33688 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 82100 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 82100 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 82100 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 82100 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.001880 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.001880 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.012141 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.012141 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.006090 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.006090 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.006090 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.006090 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 97175.824176 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 97175.824176 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 80121.026895 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 80121.026895 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 83225 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 83225 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 83225 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 83225 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 6 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 6 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 198 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 198 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 204 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 204 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 204 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 204 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 85 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 85 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 211 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 211 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 296 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 296 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 296 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 296 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 8161000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 8161000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 16932000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 16932000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 25093000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 25093000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 25093000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 25093000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001756 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001756 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006263 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006263 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003605 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.003605 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003605 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.003605 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 96011.764706 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 96011.764706 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 80246.445498 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 80246.445498 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 84773.648649 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 84773.648649 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 84773.648649 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 84773.648649 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 257396500 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 44 # number of replacements +system.cpu.icache.tags.tagsinuse 581.971054 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 86953 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1105 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 78.690498 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 581.971054 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.284166 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.284166 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1061 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 257 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 746 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.518066 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 177221 # Number of tag accesses +system.cpu.icache.tags.data_accesses 177221 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 257396500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 86953 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 86953 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 86953 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 86953 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 86953 # number of overall hits +system.cpu.icache.overall_hits::total 86953 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1105 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1105 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1105 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1105 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1105 # number of overall misses +system.cpu.icache.overall_misses::total 1105 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 95598500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 95598500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 95598500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 95598500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 95598500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 95598500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 88058 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 88058 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 88058 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 88058 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 88058 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 88058 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.012549 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.012549 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.012549 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.012549 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.012549 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.012549 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 86514.479638 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 86514.479638 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 86514.479638 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 86514.479638 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 86514.479638 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 86514.479638 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.icache.writebacks::writebacks 44 # number of writebacks +system.cpu.icache.writebacks::total 44 # number of writebacks +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1105 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1105 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1105 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1105 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1105 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1105 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 94493500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 94493500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 94493500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 94493500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 94493500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 94493500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.012549 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.012549 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.012549 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.012549 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.012549 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.012549 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 85514.479638 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 85514.479638 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 85514.479638 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 85514.479638 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 85514.479638 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 85514.479638 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 257396500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.replacements 0 # number of replacements +system.cpu.l2cache.tags.tagsinuse 828.582477 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 45 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 1400 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.032143 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::cpu.inst 591.965303 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 236.617175 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.018065 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.007221 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.025286 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 1400 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 65 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 282 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1053 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.042725 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 12960 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 12960 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 257396500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.WritebackClean_hits::writebacks 44 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 44 # number of WritebackClean hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 1 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.data 1 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 1 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.data 1 # number of overall hits +system.cpu.l2cache.overall_hits::total 1 # number of overall hits +system.cpu.l2cache.ReadExReq_misses::cpu.data 211 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 211 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 1105 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 1105 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 84 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 84 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.inst 1105 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 295 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 1400 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 1105 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 295 # number of overall misses +system.cpu.l2cache.overall_misses::total 1400 # number of overall misses +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 16615500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 16615500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 92835500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 92835500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 8021000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 8021000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 92835500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 24636500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 117472000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 92835500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 24636500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 117472000 # number of overall miss cycles +system.cpu.l2cache.WritebackClean_accesses::writebacks 44 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 44 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 211 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 211 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1105 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 1105 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 85 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 85 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 1105 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 296 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 1401 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 1105 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 296 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 1401 # number of overall (read+write) accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 1 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 1 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.988235 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.988235 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.996622 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.999286 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.996622 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.999286 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78746.445498 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 78746.445498 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 84014.027149 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 84014.027149 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 95488.095238 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 95488.095238 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 84014.027149 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 83513.559322 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 83908.571429 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 84014.027149 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 83513.559322 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 83908.571429 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 211 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 211 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 1105 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 1105 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 84 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 84 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 1105 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 295 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 1400 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 1105 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 295 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 1400 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 14505500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 14505500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 81785500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 81785500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 7181000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 7181000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 81785500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 21686500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 103472000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 81785500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 21686500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 103472000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 1 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.988235 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.988235 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.996622 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.999286 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.996622 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.999286 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68746.445498 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68746.445498 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 74014.027149 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 74014.027149 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 85488.095238 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 85488.095238 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 74014.027149 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73513.559322 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 73908.571429 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 74014.027149 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73513.559322 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 73908.571429 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 1445 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 45 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 257396500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 1190 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 44 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 211 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 211 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 1105 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 85 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2254 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 592 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 2846 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 73536 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18944 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 92480 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 1401 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.000714 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.026717 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 1400 99.93% 99.93% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 1 0.07% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 1401 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 766500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 1657500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.6 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 444000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) +system.membus.snoop_filter.tot_requests 1400 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 257396500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 1189 # Transaction distribution +system.membus.trans_dist::ReadExReq 211 # Transaction distribution +system.membus.trans_dist::ReadExResp 211 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 1189 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 2800 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 2800 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 89600 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 89600 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoopTraffic 0 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 1400 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 1400 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 1400 # Request fanout histogram +system.membus.reqLayer0.occupancy 1611500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.6 # Layer utilization (%) +system.membus.respLayer1.occupancy 7433000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 2.9 # Layer utilization (%) + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-atomic/config.ini b/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-atomic/config.ini new file mode 100644 index 000000000..d8016ae2d --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-atomic/config.ini @@ -0,0 +1,211 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain +boot_osflags=a +cache_line_size=64 +clk_domain=system.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +exit_on_work_items=false +init_param=0 +kernel= +kernel_addr_check=true +load_addr_mask=1099511627775 +load_offset=0 +mem_mode=atomic +mem_ranges= +memories=system.physmem +mmap_using_noreserve=false +multi_thread=false +num_work_ids=16 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +readfile= +symbolfile= +thermal_components= +thermal_model=Null +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=AtomicSimpleCPU +children=dtb interrupts isa itb tracer workload +branchPred=Null +checker=Null +clk_domain=system.cpu_clk_domain +cpu_id=0 +default_p_state=UNDEFINED +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +eventq_index=0 +fastmem=false +function_trace=false +function_trace_start=0 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +profile=0 +progress_interval=0 +simpoint_start_insts= +simulate_data_stalls=false +simulate_inst_stalls=false +socket_id=0 +switched_out=false +system=system +tracer=system.cpu.tracer +width=1 +workload=system.cpu.workload +dcache_port=system.membus.slave[2] +icache_port=system.membus.slave[1] + +[system.cpu.dtb] +type=RiscvTLB +eventq_index=0 +size=64 + +[system.cpu.interrupts] +type=RiscvInterrupts +eventq_index=0 + +[system.cpu.isa] +type=RiscvISA +eventq_index=0 + +[system.cpu.itb] +type=RiscvTLB +eventq_index=0 +size=64 + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=LiveProcess +cmd=insttest +cwd= +drivers= +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable=/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64i/insttest +gid=100 +input=cin +kvmInSE=false +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=0 +system=system +uid=100 +useArchPT=false + +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000000 + +[system.membus] +type=CoherentXBar +children=snoop_filter +clk_domain=system.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +forward_latency=4 +frontend_latency=3 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +point_of_coherency=true +power_model=Null +response_latency=2 +snoop_filter=system.membus.snoop_filter +snoop_response_latency=4 +system=system +use_default_range=false +width=16 +master=system.physmem.port +slave=system.system_port system.cpu.icache_port system.cpu.dcache_port + +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + +[system.physmem] +type=SimpleMemory +bandwidth=73.000000 +clk_domain=system.clk_domain +conf_table_reported=true +default_p_state=UNDEFINED +eventq_index=0 +in_addr_map=true +kvm_map=true +latency=30000 +latency_var=0 +null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +range=0:134217727:0:0:0:0 +port=system.membus.master[0] + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-atomic/config.json b/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-atomic/config.json new file mode 100644 index 000000000..e72d8a19b --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-atomic/config.json @@ -0,0 +1,289 @@ +{ + "name": null, + "sim_quantum": 0, + "system": { + "kernel": "", + "mmap_using_noreserve": false, + "kernel_addr_check": true, + "membus": { + "point_of_coherency": true, + "system": "system", + "response_latency": 2, + "cxx_class": "CoherentXBar", + "forward_latency": 4, + "clk_domain": "system.clk_domain", + "width": 16, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "master": { + "peer": [ + "system.physmem.port" + ], + "role": "MASTER" + }, + "type": "CoherentXBar", + "frontend_latency": 3, + "slave": { + "peer": [ + "system.system_port", + "system.cpu.icache_port", + "system.cpu.dcache_port" + ], + "role": "SLAVE" + }, + "p_state_clk_gate_min": 1000, + "snoop_filter": { + "name": "snoop_filter", + "system": "system", + "max_capacity": 8388608, + "eventq_index": 0, + "cxx_class": "SnoopFilter", + "path": "system.membus.snoop_filter", + "type": "SnoopFilter", + "lookup_latency": 1 + }, + "power_model": null, + "path": "system.membus", + "snoop_response_latency": 4, + "name": "membus", + "p_state_clk_gate_bins": 20, + "use_default_range": false + }, + "symbolfile": "", + "readfile": "", + "thermal_model": null, + "cxx_class": "System", + "work_begin_cpu_id_exit": -1, + "load_offset": 0, + "work_begin_exit_count": 0, + "p_state_clk_gate_min": 1000, + "memories": [ + "system.physmem" + ], + "work_begin_ckpt_count": 0, + "clk_domain": { + "name": "clk_domain", + "clock": [ + 1000 + ], + "init_perf_level": 0, + "voltage_domain": "system.voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "mem_ranges": [], + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "dvfs_handler": { + "enable": false, + "name": "dvfs_handler", + "sys_clk_domain": "system.clk_domain", + "transition_latency": 100000000, + "eventq_index": 0, + "cxx_class": "DVFSHandler", + "domains": [], + "path": "system.dvfs_handler", + "type": "DVFSHandler" + }, + "work_end_exit_count": 0, + "type": "System", + "voltage_domain": { + "name": "voltage_domain", + "eventq_index": 0, + "voltage": [ + "1.0" + ], + "cxx_class": "VoltageDomain", + "path": "system.voltage_domain", + "type": "VoltageDomain" + }, + "cache_line_size": 64, + "boot_osflags": "a", + "system_port": { + "peer": "system.membus.slave[0]", + "role": "MASTER" + }, + "physmem": { + "range": "0:134217727:0:0:0:0", + "latency": 30000, + "name": "physmem", + "p_state_clk_gate_min": 1000, + "eventq_index": 0, + "p_state_clk_gate_bins": 20, + "default_p_state": "UNDEFINED", + "kvm_map": true, + "clk_domain": "system.clk_domain", + "power_model": null, + "latency_var": 0, + "bandwidth": "73.000000", + "conf_table_reported": true, + "cxx_class": "SimpleMemory", + "p_state_clk_gate_max": 1000000000000, + "path": "system.physmem", + "null": false, + "type": "SimpleMemory", + "port": { + "peer": "system.membus.master[0]", + "role": "SLAVE" + }, + "in_addr_map": true + }, + "power_model": null, + "work_cpus_ckpt_count": 0, + "thermal_components": [], + "path": "system", + "cpu_clk_domain": { + "name": "cpu_clk_domain", + "clock": [ + 500 + ], + "init_perf_level": 0, + "voltage_domain": "system.voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.cpu_clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "work_end_ckpt_count": 0, + "mem_mode": "atomic", + "name": "system", + "init_param": 0, + "p_state_clk_gate_bins": 20, + "load_addr_mask": 1099511627775, + "cpu": [ + { + "do_statistics_insts": true, + "numThreads": 1, + "itb": { + "name": "itb", + "eventq_index": 0, + "cxx_class": "RiscvISA::TLB", + "path": "system.cpu.itb", + "type": "RiscvTLB", + "size": 64 + }, + "simulate_data_stalls": false, + "function_trace": false, + "do_checkpoint_insts": true, + "cxx_class": "AtomicSimpleCPU", + "max_loads_all_threads": 0, + "system": "system", + "clk_domain": "system.cpu_clk_domain", + "function_trace_start": 0, + "cpu_id": 0, + "width": 1, + "checker": null, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "do_quiesce": true, + "type": "AtomicSimpleCPU", + "fastmem": false, + "profile": 0, + "icache_port": { + "peer": "system.membus.slave[1]", + "role": "MASTER" + }, + "p_state_clk_gate_bins": 20, + "p_state_clk_gate_min": 1000, + "interrupts": [ + { + "eventq_index": 0, + "path": "system.cpu.interrupts", + "type": "RiscvInterrupts", + "name": "interrupts", + "cxx_class": "RiscvISA::Interrupts" + } + ], + "dcache_port": { + "peer": "system.membus.slave[2]", + "role": "MASTER" + }, + "socket_id": 0, + "power_model": null, + "max_insts_all_threads": 0, + "path": "system.cpu", + "max_loads_any_thread": 0, + "switched_out": false, + "workload": [ + { + "uid": 100, + "pid": 100, + "kvmInSE": false, + "cxx_class": "LiveProcess", + "executable": "/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64i/insttest", + "drivers": [], + "system": "system", + "gid": 100, + "eventq_index": 0, + "env": [], + "input": "cin", + "ppid": 99, + "type": "LiveProcess", + "cwd": "", + "simpoint": 0, + "euid": 100, + "path": "system.cpu.workload", + "max_stack_size": 67108864, + "name": "workload", + "cmd": [ + "insttest" + ], + "errout": "cerr", + "useArchPT": false, + "egid": 100, + "output": "cout" + } + ], + "name": "cpu", + "dtb": { + "name": "dtb", + "eventq_index": 0, + "cxx_class": "RiscvISA::TLB", + "path": "system.cpu.dtb", + "type": "RiscvTLB", + "size": 64 + }, + "simpoint_start_insts": [], + "max_insts_any_thread": 0, + "simulate_inst_stalls": false, + "progress_interval": 0, + "branchPred": null, + "isa": [ + { + "eventq_index": 0, + "path": "system.cpu.isa", + "type": "RiscvISA", + "name": "isa", + "cxx_class": "RiscvISA::ISA" + } + ], + "tracer": { + "eventq_index": 0, + "path": "system.cpu.tracer", + "type": "ExeTracer", + "name": "tracer", + "cxx_class": "Trace::ExeTracer" + } + } + ], + "multi_thread": false, + "exit_on_work_items": false, + "work_item_id": -1, + "num_work_ids": 16 + }, + "time_sync_period": 100000000000, + "eventq_index": 0, + "time_sync_spin_threshold": 100000000, + "cxx_class": "Root", + "path": "root", + "time_sync_enable": false, + "type": "Root", + "full_system": false +}
\ No newline at end of file diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-atomic/simerr b/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-atomic/simerr new file mode 100755 index 000000000..fd133b12b --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-atomic/simerr @@ -0,0 +1,3 @@ +warn: Unknown operating system; assuming Linux. +warn: Sockets disabled, not accepting gdb connections +warn: ClockedObject: More than one power state change request encountered within the same simulation tick diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-atomic/simout b/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-atomic/simout new file mode 100755 index 000000000..97d9d4fd2 --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-atomic/simout @@ -0,0 +1,171 @@ +Redirecting stdout to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64i/simple-atomic/simout +Redirecting stderr to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64i/simple-atomic/simerr +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled Nov 30 2016 14:33:35 +gem5 started Nov 30 2016 16:18:43 +gem5 executing on zizzer, pid 34088 +command line: /z/powerjg/gem5-upstream/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64i/simple-atomic -re /z/powerjg/gem5-upstream/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64i/simple-atomic + +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. +lui: PASS +lui, negative: PASS +auipc: 0x157E0 +auipc: PASS +jal: PASS +jalr: PASS +beq, equal: PASS +beq, not equal: PASS +bne, equal: PASS +bne, not equal: PASS +blt, less: PASS +blt, equal: PASS +blt, greater: PASS +bge, less: PASS +bge, equal: PASS +bge, greater: PASS +bltu, greater: PASS +bltu, equal: PASS +bltu, less: PASS +bgeu, greater: PASS +bgeu, equal: PASS +bgeu, less: PASS +lb, positive: PASS +lb, negative: PASS +lh, positive: PASS +lh, negative: PASS +lw, positive: PASS +lw, negative: PASS +lbu: PASS +lhu: PASS +sb: PASS +sh: PASS +sw: PASS +addi: PASS +addi, overflow: PASS +slti, true: PASS +slti, false: PASS +sltiu, false: PASS +sltiu, true: PASS +xori (1): PASS +xori (0): PASS +ori (1): PASS +ori (A): PASS +andi (0): PASS +andi (1): PASS +slli, general: PASS +slli, erase: PASS +srli, general: PASS +srli, erase: PASS +srli, negative: PASS +srai, general: PASS +srai, erase: PASS +srai, negative: PASS +add: PASS +add, overflow: PASS +sub: PASS +sub, "overflow": PASS +sll, general: PASS +sll, erase: PASS +slt, true: PASS +slt, false: PASS +sltu, false: PASS +sltu, true: PASS +xor (1): PASS +xor (0): PASS +srl, general: PASS +srl, erase: PASS +srl, negative: PASS +sra, general: PASS +sra, erase: PASS +sra, negative: PASS +or (1): PASS +or (A): PASS +and (0): PASS +and (-1): PASS +Bytes written: 15 +open, write: PASS +access F_OK: PASS +access R_OK: PASS +access W_OK: PASS +access X_OK: PASS +stat: + st_dev = 2054 + st_ino = 55451710 + st_mode = 33188 + st_nlink = 1 + st_uid = 1004 + st_gid = 1007 + st_rdev = 0 + st_size = 0 + st_blksize = 0 + st_blocks = 1480540729 +fstat: + st_dev = 2054 + st_ino = 55451710 + st_mode = 33188 + st_nlink = 1 + st_uid = 1004 + st_gid = 1007 + st_rdev = 0 + st_size = 0 + st_blksize = 0 + st_blocks = 1480540730 +open, stat: PASS +Bytes read: 15 +String read: this is a test +open, read, unlink: PASS +times: + tms_utime = 0 + tms_stime = 0 + tms_cutime = 0 + tms_cstime = 0 +times: PASS +timeval: + tv_sec = 1000000000 + tv_usec = 102 +gettimeofday: PASS +Cycles: 210287 +rdcycle: PASS +Time: 1480540732 +rdtime: PASS +Instructions Retired: 215205 +rdinstret: PASS +lwu: PASS +ld: PASS +sd: PASS +addiw: PASS +addiw, overflow: PASS +addiw, truncate: PASS +slliw, general: PASS +slliw, erase: PASS +slliw, truncate: PASS +srliw, general: PASS +srliw, erase: PASS +srliw, negative: PASS +srliw, truncate: PASS +sraiw, general: PASS +sraiw, erase: PASS +sraiw, negative: PASS +sraiw, truncate: PASS +addw: PASS +addw, overflow: PASS +addw, truncate: PASS +subw: PASS +subw, "overflow": PASS +subw, truncate: PASS +sllw, general: PASS +sllw, erase: PASS +sllw, truncate: PASS +srlw, general: PASS +srlw, erase: PASS +srlw, negative: PASS +srlw, truncate: PASS +sraw, general: PASS +sraw, erase: PASS +sraw, negative: PASS +sraw, truncate: PASS +Exiting @ tick 133105500 because target called exit() diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-atomic/stats.txt b/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-atomic/stats.txt new file mode 100644 index 000000000..774499b09 --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-atomic/stats.txt @@ -0,0 +1,153 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.000133 # Number of seconds simulated +sim_ticks 133105500 # Number of ticks simulated +final_tick 133105500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 24056 # Simulator instruction rate (inst/s) +host_op_rate 24056 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 12036090 # Simulator tick rate (ticks/s) +host_mem_usage 234212 # Number of bytes of host memory used +host_seconds 11.06 # Real time elapsed on the host +sim_insts 266028 # Number of instructions simulated +sim_ops 266028 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 133105500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 1064848 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 412103 # Number of bytes read from this memory +system.physmem.bytes_read::total 1476951 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1064848 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1064848 # Number of instructions bytes read from this memory +system.physmem.bytes_written::cpu.data 270848 # Number of bytes written to this memory +system.physmem.bytes_written::total 270848 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 266212 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 62869 # Number of read requests responded to by this memory +system.physmem.num_reads::total 329081 # Number of read requests responded to by this memory +system.physmem.num_writes::cpu.data 43712 # Number of write requests responded to by this memory +system.physmem.num_writes::total 43712 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 8000030051 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3096062897 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 11096092949 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 8000030051 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 8000030051 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 2034837028 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2034837028 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 8000030051 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 5130899925 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 13130929977 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 133105500 # Cumulative time (in ticks) in various power states +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 183 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 133105500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 266212 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 266028 # Number of instructions committed +system.cpu.committedOps 266028 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 266027 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses +system.cpu.num_func_calls 19074 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 39822 # number of instructions that are conditional controls +system.cpu.num_int_insts 266027 # number of integer instructions +system.cpu.num_fp_insts 0 # number of float instructions +system.cpu.num_int_register_reads 351579 # number of times the integer registers were read +system.cpu.num_int_register_writes 182492 # number of times the integer registers were written +system.cpu.num_fp_register_reads 0 # number of times the floating registers were read +system.cpu.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu.num_mem_refs 106582 # number of memory refs +system.cpu.num_load_insts 62869 # Number of load instructions +system.cpu.num_store_insts 43713 # Number of store instructions +system.cpu.num_idle_cycles 0 # Number of idle cycles +system.cpu.num_busy_cycles 266212 # Number of busy cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.Branches 58896 # Number of branches fetched +system.cpu.op_class::No_OpClass 188 0.07% 0.07% # Class of executed instruction +system.cpu.op_class::IntAlu 158769 59.64% 59.71% # Class of executed instruction +system.cpu.op_class::IntMult 431 0.16% 59.87% # Class of executed instruction +system.cpu.op_class::IntDiv 242 0.09% 59.96% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 59.96% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 59.96% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 59.96% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 59.96% # Class of executed instruction +system.cpu.op_class::FloatMultAcc 0 0.00% 59.96% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 59.96% # Class of executed instruction +system.cpu.op_class::FloatMisc 0 0.00% 59.96% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 59.96% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 59.96% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 59.96% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 59.96% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 59.96% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 59.96% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 59.96% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 59.96% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 59.96% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 59.96% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 59.96% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 59.96% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 59.96% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 59.96% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 59.96% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 59.96% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 59.96% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 59.96% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 59.96% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 59.96% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 59.96% # Class of executed instruction +system.cpu.op_class::MemRead 62869 23.62% 83.58% # Class of executed instruction +system.cpu.op_class::MemWrite 43713 16.42% 100.00% # Class of executed instruction +system.cpu.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 266212 # Class of executed instruction +system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 133105500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadReq 329081 # Transaction distribution +system.membus.trans_dist::ReadResp 329081 # Transaction distribution +system.membus.trans_dist::WriteReq 43712 # Transaction distribution +system.membus.trans_dist::WriteResp 43712 # Transaction distribution +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 532424 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 213162 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 745586 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 1064848 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 682951 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 1747799 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoopTraffic 0 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 372793 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 372793 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 372793 # Request fanout histogram + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-timing-ruby/config.ini b/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-timing-ruby/config.ini new file mode 100644 index 000000000..f98935352 --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-timing-ruby/config.ini @@ -0,0 +1,1265 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000 +time_sync_spin_threshold=100000 + +[system] +type=System +children=clk_domain cpu dvfs_handler mem_ctrls ruby sys_port_proxy voltage_domain +boot_osflags=a +cache_line_size=64 +clk_domain=system.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +exit_on_work_items=false +init_param=0 +kernel= +kernel_addr_check=true +load_addr_mask=1099511627775 +load_offset=0 +mem_mode=timing +mem_ranges=0:268435455:0:0:0:0 +memories=system.mem_ctrls +mmap_using_noreserve=false +multi_thread=false +num_work_ids=16 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null +readfile= +symbolfile= +thermal_components= +thermal_model=Null +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.sys_port_proxy.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=TimingSimpleCPU +children=clk_domain dtb interrupts isa itb tracer workload +branchPred=Null +checker=Null +clk_domain=system.cpu.clk_domain +cpu_id=0 +default_p_state=UNDEFINED +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +eventq_index=0 +function_trace=false +function_trace_start=0 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null +profile=0 +progress_interval=0 +simpoint_start_insts= +socket_id=0 +switched_out=false +system=system +tracer=system.cpu.tracer +workload=system.cpu.workload +dcache_port=system.ruby.l1_cntrl0.sequencer.slave[1] +icache_port=system.ruby.l1_cntrl0.sequencer.slave[0] + +[system.cpu.clk_domain] +type=SrcClockDomain +clock=1 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu.dtb] +type=RiscvTLB +eventq_index=0 +size=64 + +[system.cpu.interrupts] +type=RiscvInterrupts +eventq_index=0 + +[system.cpu.isa] +type=RiscvISA +eventq_index=0 + +[system.cpu.itb] +type=RiscvTLB +eventq_index=0 +size=64 + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=LiveProcess +cmd=insttest +cwd= +drivers= +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable=/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64i/insttest +gid=100 +input=cin +kvmInSE=false +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=0 +system=system +uid=100 +useArchPT=false + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000 + +[system.mem_ctrls] +type=DRAMCtrl +IDD0=0.055000 +IDD02=0.000000 +IDD2N=0.032000 +IDD2N2=0.000000 +IDD2P0=0.000000 +IDD2P02=0.000000 +IDD2P1=0.032000 +IDD2P12=0.000000 +IDD3N=0.038000 +IDD3N2=0.000000 +IDD3P0=0.000000 +IDD3P02=0.000000 +IDD3P1=0.038000 +IDD3P12=0.000000 +IDD4R=0.157000 +IDD4R2=0.000000 +IDD4W=0.125000 +IDD4W2=0.000000 +IDD5=0.235000 +IDD52=0.000000 +IDD6=0.020000 +IDD62=0.000000 +VDD=1.500000 +VDD2=0.000000 +activation_limit=4 +addr_mapping=RoRaBaCoCh +bank_groups_per_rank=0 +banks_per_rank=8 +burst_length=8 +channels=1 +clk_domain=system.clk_domain +conf_table_reported=true +default_p_state=UNDEFINED +device_bus_width=8 +device_rowbuffer_size=1024 +device_size=536870912 +devices_per_rank=8 +dll=true +eventq_index=0 +in_addr_map=true +kvm_map=true +max_accesses_per_row=16 +mem_sched_policy=frfcfs +min_writes_per_switch=16 +null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +page_policy=open_adaptive +power_model=Null +range=0:268435455:5:19:0:0 +ranks_per_channel=2 +read_buffer_size=32 +static_backend_latency=10 +static_frontend_latency=10 +tBURST=5 +tCCD_L=0 +tCK=1 +tCL=14 +tCS=3 +tRAS=35 +tRCD=14 +tREFI=7800 +tRFC=260 +tRP=14 +tRRD=6 +tRRD_L=0 +tRTP=8 +tRTW=3 +tWR=15 +tWTR=8 +tXAW=30 +tXP=6 +tXPDLL=0 +tXS=270 +tXSDLL=0 +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 +port=system.ruby.dir_cntrl0.memory + +[system.ruby] +type=RubySystem +children=clk_domain dir_cntrl0 l1_cntrl0 memctrl_clk_domain network +access_backing_store=false +all_instructions=false +block_size_bytes=64 +clk_domain=system.ruby.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +hot_lines=false +memory_size_bits=48 +num_of_sequencers=1 +number_of_virtual_networks=5 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +phys_mem=Null +power_model=Null +randomization=false + +[system.ruby.clk_domain] +type=SrcClockDomain +clock=1 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.ruby.dir_cntrl0] +type=Directory_Controller +children=directory dmaRequestToDir dmaResponseFromDir forwardFromDir requestToDir responseFromDir responseFromMemory +buffer_size=0 +clk_domain=system.ruby.clk_domain +cluster_id=0 +default_p_state=UNDEFINED +directory=system.ruby.dir_cntrl0.directory +directory_latency=12 +dmaRequestToDir=system.ruby.dir_cntrl0.dmaRequestToDir +dmaResponseFromDir=system.ruby.dir_cntrl0.dmaResponseFromDir +eventq_index=0 +forwardFromDir=system.ruby.dir_cntrl0.forwardFromDir +number_of_TBEs=256 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null +recycle_latency=10 +requestToDir=system.ruby.dir_cntrl0.requestToDir +responseFromDir=system.ruby.dir_cntrl0.responseFromDir +responseFromMemory=system.ruby.dir_cntrl0.responseFromMemory +ruby_system=system.ruby +system=system +to_memory_controller_latency=1 +transitions_per_cycle=4 +version=0 +memory=system.mem_ctrls.port + +[system.ruby.dir_cntrl0.directory] +type=RubyDirectoryMemory +eventq_index=0 +numa_high_bit=5 +size=268435456 +version=0 + +[system.ruby.dir_cntrl0.dmaRequestToDir] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +slave=system.ruby.network.master[3] + +[system.ruby.dir_cntrl0.dmaResponseFromDir] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +master=system.ruby.network.slave[3] + +[system.ruby.dir_cntrl0.forwardFromDir] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=false +randomization=false +master=system.ruby.network.slave[4] + +[system.ruby.dir_cntrl0.requestToDir] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +slave=system.ruby.network.master[2] + +[system.ruby.dir_cntrl0.responseFromDir] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=false +randomization=false +master=system.ruby.network.slave[2] + +[system.ruby.dir_cntrl0.responseFromMemory] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=false +randomization=false + +[system.ruby.l1_cntrl0] +type=L1Cache_Controller +children=cacheMemory forwardToCache mandatoryQueue requestFromCache responseFromCache responseToCache sequencer +buffer_size=0 +cacheMemory=system.ruby.l1_cntrl0.cacheMemory +cache_response_latency=12 +clk_domain=system.cpu.clk_domain +cluster_id=0 +default_p_state=UNDEFINED +eventq_index=0 +forwardToCache=system.ruby.l1_cntrl0.forwardToCache +issue_latency=2 +mandatoryQueue=system.ruby.l1_cntrl0.mandatoryQueue +number_of_TBEs=256 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null +recycle_latency=10 +requestFromCache=system.ruby.l1_cntrl0.requestFromCache +responseFromCache=system.ruby.l1_cntrl0.responseFromCache +responseToCache=system.ruby.l1_cntrl0.responseToCache +ruby_system=system.ruby +send_evictions=false +sequencer=system.ruby.l1_cntrl0.sequencer +system=system +transitions_per_cycle=4 +version=0 + +[system.ruby.l1_cntrl0.cacheMemory] +type=RubyCache +children=replacement_policy +assoc=2 +block_size=0 +dataAccessLatency=1 +dataArrayBanks=1 +eventq_index=0 +is_icache=false +replacement_policy=system.ruby.l1_cntrl0.cacheMemory.replacement_policy +resourceStalls=false +ruby_system=system.ruby +size=256 +start_index_bit=6 +tagAccessLatency=1 +tagArrayBanks=1 + +[system.ruby.l1_cntrl0.cacheMemory.replacement_policy] +type=PseudoLRUReplacementPolicy +assoc=2 +block_size=64 +eventq_index=0 +size=256 + +[system.ruby.l1_cntrl0.forwardToCache] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +slave=system.ruby.network.master[0] + +[system.ruby.l1_cntrl0.mandatoryQueue] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=false +randomization=false + +[system.ruby.l1_cntrl0.requestFromCache] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +master=system.ruby.network.slave[0] + +[system.ruby.l1_cntrl0.responseFromCache] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +master=system.ruby.network.slave[1] + +[system.ruby.l1_cntrl0.responseToCache] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +slave=system.ruby.network.master[1] + +[system.ruby.l1_cntrl0.sequencer] +type=RubySequencer +clk_domain=system.cpu.clk_domain +coreid=99 +dcache=system.ruby.l1_cntrl0.cacheMemory +dcache_hit_latency=1 +deadlock_threshold=500000 +default_p_state=UNDEFINED +eventq_index=0 +garnet_standalone=false +icache=system.ruby.l1_cntrl0.cacheMemory +icache_hit_latency=1 +is_cpu_sequencer=true +max_outstanding_requests=16 +no_retry_on_stall=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null +ruby_system=system.ruby +support_data_reqs=true +support_inst_reqs=true +system=system +using_ruby_tester=false +version=0 +slave=system.cpu.icache_port system.cpu.dcache_port + +[system.ruby.memctrl_clk_domain] +type=DerivedClockDomain +clk_divider=3 +clk_domain=system.ruby.clk_domain +eventq_index=0 + +[system.ruby.network] +type=SimpleNetwork +children=ext_links0 ext_links1 int_link_buffers00 int_link_buffers01 int_link_buffers02 int_link_buffers03 int_link_buffers04 int_link_buffers05 int_link_buffers06 int_link_buffers07 int_link_buffers08 int_link_buffers09 int_link_buffers10 int_link_buffers11 int_link_buffers12 int_link_buffers13 int_link_buffers14 int_link_buffers15 int_link_buffers16 int_link_buffers17 int_link_buffers18 int_link_buffers19 int_link_buffers20 int_link_buffers21 int_link_buffers22 int_link_buffers23 int_link_buffers24 int_link_buffers25 int_link_buffers26 int_link_buffers27 int_link_buffers28 int_link_buffers29 int_link_buffers30 int_link_buffers31 int_link_buffers32 int_link_buffers33 int_link_buffers34 int_link_buffers35 int_link_buffers36 int_link_buffers37 int_link_buffers38 int_link_buffers39 int_links0 int_links1 int_links2 int_links3 routers0 routers1 routers2 +adaptive_routing=false +buffer_size=0 +clk_domain=system.ruby.clk_domain +control_msg_size=8 +default_p_state=UNDEFINED +endpoint_bandwidth=1000 +eventq_index=0 +ext_links=system.ruby.network.ext_links0 system.ruby.network.ext_links1 +int_link_buffers=system.ruby.network.int_link_buffers00 system.ruby.network.int_link_buffers01 system.ruby.network.int_link_buffers02 system.ruby.network.int_link_buffers03 system.ruby.network.int_link_buffers04 system.ruby.network.int_link_buffers05 system.ruby.network.int_link_buffers06 system.ruby.network.int_link_buffers07 system.ruby.network.int_link_buffers08 system.ruby.network.int_link_buffers09 system.ruby.network.int_link_buffers10 system.ruby.network.int_link_buffers11 system.ruby.network.int_link_buffers12 system.ruby.network.int_link_buffers13 system.ruby.network.int_link_buffers14 system.ruby.network.int_link_buffers15 system.ruby.network.int_link_buffers16 system.ruby.network.int_link_buffers17 system.ruby.network.int_link_buffers18 system.ruby.network.int_link_buffers19 system.ruby.network.int_link_buffers20 system.ruby.network.int_link_buffers21 system.ruby.network.int_link_buffers22 system.ruby.network.int_link_buffers23 system.ruby.network.int_link_buffers24 system.ruby.network.int_link_buffers25 system.ruby.network.int_link_buffers26 system.ruby.network.int_link_buffers27 system.ruby.network.int_link_buffers28 system.ruby.network.int_link_buffers29 system.ruby.network.int_link_buffers30 system.ruby.network.int_link_buffers31 system.ruby.network.int_link_buffers32 system.ruby.network.int_link_buffers33 system.ruby.network.int_link_buffers34 system.ruby.network.int_link_buffers35 system.ruby.network.int_link_buffers36 system.ruby.network.int_link_buffers37 system.ruby.network.int_link_buffers38 system.ruby.network.int_link_buffers39 +int_links=system.ruby.network.int_links0 system.ruby.network.int_links1 system.ruby.network.int_links2 system.ruby.network.int_links3 +netifs= +number_of_virtual_networks=5 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null +routers=system.ruby.network.routers0 system.ruby.network.routers1 system.ruby.network.routers2 +ruby_system=system.ruby +topology=Crossbar +master=system.ruby.l1_cntrl0.forwardToCache.slave system.ruby.l1_cntrl0.responseToCache.slave system.ruby.dir_cntrl0.requestToDir.slave system.ruby.dir_cntrl0.dmaRequestToDir.slave +slave=system.ruby.l1_cntrl0.requestFromCache.master system.ruby.l1_cntrl0.responseFromCache.master system.ruby.dir_cntrl0.responseFromDir.master system.ruby.dir_cntrl0.dmaResponseFromDir.master system.ruby.dir_cntrl0.forwardFromDir.master + +[system.ruby.network.ext_links0] +type=SimpleExtLink +bandwidth_factor=16 +eventq_index=0 +ext_node=system.ruby.l1_cntrl0 +int_node=system.ruby.network.routers0 +latency=1 +link_id=0 +weight=1 + +[system.ruby.network.ext_links1] +type=SimpleExtLink +bandwidth_factor=16 +eventq_index=0 +ext_node=system.ruby.dir_cntrl0 +int_node=system.ruby.network.routers1 +latency=1 +link_id=1 +weight=1 + +[system.ruby.network.int_link_buffers00] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers01] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers02] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers03] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers04] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers05] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers06] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers07] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers08] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers09] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers10] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers11] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers12] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers13] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers14] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers15] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers16] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers17] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers18] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers19] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers20] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers21] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers22] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers23] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers24] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers25] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers26] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers27] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers28] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers29] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers30] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers31] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers32] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers33] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers34] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers35] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers36] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers37] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers38] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers39] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_links0] +type=SimpleIntLink +bandwidth_factor=16 +dst_inport= +dst_node=system.ruby.network.routers2 +eventq_index=0 +latency=1 +link_id=2 +src_node=system.ruby.network.routers0 +src_outport= +weight=1 + +[system.ruby.network.int_links1] +type=SimpleIntLink +bandwidth_factor=16 +dst_inport= +dst_node=system.ruby.network.routers2 +eventq_index=0 +latency=1 +link_id=3 +src_node=system.ruby.network.routers1 +src_outport= +weight=1 + +[system.ruby.network.int_links2] +type=SimpleIntLink +bandwidth_factor=16 +dst_inport= +dst_node=system.ruby.network.routers0 +eventq_index=0 +latency=1 +link_id=4 +src_node=system.ruby.network.routers2 +src_outport= +weight=1 + +[system.ruby.network.int_links3] +type=SimpleIntLink +bandwidth_factor=16 +dst_inport= +dst_node=system.ruby.network.routers1 +eventq_index=0 +latency=1 +link_id=5 +src_node=system.ruby.network.routers2 +src_outport= +weight=1 + +[system.ruby.network.routers0] +type=Switch +children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14 +clk_domain=system.ruby.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +port_buffers=system.ruby.network.routers0.port_buffers00 system.ruby.network.routers0.port_buffers01 system.ruby.network.routers0.port_buffers02 system.ruby.network.routers0.port_buffers03 system.ruby.network.routers0.port_buffers04 system.ruby.network.routers0.port_buffers05 system.ruby.network.routers0.port_buffers06 system.ruby.network.routers0.port_buffers07 system.ruby.network.routers0.port_buffers08 system.ruby.network.routers0.port_buffers09 system.ruby.network.routers0.port_buffers10 system.ruby.network.routers0.port_buffers11 system.ruby.network.routers0.port_buffers12 system.ruby.network.routers0.port_buffers13 system.ruby.network.routers0.port_buffers14 +power_model=Null +router_id=0 +virt_nets=5 + +[system.ruby.network.routers0.port_buffers00] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers0.port_buffers01] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers0.port_buffers02] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers0.port_buffers03] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers0.port_buffers04] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers0.port_buffers05] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers0.port_buffers06] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers0.port_buffers07] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers0.port_buffers08] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers0.port_buffers09] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers0.port_buffers10] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers0.port_buffers11] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers0.port_buffers12] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers0.port_buffers13] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers0.port_buffers14] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers1] +type=Switch +children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14 +clk_domain=system.ruby.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +port_buffers=system.ruby.network.routers1.port_buffers00 system.ruby.network.routers1.port_buffers01 system.ruby.network.routers1.port_buffers02 system.ruby.network.routers1.port_buffers03 system.ruby.network.routers1.port_buffers04 system.ruby.network.routers1.port_buffers05 system.ruby.network.routers1.port_buffers06 system.ruby.network.routers1.port_buffers07 system.ruby.network.routers1.port_buffers08 system.ruby.network.routers1.port_buffers09 system.ruby.network.routers1.port_buffers10 system.ruby.network.routers1.port_buffers11 system.ruby.network.routers1.port_buffers12 system.ruby.network.routers1.port_buffers13 system.ruby.network.routers1.port_buffers14 +power_model=Null +router_id=1 +virt_nets=5 + +[system.ruby.network.routers1.port_buffers00] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers1.port_buffers01] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers1.port_buffers02] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers1.port_buffers03] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers1.port_buffers04] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers1.port_buffers05] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers1.port_buffers06] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers1.port_buffers07] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers1.port_buffers08] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers1.port_buffers09] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers1.port_buffers10] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers1.port_buffers11] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers1.port_buffers12] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers1.port_buffers13] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers1.port_buffers14] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2] +type=Switch +children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14 port_buffers15 port_buffers16 port_buffers17 port_buffers18 port_buffers19 +clk_domain=system.ruby.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +port_buffers=system.ruby.network.routers2.port_buffers00 system.ruby.network.routers2.port_buffers01 system.ruby.network.routers2.port_buffers02 system.ruby.network.routers2.port_buffers03 system.ruby.network.routers2.port_buffers04 system.ruby.network.routers2.port_buffers05 system.ruby.network.routers2.port_buffers06 system.ruby.network.routers2.port_buffers07 system.ruby.network.routers2.port_buffers08 system.ruby.network.routers2.port_buffers09 system.ruby.network.routers2.port_buffers10 system.ruby.network.routers2.port_buffers11 system.ruby.network.routers2.port_buffers12 system.ruby.network.routers2.port_buffers13 system.ruby.network.routers2.port_buffers14 system.ruby.network.routers2.port_buffers15 system.ruby.network.routers2.port_buffers16 system.ruby.network.routers2.port_buffers17 system.ruby.network.routers2.port_buffers18 system.ruby.network.routers2.port_buffers19 +power_model=Null +router_id=2 +virt_nets=5 + +[system.ruby.network.routers2.port_buffers00] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers01] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers02] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers03] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers04] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers05] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers06] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers07] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers08] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers09] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers10] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers11] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers12] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers13] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers14] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers15] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers16] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers17] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers18] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers19] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.sys_port_proxy] +type=RubyPortProxy +clk_domain=system.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +is_cpu_sequencer=true +no_retry_on_stall=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null +ruby_system=system.ruby +support_data_reqs=true +support_inst_reqs=true +system=system +using_ruby_tester=false +version=0 +slave=system.system_port + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-timing-ruby/config.json b/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-timing-ruby/config.json new file mode 100644 index 000000000..0c28bed70 --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-timing-ruby/config.json @@ -0,0 +1,1734 @@ +{ + "name": null, + "sim_quantum": 0, + "system": { + "kernel": "", + "mmap_using_noreserve": false, + "kernel_addr_check": true, + "symbolfile": "", + "readfile": "", + "thermal_model": null, + "cxx_class": "System", + "work_begin_cpu_id_exit": -1, + "load_offset": 0, + "work_begin_exit_count": 0, + "p_state_clk_gate_min": 1, + "memories": [ + "system.mem_ctrls" + ], + "work_begin_ckpt_count": 0, + "clk_domain": { + "name": "clk_domain", + "clock": [ + 1 + ], + "init_perf_level": 0, + "voltage_domain": "system.voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "mem_ranges": [ + "0:268435455:0:0:0:0" + ], + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000, + "dvfs_handler": { + "enable": false, + "name": "dvfs_handler", + "sys_clk_domain": "system.clk_domain", + "transition_latency": 100000, + "eventq_index": 0, + "cxx_class": "DVFSHandler", + "domains": [], + "path": "system.dvfs_handler", + "type": "DVFSHandler" + }, + "work_end_exit_count": 0, + "type": "System", + "voltage_domain": { + "name": "voltage_domain", + "eventq_index": 0, + "voltage": [ + "1.0" + ], + "cxx_class": "VoltageDomain", + "path": "system.voltage_domain", + "type": "VoltageDomain" + }, + "cache_line_size": 64, + "boot_osflags": "a", + "system_port": { + "peer": "system.sys_port_proxy.slave[0]", + "role": "MASTER" + }, + "sys_port_proxy": { + "system": "system", + "support_inst_reqs": true, + "slave": { + "peer": [ + "system.system_port" + ], + "role": "SLAVE" + }, + "name": "sys_port_proxy", + "p_state_clk_gate_min": 1, + "no_retry_on_stall": false, + "p_state_clk_gate_bins": 20, + "support_data_reqs": true, + "cxx_class": "RubyPortProxy", + "clk_domain": "system.clk_domain", + "power_model": null, + "is_cpu_sequencer": true, + "version": 0, + "eventq_index": 0, + "using_ruby_tester": false, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000, + "path": "system.sys_port_proxy", + "type": "RubyPortProxy", + "ruby_system": "system.ruby" + }, + "power_model": null, + "work_cpus_ckpt_count": 0, + "thermal_components": [], + "path": "system", + "ruby": { + "all_instructions": false, + "memory_size_bits": 48, + "cxx_class": "RubySystem", + "l1_cntrl0": { + "requestFromCache": { + "ordered": true, + "name": "requestFromCache", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "master": { + "peer": "system.ruby.network.slave[0]", + "role": "MASTER" + }, + "buffer_size": 0, + "path": "system.ruby.l1_cntrl0.requestFromCache", + "type": "MessageBuffer" + }, + "cxx_class": "L1Cache_Controller", + "forwardToCache": { + "ordered": true, + "name": "forwardToCache", + "cxx_class": "MessageBuffer", + "slave": { + "peer": "system.ruby.network.master[0]", + "role": "SLAVE" + }, + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.l1_cntrl0.forwardToCache", + "type": "MessageBuffer" + }, + "system": "system", + "cluster_id": 0, + "sequencer": { + "no_retry_on_stall": false, + "deadlock_threshold": 500000, + "using_ruby_tester": false, + "system": "system", + "dcache": "system.ruby.l1_cntrl0.cacheMemory", + "cxx_class": "Sequencer", + "garnet_standalone": false, + "clk_domain": "system.cpu.clk_domain", + "icache_hit_latency": 1, + "version": 0, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000, + "type": "RubySequencer", + "icache": "system.ruby.l1_cntrl0.cacheMemory", + "slave": { + "peer": [ + "system.cpu.icache_port", + "system.cpu.dcache_port" + ], + "role": "SLAVE" + }, + "p_state_clk_gate_min": 1, + "power_model": null, + "coreid": 99, + "path": "system.ruby.l1_cntrl0.sequencer", + "ruby_system": "system.ruby", + "support_inst_reqs": true, + "name": "sequencer", + "max_outstanding_requests": 16, + "p_state_clk_gate_bins": 20, + "dcache_hit_latency": 1, + "support_data_reqs": true, + "is_cpu_sequencer": true + }, + "type": "L1Cache_Controller", + "issue_latency": 2, + "recycle_latency": 10, + "clk_domain": "system.cpu.clk_domain", + "version": 0, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000, + "number_of_TBEs": 256, + "p_state_clk_gate_min": 1, + "responseToCache": { + "ordered": true, + "name": "responseToCache", + "cxx_class": "MessageBuffer", + "slave": { + "peer": "system.ruby.network.master[1]", + "role": "SLAVE" + }, + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.l1_cntrl0.responseToCache", + "type": "MessageBuffer" + }, + "transitions_per_cycle": 4, + "responseFromCache": { + "ordered": true, + "name": "responseFromCache", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "master": { + "peer": "system.ruby.network.slave[1]", + "role": "MASTER" + }, + "buffer_size": 0, + "path": "system.ruby.l1_cntrl0.responseFromCache", + "type": "MessageBuffer" + }, + "power_model": null, + "cache_response_latency": 12, + "buffer_size": 0, + "send_evictions": false, + "cacheMemory": { + "size": 256, + "resourceStalls": false, + "is_icache": false, + "name": "cacheMemory", + "eventq_index": 0, + "dataAccessLatency": 1, + "tagArrayBanks": 1, + "tagAccessLatency": 1, + "replacement_policy": { + "name": "replacement_policy", + "eventq_index": 0, + "assoc": 2, + "cxx_class": "PseudoLRUPolicy", + "path": "system.ruby.l1_cntrl0.cacheMemory.replacement_policy", + "block_size": 64, + "type": "PseudoLRUReplacementPolicy", + "size": 256 + }, + "assoc": 2, + "start_index_bit": 6, + "cxx_class": "CacheMemory", + "path": "system.ruby.l1_cntrl0.cacheMemory", + "block_size": 0, + "type": "RubyCache", + "dataArrayBanks": 1, + "ruby_system": "system.ruby" + }, + "ruby_system": "system.ruby", + "name": "l1_cntrl0", + "p_state_clk_gate_bins": 20, + "mandatoryQueue": { + "ordered": false, + "name": "mandatoryQueue", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.l1_cntrl0.mandatoryQueue", + "type": "MessageBuffer" + }, + "path": "system.ruby.l1_cntrl0" + }, + "network": { + "int_link_buffers": [ + { + "ordered": true, + "name": "int_link_buffers00", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers00", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers01", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers01", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers02", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers02", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers03", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers03", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers04", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers04", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers05", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers05", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers06", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers06", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers07", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers07", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers08", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers08", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers09", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers09", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers10", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers10", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers11", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers11", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers12", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers12", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers13", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers13", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers14", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers14", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers15", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers15", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers16", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers16", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers17", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers17", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers18", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers18", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers19", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers19", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers20", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers20", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers21", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers21", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers22", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers22", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers23", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers23", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers24", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers24", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers25", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers25", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers26", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers26", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers27", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers27", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers28", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers28", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers29", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers29", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers30", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers30", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers31", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers31", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers32", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers32", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers33", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers33", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers34", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers34", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers35", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers35", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers36", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers36", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers37", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers37", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers38", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers38", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers39", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers39", + "type": "MessageBuffer" + } + ], + "cxx_class": "SimpleNetwork", + "clk_domain": "system.ruby.clk_domain", + "adaptive_routing": false, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000, + "master": { + "peer": [ + "system.ruby.l1_cntrl0.forwardToCache.slave", + "system.ruby.l1_cntrl0.responseToCache.slave", + "system.ruby.dir_cntrl0.requestToDir.slave", + "system.ruby.dir_cntrl0.dmaRequestToDir.slave" + ], + "role": "MASTER" + }, + "topology": "Crossbar", + "type": "SimpleNetwork", + "slave": { + "peer": [ + "system.ruby.l1_cntrl0.requestFromCache.master", + "system.ruby.l1_cntrl0.responseFromCache.master", + "system.ruby.dir_cntrl0.responseFromDir.master", + "system.ruby.dir_cntrl0.dmaResponseFromDir.master", + "system.ruby.dir_cntrl0.forwardFromDir.master" + ], + "role": "SLAVE" + }, + "p_state_clk_gate_min": 1, + "int_links": [ + { + "latency": 1, + "name": "int_links0", + "weight": 1, + "src_node": "system.ruby.network.routers0", + "dst_inport": "", + "link_id": 2, + "dst_node": "system.ruby.network.routers2", + "eventq_index": 0, + "src_outport": "", + "cxx_class": "SimpleIntLink", + "path": "system.ruby.network.int_links0", + "type": "SimpleIntLink", + "bandwidth_factor": 16 + }, + { + "latency": 1, + "name": "int_links1", + "weight": 1, + "src_node": "system.ruby.network.routers1", + "dst_inport": "", + "link_id": 3, + "dst_node": "system.ruby.network.routers2", + "eventq_index": 0, + "src_outport": "", + "cxx_class": "SimpleIntLink", + "path": "system.ruby.network.int_links1", + "type": "SimpleIntLink", + "bandwidth_factor": 16 + }, + { + "latency": 1, + "name": "int_links2", + "weight": 1, + "src_node": "system.ruby.network.routers2", + "dst_inport": "", + "link_id": 4, + "dst_node": "system.ruby.network.routers0", + "eventq_index": 0, + "src_outport": "", + "cxx_class": "SimpleIntLink", + "path": "system.ruby.network.int_links2", + "type": "SimpleIntLink", + "bandwidth_factor": 16 + }, + { + "latency": 1, + "name": "int_links3", + "weight": 1, + "src_node": "system.ruby.network.routers2", + "dst_inport": "", + "link_id": 5, + "dst_node": "system.ruby.network.routers1", + "eventq_index": 0, + "src_outport": "", + "cxx_class": "SimpleIntLink", + "path": "system.ruby.network.int_links3", + "type": "SimpleIntLink", + "bandwidth_factor": 16 + } + ], + "routers": [ + { + "router_id": 0, + "latency": 1, + "name": "routers0", + "p_state_clk_gate_min": 1, + "virt_nets": 5, + "p_state_clk_gate_bins": 20, + "cxx_class": "Switch", + "clk_domain": "system.ruby.clk_domain", + "power_model": null, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000, + "path": "system.ruby.network.routers0", + "type": "Switch", + "port_buffers": [ + { + "ordered": true, + "name": "port_buffers00", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers0.port_buffers00", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers01", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers0.port_buffers01", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers02", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers0.port_buffers02", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers03", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers0.port_buffers03", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers04", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers0.port_buffers04", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers05", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers0.port_buffers05", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers06", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers0.port_buffers06", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers07", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers0.port_buffers07", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers08", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers0.port_buffers08", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers09", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers0.port_buffers09", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers10", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers0.port_buffers10", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers11", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers0.port_buffers11", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers12", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers0.port_buffers12", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers13", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers0.port_buffers13", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers14", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers0.port_buffers14", + "type": "MessageBuffer" + } + ] + }, + { + "router_id": 1, + "latency": 1, + "name": "routers1", + "p_state_clk_gate_min": 1, + "virt_nets": 5, + "p_state_clk_gate_bins": 20, + "cxx_class": "Switch", + "clk_domain": "system.ruby.clk_domain", + "power_model": null, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000, + "path": "system.ruby.network.routers1", + "type": "Switch", + "port_buffers": [ + { + "ordered": true, + "name": "port_buffers00", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers1.port_buffers00", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers01", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers1.port_buffers01", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers02", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers1.port_buffers02", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers03", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers1.port_buffers03", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers04", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers1.port_buffers04", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers05", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers1.port_buffers05", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers06", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers1.port_buffers06", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers07", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers1.port_buffers07", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers08", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers1.port_buffers08", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers09", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers1.port_buffers09", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers10", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers1.port_buffers10", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers11", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers1.port_buffers11", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers12", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers1.port_buffers12", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers13", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers1.port_buffers13", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers14", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers1.port_buffers14", + "type": "MessageBuffer" + } + ] + }, + { + "router_id": 2, + "latency": 1, + "name": "routers2", + "p_state_clk_gate_min": 1, + "virt_nets": 5, + "p_state_clk_gate_bins": 20, + "cxx_class": "Switch", + "clk_domain": "system.ruby.clk_domain", + "power_model": null, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000, + "path": "system.ruby.network.routers2", + "type": "Switch", + "port_buffers": [ + { + "ordered": true, + "name": "port_buffers00", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers2.port_buffers00", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers01", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers2.port_buffers01", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers02", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers2.port_buffers02", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers03", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers2.port_buffers03", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers04", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers2.port_buffers04", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers05", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers2.port_buffers05", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers06", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers2.port_buffers06", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers07", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers2.port_buffers07", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers08", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers2.port_buffers08", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers09", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers2.port_buffers09", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers10", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers2.port_buffers10", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers11", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers2.port_buffers11", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers12", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers2.port_buffers12", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers13", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers2.port_buffers13", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers14", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers2.port_buffers14", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers15", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers2.port_buffers15", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers16", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers2.port_buffers16", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers17", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers2.port_buffers17", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers18", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers2.port_buffers18", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers19", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers2.port_buffers19", + "type": "MessageBuffer" + } + ] + } + ], + "power_model": null, + "netifs": [], + "control_msg_size": 8, + "buffer_size": 0, + "endpoint_bandwidth": 1000, + "ruby_system": "system.ruby", + "name": "network", + "p_state_clk_gate_bins": 20, + "ext_links": [ + { + "latency": 1, + "name": "ext_links0", + "weight": 1, + "ext_node": "system.ruby.l1_cntrl0", + "link_id": 0, + "eventq_index": 0, + "cxx_class": "SimpleExtLink", + "path": "system.ruby.network.ext_links0", + "int_node": "system.ruby.network.routers0", + "type": "SimpleExtLink", + "bandwidth_factor": 16 + }, + { + "latency": 1, + "name": "ext_links1", + "weight": 1, + "ext_node": "system.ruby.dir_cntrl0", + "link_id": 1, + "eventq_index": 0, + "cxx_class": "SimpleExtLink", + "path": "system.ruby.network.ext_links1", + "int_node": "system.ruby.network.routers1", + "type": "SimpleExtLink", + "bandwidth_factor": 16 + } + ], + "number_of_virtual_networks": 5, + "path": "system.ruby.network" + }, + "clk_domain": { + "name": "clk_domain", + "clock": [ + 1 + ], + "init_perf_level": 0, + "voltage_domain": "system.voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.ruby.clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "randomization": false, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000, + "phys_mem": null, + "type": "RubySystem", + "p_state_clk_gate_min": 1, + "hot_lines": false, + "power_model": null, + "path": "system.ruby", + "memctrl_clk_domain": { + "name": "memctrl_clk_domain", + "clk_domain": "system.ruby.clk_domain", + "eventq_index": 0, + "cxx_class": "DerivedClockDomain", + "path": "system.ruby.memctrl_clk_domain", + "type": "DerivedClockDomain", + "clk_divider": 3 + }, + "name": "ruby", + "p_state_clk_gate_bins": 20, + "block_size_bytes": 64, + "access_backing_store": false, + "number_of_virtual_networks": 5, + "num_of_sequencers": 1, + "dir_cntrl0": { + "system": "system", + "cluster_id": 0, + "responseFromMemory": { + "ordered": false, + "name": "responseFromMemory", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.dir_cntrl0.responseFromMemory", + "type": "MessageBuffer" + }, + "cxx_class": "Directory_Controller", + "forwardFromDir": { + "ordered": false, + "name": "forwardFromDir", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "master": { + "peer": "system.ruby.network.slave[4]", + "role": "MASTER" + }, + "buffer_size": 0, + "path": "system.ruby.dir_cntrl0.forwardFromDir", + "type": "MessageBuffer" + }, + "dmaRequestToDir": { + "ordered": true, + "name": "dmaRequestToDir", + "cxx_class": "MessageBuffer", + "slave": { + "peer": "system.ruby.network.master[3]", + "role": "SLAVE" + }, + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.dir_cntrl0.dmaRequestToDir", + "type": "MessageBuffer" + }, + "type": "Directory_Controller", + "recycle_latency": 10, + "clk_domain": "system.ruby.clk_domain", + "version": 0, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000, + "directory_latency": 12, + "number_of_TBEs": 256, + "to_memory_controller_latency": 1, + "p_state_clk_gate_min": 1, + "responseFromDir": { + "ordered": false, + "name": "responseFromDir", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "master": { + "peer": "system.ruby.network.slave[2]", + "role": "MASTER" + }, + "buffer_size": 0, + "path": "system.ruby.dir_cntrl0.responseFromDir", + "type": "MessageBuffer" + }, + "transitions_per_cycle": 4, + "memory": { + "peer": "system.mem_ctrls.port", + "role": "MASTER" + }, + "power_model": null, + "buffer_size": 0, + "ruby_system": "system.ruby", + "requestToDir": { + "ordered": true, + "name": "requestToDir", + "cxx_class": "MessageBuffer", + "slave": { + "peer": "system.ruby.network.master[2]", + "role": "SLAVE" + }, + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.dir_cntrl0.requestToDir", + "type": "MessageBuffer" + }, + "dmaResponseFromDir": { + "ordered": true, + "name": "dmaResponseFromDir", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "master": { + "peer": "system.ruby.network.slave[3]", + "role": "MASTER" + }, + "buffer_size": 0, + "path": "system.ruby.dir_cntrl0.dmaResponseFromDir", + "type": "MessageBuffer" + }, + "name": "dir_cntrl0", + "p_state_clk_gate_bins": 20, + "directory": { + "name": "directory", + "version": 0, + "eventq_index": 0, + "cxx_class": "DirectoryMemory", + "path": "system.ruby.dir_cntrl0.directory", + "type": "RubyDirectoryMemory", + "numa_high_bit": 5, + "size": 268435456 + }, + "path": "system.ruby.dir_cntrl0" + } + }, + "work_end_ckpt_count": 0, + "mem_mode": "timing", + "name": "system", + "init_param": 0, + "p_state_clk_gate_bins": 20, + "load_addr_mask": 1099511627775, + "cpu": { + "do_statistics_insts": true, + "numThreads": 1, + "itb": { + "name": "itb", + "eventq_index": 0, + "cxx_class": "RiscvISA::TLB", + "path": "system.cpu.itb", + "type": "RiscvTLB", + "size": 64 + }, + "system": "system", + "function_trace": false, + "do_checkpoint_insts": true, + "cxx_class": "TimingSimpleCPU", + "max_loads_all_threads": 0, + "clk_domain": { + "name": "clk_domain", + "clock": [ + 1 + ], + "init_perf_level": 0, + "voltage_domain": "system.voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.cpu.clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "function_trace_start": 0, + "cpu_id": 0, + "checker": null, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000, + "do_quiesce": true, + "type": "TimingSimpleCPU", + "profile": 0, + "icache_port": { + "peer": "system.ruby.l1_cntrl0.sequencer.slave[0]", + "role": "MASTER" + }, + "p_state_clk_gate_bins": 20, + "p_state_clk_gate_min": 1, + "interrupts": [ + { + "eventq_index": 0, + "path": "system.cpu.interrupts", + "type": "RiscvInterrupts", + "name": "interrupts", + "cxx_class": "RiscvISA::Interrupts" + } + ], + "dcache_port": { + "peer": "system.ruby.l1_cntrl0.sequencer.slave[1]", + "role": "MASTER" + }, + "socket_id": 0, + "power_model": null, + "max_insts_all_threads": 0, + "path": "system.cpu", + "max_loads_any_thread": 0, + "switched_out": false, + "workload": [ + { + "uid": 100, + "pid": 100, + "kvmInSE": false, + "cxx_class": "LiveProcess", + "executable": "/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64i/insttest", + "drivers": [], + "system": "system", + "gid": 100, + "eventq_index": 0, + "env": [], + "input": "cin", + "ppid": 99, + "type": "LiveProcess", + "cwd": "", + "simpoint": 0, + "euid": 100, + "path": "system.cpu.workload", + "max_stack_size": 67108864, + "name": "workload", + "cmd": [ + "insttest" + ], + "errout": "cerr", + "useArchPT": false, + "egid": 100, + "output": "cout" + } + ], + "name": "cpu", + "dtb": { + "name": "dtb", + "eventq_index": 0, + "cxx_class": "RiscvISA::TLB", + "path": "system.cpu.dtb", + "type": "RiscvTLB", + "size": 64 + }, + "simpoint_start_insts": [], + "max_insts_any_thread": 0, + "progress_interval": 0, + "branchPred": null, + "isa": [ + { + "eventq_index": 0, + "path": "system.cpu.isa", + "type": "RiscvISA", + "name": "isa", + "cxx_class": "RiscvISA::ISA" + } + ], + "tracer": { + "eventq_index": 0, + "path": "system.cpu.tracer", + "type": "ExeTracer", + "name": "tracer", + "cxx_class": "Trace::ExeTracer" + } + }, + "multi_thread": false, + "mem_ctrls": [ + { + "static_frontend_latency": 10, + "tRFC": 260, + "activation_limit": 4, + "in_addr_map": true, + "IDD3N2": "0.0", + "tWTR": 8, + "IDD52": "0.0", + "clk_domain": "system.clk_domain", + "channels": 1, + "write_buffer_size": 64, + "device_bus_width": 8, + "VDD": "1.5", + "write_high_thresh_perc": 85, + "cxx_class": "DRAMCtrl", + "bank_groups_per_rank": 0, + "IDD2N2": "0.0", + "port": { + "peer": "system.ruby.dir_cntrl0.memory", + "role": "SLAVE" + }, + "tCCD_L": 0, + "IDD2N": "0.032", + "p_state_clk_gate_min": 1, + "null": false, + "IDD2P1": "0.032", + "eventq_index": 0, + "tRRD": 6, + "tRTW": 3, + "IDD4R": "0.157", + "burst_length": 8, + "tRTP": 8, + "IDD4W": "0.125", + "tWR": 15, + "banks_per_rank": 8, + "devices_per_rank": 8, + "IDD2P02": "0.0", + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000, + "IDD6": "0.02", + "IDD5": "0.235", + "tRCD": 14, + "type": "DRAMCtrl", + "IDD3P02": "0.0", + "tRRD_L": 0, + "IDD0": "0.055", + "IDD62": "0.0", + "min_writes_per_switch": 16, + "mem_sched_policy": "frfcfs", + "IDD02": "0.0", + "IDD2P0": "0.0", + "ranks_per_channel": 2, + "page_policy": "open_adaptive", + "IDD4W2": "0.0", + "tCS": 3, + "power_model": null, + "tCL": 14, + "read_buffer_size": 32, + "conf_table_reported": true, + "tCK": 1, + "tRAS": 35, + "tRP": 14, + "tBURST": 5, + "path": "system.mem_ctrls", + "tXP": 6, + "tXS": 270, + "addr_mapping": "RoRaBaCoCh", + "IDD3P0": "0.0", + "IDD3P1": "0.038", + "IDD3N": "0.038", + "name": "mem_ctrls", + "tXSDLL": 0, + "device_size": 536870912, + "kvm_map": true, + "dll": true, + "tXAW": 30, + "write_low_thresh_perc": 50, + "range": "0:268435455:5:19:0:0", + "VDD2": "0.0", + "IDD2P12": "0.0", + "p_state_clk_gate_bins": 20, + "tXPDLL": 0, + "IDD4R2": "0.0", + "device_rowbuffer_size": 1024, + "static_backend_latency": 10, + "max_accesses_per_row": 16, + "IDD3P12": "0.0", + "tREFI": 7800 + } + ], + "exit_on_work_items": false, + "work_item_id": -1, + "num_work_ids": 16 + }, + "time_sync_period": 100000000, + "eventq_index": 0, + "time_sync_spin_threshold": 100000, + "cxx_class": "Root", + "path": "root", + "time_sync_enable": false, + "type": "Root", + "full_system": false +}
\ No newline at end of file diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-timing-ruby/simerr b/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-timing-ruby/simerr new file mode 100755 index 000000000..63b14556f --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-timing-ruby/simerr @@ -0,0 +1,11 @@ +warn: rounding error > tolerance + 1.250000 rounded to 1 +warn: rounding error > tolerance + 1.250000 rounded to 1 +warn: rounding error > tolerance + 1.250000 rounded to 1 +warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes) +warn: Unknown operating system; assuming Linux. +warn: Sockets disabled, not accepting gdb connections +warn: ClockedObject: More than one power state change request encountered within the same simulation tick +warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files! diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-timing-ruby/simout b/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-timing-ruby/simout new file mode 100755 index 000000000..ea970ac1c --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-timing-ruby/simout @@ -0,0 +1,171 @@ +Redirecting stdout to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64i/simple-timing-ruby/simout +Redirecting stderr to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64i/simple-timing-ruby/simerr +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled Nov 30 2016 14:33:35 +gem5 started Nov 30 2016 16:18:44 +gem5 executing on zizzer, pid 34093 +command line: /z/powerjg/gem5-upstream/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64i/simple-timing-ruby -re /z/powerjg/gem5-upstream/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64i/simple-timing-ruby + +Global frequency set at 1000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. +lui: PASS +lui, negative: PASS +auipc: 0x157E0 +auipc: PASS +jal: PASS +jalr: PASS +beq, equal: PASS +beq, not equal: PASS +bne, equal: PASS +bne, not equal: PASS +blt, less: PASS +blt, equal: PASS +blt, greater: PASS +bge, less: PASS +bge, equal: PASS +bge, greater: PASS +bltu, greater: PASS +bltu, equal: PASS +bltu, less: PASS +bgeu, greater: PASS +bgeu, equal: PASS +bgeu, less: PASS +lb, positive: PASS +lb, negative: PASS +lh, positive: PASS +lh, negative: PASS +lw, positive: PASS +lw, negative: PASS +lbu: PASS +lhu: PASS +sb: PASS +sh: PASS +sw: PASS +addi: PASS +addi, overflow: PASS +slti, true: PASS +slti, false: PASS +sltiu, false: PASS +sltiu, true: PASS +xori (1): PASS +xori (0): PASS +ori (1): PASS +ori (A): PASS +andi (0): PASS +andi (1): PASS +slli, general: PASS +slli, erase: PASS +srli, general: PASS +srli, erase: PASS +srli, negative: PASS +srai, general: PASS +srai, erase: PASS +srai, negative: PASS +add: PASS +add, overflow: PASS +sub: PASS +sub, "overflow": PASS +sll, general: PASS +sll, erase: PASS +slt, true: PASS +slt, false: PASS +sltu, false: PASS +sltu, true: PASS +xor (1): PASS +xor (0): PASS +srl, general: PASS +srl, erase: PASS +srl, negative: PASS +sra, general: PASS +sra, erase: PASS +sra, negative: PASS +or (1): PASS +or (A): PASS +and (0): PASS +and (-1): PASS +Bytes written: 15 +open, write: PASS +access F_OK: PASS +access R_OK: PASS +access W_OK: PASS +access X_OK: PASS +stat: + st_dev = 2054 + st_ino = 55451710 + st_mode = 33188 + st_nlink = 1 + st_uid = 1004 + st_gid = 1007 + st_rdev = 0 + st_size = 0 + st_blksize = 0 + st_blocks = 1480540733 +fstat: + st_dev = 2054 + st_ino = 55451710 + st_mode = 33188 + st_nlink = 1 + st_uid = 1004 + st_gid = 1007 + st_rdev = 0 + st_size = 0 + st_blksize = 0 + st_blocks = 1480540733 +open, stat: PASS +Bytes read: 15 +String read: this is a test +open, read, unlink: PASS +times: + tms_utime = 0 + tms_stime = 0 + tms_cutime = 0 + tms_cstime = 0 +times: PASS +timeval: + tv_sec = 1000000000 + tv_usec = 3935 +gettimeofday: PASS +Cycles: 4032706 +rdcycle: PASS +Time: 1480540736 +rdtime: PASS +Instructions Retired: 215243 +rdinstret: PASS +lwu: PASS +ld: PASS +sd: PASS +addiw: PASS +addiw, overflow: PASS +addiw, truncate: PASS +slliw, general: PASS +slliw, erase: PASS +slliw, truncate: PASS +srliw, general: PASS +srliw, erase: PASS +srliw, negative: PASS +srliw, truncate: PASS +sraiw, general: PASS +sraiw, erase: PASS +sraiw, negative: PASS +sraiw, truncate: PASS +addw: PASS +addw, overflow: PASS +addw, truncate: PASS +subw: PASS +subw, "overflow": PASS +subw, truncate: PASS +sllw, general: PASS +sllw, erase: PASS +sllw, truncate: PASS +srlw, general: PASS +srlw, erase: PASS +srlw, negative: PASS +srlw, truncate: PASS +sraw, general: PASS +sraw, erase: PASS +sraw, negative: PASS +sraw, truncate: PASS +Exiting @ tick 5246466 because target called exit() diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-timing-ruby/stats.txt b/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-timing-ruby/stats.txt new file mode 100644 index 000000000..70b5b9855 --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-timing-ruby/stats.txt @@ -0,0 +1,644 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.005246 # Number of seconds simulated +sim_ticks 5246466 # Number of ticks simulated +final_tick 5246466 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000 # Frequency of simulated ticks +host_inst_rate 18477 # Simulator instruction rate (inst/s) +host_op_rate 18477 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 364337 # Simulator tick rate (ticks/s) +host_mem_usage 412052 # Number of bytes of host memory used +host_seconds 14.40 # Real time elapsed on the host +sim_insts 266066 # Number of instructions simulated +sim_ops 266066 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1 # Clock period in ticks +system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 5246466 # Cumulative time (in ticks) in various power states +system.mem_ctrls.bytes_read::ruby.dir_cntrl0 5073344 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::total 5073344 # Number of bytes read from this memory +system.mem_ctrls.bytes_written::ruby.dir_cntrl0 5073088 # Number of bytes written to this memory +system.mem_ctrls.bytes_written::total 5073088 # Number of bytes written to this memory +system.mem_ctrls.num_reads::ruby.dir_cntrl0 79271 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::total 79271 # Number of read requests responded to by this memory +system.mem_ctrls.num_writes::ruby.dir_cntrl0 79267 # Number of write requests responded to by this memory +system.mem_ctrls.num_writes::total 79267 # Number of write requests responded to by this memory +system.mem_ctrls.bw_read::ruby.dir_cntrl0 967002169 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::total 967002169 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::ruby.dir_cntrl0 966953374 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::total 966953374 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_total::ruby.dir_cntrl0 1933955543 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::total 1933955543 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.readReqs 79271 # Number of read requests accepted +system.mem_ctrls.writeReqs 79267 # Number of write requests accepted +system.mem_ctrls.readBursts 79271 # Number of DRAM read bursts, including those serviced by the write queue +system.mem_ctrls.writeBursts 79267 # Number of DRAM write bursts, including those merged in the write queue +system.mem_ctrls.bytesReadDRAM 2666176 # Total number of bytes read from DRAM +system.mem_ctrls.bytesReadWrQ 2407168 # Total number of bytes read from write queue +system.mem_ctrls.bytesWritten 2784128 # Total number of bytes written to DRAM +system.mem_ctrls.bytesReadSys 5073344 # Total read bytes from the system interface side +system.mem_ctrls.bytesWrittenSys 5073088 # Total written bytes from the system interface side +system.mem_ctrls.servicedByWrQ 37612 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrls.mergedWrBursts 35741 # Number of DRAM write bursts merged with an existing one +system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.mem_ctrls.perBankRdBursts::0 4161 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::1 6493 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::2 322 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::3 11183 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::4 1470 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::5 254 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::6 44 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::7 830 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::8 271 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::9 850 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::10 2251 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::11 11315 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::12 562 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::13 405 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::14 342 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::15 906 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::0 4421 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::1 6791 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::2 332 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::3 11984 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::4 1476 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::5 255 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::6 44 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::7 877 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::8 282 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::9 852 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::10 2350 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::11 11612 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::12 563 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::13 405 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::14 350 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::15 908 # Per bank write bursts +system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry +system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry +system.mem_ctrls.totGap 5246394 # Total gap between requests +system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::6 79271 # Read request sizes (log2) +system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::6 79267 # Write request sizes (log2) +system.mem_ctrls.rdQLenPdf::0 41659 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::1 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::2 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::4 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::0 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::1 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::2 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::3 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::4 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::5 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::6 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::7 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::8 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::9 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::10 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::11 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::15 330 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::16 402 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::17 2224 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::18 2668 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::19 2708 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::20 2791 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::21 2963 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::22 2810 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::23 2680 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::24 2663 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::25 2661 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::26 2661 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::27 2658 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::28 2660 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::29 2658 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::30 2658 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::31 2658 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::32 2658 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.mem_ctrls.bytesPerActivate::samples 15795 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::mean 344.923330 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::gmean 229.090130 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::stdev 305.803840 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::0-127 3621 22.92% 22.92% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::128-255 4154 26.30% 49.22% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::256-383 2325 14.72% 63.94% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::384-511 1784 11.29% 75.24% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::512-639 865 5.48% 80.72% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::640-767 706 4.47% 85.19% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::768-895 510 3.23% 88.41% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::896-1023 328 2.08% 90.49% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::1024-1151 1502 9.51% 100.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::total 15795 # Bytes accessed per row activation +system.mem_ctrls.rdPerTurnAround::samples 2658 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::mean 15.670429 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::gmean 15.605623 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::stdev 1.463558 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::12-13 110 4.14% 4.14% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::14-15 1181 44.43% 48.57% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::16-17 1114 41.91% 90.48% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::18-19 223 8.39% 98.87% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::20-21 29 1.09% 99.96% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::36-37 1 0.04% 100.00% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::total 2658 # Reads before turning the bus around for writes +system.mem_ctrls.wrPerTurnAround::samples 2658 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::mean 16.366441 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::gmean 16.340186 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::stdev 0.970216 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::16 2300 86.53% 86.53% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::17 19 0.71% 87.25% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::18 111 4.18% 91.42% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::19 179 6.73% 98.16% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::20 49 1.84% 100.00% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::total 2658 # Writes before turning the bus around for reads +system.mem_ctrls.totQLat 835288 # Total ticks spent queuing +system.mem_ctrls.totMemAccLat 1626809 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.totBusLat 208295 # Total ticks spent in databus transfers +system.mem_ctrls.avgQLat 20.05 # Average queueing delay per DRAM burst +system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst +system.mem_ctrls.avgMemAccLat 39.05 # Average memory access latency per DRAM burst +system.mem_ctrls.avgRdBW 508.19 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrls.avgWrBW 530.67 # Average achieved write bandwidth in MiByte/s +system.mem_ctrls.avgRdBWSys 967.00 # Average system read bandwidth in MiByte/s +system.mem_ctrls.avgWrBWSys 966.95 # Average system write bandwidth in MiByte/s +system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.mem_ctrls.busUtil 8.12 # Data bus utilization in percentage +system.mem_ctrls.busUtilRead 3.97 # Data bus utilization in percentage for reads +system.mem_ctrls.busUtilWrite 4.15 # Data bus utilization in percentage for writes +system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing +system.mem_ctrls.avgWrQLen 26.01 # Average write queue length when enqueuing +system.mem_ctrls.readRowHits 29472 # Number of row buffer hits during reads +system.mem_ctrls.writeRowHits 39888 # Number of row buffer hits during writes +system.mem_ctrls.readRowHitRate 70.75 # Row buffer hit rate for reads +system.mem_ctrls.writeRowHitRate 91.64 # Row buffer hit rate for writes +system.mem_ctrls.avgGap 33.09 # Average gap between requests +system.mem_ctrls.pageHitRate 81.42 # Row buffer hit rate, read and write combined +system.mem_ctrls_0.actEnergy 79710960 # Energy for activate commands per rank (pJ) +system.mem_ctrls_0.preEnergy 43126104 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_0.readEnergy 282823968 # Energy for read commands per rank (pJ) +system.mem_ctrls_0.writeEnergy 218655360 # Energy for write commands per rank (pJ) +system.mem_ctrls_0.refreshEnergy 414882000.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_0.actBackEnergy 659598072 # Energy for active background per rank (pJ) +system.mem_ctrls_0.preBackEnergy 10126848 # Energy for precharge background per rank (pJ) +system.mem_ctrls_0.actPowerDownEnergy 1616957760 # Energy for active power-down per rank (pJ) +system.mem_ctrls_0.prePowerDownEnergy 62452224 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls_0.selfRefreshEnergy 21677280 # Energy for self refresh per rank (pJ) +system.mem_ctrls_0.totalEnergy 3410010576 # Total energy per rank (pJ) +system.mem_ctrls_0.averagePower 649.963342 # Core power per rank (mW) +system.mem_ctrls_0.totalIdleTime 3773570 # Total Idle time Per DRAM Rank +system.mem_ctrls_0.memoryStateTime::IDLE 6170 # Time in different power states +system.mem_ctrls_0.memoryStateTime::REF 175566 # Time in different power states +system.mem_ctrls_0.memoryStateTime::SREF 65011 # Time in different power states +system.mem_ctrls_0.memoryStateTime::PRE_PDN 162636 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT 1291123 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT_PDN 3545960 # Time in different power states +system.mem_ctrls_1.actEnergy 33108180 # Energy for activate commands per rank (pJ) +system.mem_ctrls_1.preEnergy 17905776 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_1.readEnergy 193088448 # Energy for read commands per rank (pJ) +system.mem_ctrls_1.writeEnergy 144673344 # Energy for write commands per rank (pJ) +system.mem_ctrls_1.refreshEnergy 397057440.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_1.actBackEnergy 650520024 # Energy for active background per rank (pJ) +system.mem_ctrls_1.preBackEnergy 12185088 # Energy for precharge background per rank (pJ) +system.mem_ctrls_1.actPowerDownEnergy 1517506896 # Energy for active power-down per rank (pJ) +system.mem_ctrls_1.prePowerDownEnergy 81936768 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls_1.selfRefreshEnergy 62020080 # Energy for self refresh per rank (pJ) +system.mem_ctrls_1.totalEnergy 3110002044 # Total energy per rank (pJ) +system.mem_ctrls_1.averagePower 592.780368 # Core power per rank (mW) +system.mem_ctrls_1.totalIdleTime 3787958 # Total Idle time Per DRAM Rank +system.mem_ctrls_1.memoryStateTime::IDLE 12732 # Time in different power states +system.mem_ctrls_1.memoryStateTime::REF 167990 # Time in different power states +system.mem_ctrls_1.memoryStateTime::SREF 246912 # Time in different power states +system.mem_ctrls_1.memoryStateTime::PRE_PDN 213377 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT 1277589 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT_PDN 3327866 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 5246466 # Cumulative time (in ticks) in various power states +system.cpu.clk_domain.clock 1 # Clock period in ticks +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 183 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 5246466 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 5246466 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 266066 # Number of instructions committed +system.cpu.committedOps 266066 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 266065 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses +system.cpu.num_func_calls 19074 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 39832 # number of instructions that are conditional controls +system.cpu.num_int_insts 266065 # number of integer instructions +system.cpu.num_fp_insts 0 # number of float instructions +system.cpu.num_int_register_reads 351637 # number of times the integer registers were read +system.cpu.num_int_register_writes 182516 # number of times the integer registers were written +system.cpu.num_fp_register_reads 0 # number of times the floating registers were read +system.cpu.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu.num_mem_refs 106592 # number of memory refs +system.cpu.num_load_insts 62875 # Number of load instructions +system.cpu.num_store_insts 43717 # Number of store instructions +system.cpu.num_idle_cycles 0 # Number of idle cycles +system.cpu.num_busy_cycles 5246466 # Number of busy cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.Branches 58906 # Number of branches fetched +system.cpu.op_class::No_OpClass 188 0.07% 0.07% # Class of executed instruction +system.cpu.op_class::IntAlu 158793 59.64% 59.71% # Class of executed instruction +system.cpu.op_class::IntMult 431 0.16% 59.87% # Class of executed instruction +system.cpu.op_class::IntDiv 246 0.09% 59.97% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 59.97% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 59.97% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 59.97% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 59.97% # Class of executed instruction +system.cpu.op_class::FloatMultAcc 0 0.00% 59.97% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 59.97% # Class of executed instruction +system.cpu.op_class::FloatMisc 0 0.00% 59.97% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 59.97% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 59.97% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 59.97% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 59.97% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 59.97% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 59.97% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 59.97% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 59.97% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 59.97% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 59.97% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 59.97% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 59.97% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 59.97% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 59.97% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 59.97% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 59.97% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 59.97% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 59.97% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 59.97% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 59.97% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 59.97% # Class of executed instruction +system.cpu.op_class::MemRead 62875 23.62% 83.58% # Class of executed instruction +system.cpu.op_class::MemWrite 43717 16.42% 100.00% # Class of executed instruction +system.cpu.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 266250 # Class of executed instruction +system.ruby.clk_domain.clock 1 # Clock period in ticks +system.ruby.pwrStateResidencyTicks::UNDEFINED 5246466 # Cumulative time (in ticks) in various power states +system.ruby.delayHist::bucket_size 1 # delay histogram for all message +system.ruby.delayHist::max_bucket 9 # delay histogram for all message +system.ruby.delayHist::samples 158538 # delay histogram for all message +system.ruby.delayHist | 158538 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message +system.ruby.delayHist::total 158538 # delay histogram for all message +system.ruby.outstanding_req_hist_seqr::bucket_size 1 +system.ruby.outstanding_req_hist_seqr::max_bucket 9 +system.ruby.outstanding_req_hist_seqr::samples 372842 +system.ruby.outstanding_req_hist_seqr::mean 1 +system.ruby.outstanding_req_hist_seqr::gmean 1 +system.ruby.outstanding_req_hist_seqr | 0 0.00% 0.00% | 372842 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.outstanding_req_hist_seqr::total 372842 +system.ruby.latency_hist_seqr::bucket_size 64 +system.ruby.latency_hist_seqr::max_bucket 639 +system.ruby.latency_hist_seqr::samples 372841 +system.ruby.latency_hist_seqr::mean 13.071591 +system.ruby.latency_hist_seqr::gmean 2.303358 +system.ruby.latency_hist_seqr::stdev 28.899910 +system.ruby.latency_hist_seqr | 332521 89.19% 89.19% | 37494 10.06% 99.24% | 1855 0.50% 99.74% | 376 0.10% 99.84% | 322 0.09% 99.93% | 238 0.06% 99.99% | 17 0.00% 100.00% | 3 0.00% 100.00% | 2 0.00% 100.00% | 13 0.00% 100.00% +system.ruby.latency_hist_seqr::total 372841 +system.ruby.hit_latency_hist_seqr::bucket_size 1 +system.ruby.hit_latency_hist_seqr::max_bucket 9 +system.ruby.hit_latency_hist_seqr::samples 293570 +system.ruby.hit_latency_hist_seqr::mean 1 +system.ruby.hit_latency_hist_seqr::gmean 1 +system.ruby.hit_latency_hist_seqr | 0 0.00% 0.00% | 293570 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.hit_latency_hist_seqr::total 293570 +system.ruby.miss_latency_hist_seqr::bucket_size 64 +system.ruby.miss_latency_hist_seqr::max_bucket 639 +system.ruby.miss_latency_hist_seqr::samples 79271 +system.ruby.miss_latency_hist_seqr::mean 57.777182 +system.ruby.miss_latency_hist_seqr::gmean 50.619805 +system.ruby.miss_latency_hist_seqr::stdev 37.283085 +system.ruby.miss_latency_hist_seqr | 38951 49.14% 49.14% | 37494 47.30% 96.44% | 1855 2.34% 98.78% | 376 0.47% 99.25% | 322 0.41% 99.66% | 238 0.30% 99.96% | 17 0.02% 99.98% | 3 0.00% 99.98% | 2 0.00% 99.98% | 13 0.02% 100.00% +system.ruby.miss_latency_hist_seqr::total 79271 +system.ruby.Directory.incomplete_times_seqr 79270 +system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 5246466 # Cumulative time (in ticks) in various power states +system.ruby.l1_cntrl0.cacheMemory.demand_hits 293570 # Number of cache demand hits +system.ruby.l1_cntrl0.cacheMemory.demand_misses 79271 # Number of cache demand misses +system.ruby.l1_cntrl0.cacheMemory.demand_accesses 372841 # Number of cache demand accesses +system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 5246466 # Cumulative time (in ticks) in various power states +system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 5246466 # Cumulative time (in ticks) in various power states +system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks +system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 5246466 # Cumulative time (in ticks) in various power states +system.ruby.network.routers0.percent_links_utilized 7.554514 +system.ruby.network.routers0.msg_count.Control::2 79271 +system.ruby.network.routers0.msg_count.Data::2 79267 +system.ruby.network.routers0.msg_count.Response_Data::4 79271 +system.ruby.network.routers0.msg_count.Writeback_Control::3 79267 +system.ruby.network.routers0.msg_bytes.Control::2 634168 +system.ruby.network.routers0.msg_bytes.Data::2 5707224 +system.ruby.network.routers0.msg_bytes.Response_Data::4 5707512 +system.ruby.network.routers0.msg_bytes.Writeback_Control::3 634136 +system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 5246466 # Cumulative time (in ticks) in various power states +system.ruby.network.routers1.percent_links_utilized 7.554514 +system.ruby.network.routers1.msg_count.Control::2 79271 +system.ruby.network.routers1.msg_count.Data::2 79267 +system.ruby.network.routers1.msg_count.Response_Data::4 79271 +system.ruby.network.routers1.msg_count.Writeback_Control::3 79267 +system.ruby.network.routers1.msg_bytes.Control::2 634168 +system.ruby.network.routers1.msg_bytes.Data::2 5707224 +system.ruby.network.routers1.msg_bytes.Response_Data::4 5707512 +system.ruby.network.routers1.msg_bytes.Writeback_Control::3 634136 +system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 5246466 # Cumulative time (in ticks) in various power states +system.ruby.network.routers2.percent_links_utilized 7.554514 +system.ruby.network.routers2.msg_count.Control::2 79271 +system.ruby.network.routers2.msg_count.Data::2 79267 +system.ruby.network.routers2.msg_count.Response_Data::4 79271 +system.ruby.network.routers2.msg_count.Writeback_Control::3 79267 +system.ruby.network.routers2.msg_bytes.Control::2 634168 +system.ruby.network.routers2.msg_bytes.Data::2 5707224 +system.ruby.network.routers2.msg_bytes.Response_Data::4 5707512 +system.ruby.network.routers2.msg_bytes.Writeback_Control::3 634136 +system.ruby.network.pwrStateResidencyTicks::UNDEFINED 5246466 # Cumulative time (in ticks) in various power states +system.ruby.network.msg_count.Control 237813 +system.ruby.network.msg_count.Data 237801 +system.ruby.network.msg_count.Response_Data 237813 +system.ruby.network.msg_count.Writeback_Control 237801 +system.ruby.network.msg_byte.Control 1902504 +system.ruby.network.msg_byte.Data 17121672 +system.ruby.network.msg_byte.Response_Data 17122536 +system.ruby.network.msg_byte.Writeback_Control 1902408 +system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 5246466 # Cumulative time (in ticks) in various power states +system.ruby.network.routers0.throttle0.link_utilization 7.554666 +system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 79271 +system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 79267 +system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 5707512 +system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3 634136 +system.ruby.network.routers0.throttle1.link_utilization 7.554361 +system.ruby.network.routers0.throttle1.msg_count.Control::2 79271 +system.ruby.network.routers0.throttle1.msg_count.Data::2 79267 +system.ruby.network.routers0.throttle1.msg_bytes.Control::2 634168 +system.ruby.network.routers0.throttle1.msg_bytes.Data::2 5707224 +system.ruby.network.routers1.throttle0.link_utilization 7.554361 +system.ruby.network.routers1.throttle0.msg_count.Control::2 79271 +system.ruby.network.routers1.throttle0.msg_count.Data::2 79267 +system.ruby.network.routers1.throttle0.msg_bytes.Control::2 634168 +system.ruby.network.routers1.throttle0.msg_bytes.Data::2 5707224 +system.ruby.network.routers1.throttle1.link_utilization 7.554666 +system.ruby.network.routers1.throttle1.msg_count.Response_Data::4 79271 +system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::3 79267 +system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4 5707512 +system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::3 634136 +system.ruby.network.routers2.throttle0.link_utilization 7.554666 +system.ruby.network.routers2.throttle0.msg_count.Response_Data::4 79271 +system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3 79267 +system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4 5707512 +system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3 634136 +system.ruby.network.routers2.throttle1.link_utilization 7.554361 +system.ruby.network.routers2.throttle1.msg_count.Control::2 79271 +system.ruby.network.routers2.throttle1.msg_count.Data::2 79267 +system.ruby.network.routers2.throttle1.msg_bytes.Control::2 634168 +system.ruby.network.routers2.throttle1.msg_bytes.Data::2 5707224 +system.ruby.delayVCHist.vnet_1::bucket_size 1 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1::max_bucket 9 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1::samples 79271 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1 | 79271 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1::total 79271 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_2::bucket_size 1 # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2::max_bucket 9 # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2::samples 79267 # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2 | 79267 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2::total 79267 # delay histogram for vnet_2 +system.ruby.LD.latency_hist_seqr::bucket_size 64 +system.ruby.LD.latency_hist_seqr::max_bucket 639 +system.ruby.LD.latency_hist_seqr::samples 62875 +system.ruby.LD.latency_hist_seqr::mean 27.680191 +system.ruby.LD.latency_hist_seqr::gmean 7.180276 +system.ruby.LD.latency_hist_seqr::stdev 35.811045 +system.ruby.LD.latency_hist_seqr | 50013 79.54% 79.54% | 11930 18.97% 98.52% | 656 1.04% 99.56% | 86 0.14% 99.70% | 110 0.17% 99.87% | 69 0.11% 99.98% | 11 0.02% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.latency_hist_seqr::total 62875 +system.ruby.LD.hit_latency_hist_seqr::bucket_size 1 +system.ruby.LD.hit_latency_hist_seqr::max_bucket 9 +system.ruby.LD.hit_latency_hist_seqr::samples 30585 +system.ruby.LD.hit_latency_hist_seqr::mean 1 +system.ruby.LD.hit_latency_hist_seqr::gmean 1 +system.ruby.LD.hit_latency_hist_seqr | 0 0.00% 0.00% | 30585 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.hit_latency_hist_seqr::total 30585 +system.ruby.LD.miss_latency_hist_seqr::bucket_size 64 +system.ruby.LD.miss_latency_hist_seqr::max_bucket 639 +system.ruby.LD.miss_latency_hist_seqr::samples 32290 +system.ruby.LD.miss_latency_hist_seqr::mean 52.951595 +system.ruby.LD.miss_latency_hist_seqr::gmean 46.459624 +system.ruby.LD.miss_latency_hist_seqr::stdev 34.412980 +system.ruby.LD.miss_latency_hist_seqr | 19428 60.17% 60.17% | 11930 36.95% 97.11% | 656 2.03% 99.15% | 86 0.27% 99.41% | 110 0.34% 99.75% | 69 0.21% 99.97% | 11 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.miss_latency_hist_seqr::total 32290 +system.ruby.ST.latency_hist_seqr::bucket_size 64 +system.ruby.ST.latency_hist_seqr::max_bucket 639 +system.ruby.ST.latency_hist_seqr::samples 43716 +system.ruby.ST.latency_hist_seqr::mean 11.968158 +system.ruby.ST.latency_hist_seqr::gmean 2.425644 +system.ruby.ST.latency_hist_seqr::stdev 26.441690 +system.ruby.ST.latency_hist_seqr | 40932 93.63% 93.63% | 2520 5.76% 99.40% | 167 0.38% 99.78% | 45 0.10% 99.88% | 22 0.05% 99.93% | 18 0.04% 99.97% | 0 0.00% 99.97% | 0 0.00% 99.97% | 2 0.00% 99.98% | 10 0.02% 100.00% +system.ruby.ST.latency_hist_seqr::total 43716 +system.ruby.ST.hit_latency_hist_seqr::bucket_size 1 +system.ruby.ST.hit_latency_hist_seqr::max_bucket 9 +system.ruby.ST.hit_latency_hist_seqr::samples 33299 +system.ruby.ST.hit_latency_hist_seqr::mean 1 +system.ruby.ST.hit_latency_hist_seqr::gmean 1 +system.ruby.ST.hit_latency_hist_seqr | 0 0.00% 0.00% | 33299 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.hit_latency_hist_seqr::total 33299 +system.ruby.ST.miss_latency_hist_seqr::bucket_size 64 +system.ruby.ST.miss_latency_hist_seqr::max_bucket 639 +system.ruby.ST.miss_latency_hist_seqr::samples 10417 +system.ruby.ST.miss_latency_hist_seqr::mean 47.028991 +system.ruby.ST.miss_latency_hist_seqr::gmean 41.206543 +system.ruby.ST.miss_latency_hist_seqr::stdev 36.336668 +system.ruby.ST.miss_latency_hist_seqr | 7633 73.27% 73.27% | 2520 24.19% 97.47% | 167 1.60% 99.07% | 45 0.43% 99.50% | 22 0.21% 99.71% | 18 0.17% 99.88% | 0 0.00% 99.88% | 0 0.00% 99.88% | 2 0.02% 99.90% | 10 0.10% 100.00% +system.ruby.ST.miss_latency_hist_seqr::total 10417 +system.ruby.IFETCH.latency_hist_seqr::bucket_size 64 +system.ruby.IFETCH.latency_hist_seqr::max_bucket 639 +system.ruby.IFETCH.latency_hist_seqr::samples 266250 +system.ruby.IFETCH.latency_hist_seqr::mean 9.802941 +system.ruby.IFETCH.latency_hist_seqr::gmean 1.746090 +system.ruby.IFETCH.latency_hist_seqr::stdev 26.280316 +system.ruby.IFETCH.latency_hist_seqr | 241576 90.73% 90.73% | 23044 8.66% 99.39% | 1032 0.39% 99.78% | 245 0.09% 99.87% | 190 0.07% 99.94% | 151 0.06% 100.00% | 6 0.00% 100.00% | 3 0.00% 100.00% | 0 0.00% 100.00% | 3 0.00% 100.00% +system.ruby.IFETCH.latency_hist_seqr::total 266250 +system.ruby.IFETCH.hit_latency_hist_seqr::bucket_size 1 +system.ruby.IFETCH.hit_latency_hist_seqr::max_bucket 9 +system.ruby.IFETCH.hit_latency_hist_seqr::samples 229686 +system.ruby.IFETCH.hit_latency_hist_seqr::mean 1 +system.ruby.IFETCH.hit_latency_hist_seqr::gmean 1 +system.ruby.IFETCH.hit_latency_hist_seqr | 0 0.00% 0.00% | 229686 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.hit_latency_hist_seqr::total 229686 +system.ruby.IFETCH.miss_latency_hist_seqr::bucket_size 64 +system.ruby.IFETCH.miss_latency_hist_seqr::max_bucket 639 +system.ruby.IFETCH.miss_latency_hist_seqr::samples 36564 +system.ruby.IFETCH.miss_latency_hist_seqr::mean 65.100837 +system.ruby.IFETCH.miss_latency_hist_seqr::gmean 57.898658 +system.ruby.IFETCH.miss_latency_hist_seqr::stdev 38.529976 +system.ruby.IFETCH.miss_latency_hist_seqr | 11890 32.52% 32.52% | 23044 63.02% 95.54% | 1032 2.82% 98.36% | 245 0.67% 99.03% | 190 0.52% 99.55% | 151 0.41% 99.97% | 6 0.02% 99.98% | 3 0.01% 99.99% | 0 0.00% 99.99% | 3 0.01% 100.00% +system.ruby.IFETCH.miss_latency_hist_seqr::total 36564 +system.ruby.Directory.miss_mach_latency_hist_seqr::bucket_size 64 +system.ruby.Directory.miss_mach_latency_hist_seqr::max_bucket 639 +system.ruby.Directory.miss_mach_latency_hist_seqr::samples 79271 +system.ruby.Directory.miss_mach_latency_hist_seqr::mean 57.777182 +system.ruby.Directory.miss_mach_latency_hist_seqr::gmean 50.619805 +system.ruby.Directory.miss_mach_latency_hist_seqr::stdev 37.283085 +system.ruby.Directory.miss_mach_latency_hist_seqr | 38951 49.14% 49.14% | 37494 47.30% 96.44% | 1855 2.34% 98.78% | 376 0.47% 99.25% | 322 0.41% 99.66% | 238 0.30% 99.96% | 17 0.02% 99.98% | 3 0.00% 99.98% | 2 0.00% 99.98% | 13 0.02% 100.00% +system.ruby.Directory.miss_mach_latency_hist_seqr::total 79271 +system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::bucket_size 1 +system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::max_bucket 9 +system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::samples 1 +system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::stdev nan +system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::total 1 +system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::bucket_size 1 +system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::max_bucket 9 +system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::samples 1 +system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::stdev nan +system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::total 1 +system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::bucket_size 1 +system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::max_bucket 9 +system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::samples 1 +system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::stdev nan +system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::total 1 +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::bucket_size 8 +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::max_bucket 79 +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::samples 1 +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::mean 75 +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::gmean 75.000000 +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::stdev nan +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::total 1 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::samples 32290 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::mean 52.951595 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::gmean 46.459624 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::stdev 34.412980 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr | 19428 60.17% 60.17% | 11930 36.95% 97.11% | 656 2.03% 99.15% | 86 0.27% 99.41% | 110 0.34% 99.75% | 69 0.21% 99.97% | 11 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::total 32290 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::samples 10417 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::mean 47.028991 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::gmean 41.206543 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::stdev 36.336668 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr | 7633 73.27% 73.27% | 2520 24.19% 97.47% | 167 1.60% 99.07% | 45 0.43% 99.50% | 22 0.21% 99.71% | 18 0.17% 99.88% | 0 0.00% 99.88% | 0 0.00% 99.88% | 2 0.02% 99.90% | 10 0.10% 100.00% +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::total 10417 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::samples 36564 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::mean 65.100837 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::gmean 57.898658 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::stdev 38.529976 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr | 11890 32.52% 32.52% | 23044 63.02% 95.54% | 1032 2.82% 98.36% | 245 0.67% 99.03% | 190 0.52% 99.55% | 151 0.41% 99.97% | 6 0.02% 99.98% | 3 0.01% 99.99% | 0 0.00% 99.99% | 3 0.01% 100.00% +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::total 36564 +system.ruby.Directory_Controller.GETX 79271 0.00% 0.00% +system.ruby.Directory_Controller.PUTX 79267 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Data 79271 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Ack 79267 0.00% 0.00% +system.ruby.Directory_Controller.I.GETX 79271 0.00% 0.00% +system.ruby.Directory_Controller.M.PUTX 79267 0.00% 0.00% +system.ruby.Directory_Controller.IM.Memory_Data 79271 0.00% 0.00% +system.ruby.Directory_Controller.MI.Memory_Ack 79267 0.00% 0.00% +system.ruby.L1Cache_Controller.Load 62875 0.00% 0.00% +system.ruby.L1Cache_Controller.Ifetch 266250 0.00% 0.00% +system.ruby.L1Cache_Controller.Store 43716 0.00% 0.00% +system.ruby.L1Cache_Controller.Data 79271 0.00% 0.00% +system.ruby.L1Cache_Controller.Replacement 79267 0.00% 0.00% +system.ruby.L1Cache_Controller.Writeback_Ack 79267 0.00% 0.00% +system.ruby.L1Cache_Controller.I.Load 32290 0.00% 0.00% +system.ruby.L1Cache_Controller.I.Ifetch 36564 0.00% 0.00% +system.ruby.L1Cache_Controller.I.Store 10417 0.00% 0.00% +system.ruby.L1Cache_Controller.M.Load 30585 0.00% 0.00% +system.ruby.L1Cache_Controller.M.Ifetch 229686 0.00% 0.00% +system.ruby.L1Cache_Controller.M.Store 33299 0.00% 0.00% +system.ruby.L1Cache_Controller.M.Replacement 79267 0.00% 0.00% +system.ruby.L1Cache_Controller.MI.Writeback_Ack 79267 0.00% 0.00% +system.ruby.L1Cache_Controller.IS.Data 68854 0.00% 0.00% +system.ruby.L1Cache_Controller.IM.Data 10417 0.00% 0.00% + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-timing/config.ini b/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-timing/config.ini new file mode 100644 index 000000000..eb052bbd2 --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-timing/config.ini @@ -0,0 +1,380 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain +boot_osflags=a +cache_line_size=64 +clk_domain=system.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +exit_on_work_items=false +init_param=0 +kernel= +kernel_addr_check=true +load_addr_mask=1099511627775 +load_offset=0 +mem_mode=timing +mem_ranges= +memories=system.physmem +mmap_using_noreserve=false +multi_thread=false +num_work_ids=16 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +readfile= +symbolfile= +thermal_components= +thermal_model=Null +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=TimingSimpleCPU +children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload +branchPred=Null +checker=Null +clk_domain=system.cpu_clk_domain +cpu_id=0 +default_p_state=UNDEFINED +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +eventq_index=0 +function_trace=false +function_trace_start=0 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +profile=0 +progress_interval=0 +simpoint_start_insts= +socket_id=0 +switched_out=false +system=system +tracer=system.cpu.tracer +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.dcache] +type=Cache +children=tags +addr_ranges=0:18446744073709551615:0:0:0:0 +assoc=2 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +data_latency=2 +default_p_state=UNDEFINED +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=4 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=262144 +system=system +tag_latency=2 +tags=system.cpu.dcache.tags +tgts_per_mshr=20 +write_buffers=8 +writeback_clean=false +cpu_side=system.cpu.dcache_port +mem_side=system.cpu.toL2Bus.slave[1] + +[system.cpu.dcache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +data_latency=2 +default_p_state=UNDEFINED +eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +sequential_access=false +size=262144 +tag_latency=2 + +[system.cpu.dtb] +type=RiscvTLB +eventq_index=0 +size=64 + +[system.cpu.icache] +type=Cache +children=tags +addr_ranges=0:18446744073709551615:0:0:0:0 +assoc=2 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +data_latency=2 +default_p_state=UNDEFINED +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=true +max_miss_count=0 +mshrs=4 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=131072 +system=system +tag_latency=2 +tags=system.cpu.icache.tags +tgts_per_mshr=20 +write_buffers=8 +writeback_clean=true +cpu_side=system.cpu.icache_port +mem_side=system.cpu.toL2Bus.slave[0] + +[system.cpu.icache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +data_latency=2 +default_p_state=UNDEFINED +eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +sequential_access=false +size=131072 +tag_latency=2 + +[system.cpu.interrupts] +type=RiscvInterrupts +eventq_index=0 + +[system.cpu.isa] +type=RiscvISA +eventq_index=0 + +[system.cpu.itb] +type=RiscvTLB +eventq_index=0 +size=64 + +[system.cpu.l2cache] +type=Cache +children=tags +addr_ranges=0:18446744073709551615:0:0:0:0 +assoc=8 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +data_latency=20 +default_p_state=UNDEFINED +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=20 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +prefetch_on_access=false +prefetcher=Null +response_latency=20 +sequential_access=false +size=2097152 +system=system +tag_latency=20 +tags=system.cpu.l2cache.tags +tgts_per_mshr=12 +write_buffers=8 +writeback_clean=false +cpu_side=system.cpu.toL2Bus.master[0] +mem_side=system.membus.slave[1] + +[system.cpu.l2cache.tags] +type=LRU +assoc=8 +block_size=64 +clk_domain=system.cpu_clk_domain +data_latency=20 +default_p_state=UNDEFINED +eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +sequential_access=false +size=2097152 +tag_latency=20 + +[system.cpu.toL2Bus] +type=CoherentXBar +children=snoop_filter +clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED +eventq_index=0 +forward_latency=0 +frontend_latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +point_of_coherency=false +power_model=Null +response_latency=1 +snoop_filter=system.cpu.toL2Bus.snoop_filter +snoop_response_latency=1 +system=system +use_default_range=false +width=32 +master=system.cpu.l2cache.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side + +[system.cpu.toL2Bus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=0 +max_capacity=8388608 +system=system + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=LiveProcess +cmd=insttest +cwd= +drivers= +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable=/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64i/insttest +gid=100 +input=cin +kvmInSE=false +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=0 +system=system +uid=100 +useArchPT=false + +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000000 + +[system.membus] +type=CoherentXBar +children=snoop_filter +clk_domain=system.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +forward_latency=4 +frontend_latency=3 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +point_of_coherency=true +power_model=Null +response_latency=2 +snoop_filter=system.membus.snoop_filter +snoop_response_latency=4 +system=system +use_default_range=false +width=16 +master=system.physmem.port +slave=system.system_port system.cpu.l2cache.mem_side + +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + +[system.physmem] +type=SimpleMemory +bandwidth=73.000000 +clk_domain=system.clk_domain +conf_table_reported=true +default_p_state=UNDEFINED +eventq_index=0 +in_addr_map=true +kvm_map=true +latency=30000 +latency_var=0 +null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +range=0:134217727:0:0:0:0 +port=system.membus.master[0] + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-timing/config.json b/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-timing/config.json new file mode 100644 index 000000000..e14de7091 --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-timing/config.json @@ -0,0 +1,508 @@ +{ + "name": null, + "sim_quantum": 0, + "system": { + "kernel": "", + "mmap_using_noreserve": false, + "kernel_addr_check": true, + "membus": { + "point_of_coherency": true, + "system": "system", + "response_latency": 2, + "cxx_class": "CoherentXBar", + "forward_latency": 4, + "clk_domain": "system.clk_domain", + "width": 16, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "master": { + "peer": [ + "system.physmem.port" + ], + "role": "MASTER" + }, + "type": "CoherentXBar", + "frontend_latency": 3, + "slave": { + "peer": [ + "system.system_port", + "system.cpu.l2cache.mem_side" + ], + "role": "SLAVE" + }, + "p_state_clk_gate_min": 1000, + "snoop_filter": { + "name": "snoop_filter", + "system": "system", + "max_capacity": 8388608, + "eventq_index": 0, + "cxx_class": "SnoopFilter", + "path": "system.membus.snoop_filter", + "type": "SnoopFilter", + "lookup_latency": 1 + }, + "power_model": null, + "path": "system.membus", + "snoop_response_latency": 4, + "name": "membus", + "p_state_clk_gate_bins": 20, + "use_default_range": false + }, + "symbolfile": "", + "readfile": "", + "thermal_model": null, + "cxx_class": "System", + "work_begin_cpu_id_exit": -1, + "load_offset": 0, + "work_begin_exit_count": 0, + "p_state_clk_gate_min": 1000, + "memories": [ + "system.physmem" + ], + "work_begin_ckpt_count": 0, + "clk_domain": { + "name": "clk_domain", + "clock": [ + 1000 + ], + "init_perf_level": 0, + "voltage_domain": "system.voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "mem_ranges": [], + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "dvfs_handler": { + "enable": false, + "name": "dvfs_handler", + "sys_clk_domain": "system.clk_domain", + "transition_latency": 100000000, + "eventq_index": 0, + "cxx_class": "DVFSHandler", + "domains": [], + "path": "system.dvfs_handler", + "type": "DVFSHandler" + }, + "work_end_exit_count": 0, + "type": "System", + "voltage_domain": { + "name": "voltage_domain", + "eventq_index": 0, + "voltage": [ + "1.0" + ], + "cxx_class": "VoltageDomain", + "path": "system.voltage_domain", + "type": "VoltageDomain" + }, + "cache_line_size": 64, + "boot_osflags": "a", + "system_port": { + "peer": "system.membus.slave[0]", + "role": "MASTER" + }, + "physmem": { + "range": "0:134217727:0:0:0:0", + "latency": 30000, + "name": "physmem", + "p_state_clk_gate_min": 1000, + "eventq_index": 0, + "p_state_clk_gate_bins": 20, + "default_p_state": "UNDEFINED", + "kvm_map": true, + "clk_domain": "system.clk_domain", + "power_model": null, + "latency_var": 0, + "bandwidth": "73.000000", + "conf_table_reported": true, + "cxx_class": "SimpleMemory", + "p_state_clk_gate_max": 1000000000000, + "path": "system.physmem", + "null": false, + "type": "SimpleMemory", + "port": { + "peer": "system.membus.master[0]", + "role": "SLAVE" + }, + "in_addr_map": true + }, + "power_model": null, + "work_cpus_ckpt_count": 0, + "thermal_components": [], + "path": "system", + "cpu_clk_domain": { + "name": "cpu_clk_domain", + "clock": [ + 500 + ], + "init_perf_level": 0, + "voltage_domain": "system.voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.cpu_clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "work_end_ckpt_count": 0, + "mem_mode": "timing", + "name": "system", + "init_param": 0, + "p_state_clk_gate_bins": 20, + "load_addr_mask": 1099511627775, + "cpu": [ + { + "do_statistics_insts": true, + "numThreads": 1, + "itb": { + "name": "itb", + "eventq_index": 0, + "cxx_class": "RiscvISA::TLB", + "path": "system.cpu.itb", + "type": "RiscvTLB", + "size": 64 + }, + "system": "system", + "icache": { + "cpu_side": { + "peer": "system.cpu.icache_port", + "role": "SLAVE" + }, + "clusivity": "mostly_incl", + "prefetcher": null, + "system": "system", + "write_buffers": 8, + "response_latency": 2, + "cxx_class": "Cache", + "size": 131072, + "type": "Cache", + "clk_domain": "system.cpu_clk_domain", + "max_miss_count": 0, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "mem_side": { + "peer": "system.cpu.toL2Bus.slave[0]", + "role": "MASTER" + }, + "mshrs": 4, + "writeback_clean": true, + "p_state_clk_gate_min": 1000, + "tags": { + "size": 131072, + "tag_latency": 2, + "name": "tags", + "p_state_clk_gate_min": 1000, + "eventq_index": 0, + "p_state_clk_gate_bins": 20, + "default_p_state": "UNDEFINED", + "clk_domain": "system.cpu_clk_domain", + "power_model": null, + "sequential_access": false, + "assoc": 2, + "cxx_class": "LRU", + "p_state_clk_gate_max": 1000000000000, + "path": "system.cpu.icache.tags", + "block_size": 64, + "type": "LRU", + "data_latency": 2 + }, + "tgts_per_mshr": 20, + "demand_mshr_reserve": 1, + "power_model": null, + "addr_ranges": [ + "0:18446744073709551615:0:0:0:0" + ], + "is_read_only": true, + "prefetch_on_access": false, + "path": "system.cpu.icache", + "data_latency": 2, + "tag_latency": 2, + "name": "icache", + "p_state_clk_gate_bins": 20, + "sequential_access": false, + "assoc": 2 + }, + "function_trace": false, + "do_checkpoint_insts": true, + "cxx_class": "TimingSimpleCPU", + "max_loads_all_threads": 0, + "clk_domain": "system.cpu_clk_domain", + "function_trace_start": 0, + "cpu_id": 0, + "checker": null, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "toL2Bus": { + "point_of_coherency": false, + "system": "system", + "response_latency": 1, + "cxx_class": "CoherentXBar", + "forward_latency": 0, + "clk_domain": "system.cpu_clk_domain", + "width": 32, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "master": { + "peer": [ + "system.cpu.l2cache.cpu_side" + ], + "role": "MASTER" + }, + "type": "CoherentXBar", + "frontend_latency": 1, + "slave": { + "peer": [ + "system.cpu.icache.mem_side", + "system.cpu.dcache.mem_side" + ], + "role": "SLAVE" + }, + "p_state_clk_gate_min": 1000, + "snoop_filter": { + "name": "snoop_filter", + "system": "system", + "max_capacity": 8388608, + "eventq_index": 0, + "cxx_class": "SnoopFilter", + "path": "system.cpu.toL2Bus.snoop_filter", + "type": "SnoopFilter", + "lookup_latency": 0 + }, + "power_model": null, + "path": "system.cpu.toL2Bus", + "snoop_response_latency": 1, + "name": "toL2Bus", + "p_state_clk_gate_bins": 20, + "use_default_range": false + }, + "do_quiesce": true, + "type": "TimingSimpleCPU", + "profile": 0, + "icache_port": { + "peer": "system.cpu.icache.cpu_side", + "role": "MASTER" + }, + "p_state_clk_gate_bins": 20, + "p_state_clk_gate_min": 1000, + "interrupts": [ + { + "eventq_index": 0, + "path": "system.cpu.interrupts", + "type": "RiscvInterrupts", + "name": "interrupts", + "cxx_class": "RiscvISA::Interrupts" + } + ], + "dcache_port": { + "peer": "system.cpu.dcache.cpu_side", + "role": "MASTER" + }, + "socket_id": 0, + "power_model": null, + "max_insts_all_threads": 0, + "l2cache": { + "cpu_side": { + "peer": "system.cpu.toL2Bus.master[0]", + "role": "SLAVE" + }, + "clusivity": "mostly_incl", + "prefetcher": null, + "system": "system", + "write_buffers": 8, + "response_latency": 20, + "cxx_class": "Cache", + "size": 2097152, + "type": "Cache", + "clk_domain": "system.cpu_clk_domain", + "max_miss_count": 0, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "mem_side": { + "peer": "system.membus.slave[1]", + "role": "MASTER" + }, + "mshrs": 20, + "writeback_clean": false, + "p_state_clk_gate_min": 1000, + "tags": { + "size": 2097152, + "tag_latency": 20, + "name": "tags", + "p_state_clk_gate_min": 1000, + "eventq_index": 0, + "p_state_clk_gate_bins": 20, + "default_p_state": "UNDEFINED", + "clk_domain": "system.cpu_clk_domain", + "power_model": null, + "sequential_access": false, + "assoc": 8, + "cxx_class": "LRU", + "p_state_clk_gate_max": 1000000000000, + "path": "system.cpu.l2cache.tags", + "block_size": 64, + "type": "LRU", + "data_latency": 20 + }, + "tgts_per_mshr": 12, + "demand_mshr_reserve": 1, + "power_model": null, + "addr_ranges": [ + "0:18446744073709551615:0:0:0:0" + ], + "is_read_only": false, + "prefetch_on_access": false, + "path": "system.cpu.l2cache", + "data_latency": 20, + "tag_latency": 20, + "name": "l2cache", + "p_state_clk_gate_bins": 20, + "sequential_access": false, + "assoc": 8 + }, + "path": "system.cpu", + "max_loads_any_thread": 0, + "switched_out": false, + "workload": [ + { + "uid": 100, + "pid": 100, + "kvmInSE": false, + "cxx_class": "LiveProcess", + "executable": "/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64i/insttest", + "drivers": [], + "system": "system", + "gid": 100, + "eventq_index": 0, + "env": [], + "input": "cin", + "ppid": 99, + "type": "LiveProcess", + "cwd": "", + "simpoint": 0, + "euid": 100, + "path": "system.cpu.workload", + "max_stack_size": 67108864, + "name": "workload", + "cmd": [ + "insttest" + ], + "errout": "cerr", + "useArchPT": false, + "egid": 100, + "output": "cout" + } + ], + "name": "cpu", + "dtb": { + "name": "dtb", + "eventq_index": 0, + "cxx_class": "RiscvISA::TLB", + "path": "system.cpu.dtb", + "type": "RiscvTLB", + "size": 64 + }, + "simpoint_start_insts": [], + "max_insts_any_thread": 0, + "progress_interval": 0, + "branchPred": null, + "dcache": { + "cpu_side": { + "peer": "system.cpu.dcache_port", + "role": "SLAVE" + }, + "clusivity": "mostly_incl", + "prefetcher": null, + "system": "system", + "write_buffers": 8, + "response_latency": 2, + "cxx_class": "Cache", + "size": 262144, + "type": "Cache", + "clk_domain": "system.cpu_clk_domain", + "max_miss_count": 0, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "mem_side": { + "peer": "system.cpu.toL2Bus.slave[1]", + "role": "MASTER" + }, + "mshrs": 4, + "writeback_clean": false, + "p_state_clk_gate_min": 1000, + "tags": { + "size": 262144, + "tag_latency": 2, + "name": "tags", + "p_state_clk_gate_min": 1000, + "eventq_index": 0, + "p_state_clk_gate_bins": 20, + "default_p_state": "UNDEFINED", + "clk_domain": "system.cpu_clk_domain", + "power_model": null, + "sequential_access": false, + "assoc": 2, + "cxx_class": "LRU", + "p_state_clk_gate_max": 1000000000000, + "path": "system.cpu.dcache.tags", + "block_size": 64, + "type": "LRU", + "data_latency": 2 + }, + "tgts_per_mshr": 20, + "demand_mshr_reserve": 1, + "power_model": null, + "addr_ranges": [ + "0:18446744073709551615:0:0:0:0" + ], + "is_read_only": false, + "prefetch_on_access": false, + "path": "system.cpu.dcache", + "data_latency": 2, + "tag_latency": 2, + "name": "dcache", + "p_state_clk_gate_bins": 20, + "sequential_access": false, + "assoc": 2 + }, + "isa": [ + { + "eventq_index": 0, + "path": "system.cpu.isa", + "type": "RiscvISA", + "name": "isa", + "cxx_class": "RiscvISA::ISA" + } + ], + "tracer": { + "eventq_index": 0, + "path": "system.cpu.tracer", + "type": "ExeTracer", + "name": "tracer", + "cxx_class": "Trace::ExeTracer" + } + } + ], + "multi_thread": false, + "exit_on_work_items": false, + "work_item_id": -1, + "num_work_ids": 16 + }, + "time_sync_period": 100000000000, + "eventq_index": 0, + "time_sync_spin_threshold": 100000000, + "cxx_class": "Root", + "path": "root", + "time_sync_enable": false, + "type": "Root", + "full_system": false +}
\ No newline at end of file diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-timing/simerr b/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-timing/simerr new file mode 100755 index 000000000..fd133b12b --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-timing/simerr @@ -0,0 +1,3 @@ +warn: Unknown operating system; assuming Linux. +warn: Sockets disabled, not accepting gdb connections +warn: ClockedObject: More than one power state change request encountered within the same simulation tick diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-timing/simout b/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-timing/simout new file mode 100755 index 000000000..ac54effb0 --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-timing/simout @@ -0,0 +1,121 @@ +Redirecting stdout to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64i/simple-timing/simout +Redirecting stderr to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64i/simple-timing/simerr +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled Nov 30 2016 14:33:35 +gem5 started Nov 30 2016 16:18:43 +gem5 executing on zizzer, pid 34089 +command line: /z/powerjg/gem5-upstream/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64i/simple-timing -re /z/powerjg/gem5-upstream/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64i/simple-timing + +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. +lui: PASS +lui, negative: PASS +auipc: 0x157E0 +auipc: PASS +jal: PASS +jalr: PASS +beq, equal: PASS +beq, not equal: PASS +bne, equal: PASS +bne, not equal: PASS +blt, less: PASS +blt, equal: PASS +blt, greater: PASS +bge, less: PASS +bge, equal: PASS +bge, greater: PASS +bltu, greater: PASS +bltu, equal: PASS +bltu, less: PASS +bgeu, greater: PASS +bgeu, equal: PASS +bgeu, less: PASS +lb, positive: PASS +lb, negative: PASS +lh, positive: PASS +lh, negative: PASS +lw, positive: PASS +lw, negative: PASS +lbu: PASS +lhu: PASS +sb: PASS +sh: PASS +sw: PASS +addi: PASS +addi, overflow: PASS +slti, true: PASS +slti, false: PASS +sltiu, false: PASS +sltiu, true: PASS +xori (1): PASS +xori (0): PASS +ori (1): PASS +ori (A): PASS +andi (0): PASS +andi (1): PASS +slli, general: PASS +slli, erase: PASS +srli, general: PASS +srli, erase: PASS +srli, negative: PASS +srai, general: PASS +srai, erase: PASS +srai, negative: PASS +add: PASS +add, overflow: PASS +sub: PASS +sub, "overflow": PASS +sll, general: PASS +sll, erase: PASS +slt, true: PASS +slt, false: PASS +sltu, false: PASS +sltu, true: PASS +xor (1): PASS +xor (0): PASS +srl, general: PASS +srl, erase: PASS +srl, negative: PASS +sra, general: PASS +sra, erase: PASS +sra, negative: PASS +or (1): PASS +or (A): PASS +and (0): PASS +and (-1): PASS +Bytes written: 15 +open, write: PASS +access F_OK: PASS +access R_OK: PASS +access W_OK: PASS +access X_OK: PASS +stat: + st_dev = 2054 + st_ino = 55451710 + st_mode = 33188 + st_nlink = 1 + st_uid = 1004 + st_gid = 1007 + st_rdev = 0 + st_size = 0 + st_blksize = 0 + st_blocks = 1480540730 +fstat: + st_dev = 2054 + st_ino = 58196126 + st_mode = 33277 + st_nlink = 1 + st_uid = 1004 + st_gid = 1007 + st_rdev = 0 + st_size = 0 + st_blksize = 0 + st_blocks = 1480540723 +open, stat: PASS +Bytes read: 9 +String read: Ð +open, read, unlink: [1;31mFAIL[0m (expected 1; found 0) +Exiting @ tick 352925500 because target called exit() diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-timing/stats.txt b/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-timing/stats.txt new file mode 100644 index 000000000..32254e280 --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-timing/stats.txt @@ -0,0 +1,515 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.000353 # Number of seconds simulated +sim_ticks 352925500 # Number of ticks simulated +final_tick 352925500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 23308 # Simulator instruction rate (inst/s) +host_op_rate 23308 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 40827277 # Simulator tick rate (ticks/s) +host_mem_usage 243536 # Number of bytes of host memory used +host_seconds 8.64 # Real time elapsed on the host +sim_insts 201478 # Number of instructions simulated +sim_ops 201478 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 352925500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 55168 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 18368 # Number of bytes read from this memory +system.physmem.bytes_read::total 73536 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 55168 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 55168 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 862 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 287 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1149 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 156316276 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 52044978 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 208361255 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 156316276 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 156316276 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 156316276 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 52044978 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 208361255 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 352925500 # Cumulative time (in ticks) in various power states +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 130 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 352925500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 705851 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 201478 # Number of instructions committed +system.cpu.committedOps 201478 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 201477 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses +system.cpu.num_func_calls 14627 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 30164 # number of instructions that are conditional controls +system.cpu.num_int_insts 201477 # number of integer instructions +system.cpu.num_fp_insts 0 # number of float instructions +system.cpu.num_int_register_reads 266871 # number of times the integer registers were read +system.cpu.num_int_register_writes 137624 # number of times the integer registers were written +system.cpu.num_fp_register_reads 0 # number of times the floating registers were read +system.cpu.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu.num_mem_refs 80078 # number of memory refs +system.cpu.num_load_insts 46389 # Number of load instructions +system.cpu.num_store_insts 33689 # Number of store instructions +system.cpu.num_idle_cycles 0 # Number of idle cycles +system.cpu.num_busy_cycles 705851 # Number of busy cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.Branches 44791 # Number of branches fetched +system.cpu.op_class::No_OpClass 132 0.07% 0.07% # Class of executed instruction +system.cpu.op_class::IntAlu 120936 59.99% 60.05% # Class of executed instruction +system.cpu.op_class::IntMult 297 0.15% 60.20% # Class of executed instruction +system.cpu.op_class::IntDiv 166 0.08% 60.28% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 60.28% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 60.28% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 60.28% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 60.28% # Class of executed instruction +system.cpu.op_class::FloatMultAcc 0 0.00% 60.28% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 60.28% # Class of executed instruction +system.cpu.op_class::FloatMisc 0 0.00% 60.28% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 60.28% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 60.28% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 60.28% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 60.28% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 60.28% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 60.28% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 60.28% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 60.28% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 60.28% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 60.28% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 60.28% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 60.28% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 60.28% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 60.28% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 60.28% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 60.28% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 60.28% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 60.28% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 60.28% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 60.28% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 60.28% # Class of executed instruction +system.cpu.op_class::MemRead 46389 23.01% 83.29% # Class of executed instruction +system.cpu.op_class::MemWrite 33689 16.71% 100.00% # Class of executed instruction +system.cpu.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 201609 # Class of executed instruction +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 352925500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 0 # number of replacements +system.cpu.dcache.tags.tagsinuse 237.806291 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 79790 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 287 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 278.013937 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 237.806291 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.058058 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.058058 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 287 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 5 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 18 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 264 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.070068 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 160441 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 160441 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 352925500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 46314 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 46314 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 33476 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 33476 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 79790 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 79790 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 79790 # number of overall hits +system.cpu.dcache.overall_hits::total 79790 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 75 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 75 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 212 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 212 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 287 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 287 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 287 # number of overall misses +system.cpu.dcache.overall_misses::total 287 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 4725000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 4725000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 13356000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 13356000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 18081000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 18081000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 18081000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 18081000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 46389 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 46389 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 33688 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 33688 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 80077 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 80077 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 80077 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 80077 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.001617 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.001617 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006293 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.006293 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.003584 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.003584 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.003584 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.003584 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63000 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 63000 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 63000 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 63000 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 63000 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 63000 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 63000 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 75 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 75 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 212 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 212 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 287 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 287 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 287 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 287 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4650000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4650000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 13144000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 13144000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 17794000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 17794000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 17794000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 17794000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001617 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001617 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006293 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006293 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003584 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.003584 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003584 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.003584 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 62000 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 62000 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 62000 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 62000 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 62000 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 62000 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 62000 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 62000 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 352925500 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 16 # number of replacements +system.cpu.icache.tags.tagsinuse 467.242122 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 200748 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 862 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 232.886311 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 467.242122 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.228146 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.228146 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 846 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 47 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 167 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 632 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.413086 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 404082 # Number of tag accesses +system.cpu.icache.tags.data_accesses 404082 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 352925500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 200748 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 200748 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 200748 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 200748 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 200748 # number of overall hits +system.cpu.icache.overall_hits::total 200748 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 862 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 862 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 862 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 862 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 862 # number of overall misses +system.cpu.icache.overall_misses::total 862 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 54307500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 54307500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 54307500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 54307500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 54307500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 54307500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 201610 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 201610 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 201610 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 201610 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 201610 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 201610 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.004276 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.004276 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.004276 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.004276 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.004276 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.004276 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 63001.740139 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 63001.740139 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 63001.740139 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 63001.740139 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 63001.740139 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 63001.740139 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.icache.writebacks::writebacks 16 # number of writebacks +system.cpu.icache.writebacks::total 16 # number of writebacks +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 862 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 862 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 862 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 862 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 862 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 862 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 53445500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 53445500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 53445500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 53445500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 53445500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 53445500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.004276 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.004276 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.004276 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.004276 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.004276 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.004276 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 62001.740139 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 62001.740139 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 62001.740139 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 62001.740139 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 62001.740139 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 62001.740139 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 352925500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.replacements 0 # number of replacements +system.cpu.l2cache.tags.tagsinuse 708.129693 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 16 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 1149 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.013925 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::cpu.inst 470.314864 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 237.814829 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.014353 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.007258 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.021610 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 1149 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 185 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 912 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.035065 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 10469 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 10469 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 352925500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.WritebackClean_hits::writebacks 16 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 16 # number of WritebackClean hits +system.cpu.l2cache.ReadExReq_misses::cpu.data 212 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 212 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 862 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 862 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 75 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 75 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.inst 862 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 287 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 1149 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 862 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 287 # number of overall misses +system.cpu.l2cache.overall_misses::total 1149 # number of overall misses +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 12826000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 12826000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 52152000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 52152000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 4537500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 4537500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 52152000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 17363500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 69515500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 52152000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 17363500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 69515500 # number of overall miss cycles +system.cpu.l2cache.WritebackClean_accesses::writebacks 16 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 16 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 212 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 212 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 862 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 862 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 75 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 75 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 862 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 287 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 1149 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 862 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 287 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 1149 # number of overall (read+write) accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 1 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 1 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 1 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 1 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60500 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60500 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60501.160093 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60501.160093 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60500 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60500 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60501.160093 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60500 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 60500.870322 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60501.160093 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60500 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 60500.870322 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 212 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 212 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 862 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 862 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 75 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 75 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 862 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 287 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 1149 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 862 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 287 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 1149 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 10706000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 10706000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 43532000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 43532000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 3787500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 3787500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 43532000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 14493500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 58025500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 43532000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 14493500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 58025500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 1 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50501.160093 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50501.160093 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50501.160093 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50500.870322 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50501.160093 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50500.870322 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 1165 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 16 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 352925500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 937 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 16 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 212 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 212 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 862 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 75 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1740 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 574 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 2314 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 56192 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18368 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 74560 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 1149 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 1149 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 1149 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 598500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 1293000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.4 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 430500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) +system.membus.snoop_filter.tot_requests 1149 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 352925500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 937 # Transaction distribution +system.membus.trans_dist::ReadExReq 212 # Transaction distribution +system.membus.trans_dist::ReadExResp 212 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 937 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 2298 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 2298 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 73536 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 73536 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoopTraffic 0 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 1149 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 1149 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 1149 # Request fanout histogram +system.membus.reqLayer0.occupancy 1150000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.3 # Layer utilization (%) +system.membus.respLayer1.occupancy 5745000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 1.6 # Layer utilization (%) + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/minor-timing/config.ini b/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/minor-timing/config.ini new file mode 100644 index 000000000..778748b0c --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/minor-timing/config.ini @@ -0,0 +1,902 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain +boot_osflags=a +cache_line_size=64 +clk_domain=system.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +exit_on_work_items=false +init_param=0 +kernel= +kernel_addr_check=true +load_addr_mask=1099511627775 +load_offset=0 +mem_mode=timing +mem_ranges= +memories=system.physmem +mmap_using_noreserve=false +multi_thread=false +num_work_ids=16 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +readfile= +symbolfile= +thermal_components= +thermal_model=Null +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=MinorCPU +children=branchPred dcache dtb executeFuncUnits icache interrupts isa itb l2cache toL2Bus tracer workload +branchPred=system.cpu.branchPred +checker=Null +clk_domain=system.cpu_clk_domain +cpu_id=0 +decodeCycleInput=true +decodeInputBufferSize=3 +decodeInputWidth=2 +decodeToExecuteForwardDelay=1 +default_p_state=UNDEFINED +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +enableIdling=true +eventq_index=0 +executeAllowEarlyMemoryIssue=true +executeBranchDelay=1 +executeCommitLimit=2 +executeCycleInput=true +executeFuncUnits=system.cpu.executeFuncUnits +executeInputBufferSize=7 +executeInputWidth=2 +executeIssueLimit=2 +executeLSQMaxStoreBufferStoresPerCycle=2 +executeLSQRequestsQueueSize=1 +executeLSQStoreBufferSize=5 +executeLSQTransfersQueueSize=2 +executeMaxAccessesInMemory=2 +executeMemoryCommitLimit=1 +executeMemoryIssueLimit=1 +executeMemoryWidth=0 +executeSetTraceTimeOnCommit=true +executeSetTraceTimeOnIssue=false +fetch1FetchLimit=1 +fetch1LineSnapWidth=0 +fetch1LineWidth=0 +fetch1ToFetch2BackwardDelay=1 +fetch1ToFetch2ForwardDelay=1 +fetch2CycleInput=true +fetch2InputBufferSize=2 +fetch2ToDecodeForwardDelay=1 +function_trace=false +function_trace_start=0 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +profile=0 +progress_interval=0 +simpoint_start_insts= +socket_id=0 +switched_out=false +system=system +threadPolicy=RoundRobin +tracer=system.cpu.tracer +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.branchPred] +type=TournamentBP +BTBEntries=4096 +BTBTagSize=16 +RASSize=16 +choiceCtrBits=2 +choicePredictorSize=8192 +eventq_index=0 +globalCtrBits=2 +globalPredictorSize=8192 +indirectHashGHR=true +indirectHashTargets=true +indirectPathLength=3 +indirectSets=256 +indirectTagSize=16 +indirectWays=2 +instShiftAmt=2 +localCtrBits=2 +localHistoryTableSize=2048 +localPredictorSize=2048 +numThreads=1 +useIndirect=true + +[system.cpu.dcache] +type=Cache +children=tags +addr_ranges=0:18446744073709551615:0:0:0:0 +assoc=2 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +data_latency=2 +default_p_state=UNDEFINED +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=4 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=262144 +system=system +tag_latency=2 +tags=system.cpu.dcache.tags +tgts_per_mshr=20 +write_buffers=8 +writeback_clean=false +cpu_side=system.cpu.dcache_port +mem_side=system.cpu.toL2Bus.slave[1] + +[system.cpu.dcache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +data_latency=2 +default_p_state=UNDEFINED +eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +sequential_access=false +size=262144 +tag_latency=2 + +[system.cpu.dtb] +type=RiscvTLB +eventq_index=0 +size=64 + +[system.cpu.executeFuncUnits] +type=MinorFUPool +children=funcUnits0 funcUnits1 funcUnits2 funcUnits3 funcUnits4 funcUnits5 funcUnits6 +eventq_index=0 +funcUnits=system.cpu.executeFuncUnits.funcUnits0 system.cpu.executeFuncUnits.funcUnits1 system.cpu.executeFuncUnits.funcUnits2 system.cpu.executeFuncUnits.funcUnits3 system.cpu.executeFuncUnits.funcUnits4 system.cpu.executeFuncUnits.funcUnits5 system.cpu.executeFuncUnits.funcUnits6 + +[system.cpu.executeFuncUnits.funcUnits0] +type=MinorFU +children=opClasses timings +cantForwardFromFUIndices= +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses +opLat=3 +timings=system.cpu.executeFuncUnits.funcUnits0.timings + +[system.cpu.executeFuncUnits.funcUnits0.opClasses] +type=MinorOpClassSet +children=opClasses +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses + +[system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses] +type=MinorOpClass +eventq_index=0 +opClass=IntAlu + +[system.cpu.executeFuncUnits.funcUnits0.timings] +type=MinorFUTiming +children=opClasses +description=Int +eventq_index=0 +extraAssumedLat=0 +extraCommitLat=0 +extraCommitLatExpr=Null +mask=0 +match=0 +opClasses=system.cpu.executeFuncUnits.funcUnits0.timings.opClasses +srcRegsRelativeLats=2 +suppress=false + +[system.cpu.executeFuncUnits.funcUnits0.timings.opClasses] +type=MinorOpClassSet +eventq_index=0 +opClasses= + +[system.cpu.executeFuncUnits.funcUnits1] +type=MinorFU +children=opClasses timings +cantForwardFromFUIndices= +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses +opLat=3 +timings=system.cpu.executeFuncUnits.funcUnits1.timings + +[system.cpu.executeFuncUnits.funcUnits1.opClasses] +type=MinorOpClassSet +children=opClasses +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses + +[system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses] +type=MinorOpClass +eventq_index=0 +opClass=IntAlu + +[system.cpu.executeFuncUnits.funcUnits1.timings] +type=MinorFUTiming +children=opClasses +description=Int +eventq_index=0 +extraAssumedLat=0 +extraCommitLat=0 +extraCommitLatExpr=Null +mask=0 +match=0 +opClasses=system.cpu.executeFuncUnits.funcUnits1.timings.opClasses +srcRegsRelativeLats=2 +suppress=false + +[system.cpu.executeFuncUnits.funcUnits1.timings.opClasses] +type=MinorOpClassSet +eventq_index=0 +opClasses= + +[system.cpu.executeFuncUnits.funcUnits2] +type=MinorFU +children=opClasses timings +cantForwardFromFUIndices= +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits2.opClasses +opLat=3 +timings=system.cpu.executeFuncUnits.funcUnits2.timings + +[system.cpu.executeFuncUnits.funcUnits2.opClasses] +type=MinorOpClassSet +children=opClasses +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses + +[system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses] +type=MinorOpClass +eventq_index=0 +opClass=IntMult + +[system.cpu.executeFuncUnits.funcUnits2.timings] +type=MinorFUTiming +children=opClasses +description=Mul +eventq_index=0 +extraAssumedLat=0 +extraCommitLat=0 +extraCommitLatExpr=Null +mask=0 +match=0 +opClasses=system.cpu.executeFuncUnits.funcUnits2.timings.opClasses +srcRegsRelativeLats=0 +suppress=false + +[system.cpu.executeFuncUnits.funcUnits2.timings.opClasses] +type=MinorOpClassSet +eventq_index=0 +opClasses= + +[system.cpu.executeFuncUnits.funcUnits3] +type=MinorFU +children=opClasses +cantForwardFromFUIndices= +eventq_index=0 +issueLat=9 +opClasses=system.cpu.executeFuncUnits.funcUnits3.opClasses +opLat=9 +timings= + +[system.cpu.executeFuncUnits.funcUnits3.opClasses] +type=MinorOpClassSet +children=opClasses +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses + +[system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses] +type=MinorOpClass +eventq_index=0 +opClass=IntDiv + +[system.cpu.executeFuncUnits.funcUnits4] +type=MinorFU +children=opClasses timings +cantForwardFromFUIndices= +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses +opLat=6 +timings=system.cpu.executeFuncUnits.funcUnits4.timings + +[system.cpu.executeFuncUnits.funcUnits4.opClasses] +type=MinorOpClassSet +children=opClasses00 opClasses01 opClasses02 opClasses03 opClasses04 opClasses05 opClasses06 opClasses07 opClasses08 opClasses09 opClasses10 opClasses11 opClasses12 opClasses13 opClasses14 opClasses15 opClasses16 opClasses17 opClasses18 opClasses19 opClasses20 opClasses21 opClasses22 opClasses23 opClasses24 opClasses25 opClasses26 opClasses27 +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses26 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses27 + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00] +type=MinorOpClass +eventq_index=0 +opClass=FloatAdd + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01] +type=MinorOpClass +eventq_index=0 +opClass=FloatCmp + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02] +type=MinorOpClass +eventq_index=0 +opClass=FloatCvt + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03] +type=MinorOpClass +eventq_index=0 +opClass=FloatMisc + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04] +type=MinorOpClass +eventq_index=0 +opClass=FloatMult + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05] +type=MinorOpClass +eventq_index=0 +opClass=FloatMultAcc + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06] +type=MinorOpClass +eventq_index=0 +opClass=FloatDiv + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07] +type=MinorOpClass +eventq_index=0 +opClass=FloatSqrt + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08] +type=MinorOpClass +eventq_index=0 +opClass=SimdAdd + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09] +type=MinorOpClass +eventq_index=0 +opClass=SimdAddAcc + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10] +type=MinorOpClass +eventq_index=0 +opClass=SimdAlu + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11] +type=MinorOpClass +eventq_index=0 +opClass=SimdCmp + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12] +type=MinorOpClass +eventq_index=0 +opClass=SimdCvt + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13] +type=MinorOpClass +eventq_index=0 +opClass=SimdMisc + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14] +type=MinorOpClass +eventq_index=0 +opClass=SimdMult + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15] +type=MinorOpClass +eventq_index=0 +opClass=SimdMultAcc + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16] +type=MinorOpClass +eventq_index=0 +opClass=SimdShift + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17] +type=MinorOpClass +eventq_index=0 +opClass=SimdShiftAcc + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18] +type=MinorOpClass +eventq_index=0 +opClass=SimdSqrt + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatAdd + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatAlu + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatCmp + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatCvt + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatDiv + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatMisc + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatMult + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses26] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatMultAcc + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses27] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatSqrt + +[system.cpu.executeFuncUnits.funcUnits4.timings] +type=MinorFUTiming +children=opClasses +description=FloatSimd +eventq_index=0 +extraAssumedLat=0 +extraCommitLat=0 +extraCommitLatExpr=Null +mask=0 +match=0 +opClasses=system.cpu.executeFuncUnits.funcUnits4.timings.opClasses +srcRegsRelativeLats=2 +suppress=false + +[system.cpu.executeFuncUnits.funcUnits4.timings.opClasses] +type=MinorOpClassSet +eventq_index=0 +opClasses= + +[system.cpu.executeFuncUnits.funcUnits5] +type=MinorFU +children=opClasses timings +cantForwardFromFUIndices= +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses +opLat=1 +timings=system.cpu.executeFuncUnits.funcUnits5.timings + +[system.cpu.executeFuncUnits.funcUnits5.opClasses] +type=MinorOpClassSet +children=opClasses0 opClasses1 opClasses2 opClasses3 +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1 system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses2 system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses3 + +[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0] +type=MinorOpClass +eventq_index=0 +opClass=MemRead + +[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1] +type=MinorOpClass +eventq_index=0 +opClass=MemWrite + +[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses2] +type=MinorOpClass +eventq_index=0 +opClass=FloatMemRead + +[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses3] +type=MinorOpClass +eventq_index=0 +opClass=FloatMemWrite + +[system.cpu.executeFuncUnits.funcUnits5.timings] +type=MinorFUTiming +children=opClasses +description=Mem +eventq_index=0 +extraAssumedLat=2 +extraCommitLat=0 +extraCommitLatExpr=Null +mask=0 +match=0 +opClasses=system.cpu.executeFuncUnits.funcUnits5.timings.opClasses +srcRegsRelativeLats=1 +suppress=false + +[system.cpu.executeFuncUnits.funcUnits5.timings.opClasses] +type=MinorOpClassSet +eventq_index=0 +opClasses= + +[system.cpu.executeFuncUnits.funcUnits6] +type=MinorFU +children=opClasses +cantForwardFromFUIndices= +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses +opLat=1 +timings= + +[system.cpu.executeFuncUnits.funcUnits6.opClasses] +type=MinorOpClassSet +children=opClasses0 opClasses1 +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1 + +[system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0] +type=MinorOpClass +eventq_index=0 +opClass=IprAccess + +[system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1] +type=MinorOpClass +eventq_index=0 +opClass=InstPrefetch + +[system.cpu.icache] +type=Cache +children=tags +addr_ranges=0:18446744073709551615:0:0:0:0 +assoc=2 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +data_latency=2 +default_p_state=UNDEFINED +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=true +max_miss_count=0 +mshrs=4 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=131072 +system=system +tag_latency=2 +tags=system.cpu.icache.tags +tgts_per_mshr=20 +write_buffers=8 +writeback_clean=true +cpu_side=system.cpu.icache_port +mem_side=system.cpu.toL2Bus.slave[0] + +[system.cpu.icache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +data_latency=2 +default_p_state=UNDEFINED +eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +sequential_access=false +size=131072 +tag_latency=2 + +[system.cpu.interrupts] +type=RiscvInterrupts +eventq_index=0 + +[system.cpu.isa] +type=RiscvISA +eventq_index=0 + +[system.cpu.itb] +type=RiscvTLB +eventq_index=0 +size=64 + +[system.cpu.l2cache] +type=Cache +children=tags +addr_ranges=0:18446744073709551615:0:0:0:0 +assoc=8 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +data_latency=20 +default_p_state=UNDEFINED +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=20 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +prefetch_on_access=false +prefetcher=Null +response_latency=20 +sequential_access=false +size=2097152 +system=system +tag_latency=20 +tags=system.cpu.l2cache.tags +tgts_per_mshr=12 +write_buffers=8 +writeback_clean=false +cpu_side=system.cpu.toL2Bus.master[0] +mem_side=system.membus.slave[1] + +[system.cpu.l2cache.tags] +type=LRU +assoc=8 +block_size=64 +clk_domain=system.cpu_clk_domain +data_latency=20 +default_p_state=UNDEFINED +eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +sequential_access=false +size=2097152 +tag_latency=20 + +[system.cpu.toL2Bus] +type=CoherentXBar +children=snoop_filter +clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED +eventq_index=0 +forward_latency=0 +frontend_latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +point_of_coherency=false +power_model=Null +response_latency=1 +snoop_filter=system.cpu.toL2Bus.snoop_filter +snoop_response_latency=1 +system=system +use_default_range=false +width=32 +master=system.cpu.l2cache.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side + +[system.cpu.toL2Bus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=0 +max_capacity=8388608 +system=system + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=LiveProcess +cmd=insttest +cwd= +drivers= +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable=/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64m/insttest +gid=100 +input=cin +kvmInSE=false +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=0 +system=system +uid=100 +useArchPT=false + +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000000 + +[system.membus] +type=CoherentXBar +children=snoop_filter +clk_domain=system.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +forward_latency=4 +frontend_latency=3 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +point_of_coherency=true +power_model=Null +response_latency=2 +snoop_filter=system.membus.snoop_filter +snoop_response_latency=4 +system=system +use_default_range=false +width=16 +master=system.physmem.port +slave=system.system_port system.cpu.l2cache.mem_side + +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + +[system.physmem] +type=DRAMCtrl +IDD0=0.055000 +IDD02=0.000000 +IDD2N=0.032000 +IDD2N2=0.000000 +IDD2P0=0.000000 +IDD2P02=0.000000 +IDD2P1=0.032000 +IDD2P12=0.000000 +IDD3N=0.038000 +IDD3N2=0.000000 +IDD3P0=0.000000 +IDD3P02=0.000000 +IDD3P1=0.038000 +IDD3P12=0.000000 +IDD4R=0.157000 +IDD4R2=0.000000 +IDD4W=0.125000 +IDD4W2=0.000000 +IDD5=0.235000 +IDD52=0.000000 +IDD6=0.020000 +IDD62=0.000000 +VDD=1.500000 +VDD2=0.000000 +activation_limit=4 +addr_mapping=RoRaBaCoCh +bank_groups_per_rank=0 +banks_per_rank=8 +burst_length=8 +channels=1 +clk_domain=system.clk_domain +conf_table_reported=true +default_p_state=UNDEFINED +device_bus_width=8 +device_rowbuffer_size=1024 +device_size=536870912 +devices_per_rank=8 +dll=true +eventq_index=0 +in_addr_map=true +kvm_map=true +max_accesses_per_row=16 +mem_sched_policy=frfcfs +min_writes_per_switch=16 +null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +page_policy=open_adaptive +power_model=Null +range=0:134217727:0:0:0:0 +ranks_per_channel=2 +read_buffer_size=32 +static_backend_latency=10000 +static_frontend_latency=10000 +tBURST=5000 +tCCD_L=0 +tCK=1250 +tCL=13750 +tCS=2500 +tRAS=35000 +tRCD=13750 +tREFI=7800000 +tRFC=260000 +tRP=13750 +tRRD=6000 +tRRD_L=0 +tRTP=7500 +tRTW=2500 +tWR=15000 +tWTR=7500 +tXAW=30000 +tXP=6000 +tXPDLL=0 +tXS=270000 +tXSDLL=0 +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 +port=system.membus.master[0] + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/minor-timing/config.json b/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/minor-timing/config.json new file mode 100644 index 000000000..c05fef680 --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/minor-timing/config.json @@ -0,0 +1,1211 @@ +{ + "name": null, + "sim_quantum": 0, + "system": { + "kernel": "", + "mmap_using_noreserve": false, + "kernel_addr_check": true, + "membus": { + "point_of_coherency": true, + "system": "system", + "response_latency": 2, + "cxx_class": "CoherentXBar", + "forward_latency": 4, + "clk_domain": "system.clk_domain", + "width": 16, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "master": { + "peer": [ + "system.physmem.port" + ], + "role": "MASTER" + }, + "type": "CoherentXBar", + "frontend_latency": 3, + "slave": { + "peer": [ + "system.system_port", + "system.cpu.l2cache.mem_side" + ], + "role": "SLAVE" + }, + "p_state_clk_gate_min": 1000, + "snoop_filter": { + "name": "snoop_filter", + "system": "system", + "max_capacity": 8388608, + "eventq_index": 0, + "cxx_class": "SnoopFilter", + "path": "system.membus.snoop_filter", + "type": "SnoopFilter", + "lookup_latency": 1 + }, + "power_model": null, + "path": "system.membus", + "snoop_response_latency": 4, + "name": "membus", + "p_state_clk_gate_bins": 20, + "use_default_range": false + }, + "symbolfile": "", + "readfile": "", + "thermal_model": null, + "cxx_class": "System", + "work_begin_cpu_id_exit": -1, + "load_offset": 0, + "work_begin_exit_count": 0, + "p_state_clk_gate_min": 1000, + "memories": [ + "system.physmem" + ], + "work_begin_ckpt_count": 0, + "clk_domain": { + "name": "clk_domain", + "clock": [ + 1000 + ], + "init_perf_level": 0, + "voltage_domain": "system.voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "mem_ranges": [], + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "dvfs_handler": { + "enable": false, + "name": "dvfs_handler", + "sys_clk_domain": "system.clk_domain", + "transition_latency": 100000000, + "eventq_index": 0, + "cxx_class": "DVFSHandler", + "domains": [], + "path": "system.dvfs_handler", + "type": "DVFSHandler" + }, + "work_end_exit_count": 0, + "type": "System", + "voltage_domain": { + "name": "voltage_domain", + "eventq_index": 0, + "voltage": [ + "1.0" + ], + "cxx_class": "VoltageDomain", + "path": "system.voltage_domain", + "type": "VoltageDomain" + }, + "cache_line_size": 64, + "boot_osflags": "a", + "system_port": { + "peer": "system.membus.slave[0]", + "role": "MASTER" + }, + "physmem": { + "static_frontend_latency": 10000, + "tRFC": 260000, + "activation_limit": 4, + "in_addr_map": true, + "IDD3N2": "0.0", + "tWTR": 7500, + "IDD52": "0.0", + "clk_domain": "system.clk_domain", + "channels": 1, + "write_buffer_size": 64, + "device_bus_width": 8, + "VDD": "1.5", + "write_high_thresh_perc": 85, + "cxx_class": "DRAMCtrl", + "bank_groups_per_rank": 0, + "IDD2N2": "0.0", + "port": { + "peer": "system.membus.master[0]", + "role": "SLAVE" + }, + "tCCD_L": 0, + "IDD2N": "0.032", + "p_state_clk_gate_min": 1000, + "null": false, + "IDD2P1": "0.032", + "eventq_index": 0, + "tRRD": 6000, + "tRTW": 2500, + "IDD4R": "0.157", + "burst_length": 8, + "tRTP": 7500, + "IDD4W": "0.125", + "tWR": 15000, + "banks_per_rank": 8, + "devices_per_rank": 8, + "IDD2P02": "0.0", + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "IDD6": "0.02", + "IDD5": "0.235", + "tRCD": 13750, + "type": "DRAMCtrl", + "IDD3P02": "0.0", + "tRRD_L": 0, + "IDD0": "0.055", + "IDD62": "0.0", + "min_writes_per_switch": 16, + "mem_sched_policy": "frfcfs", + "IDD02": "0.0", + "IDD2P0": "0.0", + "ranks_per_channel": 2, + "page_policy": "open_adaptive", + "IDD4W2": "0.0", + "tCS": 2500, + "power_model": null, + "tCL": 13750, + "read_buffer_size": 32, + "conf_table_reported": true, + "tCK": 1250, + "tRAS": 35000, + "tRP": 13750, + "tBURST": 5000, + "path": "system.physmem", + "tXP": 6000, + "tXS": 270000, + "addr_mapping": "RoRaBaCoCh", + "IDD3P0": "0.0", + "IDD3P1": "0.038", + "IDD3N": "0.038", + "name": "physmem", + "tXSDLL": 0, + "device_size": 536870912, + "kvm_map": true, + "dll": true, + "tXAW": 30000, + "write_low_thresh_perc": 50, + "range": "0:134217727:0:0:0:0", + "VDD2": "0.0", + "IDD2P12": "0.0", + "p_state_clk_gate_bins": 20, + "tXPDLL": 0, + "IDD4R2": "0.0", + "device_rowbuffer_size": 1024, + "static_backend_latency": 10000, + "max_accesses_per_row": 16, + "IDD3P12": "0.0", + "tREFI": 7800000 + }, + "power_model": null, + "work_cpus_ckpt_count": 0, + "thermal_components": [], + "path": "system", + "cpu_clk_domain": { + "name": "cpu_clk_domain", + "clock": [ + 500 + ], + "init_perf_level": 0, + "voltage_domain": "system.voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.cpu_clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "work_end_ckpt_count": 0, + "mem_mode": "timing", + "name": "system", + "init_param": 0, + "p_state_clk_gate_bins": 20, + "load_addr_mask": 1099511627775, + "cpu": [ + { + "max_insts_any_thread": 0, + "do_statistics_insts": true, + "numThreads": 1, + "fetch1LineSnapWidth": 0, + "fetch1ToFetch2BackwardDelay": 1, + "fetch1FetchLimit": 1, + "executeIssueLimit": 2, + "system": "system", + "executeLSQMaxStoreBufferStoresPerCycle": 2, + "icache": { + "cpu_side": { + "peer": "system.cpu.icache_port", + "role": "SLAVE" + }, + "clusivity": "mostly_incl", + "prefetcher": null, + "system": "system", + "write_buffers": 8, + "response_latency": 2, + "cxx_class": "Cache", + "size": 131072, + "type": "Cache", + "clk_domain": "system.cpu_clk_domain", + "max_miss_count": 0, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "mem_side": { + "peer": "system.cpu.toL2Bus.slave[0]", + "role": "MASTER" + }, + "mshrs": 4, + "writeback_clean": true, + "p_state_clk_gate_min": 1000, + "tags": { + "size": 131072, + "tag_latency": 2, + "name": "tags", + "p_state_clk_gate_min": 1000, + "eventq_index": 0, + "p_state_clk_gate_bins": 20, + "default_p_state": "UNDEFINED", + "clk_domain": "system.cpu_clk_domain", + "power_model": null, + "sequential_access": false, + "assoc": 2, + "cxx_class": "LRU", + "p_state_clk_gate_max": 1000000000000, + "path": "system.cpu.icache.tags", + "block_size": 64, + "type": "LRU", + "data_latency": 2 + }, + "tgts_per_mshr": 20, + "demand_mshr_reserve": 1, + "power_model": null, + "addr_ranges": [ + "0:18446744073709551615:0:0:0:0" + ], + "is_read_only": true, + "prefetch_on_access": false, + "path": "system.cpu.icache", + "data_latency": 2, + "tag_latency": 2, + "name": "icache", + "p_state_clk_gate_bins": 20, + "sequential_access": false, + "assoc": 2 + }, + "function_trace": false, + "do_checkpoint_insts": true, + "decodeInputWidth": 2, + "cxx_class": "MinorCPU", + "max_loads_all_threads": 0, + "executeMemoryIssueLimit": 1, + "decodeCycleInput": true, + "max_loads_any_thread": 0, + "executeLSQTransfersQueueSize": 2, + "p_state_clk_gate_max": 1000000000000, + "clk_domain": "system.cpu_clk_domain", + "function_trace_start": 0, + "cpu_id": 0, + "checker": null, + "eventq_index": 0, + "executeMemoryWidth": 0, + "default_p_state": "UNDEFINED", + "executeBranchDelay": 1, + "executeMemoryCommitLimit": 1, + "l2cache": { + "cpu_side": { + "peer": "system.cpu.toL2Bus.master[0]", + "role": "SLAVE" + }, + "clusivity": "mostly_incl", + "prefetcher": null, + "system": "system", + "write_buffers": 8, + "response_latency": 20, + "cxx_class": "Cache", + "size": 2097152, + "type": "Cache", + "clk_domain": "system.cpu_clk_domain", + "max_miss_count": 0, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "mem_side": { + "peer": "system.membus.slave[1]", + "role": "MASTER" + }, + "mshrs": 20, + "writeback_clean": false, + "p_state_clk_gate_min": 1000, + "tags": { + "size": 2097152, + "tag_latency": 20, + "name": "tags", + "p_state_clk_gate_min": 1000, + "eventq_index": 0, + "p_state_clk_gate_bins": 20, + "default_p_state": "UNDEFINED", + "clk_domain": "system.cpu_clk_domain", + "power_model": null, + "sequential_access": false, + "assoc": 8, + "cxx_class": "LRU", + "p_state_clk_gate_max": 1000000000000, + "path": "system.cpu.l2cache.tags", + "block_size": 64, + "type": "LRU", + "data_latency": 20 + }, + "tgts_per_mshr": 12, + "demand_mshr_reserve": 1, + "power_model": null, + "addr_ranges": [ + "0:18446744073709551615:0:0:0:0" + ], + "is_read_only": false, + "prefetch_on_access": false, + "path": "system.cpu.l2cache", + "data_latency": 20, + "tag_latency": 20, + "name": "l2cache", + "p_state_clk_gate_bins": 20, + "sequential_access": false, + "assoc": 8 + }, + "do_quiesce": true, + "type": "MinorCPU", + "executeCycleInput": true, + "executeAllowEarlyMemoryIssue": true, + "executeInputBufferSize": 7, + "icache_port": { + "peer": "system.cpu.icache.cpu_side", + "role": "MASTER" + }, + "p_state_clk_gate_bins": 20, + "socket_id": 0, + "progress_interval": 0, + "p_state_clk_gate_min": 1000, + "toL2Bus": { + "point_of_coherency": false, + "system": "system", + "response_latency": 1, + "cxx_class": "CoherentXBar", + "forward_latency": 0, + "clk_domain": "system.cpu_clk_domain", + "width": 32, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "master": { + "peer": [ + "system.cpu.l2cache.cpu_side" + ], + "role": "MASTER" + }, + "type": "CoherentXBar", + "frontend_latency": 1, + "slave": { + "peer": [ + "system.cpu.icache.mem_side", + "system.cpu.dcache.mem_side" + ], + "role": "SLAVE" + }, + "p_state_clk_gate_min": 1000, + "snoop_filter": { + "name": "snoop_filter", + "system": "system", + "max_capacity": 8388608, + "eventq_index": 0, + "cxx_class": "SnoopFilter", + "path": "system.cpu.toL2Bus.snoop_filter", + "type": "SnoopFilter", + "lookup_latency": 0 + }, + "power_model": null, + "path": "system.cpu.toL2Bus", + "snoop_response_latency": 1, + "name": "toL2Bus", + "p_state_clk_gate_bins": 20, + "use_default_range": false + }, + "isa": [ + { + "eventq_index": 0, + "path": "system.cpu.isa", + "type": "RiscvISA", + "name": "isa", + "cxx_class": "RiscvISA::ISA" + } + ], + "itb": { + "name": "itb", + "eventq_index": 0, + "cxx_class": "RiscvISA::TLB", + "path": "system.cpu.itb", + "type": "RiscvTLB", + "size": 64 + }, + "interrupts": [ + { + "eventq_index": 0, + "path": "system.cpu.interrupts", + "type": "RiscvInterrupts", + "name": "interrupts", + "cxx_class": "RiscvISA::Interrupts" + } + ], + "dcache_port": { + "peer": "system.cpu.dcache.cpu_side", + "role": "MASTER" + }, + "executeFuncUnits": { + "name": "executeFuncUnits", + "eventq_index": 0, + "cxx_class": "MinorFUPool", + "path": "system.cpu.executeFuncUnits", + "funcUnits": [ + { + "issueLat": 1, + "opLat": 3, + "name": "funcUnits0", + "cantForwardFromFUIndices": [], + "opClasses": { + "name": "opClasses", + "opClasses": [ + { + "opClass": "IntAlu", + "name": "opClasses", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses", + "type": "MinorOpClass" + } + ], + "eventq_index": 0, + "cxx_class": "MinorOpClassSet", + "path": "system.cpu.executeFuncUnits.funcUnits0.opClasses", + "type": "MinorOpClassSet" + }, + "eventq_index": 0, + "timings": [ + { + "extraAssumedLat": 0, + "description": "Int", + "srcRegsRelativeLats": [ + 2 + ], + "suppress": false, + "mask": 0, + "extraCommitLat": 0, + "eventq_index": 0, + "opClasses": { + "name": "opClasses", + "opClasses": [], + "eventq_index": 0, + "cxx_class": "MinorOpClassSet", + "path": "system.cpu.executeFuncUnits.funcUnits0.timings.opClasses", + "type": "MinorOpClassSet" + }, + "cxx_class": "MinorFUTiming", + "path": "system.cpu.executeFuncUnits.funcUnits0.timings", + "extraCommitLatExpr": null, + "type": "MinorFUTiming", + "match": 0, + "name": "timings" + } + ], + "cxx_class": "MinorFU", + "path": "system.cpu.executeFuncUnits.funcUnits0", + "type": "MinorFU" + }, + { + "issueLat": 1, + "opLat": 3, + "name": "funcUnits1", + "cantForwardFromFUIndices": [], + "opClasses": { + "name": "opClasses", + "opClasses": [ + { + "opClass": "IntAlu", + "name": "opClasses", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses", + "type": "MinorOpClass" + } + ], + "eventq_index": 0, + "cxx_class": "MinorOpClassSet", + "path": "system.cpu.executeFuncUnits.funcUnits1.opClasses", + "type": "MinorOpClassSet" + }, + "eventq_index": 0, + "timings": [ + { + "extraAssumedLat": 0, + "description": "Int", + "srcRegsRelativeLats": [ + 2 + ], + "suppress": false, + "mask": 0, + "extraCommitLat": 0, + "eventq_index": 0, + "opClasses": { + "name": "opClasses", + "opClasses": [], + "eventq_index": 0, + "cxx_class": "MinorOpClassSet", + "path": "system.cpu.executeFuncUnits.funcUnits1.timings.opClasses", + "type": "MinorOpClassSet" + }, + "cxx_class": "MinorFUTiming", + "path": "system.cpu.executeFuncUnits.funcUnits1.timings", + "extraCommitLatExpr": null, + "type": "MinorFUTiming", + "match": 0, + "name": "timings" + } + ], + "cxx_class": "MinorFU", + "path": "system.cpu.executeFuncUnits.funcUnits1", + "type": "MinorFU" + }, + { + "issueLat": 1, + "opLat": 3, + "name": "funcUnits2", + "cantForwardFromFUIndices": [], + "opClasses": { + "name": "opClasses", + "opClasses": [ + { + "opClass": "IntMult", + "name": "opClasses", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses", + "type": "MinorOpClass" + } + ], + "eventq_index": 0, + "cxx_class": "MinorOpClassSet", + "path": "system.cpu.executeFuncUnits.funcUnits2.opClasses", + "type": "MinorOpClassSet" + }, + "eventq_index": 0, + "timings": [ + { + "extraAssumedLat": 0, + "description": "Mul", + "srcRegsRelativeLats": [ + 0 + ], + "suppress": false, + "mask": 0, + "extraCommitLat": 0, + "eventq_index": 0, + "opClasses": { + "name": "opClasses", + "opClasses": [], + "eventq_index": 0, + "cxx_class": "MinorOpClassSet", + "path": "system.cpu.executeFuncUnits.funcUnits2.timings.opClasses", + "type": "MinorOpClassSet" + }, + "cxx_class": "MinorFUTiming", + "path": "system.cpu.executeFuncUnits.funcUnits2.timings", + "extraCommitLatExpr": null, + "type": "MinorFUTiming", + "match": 0, + "name": "timings" + } + ], + "cxx_class": "MinorFU", + "path": "system.cpu.executeFuncUnits.funcUnits2", + "type": "MinorFU" + }, + { + "issueLat": 9, + "opLat": 9, + "name": "funcUnits3", + "cantForwardFromFUIndices": [], + "opClasses": { + "name": "opClasses", + "opClasses": [ + { + "opClass": "IntDiv", + "name": "opClasses", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses", + "type": "MinorOpClass" + } + ], + "eventq_index": 0, + "cxx_class": "MinorOpClassSet", + "path": "system.cpu.executeFuncUnits.funcUnits3.opClasses", + "type": "MinorOpClassSet" + }, + "eventq_index": 0, + "timings": [], + "cxx_class": "MinorFU", + "path": "system.cpu.executeFuncUnits.funcUnits3", + "type": "MinorFU" + }, + { + "issueLat": 1, + "opLat": 6, + "name": "funcUnits4", + "cantForwardFromFUIndices": [], + "opClasses": { + "name": "opClasses", + "opClasses": [ + { + "opClass": "FloatAdd", + "name": "opClasses00", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00", + "type": "MinorOpClass" + }, + { + "opClass": "FloatCmp", + "name": "opClasses01", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01", + "type": "MinorOpClass" + }, + { + "opClass": "FloatCvt", + "name": "opClasses02", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02", + "type": "MinorOpClass" + }, + { + "opClass": "FloatMisc", + "name": "opClasses03", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03", + "type": "MinorOpClass" + }, + { + "opClass": "FloatMult", + "name": "opClasses04", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04", + "type": "MinorOpClass" + }, + { + "opClass": "FloatMultAcc", + "name": "opClasses05", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05", + "type": "MinorOpClass" + }, + { + "opClass": "FloatDiv", + "name": "opClasses06", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06", + "type": "MinorOpClass" + }, + { + "opClass": "FloatSqrt", + "name": "opClasses07", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07", + "type": "MinorOpClass" + }, + { + "opClass": "SimdAdd", + "name": "opClasses08", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08", + "type": "MinorOpClass" + }, + { + "opClass": "SimdAddAcc", + "name": "opClasses09", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09", + "type": "MinorOpClass" + }, + { + "opClass": "SimdAlu", + "name": "opClasses10", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10", + "type": "MinorOpClass" + }, + { + "opClass": "SimdCmp", + "name": "opClasses11", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11", + "type": "MinorOpClass" + }, + { + "opClass": "SimdCvt", + "name": "opClasses12", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12", + "type": "MinorOpClass" + }, + { + "opClass": "SimdMisc", + "name": "opClasses13", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13", + "type": "MinorOpClass" + }, + { + "opClass": "SimdMult", + "name": "opClasses14", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14", + "type": "MinorOpClass" + }, + { + "opClass": "SimdMultAcc", + "name": "opClasses15", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15", + "type": "MinorOpClass" + }, + { + "opClass": "SimdShift", + "name": "opClasses16", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16", + "type": "MinorOpClass" + }, + { + "opClass": "SimdShiftAcc", + "name": "opClasses17", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17", + "type": "MinorOpClass" + }, + { + "opClass": "SimdSqrt", + "name": "opClasses18", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18", + "type": "MinorOpClass" + }, + { + "opClass": "SimdFloatAdd", + "name": "opClasses19", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19", + "type": "MinorOpClass" + }, + { + "opClass": "SimdFloatAlu", + "name": "opClasses20", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20", + "type": "MinorOpClass" + }, + { + "opClass": "SimdFloatCmp", + "name": "opClasses21", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21", + "type": "MinorOpClass" + }, + { + "opClass": "SimdFloatCvt", + "name": "opClasses22", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22", + "type": "MinorOpClass" + }, + { + "opClass": "SimdFloatDiv", + "name": "opClasses23", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23", + "type": "MinorOpClass" + }, + { + "opClass": "SimdFloatMisc", + "name": "opClasses24", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24", + "type": "MinorOpClass" + }, + { + "opClass": "SimdFloatMult", + "name": "opClasses25", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25", + "type": "MinorOpClass" + }, + { + "opClass": "SimdFloatMultAcc", + "name": "opClasses26", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses26", + "type": "MinorOpClass" + }, + { + "opClass": "SimdFloatSqrt", + "name": "opClasses27", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses27", + "type": "MinorOpClass" + } + ], + "eventq_index": 0, + "cxx_class": "MinorOpClassSet", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses", + "type": "MinorOpClassSet" + }, + "eventq_index": 0, + "timings": [ + { + "extraAssumedLat": 0, + "description": "FloatSimd", + "srcRegsRelativeLats": [ + 2 + ], + "suppress": false, + "mask": 0, + "extraCommitLat": 0, + "eventq_index": 0, + "opClasses": { + "name": "opClasses", + "opClasses": [], + "eventq_index": 0, + "cxx_class": "MinorOpClassSet", + "path": "system.cpu.executeFuncUnits.funcUnits4.timings.opClasses", + "type": "MinorOpClassSet" + }, + "cxx_class": "MinorFUTiming", + "path": "system.cpu.executeFuncUnits.funcUnits4.timings", + "extraCommitLatExpr": null, + "type": "MinorFUTiming", + "match": 0, + "name": "timings" + } + ], + "cxx_class": "MinorFU", + "path": "system.cpu.executeFuncUnits.funcUnits4", + "type": "MinorFU" + }, + { + "issueLat": 1, + "opLat": 1, + "name": "funcUnits5", + "cantForwardFromFUIndices": [], + "opClasses": { + "name": "opClasses", + "opClasses": [ + { + "opClass": "MemRead", + "name": "opClasses0", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0", + "type": "MinorOpClass" + }, + { + "opClass": "MemWrite", + "name": "opClasses1", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1", + "type": "MinorOpClass" + }, + { + "opClass": "FloatMemRead", + "name": "opClasses2", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses2", + "type": "MinorOpClass" + }, + { + "opClass": "FloatMemWrite", + "name": "opClasses3", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses3", + "type": "MinorOpClass" + } + ], + "eventq_index": 0, + "cxx_class": "MinorOpClassSet", + "path": "system.cpu.executeFuncUnits.funcUnits5.opClasses", + "type": "MinorOpClassSet" + }, + "eventq_index": 0, + "timings": [ + { + "extraAssumedLat": 2, + "description": "Mem", + "srcRegsRelativeLats": [ + 1 + ], + "suppress": false, + "mask": 0, + "extraCommitLat": 0, + "eventq_index": 0, + "opClasses": { + "name": "opClasses", + "opClasses": [], + "eventq_index": 0, + "cxx_class": "MinorOpClassSet", + "path": "system.cpu.executeFuncUnits.funcUnits5.timings.opClasses", + "type": "MinorOpClassSet" + }, + "cxx_class": "MinorFUTiming", + "path": "system.cpu.executeFuncUnits.funcUnits5.timings", + "extraCommitLatExpr": null, + "type": "MinorFUTiming", + "match": 0, + "name": "timings" + } + ], + "cxx_class": "MinorFU", + "path": "system.cpu.executeFuncUnits.funcUnits5", + "type": "MinorFU" + }, + { + "issueLat": 1, + "opLat": 1, + "name": "funcUnits6", + "cantForwardFromFUIndices": [], + "opClasses": { + "name": "opClasses", + "opClasses": [ + { + "opClass": "IprAccess", + "name": "opClasses0", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0", + "type": "MinorOpClass" + }, + { + "opClass": "InstPrefetch", + "name": "opClasses1", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1", + "type": "MinorOpClass" + } + ], + "eventq_index": 0, + "cxx_class": "MinorOpClassSet", + "path": "system.cpu.executeFuncUnits.funcUnits6.opClasses", + "type": "MinorOpClassSet" + }, + "eventq_index": 0, + "timings": [], + "cxx_class": "MinorFU", + "path": "system.cpu.executeFuncUnits.funcUnits6", + "type": "MinorFU" + } + ], + "type": "MinorFUPool" + }, + "switched_out": false, + "power_model": null, + "max_insts_all_threads": 0, + "executeSetTraceTimeOnIssue": false, + "fetch2InputBufferSize": 2, + "profile": 0, + "fetch2ToDecodeForwardDelay": 1, + "executeInputWidth": 2, + "decodeToExecuteForwardDelay": 1, + "executeLSQRequestsQueueSize": 1, + "fetch2CycleInput": true, + "executeMaxAccessesInMemory": 2, + "enableIdling": true, + "executeLSQStoreBufferSize": 5, + "workload": [ + { + "uid": 100, + "pid": 100, + "kvmInSE": false, + "cxx_class": "LiveProcess", + "executable": "/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64m/insttest", + "drivers": [], + "system": "system", + "gid": 100, + "eventq_index": 0, + "env": [], + "input": "cin", + "ppid": 99, + "type": "LiveProcess", + "cwd": "", + "simpoint": 0, + "euid": 100, + "path": "system.cpu.workload", + "max_stack_size": 67108864, + "name": "workload", + "cmd": [ + "insttest" + ], + "errout": "cerr", + "useArchPT": false, + "egid": 100, + "output": "cout" + } + ], + "name": "cpu", + "dtb": { + "name": "dtb", + "eventq_index": 0, + "cxx_class": "RiscvISA::TLB", + "path": "system.cpu.dtb", + "type": "RiscvTLB", + "size": 64 + }, + "simpoint_start_insts": [], + "executeSetTraceTimeOnCommit": true, + "tracer": { + "eventq_index": 0, + "path": "system.cpu.tracer", + "type": "ExeTracer", + "name": "tracer", + "cxx_class": "Trace::ExeTracer" + }, + "threadPolicy": "RoundRobin", + "executeCommitLimit": 2, + "fetch1LineWidth": 0, + "branchPred": { + "numThreads": 1, + "BTBEntries": 4096, + "cxx_class": "TournamentBP", + "indirectPathLength": 3, + "globalCtrBits": 2, + "choicePredictorSize": 8192, + "indirectHashGHR": true, + "eventq_index": 0, + "localHistoryTableSize": 2048, + "type": "TournamentBP", + "indirectSets": 256, + "indirectWays": 2, + "choiceCtrBits": 2, + "useIndirect": true, + "localCtrBits": 2, + "path": "system.cpu.branchPred", + "localPredictorSize": 2048, + "RASSize": 16, + "globalPredictorSize": 8192, + "name": "branchPred", + "indirectHashTargets": true, + "instShiftAmt": 2, + "indirectTagSize": 16, + "BTBTagSize": 16 + }, + "dcache": { + "cpu_side": { + "peer": "system.cpu.dcache_port", + "role": "SLAVE" + }, + "clusivity": "mostly_incl", + "prefetcher": null, + "system": "system", + "write_buffers": 8, + "response_latency": 2, + "cxx_class": "Cache", + "size": 262144, + "type": "Cache", + "clk_domain": "system.cpu_clk_domain", + "max_miss_count": 0, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "mem_side": { + "peer": "system.cpu.toL2Bus.slave[1]", + "role": "MASTER" + }, + "mshrs": 4, + "writeback_clean": false, + "p_state_clk_gate_min": 1000, + "tags": { + "size": 262144, + "tag_latency": 2, + "name": "tags", + "p_state_clk_gate_min": 1000, + "eventq_index": 0, + "p_state_clk_gate_bins": 20, + "default_p_state": "UNDEFINED", + "clk_domain": "system.cpu_clk_domain", + "power_model": null, + "sequential_access": false, + "assoc": 2, + "cxx_class": "LRU", + "p_state_clk_gate_max": 1000000000000, + "path": "system.cpu.dcache.tags", + "block_size": 64, + "type": "LRU", + "data_latency": 2 + }, + "tgts_per_mshr": 20, + "demand_mshr_reserve": 1, + "power_model": null, + "addr_ranges": [ + "0:18446744073709551615:0:0:0:0" + ], + "is_read_only": false, + "prefetch_on_access": false, + "path": "system.cpu.dcache", + "data_latency": 2, + "tag_latency": 2, + "name": "dcache", + "p_state_clk_gate_bins": 20, + "sequential_access": false, + "assoc": 2 + }, + "path": "system.cpu", + "fetch1ToFetch2ForwardDelay": 1, + "decodeInputBufferSize": 3 + } + ], + "multi_thread": false, + "exit_on_work_items": false, + "work_item_id": -1, + "num_work_ids": 16 + }, + "time_sync_period": 100000000000, + "eventq_index": 0, + "time_sync_spin_threshold": 100000000, + "cxx_class": "Root", + "path": "root", + "time_sync_enable": false, + "type": "Root", + "full_system": false +}
\ No newline at end of file diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/minor-timing/simerr b/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/minor-timing/simerr new file mode 100755 index 000000000..85a6a33ad --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/minor-timing/simerr @@ -0,0 +1,4 @@ +warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes) +warn: Unknown operating system; assuming Linux. +warn: Sockets disabled, not accepting gdb connections +warn: ClockedObject: More than one power state change request encountered within the same simulation tick diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/minor-timing/simout b/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/minor-timing/simout new file mode 100755 index 000000000..eb07824f2 --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/minor-timing/simout @@ -0,0 +1,51 @@ +Redirecting stdout to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64m/minor-timing/simout +Redirecting stderr to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64m/minor-timing/simerr +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled Nov 30 2016 14:33:35 +gem5 started Nov 30 2016 16:18:44 +gem5 executing on zizzer, pid 34094 +command line: /z/powerjg/gem5-upstream/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64m/minor-timing -re /z/powerjg/gem5-upstream/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64m/minor-timing + +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. +mul: PASS +mul, overflow: PASS +mulh: PASS +mulh, negative: PASS +mulh, all bits set: PASS +mulhsu, all bits set: PASS +mulhsu: PASS +mulhu: PASS +mulhu, all bits set: PASS +div: PASS +div/0: PASS +div, overflow: PASS +divu: PASS +divu/0: PASS +divu, "overflow": PASS +rem: PASS +rem/0: PASS +rem, overflow: PASS +remu: PASS +remu/0: PASS +remu, "overflow": PASS +mulw, truncate: PASS +mulw, overflow: PASS +divw, truncate: PASS +divw/0: PASS +divw, overflow: PASS +divuw, truncate: PASS +divuw/0: PASS +divuw, "overflow": PASS +divuw, sign extend: PASS +remw, truncate: PASS +remw/0: PASS +remw, overflow: PASS +remuw, truncate: PASS +remuw/0: PASS +remuw, "overflow": PASS +remuw, sign extend: PASS +Exiting @ tick 165091500 because target called exit() diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/minor-timing/stats.txt b/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/minor-timing/stats.txt new file mode 100644 index 000000000..4aec07287 --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/minor-timing/stats.txt @@ -0,0 +1,761 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.000165 # Number of seconds simulated +sim_ticks 165091500 # Number of ticks simulated +final_tick 165091500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 30601 # Simulator instruction rate (inst/s) +host_op_rate 30601 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 44574860 # Simulator tick rate (ticks/s) +host_mem_usage 244264 # Number of bytes of host memory used +host_seconds 3.70 # Real time elapsed on the host +sim_insts 113337 # Number of instructions simulated +sim_ops 113337 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 165091500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 49984 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 16768 # Number of bytes read from this memory +system.physmem.bytes_read::total 66752 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 49984 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 49984 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 781 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 262 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1043 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 302765436 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 101567918 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 404333355 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 302765436 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 302765436 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 302765436 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 101567918 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 404333355 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1043 # Number of read requests accepted +system.physmem.writeReqs 0 # Number of write requests accepted +system.physmem.readBursts 1043 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 66752 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue +system.physmem.bytesWritten 0 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 66752 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 93 # Per bank write bursts +system.physmem.perBankRdBursts::1 5 # Per bank write bursts +system.physmem.perBankRdBursts::2 17 # Per bank write bursts +system.physmem.perBankRdBursts::3 108 # Per bank write bursts +system.physmem.perBankRdBursts::4 59 # Per bank write bursts +system.physmem.perBankRdBursts::5 95 # Per bank write bursts +system.physmem.perBankRdBursts::6 66 # Per bank write bursts +system.physmem.perBankRdBursts::7 26 # Per bank write bursts +system.physmem.perBankRdBursts::8 58 # Per bank write bursts +system.physmem.perBankRdBursts::9 78 # Per bank write bursts +system.physmem.perBankRdBursts::10 82 # Per bank write bursts +system.physmem.perBankRdBursts::11 51 # Per bank write bursts +system.physmem.perBankRdBursts::12 133 # Per bank write bursts +system.physmem.perBankRdBursts::13 67 # Per bank write bursts +system.physmem.perBankRdBursts::14 98 # Per bank write bursts +system.physmem.perBankRdBursts::15 7 # Per bank write bursts +system.physmem.perBankWrBursts::0 0 # Per bank write bursts +system.physmem.perBankWrBursts::1 0 # Per bank write bursts +system.physmem.perBankWrBursts::2 0 # Per bank write bursts +system.physmem.perBankWrBursts::3 0 # Per bank write bursts +system.physmem.perBankWrBursts::4 0 # Per bank write bursts +system.physmem.perBankWrBursts::5 0 # Per bank write bursts +system.physmem.perBankWrBursts::6 0 # Per bank write bursts +system.physmem.perBankWrBursts::7 0 # Per bank write bursts +system.physmem.perBankWrBursts::8 0 # Per bank write bursts +system.physmem.perBankWrBursts::9 0 # Per bank write bursts +system.physmem.perBankWrBursts::10 0 # Per bank write bursts +system.physmem.perBankWrBursts::11 0 # Per bank write bursts +system.physmem.perBankWrBursts::12 0 # Per bank write bursts +system.physmem.perBankWrBursts::13 0 # Per bank write bursts +system.physmem.perBankWrBursts::14 0 # Per bank write bursts +system.physmem.perBankWrBursts::15 0 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 164764000 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 1043 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 0 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 988 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 51 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 209 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 312.956938 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 206.620752 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 291.549711 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 58 27.75% 27.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 50 23.92% 51.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 39 18.66% 70.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 19 9.09% 79.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 9 4.31% 83.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 8 3.83% 87.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 6 2.87% 90.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 3 1.44% 91.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 17 8.13% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 209 # Bytes accessed per row activation +system.physmem.totQLat 16657750 # Total ticks spent queuing +system.physmem.totMemAccLat 36214000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 5215000 # Total ticks spent in databus transfers +system.physmem.avgQLat 15971.00 # Average queueing delay per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 34721.00 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 404.33 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 404.33 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.busUtil 3.16 # Data bus utilization in percentage +system.physmem.busUtilRead 3.16 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing +system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing +system.physmem.readRowHits 829 # Number of row buffer hits during reads +system.physmem.writeRowHits 0 # Number of row buffer hits during writes +system.physmem.readRowHitRate 79.48 # Row buffer hit rate for reads +system.physmem.writeRowHitRate nan # Row buffer hit rate for writes +system.physmem.avgGap 157971.24 # Average gap between requests +system.physmem.pageHitRate 79.48 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 778260 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 409860 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 3348660 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 13522080.000000 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 9067560 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 480480 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 54701760 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 6869760 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 2569980 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 91748400 # Total energy per rank (pJ) +system.physmem_0.averagePower 555.739358 # Core power per rank (mW) +system.physmem_0.totalIdleTime 143461250 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 642000 # Time in different power states +system.physmem_0.memoryStateTime::REF 5732000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 6106000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 17892500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 14770000 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 119949000 # Time in different power states +system.physmem_1.actEnergy 749700 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 383295 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 4098360 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 12907440.000000 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 9572580 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 409440 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 46964580 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 13642080 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 1635840 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 90363315 # Total energy per rank (pJ) +system.physmem_1.averagePower 547.349607 # Core power per rank (mW) +system.physmem_1.totalIdleTime 142759500 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 477500 # Time in different power states +system.physmem_1.memoryStateTime::REF 5472000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 4514500 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 35521500 # Time in different power states +system.physmem_1.memoryStateTime::ACT 16091750 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 103014250 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 165091500 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 31704 # Number of BP lookups +system.cpu.branchPred.condPredicted 20239 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 2235 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 27881 # Number of BTB lookups +system.cpu.branchPred.BTBHits 15332 # Number of BTB hits +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 54.990854 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 0 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 5600 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 3678 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 1922 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 1024 # Number of mispredicted indirect branches. +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 45 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 165091500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 330183 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 113337 # Number of instructions committed +system.cpu.committedOps 113337 # Number of ops (including micro ops) committed +system.cpu.discardedOps 5814 # Number of ops (including micro ops) which were discarded before commit +system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching +system.cpu.cpi 2.913285 # CPI: cycles per instruction +system.cpu.ipc 0.343255 # IPC: instructions per cycle +system.cpu.op_class_0::No_OpClass 45 0.04% 0.04% # Class of committed instruction +system.cpu.op_class_0::IntAlu 69651 61.45% 61.49% # Class of committed instruction +system.cpu.op_class_0::IntMult 122 0.11% 61.60% # Class of committed instruction +system.cpu.op_class_0::IntDiv 26 0.02% 61.63% # Class of committed instruction +system.cpu.op_class_0::FloatAdd 0 0.00% 61.63% # Class of committed instruction +system.cpu.op_class_0::FloatCmp 0 0.00% 61.63% # Class of committed instruction +system.cpu.op_class_0::FloatCvt 0 0.00% 61.63% # Class of committed instruction +system.cpu.op_class_0::FloatMult 0 0.00% 61.63% # Class of committed instruction +system.cpu.op_class_0::FloatMultAcc 0 0.00% 61.63% # Class of committed instruction +system.cpu.op_class_0::FloatDiv 0 0.00% 61.63% # Class of committed instruction +system.cpu.op_class_0::FloatMisc 0 0.00% 61.63% # Class of committed instruction +system.cpu.op_class_0::FloatSqrt 0 0.00% 61.63% # Class of committed instruction +system.cpu.op_class_0::SimdAdd 0 0.00% 61.63% # Class of committed instruction +system.cpu.op_class_0::SimdAddAcc 0 0.00% 61.63% # Class of committed instruction +system.cpu.op_class_0::SimdAlu 0 0.00% 61.63% # Class of committed instruction +system.cpu.op_class_0::SimdCmp 0 0.00% 61.63% # Class of committed instruction +system.cpu.op_class_0::SimdCvt 0 0.00% 61.63% # Class of committed instruction +system.cpu.op_class_0::SimdMisc 0 0.00% 61.63% # Class of committed instruction +system.cpu.op_class_0::SimdMult 0 0.00% 61.63% # Class of committed instruction +system.cpu.op_class_0::SimdMultAcc 0 0.00% 61.63% # Class of committed instruction +system.cpu.op_class_0::SimdShift 0 0.00% 61.63% # Class of committed instruction +system.cpu.op_class_0::SimdShiftAcc 0 0.00% 61.63% # Class of committed instruction +system.cpu.op_class_0::SimdSqrt 0 0.00% 61.63% # Class of committed instruction +system.cpu.op_class_0::SimdFloatAdd 0 0.00% 61.63% # Class of committed instruction +system.cpu.op_class_0::SimdFloatAlu 0 0.00% 61.63% # Class of committed instruction +system.cpu.op_class_0::SimdFloatCmp 0 0.00% 61.63% # Class of committed instruction +system.cpu.op_class_0::SimdFloatCvt 0 0.00% 61.63% # Class of committed instruction +system.cpu.op_class_0::SimdFloatDiv 0 0.00% 61.63% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMisc 0 0.00% 61.63% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMult 0 0.00% 61.63% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 61.63% # Class of committed instruction +system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 61.63% # Class of committed instruction +system.cpu.op_class_0::MemRead 23780 20.98% 82.61% # Class of committed instruction +system.cpu.op_class_0::MemWrite 19713 17.39% 100.00% # Class of committed instruction +system.cpu.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction +system.cpu.op_class_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction +system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.op_class_0::total 113337 # Class of committed instruction +system.cpu.tickCycles 171254 # Number of cycles that the object actually ticked +system.cpu.idleCycles 158929 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 165091500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 0 # number of replacements +system.cpu.dcache.tags.tagsinuse 213.474286 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 43868 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 263 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 166.798479 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 213.474286 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.052118 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.052118 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 263 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 4 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 57 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 202 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.064209 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 88905 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 88905 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 165091500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 24540 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 24540 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 19328 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 19328 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 43868 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 43868 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 43868 # number of overall hits +system.cpu.dcache.overall_hits::total 43868 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 69 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 69 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 384 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 384 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 453 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 453 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 453 # number of overall misses +system.cpu.dcache.overall_misses::total 453 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 7586500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 7586500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 31133500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 31133500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 38720000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 38720000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 38720000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 38720000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 24609 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 24609 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 19712 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 19712 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 44321 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 44321 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 44321 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 44321 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002804 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.002804 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.019481 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.019481 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.010221 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.010221 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.010221 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.010221 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 109949.275362 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 109949.275362 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 81076.822917 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 81076.822917 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 85474.613687 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 85474.613687 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 85474.613687 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 85474.613687 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 4 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 186 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 186 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 190 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 190 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 190 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 190 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 65 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 65 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 198 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 198 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 263 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 263 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 263 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 263 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7121500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 7121500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 16117500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 16117500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23239000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 23239000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23239000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 23239000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002641 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002641 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010045 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010045 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005934 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.005934 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005934 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.005934 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 109561.538462 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 109561.538462 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 81401.515152 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 81401.515152 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 88361.216730 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 88361.216730 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 88361.216730 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 88361.216730 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 165091500 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 14 # number of replacements +system.cpu.icache.tags.tagsinuse 386.834879 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 49717 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 781 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 63.658131 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 386.834879 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.188884 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.188884 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 767 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 497 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 224 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.374512 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 101777 # Number of tag accesses +system.cpu.icache.tags.data_accesses 101777 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 165091500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 49717 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 49717 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 49717 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 49717 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 49717 # number of overall hits +system.cpu.icache.overall_hits::total 49717 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 781 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 781 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 781 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 781 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 781 # number of overall misses +system.cpu.icache.overall_misses::total 781 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 68473000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 68473000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 68473000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 68473000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 68473000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 68473000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 50498 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 50498 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 50498 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 50498 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 50498 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 50498 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.015466 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.015466 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.015466 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.015466 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.015466 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.015466 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 87673.495519 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 87673.495519 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 87673.495519 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 87673.495519 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 87673.495519 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 87673.495519 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.icache.writebacks::writebacks 14 # number of writebacks +system.cpu.icache.writebacks::total 14 # number of writebacks +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 781 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 781 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 781 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 781 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 781 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 781 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 67692000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 67692000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 67692000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 67692000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 67692000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 67692000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.015466 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.015466 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.015466 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.015466 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.015466 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.015466 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 86673.495519 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 86673.495519 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 86673.495519 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 86673.495519 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 86673.495519 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 86673.495519 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 165091500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.replacements 0 # number of replacements +system.cpu.l2cache.tags.tagsinuse 603.610931 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 15 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 1043 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.014382 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::cpu.inst 390.574887 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 213.036044 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.011919 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.006501 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.018421 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 1043 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 50 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 556 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 437 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.031830 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 9507 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 9507 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 165091500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.WritebackClean_hits::writebacks 14 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 14 # number of WritebackClean hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 1 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.data 1 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 1 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.data 1 # number of overall hits +system.cpu.l2cache.overall_hits::total 1 # number of overall hits +system.cpu.l2cache.ReadExReq_misses::cpu.data 198 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 198 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 781 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 781 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 64 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 64 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.inst 781 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 262 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 1043 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 781 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 262 # number of overall misses +system.cpu.l2cache.overall_misses::total 1043 # number of overall misses +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 15820000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 15820000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 66520500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 66520500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 7011500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 7011500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 66520500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 22831500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 89352000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 66520500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 22831500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 89352000 # number of overall miss cycles +system.cpu.l2cache.WritebackClean_accesses::writebacks 14 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 14 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 198 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 198 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 781 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 781 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 65 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 65 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 781 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 263 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 1044 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 781 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 263 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 1044 # number of overall (read+write) accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 1 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 1 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.984615 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.984615 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.996198 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.999042 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.996198 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.999042 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79898.989899 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79898.989899 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 85173.495519 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 85173.495519 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 109554.687500 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 109554.687500 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 85173.495519 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 87143.129771 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 85668.264621 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 85173.495519 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 87143.129771 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 85668.264621 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 198 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 198 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 781 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 781 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 64 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 64 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 781 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 262 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 1043 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 781 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 262 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 1043 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 13840000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 13840000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 58710500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 58710500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 6371500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 6371500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 58710500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 20211500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 78922000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 58710500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 20211500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 78922000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 1 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.984615 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.984615 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.996198 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.999042 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.996198 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.999042 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69898.989899 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69898.989899 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 75173.495519 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 75173.495519 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 99554.687500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 99554.687500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 75173.495519 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 77143.129771 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 75668.264621 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 75173.495519 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 77143.129771 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 75668.264621 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 1058 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 15 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 165091500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 846 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 14 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 198 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 198 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 781 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 65 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1576 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 526 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 2102 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50880 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 16832 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 67712 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 1044 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.000958 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.030949 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 1043 99.90% 99.90% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 1 0.10% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 1044 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 543000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 1171500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.7 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 394500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) +system.membus.snoop_filter.tot_requests 1043 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 165091500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 845 # Transaction distribution +system.membus.trans_dist::ReadExReq 198 # Transaction distribution +system.membus.trans_dist::ReadExResp 198 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 845 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 2086 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 2086 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 66752 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 66752 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoopTraffic 0 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 1043 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 1043 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 1043 # Request fanout histogram +system.membus.reqLayer0.occupancy 1170500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.7 # Layer utilization (%) +system.membus.respLayer1.occupancy 5536250 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 3.4 # Layer utilization (%) + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/o3-timing/config.ini b/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/o3-timing/config.ini new file mode 100644 index 000000000..aba900b27 --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/o3-timing/config.ini @@ -0,0 +1,872 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain +boot_osflags=a +cache_line_size=64 +clk_domain=system.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +exit_on_work_items=false +init_param=0 +kernel= +kernel_addr_check=true +load_addr_mask=1099511627775 +load_offset=0 +mem_mode=timing +mem_ranges= +memories=system.physmem +mmap_using_noreserve=false +multi_thread=false +num_work_ids=16 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +readfile= +symbolfile= +thermal_components= +thermal_model=Null +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=DerivO3CPU +children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload +LFSTSize=1024 +LQEntries=32 +LSQCheckLoads=true +LSQDepCheckShift=4 +SQEntries=32 +SSITSize=1024 +activity=0 +backComSize=5 +branchPred=system.cpu.branchPred +cachePorts=200 +checker=Null +clk_domain=system.cpu_clk_domain +commitToDecodeDelay=1 +commitToFetchDelay=1 +commitToIEWDelay=1 +commitToRenameDelay=1 +commitWidth=8 +cpu_id=0 +decodeToFetchDelay=1 +decodeToRenameDelay=1 +decodeWidth=8 +default_p_state=UNDEFINED +dispatchWidth=8 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +eventq_index=0 +fetchBufferSize=64 +fetchQueueSize=32 +fetchToDecodeDelay=1 +fetchTrapLatency=1 +fetchWidth=8 +forwardComSize=5 +fuPool=system.cpu.fuPool +function_trace=false +function_trace_start=0 +iewToCommitDelay=1 +iewToDecodeDelay=1 +iewToFetchDelay=1 +iewToRenameDelay=1 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +issueToExecuteDelay=1 +issueWidth=8 +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +needsTSO=false +numIQEntries=64 +numPhysCCRegs=0 +numPhysFloatRegs=256 +numPhysIntRegs=256 +numROBEntries=192 +numRobs=1 +numThreads=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +profile=0 +progress_interval=0 +renameToDecodeDelay=1 +renameToFetchDelay=1 +renameToIEWDelay=2 +renameToROBDelay=1 +renameWidth=8 +simpoint_start_insts= +smtCommitPolicy=RoundRobin +smtFetchPolicy=SingleThread +smtIQPolicy=Partitioned +smtIQThreshold=100 +smtLSQPolicy=Partitioned +smtLSQThreshold=100 +smtNumFetchingThreads=1 +smtROBPolicy=Partitioned +smtROBThreshold=100 +socket_id=0 +squashWidth=8 +store_set_clear_period=250000 +switched_out=false +system=system +tracer=system.cpu.tracer +trapLatency=13 +wbWidth=8 +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.branchPred] +type=TournamentBP +BTBEntries=4096 +BTBTagSize=16 +RASSize=16 +choiceCtrBits=2 +choicePredictorSize=8192 +eventq_index=0 +globalCtrBits=2 +globalPredictorSize=8192 +indirectHashGHR=true +indirectHashTargets=true +indirectPathLength=3 +indirectSets=256 +indirectTagSize=16 +indirectWays=2 +instShiftAmt=2 +localCtrBits=2 +localHistoryTableSize=2048 +localPredictorSize=2048 +numThreads=1 +useIndirect=true + +[system.cpu.dcache] +type=Cache +children=tags +addr_ranges=0:18446744073709551615:0:0:0:0 +assoc=2 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +data_latency=2 +default_p_state=UNDEFINED +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=4 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=262144 +system=system +tag_latency=2 +tags=system.cpu.dcache.tags +tgts_per_mshr=20 +write_buffers=8 +writeback_clean=false +cpu_side=system.cpu.dcache_port +mem_side=system.cpu.toL2Bus.slave[1] + +[system.cpu.dcache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +data_latency=2 +default_p_state=UNDEFINED +eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +sequential_access=false +size=262144 +tag_latency=2 + +[system.cpu.dtb] +type=RiscvTLB +eventq_index=0 +size=64 + +[system.cpu.fuPool] +type=FUPool +children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 +FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 +eventq_index=0 + +[system.cpu.fuPool.FUList0] +type=FUDesc +children=opList +count=6 +eventq_index=0 +opList=system.cpu.fuPool.FUList0.opList + +[system.cpu.fuPool.FUList0.opList] +type=OpDesc +eventq_index=0 +opClass=IntAlu +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList1] +type=FUDesc +children=opList0 opList1 +count=2 +eventq_index=0 +opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 + +[system.cpu.fuPool.FUList1.opList0] +type=OpDesc +eventq_index=0 +opClass=IntMult +opLat=3 +pipelined=true + +[system.cpu.fuPool.FUList1.opList1] +type=OpDesc +eventq_index=0 +opClass=IntDiv +opLat=20 +pipelined=false + +[system.cpu.fuPool.FUList2] +type=FUDesc +children=opList0 opList1 opList2 +count=4 +eventq_index=0 +opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 + +[system.cpu.fuPool.FUList2.opList0] +type=OpDesc +eventq_index=0 +opClass=FloatAdd +opLat=2 +pipelined=true + +[system.cpu.fuPool.FUList2.opList1] +type=OpDesc +eventq_index=0 +opClass=FloatCmp +opLat=2 +pipelined=true + +[system.cpu.fuPool.FUList2.opList2] +type=OpDesc +eventq_index=0 +opClass=FloatCvt +opLat=2 +pipelined=true + +[system.cpu.fuPool.FUList3] +type=FUDesc +children=opList0 opList1 opList2 opList3 opList4 +count=2 +eventq_index=0 +opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 system.cpu.fuPool.FUList3.opList3 system.cpu.fuPool.FUList3.opList4 + +[system.cpu.fuPool.FUList3.opList0] +type=OpDesc +eventq_index=0 +opClass=FloatMult +opLat=4 +pipelined=true + +[system.cpu.fuPool.FUList3.opList1] +type=OpDesc +eventq_index=0 +opClass=FloatMultAcc +opLat=5 +pipelined=true + +[system.cpu.fuPool.FUList3.opList2] +type=OpDesc +eventq_index=0 +opClass=FloatMisc +opLat=3 +pipelined=true + +[system.cpu.fuPool.FUList3.opList3] +type=OpDesc +eventq_index=0 +opClass=FloatDiv +opLat=12 +pipelined=false + +[system.cpu.fuPool.FUList3.opList4] +type=OpDesc +eventq_index=0 +opClass=FloatSqrt +opLat=24 +pipelined=false + +[system.cpu.fuPool.FUList4] +type=FUDesc +children=opList0 opList1 +count=0 +eventq_index=0 +opList=system.cpu.fuPool.FUList4.opList0 system.cpu.fuPool.FUList4.opList1 + +[system.cpu.fuPool.FUList4.opList0] +type=OpDesc +eventq_index=0 +opClass=MemRead +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList4.opList1] +type=OpDesc +eventq_index=0 +opClass=FloatMemRead +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5] +type=FUDesc +children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 +count=4 +eventq_index=0 +opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 + +[system.cpu.fuPool.FUList5.opList00] +type=OpDesc +eventq_index=0 +opClass=SimdAdd +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList01] +type=OpDesc +eventq_index=0 +opClass=SimdAddAcc +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList02] +type=OpDesc +eventq_index=0 +opClass=SimdAlu +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList03] +type=OpDesc +eventq_index=0 +opClass=SimdCmp +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList04] +type=OpDesc +eventq_index=0 +opClass=SimdCvt +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList05] +type=OpDesc +eventq_index=0 +opClass=SimdMisc +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList06] +type=OpDesc +eventq_index=0 +opClass=SimdMult +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList07] +type=OpDesc +eventq_index=0 +opClass=SimdMultAcc +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList08] +type=OpDesc +eventq_index=0 +opClass=SimdShift +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList09] +type=OpDesc +eventq_index=0 +opClass=SimdShiftAcc +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList10] +type=OpDesc +eventq_index=0 +opClass=SimdSqrt +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList11] +type=OpDesc +eventq_index=0 +opClass=SimdFloatAdd +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList12] +type=OpDesc +eventq_index=0 +opClass=SimdFloatAlu +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList13] +type=OpDesc +eventq_index=0 +opClass=SimdFloatCmp +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList14] +type=OpDesc +eventq_index=0 +opClass=SimdFloatCvt +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList15] +type=OpDesc +eventq_index=0 +opClass=SimdFloatDiv +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList16] +type=OpDesc +eventq_index=0 +opClass=SimdFloatMisc +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList17] +type=OpDesc +eventq_index=0 +opClass=SimdFloatMult +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList18] +type=OpDesc +eventq_index=0 +opClass=SimdFloatMultAcc +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList19] +type=OpDesc +eventq_index=0 +opClass=SimdFloatSqrt +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList6] +type=FUDesc +children=opList0 opList1 +count=0 +eventq_index=0 +opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1 + +[system.cpu.fuPool.FUList6.opList0] +type=OpDesc +eventq_index=0 +opClass=MemWrite +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList6.opList1] +type=OpDesc +eventq_index=0 +opClass=FloatMemWrite +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList7] +type=FUDesc +children=opList0 opList1 opList2 opList3 +count=4 +eventq_index=0 +opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 system.cpu.fuPool.FUList7.opList2 system.cpu.fuPool.FUList7.opList3 + +[system.cpu.fuPool.FUList7.opList0] +type=OpDesc +eventq_index=0 +opClass=MemRead +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList7.opList1] +type=OpDesc +eventq_index=0 +opClass=MemWrite +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList7.opList2] +type=OpDesc +eventq_index=0 +opClass=FloatMemRead +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList7.opList3] +type=OpDesc +eventq_index=0 +opClass=FloatMemWrite +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList8] +type=FUDesc +children=opList +count=1 +eventq_index=0 +opList=system.cpu.fuPool.FUList8.opList + +[system.cpu.fuPool.FUList8.opList] +type=OpDesc +eventq_index=0 +opClass=IprAccess +opLat=3 +pipelined=false + +[system.cpu.icache] +type=Cache +children=tags +addr_ranges=0:18446744073709551615:0:0:0:0 +assoc=2 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +data_latency=2 +default_p_state=UNDEFINED +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=true +max_miss_count=0 +mshrs=4 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=131072 +system=system +tag_latency=2 +tags=system.cpu.icache.tags +tgts_per_mshr=20 +write_buffers=8 +writeback_clean=true +cpu_side=system.cpu.icache_port +mem_side=system.cpu.toL2Bus.slave[0] + +[system.cpu.icache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +data_latency=2 +default_p_state=UNDEFINED +eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +sequential_access=false +size=131072 +tag_latency=2 + +[system.cpu.interrupts] +type=RiscvInterrupts +eventq_index=0 + +[system.cpu.isa] +type=RiscvISA +eventq_index=0 + +[system.cpu.itb] +type=RiscvTLB +eventq_index=0 +size=64 + +[system.cpu.l2cache] +type=Cache +children=tags +addr_ranges=0:18446744073709551615:0:0:0:0 +assoc=8 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +data_latency=20 +default_p_state=UNDEFINED +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=20 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +prefetch_on_access=false +prefetcher=Null +response_latency=20 +sequential_access=false +size=2097152 +system=system +tag_latency=20 +tags=system.cpu.l2cache.tags +tgts_per_mshr=12 +write_buffers=8 +writeback_clean=false +cpu_side=system.cpu.toL2Bus.master[0] +mem_side=system.membus.slave[1] + +[system.cpu.l2cache.tags] +type=LRU +assoc=8 +block_size=64 +clk_domain=system.cpu_clk_domain +data_latency=20 +default_p_state=UNDEFINED +eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +sequential_access=false +size=2097152 +tag_latency=20 + +[system.cpu.toL2Bus] +type=CoherentXBar +children=snoop_filter +clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED +eventq_index=0 +forward_latency=0 +frontend_latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +point_of_coherency=false +power_model=Null +response_latency=1 +snoop_filter=system.cpu.toL2Bus.snoop_filter +snoop_response_latency=1 +system=system +use_default_range=false +width=32 +master=system.cpu.l2cache.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side + +[system.cpu.toL2Bus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=0 +max_capacity=8388608 +system=system + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=LiveProcess +cmd=insttest +cwd= +drivers= +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable=/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64m/insttest +gid=100 +input=cin +kvmInSE=false +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=0 +system=system +uid=100 +useArchPT=false + +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000000 + +[system.membus] +type=CoherentXBar +children=snoop_filter +clk_domain=system.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +forward_latency=4 +frontend_latency=3 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +point_of_coherency=true +power_model=Null +response_latency=2 +snoop_filter=system.membus.snoop_filter +snoop_response_latency=4 +system=system +use_default_range=false +width=16 +master=system.physmem.port +slave=system.system_port system.cpu.l2cache.mem_side + +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + +[system.physmem] +type=DRAMCtrl +IDD0=0.055000 +IDD02=0.000000 +IDD2N=0.032000 +IDD2N2=0.000000 +IDD2P0=0.000000 +IDD2P02=0.000000 +IDD2P1=0.032000 +IDD2P12=0.000000 +IDD3N=0.038000 +IDD3N2=0.000000 +IDD3P0=0.000000 +IDD3P02=0.000000 +IDD3P1=0.038000 +IDD3P12=0.000000 +IDD4R=0.157000 +IDD4R2=0.000000 +IDD4W=0.125000 +IDD4W2=0.000000 +IDD5=0.235000 +IDD52=0.000000 +IDD6=0.020000 +IDD62=0.000000 +VDD=1.500000 +VDD2=0.000000 +activation_limit=4 +addr_mapping=RoRaBaCoCh +bank_groups_per_rank=0 +banks_per_rank=8 +burst_length=8 +channels=1 +clk_domain=system.clk_domain +conf_table_reported=true +default_p_state=UNDEFINED +device_bus_width=8 +device_rowbuffer_size=1024 +device_size=536870912 +devices_per_rank=8 +dll=true +eventq_index=0 +in_addr_map=true +kvm_map=true +max_accesses_per_row=16 +mem_sched_policy=frfcfs +min_writes_per_switch=16 +null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +page_policy=open_adaptive +power_model=Null +range=0:134217727:0:0:0:0 +ranks_per_channel=2 +read_buffer_size=32 +static_backend_latency=10000 +static_frontend_latency=10000 +tBURST=5000 +tCCD_L=0 +tCK=1250 +tCL=13750 +tCS=2500 +tRAS=35000 +tRCD=13750 +tREFI=7800000 +tRFC=260000 +tRP=13750 +tRRD=6000 +tRRD_L=0 +tRTP=7500 +tRTW=2500 +tWR=15000 +tWTR=7500 +tXAW=30000 +tXP=6000 +tXPDLL=0 +tXS=270000 +tXSDLL=0 +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 +port=system.membus.master[0] + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/o3-timing/config.json b/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/o3-timing/config.json new file mode 100644 index 000000000..c507a1468 --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/o3-timing/config.json @@ -0,0 +1,1151 @@ +{ + "name": null, + "sim_quantum": 0, + "system": { + "kernel": "", + "mmap_using_noreserve": false, + "kernel_addr_check": true, + "membus": { + "point_of_coherency": true, + "system": "system", + "response_latency": 2, + "cxx_class": "CoherentXBar", + "forward_latency": 4, + "clk_domain": "system.clk_domain", + "width": 16, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "master": { + "peer": [ + "system.physmem.port" + ], + "role": "MASTER" + }, + "type": "CoherentXBar", + "frontend_latency": 3, + "slave": { + "peer": [ + "system.system_port", + "system.cpu.l2cache.mem_side" + ], + "role": "SLAVE" + }, + "p_state_clk_gate_min": 1000, + "snoop_filter": { + "name": "snoop_filter", + "system": "system", + "max_capacity": 8388608, + "eventq_index": 0, + "cxx_class": "SnoopFilter", + "path": "system.membus.snoop_filter", + "type": "SnoopFilter", + "lookup_latency": 1 + }, + "power_model": null, + "path": "system.membus", + "snoop_response_latency": 4, + "name": "membus", + "p_state_clk_gate_bins": 20, + "use_default_range": false + }, + "symbolfile": "", + "readfile": "", + "thermal_model": null, + "cxx_class": "System", + "work_begin_cpu_id_exit": -1, + "load_offset": 0, + "work_begin_exit_count": 0, + "p_state_clk_gate_min": 1000, + "memories": [ + "system.physmem" + ], + "work_begin_ckpt_count": 0, + "clk_domain": { + "name": "clk_domain", + "clock": [ + 1000 + ], + "init_perf_level": 0, + "voltage_domain": "system.voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "mem_ranges": [], + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "dvfs_handler": { + "enable": false, + "name": "dvfs_handler", + "sys_clk_domain": "system.clk_domain", + "transition_latency": 100000000, + "eventq_index": 0, + "cxx_class": "DVFSHandler", + "domains": [], + "path": "system.dvfs_handler", + "type": "DVFSHandler" + }, + "work_end_exit_count": 0, + "type": "System", + "voltage_domain": { + "name": "voltage_domain", + "eventq_index": 0, + "voltage": [ + "1.0" + ], + "cxx_class": "VoltageDomain", + "path": "system.voltage_domain", + "type": "VoltageDomain" + }, + "cache_line_size": 64, + "boot_osflags": "a", + "system_port": { + "peer": "system.membus.slave[0]", + "role": "MASTER" + }, + "physmem": { + "static_frontend_latency": 10000, + "tRFC": 260000, + "activation_limit": 4, + "in_addr_map": true, + "IDD3N2": "0.0", + "tWTR": 7500, + "IDD52": "0.0", + "clk_domain": "system.clk_domain", + "channels": 1, + "write_buffer_size": 64, + "device_bus_width": 8, + "VDD": "1.5", + "write_high_thresh_perc": 85, + "cxx_class": "DRAMCtrl", + "bank_groups_per_rank": 0, + "IDD2N2": "0.0", + "port": { + "peer": "system.membus.master[0]", + "role": "SLAVE" + }, + "tCCD_L": 0, + "IDD2N": "0.032", + "p_state_clk_gate_min": 1000, + "null": false, + "IDD2P1": "0.032", + "eventq_index": 0, + "tRRD": 6000, + "tRTW": 2500, + "IDD4R": "0.157", + "burst_length": 8, + "tRTP": 7500, + "IDD4W": "0.125", + "tWR": 15000, + "banks_per_rank": 8, + "devices_per_rank": 8, + "IDD2P02": "0.0", + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "IDD6": "0.02", + "IDD5": "0.235", + "tRCD": 13750, + "type": "DRAMCtrl", + "IDD3P02": "0.0", + "tRRD_L": 0, + "IDD0": "0.055", + "IDD62": "0.0", + "min_writes_per_switch": 16, + "mem_sched_policy": "frfcfs", + "IDD02": "0.0", + "IDD2P0": "0.0", + "ranks_per_channel": 2, + "page_policy": "open_adaptive", + "IDD4W2": "0.0", + "tCS": 2500, + "power_model": null, + "tCL": 13750, + "read_buffer_size": 32, + "conf_table_reported": true, + "tCK": 1250, + "tRAS": 35000, + "tRP": 13750, + "tBURST": 5000, + "path": "system.physmem", + "tXP": 6000, + "tXS": 270000, + "addr_mapping": "RoRaBaCoCh", + "IDD3P0": "0.0", + "IDD3P1": "0.038", + "IDD3N": "0.038", + "name": "physmem", + "tXSDLL": 0, + "device_size": 536870912, + "kvm_map": true, + "dll": true, + "tXAW": 30000, + "write_low_thresh_perc": 50, + "range": "0:134217727:0:0:0:0", + "VDD2": "0.0", + "IDD2P12": "0.0", + "p_state_clk_gate_bins": 20, + "tXPDLL": 0, + "IDD4R2": "0.0", + "device_rowbuffer_size": 1024, + "static_backend_latency": 10000, + "max_accesses_per_row": 16, + "IDD3P12": "0.0", + "tREFI": 7800000 + }, + "power_model": null, + "work_cpus_ckpt_count": 0, + "thermal_components": [], + "path": "system", + "cpu_clk_domain": { + "name": "cpu_clk_domain", + "clock": [ + 500 + ], + "init_perf_level": 0, + "voltage_domain": "system.voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.cpu_clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "work_end_ckpt_count": 0, + "mem_mode": "timing", + "name": "system", + "init_param": 0, + "p_state_clk_gate_bins": 20, + "load_addr_mask": 1099511627775, + "cpu": [ + { + "SQEntries": 32, + "smtLSQThreshold": 100, + "fetchTrapLatency": 1, + "iewToRenameDelay": 1, + "l2cache": { + "cpu_side": { + "peer": "system.cpu.toL2Bus.master[0]", + "role": "SLAVE" + }, + "clusivity": "mostly_incl", + "prefetcher": null, + "system": "system", + "write_buffers": 8, + "response_latency": 20, + "cxx_class": "Cache", + "size": 2097152, + "type": "Cache", + "clk_domain": "system.cpu_clk_domain", + "max_miss_count": 0, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "mem_side": { + "peer": "system.membus.slave[1]", + "role": "MASTER" + }, + "mshrs": 20, + "writeback_clean": false, + "p_state_clk_gate_min": 1000, + "tags": { + "size": 2097152, + "tag_latency": 20, + "name": "tags", + "p_state_clk_gate_min": 1000, + "eventq_index": 0, + "p_state_clk_gate_bins": 20, + "default_p_state": "UNDEFINED", + "clk_domain": "system.cpu_clk_domain", + "power_model": null, + "sequential_access": false, + "assoc": 8, + "cxx_class": "LRU", + "p_state_clk_gate_max": 1000000000000, + "path": "system.cpu.l2cache.tags", + "block_size": 64, + "type": "LRU", + "data_latency": 20 + }, + "tgts_per_mshr": 12, + "demand_mshr_reserve": 1, + "power_model": null, + "addr_ranges": [ + "0:18446744073709551615:0:0:0:0" + ], + "is_read_only": false, + "prefetch_on_access": false, + "path": "system.cpu.l2cache", + "data_latency": 20, + "tag_latency": 20, + "name": "l2cache", + "p_state_clk_gate_bins": 20, + "sequential_access": false, + "assoc": 8 + }, + "itb": { + "name": "itb", + "eventq_index": 0, + "cxx_class": "RiscvISA::TLB", + "path": "system.cpu.itb", + "type": "RiscvTLB", + "size": 64 + }, + "fetchWidth": 8, + "max_loads_all_threads": 0, + "cpu_id": 0, + "fetchToDecodeDelay": 1, + "renameToDecodeDelay": 1, + "do_quiesce": true, + "renameToROBDelay": 1, + "power_model": null, + "max_insts_all_threads": 0, + "decodeWidth": 8, + "commitToFetchDelay": 1, + "needsTSO": false, + "smtIQThreshold": 100, + "workload": [ + { + "uid": 100, + "pid": 100, + "kvmInSE": false, + "cxx_class": "LiveProcess", + "executable": "/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64m/insttest", + "drivers": [], + "system": "system", + "gid": 100, + "eventq_index": 0, + "env": [], + "input": "cin", + "ppid": 99, + "type": "LiveProcess", + "cwd": "", + "simpoint": 0, + "euid": 100, + "path": "system.cpu.workload", + "max_stack_size": 67108864, + "name": "workload", + "cmd": [ + "insttest" + ], + "errout": "cerr", + "useArchPT": false, + "egid": 100, + "output": "cout" + } + ], + "name": "cpu", + "SSITSize": 1024, + "activity": 0, + "max_loads_any_thread": 0, + "tracer": { + "eventq_index": 0, + "path": "system.cpu.tracer", + "type": "ExeTracer", + "name": "tracer", + "cxx_class": "Trace::ExeTracer" + }, + "decodeToFetchDelay": 1, + "renameWidth": 8, + "numThreads": 1, + "squashWidth": 8, + "function_trace": false, + "backComSize": 5, + "decodeToRenameDelay": 1, + "store_set_clear_period": 250000, + "numPhysIntRegs": 256, + "p_state_clk_gate_max": 1000000000000, + "toL2Bus": { + "point_of_coherency": false, + "system": "system", + "response_latency": 1, + "cxx_class": "CoherentXBar", + "forward_latency": 0, + "clk_domain": "system.cpu_clk_domain", + "width": 32, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "master": { + "peer": [ + "system.cpu.l2cache.cpu_side" + ], + "role": "MASTER" + }, + "type": "CoherentXBar", + "frontend_latency": 1, + "slave": { + "peer": [ + "system.cpu.icache.mem_side", + "system.cpu.dcache.mem_side" + ], + "role": "SLAVE" + }, + "p_state_clk_gate_min": 1000, + "snoop_filter": { + "name": "snoop_filter", + "system": "system", + "max_capacity": 8388608, + "eventq_index": 0, + "cxx_class": "SnoopFilter", + "path": "system.cpu.toL2Bus.snoop_filter", + "type": "SnoopFilter", + "lookup_latency": 0 + }, + "power_model": null, + "path": "system.cpu.toL2Bus", + "snoop_response_latency": 1, + "name": "toL2Bus", + "p_state_clk_gate_bins": 20, + "use_default_range": false + }, + "p_state_clk_gate_min": 1000, + "fuPool": { + "name": "fuPool", + "FUList": [ + { + "count": 6, + "opList": [ + { + "opClass": "IntAlu", + "opLat": 1, + "name": "opList", + "pipelined": true, + "eventq_index": 0, + "cxx_class": "OpDesc", + "path": "system.cpu.fuPool.FUList0.opList", + "type": "OpDesc" + } + ], + "name": "FUList0", + "eventq_index": 0, + "cxx_class": "FUDesc", + "path": "system.cpu.fuPool.FUList0", + "type": "FUDesc" + }, + { + "count": 2, + "opList": [ + { + "opClass": "IntMult", + "opLat": 3, + "name": "opList0", + "pipelined": true, + "eventq_index": 0, + "cxx_class": "OpDesc", + "path": "system.cpu.fuPool.FUList1.opList0", + "type": "OpDesc" + }, + { + "opClass": "IntDiv", + "opLat": 20, + "name": "opList1", + "pipelined": false, + "eventq_index": 0, + "cxx_class": "OpDesc", + "path": "system.cpu.fuPool.FUList1.opList1", + "type": "OpDesc" + } + ], + "name": "FUList1", + "eventq_index": 0, + "cxx_class": "FUDesc", + "path": "system.cpu.fuPool.FUList1", + "type": "FUDesc" + }, + { + "count": 4, + "opList": [ + { + "opClass": "FloatAdd", + "opLat": 2, + "name": "opList0", + "pipelined": true, + "eventq_index": 0, + "cxx_class": "OpDesc", + "path": "system.cpu.fuPool.FUList2.opList0", + "type": "OpDesc" + }, + { + "opClass": "FloatCmp", + "opLat": 2, + "name": "opList1", + "pipelined": true, + "eventq_index": 0, + "cxx_class": "OpDesc", + "path": "system.cpu.fuPool.FUList2.opList1", + "type": "OpDesc" + }, + { + "opClass": "FloatCvt", + "opLat": 2, + "name": "opList2", + "pipelined": true, + "eventq_index": 0, + "cxx_class": "OpDesc", + "path": "system.cpu.fuPool.FUList2.opList2", + "type": "OpDesc" + } + ], + "name": "FUList2", + "eventq_index": 0, + "cxx_class": "FUDesc", + "path": "system.cpu.fuPool.FUList2", + "type": "FUDesc" + }, + { + "count": 2, + "opList": [ + { + "opClass": "FloatMult", + "opLat": 4, + "name": "opList0", + "pipelined": true, + "eventq_index": 0, + "cxx_class": "OpDesc", + "path": "system.cpu.fuPool.FUList3.opList0", + "type": "OpDesc" + }, + { + "opClass": "FloatMultAcc", + "opLat": 5, + "name": "opList1", + "pipelined": true, + "eventq_index": 0, + "cxx_class": "OpDesc", + "path": "system.cpu.fuPool.FUList3.opList1", + "type": "OpDesc" + }, + { + "opClass": "FloatMisc", + "opLat": 3, + "name": "opList2", + "pipelined": true, + "eventq_index": 0, + "cxx_class": "OpDesc", + "path": "system.cpu.fuPool.FUList3.opList2", + "type": "OpDesc" + }, + { + "opClass": "FloatDiv", + "opLat": 12, + "name": "opList3", + "pipelined": false, + "eventq_index": 0, + "cxx_class": "OpDesc", + "path": "system.cpu.fuPool.FUList3.opList3", + "type": "OpDesc" + }, + { + "opClass": "FloatSqrt", + "opLat": 24, + "name": "opList4", + "pipelined": false, + "eventq_index": 0, + "cxx_class": "OpDesc", + "path": "system.cpu.fuPool.FUList3.opList4", + "type": "OpDesc" + } + ], + "name": "FUList3", + "eventq_index": 0, + "cxx_class": "FUDesc", + "path": "system.cpu.fuPool.FUList3", + "type": "FUDesc" + }, + { + "count": 0, + "opList": [ + { + "opClass": "MemRead", + "opLat": 1, + "name": "opList0", + "pipelined": true, + "eventq_index": 0, + "cxx_class": "OpDesc", + "path": "system.cpu.fuPool.FUList4.opList0", + "type": "OpDesc" + }, + { + "opClass": "FloatMemRead", + "opLat": 1, + "name": "opList1", + "pipelined": true, + "eventq_index": 0, + "cxx_class": "OpDesc", + "path": "system.cpu.fuPool.FUList4.opList1", + "type": "OpDesc" + } + ], + "name": "FUList4", + "eventq_index": 0, + "cxx_class": "FUDesc", + "path": "system.cpu.fuPool.FUList4", + "type": "FUDesc" + }, + { + "count": 4, + "opList": [ + { + "opClass": "SimdAdd", + "opLat": 1, + "name": "opList00", + "pipelined": true, + "eventq_index": 0, + "cxx_class": "OpDesc", + "path": "system.cpu.fuPool.FUList5.opList00", + "type": "OpDesc" + }, + { + "opClass": "SimdAddAcc", + "opLat": 1, + "name": "opList01", + "pipelined": true, + "eventq_index": 0, + "cxx_class": "OpDesc", + "path": "system.cpu.fuPool.FUList5.opList01", + "type": "OpDesc" + }, + { + "opClass": "SimdAlu", + "opLat": 1, + "name": "opList02", + "pipelined": true, + "eventq_index": 0, + "cxx_class": "OpDesc", + "path": "system.cpu.fuPool.FUList5.opList02", + "type": "OpDesc" + }, + { + "opClass": "SimdCmp", + "opLat": 1, + "name": "opList03", + "pipelined": true, + "eventq_index": 0, + "cxx_class": "OpDesc", + "path": "system.cpu.fuPool.FUList5.opList03", + "type": "OpDesc" + }, + { + "opClass": "SimdCvt", + "opLat": 1, + "name": "opList04", + "pipelined": true, + "eventq_index": 0, + "cxx_class": "OpDesc", + "path": "system.cpu.fuPool.FUList5.opList04", + "type": "OpDesc" + }, + { + "opClass": "SimdMisc", + "opLat": 1, + "name": "opList05", + "pipelined": true, + "eventq_index": 0, + "cxx_class": "OpDesc", + "path": "system.cpu.fuPool.FUList5.opList05", + "type": "OpDesc" + }, + { + "opClass": "SimdMult", + "opLat": 1, + "name": "opList06", + "pipelined": true, + "eventq_index": 0, + "cxx_class": "OpDesc", + "path": "system.cpu.fuPool.FUList5.opList06", + "type": "OpDesc" + }, + { + "opClass": "SimdMultAcc", + "opLat": 1, + "name": "opList07", + "pipelined": true, + "eventq_index": 0, + "cxx_class": "OpDesc", + "path": "system.cpu.fuPool.FUList5.opList07", + "type": "OpDesc" + }, + { + "opClass": "SimdShift", + "opLat": 1, + "name": "opList08", + "pipelined": true, + "eventq_index": 0, + "cxx_class": "OpDesc", + "path": "system.cpu.fuPool.FUList5.opList08", + "type": "OpDesc" + }, + { + "opClass": "SimdShiftAcc", + "opLat": 1, + "name": "opList09", + "pipelined": true, + "eventq_index": 0, + "cxx_class": "OpDesc", + "path": "system.cpu.fuPool.FUList5.opList09", + "type": "OpDesc" + }, + { + "opClass": "SimdSqrt", + "opLat": 1, + "name": "opList10", + "pipelined": true, + "eventq_index": 0, + "cxx_class": "OpDesc", + "path": "system.cpu.fuPool.FUList5.opList10", + "type": "OpDesc" + }, + { + "opClass": "SimdFloatAdd", + "opLat": 1, + "name": "opList11", + "pipelined": true, + "eventq_index": 0, + "cxx_class": "OpDesc", + "path": "system.cpu.fuPool.FUList5.opList11", + "type": "OpDesc" + }, + { + "opClass": "SimdFloatAlu", + "opLat": 1, + "name": "opList12", + "pipelined": true, + "eventq_index": 0, + "cxx_class": "OpDesc", + "path": "system.cpu.fuPool.FUList5.opList12", + "type": "OpDesc" + }, + { + "opClass": "SimdFloatCmp", + "opLat": 1, + "name": "opList13", + "pipelined": true, + "eventq_index": 0, + "cxx_class": "OpDesc", + "path": "system.cpu.fuPool.FUList5.opList13", + "type": "OpDesc" + }, + { + "opClass": "SimdFloatCvt", + "opLat": 1, + "name": "opList14", + "pipelined": true, + "eventq_index": 0, + "cxx_class": "OpDesc", + "path": "system.cpu.fuPool.FUList5.opList14", + "type": "OpDesc" + }, + { + "opClass": "SimdFloatDiv", + "opLat": 1, + "name": "opList15", + "pipelined": true, + "eventq_index": 0, + "cxx_class": "OpDesc", + "path": "system.cpu.fuPool.FUList5.opList15", + "type": "OpDesc" + }, + { + "opClass": "SimdFloatMisc", + "opLat": 1, + "name": "opList16", + "pipelined": true, + "eventq_index": 0, + "cxx_class": "OpDesc", + "path": "system.cpu.fuPool.FUList5.opList16", + "type": "OpDesc" + }, + { + "opClass": "SimdFloatMult", + "opLat": 1, + "name": "opList17", + "pipelined": true, + "eventq_index": 0, + "cxx_class": "OpDesc", + "path": "system.cpu.fuPool.FUList5.opList17", + "type": "OpDesc" + }, + { + "opClass": "SimdFloatMultAcc", + "opLat": 1, + "name": "opList18", + "pipelined": true, + "eventq_index": 0, + "cxx_class": "OpDesc", + "path": "system.cpu.fuPool.FUList5.opList18", + "type": "OpDesc" + }, + { + "opClass": "SimdFloatSqrt", + "opLat": 1, + "name": "opList19", + "pipelined": true, + "eventq_index": 0, + "cxx_class": "OpDesc", + "path": "system.cpu.fuPool.FUList5.opList19", + "type": "OpDesc" + } + ], + "name": "FUList5", + "eventq_index": 0, + "cxx_class": "FUDesc", + "path": "system.cpu.fuPool.FUList5", + "type": "FUDesc" + }, + { + "count": 0, + "opList": [ + { + "opClass": "MemWrite", + "opLat": 1, + "name": "opList0", + "pipelined": true, + "eventq_index": 0, + "cxx_class": "OpDesc", + "path": "system.cpu.fuPool.FUList6.opList0", + "type": "OpDesc" + }, + { + "opClass": "FloatMemWrite", + "opLat": 1, + "name": "opList1", + "pipelined": true, + "eventq_index": 0, + "cxx_class": "OpDesc", + "path": "system.cpu.fuPool.FUList6.opList1", + "type": "OpDesc" + } + ], + "name": "FUList6", + "eventq_index": 0, + "cxx_class": "FUDesc", + "path": "system.cpu.fuPool.FUList6", + "type": "FUDesc" + }, + { + "count": 4, + "opList": [ + { + "opClass": "MemRead", + "opLat": 1, + "name": "opList0", + "pipelined": true, + "eventq_index": 0, + "cxx_class": "OpDesc", + "path": "system.cpu.fuPool.FUList7.opList0", + "type": "OpDesc" + }, + { + "opClass": "MemWrite", + "opLat": 1, + "name": "opList1", + "pipelined": true, + "eventq_index": 0, + "cxx_class": "OpDesc", + "path": "system.cpu.fuPool.FUList7.opList1", + "type": "OpDesc" + }, + { + "opClass": "FloatMemRead", + "opLat": 1, + "name": "opList2", + "pipelined": true, + "eventq_index": 0, + "cxx_class": "OpDesc", + "path": "system.cpu.fuPool.FUList7.opList2", + "type": "OpDesc" + }, + { + "opClass": "FloatMemWrite", + "opLat": 1, + "name": "opList3", + "pipelined": true, + "eventq_index": 0, + "cxx_class": "OpDesc", + "path": "system.cpu.fuPool.FUList7.opList3", + "type": "OpDesc" + } + ], + "name": "FUList7", + "eventq_index": 0, + "cxx_class": "FUDesc", + "path": "system.cpu.fuPool.FUList7", + "type": "FUDesc" + }, + { + "count": 1, + "opList": [ + { + "opClass": "IprAccess", + "opLat": 3, + "name": "opList", + "pipelined": false, + "eventq_index": 0, + "cxx_class": "OpDesc", + "path": "system.cpu.fuPool.FUList8.opList", + "type": "OpDesc" + } + ], + "name": "FUList8", + "eventq_index": 0, + "cxx_class": "FUDesc", + "path": "system.cpu.fuPool.FUList8", + "type": "FUDesc" + } + ], + "eventq_index": 0, + "cxx_class": "FUPool", + "path": "system.cpu.fuPool", + "type": "FUPool" + }, + "socket_id": 0, + "renameToFetchDelay": 1, + "icache": { + "cpu_side": { + "peer": "system.cpu.icache_port", + "role": "SLAVE" + }, + "clusivity": "mostly_incl", + "prefetcher": null, + "system": "system", + "write_buffers": 8, + "response_latency": 2, + "cxx_class": "Cache", + "size": 131072, + "type": "Cache", + "clk_domain": "system.cpu_clk_domain", + "max_miss_count": 0, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "mem_side": { + "peer": "system.cpu.toL2Bus.slave[0]", + "role": "MASTER" + }, + "mshrs": 4, + "writeback_clean": true, + "p_state_clk_gate_min": 1000, + "tags": { + "size": 131072, + "tag_latency": 2, + "name": "tags", + "p_state_clk_gate_min": 1000, + "eventq_index": 0, + "p_state_clk_gate_bins": 20, + "default_p_state": "UNDEFINED", + "clk_domain": "system.cpu_clk_domain", + "power_model": null, + "sequential_access": false, + "assoc": 2, + "cxx_class": "LRU", + "p_state_clk_gate_max": 1000000000000, + "path": "system.cpu.icache.tags", + "block_size": 64, + "type": "LRU", + "data_latency": 2 + }, + "tgts_per_mshr": 20, + "demand_mshr_reserve": 1, + "power_model": null, + "addr_ranges": [ + "0:18446744073709551615:0:0:0:0" + ], + "is_read_only": true, + "prefetch_on_access": false, + "path": "system.cpu.icache", + "data_latency": 2, + "tag_latency": 2, + "name": "icache", + "p_state_clk_gate_bins": 20, + "sequential_access": false, + "assoc": 2 + }, + "path": "system.cpu", + "numRobs": 1, + "switched_out": false, + "smtLSQPolicy": "Partitioned", + "fetchBufferSize": 64, + "simpoint_start_insts": [], + "max_insts_any_thread": 0, + "smtROBThreshold": 100, + "numIQEntries": 64, + "branchPred": { + "numThreads": 1, + "BTBEntries": 4096, + "cxx_class": "TournamentBP", + "indirectPathLength": 3, + "globalCtrBits": 2, + "choicePredictorSize": 8192, + "indirectHashGHR": true, + "eventq_index": 0, + "localHistoryTableSize": 2048, + "type": "TournamentBP", + "indirectSets": 256, + "indirectWays": 2, + "choiceCtrBits": 2, + "useIndirect": true, + "localCtrBits": 2, + "path": "system.cpu.branchPred", + "localPredictorSize": 2048, + "RASSize": 16, + "globalPredictorSize": 8192, + "name": "branchPred", + "indirectHashTargets": true, + "instShiftAmt": 2, + "indirectTagSize": 16, + "BTBTagSize": 16 + }, + "LFSTSize": 1024, + "isa": [ + { + "eventq_index": 0, + "path": "system.cpu.isa", + "type": "RiscvISA", + "name": "isa", + "cxx_class": "RiscvISA::ISA" + } + ], + "smtROBPolicy": "Partitioned", + "iewToFetchDelay": 1, + "do_statistics_insts": true, + "dispatchWidth": 8, + "dcache": { + "cpu_side": { + "peer": "system.cpu.dcache_port", + "role": "SLAVE" + }, + "clusivity": "mostly_incl", + "prefetcher": null, + "system": "system", + "write_buffers": 8, + "response_latency": 2, + "cxx_class": "Cache", + "size": 262144, + "type": "Cache", + "clk_domain": "system.cpu_clk_domain", + "max_miss_count": 0, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "mem_side": { + "peer": "system.cpu.toL2Bus.slave[1]", + "role": "MASTER" + }, + "mshrs": 4, + "writeback_clean": false, + "p_state_clk_gate_min": 1000, + "tags": { + "size": 262144, + "tag_latency": 2, + "name": "tags", + "p_state_clk_gate_min": 1000, + "eventq_index": 0, + "p_state_clk_gate_bins": 20, + "default_p_state": "UNDEFINED", + "clk_domain": "system.cpu_clk_domain", + "power_model": null, + "sequential_access": false, + "assoc": 2, + "cxx_class": "LRU", + "p_state_clk_gate_max": 1000000000000, + "path": "system.cpu.dcache.tags", + "block_size": 64, + "type": "LRU", + "data_latency": 2 + }, + "tgts_per_mshr": 20, + "demand_mshr_reserve": 1, + "power_model": null, + "addr_ranges": [ + "0:18446744073709551615:0:0:0:0" + ], + "is_read_only": false, + "prefetch_on_access": false, + "path": "system.cpu.dcache", + "data_latency": 2, + "tag_latency": 2, + "name": "dcache", + "p_state_clk_gate_bins": 20, + "sequential_access": false, + "assoc": 2 + }, + "commitToDecodeDelay": 1, + "smtIQPolicy": "Partitioned", + "issueWidth": 8, + "LSQCheckLoads": true, + "commitToRenameDelay": 1, + "cachePorts": 200, + "system": "system", + "checker": null, + "numPhysFloatRegs": 256, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "type": "DerivO3CPU", + "wbWidth": 8, + "interrupts": [ + { + "eventq_index": 0, + "path": "system.cpu.interrupts", + "type": "RiscvInterrupts", + "name": "interrupts", + "cxx_class": "RiscvISA::Interrupts" + } + ], + "smtCommitPolicy": "RoundRobin", + "issueToExecuteDelay": 1, + "dtb": { + "name": "dtb", + "eventq_index": 0, + "cxx_class": "RiscvISA::TLB", + "path": "system.cpu.dtb", + "type": "RiscvTLB", + "size": 64 + }, + "numROBEntries": 192, + "fetchQueueSize": 32, + "iewToCommitDelay": 1, + "smtNumFetchingThreads": 1, + "forwardComSize": 5, + "do_checkpoint_insts": true, + "cxx_class": "DerivO3CPU", + "commitToIEWDelay": 1, + "commitWidth": 8, + "clk_domain": "system.cpu_clk_domain", + "function_trace_start": 0, + "smtFetchPolicy": "SingleThread", + "profile": 0, + "icache_port": { + "peer": "system.cpu.icache.cpu_side", + "role": "MASTER" + }, + "dcache_port": { + "peer": "system.cpu.dcache.cpu_side", + "role": "MASTER" + }, + "LSQDepCheckShift": 4, + "trapLatency": 13, + "iewToDecodeDelay": 1, + "numPhysCCRegs": 0, + "renameToIEWDelay": 2, + "p_state_clk_gate_bins": 20, + "progress_interval": 0, + "LQEntries": 32 + } + ], + "multi_thread": false, + "exit_on_work_items": false, + "work_item_id": -1, + "num_work_ids": 16 + }, + "time_sync_period": 100000000000, + "eventq_index": 0, + "time_sync_spin_threshold": 100000000, + "cxx_class": "Root", + "path": "root", + "time_sync_enable": false, + "type": "Root", + "full_system": false +}
\ No newline at end of file diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/o3-timing/simerr b/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/o3-timing/simerr new file mode 100755 index 000000000..85a6a33ad --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/o3-timing/simerr @@ -0,0 +1,4 @@ +warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes) +warn: Unknown operating system; assuming Linux. +warn: Sockets disabled, not accepting gdb connections +warn: ClockedObject: More than one power state change request encountered within the same simulation tick diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/o3-timing/simout b/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/o3-timing/simout new file mode 100755 index 000000000..0c05eb2fe --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/o3-timing/simout @@ -0,0 +1,51 @@ +Redirecting stdout to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64m/o3-timing/simout +Redirecting stderr to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64m/o3-timing/simerr +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled Nov 30 2016 14:33:35 +gem5 started Nov 30 2016 16:18:44 +gem5 executing on zizzer, pid 34095 +command line: /z/powerjg/gem5-upstream/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64m/o3-timing -re /z/powerjg/gem5-upstream/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64m/o3-timing + +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. +mul: PASS +mul, overflow: PASS +mulh: PASS +mulh, negative: PASS +mulh, all bits set: PASS +mulhsu, all bits set: PASS +mulhsu: PASS +mulhu: PASS +mulhu, all bits set: PASS +div: PASS +div/0: PASS +div, overflow: PASS +divu: PASS +divu/0: PASS +divu, "overflow": PASS +rem: PASS +rem/0: PASS +rem, overflow: PASS +remu: PASS +remu/0: PASS +remu, "overflow": PASS +mulw, truncate: PASS +mulw, overflow: PASS +divw, truncate: PASS +divw/0: PASS +divw, overflow: PASS +divuw, truncate: PASS +divuw/0: PASS +divuw, "overflow": PASS +divuw, sign extend: PASS +remw, truncate: PASS +remw/0: PASS +remw, overflow: PASS +remuw, truncate: PASS +remuw/0: PASS +remuw, "overflow": PASS +remuw, sign extend: PASS +Exiting @ tick 66726000 because target called exit() diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/o3-timing/stats.txt b/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/o3-timing/stats.txt new file mode 100644 index 000000000..0be26640f --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/o3-timing/stats.txt @@ -0,0 +1,1006 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.000067 # Number of seconds simulated +sim_ticks 66726000 # Number of ticks simulated +final_tick 66726000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 30660 # Simulator instruction rate (inst/s) +host_op_rate 30660 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 18058105 # Simulator tick rate (ticks/s) +host_mem_usage 245440 # Number of bytes of host memory used +host_seconds 3.70 # Real time elapsed on the host +sim_insts 113291 # Number of instructions simulated +sim_ops 113291 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 66726000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 49472 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 16960 # Number of bytes read from this memory +system.physmem.bytes_read::total 66432 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 49472 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 49472 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 773 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 265 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1038 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 741420136 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 254173785 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 995593921 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 741420136 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 741420136 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 741420136 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 254173785 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 995593921 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1039 # Number of read requests accepted +system.physmem.writeReqs 0 # Number of write requests accepted +system.physmem.readBursts 1039 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 66496 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue +system.physmem.bytesWritten 0 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 66496 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 89 # Per bank write bursts +system.physmem.perBankRdBursts::1 8 # Per bank write bursts +system.physmem.perBankRdBursts::2 16 # Per bank write bursts +system.physmem.perBankRdBursts::3 108 # Per bank write bursts +system.physmem.perBankRdBursts::4 64 # Per bank write bursts +system.physmem.perBankRdBursts::5 91 # Per bank write bursts +system.physmem.perBankRdBursts::6 61 # Per bank write bursts +system.physmem.perBankRdBursts::7 30 # Per bank write bursts +system.physmem.perBankRdBursts::8 56 # Per bank write bursts +system.physmem.perBankRdBursts::9 76 # Per bank write bursts +system.physmem.perBankRdBursts::10 79 # Per bank write bursts +system.physmem.perBankRdBursts::11 53 # Per bank write bursts +system.physmem.perBankRdBursts::12 133 # Per bank write bursts +system.physmem.perBankRdBursts::13 64 # Per bank write bursts +system.physmem.perBankRdBursts::14 104 # Per bank write bursts +system.physmem.perBankRdBursts::15 7 # Per bank write bursts +system.physmem.perBankWrBursts::0 0 # Per bank write bursts +system.physmem.perBankWrBursts::1 0 # Per bank write bursts +system.physmem.perBankWrBursts::2 0 # Per bank write bursts +system.physmem.perBankWrBursts::3 0 # Per bank write bursts +system.physmem.perBankWrBursts::4 0 # Per bank write bursts +system.physmem.perBankWrBursts::5 0 # Per bank write bursts +system.physmem.perBankWrBursts::6 0 # Per bank write bursts +system.physmem.perBankWrBursts::7 0 # Per bank write bursts +system.physmem.perBankWrBursts::8 0 # Per bank write bursts +system.physmem.perBankWrBursts::9 0 # Per bank write bursts +system.physmem.perBankWrBursts::10 0 # Per bank write bursts +system.physmem.perBankWrBursts::11 0 # Per bank write bursts +system.physmem.perBankWrBursts::12 0 # Per bank write bursts +system.physmem.perBankWrBursts::13 0 # Per bank write bursts +system.physmem.perBankWrBursts::14 0 # Per bank write bursts +system.physmem.perBankWrBursts::15 0 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 66707000 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 1039 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 0 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 580 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 293 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 111 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 50 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 205 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 313.131707 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 191.178317 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 319.046077 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 71 34.63% 34.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 47 22.93% 57.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 29 14.15% 71.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 11 5.37% 77.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 11 5.37% 82.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 6 2.93% 85.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 3 1.46% 86.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 5 2.44% 89.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 22 10.73% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 205 # Bytes accessed per row activation +system.physmem.totQLat 13576000 # Total ticks spent queuing +system.physmem.totMemAccLat 33057250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 5195000 # Total ticks spent in databus transfers +system.physmem.avgQLat 13066.41 # Average queueing delay per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 31816.41 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 996.55 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 996.55 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.busUtil 7.79 # Data bus utilization in percentage +system.physmem.busUtilRead 7.79 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.69 # Average read queue length when enqueuing +system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing +system.physmem.readRowHits 821 # Number of row buffer hits during reads +system.physmem.writeRowHits 0 # Number of row buffer hits during writes +system.physmem.readRowHitRate 79.02 # Row buffer hit rate for reads +system.physmem.writeRowHitRate nan # Row buffer hit rate for writes +system.physmem.avgGap 64203.08 # Average gap between requests +system.physmem.pageHitRate 79.02 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 835380 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 413655 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 3334380 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 4917120.000000 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 6568110 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 113280 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 22288140 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 1209600 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 39679665 # Total energy per rank (pJ) +system.physmem_0.averagePower 594.663495 # Core power per rank (mW) +system.physmem_0.totalIdleTime 51714500 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 59500 # Time in different power states +system.physmem_0.memoryStateTime::REF 2080000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 0 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 3148750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 12569500 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 48868250 # Time in different power states +system.physmem_1.actEnergy 721140 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 364320 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 4084080 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 4917120.000000 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 6353220 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 143040 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 20623170 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 2762880 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 39968970 # Total energy per rank (pJ) +system.physmem_1.averagePower 598.999194 # Core power per rank (mW) +system.physmem_1.totalIdleTime 52416000 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 150500 # Time in different power states +system.physmem_1.memoryStateTime::REF 2080000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 0 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 7195250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 12079500 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 45220750 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 66726000 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 39966 # Number of BP lookups +system.cpu.branchPred.condPredicted 24999 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 2671 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 33955 # Number of BTB lookups +system.cpu.branchPred.BTBHits 19441 # Number of BTB hits +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 57.255191 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 0 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 7662 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 3924 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 3738 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 1190 # Number of mispredicted indirect branches. +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 45 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 66726000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 133453 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.fetch.icacheStallCycles 32838 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 168786 # Number of instructions fetch has processed +system.cpu.fetch.Branches 39966 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 23365 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 44071 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 5482 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 503 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.IcacheWaitRetryStallCycles 181 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 22322 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 1285 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 80334 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.101053 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.833149 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 43916 54.67% 54.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 3396 4.23% 58.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 6102 7.60% 66.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 5424 6.75% 73.24% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2470 3.07% 76.32% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 6562 8.17% 84.48% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1937 2.41% 86.90% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1614 2.01% 88.91% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 8913 11.09% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 80334 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.299476 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.264760 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 33037 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 11879 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 32363 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 923 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 2132 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 6308 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 640 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 154953 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 1928 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 2132 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 34625 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 3379 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 1413 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 31599 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 7186 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 148471 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 97 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 6 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 431 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 6512 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 101480 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 195404 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 195404 # Number of integer rename lookups +system.cpu.rename.CommittedMaps 76188 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 25292 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 58 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 58 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 3325 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 28879 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 22638 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 630 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 17 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 137222 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 69 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 131068 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 381 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 23997 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 13432 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 22 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 80334 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.631538 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.013515 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 38041 47.35% 47.35% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 10252 12.76% 60.12% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 8094 10.08% 70.19% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 8074 10.05% 80.24% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 5916 7.36% 87.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 4749 5.91% 93.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 3775 4.70% 98.22% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1117 1.39% 99.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 316 0.39% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 80334 # Number of insts issued each cycle +system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 175 6.09% 6.09% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 6.09% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 6.09% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.09% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.09% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.09% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 6.09% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 6.09% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.09% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 0 0.00% 6.09% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 6.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 6.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.09% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1363 47.43% 53.51% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 1336 46.49% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemRead 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemWrite 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.FU_type_0::No_OpClass 45 0.03% 0.03% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 81693 62.33% 62.36% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 129 0.10% 62.46% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 30 0.02% 62.48% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.48% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.48% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.48% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.48% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 62.48% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.48% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 62.48% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.48% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 27948 21.32% 83.81% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 21223 16.19% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemRead 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemWrite 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::total 131068 # Type of FU issued +system.cpu.iq.rate 0.982129 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2874 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.021928 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 345725 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 161326 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 125053 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 133897 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 2531 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread0.squashedLoads 5099 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 4 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 35 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 2926 # Number of stores squashed +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread0.rescheduledLoads 4 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 101 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu.iew.iewSquashCycles 2132 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 2287 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 246 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 137289 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 950 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 28879 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 22638 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 67 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 254 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 35 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 498 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 1893 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 2391 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 126811 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 27146 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 4257 # Number of squashed instructions skipped in execute +system.cpu.iew.exec_swp 0 # number of swp insts executed +system.cpu.iew.exec_nop 0 # number of nop insts executed +system.cpu.iew.exec_refs 47872 # number of memory reference insts executed +system.cpu.iew.exec_branches 29089 # Number of branches executed +system.cpu.iew.exec_stores 20726 # Number of stores executed +system.cpu.iew.exec_rate 0.950230 # Inst execution rate +system.cpu.iew.wb_sent 125714 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 125053 # cumulative count of insts written-back +system.cpu.iew.wb_producers 49299 # num instructions producing a value +system.cpu.iew.wb_consumers 72928 # num instructions consuming a value +system.cpu.iew.wb_rate 0.937056 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.675996 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 24018 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 45 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 2062 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 75915 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.492340 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.298348 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 42174 55.55% 55.55% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 10802 14.23% 69.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 5429 7.15% 76.93% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 4052 5.34% 82.27% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 3273 4.31% 86.58% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 3050 4.02% 90.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 2519 3.32% 93.92% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 909 1.20% 95.12% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 3707 4.88% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 75915 # Number of insts commited each cycle +system.cpu.commit.committedInsts 113291 # Number of instructions committed +system.cpu.commit.committedOps 113291 # Number of ops (including micro ops) committed +system.cpu.commit.swp_count 0 # Number of s/w prefetches committed +system.cpu.commit.refs 43492 # Number of memory references committed +system.cpu.commit.loads 23780 # Number of loads committed +system.cpu.commit.membars 0 # Number of memory barriers committed +system.cpu.commit.branches 25920 # Number of branches committed +system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. +system.cpu.commit.int_insts 113291 # Number of committed integer instructions. +system.cpu.commit.function_calls 8529 # Number of function calls committed. +system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 69651 61.48% 61.48% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 122 0.11% 61.59% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 26 0.02% 61.61% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 0 0.00% 61.61% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 0 0.00% 61.61% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 0 0.00% 61.61% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 0 0.00% 61.61% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 61.61% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 0 0.00% 61.61% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMisc 0 0.00% 61.61% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 61.61% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 0 0.00% 61.61% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 61.61% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 0 0.00% 61.61% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 0 0.00% 61.61% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 61.61% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 0 0.00% 61.61% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 61.61% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 61.61% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 61.61% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 61.61% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 61.61% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 61.61% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 61.61% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 61.61% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 61.61% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 61.61% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 61.61% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 61.61% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 61.61% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 61.61% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 23780 20.99% 82.60% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 19712 17.40% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::total 113291 # Class of committed instruction +system.cpu.commit.bw_lim_events 3707 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 208932 # The number of ROB reads +system.cpu.rob.rob_writes 279096 # The number of ROB writes +system.cpu.timesIdled 413 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 53119 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 113291 # Number of Instructions Simulated +system.cpu.committedOps 113291 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 1.177966 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.177966 # CPI: Total CPI of All Threads +system.cpu.ipc 0.848921 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.848921 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 166154 # number of integer regfile reads +system.cpu.int_regfile_writes 85972 # number of integer regfile writes +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 66726000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 0 # number of replacements +system.cpu.dcache.tags.tagsinuse 217.973737 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 42393 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 265 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 159.973585 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 217.973737 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.053216 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.053216 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 265 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 8 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 257 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.064697 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 88473 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 88473 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 66726000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 24147 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 24147 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 18246 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 18246 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 42393 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 42393 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 42393 # number of overall hits +system.cpu.dcache.overall_hits::total 42393 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 245 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 245 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1466 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1466 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 1711 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1711 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1711 # number of overall misses +system.cpu.dcache.overall_misses::total 1711 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 20376500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 20376500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 95969940 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 95969940 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 116346440 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 116346440 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 116346440 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 116346440 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 24392 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 24392 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 19712 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 19712 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 44104 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 44104 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 44104 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 44104 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.010044 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.010044 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.074371 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.074371 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.038795 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.038795 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.038795 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.038795 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 83169.387755 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 83169.387755 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65463.806276 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 65463.806276 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 67999.088252 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 67999.088252 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 67999.088252 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 67999.088252 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 5526 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 63 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 87.714286 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 175 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 175 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1269 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1269 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1444 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1444 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1444 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1444 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 70 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 70 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 197 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 197 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 267 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 267 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 267 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 267 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6394500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 6394500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 15710500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 15710500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 22105000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 22105000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 22105000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 22105000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002870 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002870 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009994 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009994 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006054 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.006054 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006054 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.006054 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 91350 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 91350 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79748.730964 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79748.730964 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 82790.262172 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 82790.262172 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 82790.262172 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 82790.262172 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 66726000 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 16 # number of replacements +system.cpu.icache.tags.tagsinuse 390.097209 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 21273 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 775 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 27.449032 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 390.097209 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.190477 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.190477 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 759 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 79 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 680 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.370605 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 45403 # Number of tag accesses +system.cpu.icache.tags.data_accesses 45403 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 66726000 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 21273 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 21273 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 21273 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 21273 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 21273 # number of overall hits +system.cpu.icache.overall_hits::total 21273 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1041 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1041 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1041 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1041 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1041 # number of overall misses +system.cpu.icache.overall_misses::total 1041 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 81501497 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 81501497 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 81501497 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 81501497 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 81501497 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 81501497 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 22314 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 22314 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 22314 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 22314 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 22314 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 22314 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.046652 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.046652 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.046652 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.046652 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.046652 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.046652 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 78291.543708 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 78291.543708 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 78291.543708 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 78291.543708 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 78291.543708 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 78291.543708 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 2316 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 36 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 64.333333 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.icache.writebacks::writebacks 16 # number of writebacks +system.cpu.icache.writebacks::total 16 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 266 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 266 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 266 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 266 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 266 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 266 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 775 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 775 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 775 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 775 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 775 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 775 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 65524999 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 65524999 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 65524999 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 65524999 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 65524999 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 65524999 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.034732 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.034732 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.034732 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.034732 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.034732 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.034732 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 84548.385806 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 84548.385806 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 84548.385806 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 84548.385806 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 84548.385806 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 84548.385806 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 66726000 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.replacements 0 # number of replacements +system.cpu.l2cache.tags.tagsinuse 612.345284 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 16 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 1038 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.015414 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::cpu.inst 394.329847 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 218.015437 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.012034 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.006653 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.018687 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 1038 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 87 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 951 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.031677 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 9486 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 9486 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 66726000 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.WritebackClean_hits::writebacks 16 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 16 # number of WritebackClean hits +system.cpu.l2cache.ReadExReq_misses::cpu.data 197 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 197 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 773 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 773 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 70 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 70 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.inst 773 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 267 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 1040 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 773 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 267 # number of overall misses +system.cpu.l2cache.overall_misses::total 1040 # number of overall misses +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 15415000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 15415000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 64356500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 64356500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 6291000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 6291000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 64356500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 21706000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 86062500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 64356500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 21706000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 86062500 # number of overall miss cycles +system.cpu.l2cache.WritebackClean_accesses::writebacks 16 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 16 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 197 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 197 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 773 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 773 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 70 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 70 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 773 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 267 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 1040 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 773 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 267 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 1040 # number of overall (read+write) accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 1 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 1 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 1 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 1 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78248.730964 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 78248.730964 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 83255.498060 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 83255.498060 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 89871.428571 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 89871.428571 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 83255.498060 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 81295.880150 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 82752.403846 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 83255.498060 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 81295.880150 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 82752.403846 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 197 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 197 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 773 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 773 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 70 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 70 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 773 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 267 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 1040 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 773 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 267 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 1040 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 13445000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 13445000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 56626500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 56626500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 5611000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 5611000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 56626500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 19056000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 75682500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 56626500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 19056000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 75682500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 1 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68248.730964 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68248.730964 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 73255.498060 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 73255.498060 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 80157.142857 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 80157.142857 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 73255.498060 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71370.786517 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72771.634615 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 73255.498060 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71370.786517 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72771.634615 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 1058 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 18 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 66726000 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 843 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 16 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 197 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 197 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 775 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 70 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1564 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 532 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 2096 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50496 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 16960 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 67456 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 2 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 128 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 1042 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.001919 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.043790 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 1040 99.81% 99.81% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 2 0.19% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 1042 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 545000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.8 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 1162500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 1.7 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 397500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.6 # Layer utilization (%) +system.membus.snoop_filter.tot_requests 1039 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 66726000 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 841 # Transaction distribution +system.membus.trans_dist::ReadExReq 197 # Transaction distribution +system.membus.trans_dist::ReadExResp 197 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 842 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 2077 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 2077 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 66432 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 66432 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoopTraffic 0 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 1039 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 1039 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 1039 # Request fanout histogram +system.membus.reqLayer0.occupancy 1253500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 1.9 # Layer utilization (%) +system.membus.respLayer1.occupancy 5477500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 8.2 # Layer utilization (%) + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/simple-atomic/config.ini b/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/simple-atomic/config.ini new file mode 100644 index 000000000..9b465ed9b --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/simple-atomic/config.ini @@ -0,0 +1,211 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain +boot_osflags=a +cache_line_size=64 +clk_domain=system.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +exit_on_work_items=false +init_param=0 +kernel= +kernel_addr_check=true +load_addr_mask=1099511627775 +load_offset=0 +mem_mode=atomic +mem_ranges= +memories=system.physmem +mmap_using_noreserve=false +multi_thread=false +num_work_ids=16 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +readfile= +symbolfile= +thermal_components= +thermal_model=Null +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=AtomicSimpleCPU +children=dtb interrupts isa itb tracer workload +branchPred=Null +checker=Null +clk_domain=system.cpu_clk_domain +cpu_id=0 +default_p_state=UNDEFINED +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +eventq_index=0 +fastmem=false +function_trace=false +function_trace_start=0 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +profile=0 +progress_interval=0 +simpoint_start_insts= +simulate_data_stalls=false +simulate_inst_stalls=false +socket_id=0 +switched_out=false +system=system +tracer=system.cpu.tracer +width=1 +workload=system.cpu.workload +dcache_port=system.membus.slave[2] +icache_port=system.membus.slave[1] + +[system.cpu.dtb] +type=RiscvTLB +eventq_index=0 +size=64 + +[system.cpu.interrupts] +type=RiscvInterrupts +eventq_index=0 + +[system.cpu.isa] +type=RiscvISA +eventq_index=0 + +[system.cpu.itb] +type=RiscvTLB +eventq_index=0 +size=64 + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=LiveProcess +cmd=insttest +cwd= +drivers= +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable=/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64m/insttest +gid=100 +input=cin +kvmInSE=false +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=0 +system=system +uid=100 +useArchPT=false + +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000000 + +[system.membus] +type=CoherentXBar +children=snoop_filter +clk_domain=system.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +forward_latency=4 +frontend_latency=3 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +point_of_coherency=true +power_model=Null +response_latency=2 +snoop_filter=system.membus.snoop_filter +snoop_response_latency=4 +system=system +use_default_range=false +width=16 +master=system.physmem.port +slave=system.system_port system.cpu.icache_port system.cpu.dcache_port + +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + +[system.physmem] +type=SimpleMemory +bandwidth=73.000000 +clk_domain=system.clk_domain +conf_table_reported=true +default_p_state=UNDEFINED +eventq_index=0 +in_addr_map=true +kvm_map=true +latency=30000 +latency_var=0 +null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +range=0:134217727:0:0:0:0 +port=system.membus.master[0] + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/simple-atomic/config.json b/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/simple-atomic/config.json new file mode 100644 index 000000000..56400a045 --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/simple-atomic/config.json @@ -0,0 +1,289 @@ +{ + "name": null, + "sim_quantum": 0, + "system": { + "kernel": "", + "mmap_using_noreserve": false, + "kernel_addr_check": true, + "membus": { + "point_of_coherency": true, + "system": "system", + "response_latency": 2, + "cxx_class": "CoherentXBar", + "forward_latency": 4, + "clk_domain": "system.clk_domain", + "width": 16, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "master": { + "peer": [ + "system.physmem.port" + ], + "role": "MASTER" + }, + "type": "CoherentXBar", + "frontend_latency": 3, + "slave": { + "peer": [ + "system.system_port", + "system.cpu.icache_port", + "system.cpu.dcache_port" + ], + "role": "SLAVE" + }, + "p_state_clk_gate_min": 1000, + "snoop_filter": { + "name": "snoop_filter", + "system": "system", + "max_capacity": 8388608, + "eventq_index": 0, + "cxx_class": "SnoopFilter", + "path": "system.membus.snoop_filter", + "type": "SnoopFilter", + "lookup_latency": 1 + }, + "power_model": null, + "path": "system.membus", + "snoop_response_latency": 4, + "name": "membus", + "p_state_clk_gate_bins": 20, + "use_default_range": false + }, + "symbolfile": "", + "readfile": "", + "thermal_model": null, + "cxx_class": "System", + "work_begin_cpu_id_exit": -1, + "load_offset": 0, + "work_begin_exit_count": 0, + "p_state_clk_gate_min": 1000, + "memories": [ + "system.physmem" + ], + "work_begin_ckpt_count": 0, + "clk_domain": { + "name": "clk_domain", + "clock": [ + 1000 + ], + "init_perf_level": 0, + "voltage_domain": "system.voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "mem_ranges": [], + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "dvfs_handler": { + "enable": false, + "name": "dvfs_handler", + "sys_clk_domain": "system.clk_domain", + "transition_latency": 100000000, + "eventq_index": 0, + "cxx_class": "DVFSHandler", + "domains": [], + "path": "system.dvfs_handler", + "type": "DVFSHandler" + }, + "work_end_exit_count": 0, + "type": "System", + "voltage_domain": { + "name": "voltage_domain", + "eventq_index": 0, + "voltage": [ + "1.0" + ], + "cxx_class": "VoltageDomain", + "path": "system.voltage_domain", + "type": "VoltageDomain" + }, + "cache_line_size": 64, + "boot_osflags": "a", + "system_port": { + "peer": "system.membus.slave[0]", + "role": "MASTER" + }, + "physmem": { + "range": "0:134217727:0:0:0:0", + "latency": 30000, + "name": "physmem", + "p_state_clk_gate_min": 1000, + "eventq_index": 0, + "p_state_clk_gate_bins": 20, + "default_p_state": "UNDEFINED", + "kvm_map": true, + "clk_domain": "system.clk_domain", + "power_model": null, + "latency_var": 0, + "bandwidth": "73.000000", + "conf_table_reported": true, + "cxx_class": "SimpleMemory", + "p_state_clk_gate_max": 1000000000000, + "path": "system.physmem", + "null": false, + "type": "SimpleMemory", + "port": { + "peer": "system.membus.master[0]", + "role": "SLAVE" + }, + "in_addr_map": true + }, + "power_model": null, + "work_cpus_ckpt_count": 0, + "thermal_components": [], + "path": "system", + "cpu_clk_domain": { + "name": "cpu_clk_domain", + "clock": [ + 500 + ], + "init_perf_level": 0, + "voltage_domain": "system.voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.cpu_clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "work_end_ckpt_count": 0, + "mem_mode": "atomic", + "name": "system", + "init_param": 0, + "p_state_clk_gate_bins": 20, + "load_addr_mask": 1099511627775, + "cpu": [ + { + "do_statistics_insts": true, + "numThreads": 1, + "itb": { + "name": "itb", + "eventq_index": 0, + "cxx_class": "RiscvISA::TLB", + "path": "system.cpu.itb", + "type": "RiscvTLB", + "size": 64 + }, + "simulate_data_stalls": false, + "function_trace": false, + "do_checkpoint_insts": true, + "cxx_class": "AtomicSimpleCPU", + "max_loads_all_threads": 0, + "system": "system", + "clk_domain": "system.cpu_clk_domain", + "function_trace_start": 0, + "cpu_id": 0, + "width": 1, + "checker": null, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "do_quiesce": true, + "type": "AtomicSimpleCPU", + "fastmem": false, + "profile": 0, + "icache_port": { + "peer": "system.membus.slave[1]", + "role": "MASTER" + }, + "p_state_clk_gate_bins": 20, + "p_state_clk_gate_min": 1000, + "interrupts": [ + { + "eventq_index": 0, + "path": "system.cpu.interrupts", + "type": "RiscvInterrupts", + "name": "interrupts", + "cxx_class": "RiscvISA::Interrupts" + } + ], + "dcache_port": { + "peer": "system.membus.slave[2]", + "role": "MASTER" + }, + "socket_id": 0, + "power_model": null, + "max_insts_all_threads": 0, + "path": "system.cpu", + "max_loads_any_thread": 0, + "switched_out": false, + "workload": [ + { + "uid": 100, + "pid": 100, + "kvmInSE": false, + "cxx_class": "LiveProcess", + "executable": "/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64m/insttest", + "drivers": [], + "system": "system", + "gid": 100, + "eventq_index": 0, + "env": [], + "input": "cin", + "ppid": 99, + "type": "LiveProcess", + "cwd": "", + "simpoint": 0, + "euid": 100, + "path": "system.cpu.workload", + "max_stack_size": 67108864, + "name": "workload", + "cmd": [ + "insttest" + ], + "errout": "cerr", + "useArchPT": false, + "egid": 100, + "output": "cout" + } + ], + "name": "cpu", + "dtb": { + "name": "dtb", + "eventq_index": 0, + "cxx_class": "RiscvISA::TLB", + "path": "system.cpu.dtb", + "type": "RiscvTLB", + "size": 64 + }, + "simpoint_start_insts": [], + "max_insts_any_thread": 0, + "simulate_inst_stalls": false, + "progress_interval": 0, + "branchPred": null, + "isa": [ + { + "eventq_index": 0, + "path": "system.cpu.isa", + "type": "RiscvISA", + "name": "isa", + "cxx_class": "RiscvISA::ISA" + } + ], + "tracer": { + "eventq_index": 0, + "path": "system.cpu.tracer", + "type": "ExeTracer", + "name": "tracer", + "cxx_class": "Trace::ExeTracer" + } + } + ], + "multi_thread": false, + "exit_on_work_items": false, + "work_item_id": -1, + "num_work_ids": 16 + }, + "time_sync_period": 100000000000, + "eventq_index": 0, + "time_sync_spin_threshold": 100000000, + "cxx_class": "Root", + "path": "root", + "time_sync_enable": false, + "type": "Root", + "full_system": false +}
\ No newline at end of file diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/simple-atomic/simerr b/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/simple-atomic/simerr new file mode 100755 index 000000000..fd133b12b --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/simple-atomic/simerr @@ -0,0 +1,3 @@ +warn: Unknown operating system; assuming Linux. +warn: Sockets disabled, not accepting gdb connections +warn: ClockedObject: More than one power state change request encountered within the same simulation tick diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/simple-atomic/simout b/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/simple-atomic/simout new file mode 100755 index 000000000..100328c9d --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/simple-atomic/simout @@ -0,0 +1,51 @@ +Redirecting stdout to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64m/simple-atomic/simout +Redirecting stderr to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64m/simple-atomic/simerr +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled Nov 30 2016 14:33:35 +gem5 started Nov 30 2016 16:18:49 +gem5 executing on zizzer, pid 34098 +command line: /z/powerjg/gem5-upstream/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64m/simple-atomic -re /z/powerjg/gem5-upstream/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64m/simple-atomic + +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. +mul: PASS +mul, overflow: PASS +mulh: PASS +mulh, negative: PASS +mulh, all bits set: PASS +mulhsu, all bits set: PASS +mulhsu: PASS +mulhu: PASS +mulhu, all bits set: PASS +div: PASS +div/0: PASS +div, overflow: PASS +divu: PASS +divu/0: PASS +divu, "overflow": PASS +rem: PASS +rem/0: PASS +rem, overflow: PASS +remu: PASS +remu/0: PASS +remu, "overflow": PASS +mulw, truncate: PASS +mulw, overflow: PASS +divw, truncate: PASS +divw/0: PASS +divw, overflow: PASS +divuw, truncate: PASS +divuw/0: PASS +divuw, "overflow": PASS +divuw, sign extend: PASS +remw, truncate: PASS +remw/0: PASS +remw, overflow: PASS +remuw, truncate: PASS +remuw/0: PASS +remuw, "overflow": PASS +remuw, sign extend: PASS +Exiting @ tick 56668000 because target called exit() diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/simple-atomic/stats.txt b/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/simple-atomic/stats.txt new file mode 100644 index 000000000..729707f96 --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/simple-atomic/stats.txt @@ -0,0 +1,153 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.000057 # Number of seconds simulated +sim_ticks 56668000 # Number of ticks simulated +final_tick 56668000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 42634 # Simulator instruction rate (inst/s) +host_op_rate 42633 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 21324951 # Simulator tick rate (ticks/s) +host_mem_usage 233724 # Number of bytes of host memory used +host_seconds 2.66 # Real time elapsed on the host +sim_insts 113291 # Number of instructions simulated +sim_ops 113291 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 56668000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 453348 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 156046 # Number of bytes read from this memory +system.physmem.bytes_read::total 609394 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 453348 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 453348 # Number of instructions bytes read from this memory +system.physmem.bytes_written::cpu.data 110317 # Number of bytes written to this memory +system.physmem.bytes_written::total 110317 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 113337 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 23780 # Number of read requests responded to by this memory +system.physmem.num_reads::total 137117 # Number of read requests responded to by this memory +system.physmem.num_writes::cpu.data 19712 # Number of write requests responded to by this memory +system.physmem.num_writes::total 19712 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 8000070587 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2753688149 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 10753758735 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 8000070587 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 8000070587 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1946724783 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1946724783 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 8000070587 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4700412931 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 12700483518 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 56668000 # Cumulative time (in ticks) in various power states +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 45 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 56668000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 113337 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 113291 # Number of instructions committed +system.cpu.committedOps 113291 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 113292 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses +system.cpu.num_func_calls 8529 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 17391 # number of instructions that are conditional controls +system.cpu.num_int_insts 113292 # number of integer instructions +system.cpu.num_fp_insts 0 # number of float instructions +system.cpu.num_int_register_reads 151096 # number of times the integer registers were read +system.cpu.num_int_register_writes 76188 # number of times the integer registers were written +system.cpu.num_fp_register_reads 0 # number of times the floating registers were read +system.cpu.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu.num_mem_refs 43493 # number of memory refs +system.cpu.num_load_insts 23780 # Number of load instructions +system.cpu.num_store_insts 19713 # Number of store instructions +system.cpu.num_idle_cycles 0 # Number of idle cycles +system.cpu.num_busy_cycles 113337 # Number of busy cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.Branches 25920 # Number of branches fetched +system.cpu.op_class::No_OpClass 45 0.04% 0.04% # Class of executed instruction +system.cpu.op_class::IntAlu 69651 61.45% 61.49% # Class of executed instruction +system.cpu.op_class::IntMult 122 0.11% 61.60% # Class of executed instruction +system.cpu.op_class::IntDiv 26 0.02% 61.63% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 61.63% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 61.63% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 61.63% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 61.63% # Class of executed instruction +system.cpu.op_class::FloatMultAcc 0 0.00% 61.63% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 61.63% # Class of executed instruction +system.cpu.op_class::FloatMisc 0 0.00% 61.63% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 61.63% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 61.63% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 61.63% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 61.63% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 61.63% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 61.63% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 61.63% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 61.63% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 61.63% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 61.63% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 61.63% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 61.63% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 61.63% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 61.63% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 61.63% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 61.63% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 61.63% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 61.63% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 61.63% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 61.63% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 61.63% # Class of executed instruction +system.cpu.op_class::MemRead 23780 20.98% 82.61% # Class of executed instruction +system.cpu.op_class::MemWrite 19713 17.39% 100.00% # Class of executed instruction +system.cpu.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 113337 # Class of executed instruction +system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 56668000 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadReq 137117 # Transaction distribution +system.membus.trans_dist::ReadResp 137117 # Transaction distribution +system.membus.trans_dist::WriteReq 19712 # Transaction distribution +system.membus.trans_dist::WriteResp 19712 # Transaction distribution +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 226674 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 86984 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 313658 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 453348 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 266363 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 719711 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoopTraffic 0 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 156829 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 156829 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 156829 # Request fanout histogram + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/simple-timing-ruby/config.ini b/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/simple-timing-ruby/config.ini new file mode 100644 index 000000000..2d0e2ebad --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/simple-timing-ruby/config.ini @@ -0,0 +1,1265 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000 +time_sync_spin_threshold=100000 + +[system] +type=System +children=clk_domain cpu dvfs_handler mem_ctrls ruby sys_port_proxy voltage_domain +boot_osflags=a +cache_line_size=64 +clk_domain=system.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +exit_on_work_items=false +init_param=0 +kernel= +kernel_addr_check=true +load_addr_mask=1099511627775 +load_offset=0 +mem_mode=timing +mem_ranges=0:268435455:0:0:0:0 +memories=system.mem_ctrls +mmap_using_noreserve=false +multi_thread=false +num_work_ids=16 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null +readfile= +symbolfile= +thermal_components= +thermal_model=Null +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.sys_port_proxy.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=TimingSimpleCPU +children=clk_domain dtb interrupts isa itb tracer workload +branchPred=Null +checker=Null +clk_domain=system.cpu.clk_domain +cpu_id=0 +default_p_state=UNDEFINED +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +eventq_index=0 +function_trace=false +function_trace_start=0 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null +profile=0 +progress_interval=0 +simpoint_start_insts= +socket_id=0 +switched_out=false +system=system +tracer=system.cpu.tracer +workload=system.cpu.workload +dcache_port=system.ruby.l1_cntrl0.sequencer.slave[1] +icache_port=system.ruby.l1_cntrl0.sequencer.slave[0] + +[system.cpu.clk_domain] +type=SrcClockDomain +clock=1 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu.dtb] +type=RiscvTLB +eventq_index=0 +size=64 + +[system.cpu.interrupts] +type=RiscvInterrupts +eventq_index=0 + +[system.cpu.isa] +type=RiscvISA +eventq_index=0 + +[system.cpu.itb] +type=RiscvTLB +eventq_index=0 +size=64 + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=LiveProcess +cmd=insttest +cwd= +drivers= +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable=/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64m/insttest +gid=100 +input=cin +kvmInSE=false +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=0 +system=system +uid=100 +useArchPT=false + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000 + +[system.mem_ctrls] +type=DRAMCtrl +IDD0=0.055000 +IDD02=0.000000 +IDD2N=0.032000 +IDD2N2=0.000000 +IDD2P0=0.000000 +IDD2P02=0.000000 +IDD2P1=0.032000 +IDD2P12=0.000000 +IDD3N=0.038000 +IDD3N2=0.000000 +IDD3P0=0.000000 +IDD3P02=0.000000 +IDD3P1=0.038000 +IDD3P12=0.000000 +IDD4R=0.157000 +IDD4R2=0.000000 +IDD4W=0.125000 +IDD4W2=0.000000 +IDD5=0.235000 +IDD52=0.000000 +IDD6=0.020000 +IDD62=0.000000 +VDD=1.500000 +VDD2=0.000000 +activation_limit=4 +addr_mapping=RoRaBaCoCh +bank_groups_per_rank=0 +banks_per_rank=8 +burst_length=8 +channels=1 +clk_domain=system.clk_domain +conf_table_reported=true +default_p_state=UNDEFINED +device_bus_width=8 +device_rowbuffer_size=1024 +device_size=536870912 +devices_per_rank=8 +dll=true +eventq_index=0 +in_addr_map=true +kvm_map=true +max_accesses_per_row=16 +mem_sched_policy=frfcfs +min_writes_per_switch=16 +null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +page_policy=open_adaptive +power_model=Null +range=0:268435455:5:19:0:0 +ranks_per_channel=2 +read_buffer_size=32 +static_backend_latency=10 +static_frontend_latency=10 +tBURST=5 +tCCD_L=0 +tCK=1 +tCL=14 +tCS=3 +tRAS=35 +tRCD=14 +tREFI=7800 +tRFC=260 +tRP=14 +tRRD=6 +tRRD_L=0 +tRTP=8 +tRTW=3 +tWR=15 +tWTR=8 +tXAW=30 +tXP=6 +tXPDLL=0 +tXS=270 +tXSDLL=0 +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 +port=system.ruby.dir_cntrl0.memory + +[system.ruby] +type=RubySystem +children=clk_domain dir_cntrl0 l1_cntrl0 memctrl_clk_domain network +access_backing_store=false +all_instructions=false +block_size_bytes=64 +clk_domain=system.ruby.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +hot_lines=false +memory_size_bits=48 +num_of_sequencers=1 +number_of_virtual_networks=5 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +phys_mem=Null +power_model=Null +randomization=false + +[system.ruby.clk_domain] +type=SrcClockDomain +clock=1 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.ruby.dir_cntrl0] +type=Directory_Controller +children=directory dmaRequestToDir dmaResponseFromDir forwardFromDir requestToDir responseFromDir responseFromMemory +buffer_size=0 +clk_domain=system.ruby.clk_domain +cluster_id=0 +default_p_state=UNDEFINED +directory=system.ruby.dir_cntrl0.directory +directory_latency=12 +dmaRequestToDir=system.ruby.dir_cntrl0.dmaRequestToDir +dmaResponseFromDir=system.ruby.dir_cntrl0.dmaResponseFromDir +eventq_index=0 +forwardFromDir=system.ruby.dir_cntrl0.forwardFromDir +number_of_TBEs=256 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null +recycle_latency=10 +requestToDir=system.ruby.dir_cntrl0.requestToDir +responseFromDir=system.ruby.dir_cntrl0.responseFromDir +responseFromMemory=system.ruby.dir_cntrl0.responseFromMemory +ruby_system=system.ruby +system=system +to_memory_controller_latency=1 +transitions_per_cycle=4 +version=0 +memory=system.mem_ctrls.port + +[system.ruby.dir_cntrl0.directory] +type=RubyDirectoryMemory +eventq_index=0 +numa_high_bit=5 +size=268435456 +version=0 + +[system.ruby.dir_cntrl0.dmaRequestToDir] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +slave=system.ruby.network.master[3] + +[system.ruby.dir_cntrl0.dmaResponseFromDir] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +master=system.ruby.network.slave[3] + +[system.ruby.dir_cntrl0.forwardFromDir] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=false +randomization=false +master=system.ruby.network.slave[4] + +[system.ruby.dir_cntrl0.requestToDir] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +slave=system.ruby.network.master[2] + +[system.ruby.dir_cntrl0.responseFromDir] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=false +randomization=false +master=system.ruby.network.slave[2] + +[system.ruby.dir_cntrl0.responseFromMemory] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=false +randomization=false + +[system.ruby.l1_cntrl0] +type=L1Cache_Controller +children=cacheMemory forwardToCache mandatoryQueue requestFromCache responseFromCache responseToCache sequencer +buffer_size=0 +cacheMemory=system.ruby.l1_cntrl0.cacheMemory +cache_response_latency=12 +clk_domain=system.cpu.clk_domain +cluster_id=0 +default_p_state=UNDEFINED +eventq_index=0 +forwardToCache=system.ruby.l1_cntrl0.forwardToCache +issue_latency=2 +mandatoryQueue=system.ruby.l1_cntrl0.mandatoryQueue +number_of_TBEs=256 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null +recycle_latency=10 +requestFromCache=system.ruby.l1_cntrl0.requestFromCache +responseFromCache=system.ruby.l1_cntrl0.responseFromCache +responseToCache=system.ruby.l1_cntrl0.responseToCache +ruby_system=system.ruby +send_evictions=false +sequencer=system.ruby.l1_cntrl0.sequencer +system=system +transitions_per_cycle=4 +version=0 + +[system.ruby.l1_cntrl0.cacheMemory] +type=RubyCache +children=replacement_policy +assoc=2 +block_size=0 +dataAccessLatency=1 +dataArrayBanks=1 +eventq_index=0 +is_icache=false +replacement_policy=system.ruby.l1_cntrl0.cacheMemory.replacement_policy +resourceStalls=false +ruby_system=system.ruby +size=256 +start_index_bit=6 +tagAccessLatency=1 +tagArrayBanks=1 + +[system.ruby.l1_cntrl0.cacheMemory.replacement_policy] +type=PseudoLRUReplacementPolicy +assoc=2 +block_size=64 +eventq_index=0 +size=256 + +[system.ruby.l1_cntrl0.forwardToCache] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +slave=system.ruby.network.master[0] + +[system.ruby.l1_cntrl0.mandatoryQueue] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=false +randomization=false + +[system.ruby.l1_cntrl0.requestFromCache] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +master=system.ruby.network.slave[0] + +[system.ruby.l1_cntrl0.responseFromCache] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +master=system.ruby.network.slave[1] + +[system.ruby.l1_cntrl0.responseToCache] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +slave=system.ruby.network.master[1] + +[system.ruby.l1_cntrl0.sequencer] +type=RubySequencer +clk_domain=system.cpu.clk_domain +coreid=99 +dcache=system.ruby.l1_cntrl0.cacheMemory +dcache_hit_latency=1 +deadlock_threshold=500000 +default_p_state=UNDEFINED +eventq_index=0 +garnet_standalone=false +icache=system.ruby.l1_cntrl0.cacheMemory +icache_hit_latency=1 +is_cpu_sequencer=true +max_outstanding_requests=16 +no_retry_on_stall=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null +ruby_system=system.ruby +support_data_reqs=true +support_inst_reqs=true +system=system +using_ruby_tester=false +version=0 +slave=system.cpu.icache_port system.cpu.dcache_port + +[system.ruby.memctrl_clk_domain] +type=DerivedClockDomain +clk_divider=3 +clk_domain=system.ruby.clk_domain +eventq_index=0 + +[system.ruby.network] +type=SimpleNetwork +children=ext_links0 ext_links1 int_link_buffers00 int_link_buffers01 int_link_buffers02 int_link_buffers03 int_link_buffers04 int_link_buffers05 int_link_buffers06 int_link_buffers07 int_link_buffers08 int_link_buffers09 int_link_buffers10 int_link_buffers11 int_link_buffers12 int_link_buffers13 int_link_buffers14 int_link_buffers15 int_link_buffers16 int_link_buffers17 int_link_buffers18 int_link_buffers19 int_link_buffers20 int_link_buffers21 int_link_buffers22 int_link_buffers23 int_link_buffers24 int_link_buffers25 int_link_buffers26 int_link_buffers27 int_link_buffers28 int_link_buffers29 int_link_buffers30 int_link_buffers31 int_link_buffers32 int_link_buffers33 int_link_buffers34 int_link_buffers35 int_link_buffers36 int_link_buffers37 int_link_buffers38 int_link_buffers39 int_links0 int_links1 int_links2 int_links3 routers0 routers1 routers2 +adaptive_routing=false +buffer_size=0 +clk_domain=system.ruby.clk_domain +control_msg_size=8 +default_p_state=UNDEFINED +endpoint_bandwidth=1000 +eventq_index=0 +ext_links=system.ruby.network.ext_links0 system.ruby.network.ext_links1 +int_link_buffers=system.ruby.network.int_link_buffers00 system.ruby.network.int_link_buffers01 system.ruby.network.int_link_buffers02 system.ruby.network.int_link_buffers03 system.ruby.network.int_link_buffers04 system.ruby.network.int_link_buffers05 system.ruby.network.int_link_buffers06 system.ruby.network.int_link_buffers07 system.ruby.network.int_link_buffers08 system.ruby.network.int_link_buffers09 system.ruby.network.int_link_buffers10 system.ruby.network.int_link_buffers11 system.ruby.network.int_link_buffers12 system.ruby.network.int_link_buffers13 system.ruby.network.int_link_buffers14 system.ruby.network.int_link_buffers15 system.ruby.network.int_link_buffers16 system.ruby.network.int_link_buffers17 system.ruby.network.int_link_buffers18 system.ruby.network.int_link_buffers19 system.ruby.network.int_link_buffers20 system.ruby.network.int_link_buffers21 system.ruby.network.int_link_buffers22 system.ruby.network.int_link_buffers23 system.ruby.network.int_link_buffers24 system.ruby.network.int_link_buffers25 system.ruby.network.int_link_buffers26 system.ruby.network.int_link_buffers27 system.ruby.network.int_link_buffers28 system.ruby.network.int_link_buffers29 system.ruby.network.int_link_buffers30 system.ruby.network.int_link_buffers31 system.ruby.network.int_link_buffers32 system.ruby.network.int_link_buffers33 system.ruby.network.int_link_buffers34 system.ruby.network.int_link_buffers35 system.ruby.network.int_link_buffers36 system.ruby.network.int_link_buffers37 system.ruby.network.int_link_buffers38 system.ruby.network.int_link_buffers39 +int_links=system.ruby.network.int_links0 system.ruby.network.int_links1 system.ruby.network.int_links2 system.ruby.network.int_links3 +netifs= +number_of_virtual_networks=5 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null +routers=system.ruby.network.routers0 system.ruby.network.routers1 system.ruby.network.routers2 +ruby_system=system.ruby +topology=Crossbar +master=system.ruby.l1_cntrl0.forwardToCache.slave system.ruby.l1_cntrl0.responseToCache.slave system.ruby.dir_cntrl0.requestToDir.slave system.ruby.dir_cntrl0.dmaRequestToDir.slave +slave=system.ruby.l1_cntrl0.requestFromCache.master system.ruby.l1_cntrl0.responseFromCache.master system.ruby.dir_cntrl0.responseFromDir.master system.ruby.dir_cntrl0.dmaResponseFromDir.master system.ruby.dir_cntrl0.forwardFromDir.master + +[system.ruby.network.ext_links0] +type=SimpleExtLink +bandwidth_factor=16 +eventq_index=0 +ext_node=system.ruby.l1_cntrl0 +int_node=system.ruby.network.routers0 +latency=1 +link_id=0 +weight=1 + +[system.ruby.network.ext_links1] +type=SimpleExtLink +bandwidth_factor=16 +eventq_index=0 +ext_node=system.ruby.dir_cntrl0 +int_node=system.ruby.network.routers1 +latency=1 +link_id=1 +weight=1 + +[system.ruby.network.int_link_buffers00] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers01] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers02] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers03] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers04] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers05] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers06] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers07] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers08] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers09] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers10] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers11] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers12] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers13] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers14] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers15] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers16] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers17] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers18] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers19] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers20] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers21] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers22] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers23] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers24] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers25] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers26] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers27] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers28] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers29] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers30] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers31] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers32] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers33] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers34] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers35] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers36] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers37] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers38] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers39] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_links0] +type=SimpleIntLink +bandwidth_factor=16 +dst_inport= +dst_node=system.ruby.network.routers2 +eventq_index=0 +latency=1 +link_id=2 +src_node=system.ruby.network.routers0 +src_outport= +weight=1 + +[system.ruby.network.int_links1] +type=SimpleIntLink +bandwidth_factor=16 +dst_inport= +dst_node=system.ruby.network.routers2 +eventq_index=0 +latency=1 +link_id=3 +src_node=system.ruby.network.routers1 +src_outport= +weight=1 + +[system.ruby.network.int_links2] +type=SimpleIntLink +bandwidth_factor=16 +dst_inport= +dst_node=system.ruby.network.routers0 +eventq_index=0 +latency=1 +link_id=4 +src_node=system.ruby.network.routers2 +src_outport= +weight=1 + +[system.ruby.network.int_links3] +type=SimpleIntLink +bandwidth_factor=16 +dst_inport= +dst_node=system.ruby.network.routers1 +eventq_index=0 +latency=1 +link_id=5 +src_node=system.ruby.network.routers2 +src_outport= +weight=1 + +[system.ruby.network.routers0] +type=Switch +children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14 +clk_domain=system.ruby.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +port_buffers=system.ruby.network.routers0.port_buffers00 system.ruby.network.routers0.port_buffers01 system.ruby.network.routers0.port_buffers02 system.ruby.network.routers0.port_buffers03 system.ruby.network.routers0.port_buffers04 system.ruby.network.routers0.port_buffers05 system.ruby.network.routers0.port_buffers06 system.ruby.network.routers0.port_buffers07 system.ruby.network.routers0.port_buffers08 system.ruby.network.routers0.port_buffers09 system.ruby.network.routers0.port_buffers10 system.ruby.network.routers0.port_buffers11 system.ruby.network.routers0.port_buffers12 system.ruby.network.routers0.port_buffers13 system.ruby.network.routers0.port_buffers14 +power_model=Null +router_id=0 +virt_nets=5 + +[system.ruby.network.routers0.port_buffers00] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers0.port_buffers01] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers0.port_buffers02] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers0.port_buffers03] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers0.port_buffers04] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers0.port_buffers05] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers0.port_buffers06] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers0.port_buffers07] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers0.port_buffers08] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers0.port_buffers09] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers0.port_buffers10] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers0.port_buffers11] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers0.port_buffers12] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers0.port_buffers13] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers0.port_buffers14] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers1] +type=Switch +children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14 +clk_domain=system.ruby.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +port_buffers=system.ruby.network.routers1.port_buffers00 system.ruby.network.routers1.port_buffers01 system.ruby.network.routers1.port_buffers02 system.ruby.network.routers1.port_buffers03 system.ruby.network.routers1.port_buffers04 system.ruby.network.routers1.port_buffers05 system.ruby.network.routers1.port_buffers06 system.ruby.network.routers1.port_buffers07 system.ruby.network.routers1.port_buffers08 system.ruby.network.routers1.port_buffers09 system.ruby.network.routers1.port_buffers10 system.ruby.network.routers1.port_buffers11 system.ruby.network.routers1.port_buffers12 system.ruby.network.routers1.port_buffers13 system.ruby.network.routers1.port_buffers14 +power_model=Null +router_id=1 +virt_nets=5 + +[system.ruby.network.routers1.port_buffers00] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers1.port_buffers01] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers1.port_buffers02] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers1.port_buffers03] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers1.port_buffers04] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers1.port_buffers05] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers1.port_buffers06] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers1.port_buffers07] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers1.port_buffers08] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers1.port_buffers09] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers1.port_buffers10] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers1.port_buffers11] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers1.port_buffers12] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers1.port_buffers13] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers1.port_buffers14] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2] +type=Switch +children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14 port_buffers15 port_buffers16 port_buffers17 port_buffers18 port_buffers19 +clk_domain=system.ruby.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +port_buffers=system.ruby.network.routers2.port_buffers00 system.ruby.network.routers2.port_buffers01 system.ruby.network.routers2.port_buffers02 system.ruby.network.routers2.port_buffers03 system.ruby.network.routers2.port_buffers04 system.ruby.network.routers2.port_buffers05 system.ruby.network.routers2.port_buffers06 system.ruby.network.routers2.port_buffers07 system.ruby.network.routers2.port_buffers08 system.ruby.network.routers2.port_buffers09 system.ruby.network.routers2.port_buffers10 system.ruby.network.routers2.port_buffers11 system.ruby.network.routers2.port_buffers12 system.ruby.network.routers2.port_buffers13 system.ruby.network.routers2.port_buffers14 system.ruby.network.routers2.port_buffers15 system.ruby.network.routers2.port_buffers16 system.ruby.network.routers2.port_buffers17 system.ruby.network.routers2.port_buffers18 system.ruby.network.routers2.port_buffers19 +power_model=Null +router_id=2 +virt_nets=5 + +[system.ruby.network.routers2.port_buffers00] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers01] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers02] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers03] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers04] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers05] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers06] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers07] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers08] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers09] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers10] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers11] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers12] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers13] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers14] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers15] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers16] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers17] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers18] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers19] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.sys_port_proxy] +type=RubyPortProxy +clk_domain=system.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +is_cpu_sequencer=true +no_retry_on_stall=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null +ruby_system=system.ruby +support_data_reqs=true +support_inst_reqs=true +system=system +using_ruby_tester=false +version=0 +slave=system.system_port + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/simple-timing-ruby/config.json b/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/simple-timing-ruby/config.json new file mode 100644 index 000000000..491401e32 --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/simple-timing-ruby/config.json @@ -0,0 +1,1734 @@ +{ + "name": null, + "sim_quantum": 0, + "system": { + "kernel": "", + "mmap_using_noreserve": false, + "kernel_addr_check": true, + "symbolfile": "", + "readfile": "", + "thermal_model": null, + "cxx_class": "System", + "work_begin_cpu_id_exit": -1, + "load_offset": 0, + "work_begin_exit_count": 0, + "p_state_clk_gate_min": 1, + "memories": [ + "system.mem_ctrls" + ], + "work_begin_ckpt_count": 0, + "clk_domain": { + "name": "clk_domain", + "clock": [ + 1 + ], + "init_perf_level": 0, + "voltage_domain": "system.voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "mem_ranges": [ + "0:268435455:0:0:0:0" + ], + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000, + "dvfs_handler": { + "enable": false, + "name": "dvfs_handler", + "sys_clk_domain": "system.clk_domain", + "transition_latency": 100000, + "eventq_index": 0, + "cxx_class": "DVFSHandler", + "domains": [], + "path": "system.dvfs_handler", + "type": "DVFSHandler" + }, + "work_end_exit_count": 0, + "type": "System", + "voltage_domain": { + "name": "voltage_domain", + "eventq_index": 0, + "voltage": [ + "1.0" + ], + "cxx_class": "VoltageDomain", + "path": "system.voltage_domain", + "type": "VoltageDomain" + }, + "cache_line_size": 64, + "boot_osflags": "a", + "system_port": { + "peer": "system.sys_port_proxy.slave[0]", + "role": "MASTER" + }, + "sys_port_proxy": { + "system": "system", + "support_inst_reqs": true, + "slave": { + "peer": [ + "system.system_port" + ], + "role": "SLAVE" + }, + "name": "sys_port_proxy", + "p_state_clk_gate_min": 1, + "no_retry_on_stall": false, + "p_state_clk_gate_bins": 20, + "support_data_reqs": true, + "cxx_class": "RubyPortProxy", + "clk_domain": "system.clk_domain", + "power_model": null, + "is_cpu_sequencer": true, + "version": 0, + "eventq_index": 0, + "using_ruby_tester": false, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000, + "path": "system.sys_port_proxy", + "type": "RubyPortProxy", + "ruby_system": "system.ruby" + }, + "power_model": null, + "work_cpus_ckpt_count": 0, + "thermal_components": [], + "path": "system", + "ruby": { + "all_instructions": false, + "memory_size_bits": 48, + "cxx_class": "RubySystem", + "l1_cntrl0": { + "requestFromCache": { + "ordered": true, + "name": "requestFromCache", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "master": { + "peer": "system.ruby.network.slave[0]", + "role": "MASTER" + }, + "buffer_size": 0, + "path": "system.ruby.l1_cntrl0.requestFromCache", + "type": "MessageBuffer" + }, + "cxx_class": "L1Cache_Controller", + "forwardToCache": { + "ordered": true, + "name": "forwardToCache", + "cxx_class": "MessageBuffer", + "slave": { + "peer": "system.ruby.network.master[0]", + "role": "SLAVE" + }, + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.l1_cntrl0.forwardToCache", + "type": "MessageBuffer" + }, + "system": "system", + "cluster_id": 0, + "sequencer": { + "no_retry_on_stall": false, + "deadlock_threshold": 500000, + "using_ruby_tester": false, + "system": "system", + "dcache": "system.ruby.l1_cntrl0.cacheMemory", + "cxx_class": "Sequencer", + "garnet_standalone": false, + "clk_domain": "system.cpu.clk_domain", + "icache_hit_latency": 1, + "version": 0, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000, + "type": "RubySequencer", + "icache": "system.ruby.l1_cntrl0.cacheMemory", + "slave": { + "peer": [ + "system.cpu.icache_port", + "system.cpu.dcache_port" + ], + "role": "SLAVE" + }, + "p_state_clk_gate_min": 1, + "power_model": null, + "coreid": 99, + "path": "system.ruby.l1_cntrl0.sequencer", + "ruby_system": "system.ruby", + "support_inst_reqs": true, + "name": "sequencer", + "max_outstanding_requests": 16, + "p_state_clk_gate_bins": 20, + "dcache_hit_latency": 1, + "support_data_reqs": true, + "is_cpu_sequencer": true + }, + "type": "L1Cache_Controller", + "issue_latency": 2, + "recycle_latency": 10, + "clk_domain": "system.cpu.clk_domain", + "version": 0, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000, + "number_of_TBEs": 256, + "p_state_clk_gate_min": 1, + "responseToCache": { + "ordered": true, + "name": "responseToCache", + "cxx_class": "MessageBuffer", + "slave": { + "peer": "system.ruby.network.master[1]", + "role": "SLAVE" + }, + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.l1_cntrl0.responseToCache", + "type": "MessageBuffer" + }, + "transitions_per_cycle": 4, + "responseFromCache": { + "ordered": true, + "name": "responseFromCache", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "master": { + "peer": "system.ruby.network.slave[1]", + "role": "MASTER" + }, + "buffer_size": 0, + "path": "system.ruby.l1_cntrl0.responseFromCache", + "type": "MessageBuffer" + }, + "power_model": null, + "cache_response_latency": 12, + "buffer_size": 0, + "send_evictions": false, + "cacheMemory": { + "size": 256, + "resourceStalls": false, + "is_icache": false, + "name": "cacheMemory", + "eventq_index": 0, + "dataAccessLatency": 1, + "tagArrayBanks": 1, + "tagAccessLatency": 1, + "replacement_policy": { + "name": "replacement_policy", + "eventq_index": 0, + "assoc": 2, + "cxx_class": "PseudoLRUPolicy", + "path": "system.ruby.l1_cntrl0.cacheMemory.replacement_policy", + "block_size": 64, + "type": "PseudoLRUReplacementPolicy", + "size": 256 + }, + "assoc": 2, + "start_index_bit": 6, + "cxx_class": "CacheMemory", + "path": "system.ruby.l1_cntrl0.cacheMemory", + "block_size": 0, + "type": "RubyCache", + "dataArrayBanks": 1, + "ruby_system": "system.ruby" + }, + "ruby_system": "system.ruby", + "name": "l1_cntrl0", + "p_state_clk_gate_bins": 20, + "mandatoryQueue": { + "ordered": false, + "name": "mandatoryQueue", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.l1_cntrl0.mandatoryQueue", + "type": "MessageBuffer" + }, + "path": "system.ruby.l1_cntrl0" + }, + "network": { + "int_link_buffers": [ + { + "ordered": true, + "name": "int_link_buffers00", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers00", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers01", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers01", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers02", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers02", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers03", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers03", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers04", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers04", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers05", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers05", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers06", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers06", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers07", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers07", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers08", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers08", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers09", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers09", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers10", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers10", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers11", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers11", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers12", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers12", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers13", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers13", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers14", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers14", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers15", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers15", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers16", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers16", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers17", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers17", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers18", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers18", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers19", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers19", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers20", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers20", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers21", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers21", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers22", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers22", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers23", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers23", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers24", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers24", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers25", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers25", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers26", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers26", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers27", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers27", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers28", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers28", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers29", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers29", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers30", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers30", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers31", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers31", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers32", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers32", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers33", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers33", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers34", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers34", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers35", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers35", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers36", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers36", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers37", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers37", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers38", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers38", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "int_link_buffers39", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.int_link_buffers39", + "type": "MessageBuffer" + } + ], + "cxx_class": "SimpleNetwork", + "clk_domain": "system.ruby.clk_domain", + "adaptive_routing": false, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000, + "master": { + "peer": [ + "system.ruby.l1_cntrl0.forwardToCache.slave", + "system.ruby.l1_cntrl0.responseToCache.slave", + "system.ruby.dir_cntrl0.requestToDir.slave", + "system.ruby.dir_cntrl0.dmaRequestToDir.slave" + ], + "role": "MASTER" + }, + "topology": "Crossbar", + "type": "SimpleNetwork", + "slave": { + "peer": [ + "system.ruby.l1_cntrl0.requestFromCache.master", + "system.ruby.l1_cntrl0.responseFromCache.master", + "system.ruby.dir_cntrl0.responseFromDir.master", + "system.ruby.dir_cntrl0.dmaResponseFromDir.master", + "system.ruby.dir_cntrl0.forwardFromDir.master" + ], + "role": "SLAVE" + }, + "p_state_clk_gate_min": 1, + "int_links": [ + { + "latency": 1, + "name": "int_links0", + "weight": 1, + "src_node": "system.ruby.network.routers0", + "dst_inport": "", + "link_id": 2, + "dst_node": "system.ruby.network.routers2", + "eventq_index": 0, + "src_outport": "", + "cxx_class": "SimpleIntLink", + "path": "system.ruby.network.int_links0", + "type": "SimpleIntLink", + "bandwidth_factor": 16 + }, + { + "latency": 1, + "name": "int_links1", + "weight": 1, + "src_node": "system.ruby.network.routers1", + "dst_inport": "", + "link_id": 3, + "dst_node": "system.ruby.network.routers2", + "eventq_index": 0, + "src_outport": "", + "cxx_class": "SimpleIntLink", + "path": "system.ruby.network.int_links1", + "type": "SimpleIntLink", + "bandwidth_factor": 16 + }, + { + "latency": 1, + "name": "int_links2", + "weight": 1, + "src_node": "system.ruby.network.routers2", + "dst_inport": "", + "link_id": 4, + "dst_node": "system.ruby.network.routers0", + "eventq_index": 0, + "src_outport": "", + "cxx_class": "SimpleIntLink", + "path": "system.ruby.network.int_links2", + "type": "SimpleIntLink", + "bandwidth_factor": 16 + }, + { + "latency": 1, + "name": "int_links3", + "weight": 1, + "src_node": "system.ruby.network.routers2", + "dst_inport": "", + "link_id": 5, + "dst_node": "system.ruby.network.routers1", + "eventq_index": 0, + "src_outport": "", + "cxx_class": "SimpleIntLink", + "path": "system.ruby.network.int_links3", + "type": "SimpleIntLink", + "bandwidth_factor": 16 + } + ], + "routers": [ + { + "router_id": 0, + "latency": 1, + "name": "routers0", + "p_state_clk_gate_min": 1, + "virt_nets": 5, + "p_state_clk_gate_bins": 20, + "cxx_class": "Switch", + "clk_domain": "system.ruby.clk_domain", + "power_model": null, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000, + "path": "system.ruby.network.routers0", + "type": "Switch", + "port_buffers": [ + { + "ordered": true, + "name": "port_buffers00", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers0.port_buffers00", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers01", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers0.port_buffers01", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers02", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers0.port_buffers02", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers03", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers0.port_buffers03", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers04", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers0.port_buffers04", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers05", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers0.port_buffers05", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers06", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers0.port_buffers06", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers07", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers0.port_buffers07", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers08", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers0.port_buffers08", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers09", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers0.port_buffers09", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers10", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers0.port_buffers10", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers11", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers0.port_buffers11", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers12", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers0.port_buffers12", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers13", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers0.port_buffers13", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers14", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers0.port_buffers14", + "type": "MessageBuffer" + } + ] + }, + { + "router_id": 1, + "latency": 1, + "name": "routers1", + "p_state_clk_gate_min": 1, + "virt_nets": 5, + "p_state_clk_gate_bins": 20, + "cxx_class": "Switch", + "clk_domain": "system.ruby.clk_domain", + "power_model": null, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000, + "path": "system.ruby.network.routers1", + "type": "Switch", + "port_buffers": [ + { + "ordered": true, + "name": "port_buffers00", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers1.port_buffers00", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers01", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers1.port_buffers01", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers02", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers1.port_buffers02", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers03", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers1.port_buffers03", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers04", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers1.port_buffers04", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers05", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers1.port_buffers05", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers06", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers1.port_buffers06", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers07", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers1.port_buffers07", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers08", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers1.port_buffers08", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers09", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers1.port_buffers09", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers10", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers1.port_buffers10", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers11", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers1.port_buffers11", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers12", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers1.port_buffers12", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers13", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers1.port_buffers13", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers14", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers1.port_buffers14", + "type": "MessageBuffer" + } + ] + }, + { + "router_id": 2, + "latency": 1, + "name": "routers2", + "p_state_clk_gate_min": 1, + "virt_nets": 5, + "p_state_clk_gate_bins": 20, + "cxx_class": "Switch", + "clk_domain": "system.ruby.clk_domain", + "power_model": null, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000, + "path": "system.ruby.network.routers2", + "type": "Switch", + "port_buffers": [ + { + "ordered": true, + "name": "port_buffers00", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers2.port_buffers00", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers01", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers2.port_buffers01", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers02", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers2.port_buffers02", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers03", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers2.port_buffers03", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers04", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers2.port_buffers04", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers05", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers2.port_buffers05", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers06", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers2.port_buffers06", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers07", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers2.port_buffers07", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers08", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers2.port_buffers08", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers09", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers2.port_buffers09", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers10", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers2.port_buffers10", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers11", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers2.port_buffers11", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers12", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers2.port_buffers12", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers13", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers2.port_buffers13", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers14", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers2.port_buffers14", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers15", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers2.port_buffers15", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers16", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers2.port_buffers16", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers17", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers2.port_buffers17", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers18", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers2.port_buffers18", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers19", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers2.port_buffers19", + "type": "MessageBuffer" + } + ] + } + ], + "power_model": null, + "netifs": [], + "control_msg_size": 8, + "buffer_size": 0, + "endpoint_bandwidth": 1000, + "ruby_system": "system.ruby", + "name": "network", + "p_state_clk_gate_bins": 20, + "ext_links": [ + { + "latency": 1, + "name": "ext_links0", + "weight": 1, + "ext_node": "system.ruby.l1_cntrl0", + "link_id": 0, + "eventq_index": 0, + "cxx_class": "SimpleExtLink", + "path": "system.ruby.network.ext_links0", + "int_node": "system.ruby.network.routers0", + "type": "SimpleExtLink", + "bandwidth_factor": 16 + }, + { + "latency": 1, + "name": "ext_links1", + "weight": 1, + "ext_node": "system.ruby.dir_cntrl0", + "link_id": 1, + "eventq_index": 0, + "cxx_class": "SimpleExtLink", + "path": "system.ruby.network.ext_links1", + "int_node": "system.ruby.network.routers1", + "type": "SimpleExtLink", + "bandwidth_factor": 16 + } + ], + "number_of_virtual_networks": 5, + "path": "system.ruby.network" + }, + "clk_domain": { + "name": "clk_domain", + "clock": [ + 1 + ], + "init_perf_level": 0, + "voltage_domain": "system.voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.ruby.clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "randomization": false, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000, + "phys_mem": null, + "type": "RubySystem", + "p_state_clk_gate_min": 1, + "hot_lines": false, + "power_model": null, + "path": "system.ruby", + "memctrl_clk_domain": { + "name": "memctrl_clk_domain", + "clk_domain": "system.ruby.clk_domain", + "eventq_index": 0, + "cxx_class": "DerivedClockDomain", + "path": "system.ruby.memctrl_clk_domain", + "type": "DerivedClockDomain", + "clk_divider": 3 + }, + "name": "ruby", + "p_state_clk_gate_bins": 20, + "block_size_bytes": 64, + "access_backing_store": false, + "number_of_virtual_networks": 5, + "num_of_sequencers": 1, + "dir_cntrl0": { + "system": "system", + "cluster_id": 0, + "responseFromMemory": { + "ordered": false, + "name": "responseFromMemory", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.dir_cntrl0.responseFromMemory", + "type": "MessageBuffer" + }, + "cxx_class": "Directory_Controller", + "forwardFromDir": { + "ordered": false, + "name": "forwardFromDir", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "master": { + "peer": "system.ruby.network.slave[4]", + "role": "MASTER" + }, + "buffer_size": 0, + "path": "system.ruby.dir_cntrl0.forwardFromDir", + "type": "MessageBuffer" + }, + "dmaRequestToDir": { + "ordered": true, + "name": "dmaRequestToDir", + "cxx_class": "MessageBuffer", + "slave": { + "peer": "system.ruby.network.master[3]", + "role": "SLAVE" + }, + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.dir_cntrl0.dmaRequestToDir", + "type": "MessageBuffer" + }, + "type": "Directory_Controller", + "recycle_latency": 10, + "clk_domain": "system.ruby.clk_domain", + "version": 0, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000, + "directory_latency": 12, + "number_of_TBEs": 256, + "to_memory_controller_latency": 1, + "p_state_clk_gate_min": 1, + "responseFromDir": { + "ordered": false, + "name": "responseFromDir", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "master": { + "peer": "system.ruby.network.slave[2]", + "role": "MASTER" + }, + "buffer_size": 0, + "path": "system.ruby.dir_cntrl0.responseFromDir", + "type": "MessageBuffer" + }, + "transitions_per_cycle": 4, + "memory": { + "peer": "system.mem_ctrls.port", + "role": "MASTER" + }, + "power_model": null, + "buffer_size": 0, + "ruby_system": "system.ruby", + "requestToDir": { + "ordered": true, + "name": "requestToDir", + "cxx_class": "MessageBuffer", + "slave": { + "peer": "system.ruby.network.master[2]", + "role": "SLAVE" + }, + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.dir_cntrl0.requestToDir", + "type": "MessageBuffer" + }, + "dmaResponseFromDir": { + "ordered": true, + "name": "dmaResponseFromDir", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "master": { + "peer": "system.ruby.network.slave[3]", + "role": "MASTER" + }, + "buffer_size": 0, + "path": "system.ruby.dir_cntrl0.dmaResponseFromDir", + "type": "MessageBuffer" + }, + "name": "dir_cntrl0", + "p_state_clk_gate_bins": 20, + "directory": { + "name": "directory", + "version": 0, + "eventq_index": 0, + "cxx_class": "DirectoryMemory", + "path": "system.ruby.dir_cntrl0.directory", + "type": "RubyDirectoryMemory", + "numa_high_bit": 5, + "size": 268435456 + }, + "path": "system.ruby.dir_cntrl0" + } + }, + "work_end_ckpt_count": 0, + "mem_mode": "timing", + "name": "system", + "init_param": 0, + "p_state_clk_gate_bins": 20, + "load_addr_mask": 1099511627775, + "cpu": { + "do_statistics_insts": true, + "numThreads": 1, + "itb": { + "name": "itb", + "eventq_index": 0, + "cxx_class": "RiscvISA::TLB", + "path": "system.cpu.itb", + "type": "RiscvTLB", + "size": 64 + }, + "system": "system", + "function_trace": false, + "do_checkpoint_insts": true, + "cxx_class": "TimingSimpleCPU", + "max_loads_all_threads": 0, + "clk_domain": { + "name": "clk_domain", + "clock": [ + 1 + ], + "init_perf_level": 0, + "voltage_domain": "system.voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.cpu.clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "function_trace_start": 0, + "cpu_id": 0, + "checker": null, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000, + "do_quiesce": true, + "type": "TimingSimpleCPU", + "profile": 0, + "icache_port": { + "peer": "system.ruby.l1_cntrl0.sequencer.slave[0]", + "role": "MASTER" + }, + "p_state_clk_gate_bins": 20, + "p_state_clk_gate_min": 1, + "interrupts": [ + { + "eventq_index": 0, + "path": "system.cpu.interrupts", + "type": "RiscvInterrupts", + "name": "interrupts", + "cxx_class": "RiscvISA::Interrupts" + } + ], + "dcache_port": { + "peer": "system.ruby.l1_cntrl0.sequencer.slave[1]", + "role": "MASTER" + }, + "socket_id": 0, + "power_model": null, + "max_insts_all_threads": 0, + "path": "system.cpu", + "max_loads_any_thread": 0, + "switched_out": false, + "workload": [ + { + "uid": 100, + "pid": 100, + "kvmInSE": false, + "cxx_class": "LiveProcess", + "executable": "/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64m/insttest", + "drivers": [], + "system": "system", + "gid": 100, + "eventq_index": 0, + "env": [], + "input": "cin", + "ppid": 99, + "type": "LiveProcess", + "cwd": "", + "simpoint": 0, + "euid": 100, + "path": "system.cpu.workload", + "max_stack_size": 67108864, + "name": "workload", + "cmd": [ + "insttest" + ], + "errout": "cerr", + "useArchPT": false, + "egid": 100, + "output": "cout" + } + ], + "name": "cpu", + "dtb": { + "name": "dtb", + "eventq_index": 0, + "cxx_class": "RiscvISA::TLB", + "path": "system.cpu.dtb", + "type": "RiscvTLB", + "size": 64 + }, + "simpoint_start_insts": [], + "max_insts_any_thread": 0, + "progress_interval": 0, + "branchPred": null, + "isa": [ + { + "eventq_index": 0, + "path": "system.cpu.isa", + "type": "RiscvISA", + "name": "isa", + "cxx_class": "RiscvISA::ISA" + } + ], + "tracer": { + "eventq_index": 0, + "path": "system.cpu.tracer", + "type": "ExeTracer", + "name": "tracer", + "cxx_class": "Trace::ExeTracer" + } + }, + "multi_thread": false, + "mem_ctrls": [ + { + "static_frontend_latency": 10, + "tRFC": 260, + "activation_limit": 4, + "in_addr_map": true, + "IDD3N2": "0.0", + "tWTR": 8, + "IDD52": "0.0", + "clk_domain": "system.clk_domain", + "channels": 1, + "write_buffer_size": 64, + "device_bus_width": 8, + "VDD": "1.5", + "write_high_thresh_perc": 85, + "cxx_class": "DRAMCtrl", + "bank_groups_per_rank": 0, + "IDD2N2": "0.0", + "port": { + "peer": "system.ruby.dir_cntrl0.memory", + "role": "SLAVE" + }, + "tCCD_L": 0, + "IDD2N": "0.032", + "p_state_clk_gate_min": 1, + "null": false, + "IDD2P1": "0.032", + "eventq_index": 0, + "tRRD": 6, + "tRTW": 3, + "IDD4R": "0.157", + "burst_length": 8, + "tRTP": 8, + "IDD4W": "0.125", + "tWR": 15, + "banks_per_rank": 8, + "devices_per_rank": 8, + "IDD2P02": "0.0", + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000, + "IDD6": "0.02", + "IDD5": "0.235", + "tRCD": 14, + "type": "DRAMCtrl", + "IDD3P02": "0.0", + "tRRD_L": 0, + "IDD0": "0.055", + "IDD62": "0.0", + "min_writes_per_switch": 16, + "mem_sched_policy": "frfcfs", + "IDD02": "0.0", + "IDD2P0": "0.0", + "ranks_per_channel": 2, + "page_policy": "open_adaptive", + "IDD4W2": "0.0", + "tCS": 3, + "power_model": null, + "tCL": 14, + "read_buffer_size": 32, + "conf_table_reported": true, + "tCK": 1, + "tRAS": 35, + "tRP": 14, + "tBURST": 5, + "path": "system.mem_ctrls", + "tXP": 6, + "tXS": 270, + "addr_mapping": "RoRaBaCoCh", + "IDD3P0": "0.0", + "IDD3P1": "0.038", + "IDD3N": "0.038", + "name": "mem_ctrls", + "tXSDLL": 0, + "device_size": 536870912, + "kvm_map": true, + "dll": true, + "tXAW": 30, + "write_low_thresh_perc": 50, + "range": "0:268435455:5:19:0:0", + "VDD2": "0.0", + "IDD2P12": "0.0", + "p_state_clk_gate_bins": 20, + "tXPDLL": 0, + "IDD4R2": "0.0", + "device_rowbuffer_size": 1024, + "static_backend_latency": 10, + "max_accesses_per_row": 16, + "IDD3P12": "0.0", + "tREFI": 7800 + } + ], + "exit_on_work_items": false, + "work_item_id": -1, + "num_work_ids": 16 + }, + "time_sync_period": 100000000, + "eventq_index": 0, + "time_sync_spin_threshold": 100000, + "cxx_class": "Root", + "path": "root", + "time_sync_enable": false, + "type": "Root", + "full_system": false +}
\ No newline at end of file diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/simple-timing-ruby/simerr b/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/simple-timing-ruby/simerr new file mode 100755 index 000000000..63b14556f --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/simple-timing-ruby/simerr @@ -0,0 +1,11 @@ +warn: rounding error > tolerance + 1.250000 rounded to 1 +warn: rounding error > tolerance + 1.250000 rounded to 1 +warn: rounding error > tolerance + 1.250000 rounded to 1 +warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes) +warn: Unknown operating system; assuming Linux. +warn: Sockets disabled, not accepting gdb connections +warn: ClockedObject: More than one power state change request encountered within the same simulation tick +warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files! diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/simple-timing-ruby/simout b/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/simple-timing-ruby/simout new file mode 100755 index 000000000..81d54f27f --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/simple-timing-ruby/simout @@ -0,0 +1,51 @@ +Redirecting stdout to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64m/simple-timing-ruby/simout +Redirecting stderr to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64m/simple-timing-ruby/simerr +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled Nov 30 2016 14:33:35 +gem5 started Nov 30 2016 16:18:53 +gem5 executing on zizzer, pid 34103 +command line: /z/powerjg/gem5-upstream/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64m/simple-timing-ruby -re /z/powerjg/gem5-upstream/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64m/simple-timing-ruby + +Global frequency set at 1000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. +mul: PASS +mul, overflow: PASS +mulh: PASS +mulh, negative: PASS +mulh, all bits set: PASS +mulhsu, all bits set: PASS +mulhsu: PASS +mulhu: PASS +mulhu, all bits set: PASS +div: PASS +div/0: PASS +div, overflow: PASS +divu: PASS +divu/0: PASS +divu, "overflow": PASS +rem: PASS +rem/0: PASS +rem, overflow: PASS +remu: PASS +remu/0: PASS +remu, "overflow": PASS +mulw, truncate: PASS +mulw, overflow: PASS +divw, truncate: PASS +divw/0: PASS +divw, overflow: PASS +divuw, truncate: PASS +divuw/0: PASS +divuw, "overflow": PASS +divuw, sign extend: PASS +remw, truncate: PASS +remw/0: PASS +remw, overflow: PASS +remuw, truncate: PASS +remuw/0: PASS +remuw, "overflow": PASS +remuw, sign extend: PASS +Exiting @ tick 1841805 because target called exit() diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/simple-timing-ruby/stats.txt b/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/simple-timing-ruby/stats.txt new file mode 100644 index 000000000..bf416790e --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/simple-timing-ruby/stats.txt @@ -0,0 +1,644 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.001842 # Number of seconds simulated +sim_ticks 1841805 # Number of ticks simulated +final_tick 1841805 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000 # Frequency of simulated ticks +host_inst_rate 30529 # Simulator instruction rate (inst/s) +host_op_rate 30529 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 496310 # Simulator tick rate (ticks/s) +host_mem_usage 411128 # Number of bytes of host memory used +host_seconds 3.71 # Real time elapsed on the host +sim_insts 113291 # Number of instructions simulated +sim_ops 113291 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1 # Clock period in ticks +system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 1841805 # Cumulative time (in ticks) in various power states +system.mem_ctrls.bytes_read::ruby.dir_cntrl0 1901888 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::total 1901888 # Number of bytes read from this memory +system.mem_ctrls.bytes_written::ruby.dir_cntrl0 1901632 # Number of bytes written to this memory +system.mem_ctrls.bytes_written::total 1901632 # Number of bytes written to this memory +system.mem_ctrls.num_reads::ruby.dir_cntrl0 29717 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::total 29717 # Number of read requests responded to by this memory +system.mem_ctrls.num_writes::ruby.dir_cntrl0 29713 # Number of write requests responded to by this memory +system.mem_ctrls.num_writes::total 29713 # Number of write requests responded to by this memory +system.mem_ctrls.bw_read::ruby.dir_cntrl0 1032621803 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::total 1032621803 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::ruby.dir_cntrl0 1032482809 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::total 1032482809 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_total::ruby.dir_cntrl0 2065104612 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::total 2065104612 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.readReqs 29717 # Number of read requests accepted +system.mem_ctrls.writeReqs 29713 # Number of write requests accepted +system.mem_ctrls.readBursts 29717 # Number of DRAM read bursts, including those serviced by the write queue +system.mem_ctrls.writeBursts 29713 # Number of DRAM write bursts, including those merged in the write queue +system.mem_ctrls.bytesReadDRAM 810816 # Total number of bytes read from DRAM +system.mem_ctrls.bytesReadWrQ 1091072 # Total number of bytes read from write queue +system.mem_ctrls.bytesWritten 842496 # Total number of bytes written to DRAM +system.mem_ctrls.bytesReadSys 1901888 # Total read bytes from the system interface side +system.mem_ctrls.bytesWrittenSys 1901632 # Total written bytes from the system interface side +system.mem_ctrls.servicedByWrQ 17048 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrls.mergedWrBursts 16517 # Number of DRAM write bursts merged with an existing one +system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.mem_ctrls.perBankRdBursts::0 1366 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::1 3 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::2 241 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::3 400 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::4 244 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::5 371 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::6 334 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::7 67 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::8 341 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::9 2380 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::10 1301 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::11 1236 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::12 1592 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::13 483 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::14 2223 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::15 87 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::0 1405 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::1 3 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::2 241 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::3 412 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::4 257 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::5 383 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::6 346 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::7 69 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::8 351 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::9 2448 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::10 1316 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::11 1275 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::12 1634 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::13 505 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::14 2424 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::15 95 # Per bank write bursts +system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry +system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry +system.mem_ctrls.totGap 1841733 # Total gap between requests +system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::6 29717 # Read request sizes (log2) +system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::6 29713 # Write request sizes (log2) +system.mem_ctrls.rdQLenPdf::0 12669 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::1 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::2 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::4 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::0 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::1 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::2 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::3 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::4 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::5 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::6 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::7 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::8 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::9 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::10 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::11 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::15 104 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::16 124 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::17 715 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::18 812 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::19 810 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::20 826 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::21 868 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::22 857 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::23 811 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::24 806 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::25 806 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::26 807 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::27 806 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::28 806 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::29 806 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::30 806 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::31 806 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::32 805 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.mem_ctrls.bytesPerActivate::samples 4235 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::mean 390.135537 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::gmean 255.090286 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::stdev 338.320461 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::0-127 828 19.55% 19.55% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::128-255 1136 26.82% 46.38% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::256-383 580 13.70% 60.07% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::384-511 361 8.52% 68.60% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::512-639 278 6.56% 75.16% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::640-767 169 3.99% 79.15% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::768-895 146 3.45% 82.60% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::896-1023 150 3.54% 86.14% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::1024-1151 587 13.86% 100.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::total 4235 # Bytes accessed per row activation +system.mem_ctrls.rdPerTurnAround::samples 805 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::mean 15.719255 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::gmean 15.645655 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::stdev 1.595450 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::12-13 50 6.21% 6.21% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::14-15 309 38.39% 44.60% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::16-17 373 46.34% 90.93% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::18-19 65 8.07% 99.01% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::20-21 7 0.87% 99.88% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::36-37 1 0.12% 100.00% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::total 805 # Reads before turning the bus around for writes +system.mem_ctrls.wrPerTurnAround::samples 805 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::mean 16.352795 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::gmean 16.329834 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::stdev 0.903150 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::16 691 85.84% 85.84% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::17 4 0.50% 86.34% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::18 56 6.96% 93.29% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::19 48 5.96% 99.25% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::20 6 0.75% 100.00% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::total 805 # Writes before turning the bus around for reads +system.mem_ctrls.totQLat 239535 # Total ticks spent queuing +system.mem_ctrls.totMemAccLat 480246 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.totBusLat 63345 # Total ticks spent in databus transfers +system.mem_ctrls.avgQLat 18.91 # Average queueing delay per DRAM burst +system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst +system.mem_ctrls.avgMemAccLat 37.91 # Average memory access latency per DRAM burst +system.mem_ctrls.avgRdBW 440.23 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrls.avgWrBW 457.43 # Average achieved write bandwidth in MiByte/s +system.mem_ctrls.avgRdBWSys 1032.62 # Average system read bandwidth in MiByte/s +system.mem_ctrls.avgWrBWSys 1032.48 # Average system write bandwidth in MiByte/s +system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.mem_ctrls.busUtil 7.01 # Data bus utilization in percentage +system.mem_ctrls.busUtilRead 3.44 # Data bus utilization in percentage for reads +system.mem_ctrls.busUtilWrite 3.57 # Data bus utilization in percentage for writes +system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing +system.mem_ctrls.avgWrQLen 25.93 # Average write queue length when enqueuing +system.mem_ctrls.readRowHits 9468 # Number of row buffer hits during reads +system.mem_ctrls.writeRowHits 12124 # Number of row buffer hits during writes +system.mem_ctrls.readRowHitRate 74.73 # Row buffer hit rate for reads +system.mem_ctrls.writeRowHitRate 91.88 # Row buffer hit rate for writes +system.mem_ctrls.avgGap 30.99 # Average gap between requests +system.mem_ctrls.pageHitRate 83.48 # Row buffer hit rate, read and write combined +system.mem_ctrls_0.actEnergy 10074540 # Energy for activate commands per rank (pJ) +system.mem_ctrls_0.preEnergy 5448240 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_0.readEnergy 34569024 # Energy for read commands per rank (pJ) +system.mem_ctrls_0.writeEnergy 26024832 # Energy for write commands per rank (pJ) +system.mem_ctrls_0.refreshEnergy 127230480.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_0.actBackEnergy 197709288 # Energy for active background per rank (pJ) +system.mem_ctrls_0.preBackEnergy 3259392 # Energy for precharge background per rank (pJ) +system.mem_ctrls_0.actPowerDownEnergy 446690304 # Energy for active power-down per rank (pJ) +system.mem_ctrls_0.prePowerDownEnergy 61497984 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls_0.selfRefreshEnergy 65163360 # Energy for self refresh per rank (pJ) +system.mem_ctrls_0.totalEnergy 977667444 # Total energy per rank (pJ) +system.mem_ctrls_0.averagePower 530.820279 # Core power per rank (mW) +system.mem_ctrls_0.totalIdleTime 1399707 # Total Idle time Per DRAM Rank +system.mem_ctrls_0.memoryStateTime::IDLE 2653 # Time in different power states +system.mem_ctrls_0.memoryStateTime::REF 53850 # Time in different power states +system.mem_ctrls_0.memoryStateTime::SREF 260009 # Time in different power states +system.mem_ctrls_0.memoryStateTime::PRE_PDN 160151 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT 385558 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT_PDN 979584 # Time in different power states +system.mem_ctrls_1.actEnergy 20206200 # Energy for activate commands per rank (pJ) +system.mem_ctrls_1.preEnergy 10915800 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_1.readEnergy 110161632 # Energy for read commands per rank (pJ) +system.mem_ctrls_1.writeEnergy 83920896 # Energy for write commands per rank (pJ) +system.mem_ctrls_1.refreshEnergy 145055040.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_1.actBackEnergy 217978032 # Energy for active background per rank (pJ) +system.mem_ctrls_1.preBackEnergy 3880704 # Energy for precharge background per rank (pJ) +system.mem_ctrls_1.actPowerDownEnergy 529686864 # Energy for active power-down per rank (pJ) +system.mem_ctrls_1.prePowerDownEnergy 51989376 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls_1.selfRefreshEnergy 18024480 # Energy for self refresh per rank (pJ) +system.mem_ctrls_1.totalEnergy 1191819024 # Total energy per rank (pJ) +system.mem_ctrls_1.averagePower 647.092946 # Core power per rank (mW) +system.mem_ctrls_1.totalIdleTime 1353468 # Total Idle time Per DRAM Rank +system.mem_ctrls_1.memoryStateTime::IDLE 3236 # Time in different power states +system.mem_ctrls_1.memoryStateTime::REF 61408 # Time in different power states +system.mem_ctrls_1.memoryStateTime::SREF 56694 # Time in different power states +system.mem_ctrls_1.memoryStateTime::PRE_PDN 135389 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT 423484 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT_PDN 1161594 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 1841805 # Cumulative time (in ticks) in various power states +system.cpu.clk_domain.clock 1 # Clock period in ticks +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 45 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 1841805 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 1841805 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 113291 # Number of instructions committed +system.cpu.committedOps 113291 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 113292 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses +system.cpu.num_func_calls 8529 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 17391 # number of instructions that are conditional controls +system.cpu.num_int_insts 113292 # number of integer instructions +system.cpu.num_fp_insts 0 # number of float instructions +system.cpu.num_int_register_reads 151096 # number of times the integer registers were read +system.cpu.num_int_register_writes 76188 # number of times the integer registers were written +system.cpu.num_fp_register_reads 0 # number of times the floating registers were read +system.cpu.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu.num_mem_refs 43493 # number of memory refs +system.cpu.num_load_insts 23780 # Number of load instructions +system.cpu.num_store_insts 19713 # Number of store instructions +system.cpu.num_idle_cycles 0 # Number of idle cycles +system.cpu.num_busy_cycles 1841805 # Number of busy cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.Branches 25920 # Number of branches fetched +system.cpu.op_class::No_OpClass 45 0.04% 0.04% # Class of executed instruction +system.cpu.op_class::IntAlu 69651 61.45% 61.49% # Class of executed instruction +system.cpu.op_class::IntMult 122 0.11% 61.60% # Class of executed instruction +system.cpu.op_class::IntDiv 26 0.02% 61.63% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 61.63% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 61.63% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 61.63% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 61.63% # Class of executed instruction +system.cpu.op_class::FloatMultAcc 0 0.00% 61.63% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 61.63% # Class of executed instruction +system.cpu.op_class::FloatMisc 0 0.00% 61.63% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 61.63% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 61.63% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 61.63% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 61.63% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 61.63% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 61.63% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 61.63% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 61.63% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 61.63% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 61.63% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 61.63% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 61.63% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 61.63% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 61.63% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 61.63% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 61.63% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 61.63% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 61.63% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 61.63% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 61.63% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 61.63% # Class of executed instruction +system.cpu.op_class::MemRead 23780 20.98% 82.61% # Class of executed instruction +system.cpu.op_class::MemWrite 19713 17.39% 100.00% # Class of executed instruction +system.cpu.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 113337 # Class of executed instruction +system.ruby.clk_domain.clock 1 # Clock period in ticks +system.ruby.pwrStateResidencyTicks::UNDEFINED 1841805 # Cumulative time (in ticks) in various power states +system.ruby.delayHist::bucket_size 1 # delay histogram for all message +system.ruby.delayHist::max_bucket 9 # delay histogram for all message +system.ruby.delayHist::samples 59430 # delay histogram for all message +system.ruby.delayHist | 59430 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message +system.ruby.delayHist::total 59430 # delay histogram for all message +system.ruby.outstanding_req_hist_seqr::bucket_size 1 +system.ruby.outstanding_req_hist_seqr::max_bucket 9 +system.ruby.outstanding_req_hist_seqr::samples 156830 +system.ruby.outstanding_req_hist_seqr::mean 1 +system.ruby.outstanding_req_hist_seqr::gmean 1 +system.ruby.outstanding_req_hist_seqr | 0 0.00% 0.00% | 156830 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.outstanding_req_hist_seqr::total 156830 +system.ruby.latency_hist_seqr::bucket_size 64 +system.ruby.latency_hist_seqr::max_bucket 639 +system.ruby.latency_hist_seqr::samples 156829 +system.ruby.latency_hist_seqr::mean 10.744033 +system.ruby.latency_hist_seqr::gmean 2.067079 +system.ruby.latency_hist_seqr::stdev 25.213617 +system.ruby.latency_hist_seqr | 144536 92.16% 92.16% | 11426 7.29% 99.45% | 606 0.39% 99.83% | 87 0.06% 99.89% | 95 0.06% 99.95% | 65 0.04% 99.99% | 1 0.00% 99.99% | 3 0.00% 99.99% | 0 0.00% 99.99% | 10 0.01% 100.00% +system.ruby.latency_hist_seqr::total 156829 +system.ruby.hit_latency_hist_seqr::bucket_size 1 +system.ruby.hit_latency_hist_seqr::max_bucket 9 +system.ruby.hit_latency_hist_seqr::samples 127112 +system.ruby.hit_latency_hist_seqr::mean 1 +system.ruby.hit_latency_hist_seqr::gmean 1 +system.ruby.hit_latency_hist_seqr | 0 0.00% 0.00% | 127112 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.hit_latency_hist_seqr::total 127112 +system.ruby.miss_latency_hist_seqr::bucket_size 64 +system.ruby.miss_latency_hist_seqr::max_bucket 639 +system.ruby.miss_latency_hist_seqr::samples 29717 +system.ruby.miss_latency_hist_seqr::mean 52.423327 +system.ruby.miss_latency_hist_seqr::gmean 46.160524 +system.ruby.miss_latency_hist_seqr::stdev 34.809845 +system.ruby.miss_latency_hist_seqr | 17424 58.63% 58.63% | 11426 38.45% 97.08% | 606 2.04% 99.12% | 87 0.29% 99.41% | 95 0.32% 99.73% | 65 0.22% 99.95% | 1 0.00% 99.96% | 3 0.01% 99.97% | 0 0.00% 99.97% | 10 0.03% 100.00% +system.ruby.miss_latency_hist_seqr::total 29717 +system.ruby.Directory.incomplete_times_seqr 29716 +system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 1841805 # Cumulative time (in ticks) in various power states +system.ruby.l1_cntrl0.cacheMemory.demand_hits 127112 # Number of cache demand hits +system.ruby.l1_cntrl0.cacheMemory.demand_misses 29717 # Number of cache demand misses +system.ruby.l1_cntrl0.cacheMemory.demand_accesses 156829 # Number of cache demand accesses +system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 1841805 # Cumulative time (in ticks) in various power states +system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 1841805 # Cumulative time (in ticks) in various power states +system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks +system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 1841805 # Cumulative time (in ticks) in various power states +system.ruby.network.routers0.percent_links_utilized 8.066815 +system.ruby.network.routers0.msg_count.Control::2 29717 +system.ruby.network.routers0.msg_count.Data::2 29713 +system.ruby.network.routers0.msg_count.Response_Data::4 29717 +system.ruby.network.routers0.msg_count.Writeback_Control::3 29713 +system.ruby.network.routers0.msg_bytes.Control::2 237736 +system.ruby.network.routers0.msg_bytes.Data::2 2139336 +system.ruby.network.routers0.msg_bytes.Response_Data::4 2139624 +system.ruby.network.routers0.msg_bytes.Writeback_Control::3 237704 +system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 1841805 # Cumulative time (in ticks) in various power states +system.ruby.network.routers1.percent_links_utilized 8.066815 +system.ruby.network.routers1.msg_count.Control::2 29717 +system.ruby.network.routers1.msg_count.Data::2 29713 +system.ruby.network.routers1.msg_count.Response_Data::4 29717 +system.ruby.network.routers1.msg_count.Writeback_Control::3 29713 +system.ruby.network.routers1.msg_bytes.Control::2 237736 +system.ruby.network.routers1.msg_bytes.Data::2 2139336 +system.ruby.network.routers1.msg_bytes.Response_Data::4 2139624 +system.ruby.network.routers1.msg_bytes.Writeback_Control::3 237704 +system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 1841805 # Cumulative time (in ticks) in various power states +system.ruby.network.routers2.percent_links_utilized 8.066815 +system.ruby.network.routers2.msg_count.Control::2 29717 +system.ruby.network.routers2.msg_count.Data::2 29713 +system.ruby.network.routers2.msg_count.Response_Data::4 29717 +system.ruby.network.routers2.msg_count.Writeback_Control::3 29713 +system.ruby.network.routers2.msg_bytes.Control::2 237736 +system.ruby.network.routers2.msg_bytes.Data::2 2139336 +system.ruby.network.routers2.msg_bytes.Response_Data::4 2139624 +system.ruby.network.routers2.msg_bytes.Writeback_Control::3 237704 +system.ruby.network.pwrStateResidencyTicks::UNDEFINED 1841805 # Cumulative time (in ticks) in various power states +system.ruby.network.msg_count.Control 89151 +system.ruby.network.msg_count.Data 89139 +system.ruby.network.msg_count.Response_Data 89151 +system.ruby.network.msg_count.Writeback_Control 89139 +system.ruby.network.msg_byte.Control 713208 +system.ruby.network.msg_byte.Data 6418008 +system.ruby.network.msg_byte.Response_Data 6418872 +system.ruby.network.msg_byte.Writeback_Control 713112 +system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 1841805 # Cumulative time (in ticks) in various power states +system.ruby.network.routers0.throttle0.link_utilization 8.067249 +system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 29717 +system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 29713 +system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 2139624 +system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3 237704 +system.ruby.network.routers0.throttle1.link_utilization 8.066381 +system.ruby.network.routers0.throttle1.msg_count.Control::2 29717 +system.ruby.network.routers0.throttle1.msg_count.Data::2 29713 +system.ruby.network.routers0.throttle1.msg_bytes.Control::2 237736 +system.ruby.network.routers0.throttle1.msg_bytes.Data::2 2139336 +system.ruby.network.routers1.throttle0.link_utilization 8.066381 +system.ruby.network.routers1.throttle0.msg_count.Control::2 29717 +system.ruby.network.routers1.throttle0.msg_count.Data::2 29713 +system.ruby.network.routers1.throttle0.msg_bytes.Control::2 237736 +system.ruby.network.routers1.throttle0.msg_bytes.Data::2 2139336 +system.ruby.network.routers1.throttle1.link_utilization 8.067249 +system.ruby.network.routers1.throttle1.msg_count.Response_Data::4 29717 +system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::3 29713 +system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4 2139624 +system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::3 237704 +system.ruby.network.routers2.throttle0.link_utilization 8.067249 +system.ruby.network.routers2.throttle0.msg_count.Response_Data::4 29717 +system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3 29713 +system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4 2139624 +system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3 237704 +system.ruby.network.routers2.throttle1.link_utilization 8.066381 +system.ruby.network.routers2.throttle1.msg_count.Control::2 29717 +system.ruby.network.routers2.throttle1.msg_count.Data::2 29713 +system.ruby.network.routers2.throttle1.msg_bytes.Control::2 237736 +system.ruby.network.routers2.throttle1.msg_bytes.Data::2 2139336 +system.ruby.delayVCHist.vnet_1::bucket_size 1 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1::max_bucket 9 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1::samples 29717 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1 | 29717 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1::total 29717 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_2::bucket_size 1 # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2::max_bucket 9 # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2::samples 29713 # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2 | 29713 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2::total 29713 # delay histogram for vnet_2 +system.ruby.LD.latency_hist_seqr::bucket_size 64 +system.ruby.LD.latency_hist_seqr::max_bucket 639 +system.ruby.LD.latency_hist_seqr::samples 23780 +system.ruby.LD.latency_hist_seqr::mean 23.543860 +system.ruby.LD.latency_hist_seqr::gmean 5.728326 +system.ruby.LD.latency_hist_seqr::stdev 33.566569 +system.ruby.LD.latency_hist_seqr | 19950 83.89% 83.89% | 3533 14.86% 98.75% | 205 0.86% 99.61% | 27 0.11% 99.73% | 36 0.15% 99.88% | 25 0.11% 99.98% | 0 0.00% 99.98% | 2 0.01% 99.99% | 0 0.00% 99.99% | 2 0.01% 100.00% +system.ruby.LD.latency_hist_seqr::total 23780 +system.ruby.LD.hit_latency_hist_seqr::bucket_size 1 +system.ruby.LD.hit_latency_hist_seqr::max_bucket 9 +system.ruby.LD.hit_latency_hist_seqr::samples 12809 +system.ruby.LD.hit_latency_hist_seqr::mean 1 +system.ruby.LD.hit_latency_hist_seqr::gmean 1 +system.ruby.LD.hit_latency_hist_seqr | 0 0.00% 0.00% | 12809 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.hit_latency_hist_seqr::total 12809 +system.ruby.LD.miss_latency_hist_seqr::bucket_size 64 +system.ruby.LD.miss_latency_hist_seqr::max_bucket 639 +system.ruby.LD.miss_latency_hist_seqr::samples 10971 +system.ruby.LD.miss_latency_hist_seqr::mean 49.864552 +system.ruby.LD.miss_latency_hist_seqr::gmean 43.959200 +system.ruby.LD.miss_latency_hist_seqr::stdev 34.000652 +system.ruby.LD.miss_latency_hist_seqr | 7141 65.09% 65.09% | 3533 32.20% 97.29% | 205 1.87% 99.16% | 27 0.25% 99.41% | 36 0.33% 99.74% | 25 0.23% 99.96% | 0 0.00% 99.96% | 2 0.02% 99.98% | 0 0.00% 99.98% | 2 0.02% 100.00% +system.ruby.LD.miss_latency_hist_seqr::total 10971 +system.ruby.ST.latency_hist_seqr::bucket_size 64 +system.ruby.ST.latency_hist_seqr::max_bucket 639 +system.ruby.ST.latency_hist_seqr::samples 19712 +system.ruby.ST.latency_hist_seqr::mean 12.481128 +system.ruby.ST.latency_hist_seqr::gmean 2.637325 +system.ruby.ST.latency_hist_seqr::stdev 25.900228 +system.ruby.ST.latency_hist_seqr | 18468 93.69% 93.69% | 1151 5.84% 99.53% | 59 0.30% 99.83% | 14 0.07% 99.90% | 7 0.04% 99.93% | 6 0.03% 99.96% | 0 0.00% 99.96% | 0 0.00% 99.96% | 0 0.00% 99.96% | 7 0.04% 100.00% +system.ruby.ST.latency_hist_seqr::total 19712 +system.ruby.ST.hit_latency_hist_seqr::bucket_size 1 +system.ruby.ST.hit_latency_hist_seqr::max_bucket 9 +system.ruby.ST.hit_latency_hist_seqr::samples 14522 +system.ruby.ST.hit_latency_hist_seqr::mean 1 +system.ruby.ST.hit_latency_hist_seqr::gmean 1 +system.ruby.ST.hit_latency_hist_seqr | 0 0.00% 0.00% | 14522 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.hit_latency_hist_seqr::total 14522 +system.ruby.ST.miss_latency_hist_seqr::bucket_size 64 +system.ruby.ST.miss_latency_hist_seqr::max_bucket 639 +system.ruby.ST.miss_latency_hist_seqr::samples 5190 +system.ruby.ST.miss_latency_hist_seqr::mean 44.606166 +system.ruby.ST.miss_latency_hist_seqr::gmean 39.775024 +system.ruby.ST.miss_latency_hist_seqr::stdev 33.868458 +system.ruby.ST.miss_latency_hist_seqr | 3946 76.03% 76.03% | 1151 22.18% 98.21% | 59 1.14% 99.34% | 14 0.27% 99.61% | 7 0.13% 99.75% | 6 0.12% 99.87% | 0 0.00% 99.87% | 0 0.00% 99.87% | 0 0.00% 99.87% | 7 0.13% 100.00% +system.ruby.ST.miss_latency_hist_seqr::total 5190 +system.ruby.IFETCH.latency_hist_seqr::bucket_size 64 +system.ruby.IFETCH.latency_hist_seqr::max_bucket 639 +system.ruby.IFETCH.latency_hist_seqr::samples 113337 +system.ruby.IFETCH.latency_hist_seqr::mean 7.756293 +system.ruby.IFETCH.latency_hist_seqr::gmean 1.599835 +system.ruby.IFETCH.latency_hist_seqr::stdev 21.972545 +system.ruby.IFETCH.latency_hist_seqr | 106118 93.63% 93.63% | 6742 5.95% 99.58% | 342 0.30% 99.88% | 46 0.04% 99.92% | 52 0.05% 99.97% | 34 0.03% 100.00% | 1 0.00% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% | 1 0.00% 100.00% +system.ruby.IFETCH.latency_hist_seqr::total 113337 +system.ruby.IFETCH.hit_latency_hist_seqr::bucket_size 1 +system.ruby.IFETCH.hit_latency_hist_seqr::max_bucket 9 +system.ruby.IFETCH.hit_latency_hist_seqr::samples 99781 +system.ruby.IFETCH.hit_latency_hist_seqr::mean 1 +system.ruby.IFETCH.hit_latency_hist_seqr::gmean 1 +system.ruby.IFETCH.hit_latency_hist_seqr | 0 0.00% 0.00% | 99781 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.hit_latency_hist_seqr::total 99781 +system.ruby.IFETCH.miss_latency_hist_seqr::bucket_size 64 +system.ruby.IFETCH.miss_latency_hist_seqr::max_bucket 639 +system.ruby.IFETCH.miss_latency_hist_seqr::samples 13556 +system.ruby.IFETCH.miss_latency_hist_seqr::mean 57.487017 +system.ruby.IFETCH.miss_latency_hist_seqr::gmean 50.839427 +system.ruby.IFETCH.miss_latency_hist_seqr::stdev 35.033938 +system.ruby.IFETCH.miss_latency_hist_seqr | 6337 46.75% 46.75% | 6742 49.73% 96.48% | 342 2.52% 99.00% | 46 0.34% 99.34% | 52 0.38% 99.73% | 34 0.25% 99.98% | 1 0.01% 99.99% | 1 0.01% 99.99% | 0 0.00% 99.99% | 1 0.01% 100.00% +system.ruby.IFETCH.miss_latency_hist_seqr::total 13556 +system.ruby.Directory.miss_mach_latency_hist_seqr::bucket_size 64 +system.ruby.Directory.miss_mach_latency_hist_seqr::max_bucket 639 +system.ruby.Directory.miss_mach_latency_hist_seqr::samples 29717 +system.ruby.Directory.miss_mach_latency_hist_seqr::mean 52.423327 +system.ruby.Directory.miss_mach_latency_hist_seqr::gmean 46.160524 +system.ruby.Directory.miss_mach_latency_hist_seqr::stdev 34.809845 +system.ruby.Directory.miss_mach_latency_hist_seqr | 17424 58.63% 58.63% | 11426 38.45% 97.08% | 606 2.04% 99.12% | 87 0.29% 99.41% | 95 0.32% 99.73% | 65 0.22% 99.95% | 1 0.00% 99.96% | 3 0.01% 99.97% | 0 0.00% 99.97% | 10 0.03% 100.00% +system.ruby.Directory.miss_mach_latency_hist_seqr::total 29717 +system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::bucket_size 1 +system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::max_bucket 9 +system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::samples 1 +system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::stdev nan +system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::total 1 +system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::bucket_size 1 +system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::max_bucket 9 +system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::samples 1 +system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::stdev nan +system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::total 1 +system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::bucket_size 1 +system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::max_bucket 9 +system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::samples 1 +system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::stdev nan +system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::total 1 +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::bucket_size 8 +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::max_bucket 79 +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::samples 1 +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::mean 75 +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::gmean 75.000000 +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::stdev nan +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::total 1 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::samples 10971 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::mean 49.864552 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::gmean 43.959200 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::stdev 34.000652 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr | 7141 65.09% 65.09% | 3533 32.20% 97.29% | 205 1.87% 99.16% | 27 0.25% 99.41% | 36 0.33% 99.74% | 25 0.23% 99.96% | 0 0.00% 99.96% | 2 0.02% 99.98% | 0 0.00% 99.98% | 2 0.02% 100.00% +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::total 10971 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::samples 5190 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::mean 44.606166 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::gmean 39.775024 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::stdev 33.868458 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr | 3946 76.03% 76.03% | 1151 22.18% 98.21% | 59 1.14% 99.34% | 14 0.27% 99.61% | 7 0.13% 99.75% | 6 0.12% 99.87% | 0 0.00% 99.87% | 0 0.00% 99.87% | 0 0.00% 99.87% | 7 0.13% 100.00% +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::total 5190 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::samples 13556 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::mean 57.487017 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::gmean 50.839427 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::stdev 35.033938 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr | 6337 46.75% 46.75% | 6742 49.73% 96.48% | 342 2.52% 99.00% | 46 0.34% 99.34% | 52 0.38% 99.73% | 34 0.25% 99.98% | 1 0.01% 99.99% | 1 0.01% 99.99% | 0 0.00% 99.99% | 1 0.01% 100.00% +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::total 13556 +system.ruby.Directory_Controller.GETX 29717 0.00% 0.00% +system.ruby.Directory_Controller.PUTX 29713 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Data 29717 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Ack 29713 0.00% 0.00% +system.ruby.Directory_Controller.I.GETX 29717 0.00% 0.00% +system.ruby.Directory_Controller.M.PUTX 29713 0.00% 0.00% +system.ruby.Directory_Controller.IM.Memory_Data 29717 0.00% 0.00% +system.ruby.Directory_Controller.MI.Memory_Ack 29713 0.00% 0.00% +system.ruby.L1Cache_Controller.Load 23780 0.00% 0.00% +system.ruby.L1Cache_Controller.Ifetch 113337 0.00% 0.00% +system.ruby.L1Cache_Controller.Store 19712 0.00% 0.00% +system.ruby.L1Cache_Controller.Data 29717 0.00% 0.00% +system.ruby.L1Cache_Controller.Replacement 29713 0.00% 0.00% +system.ruby.L1Cache_Controller.Writeback_Ack 29713 0.00% 0.00% +system.ruby.L1Cache_Controller.I.Load 10971 0.00% 0.00% +system.ruby.L1Cache_Controller.I.Ifetch 13556 0.00% 0.00% +system.ruby.L1Cache_Controller.I.Store 5190 0.00% 0.00% +system.ruby.L1Cache_Controller.M.Load 12809 0.00% 0.00% +system.ruby.L1Cache_Controller.M.Ifetch 99781 0.00% 0.00% +system.ruby.L1Cache_Controller.M.Store 14522 0.00% 0.00% +system.ruby.L1Cache_Controller.M.Replacement 29713 0.00% 0.00% +system.ruby.L1Cache_Controller.MI.Writeback_Ack 29713 0.00% 0.00% +system.ruby.L1Cache_Controller.IS.Data 24527 0.00% 0.00% +system.ruby.L1Cache_Controller.IM.Data 5190 0.00% 0.00% + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/simple-timing/config.ini b/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/simple-timing/config.ini new file mode 100644 index 000000000..4d0cc1f98 --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/simple-timing/config.ini @@ -0,0 +1,380 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain +boot_osflags=a +cache_line_size=64 +clk_domain=system.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +exit_on_work_items=false +init_param=0 +kernel= +kernel_addr_check=true +load_addr_mask=1099511627775 +load_offset=0 +mem_mode=timing +mem_ranges= +memories=system.physmem +mmap_using_noreserve=false +multi_thread=false +num_work_ids=16 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +readfile= +symbolfile= +thermal_components= +thermal_model=Null +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=TimingSimpleCPU +children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload +branchPred=Null +checker=Null +clk_domain=system.cpu_clk_domain +cpu_id=0 +default_p_state=UNDEFINED +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +eventq_index=0 +function_trace=false +function_trace_start=0 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +profile=0 +progress_interval=0 +simpoint_start_insts= +socket_id=0 +switched_out=false +system=system +tracer=system.cpu.tracer +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.dcache] +type=Cache +children=tags +addr_ranges=0:18446744073709551615:0:0:0:0 +assoc=2 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +data_latency=2 +default_p_state=UNDEFINED +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=4 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=262144 +system=system +tag_latency=2 +tags=system.cpu.dcache.tags +tgts_per_mshr=20 +write_buffers=8 +writeback_clean=false +cpu_side=system.cpu.dcache_port +mem_side=system.cpu.toL2Bus.slave[1] + +[system.cpu.dcache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +data_latency=2 +default_p_state=UNDEFINED +eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +sequential_access=false +size=262144 +tag_latency=2 + +[system.cpu.dtb] +type=RiscvTLB +eventq_index=0 +size=64 + +[system.cpu.icache] +type=Cache +children=tags +addr_ranges=0:18446744073709551615:0:0:0:0 +assoc=2 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +data_latency=2 +default_p_state=UNDEFINED +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=true +max_miss_count=0 +mshrs=4 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=131072 +system=system +tag_latency=2 +tags=system.cpu.icache.tags +tgts_per_mshr=20 +write_buffers=8 +writeback_clean=true +cpu_side=system.cpu.icache_port +mem_side=system.cpu.toL2Bus.slave[0] + +[system.cpu.icache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +data_latency=2 +default_p_state=UNDEFINED +eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +sequential_access=false +size=131072 +tag_latency=2 + +[system.cpu.interrupts] +type=RiscvInterrupts +eventq_index=0 + +[system.cpu.isa] +type=RiscvISA +eventq_index=0 + +[system.cpu.itb] +type=RiscvTLB +eventq_index=0 +size=64 + +[system.cpu.l2cache] +type=Cache +children=tags +addr_ranges=0:18446744073709551615:0:0:0:0 +assoc=8 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +data_latency=20 +default_p_state=UNDEFINED +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=20 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +prefetch_on_access=false +prefetcher=Null +response_latency=20 +sequential_access=false +size=2097152 +system=system +tag_latency=20 +tags=system.cpu.l2cache.tags +tgts_per_mshr=12 +write_buffers=8 +writeback_clean=false +cpu_side=system.cpu.toL2Bus.master[0] +mem_side=system.membus.slave[1] + +[system.cpu.l2cache.tags] +type=LRU +assoc=8 +block_size=64 +clk_domain=system.cpu_clk_domain +data_latency=20 +default_p_state=UNDEFINED +eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +sequential_access=false +size=2097152 +tag_latency=20 + +[system.cpu.toL2Bus] +type=CoherentXBar +children=snoop_filter +clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED +eventq_index=0 +forward_latency=0 +frontend_latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +point_of_coherency=false +power_model=Null +response_latency=1 +snoop_filter=system.cpu.toL2Bus.snoop_filter +snoop_response_latency=1 +system=system +use_default_range=false +width=32 +master=system.cpu.l2cache.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side + +[system.cpu.toL2Bus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=0 +max_capacity=8388608 +system=system + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=LiveProcess +cmd=insttest +cwd= +drivers= +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable=/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64m/insttest +gid=100 +input=cin +kvmInSE=false +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=0 +system=system +uid=100 +useArchPT=false + +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000000 + +[system.membus] +type=CoherentXBar +children=snoop_filter +clk_domain=system.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +forward_latency=4 +frontend_latency=3 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +point_of_coherency=true +power_model=Null +response_latency=2 +snoop_filter=system.membus.snoop_filter +snoop_response_latency=4 +system=system +use_default_range=false +width=16 +master=system.physmem.port +slave=system.system_port system.cpu.l2cache.mem_side + +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + +[system.physmem] +type=SimpleMemory +bandwidth=73.000000 +clk_domain=system.clk_domain +conf_table_reported=true +default_p_state=UNDEFINED +eventq_index=0 +in_addr_map=true +kvm_map=true +latency=30000 +latency_var=0 +null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +range=0:134217727:0:0:0:0 +port=system.membus.master[0] + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/simple-timing/config.json b/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/simple-timing/config.json new file mode 100644 index 000000000..70b4bf86d --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/simple-timing/config.json @@ -0,0 +1,508 @@ +{ + "name": null, + "sim_quantum": 0, + "system": { + "kernel": "", + "mmap_using_noreserve": false, + "kernel_addr_check": true, + "membus": { + "point_of_coherency": true, + "system": "system", + "response_latency": 2, + "cxx_class": "CoherentXBar", + "forward_latency": 4, + "clk_domain": "system.clk_domain", + "width": 16, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "master": { + "peer": [ + "system.physmem.port" + ], + "role": "MASTER" + }, + "type": "CoherentXBar", + "frontend_latency": 3, + "slave": { + "peer": [ + "system.system_port", + "system.cpu.l2cache.mem_side" + ], + "role": "SLAVE" + }, + "p_state_clk_gate_min": 1000, + "snoop_filter": { + "name": "snoop_filter", + "system": "system", + "max_capacity": 8388608, + "eventq_index": 0, + "cxx_class": "SnoopFilter", + "path": "system.membus.snoop_filter", + "type": "SnoopFilter", + "lookup_latency": 1 + }, + "power_model": null, + "path": "system.membus", + "snoop_response_latency": 4, + "name": "membus", + "p_state_clk_gate_bins": 20, + "use_default_range": false + }, + "symbolfile": "", + "readfile": "", + "thermal_model": null, + "cxx_class": "System", + "work_begin_cpu_id_exit": -1, + "load_offset": 0, + "work_begin_exit_count": 0, + "p_state_clk_gate_min": 1000, + "memories": [ + "system.physmem" + ], + "work_begin_ckpt_count": 0, + "clk_domain": { + "name": "clk_domain", + "clock": [ + 1000 + ], + "init_perf_level": 0, + "voltage_domain": "system.voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "mem_ranges": [], + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "dvfs_handler": { + "enable": false, + "name": "dvfs_handler", + "sys_clk_domain": "system.clk_domain", + "transition_latency": 100000000, + "eventq_index": 0, + "cxx_class": "DVFSHandler", + "domains": [], + "path": "system.dvfs_handler", + "type": "DVFSHandler" + }, + "work_end_exit_count": 0, + "type": "System", + "voltage_domain": { + "name": "voltage_domain", + "eventq_index": 0, + "voltage": [ + "1.0" + ], + "cxx_class": "VoltageDomain", + "path": "system.voltage_domain", + "type": "VoltageDomain" + }, + "cache_line_size": 64, + "boot_osflags": "a", + "system_port": { + "peer": "system.membus.slave[0]", + "role": "MASTER" + }, + "physmem": { + "range": "0:134217727:0:0:0:0", + "latency": 30000, + "name": "physmem", + "p_state_clk_gate_min": 1000, + "eventq_index": 0, + "p_state_clk_gate_bins": 20, + "default_p_state": "UNDEFINED", + "kvm_map": true, + "clk_domain": "system.clk_domain", + "power_model": null, + "latency_var": 0, + "bandwidth": "73.000000", + "conf_table_reported": true, + "cxx_class": "SimpleMemory", + "p_state_clk_gate_max": 1000000000000, + "path": "system.physmem", + "null": false, + "type": "SimpleMemory", + "port": { + "peer": "system.membus.master[0]", + "role": "SLAVE" + }, + "in_addr_map": true + }, + "power_model": null, + "work_cpus_ckpt_count": 0, + "thermal_components": [], + "path": "system", + "cpu_clk_domain": { + "name": "cpu_clk_domain", + "clock": [ + 500 + ], + "init_perf_level": 0, + "voltage_domain": "system.voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.cpu_clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "work_end_ckpt_count": 0, + "mem_mode": "timing", + "name": "system", + "init_param": 0, + "p_state_clk_gate_bins": 20, + "load_addr_mask": 1099511627775, + "cpu": [ + { + "do_statistics_insts": true, + "numThreads": 1, + "itb": { + "name": "itb", + "eventq_index": 0, + "cxx_class": "RiscvISA::TLB", + "path": "system.cpu.itb", + "type": "RiscvTLB", + "size": 64 + }, + "system": "system", + "icache": { + "cpu_side": { + "peer": "system.cpu.icache_port", + "role": "SLAVE" + }, + "clusivity": "mostly_incl", + "prefetcher": null, + "system": "system", + "write_buffers": 8, + "response_latency": 2, + "cxx_class": "Cache", + "size": 131072, + "type": "Cache", + "clk_domain": "system.cpu_clk_domain", + "max_miss_count": 0, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "mem_side": { + "peer": "system.cpu.toL2Bus.slave[0]", + "role": "MASTER" + }, + "mshrs": 4, + "writeback_clean": true, + "p_state_clk_gate_min": 1000, + "tags": { + "size": 131072, + "tag_latency": 2, + "name": "tags", + "p_state_clk_gate_min": 1000, + "eventq_index": 0, + "p_state_clk_gate_bins": 20, + "default_p_state": "UNDEFINED", + "clk_domain": "system.cpu_clk_domain", + "power_model": null, + "sequential_access": false, + "assoc": 2, + "cxx_class": "LRU", + "p_state_clk_gate_max": 1000000000000, + "path": "system.cpu.icache.tags", + "block_size": 64, + "type": "LRU", + "data_latency": 2 + }, + "tgts_per_mshr": 20, + "demand_mshr_reserve": 1, + "power_model": null, + "addr_ranges": [ + "0:18446744073709551615:0:0:0:0" + ], + "is_read_only": true, + "prefetch_on_access": false, + "path": "system.cpu.icache", + "data_latency": 2, + "tag_latency": 2, + "name": "icache", + "p_state_clk_gate_bins": 20, + "sequential_access": false, + "assoc": 2 + }, + "function_trace": false, + "do_checkpoint_insts": true, + "cxx_class": "TimingSimpleCPU", + "max_loads_all_threads": 0, + "clk_domain": "system.cpu_clk_domain", + "function_trace_start": 0, + "cpu_id": 0, + "checker": null, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "toL2Bus": { + "point_of_coherency": false, + "system": "system", + "response_latency": 1, + "cxx_class": "CoherentXBar", + "forward_latency": 0, + "clk_domain": "system.cpu_clk_domain", + "width": 32, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "master": { + "peer": [ + "system.cpu.l2cache.cpu_side" + ], + "role": "MASTER" + }, + "type": "CoherentXBar", + "frontend_latency": 1, + "slave": { + "peer": [ + "system.cpu.icache.mem_side", + "system.cpu.dcache.mem_side" + ], + "role": "SLAVE" + }, + "p_state_clk_gate_min": 1000, + "snoop_filter": { + "name": "snoop_filter", + "system": "system", + "max_capacity": 8388608, + "eventq_index": 0, + "cxx_class": "SnoopFilter", + "path": "system.cpu.toL2Bus.snoop_filter", + "type": "SnoopFilter", + "lookup_latency": 0 + }, + "power_model": null, + "path": "system.cpu.toL2Bus", + "snoop_response_latency": 1, + "name": "toL2Bus", + "p_state_clk_gate_bins": 20, + "use_default_range": false + }, + "do_quiesce": true, + "type": "TimingSimpleCPU", + "profile": 0, + "icache_port": { + "peer": "system.cpu.icache.cpu_side", + "role": "MASTER" + }, + "p_state_clk_gate_bins": 20, + "p_state_clk_gate_min": 1000, + "interrupts": [ + { + "eventq_index": 0, + "path": "system.cpu.interrupts", + "type": "RiscvInterrupts", + "name": "interrupts", + "cxx_class": "RiscvISA::Interrupts" + } + ], + "dcache_port": { + "peer": "system.cpu.dcache.cpu_side", + "role": "MASTER" + }, + "socket_id": 0, + "power_model": null, + "max_insts_all_threads": 0, + "l2cache": { + "cpu_side": { + "peer": "system.cpu.toL2Bus.master[0]", + "role": "SLAVE" + }, + "clusivity": "mostly_incl", + "prefetcher": null, + "system": "system", + "write_buffers": 8, + "response_latency": 20, + "cxx_class": "Cache", + "size": 2097152, + "type": "Cache", + "clk_domain": "system.cpu_clk_domain", + "max_miss_count": 0, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "mem_side": { + "peer": "system.membus.slave[1]", + "role": "MASTER" + }, + "mshrs": 20, + "writeback_clean": false, + "p_state_clk_gate_min": 1000, + "tags": { + "size": 2097152, + "tag_latency": 20, + "name": "tags", + "p_state_clk_gate_min": 1000, + "eventq_index": 0, + "p_state_clk_gate_bins": 20, + "default_p_state": "UNDEFINED", + "clk_domain": "system.cpu_clk_domain", + "power_model": null, + "sequential_access": false, + "assoc": 8, + "cxx_class": "LRU", + "p_state_clk_gate_max": 1000000000000, + "path": "system.cpu.l2cache.tags", + "block_size": 64, + "type": "LRU", + "data_latency": 20 + }, + "tgts_per_mshr": 12, + "demand_mshr_reserve": 1, + "power_model": null, + "addr_ranges": [ + "0:18446744073709551615:0:0:0:0" + ], + "is_read_only": false, + "prefetch_on_access": false, + "path": "system.cpu.l2cache", + "data_latency": 20, + "tag_latency": 20, + "name": "l2cache", + "p_state_clk_gate_bins": 20, + "sequential_access": false, + "assoc": 8 + }, + "path": "system.cpu", + "max_loads_any_thread": 0, + "switched_out": false, + "workload": [ + { + "uid": 100, + "pid": 100, + "kvmInSE": false, + "cxx_class": "LiveProcess", + "executable": "/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64m/insttest", + "drivers": [], + "system": "system", + "gid": 100, + "eventq_index": 0, + "env": [], + "input": "cin", + "ppid": 99, + "type": "LiveProcess", + "cwd": "", + "simpoint": 0, + "euid": 100, + "path": "system.cpu.workload", + "max_stack_size": 67108864, + "name": "workload", + "cmd": [ + "insttest" + ], + "errout": "cerr", + "useArchPT": false, + "egid": 100, + "output": "cout" + } + ], + "name": "cpu", + "dtb": { + "name": "dtb", + "eventq_index": 0, + "cxx_class": "RiscvISA::TLB", + "path": "system.cpu.dtb", + "type": "RiscvTLB", + "size": 64 + }, + "simpoint_start_insts": [], + "max_insts_any_thread": 0, + "progress_interval": 0, + "branchPred": null, + "dcache": { + "cpu_side": { + "peer": "system.cpu.dcache_port", + "role": "SLAVE" + }, + "clusivity": "mostly_incl", + "prefetcher": null, + "system": "system", + "write_buffers": 8, + "response_latency": 2, + "cxx_class": "Cache", + "size": 262144, + "type": "Cache", + "clk_domain": "system.cpu_clk_domain", + "max_miss_count": 0, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "mem_side": { + "peer": "system.cpu.toL2Bus.slave[1]", + "role": "MASTER" + }, + "mshrs": 4, + "writeback_clean": false, + "p_state_clk_gate_min": 1000, + "tags": { + "size": 262144, + "tag_latency": 2, + "name": "tags", + "p_state_clk_gate_min": 1000, + "eventq_index": 0, + "p_state_clk_gate_bins": 20, + "default_p_state": "UNDEFINED", + "clk_domain": "system.cpu_clk_domain", + "power_model": null, + "sequential_access": false, + "assoc": 2, + "cxx_class": "LRU", + "p_state_clk_gate_max": 1000000000000, + "path": "system.cpu.dcache.tags", + "block_size": 64, + "type": "LRU", + "data_latency": 2 + }, + "tgts_per_mshr": 20, + "demand_mshr_reserve": 1, + "power_model": null, + "addr_ranges": [ + "0:18446744073709551615:0:0:0:0" + ], + "is_read_only": false, + "prefetch_on_access": false, + "path": "system.cpu.dcache", + "data_latency": 2, + "tag_latency": 2, + "name": "dcache", + "p_state_clk_gate_bins": 20, + "sequential_access": false, + "assoc": 2 + }, + "isa": [ + { + "eventq_index": 0, + "path": "system.cpu.isa", + "type": "RiscvISA", + "name": "isa", + "cxx_class": "RiscvISA::ISA" + } + ], + "tracer": { + "eventq_index": 0, + "path": "system.cpu.tracer", + "type": "ExeTracer", + "name": "tracer", + "cxx_class": "Trace::ExeTracer" + } + } + ], + "multi_thread": false, + "exit_on_work_items": false, + "work_item_id": -1, + "num_work_ids": 16 + }, + "time_sync_period": 100000000000, + "eventq_index": 0, + "time_sync_spin_threshold": 100000000, + "cxx_class": "Root", + "path": "root", + "time_sync_enable": false, + "type": "Root", + "full_system": false +}
\ No newline at end of file diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/simple-timing/simerr b/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/simple-timing/simerr new file mode 100755 index 000000000..fd133b12b --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/simple-timing/simerr @@ -0,0 +1,3 @@ +warn: Unknown operating system; assuming Linux. +warn: Sockets disabled, not accepting gdb connections +warn: ClockedObject: More than one power state change request encountered within the same simulation tick diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/simple-timing/simout b/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/simple-timing/simout new file mode 100755 index 000000000..7cb72814c --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/simple-timing/simout @@ -0,0 +1,51 @@ +Redirecting stdout to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64m/simple-timing/simout +Redirecting stderr to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64m/simple-timing/simerr +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled Nov 30 2016 14:33:35 +gem5 started Nov 30 2016 16:18:50 +gem5 executing on zizzer, pid 34099 +command line: /z/powerjg/gem5-upstream/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64m/simple-timing -re /z/powerjg/gem5-upstream/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64m/simple-timing + +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. +mul: PASS +mul, overflow: PASS +mulh: PASS +mulh, negative: PASS +mulh, all bits set: PASS +mulhsu, all bits set: PASS +mulhsu: PASS +mulhu: PASS +mulhu, all bits set: PASS +div: PASS +div/0: PASS +div, overflow: PASS +divu: PASS +divu/0: PASS +divu, "overflow": PASS +rem: PASS +rem/0: PASS +rem, overflow: PASS +remu: PASS +remu/0: PASS +remu, "overflow": PASS +mulw, truncate: PASS +mulw, overflow: PASS +divw, truncate: PASS +divw/0: PASS +divw, overflow: PASS +divuw, truncate: PASS +divuw/0: PASS +divuw, "overflow": PASS +divuw, sign extend: PASS +remw, truncate: PASS +remw/0: PASS +remw, overflow: PASS +remuw, truncate: PASS +remuw/0: PASS +remuw, "overflow": PASS +remuw, sign extend: PASS +Exiting @ tick 209715500 because target called exit() diff --git a/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/simple-timing/stats.txt b/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/simple-timing/stats.txt new file mode 100644 index 000000000..a860f5326 --- /dev/null +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/simple-timing/stats.txt @@ -0,0 +1,515 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.000210 # Number of seconds simulated +sim_ticks 209715500 # Number of ticks simulated +final_tick 209715500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 42175 # Simulator instruction rate (inst/s) +host_op_rate 42174 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 78069260 # Simulator tick rate (ticks/s) +host_mem_usage 242960 # Number of bytes of host memory used +host_seconds 2.69 # Real time elapsed on the host +sim_insts 113291 # Number of instructions simulated +sim_ops 113291 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 209715500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 37952 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 16640 # Number of bytes read from this memory +system.physmem.bytes_read::total 54592 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 37952 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 37952 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 593 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 260 # Number of read requests responded to by this memory +system.physmem.num_reads::total 853 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 180968979 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 79345590 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 260314569 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 180968979 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 180968979 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 180968979 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 79345590 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 260314569 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 209715500 # Cumulative time (in ticks) in various power states +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 45 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 209715500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 419431 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 113291 # Number of instructions committed +system.cpu.committedOps 113291 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 113292 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses +system.cpu.num_func_calls 8529 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 17391 # number of instructions that are conditional controls +system.cpu.num_int_insts 113292 # number of integer instructions +system.cpu.num_fp_insts 0 # number of float instructions +system.cpu.num_int_register_reads 151096 # number of times the integer registers were read +system.cpu.num_int_register_writes 76188 # number of times the integer registers were written +system.cpu.num_fp_register_reads 0 # number of times the floating registers were read +system.cpu.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu.num_mem_refs 43493 # number of memory refs +system.cpu.num_load_insts 23780 # Number of load instructions +system.cpu.num_store_insts 19713 # Number of store instructions +system.cpu.num_idle_cycles 0 # Number of idle cycles +system.cpu.num_busy_cycles 419431 # Number of busy cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.Branches 25920 # Number of branches fetched +system.cpu.op_class::No_OpClass 45 0.04% 0.04% # Class of executed instruction +system.cpu.op_class::IntAlu 69651 61.45% 61.49% # Class of executed instruction +system.cpu.op_class::IntMult 122 0.11% 61.60% # Class of executed instruction +system.cpu.op_class::IntDiv 26 0.02% 61.63% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 61.63% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 61.63% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 61.63% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 61.63% # Class of executed instruction +system.cpu.op_class::FloatMultAcc 0 0.00% 61.63% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 61.63% # Class of executed instruction +system.cpu.op_class::FloatMisc 0 0.00% 61.63% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 61.63% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 61.63% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 61.63% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 61.63% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 61.63% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 61.63% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 61.63% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 61.63% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 61.63% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 61.63% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 61.63% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 61.63% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 61.63% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 61.63% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 61.63% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 61.63% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 61.63% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 61.63% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 61.63% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 61.63% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 61.63% # Class of executed instruction +system.cpu.op_class::MemRead 23780 20.98% 82.61% # Class of executed instruction +system.cpu.op_class::MemWrite 19713 17.39% 100.00% # Class of executed instruction +system.cpu.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 113337 # Class of executed instruction +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 209715500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 0 # number of replacements +system.cpu.dcache.tags.tagsinuse 215.473039 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 43232 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 260 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 166.276923 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 215.473039 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.052606 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.052606 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 260 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 4 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 33 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 223 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.063477 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 87244 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 87244 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 209715500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 23719 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 23719 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 19513 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 19513 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 43232 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 43232 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 43232 # number of overall hits +system.cpu.dcache.overall_hits::total 43232 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 61 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 61 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 199 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 199 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 260 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 260 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 260 # number of overall misses +system.cpu.dcache.overall_misses::total 260 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 3843000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 3843000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 12537000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 12537000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 16380000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 16380000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 16380000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 16380000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 23780 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 23780 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 19712 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 19712 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 43492 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 43492 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 43492 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 43492 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002565 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.002565 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.010095 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.010095 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.005978 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.005978 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.005978 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.005978 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63000 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 63000 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 63000 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 63000 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 63000 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 63000 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 63000 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 61 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 61 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 199 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 199 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 260 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 260 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 260 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 260 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3782000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 3782000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12338000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 12338000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16120000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 16120000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 16120000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 16120000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002565 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002565 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010095 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010095 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005978 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.005978 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005978 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.005978 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 62000 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 62000 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 62000 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 62000 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 62000 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 62000 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 62000 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 62000 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 209715500 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 6 # number of replacements +system.cpu.icache.tags.tagsinuse 302.746737 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 112745 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 593 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 190.126476 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 302.746737 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.147826 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.147826 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 587 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 35 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 229 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 323 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.286621 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 227269 # Number of tag accesses +system.cpu.icache.tags.data_accesses 227269 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 209715500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 112745 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 112745 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 112745 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 112745 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 112745 # number of overall hits +system.cpu.icache.overall_hits::total 112745 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 593 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 593 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 593 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 593 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 593 # number of overall misses +system.cpu.icache.overall_misses::total 593 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 37359500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 37359500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 37359500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 37359500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 37359500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 37359500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 113338 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 113338 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 113338 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 113338 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 113338 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 113338 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.005232 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.005232 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.005232 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.005232 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.005232 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.005232 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 63000.843170 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 63000.843170 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 63000.843170 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 63000.843170 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 63000.843170 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 63000.843170 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.icache.writebacks::writebacks 6 # number of writebacks +system.cpu.icache.writebacks::total 6 # number of writebacks +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 593 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 593 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 593 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 593 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 593 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 593 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 36766500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 36766500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 36766500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 36766500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 36766500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 36766500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.005232 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.005232 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.005232 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.005232 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.005232 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.005232 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 62000.843170 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 62000.843170 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 62000.843170 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 62000.843170 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 62000.843170 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 62000.843170 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 209715500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.replacements 0 # number of replacements +system.cpu.l2cache.tags.tagsinuse 520.331439 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 6 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 853 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.007034 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::cpu.inst 304.845382 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 215.486056 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.009303 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.006576 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.015879 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 853 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 39 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 262 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 552 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.026031 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 7725 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 7725 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 209715500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.WritebackClean_hits::writebacks 6 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 6 # number of WritebackClean hits +system.cpu.l2cache.ReadExReq_misses::cpu.data 199 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 199 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 593 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 593 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 61 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 61 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.inst 593 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 260 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 853 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 593 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 260 # number of overall misses +system.cpu.l2cache.overall_misses::total 853 # number of overall misses +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 12039500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 12039500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 35877000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 35877000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 3690500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 3690500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 35877000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 15730000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 51607000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 35877000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 15730000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 51607000 # number of overall miss cycles +system.cpu.l2cache.WritebackClean_accesses::writebacks 6 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 6 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 199 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 199 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 593 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 593 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 61 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 61 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 593 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 260 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 853 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 593 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 260 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 853 # number of overall (read+write) accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 1 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 1 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 1 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 1 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60500 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60500 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60500.843170 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60500.843170 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60500 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60500 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60500.843170 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60500 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 60500.586166 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60500.843170 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60500 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 60500.586166 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 199 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 199 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 593 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 593 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 61 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 61 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 593 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 260 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 853 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 593 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 260 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 853 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 10049500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 10049500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 29947000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 29947000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 3080500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 3080500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 29947000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 13130000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 43077000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 29947000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 13130000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 43077000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 1 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50500.843170 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50500.843170 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50500.843170 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50500.586166 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50500.843170 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50500.586166 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 859 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 6 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 209715500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 654 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 6 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 199 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 199 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 593 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 61 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1192 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 520 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 1712 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 38336 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 16640 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 54976 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 853 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 853 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 853 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 435500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 889500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.4 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 390000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) +system.membus.snoop_filter.tot_requests 853 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 209715500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 654 # Transaction distribution +system.membus.trans_dist::ReadExReq 199 # Transaction distribution +system.membus.trans_dist::ReadExResp 199 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 654 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1706 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1706 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 54592 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 54592 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoopTraffic 0 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 853 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 853 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 853 # Request fanout histogram +system.membus.reqLayer0.occupancy 853500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.4 # Layer utilization (%) +system.membus.respLayer1.occupancy 4265000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 2.0 # Layer utilization (%) + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/config.ini b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/config.ini index c4ebeae2c..7685aa1bd 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/config.ini +++ b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/config.ini @@ -177,10 +177,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=false max_miss_count=0 mshrs=4 @@ -194,6 +194,7 @@ response_latency=2 sequential_access=false size=262144 system=system +tag_latency=2 tags=system.cpu.dcache.tags tgts_per_mshr=20 write_buffers=8 @@ -206,15 +207,16 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=262144 +tag_latency=2 [system.cpu.dtb] type=SparcTLB @@ -292,10 +294,10 @@ pipelined=true [system.cpu.fuPool.FUList3] type=FUDesc -children=opList0 opList1 opList2 +children=opList0 opList1 opList2 opList3 opList4 count=2 eventq_index=0 -opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 +opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 system.cpu.fuPool.FUList3.opList3 system.cpu.fuPool.FUList3.opList4 [system.cpu.fuPool.FUList3.opList0] type=OpDesc @@ -307,11 +309,25 @@ pipelined=true [system.cpu.fuPool.FUList3.opList1] type=OpDesc eventq_index=0 +opClass=FloatMultAcc +opLat=5 +pipelined=true + +[system.cpu.fuPool.FUList3.opList2] +type=OpDesc +eventq_index=0 +opClass=FloatMisc +opLat=3 +pipelined=true + +[system.cpu.fuPool.FUList3.opList3] +type=OpDesc +eventq_index=0 opClass=FloatDiv opLat=12 pipelined=false -[system.cpu.fuPool.FUList3.opList2] +[system.cpu.fuPool.FUList3.opList4] type=OpDesc eventq_index=0 opClass=FloatSqrt @@ -320,18 +336,25 @@ pipelined=false [system.cpu.fuPool.FUList4] type=FUDesc -children=opList +children=opList0 opList1 count=0 eventq_index=0 -opList=system.cpu.fuPool.FUList4.opList +opList=system.cpu.fuPool.FUList4.opList0 system.cpu.fuPool.FUList4.opList1 -[system.cpu.fuPool.FUList4.opList] +[system.cpu.fuPool.FUList4.opList0] type=OpDesc eventq_index=0 opClass=MemRead opLat=1 pipelined=true +[system.cpu.fuPool.FUList4.opList1] +type=OpDesc +eventq_index=0 +opClass=FloatMemRead +opLat=1 +pipelined=true + [system.cpu.fuPool.FUList5] type=FUDesc children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 @@ -481,24 +504,31 @@ pipelined=true [system.cpu.fuPool.FUList6] type=FUDesc -children=opList +children=opList0 opList1 count=0 eventq_index=0 -opList=system.cpu.fuPool.FUList6.opList +opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1 -[system.cpu.fuPool.FUList6.opList] +[system.cpu.fuPool.FUList6.opList0] type=OpDesc eventq_index=0 opClass=MemWrite opLat=1 pipelined=true +[system.cpu.fuPool.FUList6.opList1] +type=OpDesc +eventq_index=0 +opClass=FloatMemWrite +opLat=1 +pipelined=true + [system.cpu.fuPool.FUList7] type=FUDesc -children=opList0 opList1 +children=opList0 opList1 opList2 opList3 count=4 eventq_index=0 -opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 +opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 system.cpu.fuPool.FUList7.opList2 system.cpu.fuPool.FUList7.opList3 [system.cpu.fuPool.FUList7.opList0] type=OpDesc @@ -514,6 +544,20 @@ opClass=MemWrite opLat=1 pipelined=true +[system.cpu.fuPool.FUList7.opList2] +type=OpDesc +eventq_index=0 +opClass=FloatMemRead +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList7.opList3] +type=OpDesc +eventq_index=0 +opClass=FloatMemWrite +opLat=1 +pipelined=true + [system.cpu.fuPool.FUList8] type=FUDesc children=opList @@ -535,10 +579,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=true max_miss_count=0 mshrs=4 @@ -552,6 +596,7 @@ response_latency=2 sequential_access=false size=131072 system=system +tag_latency=2 tags=system.cpu.icache.tags tgts_per_mshr=20 write_buffers=8 @@ -564,15 +609,16 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=131072 +tag_latency=2 [system.cpu.interrupts] type=SparcInterrupts @@ -594,10 +640,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0 assoc=8 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=20 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=20 is_read_only=false max_miss_count=0 mshrs=20 @@ -611,6 +657,7 @@ response_latency=20 sequential_access=false size=2097152 system=system +tag_latency=20 tags=system.cpu.l2cache.tags tgts_per_mshr=12 write_buffers=8 @@ -623,15 +670,16 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=20 default_p_state=UNDEFINED eventq_index=0 -hit_latency=20 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=2097152 +tag_latency=20 [system.cpu.toL2Bus] type=CoherentXBar @@ -676,7 +724,7 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/test-progs/insttest/bin/sparc/linux/insttest +executable=/dist/m5/regression/test-progs/insttest/bin/sparc/linux/insttest gid=100 input=cin kvmInSE=false diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simout b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simout index e1ebd0d0b..7b48b6ce0 100755 --- a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simout +++ b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simout @@ -3,10 +3,10 @@ Redirecting stderr to build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/o3- gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Oct 13 2016 20:43:27 -gem5 started Oct 13 2016 20:45:42 -gem5 executing on e108600-lin, pid 17390 -command line: /work/curdun01/gem5-external.hg/build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/o3-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/02.insttest/sparc/linux/o3-timing +gem5 compiled Nov 29 2016 18:44:12 +gem5 started Nov 29 2016 18:44:33 +gem5 executing on zizzer, pid 58827 +command line: /z/powerjg/gem5-upstream/build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/o3-timing -re /z/powerjg/gem5-upstream/tests/testing/../run.py quick/se/02.insttest/sparc/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt index c02cfcc5d..4050dbfe4 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt +++ b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000030 # Nu sim_ticks 29908500 # Number of ticks simulated final_tick 29908500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 90593 # Simulator instruction rate (inst/s) -host_op_rate 90586 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 187662601 # Simulator tick rate (ticks/s) -host_mem_usage 251772 # Number of bytes of host memory used -host_seconds 0.16 # Real time elapsed on the host +host_inst_rate 19226 # Simulator instruction rate (inst/s) +host_op_rate 19225 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 39829510 # Simulator tick rate (ticks/s) +host_mem_usage 234412 # Number of bytes of host memory used +host_seconds 0.75 # Real time elapsed on the host sim_insts 14436 # Number of instructions simulated sim_ops 14436 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -201,12 +201,12 @@ system.physmem.bytesPerActivate::768-895 6 7.69% 83.33% # By system.physmem.bytesPerActivate::896-1023 1 1.28% 84.62% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 12 15.38% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 78 # Bytes accessed per row activation -system.physmem.totQLat 6721500 # Total ticks spent queuing -system.physmem.totMemAccLat 16340250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 6719500 # Total ticks spent queuing +system.physmem.totMemAccLat 16338250 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 2565000 # Total ticks spent in databus transfers -system.physmem.avgQLat 13102.34 # Average queueing delay per DRAM burst +system.physmem.avgQLat 13098.44 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 31852.34 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 31848.44 # Average memory access latency per DRAM burst system.physmem.avgRdBW 1097.75 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 1097.75 # Average system read bandwidth in MiByte/s @@ -228,9 +228,9 @@ system.physmem_0.preEnergy 174570 # En system.physmem_0.readEnergy 2199120 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 1843920.000000 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 3642300 # Energy for active background per rank (pJ) +system.physmem_0.actBackEnergy 3644010 # Energy for active background per rank (pJ) system.physmem_0.preBackEnergy 63360 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 9900900 # Energy for active power-down per rank (pJ) +system.physmem_0.actPowerDownEnergy 9899190 # Energy for active power-down per rank (pJ) system.physmem_0.prePowerDownEnergy 16800 # Energy for precharge power-down per rank (pJ) system.physmem_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) system.physmem_0.totalEnergy 18197970 # Total energy per rank (pJ) @@ -247,9 +247,9 @@ system.physmem_1.preEnergy 121440 # En system.physmem_1.readEnergy 1463700 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 1843920.000000 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 2522250 # Energy for active background per rank (pJ) +system.physmem_1.actBackEnergy 2521680 # Energy for active background per rank (pJ) system.physmem_1.preBackEnergy 86880 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 10426440 # Energy for active power-down per rank (pJ) +system.physmem_1.actPowerDownEnergy 10427010 # Energy for active power-down per rank (pJ) system.physmem_1.prePowerDownEnergy 493920 # Energy for precharge power-down per rank (pJ) system.physmem_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) system.physmem_1.totalEnergy 17237010 # Total energy per rank (pJ) @@ -340,20 +340,20 @@ system.cpu.memDep0.conflictingLoads 12 # Nu system.cpu.memDep0.conflictingStores 8 # Number of conflicting stores. system.cpu.iq.iqInstsAdded 28450 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 744 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 25032 # Number of instructions issued +system.cpu.iq.iqInstsIssued 25030 # Number of instructions issued system.cpu.iq.iqSquashedInstsIssued 132 # Number of squashed instructions issued system.cpu.iq.iqSquashedInstsExamined 14758 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 10993 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedOperandsExamined 11000 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 269 # Number of squashed non-spec instructions that were removed system.cpu.iq.issued_per_cycle::samples 35692 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.701334 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.501806 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.701278 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.501683 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 26613 74.56% 74.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 3169 8.88% 83.44% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 1586 4.44% 87.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 26611 74.56% 74.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 3173 8.89% 83.45% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 1585 4.44% 87.89% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::3 1525 4.27% 92.16% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 1197 3.35% 95.51% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 1196 3.35% 95.51% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::5 748 2.10% 97.61% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 484 1.36% 98.96% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 276 0.77% 99.74% # Number of insts issued each cycle @@ -401,7 +401,7 @@ system.cpu.iq.fu_full::FloatMemWrite 0 0.00% 100.00% # at system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 18346 73.29% 73.29% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 18344 73.29% 73.29% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 0 0.00% 73.29% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 73.29% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 73.29% # Type of FU issued @@ -438,17 +438,17 @@ system.cpu.iq.FU_type_0::FloatMemRead 0 0.00% 100.00% # Ty system.cpu.iq.FU_type_0::FloatMemWrite 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 25032 # Type of FU issued -system.cpu.iq.rate 0.418469 # Inst issue rate +system.cpu.iq.FU_type_0::total 25030 # Type of FU issued +system.cpu.iq.rate 0.418436 # Inst issue rate system.cpu.iq.fu_busy_cnt 309 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.012344 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 86197 # Number of integer instruction queue reads +system.cpu.iq.fu_busy_rate 0.012345 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 86193 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_writes 43979 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 22374 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_wakeup_accesses 22369 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 25341 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 25339 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 32 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address @@ -473,23 +473,23 @@ system.cpu.iew.iewIQFullEvents 7 # Nu system.cpu.iew.iewLSQFullEvents 4 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 28 # Number of memory order violations system.cpu.iew.predictedTakenIncorrect 207 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 1575 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1782 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 23436 # Number of executed instructions +system.cpu.iew.predictedNotTakenIncorrect 1574 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1781 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 23432 # Number of executed instructions system.cpu.iew.iewExecLoadInsts 3882 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1596 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecSquashedInsts 1598 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 1532 # number of nop insts executed -system.cpu.iew.exec_refs 6191 # number of memory reference insts executed -system.cpu.iew.exec_branches 4986 # Number of branches executed -system.cpu.iew.exec_stores 2309 # Number of stores executed -system.cpu.iew.exec_rate 0.391788 # Inst execution rate -system.cpu.iew.wb_sent 22845 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 22374 # cumulative count of insts written-back -system.cpu.iew.wb_producers 10411 # num instructions producing a value -system.cpu.iew.wb_consumers 13650 # num instructions consuming a value -system.cpu.iew.wb_rate 0.374035 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.762711 # average fanout of values written-back +system.cpu.iew.exec_refs 6190 # number of memory reference insts executed +system.cpu.iew.exec_branches 4984 # Number of branches executed +system.cpu.iew.exec_stores 2308 # Number of stores executed +system.cpu.iew.exec_rate 0.391722 # Inst execution rate +system.cpu.iew.wb_sent 22840 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 22369 # cumulative count of insts written-back +system.cpu.iew.wb_producers 10409 # num instructions producing a value +system.cpu.iew.wb_consumers 13648 # num instructions consuming a value +system.cpu.iew.wb_rate 0.373951 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.762676 # average fanout of values written-back system.cpu.commit.commitSquashedInsts 15475 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 475 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 1435 # The number of times a branch was mispredicted @@ -570,20 +570,20 @@ system.cpu.cpi 4.143669 # CP system.cpu.cpi_total 4.143669 # CPI: Total CPI of All Threads system.cpu.ipc 0.241332 # IPC: Instructions Per Cycle system.cpu.ipc_total 0.241332 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 36480 # number of integer regfile reads -system.cpu.int_regfile_writes 20296 # number of integer regfile writes -system.cpu.misc_regfile_reads 8094 # number of misc regfile reads +system.cpu.int_regfile_reads 36473 # number of integer regfile reads +system.cpu.int_regfile_writes 20293 # number of integer regfile writes +system.cpu.misc_regfile_reads 8093 # number of misc regfile reads system.cpu.misc_regfile_writes 569 # number of misc regfile writes system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 29908500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 99.158435 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 99.156027 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 4579 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 146 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 31.363014 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 99.158435 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.024209 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.024209 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 99.156027 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.024208 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.024208 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 146 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 21 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 125 # Occupied blocks per task id @@ -691,14 +691,14 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 87608.108108 system.cpu.dcache.overall_avg_mshr_miss_latency::total 87608.108108 # average overall mshr miss latency system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 29908500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 204.747820 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 204.744610 # Cycle average of tags in use system.cpu.icache.tags.total_refs 6856 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 367 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 18.681199 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 204.747820 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.099975 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.099975 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 204.744610 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.099973 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.099973 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 367 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 92 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 275 # Occupied blocks per task id @@ -718,12 +718,12 @@ system.cpu.icache.demand_misses::cpu.inst 590 # n system.cpu.icache.demand_misses::total 590 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 590 # number of overall misses system.cpu.icache.overall_misses::total 590 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 45891500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 45891500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 45891500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 45891500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 45891500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 45891500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 45890500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 45890500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 45890500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 45890500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 45890500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 45890500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 7446 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 7446 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 7446 # number of demand (read+write) accesses @@ -736,12 +736,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.079237 system.cpu.icache.demand_miss_rate::total 0.079237 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.079237 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.079237 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 77782.203390 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 77782.203390 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 77782.203390 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 77782.203390 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 77782.203390 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 77782.203390 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 77780.508475 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 77780.508475 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 77780.508475 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 77780.508475 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 77780.508475 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 77780.508475 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 123 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked @@ -760,33 +760,33 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 367 system.cpu.icache.demand_mshr_misses::total 367 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 367 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 367 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 30257500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 30257500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 30257500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 30257500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 30257500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 30257500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 30255500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 30255500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 30255500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 30255500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 30255500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 30255500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.049288 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.049288 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.049288 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.049288 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.049288 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.049288 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 82445.504087 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 82445.504087 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 82445.504087 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 82445.504087 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 82445.504087 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 82445.504087 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 82440.054496 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 82440.054496 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 82440.054496 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 82440.054496 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 82440.054496 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 82440.054496 # average overall mshr miss latency system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 29908500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 303.316506 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 303.310888 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 511 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.003914 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 204.106814 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 99.209691 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 204.103605 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 99.207284 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::cpu.inst 0.006229 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.003028 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.009256 # Average percentage of cache occupancy @@ -817,16 +817,16 @@ system.cpu.l2cache.overall_misses::cpu.data 148 # system.cpu.l2cache.overall_misses::total 513 # number of overall misses system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6762500 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 6762500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 29684000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 29684000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 29682000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 29682000 # number of ReadCleanReq miss cycles system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 5983000 # number of ReadSharedReq miss cycles system.cpu.l2cache.ReadSharedReq_miss_latency::total 5983000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 29684000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 29682000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.data 12745500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 42429500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 29684000 # number of overall miss cycles +system.cpu.l2cache.demand_miss_latency::total 42427500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 29682000 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.data 12745500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 42429500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 42427500 # number of overall miss cycles system.cpu.l2cache.ReadExReq_accesses::cpu.data 83 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 83 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 367 # number of ReadCleanReq accesses(hits+misses) @@ -853,16 +853,16 @@ system.cpu.l2cache.overall_miss_rate::cpu.data 1 system.cpu.l2cache.overall_miss_rate::total 0.996117 # miss rate for overall accesses system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 81475.903614 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 81475.903614 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 81326.027397 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 81326.027397 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 81320.547945 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 81320.547945 # average ReadCleanReq miss latency system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 92046.153846 # average ReadSharedReq miss latency system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 92046.153846 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 81326.027397 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 81320.547945 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 86118.243243 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 82708.576998 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 81326.027397 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 82704.678363 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 81320.547945 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 86118.243243 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 82708.576998 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 82704.678363 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -883,16 +883,16 @@ system.cpu.l2cache.overall_mshr_misses::cpu.data 148 system.cpu.l2cache.overall_mshr_misses::total 513 # number of overall MSHR misses system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5932500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5932500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 26034000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 26034000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 26032000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 26032000 # number of ReadCleanReq MSHR miss cycles system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 5353000 # number of ReadSharedReq MSHR miss cycles system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 5353000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 26034000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 26032000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11285500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 37319500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 26034000 # number of overall MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 37317500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 26032000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11285500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 37319500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 37317500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.994550 # mshr miss rate for ReadCleanReq accesses @@ -907,16 +907,16 @@ system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 system.cpu.l2cache.overall_mshr_miss_rate::total 0.996117 # mshr miss rate for overall accesses system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71475.903614 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71475.903614 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 71326.027397 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 71326.027397 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 71320.547945 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 71320.547945 # average ReadCleanReq mshr miss latency system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 82353.846154 # average ReadSharedReq mshr miss latency system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 82353.846154 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 71326.027397 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 71320.547945 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 76253.378378 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72747.563353 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 71326.027397 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72743.664717 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 71320.547945 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 76253.378378 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72747.563353 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72743.664717 # average overall mshr miss latency system.cpu.toL2Bus.snoop_filter.tot_requests 515 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 2 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. diff --git a/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU_RfO/config.ini b/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU_RfO/config.ini index bd0cc03e4..28bcdeb18 100644 --- a/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU_RfO/config.ini +++ b/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU_RfO/config.ini @@ -420,7 +420,7 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/test-progs/gpu-hello/bin/x86/linux/gpu-hello +executable=/dist/m5/regression/test-progs/gpu-hello/bin/x86/linux/gpu-hello gid=100 input=cin kvmInSE=false @@ -476,6 +476,7 @@ n_wf=8 num_SIMDs=4 num_global_mem_pipes=1 num_shared_mem_pipes=1 +out_of_order_data_delivery=false p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 @@ -808,6 +809,7 @@ n_wf=8 num_SIMDs=4 num_global_mem_pipes=1 num_shared_mem_pipes=1 +out_of_order_data_delivery=false p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 @@ -1152,7 +1154,7 @@ translation_port=system.dispatcher_coalescer.slave[0] [system.cpu2.cl_driver] type=ClDriver -codefile=/arm/projectscratch/randd/systems/dist/test-progs/gpu-hello/bin/x86/linux/gpu-hello-kernel.asm +codefile=/dist/m5/regression/test-progs/gpu-hello/bin/x86/linux/gpu-hello-kernel.asm eventq_index=0 filename=hsa diff --git a/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU_RfO/simout b/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU_RfO/simout index c30fce800..6eab10f97 100755 --- a/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU_RfO/simout +++ b/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU_RfO/simout @@ -3,12 +3,12 @@ Redirecting stderr to build/HSAIL_X86/tests/opt/quick/se/04.gpu/x86/linux/gpu-ru gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Oct 13 2016 21:24:38 -gem5 started Oct 13 2016 21:24:54 -gem5 executing on e108600-lin, pid 29892 -command line: /work/curdun01/gem5-external.hg/build/HSAIL_X86/gem5.opt -d build/HSAIL_X86/tests/opt/quick/se/04.gpu/x86/linux/gpu-ruby-GPU_RfO -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/04.gpu/x86/linux/gpu-ruby-GPU_RfO +gem5 compiled Nov 29 2016 19:21:01 +gem5 started Nov 29 2016 19:21:23 +gem5 executing on zizzer, pid 11568 +command line: /z/powerjg/gem5-upstream/build/HSAIL_X86/gem5.opt -d build/HSAIL_X86/tests/opt/quick/se/04.gpu/x86/linux/gpu-ruby-GPU_RfO -re /z/powerjg/gem5-upstream/tests/testing/../run.py quick/se/04.gpu/x86/linux/gpu-ruby-GPU_RfO -Using GPU kernel code file(s) /arm/projectscratch/randd/systems/dist/test-progs/gpu-hello/bin/x86/linux/gpu-hello-kernel.asm +Using GPU kernel code file(s) /dist/m5/regression/test-progs/gpu-hello/bin/x86/linux/gpu-hello-kernel.asm Global frequency set at 1000000000000 ticks per second Forcing maxCoalescedReqs to 32 (TLB assoc.) Forcing maxCoalescedReqs to 32 (TLB assoc.) @@ -20,4 +20,4 @@ info: Entering event queue @ 0. Starting simulation... keys = 0x7b2bc0, &keys = 0x798998, keys[0] = 23 the gpu says: elloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloe -Exiting @ tick 668137500 because target called exit() +Exiting @ tick 667407500 because target called exit() diff --git a/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU_RfO/stats.txt b/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU_RfO/stats.txt index 738fdd2f1..a879bebf2 100644 --- a/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU_RfO/stats.txt +++ b/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU_RfO/stats.txt @@ -1,42 +1,42 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000668 # Number of seconds simulated -sim_ticks 668137500 # Number of ticks simulated -final_tick 668137500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000667 # Number of seconds simulated +sim_ticks 667407500 # Number of ticks simulated +final_tick 667407500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 245703 # Simulator instruction rate (inst/s) -host_op_rate 505252 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2451366703 # Simulator tick rate (ticks/s) -host_mem_usage 1323744 # Number of bytes of host memory used -host_seconds 0.27 # Real time elapsed on the host +host_inst_rate 72185 # Simulator instruction rate (inst/s) +host_op_rate 148440 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 719412350 # Simulator tick rate (ticks/s) +host_mem_usage 1308600 # Number of bytes of host memory used +host_seconds 0.93 # Real time elapsed on the host sim_insts 66963 # Number of instructions simulated sim_ops 137705 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states -system.mem_ctrls.bytes_read::dir_cntrl0 99264 # Number of bytes read from this memory -system.mem_ctrls.bytes_read::total 99264 # Number of bytes read from this memory -system.mem_ctrls.num_reads::dir_cntrl0 1551 # Number of read requests responded to by this memory -system.mem_ctrls.num_reads::total 1551 # Number of read requests responded to by this memory -system.mem_ctrls.bw_read::dir_cntrl0 148568221 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_read::total 148568221 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_total::dir_cntrl0 148568221 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.bw_total::total 148568221 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.readReqs 1551 # Number of read requests accepted +system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states +system.mem_ctrls.bytes_read::dir_cntrl0 99136 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::total 99136 # Number of bytes read from this memory +system.mem_ctrls.num_reads::dir_cntrl0 1549 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::total 1549 # Number of read requests responded to by this memory +system.mem_ctrls.bw_read::dir_cntrl0 148538936 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::total 148538936 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_total::dir_cntrl0 148538936 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::total 148538936 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.readReqs 1549 # Number of read requests accepted system.mem_ctrls.writeReqs 0 # Number of write requests accepted -system.mem_ctrls.readBursts 1551 # Number of DRAM read bursts, including those serviced by the write queue +system.mem_ctrls.readBursts 1549 # Number of DRAM read bursts, including those serviced by the write queue system.mem_ctrls.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.mem_ctrls.bytesReadDRAM 99264 # Total number of bytes read from DRAM +system.mem_ctrls.bytesReadDRAM 99136 # Total number of bytes read from DRAM system.mem_ctrls.bytesReadWrQ 0 # Total number of bytes read from write queue system.mem_ctrls.bytesWritten 0 # Total number of bytes written to DRAM -system.mem_ctrls.bytesReadSys 99264 # Total read bytes from the system interface side +system.mem_ctrls.bytesReadSys 99136 # Total read bytes from the system interface side system.mem_ctrls.bytesWrittenSys 0 # Total written bytes from the system interface side system.mem_ctrls.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.mem_ctrls.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.mem_ctrls.perBankRdBursts::0 122 # Per bank write bursts system.mem_ctrls.perBankRdBursts::1 192 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::2 93 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::2 91 # Per bank write bursts system.mem_ctrls.perBankRdBursts::3 44 # Per bank write bursts system.mem_ctrls.perBankRdBursts::4 61 # Per bank write bursts system.mem_ctrls.perBankRdBursts::5 79 # Per bank write bursts @@ -68,14 +68,14 @@ system.mem_ctrls.perBankWrBursts::14 0 # Pe system.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry -system.mem_ctrls.totGap 667904000 # Total gap between requests +system.mem_ctrls.totGap 667174000 # Total gap between requests system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::6 1551 # Read request sizes (log2) +system.mem_ctrls.readPktSize::6 1549 # Read request sizes (log2) system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) @@ -83,13 +83,13 @@ system.mem_ctrls.writePktSize::3 0 # Wr system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::6 0 # Write request sizes (log2) -system.mem_ctrls.rdQLenPdf::0 1542 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::0 1540 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::1 2 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::2 1 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::3 1 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::4 1 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::4 2 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::5 1 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::6 2 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::6 1 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::7 1 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see @@ -180,28 +180,28 @@ system.mem_ctrls.wrQLenPdf::61 0 # Wh system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see system.mem_ctrls.bytesPerActivate::samples 484 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::mean 203.636364 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::gmean 145.087483 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::stdev 194.740960 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::mean 203.371901 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::gmean 144.930715 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::stdev 194.713066 # Bytes accessed per row activation system.mem_ctrls.bytesPerActivate::0-127 177 36.57% 36.57% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::128-255 167 34.50% 71.07% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::256-383 64 13.22% 84.30% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::128-255 168 34.71% 71.28% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::256-383 63 13.02% 84.30% # Bytes accessed per row activation system.mem_ctrls.bytesPerActivate::384-511 29 5.99% 90.29% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::512-639 20 4.13% 94.42% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::640-767 10 2.07% 96.49% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::512-639 19 3.93% 94.21% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::640-767 11 2.27% 96.49% # Bytes accessed per row activation system.mem_ctrls.bytesPerActivate::768-895 10 2.07% 98.55% # Bytes accessed per row activation system.mem_ctrls.bytesPerActivate::896-1023 2 0.41% 98.97% # Bytes accessed per row activation system.mem_ctrls.bytesPerActivate::1024-1151 5 1.03% 100.00% # Bytes accessed per row activation system.mem_ctrls.bytesPerActivate::total 484 # Bytes accessed per row activation -system.mem_ctrls.totQLat 31097995 # Total ticks spent queuing -system.mem_ctrls.totMemAccLat 60179245 # Total ticks spent from burst creation until serviced by the DRAM -system.mem_ctrls.totBusLat 7755000 # Total ticks spent in databus transfers -system.mem_ctrls.avgQLat 20050.29 # Average queueing delay per DRAM burst +system.mem_ctrls.totQLat 31625750 # Total ticks spent queuing +system.mem_ctrls.totMemAccLat 60669500 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.totBusLat 7745000 # Total ticks spent in databus transfers +system.mem_ctrls.avgQLat 20416.88 # Average queueing delay per DRAM burst system.mem_ctrls.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.mem_ctrls.avgMemAccLat 38800.29 # Average memory access latency per DRAM burst -system.mem_ctrls.avgRdBW 148.57 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrls.avgMemAccLat 39166.88 # Average memory access latency per DRAM burst +system.mem_ctrls.avgRdBW 148.54 # Average DRAM read bandwidth in MiByte/s system.mem_ctrls.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.mem_ctrls.avgRdBWSys 148.57 # Average system read bandwidth in MiByte/s +system.mem_ctrls.avgRdBWSys 148.54 # Average system read bandwidth in MiByte/s system.mem_ctrls.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.mem_ctrls.busUtil 1.16 # Data bus utilization in percentage @@ -209,94 +209,94 @@ system.mem_ctrls.busUtilRead 1.16 # Da system.mem_ctrls.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing system.mem_ctrls.avgWrQLen 0.00 # Average write queue length when enqueuing -system.mem_ctrls.readRowHits 1062 # Number of row buffer hits during reads +system.mem_ctrls.readRowHits 1060 # Number of row buffer hits during reads system.mem_ctrls.writeRowHits 0 # Number of row buffer hits during writes -system.mem_ctrls.readRowHitRate 68.47 # Row buffer hit rate for reads +system.mem_ctrls.readRowHitRate 68.43 # Row buffer hit rate for reads system.mem_ctrls.writeRowHitRate nan # Row buffer hit rate for writes -system.mem_ctrls.avgGap 430627.98 # Average gap between requests -system.mem_ctrls.pageHitRate 68.47 # Row buffer hit rate, read and write combined +system.mem_ctrls.avgGap 430712.72 # Average gap between requests +system.mem_ctrls.pageHitRate 68.43 # Row buffer hit rate, read and write combined system.mem_ctrls_0.actEnergy 1320900 # Energy for activate commands per rank (pJ) system.mem_ctrls_0.preEnergy 694485 # Energy for precharge commands per rank (pJ) -system.mem_ctrls_0.readEnergy 4890900 # Energy for read commands per rank (pJ) +system.mem_ctrls_0.readEnergy 4876620 # Energy for read commands per rank (pJ) system.mem_ctrls_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.mem_ctrls_0.refreshEnergy 51629760.000000 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_0.actBackEnergy 18618480 # Energy for active background per rank (pJ) +system.mem_ctrls_0.actBackEnergy 18588840 # Energy for active background per rank (pJ) system.mem_ctrls_0.preBackEnergy 1670400 # Energy for precharge background per rank (pJ) -system.mem_ctrls_0.actPowerDownEnergy 210199470 # Energy for active power-down per rank (pJ) -system.mem_ctrls_0.prePowerDownEnergy 42511680 # Energy for precharge power-down per rank (pJ) -system.mem_ctrls_0.selfRefreshEnergy 15622140 # Energy for self refresh per rank (pJ) -system.mem_ctrls_0.totalEnergy 347158215 # Total energy per rank (pJ) -system.mem_ctrls_0.averagePower 519.590975 # Core power per rank (mW) -system.mem_ctrls_0.totalIdleTime 622801252 # Total Idle time Per DRAM Rank +system.mem_ctrls_0.actPowerDownEnergy 210561990 # Energy for active power-down per rank (pJ) +system.mem_ctrls_0.prePowerDownEnergy 42231360 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls_0.selfRefreshEnergy 15446940 # Energy for self refresh per rank (pJ) +system.mem_ctrls_0.totalEnergy 347021295 # Total energy per rank (pJ) +system.mem_ctrls_0.averagePower 519.954143 # Core power per rank (mW) +system.mem_ctrls_0.totalIdleTime 622134250 # Total Idle time Per DRAM Rank system.mem_ctrls_0.memoryStateTime::IDLE 2030000 # Time in different power states system.mem_ctrls_0.memoryStateTime::REF 21876000 # Time in different power states -system.mem_ctrls_0.memoryStateTime::SREF 51287000 # Time in different power states -system.mem_ctrls_0.memoryStateTime::PRE_PDN 110705750 # Time in different power states -system.mem_ctrls_0.memoryStateTime::ACT 21255248 # Time in different power states -system.mem_ctrls_0.memoryStateTime::ACT_PDN 460983502 # Time in different power states +system.mem_ctrls_0.memoryStateTime::SREF 50557000 # Time in different power states +system.mem_ctrls_0.memoryStateTime::PRE_PDN 109975750 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT 21192250 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT_PDN 461776500 # Time in different power states system.mem_ctrls_1.actEnergy 2170560 # Energy for activate commands per rank (pJ) system.mem_ctrls_1.preEnergy 1142295 # Energy for precharge commands per rank (pJ) system.mem_ctrls_1.readEnergy 6183240 # Energy for read commands per rank (pJ) system.mem_ctrls_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.mem_ctrls_1.refreshEnergy 52244400.000000 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_1.actBackEnergy 21589320 # Energy for active background per rank (pJ) +system.mem_ctrls_1.actBackEnergy 21584190 # Energy for active background per rank (pJ) system.mem_ctrls_1.preBackEnergy 1299360 # Energy for precharge background per rank (pJ) -system.mem_ctrls_1.actPowerDownEnergy 243172830 # Energy for active power-down per rank (pJ) -system.mem_ctrls_1.prePowerDownEnergy 28283040 # Energy for precharge power-down per rank (pJ) -system.mem_ctrls_1.selfRefreshEnergy 3067740 # Energy for self refresh per rank (pJ) -system.mem_ctrls_1.totalEnergy 359152785 # Total energy per rank (pJ) -system.mem_ctrls_1.averagePower 537.543223 # Core power per rank (mW) -system.mem_ctrls_1.totalIdleTime 616852750 # Total Idle time Per DRAM Rank +system.mem_ctrls_1.actPowerDownEnergy 243510840 # Energy for active power-down per rank (pJ) +system.mem_ctrls_1.prePowerDownEnergy 28002720 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls_1.selfRefreshEnergy 2892540 # Energy for self refresh per rank (pJ) +system.mem_ctrls_1.totalEnergy 359030145 # Total energy per rank (pJ) +system.mem_ctrls_1.averagePower 537.947423 # Core power per rank (mW) +system.mem_ctrls_1.totalIdleTime 616133750 # Total Idle time Per DRAM Rank system.mem_ctrls_1.memoryStateTime::IDLE 980000 # Time in different power states system.mem_ctrls_1.memoryStateTime::REF 22106000 # Time in different power states -system.mem_ctrls_1.memoryStateTime::SREF 10481250 # Time in different power states -system.mem_ctrls_1.memoryStateTime::PRE_PDN 73643500 # Time in different power states -system.mem_ctrls_1.memoryStateTime::ACT 27629000 # Time in different power states -system.mem_ctrls_1.memoryStateTime::ACT_PDN 533297750 # Time in different power states +system.mem_ctrls_1.memoryStateTime::SREF 9751250 # Time in different power states +system.mem_ctrls_1.memoryStateTime::PRE_PDN 72913500 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT 27618000 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT_PDN 534038750 # Time in different power states system.ruby.clk_domain.clock 500 # Clock period in ticks -system.ruby.phys_mem.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states +system.ruby.phys_mem.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states system.ruby.phys_mem.bytes_read::cpu0.inst 696760 # Number of bytes read from this memory system.ruby.phys_mem.bytes_read::cpu0.data 119832 # Number of bytes read from this memory -system.ruby.phys_mem.bytes_read::cpu1.CUs0.ComputeUnit 3280 # Number of bytes read from this memory -system.ruby.phys_mem.bytes_read::cpu1.CUs1.ComputeUnit 3280 # Number of bytes read from this memory -system.ruby.phys_mem.bytes_read::total 823152 # Number of bytes read from this memory +system.ruby.phys_mem.bytes_read::cpu1.CUs0.ComputeUnit 2856 # Number of bytes read from this memory +system.ruby.phys_mem.bytes_read::cpu1.CUs1.ComputeUnit 2856 # Number of bytes read from this memory +system.ruby.phys_mem.bytes_read::total 822304 # Number of bytes read from this memory system.ruby.phys_mem.bytes_inst_read::cpu0.inst 696760 # Number of instructions bytes read from this memory -system.ruby.phys_mem.bytes_inst_read::cpu1.CUs0.ComputeUnit 2000 # Number of instructions bytes read from this memory -system.ruby.phys_mem.bytes_inst_read::cpu1.CUs1.ComputeUnit 2000 # Number of instructions bytes read from this memory -system.ruby.phys_mem.bytes_inst_read::total 700760 # Number of instructions bytes read from this memory +system.ruby.phys_mem.bytes_inst_read::cpu1.CUs0.ComputeUnit 1576 # Number of instructions bytes read from this memory +system.ruby.phys_mem.bytes_inst_read::cpu1.CUs1.ComputeUnit 1576 # Number of instructions bytes read from this memory +system.ruby.phys_mem.bytes_inst_read::total 699912 # Number of instructions bytes read from this memory system.ruby.phys_mem.bytes_written::cpu0.data 72767 # Number of bytes written to this memory system.ruby.phys_mem.bytes_written::cpu1.CUs0.ComputeUnit 256 # Number of bytes written to this memory system.ruby.phys_mem.bytes_written::cpu1.CUs1.ComputeUnit 256 # Number of bytes written to this memory system.ruby.phys_mem.bytes_written::total 73279 # Number of bytes written to this memory system.ruby.phys_mem.num_reads::cpu0.inst 87095 # Number of read requests responded to by this memory system.ruby.phys_mem.num_reads::cpu0.data 16686 # Number of read requests responded to by this memory -system.ruby.phys_mem.num_reads::cpu1.CUs0.ComputeUnit 555 # Number of read requests responded to by this memory -system.ruby.phys_mem.num_reads::cpu1.CUs1.ComputeUnit 555 # Number of read requests responded to by this memory -system.ruby.phys_mem.num_reads::total 104891 # Number of read requests responded to by this memory +system.ruby.phys_mem.num_reads::cpu1.CUs0.ComputeUnit 547 # Number of read requests responded to by this memory +system.ruby.phys_mem.num_reads::cpu1.CUs1.ComputeUnit 547 # Number of read requests responded to by this memory +system.ruby.phys_mem.num_reads::total 104875 # Number of read requests responded to by this memory system.ruby.phys_mem.num_writes::cpu0.data 10422 # Number of write requests responded to by this memory system.ruby.phys_mem.num_writes::cpu1.CUs0.ComputeUnit 256 # Number of write requests responded to by this memory system.ruby.phys_mem.num_writes::cpu1.CUs1.ComputeUnit 256 # Number of write requests responded to by this memory system.ruby.phys_mem.num_writes::total 10934 # Number of write requests responded to by this memory -system.ruby.phys_mem.bw_read::cpu0.inst 1042839236 # Total read bandwidth from this memory (bytes/s) -system.ruby.phys_mem.bw_read::cpu0.data 179352304 # Total read bandwidth from this memory (bytes/s) -system.ruby.phys_mem.bw_read::cpu1.CUs0.ComputeUnit 4909169 # Total read bandwidth from this memory (bytes/s) -system.ruby.phys_mem.bw_read::cpu1.CUs1.ComputeUnit 4909169 # Total read bandwidth from this memory (bytes/s) -system.ruby.phys_mem.bw_read::total 1232009878 # Total read bandwidth from this memory (bytes/s) -system.ruby.phys_mem.bw_inst_read::cpu0.inst 1042839236 # Instruction read bandwidth from this memory (bytes/s) -system.ruby.phys_mem.bw_inst_read::cpu1.CUs0.ComputeUnit 2993396 # Instruction read bandwidth from this memory (bytes/s) -system.ruby.phys_mem.bw_inst_read::cpu1.CUs1.ComputeUnit 2993396 # Instruction read bandwidth from this memory (bytes/s) -system.ruby.phys_mem.bw_inst_read::total 1048826028 # Instruction read bandwidth from this memory (bytes/s) -system.ruby.phys_mem.bw_write::cpu0.data 108910217 # Write bandwidth from this memory (bytes/s) -system.ruby.phys_mem.bw_write::cpu1.CUs0.ComputeUnit 383155 # Write bandwidth from this memory (bytes/s) -system.ruby.phys_mem.bw_write::cpu1.CUs1.ComputeUnit 383155 # Write bandwidth from this memory (bytes/s) -system.ruby.phys_mem.bw_write::total 109676526 # Write bandwidth from this memory (bytes/s) -system.ruby.phys_mem.bw_total::cpu0.inst 1042839236 # Total bandwidth to/from this memory (bytes/s) -system.ruby.phys_mem.bw_total::cpu0.data 288262521 # Total bandwidth to/from this memory (bytes/s) -system.ruby.phys_mem.bw_total::cpu1.CUs0.ComputeUnit 5292324 # Total bandwidth to/from this memory (bytes/s) -system.ruby.phys_mem.bw_total::cpu1.CUs1.ComputeUnit 5292324 # Total bandwidth to/from this memory (bytes/s) -system.ruby.phys_mem.bw_total::total 1341686404 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states -system.ruby.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states +system.ruby.phys_mem.bw_read::cpu0.inst 1043979877 # Total read bandwidth from this memory (bytes/s) +system.ruby.phys_mem.bw_read::cpu0.data 179548477 # Total read bandwidth from this memory (bytes/s) +system.ruby.phys_mem.bw_read::cpu1.CUs0.ComputeUnit 4279245 # Total read bandwidth from this memory (bytes/s) +system.ruby.phys_mem.bw_read::cpu1.CUs1.ComputeUnit 4279245 # Total read bandwidth from this memory (bytes/s) +system.ruby.phys_mem.bw_read::total 1232086843 # Total read bandwidth from this memory (bytes/s) +system.ruby.phys_mem.bw_inst_read::cpu0.inst 1043979877 # Instruction read bandwidth from this memory (bytes/s) +system.ruby.phys_mem.bw_inst_read::cpu1.CUs0.ComputeUnit 2361376 # Instruction read bandwidth from this memory (bytes/s) +system.ruby.phys_mem.bw_inst_read::cpu1.CUs1.ComputeUnit 2361376 # Instruction read bandwidth from this memory (bytes/s) +system.ruby.phys_mem.bw_inst_read::total 1048702629 # Instruction read bandwidth from this memory (bytes/s) +system.ruby.phys_mem.bw_write::cpu0.data 109029341 # Write bandwidth from this memory (bytes/s) +system.ruby.phys_mem.bw_write::cpu1.CUs0.ComputeUnit 383574 # Write bandwidth from this memory (bytes/s) +system.ruby.phys_mem.bw_write::cpu1.CUs1.ComputeUnit 383574 # Write bandwidth from this memory (bytes/s) +system.ruby.phys_mem.bw_write::total 109796489 # Write bandwidth from this memory (bytes/s) +system.ruby.phys_mem.bw_total::cpu0.inst 1043979877 # Total bandwidth to/from this memory (bytes/s) +system.ruby.phys_mem.bw_total::cpu0.data 288577818 # Total bandwidth to/from this memory (bytes/s) +system.ruby.phys_mem.bw_total::cpu1.CUs0.ComputeUnit 4662818 # Total bandwidth to/from this memory (bytes/s) +system.ruby.phys_mem.bw_total::cpu1.CUs1.ComputeUnit 4662818 # Total bandwidth to/from this memory (bytes/s) +system.ruby.phys_mem.bw_total::total 1341883332 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states +system.ruby.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states system.ruby.outstanding_req_hist_seqr::bucket_size 1 system.ruby.outstanding_req_hist_seqr::max_bucket 9 system.ruby.outstanding_req_hist_seqr::samples 114203 @@ -308,10 +308,10 @@ system.ruby.outstanding_req_hist_seqr::total 114203 system.ruby.outstanding_req_hist_coalsr::bucket_size 1 system.ruby.outstanding_req_hist_coalsr::max_bucket 9 system.ruby.outstanding_req_hist_coalsr::samples 27 -system.ruby.outstanding_req_hist_coalsr::mean 1.629630 -system.ruby.outstanding_req_hist_coalsr::gmean 1.438746 -system.ruby.outstanding_req_hist_coalsr::stdev 0.926040 -system.ruby.outstanding_req_hist_coalsr | 0 0.00% 0.00% | 16 59.26% 59.26% | 7 25.93% 85.19% | 2 7.41% 92.59% | 2 7.41% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.outstanding_req_hist_coalsr::mean 2.074074 +system.ruby.outstanding_req_hist_coalsr::gmean 1.820631 +system.ruby.outstanding_req_hist_coalsr::stdev 1.071517 +system.ruby.outstanding_req_hist_coalsr | 0 0.00% 0.00% | 10 37.04% 37.04% | 9 33.33% 70.37% | 4 14.81% 85.19% | 4 14.81% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.outstanding_req_hist_coalsr::total 27 system.ruby.latency_hist_seqr::bucket_size 64 system.ruby.latency_hist_seqr::max_bucket 639 @@ -324,10 +324,10 @@ system.ruby.latency_hist_seqr::total 114203 system.ruby.latency_hist_coalsr::bucket_size 64 system.ruby.latency_hist_coalsr::max_bucket 639 system.ruby.latency_hist_coalsr::samples 27 -system.ruby.latency_hist_coalsr::mean 171 -system.ruby.latency_hist_coalsr::gmean 22.942606 -system.ruby.latency_hist_coalsr::stdev 184.818206 -system.ruby.latency_hist_coalsr | 13 48.15% 48.15% | 0 0.00% 48.15% | 0 0.00% 48.15% | 7 25.93% 74.07% | 2 7.41% 81.48% | 1 3.70% 85.19% | 1 3.70% 88.89% | 1 3.70% 92.59% | 2 7.41% 100.00% | 0 0.00% 100.00% +system.ruby.latency_hist_coalsr::mean 175.777778 +system.ruby.latency_hist_coalsr::gmean 29.086037 +system.ruby.latency_hist_coalsr::stdev 175.084668 +system.ruby.latency_hist_coalsr | 13 48.15% 48.15% | 0 0.00% 48.15% | 0 0.00% 48.15% | 1 3.70% 51.85% | 2 7.41% 59.26% | 7 25.93% 85.19% | 4 14.81% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.latency_hist_coalsr::total 27 system.ruby.hit_latency_hist_seqr::bucket_size 64 system.ruby.hit_latency_hist_seqr::max_bucket 639 @@ -348,10 +348,10 @@ system.ruby.miss_latency_hist_seqr::total 112668 system.ruby.miss_latency_hist_coalsr::bucket_size 64 system.ruby.miss_latency_hist_coalsr::max_bucket 639 system.ruby.miss_latency_hist_coalsr::samples 27 -system.ruby.miss_latency_hist_coalsr::mean 171 -system.ruby.miss_latency_hist_coalsr::gmean 22.942606 -system.ruby.miss_latency_hist_coalsr::stdev 184.818206 -system.ruby.miss_latency_hist_coalsr | 13 48.15% 48.15% | 0 0.00% 48.15% | 0 0.00% 48.15% | 7 25.93% 74.07% | 2 7.41% 81.48% | 1 3.70% 85.19% | 1 3.70% 88.89% | 1 3.70% 92.59% | 2 7.41% 100.00% | 0 0.00% 100.00% +system.ruby.miss_latency_hist_coalsr::mean 175.777778 +system.ruby.miss_latency_hist_coalsr::gmean 29.086037 +system.ruby.miss_latency_hist_coalsr::stdev 175.084668 +system.ruby.miss_latency_hist_coalsr | 13 48.15% 48.15% | 0 0.00% 48.15% | 0 0.00% 48.15% | 1 3.70% 51.85% | 2 7.41% 59.26% | 7 25.93% 85.19% | 4 14.81% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.miss_latency_hist_coalsr::total 27 system.ruby.L1Cache.incomplete_times_seqr 112609 system.ruby.L2Cache.incomplete_times_seqr 59 @@ -377,27 +377,27 @@ system.cp_cntrl0.L2cache.demand_misses 1535 # Nu system.cp_cntrl0.L2cache.demand_accesses 1535 # Number of cache demand accesses system.cp_cntrl0.L2cache.num_data_array_reads 120 # number of data array reads system.cp_cntrl0.L2cache.num_data_array_writes 11982 # number of data array writes -system.cp_cntrl0.L2cache.num_tag_array_reads 12059 # number of tag array reads +system.cp_cntrl0.L2cache.num_tag_array_reads 12057 # number of tag array reads system.cp_cntrl0.L2cache.num_tag_array_writes 1649 # number of tag array writes -system.cp_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states -system.cp_cntrl0.sequencer1.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states -system.cp_cntrl0.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states +system.cp_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states +system.cp_cntrl0.sequencer1.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states +system.cp_cntrl0.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states system.cpu0.clk_domain.clock 500 # Clock period in ticks -system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states +system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states system.cpu0.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu0.interrupts.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states -system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states +system.cpu0.interrupts.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states +system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states system.cpu0.workload.num_syscalls 21 # Number of system calls system.cpu0.numPwrStateTransitions 2 # Number of power state transitions system.cpu0.pwrStateClkGateDist::samples 1 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::mean 2825501 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::mean 2095501 # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::1000-5e+10 1 100.00% 100.00% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::min_value 2825501 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::max_value 2825501 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::min_value 2095501 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::max_value 2095501 # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::total 1 # Distribution of time spent in the clock gated state system.cpu0.pwrStateResidencyTicks::ON 665311999 # Cumulative time (in ticks) in various power states -system.cpu0.pwrStateResidencyTicks::CLK_GATED 2825501 # Cumulative time (in ticks) in various power states -system.cpu0.numCycles 1336275 # number of cpu cycles simulated +system.cpu0.pwrStateResidencyTicks::CLK_GATED 2095501 # Cumulative time (in ticks) in various power states +system.cpu0.numCycles 1334815 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu0.committedInsts 66963 # Number of instructions committed @@ -417,10 +417,10 @@ system.cpu0.num_cc_register_writes 42183 # nu system.cpu0.num_mem_refs 27198 # number of memory refs system.cpu0.num_load_insts 16684 # Number of load instructions system.cpu0.num_store_insts 10514 # Number of store instructions -system.cpu0.num_idle_cycles 5651.003992 # Number of idle cycles -system.cpu0.num_busy_cycles 1330623.996008 # Number of busy cycles -system.cpu0.not_idle_fraction 0.995771 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.004229 # Percentage of idle cycles +system.cpu0.num_idle_cycles 4191.003994 # Number of idle cycles +system.cpu0.num_busy_cycles 1330623.996006 # Number of busy cycles +system.cpu0.not_idle_fraction 0.996860 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.003140 # Percentage of idle cycles system.cpu0.Branches 16199 # Number of branches fetched system.cpu0.op_class::No_OpClass 615 0.45% 0.45% # Class of executed instruction system.cpu0.op_class::IntAlu 108791 79.00% 79.45% # Class of executed instruction @@ -463,10 +463,10 @@ system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Cl system.cpu0.op_class::total 137705 # Class of executed instruction system.cpu1.clk_domain.voltage_domain.voltage 1 # Voltage in Volts system.cpu1.clk_domain.clock 1000 # Clock period in ticks -system.cpu1.CUs0.localDataStore.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states +system.cpu1.CUs0.localDataStore.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states system.cpu1.CUs0.wavefronts00.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability system.cpu1.CUs0.wavefronts00.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies -system.cpu1.CUs0.wavefronts00.timesBlockedDueRAWDependencies 498 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs0.wavefronts00.timesBlockedDueRAWDependencies 309 # number of times the wf's instructions are blocked due to RAW dependencies system.cpu1.CUs0.wavefronts00.src_reg_operand_dist::samples 39 # number of executed instructions with N source register operands system.cpu1.CUs0.wavefronts00.src_reg_operand_dist::mean 0.794872 # number of executed instructions with N source register operands system.cpu1.CUs0.wavefronts00.src_reg_operand_dist::stdev 0.863880 # number of executed instructions with N source register operands @@ -658,7 +658,7 @@ system.cpu1.CUs0.wavefronts07.dst_reg_operand_dist::max_value 0 system.cpu1.CUs0.wavefronts07.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands system.cpu1.CUs0.wavefronts08.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability system.cpu1.CUs0.wavefronts08.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies -system.cpu1.CUs0.wavefronts08.timesBlockedDueRAWDependencies 470 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs0.wavefronts08.timesBlockedDueRAWDependencies 284 # number of times the wf's instructions are blocked due to RAW dependencies system.cpu1.CUs0.wavefronts08.src_reg_operand_dist::samples 34 # number of executed instructions with N source register operands system.cpu1.CUs0.wavefronts08.src_reg_operand_dist::mean 0.852941 # number of executed instructions with N source register operands system.cpu1.CUs0.wavefronts08.src_reg_operand_dist::stdev 0.857493 # number of executed instructions with N source register operands @@ -850,7 +850,7 @@ system.cpu1.CUs0.wavefronts15.dst_reg_operand_dist::max_value 0 system.cpu1.CUs0.wavefronts15.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands system.cpu1.CUs0.wavefronts16.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability system.cpu1.CUs0.wavefronts16.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies -system.cpu1.CUs0.wavefronts16.timesBlockedDueRAWDependencies 473 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs0.wavefronts16.timesBlockedDueRAWDependencies 279 # number of times the wf's instructions are blocked due to RAW dependencies system.cpu1.CUs0.wavefronts16.src_reg_operand_dist::samples 34 # number of executed instructions with N source register operands system.cpu1.CUs0.wavefronts16.src_reg_operand_dist::mean 0.852941 # number of executed instructions with N source register operands system.cpu1.CUs0.wavefronts16.src_reg_operand_dist::stdev 0.857493 # number of executed instructions with N source register operands @@ -1042,7 +1042,7 @@ system.cpu1.CUs0.wavefronts23.dst_reg_operand_dist::max_value 0 system.cpu1.CUs0.wavefronts23.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands system.cpu1.CUs0.wavefronts24.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability system.cpu1.CUs0.wavefronts24.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies -system.cpu1.CUs0.wavefronts24.timesBlockedDueRAWDependencies 467 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs0.wavefronts24.timesBlockedDueRAWDependencies 274 # number of times the wf's instructions are blocked due to RAW dependencies system.cpu1.CUs0.wavefronts24.src_reg_operand_dist::samples 34 # number of executed instructions with N source register operands system.cpu1.CUs0.wavefronts24.src_reg_operand_dist::mean 0.852941 # number of executed instructions with N source register operands system.cpu1.CUs0.wavefronts24.src_reg_operand_dist::stdev 0.857493 # number of executed instructions with N source register operands @@ -1232,27 +1232,27 @@ system.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::overflows 0 system.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands system.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands system.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands -system.cpu1.CUs0.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states -system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::samples 43 # For each instruction fetch request recieved record how many instructions you got from it -system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::mean 5.813953 # For each instruction fetch request recieved record how many instructions you got from it -system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::stdev 2.683777 # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs0.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states +system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::samples 35 # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::mean 11.257143 # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::stdev 5.595917 # For each instruction fetch request recieved record how many instructions you got from it system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::underflows 0 0.00% 0.00% # For each instruction fetch request recieved record how many instructions you got from it system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::1 0 0.00% 0.00% # For each instruction fetch request recieved record how many instructions you got from it -system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::2 8 18.60% 18.60% # For each instruction fetch request recieved record how many instructions you got from it -system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::3 8 18.60% 37.21% # For each instruction fetch request recieved record how many instructions you got from it -system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::4 1 2.33% 39.53% # For each instruction fetch request recieved record how many instructions you got from it -system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::5 0 0.00% 39.53% # For each instruction fetch request recieved record how many instructions you got from it -system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::6 1 2.33% 41.86% # For each instruction fetch request recieved record how many instructions you got from it -system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::7 0 0.00% 41.86% # For each instruction fetch request recieved record how many instructions you got from it -system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::8 25 58.14% 100.00% # For each instruction fetch request recieved record how many instructions you got from it -system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::9 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it -system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::10 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it -system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::11 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it -system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::12 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it -system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::13 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it -system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::14 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it -system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::15 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it -system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::16 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::2 4 11.43% 11.43% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::3 4 11.43% 22.86% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::4 1 2.86% 25.71% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::5 0 0.00% 25.71% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::6 0 0.00% 25.71% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::7 0 0.00% 25.71% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::8 0 0.00% 25.71% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::9 0 0.00% 25.71% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::10 4 11.43% 37.14% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::11 4 11.43% 48.57% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::12 0 0.00% 48.57% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::13 0 0.00% 48.57% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::14 1 2.86% 51.43% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::15 0 0.00% 51.43% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::16 17 48.57% 100.00% # For each instruction fetch request recieved record how many instructions you got from it system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::17 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::18 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::19 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it @@ -1271,9 +1271,9 @@ system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::31 0 0.00 system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::32 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::overflows 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::min_value 2 # For each instruction fetch request recieved record how many instructions you got from it -system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::max_value 8 # For each instruction fetch request recieved record how many instructions you got from it -system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::total 43 # For each instruction fetch request recieved record how many instructions you got from it -system.cpu1.CUs0.ExecStage.num_cycles_with_no_issue 3471 # number of cycles the CU issues nothing +system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::max_value 16 # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::total 35 # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs0.ExecStage.num_cycles_with_no_issue 2741 # number of cycles the CU issues nothing system.cpu1.CUs0.ExecStage.num_cycles_with_instr_issued 99 # number of cycles the CU issued at least one instruction system.cpu1.CUs0.ExecStage.num_cycles_with_instrtype_issue::ALU0 30 # Number of cycles at least one instruction of specific type issued system.cpu1.CUs0.ExecStage.num_cycles_with_instrtype_issue::ALU1 29 # Number of cycles at least one instruction of specific type issued @@ -1281,57 +1281,79 @@ system.cpu1.CUs0.ExecStage.num_cycles_with_instrtype_issue::ALU2 29 system.cpu1.CUs0.ExecStage.num_cycles_with_instrtype_issue::ALU3 29 # Number of cycles at least one instruction of specific type issued system.cpu1.CUs0.ExecStage.num_cycles_with_instrtype_issue::GM 18 # Number of cycles at least one instruction of specific type issued system.cpu1.CUs0.ExecStage.num_cycles_with_instrtype_issue::LM 6 # Number of cycles at least one instruction of specific type issued -system.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::ALU0 970 # Number of cycles no instruction of specific type issued -system.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::ALU1 548 # Number of cycles no instruction of specific type issued -system.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::ALU2 566 # Number of cycles no instruction of specific type issued -system.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::ALU3 523 # Number of cycles no instruction of specific type issued -system.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::GM 398 # Number of cycles no instruction of specific type issued +system.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::ALU0 625 # Number of cycles no instruction of specific type issued +system.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::ALU1 340 # Number of cycles no instruction of specific type issued +system.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::ALU2 338 # Number of cycles no instruction of specific type issued +system.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::ALU3 335 # Number of cycles no instruction of specific type issued +system.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::GM 404 # Number of cycles no instruction of specific type issued system.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::LM 22 # Number of cycles no instruction of specific type issued -system.cpu1.CUs0.ExecStage.spc::samples 3570 # Execution units active per cycle (Exec unit=SIMD,MemPipe) -system.cpu1.CUs0.ExecStage.spc::mean 0.039496 # Execution units active per cycle (Exec unit=SIMD,MemPipe) -system.cpu1.CUs0.ExecStage.spc::stdev 0.250206 # Execution units active per cycle (Exec unit=SIMD,MemPipe) +system.cpu1.CUs0.ExecStage.spc::samples 2840 # Execution units active per cycle (Exec unit=SIMD,MemPipe) +system.cpu1.CUs0.ExecStage.spc::mean 0.049648 # Execution units active per cycle (Exec unit=SIMD,MemPipe) +system.cpu1.CUs0.ExecStage.spc::stdev 0.277106 # Execution units active per cycle (Exec unit=SIMD,MemPipe) system.cpu1.CUs0.ExecStage.spc::underflows 0 0.00% 0.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe) -system.cpu1.CUs0.ExecStage.spc::0 3471 97.23% 97.23% # Execution units active per cycle (Exec unit=SIMD,MemPipe) -system.cpu1.CUs0.ExecStage.spc::1 59 1.65% 98.88% # Execution units active per cycle (Exec unit=SIMD,MemPipe) -system.cpu1.CUs0.ExecStage.spc::2 38 1.06% 99.94% # Execution units active per cycle (Exec unit=SIMD,MemPipe) -system.cpu1.CUs0.ExecStage.spc::3 2 0.06% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe) +system.cpu1.CUs0.ExecStage.spc::0 2741 96.51% 96.51% # Execution units active per cycle (Exec unit=SIMD,MemPipe) +system.cpu1.CUs0.ExecStage.spc::1 57 2.01% 98.52% # Execution units active per cycle (Exec unit=SIMD,MemPipe) +system.cpu1.CUs0.ExecStage.spc::2 42 1.48% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe) +system.cpu1.CUs0.ExecStage.spc::3 0 0.00% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe) system.cpu1.CUs0.ExecStage.spc::4 0 0.00% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe) system.cpu1.CUs0.ExecStage.spc::5 0 0.00% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe) system.cpu1.CUs0.ExecStage.spc::6 0 0.00% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe) system.cpu1.CUs0.ExecStage.spc::overflows 0 0.00% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe) system.cpu1.CUs0.ExecStage.spc::min_value 0 # Execution units active per cycle (Exec unit=SIMD,MemPipe) -system.cpu1.CUs0.ExecStage.spc::max_value 3 # Execution units active per cycle (Exec unit=SIMD,MemPipe) -system.cpu1.CUs0.ExecStage.spc::total 3570 # Execution units active per cycle (Exec unit=SIMD,MemPipe) -system.cpu1.CUs0.ExecStage.num_transitions_active_to_idle 93 # number of CU transitions from active to idle -system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::samples 93 # duration of idle periods in cycles -system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::mean 37.225806 # duration of idle periods in cycles -system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::stdev 154.644552 # duration of idle periods in cycles +system.cpu1.CUs0.ExecStage.spc::max_value 2 # Execution units active per cycle (Exec unit=SIMD,MemPipe) +system.cpu1.CUs0.ExecStage.spc::total 2840 # Execution units active per cycle (Exec unit=SIMD,MemPipe) +system.cpu1.CUs0.ExecStage.num_transitions_active_to_idle 90 # number of CU transitions from active to idle +system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::samples 90 # duration of idle periods in cycles +system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::mean 29.322222 # duration of idle periods in cycles +system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::stdev 145.995831 # duration of idle periods in cycles system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::underflows 0 0.00% 0.00% # duration of idle periods in cycles -system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::0-4 74 79.57% 79.57% # duration of idle periods in cycles -system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::5-9 7 7.53% 87.10% # duration of idle periods in cycles -system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::10-14 1 1.08% 88.17% # duration of idle periods in cycles -system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::15-19 1 1.08% 89.25% # duration of idle periods in cycles -system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::20-24 2 2.15% 91.40% # duration of idle periods in cycles -system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::25-29 1 1.08% 92.47% # duration of idle periods in cycles -system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::30-34 0 0.00% 92.47% # duration of idle periods in cycles -system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::35-39 0 0.00% 92.47% # duration of idle periods in cycles -system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::40-44 0 0.00% 92.47% # duration of idle periods in cycles -system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::45-49 0 0.00% 92.47% # duration of idle periods in cycles -system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::50-54 0 0.00% 92.47% # duration of idle periods in cycles -system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::55-59 0 0.00% 92.47% # duration of idle periods in cycles -system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::60-64 0 0.00% 92.47% # duration of idle periods in cycles -system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::65-69 0 0.00% 92.47% # duration of idle periods in cycles -system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::70-74 0 0.00% 92.47% # duration of idle periods in cycles -system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::75 0 0.00% 92.47% # duration of idle periods in cycles -system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::overflows 7 7.53% 100.00% # duration of idle periods in cycles +system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::0-4 76 84.44% 84.44% # duration of idle periods in cycles +system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::5-9 7 7.78% 92.22% # duration of idle periods in cycles +system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::10-14 0 0.00% 92.22% # duration of idle periods in cycles +system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::15-19 0 0.00% 92.22% # duration of idle periods in cycles +system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::20-24 0 0.00% 92.22% # duration of idle periods in cycles +system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::25-29 1 1.11% 93.33% # duration of idle periods in cycles +system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::30-34 0 0.00% 93.33% # duration of idle periods in cycles +system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::35-39 0 0.00% 93.33% # duration of idle periods in cycles +system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::40-44 0 0.00% 93.33% # duration of idle periods in cycles +system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::45-49 0 0.00% 93.33% # duration of idle periods in cycles +system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::50-54 0 0.00% 93.33% # duration of idle periods in cycles +system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::55-59 0 0.00% 93.33% # duration of idle periods in cycles +system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::60-64 0 0.00% 93.33% # duration of idle periods in cycles +system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::65-69 0 0.00% 93.33% # duration of idle periods in cycles +system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::70-74 0 0.00% 93.33% # duration of idle periods in cycles +system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::75 0 0.00% 93.33% # duration of idle periods in cycles +system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::overflows 6 6.67% 100.00% # duration of idle periods in cycles system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::min_value 1 # duration of idle periods in cycles system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::max_value 1291 # duration of idle periods in cycles -system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::total 93 # duration of idle periods in cycles +system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::total 90 # duration of idle periods in cycles system.cpu1.CUs0.GlobalMemPipeline.load_vrf_bank_conflict_cycles 0 # total number of cycles GM data are delayed before updating the VRF system.cpu1.CUs0.LocalMemPipeline.load_vrf_bank_conflict_cycles 0 # total number of cycles LDS data are delayed before updating the VRF +system.cpu1.CUs0.valu_insts 68 # Number of vector ALU insts issued. +system.cpu1.CUs0.valu_insts_per_wf 17 # The avg. number of vector ALU insts issued per-wavefront. +system.cpu1.CUs0.salu_insts 0 # Number of scalar ALU insts issued. +system.cpu1.CUs0.salu_insts_per_wf 0 # The avg. number of scalar ALU insts issued per-wavefront. +system.cpu1.CUs0.inst_cycles_valu 68 # Number of cycles needed to execute VALU insts. +system.cpu1.CUs0.inst_cycles_salu 0 # Number of cycles needed to execute SALU insts. +system.cpu1.CUs0.thread_cycles_valu 3076 # Number of thread cycles used to execute vector ALU ops. Similar to instCyclesVALU but multiplied by the number of active threads. +system.cpu1.CUs0.valu_utilization 70.680147 # Percentage of active vector ALU threads in a wave. +system.cpu1.CUs0.lds_no_flat_insts 6 # Number of LDS insts issued, not including FLAT accesses that resolve to LDS. +system.cpu1.CUs0.lds_no_flat_insts_per_wf 1.500000 # The avg. number of LDS insts (not including FLAT accesses that resolve to LDS) per-wavefront. +system.cpu1.CUs0.flat_vmem_insts 0 # The number of FLAT insts that resolve to vmem issued. +system.cpu1.CUs0.flat_vmem_insts_per_wf 0 # The average number of FLAT insts that resolve to vmem issued per-wavefront. +system.cpu1.CUs0.flat_lds_insts 0 # The number of FLAT insts that resolve to LDS issued. +system.cpu1.CUs0.flat_lds_insts_per_wf 0 # The average number of FLAT insts that resolve to LDS issued per-wavefront. +system.cpu1.CUs0.vector_mem_writes 8 # Number of vector mem write insts (excluding FLAT insts). +system.cpu1.CUs0.vector_mem_writes_per_wf 2 # The average number of vector mem write insts (excluding FLAT insts) per-wavefront. +system.cpu1.CUs0.vector_mem_reads 29 # Number of vector mem read insts (excluding FLAT insts). +system.cpu1.CUs0.vector_mem_reads_per_wf 7.250000 # The avg. number of vector mem read insts (excluding FLAT insts) per-wavefront. +system.cpu1.CUs0.scalar_mem_writes 0 # Number of scalar mem write insts. +system.cpu1.CUs0.scalar_mem_writes_per_wf 0 # The average number of scalar mem write insts per-wavefront. +system.cpu1.CUs0.scalar_mem_reads 0 # Number of scalar mem read insts. +system.cpu1.CUs0.scalar_mem_reads_per_wf 0 # The average number of scalar mem read insts per-wavefront. system.cpu1.CUs0.tlb_requests 769 # number of uncoalesced requests -system.cpu1.CUs0.tlb_cycles -455223738000 # total number of cycles for all uncoalesced requests -system.cpu1.CUs0.avg_translation_latency -591968449.934981 # Avg. translation latency for data translations +system.cpu1.CUs0.tlb_cycles -454892896000 # total number of cycles for all uncoalesced requests +system.cpu1.CUs0.avg_translation_latency -591538226.267880 # Avg. translation latency for data translations system.cpu1.CUs0.TLB_hits_distribution::page_table 769 # TLB hits distribution (0 for page table, x for Lx-TLB system.cpu1.CUs0.TLB_hits_distribution::L1_TLB 0 # TLB hits distribution (0 for page table, x for Lx-TLB system.cpu1.CUs0.TLB_hits_distribution::L2_TLB 0 # TLB hits distribution (0 for page table, x for Lx-TLB @@ -1407,23 +1429,23 @@ system.cpu1.CUs0.local_mem_instr_cnt 6 # dy system.cpu1.CUs0.wg_blocked_due_lds_alloc 0 # Workgroup blocked due to LDS capacity system.cpu1.CUs0.num_instr_executed 141 # number of instructions executed system.cpu1.CUs0.inst_exec_rate::samples 141 # Instruction Execution Rate: Number of executed vector instructions per cycle -system.cpu1.CUs0.inst_exec_rate::mean 92.127660 # Instruction Execution Rate: Number of executed vector instructions per cycle -system.cpu1.CUs0.inst_exec_rate::stdev 237.147810 # Instruction Execution Rate: Number of executed vector instructions per cycle +system.cpu1.CUs0.inst_exec_rate::mean 71.028369 # Instruction Execution Rate: Number of executed vector instructions per cycle +system.cpu1.CUs0.inst_exec_rate::stdev 225.061514 # Instruction Execution Rate: Number of executed vector instructions per cycle system.cpu1.CUs0.inst_exec_rate::underflows 0 0.00% 0.00% # Instruction Execution Rate: Number of executed vector instructions per cycle system.cpu1.CUs0.inst_exec_rate::0-1 0 0.00% 0.00% # Instruction Execution Rate: Number of executed vector instructions per cycle system.cpu1.CUs0.inst_exec_rate::2-3 12 8.51% 8.51% # Instruction Execution Rate: Number of executed vector instructions per cycle -system.cpu1.CUs0.inst_exec_rate::4-5 52 36.88% 45.39% # Instruction Execution Rate: Number of executed vector instructions per cycle -system.cpu1.CUs0.inst_exec_rate::6-7 31 21.99% 67.38% # Instruction Execution Rate: Number of executed vector instructions per cycle -system.cpu1.CUs0.inst_exec_rate::8-9 3 2.13% 69.50% # Instruction Execution Rate: Number of executed vector instructions per cycle -system.cpu1.CUs0.inst_exec_rate::10 3 2.13% 71.63% # Instruction Execution Rate: Number of executed vector instructions per cycle -system.cpu1.CUs0.inst_exec_rate::overflows 40 28.37% 100.00% # Instruction Execution Rate: Number of executed vector instructions per cycle +system.cpu1.CUs0.inst_exec_rate::4-5 61 43.26% 51.77% # Instruction Execution Rate: Number of executed vector instructions per cycle +system.cpu1.CUs0.inst_exec_rate::6-7 32 22.70% 74.47% # Instruction Execution Rate: Number of executed vector instructions per cycle +system.cpu1.CUs0.inst_exec_rate::8-9 3 2.13% 76.60% # Instruction Execution Rate: Number of executed vector instructions per cycle +system.cpu1.CUs0.inst_exec_rate::10 3 2.13% 78.72% # Instruction Execution Rate: Number of executed vector instructions per cycle +system.cpu1.CUs0.inst_exec_rate::overflows 30 21.28% 100.00% # Instruction Execution Rate: Number of executed vector instructions per cycle system.cpu1.CUs0.inst_exec_rate::min_value 2 # Instruction Execution Rate: Number of executed vector instructions per cycle system.cpu1.CUs0.inst_exec_rate::max_value 1297 # Instruction Execution Rate: Number of executed vector instructions per cycle system.cpu1.CUs0.inst_exec_rate::total 141 # Instruction Execution Rate: Number of executed vector instructions per cycle system.cpu1.CUs0.num_vec_ops_executed 6769 # number of vec ops executed (e.g. WF size/inst) -system.cpu1.CUs0.num_total_cycles 3570 # number of cycles the CU ran for -system.cpu1.CUs0.vpc 1.896078 # Vector Operations per cycle (this CU only) -system.cpu1.CUs0.ipc 0.039496 # Instructions per cycle (this CU only) +system.cpu1.CUs0.num_total_cycles 2840 # number of cycles the CU ran for +system.cpu1.CUs0.vpc 2.383451 # Vector Operations per cycle (this CU only) +system.cpu1.CUs0.ipc 0.049648 # Instructions per cycle (this CU only) system.cpu1.CUs0.warp_execution_dist::samples 141 # number of lanes active per instruction (oval all instructions) system.cpu1.CUs0.warp_execution_dist::mean 48.007092 # number of lanes active per instruction (oval all instructions) system.cpu1.CUs0.warp_execution_dist::stdev 23.719942 # number of lanes active per instruction (oval all instructions) @@ -1501,10 +1523,10 @@ system.cpu1.CUs0.times_wg_blocked_due_vgpr_alloc 0 system.cpu1.CUs0.num_CAS_ops 0 # number of compare and swap operations system.cpu1.CUs0.num_failed_CAS_ops 0 # number of compare and swap operations that failed system.cpu1.CUs0.num_completed_wfs 4 # number of completed wavefronts -system.cpu1.CUs1.localDataStore.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states +system.cpu1.CUs1.localDataStore.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states system.cpu1.CUs1.wavefronts00.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability system.cpu1.CUs1.wavefronts00.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies -system.cpu1.CUs1.wavefronts00.timesBlockedDueRAWDependencies 591 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs1.wavefronts00.timesBlockedDueRAWDependencies 406 # number of times the wf's instructions are blocked due to RAW dependencies system.cpu1.CUs1.wavefronts00.src_reg_operand_dist::samples 39 # number of executed instructions with N source register operands system.cpu1.CUs1.wavefronts00.src_reg_operand_dist::mean 0.794872 # number of executed instructions with N source register operands system.cpu1.CUs1.wavefronts00.src_reg_operand_dist::stdev 0.863880 # number of executed instructions with N source register operands @@ -1696,7 +1718,7 @@ system.cpu1.CUs1.wavefronts07.dst_reg_operand_dist::max_value 0 system.cpu1.CUs1.wavefronts07.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands system.cpu1.CUs1.wavefronts08.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability system.cpu1.CUs1.wavefronts08.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies -system.cpu1.CUs1.wavefronts08.timesBlockedDueRAWDependencies 562 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs1.wavefronts08.timesBlockedDueRAWDependencies 381 # number of times the wf's instructions are blocked due to RAW dependencies system.cpu1.CUs1.wavefronts08.src_reg_operand_dist::samples 34 # number of executed instructions with N source register operands system.cpu1.CUs1.wavefronts08.src_reg_operand_dist::mean 0.852941 # number of executed instructions with N source register operands system.cpu1.CUs1.wavefronts08.src_reg_operand_dist::stdev 0.857493 # number of executed instructions with N source register operands @@ -1888,7 +1910,7 @@ system.cpu1.CUs1.wavefronts15.dst_reg_operand_dist::max_value 0 system.cpu1.CUs1.wavefronts15.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands system.cpu1.CUs1.wavefronts16.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability system.cpu1.CUs1.wavefronts16.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies -system.cpu1.CUs1.wavefronts16.timesBlockedDueRAWDependencies 561 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs1.wavefronts16.timesBlockedDueRAWDependencies 372 # number of times the wf's instructions are blocked due to RAW dependencies system.cpu1.CUs1.wavefronts16.src_reg_operand_dist::samples 34 # number of executed instructions with N source register operands system.cpu1.CUs1.wavefronts16.src_reg_operand_dist::mean 0.852941 # number of executed instructions with N source register operands system.cpu1.CUs1.wavefronts16.src_reg_operand_dist::stdev 0.857493 # number of executed instructions with N source register operands @@ -2080,7 +2102,7 @@ system.cpu1.CUs1.wavefronts23.dst_reg_operand_dist::max_value 0 system.cpu1.CUs1.wavefronts23.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands system.cpu1.CUs1.wavefronts24.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability system.cpu1.CUs1.wavefronts24.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies -system.cpu1.CUs1.wavefronts24.timesBlockedDueRAWDependencies 551 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs1.wavefronts24.timesBlockedDueRAWDependencies 364 # number of times the wf's instructions are blocked due to RAW dependencies system.cpu1.CUs1.wavefronts24.src_reg_operand_dist::samples 34 # number of executed instructions with N source register operands system.cpu1.CUs1.wavefronts24.src_reg_operand_dist::mean 0.852941 # number of executed instructions with N source register operands system.cpu1.CUs1.wavefronts24.src_reg_operand_dist::stdev 0.857493 # number of executed instructions with N source register operands @@ -2270,27 +2292,27 @@ system.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::overflows 0 system.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands system.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands system.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands -system.cpu1.CUs1.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states -system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::samples 43 # For each instruction fetch request recieved record how many instructions you got from it -system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::mean 5.813953 # For each instruction fetch request recieved record how many instructions you got from it -system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::stdev 2.683777 # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs1.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states +system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::samples 35 # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::mean 11.257143 # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::stdev 5.595917 # For each instruction fetch request recieved record how many instructions you got from it system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::underflows 0 0.00% 0.00% # For each instruction fetch request recieved record how many instructions you got from it system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::1 0 0.00% 0.00% # For each instruction fetch request recieved record how many instructions you got from it -system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::2 8 18.60% 18.60% # For each instruction fetch request recieved record how many instructions you got from it -system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::3 8 18.60% 37.21% # For each instruction fetch request recieved record how many instructions you got from it -system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::4 1 2.33% 39.53% # For each instruction fetch request recieved record how many instructions you got from it -system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::5 0 0.00% 39.53% # For each instruction fetch request recieved record how many instructions you got from it -system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::6 1 2.33% 41.86% # For each instruction fetch request recieved record how many instructions you got from it -system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::7 0 0.00% 41.86% # For each instruction fetch request recieved record how many instructions you got from it -system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::8 25 58.14% 100.00% # For each instruction fetch request recieved record how many instructions you got from it -system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::9 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it -system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::10 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it -system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::11 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it -system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::12 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it -system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::13 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it -system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::14 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it -system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::15 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it -system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::16 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::2 4 11.43% 11.43% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::3 4 11.43% 22.86% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::4 1 2.86% 25.71% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::5 0 0.00% 25.71% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::6 0 0.00% 25.71% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::7 0 0.00% 25.71% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::8 0 0.00% 25.71% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::9 0 0.00% 25.71% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::10 4 11.43% 37.14% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::11 4 11.43% 48.57% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::12 0 0.00% 48.57% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::13 0 0.00% 48.57% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::14 1 2.86% 51.43% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::15 0 0.00% 51.43% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::16 17 48.57% 100.00% # For each instruction fetch request recieved record how many instructions you got from it system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::17 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::18 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::19 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it @@ -2309,67 +2331,89 @@ system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::31 0 0.00 system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::32 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::overflows 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::min_value 2 # For each instruction fetch request recieved record how many instructions you got from it -system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::max_value 8 # For each instruction fetch request recieved record how many instructions you got from it -system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::total 43 # For each instruction fetch request recieved record how many instructions you got from it -system.cpu1.CUs1.ExecStage.num_cycles_with_no_issue 3471 # number of cycles the CU issues nothing -system.cpu1.CUs1.ExecStage.num_cycles_with_instr_issued 99 # number of cycles the CU issued at least one instruction +system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::max_value 16 # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::total 35 # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs1.ExecStage.num_cycles_with_no_issue 2740 # number of cycles the CU issues nothing +system.cpu1.CUs1.ExecStage.num_cycles_with_instr_issued 100 # number of cycles the CU issued at least one instruction system.cpu1.CUs1.ExecStage.num_cycles_with_instrtype_issue::ALU0 30 # Number of cycles at least one instruction of specific type issued system.cpu1.CUs1.ExecStage.num_cycles_with_instrtype_issue::ALU1 29 # Number of cycles at least one instruction of specific type issued system.cpu1.CUs1.ExecStage.num_cycles_with_instrtype_issue::ALU2 29 # Number of cycles at least one instruction of specific type issued system.cpu1.CUs1.ExecStage.num_cycles_with_instrtype_issue::ALU3 29 # Number of cycles at least one instruction of specific type issued system.cpu1.CUs1.ExecStage.num_cycles_with_instrtype_issue::GM 18 # Number of cycles at least one instruction of specific type issued system.cpu1.CUs1.ExecStage.num_cycles_with_instrtype_issue::LM 6 # Number of cycles at least one instruction of specific type issued -system.cpu1.CUs1.ExecStage.num_cycles_with_instr_type_no_issue::ALU0 973 # Number of cycles no instruction of specific type issued -system.cpu1.CUs1.ExecStage.num_cycles_with_instr_type_no_issue::ALU1 662 # Number of cycles no instruction of specific type issued -system.cpu1.CUs1.ExecStage.num_cycles_with_instr_type_no_issue::ALU2 634 # Number of cycles no instruction of specific type issued -system.cpu1.CUs1.ExecStage.num_cycles_with_instr_type_no_issue::ALU3 606 # Number of cycles no instruction of specific type issued -system.cpu1.CUs1.ExecStage.num_cycles_with_instr_type_no_issue::GM 404 # Number of cycles no instruction of specific type issued +system.cpu1.CUs1.ExecStage.num_cycles_with_instr_type_no_issue::ALU0 795 # Number of cycles no instruction of specific type issued +system.cpu1.CUs1.ExecStage.num_cycles_with_instr_type_no_issue::ALU1 437 # Number of cycles no instruction of specific type issued +system.cpu1.CUs1.ExecStage.num_cycles_with_instr_type_no_issue::ALU2 431 # Number of cycles no instruction of specific type issued +system.cpu1.CUs1.ExecStage.num_cycles_with_instr_type_no_issue::ALU3 422 # Number of cycles no instruction of specific type issued +system.cpu1.CUs1.ExecStage.num_cycles_with_instr_type_no_issue::GM 408 # Number of cycles no instruction of specific type issued system.cpu1.CUs1.ExecStage.num_cycles_with_instr_type_no_issue::LM 22 # Number of cycles no instruction of specific type issued -system.cpu1.CUs1.ExecStage.spc::samples 3570 # Execution units active per cycle (Exec unit=SIMD,MemPipe) -system.cpu1.CUs1.ExecStage.spc::mean 0.039496 # Execution units active per cycle (Exec unit=SIMD,MemPipe) -system.cpu1.CUs1.ExecStage.spc::stdev 0.249084 # Execution units active per cycle (Exec unit=SIMD,MemPipe) +system.cpu1.CUs1.ExecStage.spc::samples 2840 # Execution units active per cycle (Exec unit=SIMD,MemPipe) +system.cpu1.CUs1.ExecStage.spc::mean 0.049648 # Execution units active per cycle (Exec unit=SIMD,MemPipe) +system.cpu1.CUs1.ExecStage.spc::stdev 0.275831 # Execution units active per cycle (Exec unit=SIMD,MemPipe) system.cpu1.CUs1.ExecStage.spc::underflows 0 0.00% 0.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe) -system.cpu1.CUs1.ExecStage.spc::0 3471 97.23% 97.23% # Execution units active per cycle (Exec unit=SIMD,MemPipe) -system.cpu1.CUs1.ExecStage.spc::1 58 1.62% 98.85% # Execution units active per cycle (Exec unit=SIMD,MemPipe) -system.cpu1.CUs1.ExecStage.spc::2 40 1.12% 99.97% # Execution units active per cycle (Exec unit=SIMD,MemPipe) -system.cpu1.CUs1.ExecStage.spc::3 1 0.03% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe) +system.cpu1.CUs1.ExecStage.spc::0 2740 96.48% 96.48% # Execution units active per cycle (Exec unit=SIMD,MemPipe) +system.cpu1.CUs1.ExecStage.spc::1 59 2.08% 98.56% # Execution units active per cycle (Exec unit=SIMD,MemPipe) +system.cpu1.CUs1.ExecStage.spc::2 41 1.44% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe) +system.cpu1.CUs1.ExecStage.spc::3 0 0.00% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe) system.cpu1.CUs1.ExecStage.spc::4 0 0.00% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe) system.cpu1.CUs1.ExecStage.spc::5 0 0.00% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe) system.cpu1.CUs1.ExecStage.spc::6 0 0.00% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe) system.cpu1.CUs1.ExecStage.spc::overflows 0 0.00% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe) system.cpu1.CUs1.ExecStage.spc::min_value 0 # Execution units active per cycle (Exec unit=SIMD,MemPipe) -system.cpu1.CUs1.ExecStage.spc::max_value 3 # Execution units active per cycle (Exec unit=SIMD,MemPipe) -system.cpu1.CUs1.ExecStage.spc::total 3570 # Execution units active per cycle (Exec unit=SIMD,MemPipe) -system.cpu1.CUs1.ExecStage.num_transitions_active_to_idle 94 # number of CU transitions from active to idle -system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::samples 94 # duration of idle periods in cycles -system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::mean 35.776596 # duration of idle periods in cycles -system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::stdev 153.908027 # duration of idle periods in cycles +system.cpu1.CUs1.ExecStage.spc::max_value 2 # Execution units active per cycle (Exec unit=SIMD,MemPipe) +system.cpu1.CUs1.ExecStage.spc::total 2840 # Execution units active per cycle (Exec unit=SIMD,MemPipe) +system.cpu1.CUs1.ExecStage.num_transitions_active_to_idle 91 # number of CU transitions from active to idle +system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::samples 91 # duration of idle periods in cycles +system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::mean 30.010989 # duration of idle periods in cycles +system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::stdev 148.108031 # duration of idle periods in cycles system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::underflows 0 0.00% 0.00% # duration of idle periods in cycles -system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::0-4 75 79.79% 79.79% # duration of idle periods in cycles -system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::5-9 8 8.51% 88.30% # duration of idle periods in cycles -system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::10-14 0 0.00% 88.30% # duration of idle periods in cycles -system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::15-19 1 1.06% 89.36% # duration of idle periods in cycles -system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::20-24 2 2.13% 91.49% # duration of idle periods in cycles -system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::25-29 1 1.06% 92.55% # duration of idle periods in cycles -system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::30-34 0 0.00% 92.55% # duration of idle periods in cycles -system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::35-39 0 0.00% 92.55% # duration of idle periods in cycles -system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::40-44 0 0.00% 92.55% # duration of idle periods in cycles -system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::45-49 0 0.00% 92.55% # duration of idle periods in cycles -system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::50-54 0 0.00% 92.55% # duration of idle periods in cycles -system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::55-59 0 0.00% 92.55% # duration of idle periods in cycles -system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::60-64 0 0.00% 92.55% # duration of idle periods in cycles -system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::65-69 0 0.00% 92.55% # duration of idle periods in cycles -system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::70-74 0 0.00% 92.55% # duration of idle periods in cycles -system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::75 0 0.00% 92.55% # duration of idle periods in cycles -system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::overflows 7 7.45% 100.00% # duration of idle periods in cycles +system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::0-4 76 83.52% 83.52% # duration of idle periods in cycles +system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::5-9 8 8.79% 92.31% # duration of idle periods in cycles +system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::10-14 0 0.00% 92.31% # duration of idle periods in cycles +system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::15-19 0 0.00% 92.31% # duration of idle periods in cycles +system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::20-24 0 0.00% 92.31% # duration of idle periods in cycles +system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::25-29 1 1.10% 93.41% # duration of idle periods in cycles +system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::30-34 0 0.00% 93.41% # duration of idle periods in cycles +system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::35-39 0 0.00% 93.41% # duration of idle periods in cycles +system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::40-44 0 0.00% 93.41% # duration of idle periods in cycles +system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::45-49 0 0.00% 93.41% # duration of idle periods in cycles +system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::50-54 0 0.00% 93.41% # duration of idle periods in cycles +system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::55-59 0 0.00% 93.41% # duration of idle periods in cycles +system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::60-64 0 0.00% 93.41% # duration of idle periods in cycles +system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::65-69 0 0.00% 93.41% # duration of idle periods in cycles +system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::70-74 0 0.00% 93.41% # duration of idle periods in cycles +system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::75 0 0.00% 93.41% # duration of idle periods in cycles +system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::overflows 6 6.59% 100.00% # duration of idle periods in cycles system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::min_value 1 # duration of idle periods in cycles system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::max_value 1299 # duration of idle periods in cycles -system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::total 94 # duration of idle periods in cycles +system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::total 91 # duration of idle periods in cycles system.cpu1.CUs1.GlobalMemPipeline.load_vrf_bank_conflict_cycles 0 # total number of cycles GM data are delayed before updating the VRF system.cpu1.CUs1.LocalMemPipeline.load_vrf_bank_conflict_cycles 0 # total number of cycles LDS data are delayed before updating the VRF +system.cpu1.CUs1.valu_insts 68 # Number of vector ALU insts issued. +system.cpu1.CUs1.valu_insts_per_wf 17 # The avg. number of vector ALU insts issued per-wavefront. +system.cpu1.CUs1.salu_insts 0 # Number of scalar ALU insts issued. +system.cpu1.CUs1.salu_insts_per_wf 0 # The avg. number of scalar ALU insts issued per-wavefront. +system.cpu1.CUs1.inst_cycles_valu 68 # Number of cycles needed to execute VALU insts. +system.cpu1.CUs1.inst_cycles_salu 0 # Number of cycles needed to execute SALU insts. +system.cpu1.CUs1.thread_cycles_valu 3071 # Number of thread cycles used to execute vector ALU ops. Similar to instCyclesVALU but multiplied by the number of active threads. +system.cpu1.CUs1.valu_utilization 70.565257 # Percentage of active vector ALU threads in a wave. +system.cpu1.CUs1.lds_no_flat_insts 6 # Number of LDS insts issued, not including FLAT accesses that resolve to LDS. +system.cpu1.CUs1.lds_no_flat_insts_per_wf 1.500000 # The avg. number of LDS insts (not including FLAT accesses that resolve to LDS) per-wavefront. +system.cpu1.CUs1.flat_vmem_insts 0 # The number of FLAT insts that resolve to vmem issued. +system.cpu1.CUs1.flat_vmem_insts_per_wf 0 # The average number of FLAT insts that resolve to vmem issued per-wavefront. +system.cpu1.CUs1.flat_lds_insts 0 # The number of FLAT insts that resolve to LDS issued. +system.cpu1.CUs1.flat_lds_insts_per_wf 0 # The average number of FLAT insts that resolve to LDS issued per-wavefront. +system.cpu1.CUs1.vector_mem_writes 8 # Number of vector mem write insts (excluding FLAT insts). +system.cpu1.CUs1.vector_mem_writes_per_wf 2 # The average number of vector mem write insts (excluding FLAT insts) per-wavefront. +system.cpu1.CUs1.vector_mem_reads 29 # Number of vector mem read insts (excluding FLAT insts). +system.cpu1.CUs1.vector_mem_reads_per_wf 7.250000 # The avg. number of vector mem read insts (excluding FLAT insts) per-wavefront. +system.cpu1.CUs1.scalar_mem_writes 0 # Number of scalar mem write insts. +system.cpu1.CUs1.scalar_mem_writes_per_wf 0 # The average number of scalar mem write insts per-wavefront. +system.cpu1.CUs1.scalar_mem_reads 0 # Number of scalar mem read insts. +system.cpu1.CUs1.scalar_mem_reads_per_wf 0 # The average number of scalar mem read insts per-wavefront. system.cpu1.CUs1.tlb_requests 769 # number of uncoalesced requests -system.cpu1.CUs1.tlb_cycles -455230572000 # total number of cycles for all uncoalesced requests -system.cpu1.CUs1.avg_translation_latency -591977336.801040 # Avg. translation latency for data translations +system.cpu1.CUs1.tlb_cycles -454919630000 # total number of cycles for all uncoalesced requests +system.cpu1.CUs1.avg_translation_latency -591572990.897269 # Avg. translation latency for data translations system.cpu1.CUs1.TLB_hits_distribution::page_table 769 # TLB hits distribution (0 for page table, x for Lx-TLB system.cpu1.CUs1.TLB_hits_distribution::L1_TLB 0 # TLB hits distribution (0 for page table, x for Lx-TLB system.cpu1.CUs1.TLB_hits_distribution::L2_TLB 0 # TLB hits distribution (0 for page table, x for Lx-TLB @@ -2445,23 +2489,23 @@ system.cpu1.CUs1.local_mem_instr_cnt 6 # dy system.cpu1.CUs1.wg_blocked_due_lds_alloc 0 # Workgroup blocked due to LDS capacity system.cpu1.CUs1.num_instr_executed 141 # number of instructions executed system.cpu1.CUs1.inst_exec_rate::samples 141 # Instruction Execution Rate: Number of executed vector instructions per cycle -system.cpu1.CUs1.inst_exec_rate::mean 91.269504 # Instruction Execution Rate: Number of executed vector instructions per cycle -system.cpu1.CUs1.inst_exec_rate::stdev 240.230451 # Instruction Execution Rate: Number of executed vector instructions per cycle +system.cpu1.CUs1.inst_exec_rate::mean 72.113475 # Instruction Execution Rate: Number of executed vector instructions per cycle +system.cpu1.CUs1.inst_exec_rate::stdev 228.065470 # Instruction Execution Rate: Number of executed vector instructions per cycle system.cpu1.CUs1.inst_exec_rate::underflows 0 0.00% 0.00% # Instruction Execution Rate: Number of executed vector instructions per cycle system.cpu1.CUs1.inst_exec_rate::0-1 0 0.00% 0.00% # Instruction Execution Rate: Number of executed vector instructions per cycle system.cpu1.CUs1.inst_exec_rate::2-3 13 9.22% 9.22% # Instruction Execution Rate: Number of executed vector instructions per cycle -system.cpu1.CUs1.inst_exec_rate::4-5 52 36.88% 46.10% # Instruction Execution Rate: Number of executed vector instructions per cycle -system.cpu1.CUs1.inst_exec_rate::6-7 33 23.40% 69.50% # Instruction Execution Rate: Number of executed vector instructions per cycle -system.cpu1.CUs1.inst_exec_rate::8-9 6 4.26% 73.76% # Instruction Execution Rate: Number of executed vector instructions per cycle -system.cpu1.CUs1.inst_exec_rate::10 0 0.00% 73.76% # Instruction Execution Rate: Number of executed vector instructions per cycle -system.cpu1.CUs1.inst_exec_rate::overflows 37 26.24% 100.00% # Instruction Execution Rate: Number of executed vector instructions per cycle +system.cpu1.CUs1.inst_exec_rate::4-5 60 42.55% 51.77% # Instruction Execution Rate: Number of executed vector instructions per cycle +system.cpu1.CUs1.inst_exec_rate::6-7 34 24.11% 75.89% # Instruction Execution Rate: Number of executed vector instructions per cycle +system.cpu1.CUs1.inst_exec_rate::8-9 3 2.13% 78.01% # Instruction Execution Rate: Number of executed vector instructions per cycle +system.cpu1.CUs1.inst_exec_rate::10 1 0.71% 78.72% # Instruction Execution Rate: Number of executed vector instructions per cycle +system.cpu1.CUs1.inst_exec_rate::overflows 30 21.28% 100.00% # Instruction Execution Rate: Number of executed vector instructions per cycle system.cpu1.CUs1.inst_exec_rate::min_value 2 # Instruction Execution Rate: Number of executed vector instructions per cycle system.cpu1.CUs1.inst_exec_rate::max_value 1305 # Instruction Execution Rate: Number of executed vector instructions per cycle system.cpu1.CUs1.inst_exec_rate::total 141 # Instruction Execution Rate: Number of executed vector instructions per cycle system.cpu1.CUs1.num_vec_ops_executed 6762 # number of vec ops executed (e.g. WF size/inst) -system.cpu1.CUs1.num_total_cycles 3570 # number of cycles the CU ran for -system.cpu1.CUs1.vpc 1.894118 # Vector Operations per cycle (this CU only) -system.cpu1.CUs1.ipc 0.039496 # Instructions per cycle (this CU only) +system.cpu1.CUs1.num_total_cycles 2840 # number of cycles the CU ran for +system.cpu1.CUs1.vpc 2.380986 # Vector Operations per cycle (this CU only) +system.cpu1.CUs1.ipc 0.049648 # Instructions per cycle (this CU only) system.cpu1.CUs1.warp_execution_dist::samples 141 # number of lanes active per instruction (oval all instructions) system.cpu1.CUs1.warp_execution_dist::mean 47.957447 # number of lanes active per instruction (oval all instructions) system.cpu1.CUs1.warp_execution_dist::stdev 23.818022 # number of lanes active per instruction (oval all instructions) @@ -2539,20 +2583,20 @@ system.cpu1.CUs1.times_wg_blocked_due_vgpr_alloc 0 system.cpu1.CUs1.num_CAS_ops 0 # number of compare and swap operations system.cpu1.CUs1.num_failed_CAS_ops 0 # number of compare and swap operations that failed system.cpu1.CUs1.num_completed_wfs 4 # number of completed wavefronts -system.cpu1.CUs0.ldsBus.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states -system.cpu1.CUs1.ldsBus.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states -system.cpu2.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states +system.cpu1.CUs0.ldsBus.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states +system.cpu1.CUs1.ldsBus.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states +system.cpu2.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states system.cpu2.num_kernel_launched 1 # number of kernel launched system.dir_cntrl0.L3CacheMemory.demand_hits 0 # Number of cache demand hits system.dir_cntrl0.L3CacheMemory.demand_misses 0 # Number of cache demand misses system.dir_cntrl0.L3CacheMemory.demand_accesses 0 # Number of cache demand accesses -system.dir_cntrl0.L3CacheMemory.num_data_array_writes 1551 # number of data array writes -system.dir_cntrl0.L3CacheMemory.num_tag_array_reads 1551 # number of tag array reads -system.dir_cntrl0.L3CacheMemory.num_tag_array_writes 1551 # number of tag array writes -system.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states +system.dir_cntrl0.L3CacheMemory.num_data_array_writes 1549 # number of data array writes +system.dir_cntrl0.L3CacheMemory.num_tag_array_reads 1549 # number of tag array reads +system.dir_cntrl0.L3CacheMemory.num_tag_array_writes 1549 # number of tag array writes +system.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states system.dispatcher_coalescer.clk_domain.voltage_domain.voltage 1 # Voltage in Volts system.dispatcher_coalescer.clk_domain.clock 1000 # Clock period in ticks -system.dispatcher_coalescer.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states +system.dispatcher_coalescer.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states system.dispatcher_coalescer.uncoalesced_accesses 0 # Number of uncoalesced TLB accesses system.dispatcher_coalescer.coalesced_accesses 0 # Number of coalesced TLB accesses system.dispatcher_coalescer.queuing_cycles 0 # Number of cycles spent in queue @@ -2560,7 +2604,7 @@ system.dispatcher_coalescer.local_queuing_cycles 0 system.dispatcher_coalescer.local_latency nan # Avg. latency over all incoming pkts system.dispatcher_tlb.clk_domain.voltage_domain.voltage 1 # Voltage in Volts system.dispatcher_tlb.clk_domain.clock 1000 # Clock period in ticks -system.dispatcher_tlb.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states +system.dispatcher_tlb.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states system.dispatcher_tlb.local_TLB_accesses 0 # Number of TLB accesses system.dispatcher_tlb.local_TLB_hits 0 # Number of TLB hits system.dispatcher_tlb.local_TLB_misses 0 # Number of TLB misses @@ -2577,7 +2621,7 @@ system.dispatcher_tlb.local_latency nan # Av system.dispatcher_tlb.avg_reuse_distance 0 # avg. reuse distance over all pages (in ticks) system.l1_coalescer0.clk_domain.voltage_domain.voltage 1 # Voltage in Volts system.l1_coalescer0.clk_domain.clock 1000 # Clock period in ticks -system.l1_coalescer0.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states +system.l1_coalescer0.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states system.l1_coalescer0.uncoalesced_accesses 778 # Number of uncoalesced TLB accesses system.l1_coalescer0.coalesced_accesses 0 # Number of coalesced TLB accesses system.l1_coalescer0.queuing_cycles 0 # Number of cycles spent in queue @@ -2585,7 +2629,7 @@ system.l1_coalescer0.local_queuing_cycles 0 # N system.l1_coalescer0.local_latency 0 # Avg. latency over all incoming pkts system.l1_coalescer1.clk_domain.voltage_domain.voltage 1 # Voltage in Volts system.l1_coalescer1.clk_domain.clock 1000 # Clock period in ticks -system.l1_coalescer1.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states +system.l1_coalescer1.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states system.l1_coalescer1.uncoalesced_accesses 769 # Number of uncoalesced TLB accesses system.l1_coalescer1.coalesced_accesses 0 # Number of coalesced TLB accesses system.l1_coalescer1.queuing_cycles 0 # Number of cycles spent in queue @@ -2593,7 +2637,7 @@ system.l1_coalescer1.local_queuing_cycles 0 # N system.l1_coalescer1.local_latency 0 # Avg. latency over all incoming pkts system.l1_tlb0.clk_domain.voltage_domain.voltage 1 # Voltage in Volts system.l1_tlb0.clk_domain.clock 1000 # Clock period in ticks -system.l1_tlb0.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states +system.l1_tlb0.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states system.l1_tlb0.local_TLB_accesses 778 # Number of TLB accesses system.l1_tlb0.local_TLB_hits 774 # Number of TLB hits system.l1_tlb0.local_TLB_misses 4 # Number of TLB misses @@ -2610,7 +2654,7 @@ system.l1_tlb0.local_latency 0 # Av system.l1_tlb0.avg_reuse_distance 0 # avg. reuse distance over all pages (in ticks) system.l1_tlb1.clk_domain.voltage_domain.voltage 1 # Voltage in Volts system.l1_tlb1.clk_domain.clock 1000 # Clock period in ticks -system.l1_tlb1.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states +system.l1_tlb1.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states system.l1_tlb1.local_TLB_accesses 769 # Number of TLB accesses system.l1_tlb1.local_TLB_hits 766 # Number of TLB hits system.l1_tlb1.local_TLB_misses 3 # Number of TLB misses @@ -2627,7 +2671,7 @@ system.l1_tlb1.local_latency 0 # Av system.l1_tlb1.avg_reuse_distance 0 # avg. reuse distance over all pages (in ticks) system.l2_coalescer.clk_domain.voltage_domain.voltage 1 # Voltage in Volts system.l2_coalescer.clk_domain.clock 1000 # Clock period in ticks -system.l2_coalescer.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states +system.l2_coalescer.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states system.l2_coalescer.uncoalesced_accesses 8 # Number of uncoalesced TLB accesses system.l2_coalescer.coalesced_accesses 1 # Number of coalesced TLB accesses system.l2_coalescer.queuing_cycles 8000 # Number of cycles spent in queue @@ -2635,7 +2679,7 @@ system.l2_coalescer.local_queuing_cycles 1000 # Nu system.l2_coalescer.local_latency 125 # Avg. latency over all incoming pkts system.l2_tlb.clk_domain.voltage_domain.voltage 1 # Voltage in Volts system.l2_tlb.clk_domain.clock 1000 # Clock period in ticks -system.l2_tlb.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states +system.l2_tlb.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states system.l2_tlb.local_TLB_accesses 8 # Number of TLB accesses system.l2_tlb.local_TLB_hits 3 # Number of TLB hits system.l2_tlb.local_TLB_misses 5 # Number of TLB misses @@ -2652,7 +2696,7 @@ system.l2_tlb.local_latency 8625.125000 # Av system.l2_tlb.avg_reuse_distance 0 # avg. reuse distance over all pages (in ticks) system.l3_coalescer.clk_domain.voltage_domain.voltage 1 # Voltage in Volts system.l3_coalescer.clk_domain.clock 1000 # Clock period in ticks -system.l3_coalescer.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states +system.l3_coalescer.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states system.l3_coalescer.uncoalesced_accesses 5 # Number of uncoalesced TLB accesses system.l3_coalescer.coalesced_accesses 1 # Number of coalesced TLB accesses system.l3_coalescer.queuing_cycles 8000 # Number of cycles spent in queue @@ -2660,7 +2704,7 @@ system.l3_coalescer.local_queuing_cycles 1000 # Nu system.l3_coalescer.local_latency 200 # Avg. latency over all incoming pkts system.l3_tlb.clk_domain.voltage_domain.voltage 1 # Voltage in Volts system.l3_tlb.clk_domain.clock 1000 # Clock period in ticks -system.l3_tlb.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states +system.l3_tlb.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states system.l3_tlb.local_TLB_accesses 5 # Number of TLB accesses system.l3_tlb.local_TLB_hits 0 # Number of TLB hits system.l3_tlb.local_TLB_misses 5 # Number of TLB misses @@ -2675,7 +2719,7 @@ system.l3_tlb.unique_pages 5 # Nu system.l3_tlb.local_cycles 150000 # Number of cycles spent in queue for all incoming reqs system.l3_tlb.local_latency 30000 # Avg. latency over incoming coalesced reqs system.l3_tlb.avg_reuse_distance 0 # avg. reuse distance over all pages (in ticks) -system.piobus.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states +system.piobus.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states system.piobus.trans_dist::WriteReq 94 # Transaction distribution system.piobus.trans_dist::WriteResp 94 # Transaction distribution system.piobus.pkt_count_system.cp_cntrl0.sequencer.mem-master-port::system.cpu2.pio 188 # Packet count per connected master and slave (bytes) @@ -2686,47 +2730,47 @@ system.piobus.reqLayer0.occupancy 188000 # La system.piobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.piobus.respLayer0.occupancy 94000 # Layer occupancy (ticks) system.piobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.ruby.network.ext_links0.int_node.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states -system.ruby.network.ext_links0.int_node.percent_links_utilized 0.007896 -system.ruby.network.ext_links0.int_node.msg_count.Control::0 1551 -system.ruby.network.ext_links0.int_node.msg_count.Request_Control::0 1551 -system.ruby.network.ext_links0.int_node.msg_count.Response_Data::2 1563 -system.ruby.network.ext_links0.int_node.msg_count.Response_Control::2 1539 -system.ruby.network.ext_links0.int_node.msg_count.Unblock_Control::4 1551 -system.ruby.network.ext_links0.int_node.msg_bytes.Control::0 12408 -system.ruby.network.ext_links0.int_node.msg_bytes.Request_Control::0 12408 -system.ruby.network.ext_links0.int_node.msg_bytes.Response_Data::2 112536 -system.ruby.network.ext_links0.int_node.msg_bytes.Response_Control::2 12312 -system.ruby.network.ext_links0.int_node.msg_bytes.Unblock_Control::4 12408 -system.ruby.network.ext_links1.int_node.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states -system.ruby.network.ext_links1.int_node.percent_links_utilized 0.009900 -system.ruby.network.ext_links1.int_node.msg_count.Control::0 16 +system.ruby.network.ext_links0.int_node.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states +system.ruby.network.ext_links0.int_node.percent_links_utilized 0.007895 +system.ruby.network.ext_links0.int_node.msg_count.Control::0 1549 +system.ruby.network.ext_links0.int_node.msg_count.Request_Control::0 1549 +system.ruby.network.ext_links0.int_node.msg_count.Response_Data::2 1561 +system.ruby.network.ext_links0.int_node.msg_count.Response_Control::2 1537 +system.ruby.network.ext_links0.int_node.msg_count.Unblock_Control::4 1549 +system.ruby.network.ext_links0.int_node.msg_bytes.Control::0 12392 +system.ruby.network.ext_links0.int_node.msg_bytes.Request_Control::0 12392 +system.ruby.network.ext_links0.int_node.msg_bytes.Response_Data::2 112392 +system.ruby.network.ext_links0.int_node.msg_bytes.Response_Control::2 12296 +system.ruby.network.ext_links0.int_node.msg_bytes.Unblock_Control::4 12392 +system.ruby.network.ext_links1.int_node.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states +system.ruby.network.ext_links1.int_node.percent_links_utilized 0.009908 +system.ruby.network.ext_links1.int_node.msg_count.Control::0 14 system.ruby.network.ext_links1.int_node.msg_count.Request_Control::0 1535 system.ruby.network.ext_links1.int_node.msg_count.Response_Data::2 1537 -system.ruby.network.ext_links1.int_node.msg_count.Response_Control::2 14 +system.ruby.network.ext_links1.int_node.msg_count.Response_Control::2 12 system.ruby.network.ext_links1.int_node.msg_count.Unblock_Control::4 1535 -system.ruby.network.ext_links1.int_node.msg_bytes.Control::0 128 +system.ruby.network.ext_links1.int_node.msg_bytes.Control::0 112 system.ruby.network.ext_links1.int_node.msg_bytes.Request_Control::0 12280 system.ruby.network.ext_links1.int_node.msg_bytes.Response_Data::2 110664 -system.ruby.network.ext_links1.int_node.msg_bytes.Response_Control::2 112 +system.ruby.network.ext_links1.int_node.msg_bytes.Response_Control::2 96 system.ruby.network.ext_links1.int_node.msg_bytes.Unblock_Control::4 12280 system.tcp_cntrl0.L1cache.demand_hits 0 # Number of cache demand hits system.tcp_cntrl0.L1cache.demand_misses 0 # Number of cache demand misses system.tcp_cntrl0.L1cache.demand_accesses 0 # Number of cache demand accesses -system.tcp_cntrl0.L1cache.num_data_array_reads 9 # number of data array reads +system.tcp_cntrl0.L1cache.num_data_array_reads 8 # number of data array reads system.tcp_cntrl0.L1cache.num_data_array_writes 11 # number of data array writes system.tcp_cntrl0.L1cache.num_tag_array_reads 26 # number of tag array reads system.tcp_cntrl0.L1cache.num_tag_array_writes 18 # number of tag array writes -system.tcp_cntrl0.L1cache.num_data_array_stalls 2 # number of stalls caused by data array -system.tcp_cntrl0.coalescer.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states +system.tcp_cntrl0.L1cache.num_data_array_stalls 6 # number of stalls caused by data array +system.tcp_cntrl0.coalescer.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states system.tcp_cntrl0.coalescer.gpu_tcp_ld_hits 2 # loads that hit in the TCP system.tcp_cntrl0.coalescer.gpu_tcp_ld_transfers 0 # TCP to TCP load transfers system.tcp_cntrl0.coalescer.gpu_tcc_ld_hits 0 # loads that hit in the TCC system.tcp_cntrl0.coalescer.gpu_ld_misses 2 # loads that miss in the GPU system.tcp_cntrl0.coalescer.gpu_tcp_st_hits 4 # stores that hit in the TCP -system.tcp_cntrl0.coalescer.gpu_tcp_st_transfers 1 # TCP to TCP store transfers +system.tcp_cntrl0.coalescer.gpu_tcp_st_transfers 0 # TCP to TCP store transfers system.tcp_cntrl0.coalescer.gpu_tcc_st_hits 0 # stores that hit in the TCC -system.tcp_cntrl0.coalescer.gpu_st_misses 4 # stores that miss in the GPU +system.tcp_cntrl0.coalescer.gpu_st_misses 5 # stores that miss in the GPU system.tcp_cntrl0.coalescer.cp_tcp_ld_hits 0 # loads that hit in the TCP system.tcp_cntrl0.coalescer.cp_tcp_ld_transfers 0 # TCP to TCP load transfers system.tcp_cntrl0.coalescer.cp_tcc_ld_hits 0 # loads that hit in the TCC @@ -2735,46 +2779,46 @@ system.tcp_cntrl0.coalescer.cp_tcp_st_hits 0 # system.tcp_cntrl0.coalescer.cp_tcp_st_transfers 0 # TCP to TCP store transfers system.tcp_cntrl0.coalescer.cp_tcc_st_hits 0 # stores that hit in the TCC system.tcp_cntrl0.coalescer.cp_st_misses 0 # stores that miss in the GPU -system.tcp_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states -system.tcp_cntrl0.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states -system.ruby.network.ext_links2.int_node.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states -system.ruby.network.ext_links2.int_node.percent_links_utilized 0.000716 +system.tcp_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states +system.tcp_cntrl0.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states +system.ruby.network.ext_links2.int_node.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states +system.ruby.network.ext_links2.int_node.percent_links_utilized 0.000708 system.ruby.network.ext_links2.int_node.msg_count.Control::0 1535 system.ruby.network.ext_links2.int_node.msg_count.Control::1 14 -system.ruby.network.ext_links2.int_node.msg_count.Request_Control::0 16 -system.ruby.network.ext_links2.int_node.msg_count.Request_Control::1 19 -system.ruby.network.ext_links2.int_node.msg_count.Response_Data::2 26 -system.ruby.network.ext_links2.int_node.msg_count.Response_Data::3 33 +system.ruby.network.ext_links2.int_node.msg_count.Request_Control::0 14 +system.ruby.network.ext_links2.int_node.msg_count.Request_Control::1 17 +system.ruby.network.ext_links2.int_node.msg_count.Response_Data::2 24 +system.ruby.network.ext_links2.int_node.msg_count.Response_Data::3 31 system.ruby.network.ext_links2.int_node.msg_count.Response_Control::2 1525 -system.ruby.network.ext_links2.int_node.msg_count.Unblock_Control::4 16 -system.ruby.network.ext_links2.int_node.msg_count.Unblock_Control::5 19 +system.ruby.network.ext_links2.int_node.msg_count.Unblock_Control::4 14 +system.ruby.network.ext_links2.int_node.msg_count.Unblock_Control::5 17 system.ruby.network.ext_links2.int_node.msg_bytes.Control::0 12280 system.ruby.network.ext_links2.int_node.msg_bytes.Control::1 112 -system.ruby.network.ext_links2.int_node.msg_bytes.Request_Control::0 128 -system.ruby.network.ext_links2.int_node.msg_bytes.Request_Control::1 152 -system.ruby.network.ext_links2.int_node.msg_bytes.Response_Data::2 1872 -system.ruby.network.ext_links2.int_node.msg_bytes.Response_Data::3 2376 +system.ruby.network.ext_links2.int_node.msg_bytes.Request_Control::0 112 +system.ruby.network.ext_links2.int_node.msg_bytes.Request_Control::1 136 +system.ruby.network.ext_links2.int_node.msg_bytes.Response_Data::2 1728 +system.ruby.network.ext_links2.int_node.msg_bytes.Response_Data::3 2232 system.ruby.network.ext_links2.int_node.msg_bytes.Response_Control::2 12200 -system.ruby.network.ext_links2.int_node.msg_bytes.Unblock_Control::4 128 -system.ruby.network.ext_links2.int_node.msg_bytes.Unblock_Control::5 152 +system.ruby.network.ext_links2.int_node.msg_bytes.Unblock_Control::4 112 +system.ruby.network.ext_links2.int_node.msg_bytes.Unblock_Control::5 136 system.tcp_cntrl1.L1cache.demand_hits 0 # Number of cache demand hits system.tcp_cntrl1.L1cache.demand_misses 0 # Number of cache demand misses system.tcp_cntrl1.L1cache.demand_accesses 0 # Number of cache demand accesses -system.tcp_cntrl1.L1cache.num_data_array_reads 7 # number of data array reads +system.tcp_cntrl1.L1cache.num_data_array_reads 8 # number of data array reads system.tcp_cntrl1.L1cache.num_data_array_writes 11 # number of data array writes system.tcp_cntrl1.L1cache.num_tag_array_reads 25 # number of tag array reads system.tcp_cntrl1.L1cache.num_tag_array_writes 18 # number of tag array writes system.tcp_cntrl1.L1cache.num_tag_array_stalls 2 # number of stalls caused by tag array -system.tcp_cntrl1.L1cache.num_data_array_stalls 2 # number of stalls caused by data array -system.tcp_cntrl1.coalescer.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states +system.tcp_cntrl1.L1cache.num_data_array_stalls 6 # number of stalls caused by data array +system.tcp_cntrl1.coalescer.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states system.tcp_cntrl1.coalescer.gpu_tcp_ld_hits 3 # loads that hit in the TCP system.tcp_cntrl1.coalescer.gpu_tcp_ld_transfers 2 # TCP to TCP load transfers system.tcp_cntrl1.coalescer.gpu_tcc_ld_hits 0 # loads that hit in the TCC system.tcp_cntrl1.coalescer.gpu_ld_misses 0 # loads that miss in the GPU system.tcp_cntrl1.coalescer.gpu_tcp_st_hits 4 # stores that hit in the TCP -system.tcp_cntrl1.coalescer.gpu_tcp_st_transfers 0 # TCP to TCP store transfers +system.tcp_cntrl1.coalescer.gpu_tcp_st_transfers 1 # TCP to TCP store transfers system.tcp_cntrl1.coalescer.gpu_tcc_st_hits 0 # stores that hit in the TCC -system.tcp_cntrl1.coalescer.gpu_st_misses 5 # stores that miss in the GPU +system.tcp_cntrl1.coalescer.gpu_st_misses 4 # stores that miss in the GPU system.tcp_cntrl1.coalescer.cp_tcp_ld_hits 0 # loads that hit in the TCP system.tcp_cntrl1.coalescer.cp_tcp_ld_transfers 0 # TCP to TCP load transfers system.tcp_cntrl1.coalescer.cp_tcc_ld_hits 0 # loads that hit in the TCC @@ -2783,98 +2827,98 @@ system.tcp_cntrl1.coalescer.cp_tcp_st_hits 0 # system.tcp_cntrl1.coalescer.cp_tcp_st_transfers 0 # TCP to TCP store transfers system.tcp_cntrl1.coalescer.cp_tcc_st_hits 0 # stores that hit in the TCC system.tcp_cntrl1.coalescer.cp_st_misses 0 # stores that miss in the GPU -system.tcp_cntrl1.sequencer.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states -system.tcp_cntrl1.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states +system.tcp_cntrl1.sequencer.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states +system.tcp_cntrl1.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states system.sqc_cntrl0.L1cache.demand_hits 0 # Number of cache demand hits system.sqc_cntrl0.L1cache.demand_misses 0 # Number of cache demand misses system.sqc_cntrl0.L1cache.demand_accesses 0 # Number of cache demand accesses -system.sqc_cntrl0.L1cache.num_data_array_reads 86 # number of data array reads -system.sqc_cntrl0.L1cache.num_data_array_writes 5 # number of data array writes -system.sqc_cntrl0.L1cache.num_tag_array_reads 86 # number of tag array reads -system.sqc_cntrl0.L1cache.num_tag_array_writes 5 # number of tag array writes -system.sqc_cntrl0.L1cache.num_data_array_stalls 47 # number of stalls caused by data array -system.sqc_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states -system.sqc_cntrl0.sequencer.load_waiting_on_load 120 # Number of times a load aliased with a pending load -system.sqc_cntrl0.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states +system.sqc_cntrl0.L1cache.num_data_array_reads 70 # number of data array reads +system.sqc_cntrl0.L1cache.num_data_array_writes 3 # number of data array writes +system.sqc_cntrl0.L1cache.num_tag_array_reads 70 # number of tag array reads +system.sqc_cntrl0.L1cache.num_tag_array_writes 3 # number of tag array writes +system.sqc_cntrl0.L1cache.num_data_array_stalls 28 # number of stalls caused by data array +system.sqc_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states +system.sqc_cntrl0.sequencer.load_waiting_on_load 75 # Number of times a load aliased with a pending load +system.sqc_cntrl0.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states system.tcc_cntrl0.L2cache.demand_hits 0 # Number of cache demand hits system.tcc_cntrl0.L2cache.demand_misses 0 # Number of cache demand misses system.tcc_cntrl0.L2cache.demand_accesses 0 # Number of cache demand accesses -system.tcc_cntrl0.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states +system.tcc_cntrl0.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states system.tccdir_cntrl0.directory.demand_hits 0 # Number of cache demand hits system.tccdir_cntrl0.directory.demand_misses 0 # Number of cache demand misses system.tccdir_cntrl0.directory.demand_accesses 0 # Number of cache demand accesses -system.tccdir_cntrl0.directory.num_tag_array_reads 1554 # number of tag array reads -system.tccdir_cntrl0.directory.num_tag_array_writes 27 # number of tag array writes -system.tccdir_cntrl0.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states -system.ruby.network.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states -system.ruby.network.msg_count.Control 3116 -system.ruby.network.msg_count.Request_Control 3121 -system.ruby.network.msg_count.Response_Data 3159 -system.ruby.network.msg_count.Response_Control 3078 -system.ruby.network.msg_count.Unblock_Control 3121 -system.ruby.network.msg_byte.Control 24928 -system.ruby.network.msg_byte.Request_Control 24968 -system.ruby.network.msg_byte.Response_Data 227448 -system.ruby.network.msg_byte.Response_Control 24624 -system.ruby.network.msg_byte.Unblock_Control 24968 +system.tccdir_cntrl0.directory.num_tag_array_reads 1552 # number of tag array reads +system.tccdir_cntrl0.directory.num_tag_array_writes 25 # number of tag array writes +system.tccdir_cntrl0.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states +system.ruby.network.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states +system.ruby.network.msg_count.Control 3112 +system.ruby.network.msg_count.Request_Control 3115 +system.ruby.network.msg_count.Response_Data 3153 +system.ruby.network.msg_count.Response_Control 3074 +system.ruby.network.msg_count.Unblock_Control 3115 +system.ruby.network.msg_byte.Control 24896 +system.ruby.network.msg_byte.Request_Control 24920 +system.ruby.network.msg_byte.Response_Data 227016 +system.ruby.network.msg_byte.Response_Control 24592 +system.ruby.network.msg_byte.Unblock_Control 24920 system.sqc_coalescer.clk_domain.voltage_domain.voltage 1 # Voltage in Volts system.sqc_coalescer.clk_domain.clock 1000 # Clock period in ticks -system.sqc_coalescer.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states -system.sqc_coalescer.uncoalesced_accesses 86 # Number of uncoalesced TLB accesses -system.sqc_coalescer.coalesced_accesses 60 # Number of coalesced TLB accesses -system.sqc_coalescer.queuing_cycles 108000 # Number of cycles spent in queue -system.sqc_coalescer.local_queuing_cycles 108000 # Number of cycles spent in queue for all incoming reqs -system.sqc_coalescer.local_latency 1255.813953 # Avg. latency over all incoming pkts +system.sqc_coalescer.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states +system.sqc_coalescer.uncoalesced_accesses 70 # Number of uncoalesced TLB accesses +system.sqc_coalescer.coalesced_accesses 50 # Number of coalesced TLB accesses +system.sqc_coalescer.queuing_cycles 100000 # Number of cycles spent in queue +system.sqc_coalescer.local_queuing_cycles 100000 # Number of cycles spent in queue for all incoming reqs +system.sqc_coalescer.local_latency 1428.571429 # Avg. latency over all incoming pkts system.sqc_tlb.clk_domain.voltage_domain.voltage 1 # Voltage in Volts system.sqc_tlb.clk_domain.clock 1000 # Clock period in ticks -system.sqc_tlb.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states -system.sqc_tlb.local_TLB_accesses 60 # Number of TLB accesses -system.sqc_tlb.local_TLB_hits 59 # Number of TLB hits +system.sqc_tlb.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states +system.sqc_tlb.local_TLB_accesses 50 # Number of TLB accesses +system.sqc_tlb.local_TLB_hits 49 # Number of TLB hits system.sqc_tlb.local_TLB_misses 1 # Number of TLB misses -system.sqc_tlb.local_TLB_miss_rate 1.666667 # TLB miss rate -system.sqc_tlb.global_TLB_accesses 86 # Number of TLB accesses -system.sqc_tlb.global_TLB_hits 78 # Number of TLB hits +system.sqc_tlb.local_TLB_miss_rate 2 # TLB miss rate +system.sqc_tlb.global_TLB_accesses 70 # Number of TLB accesses +system.sqc_tlb.global_TLB_hits 62 # Number of TLB hits system.sqc_tlb.global_TLB_misses 8 # Number of TLB misses -system.sqc_tlb.global_TLB_miss_rate 9.302326 # TLB miss rate -system.sqc_tlb.access_cycles 86008 # Cycles spent accessing this TLB level +system.sqc_tlb.global_TLB_miss_rate 11.428571 # TLB miss rate +system.sqc_tlb.access_cycles 70008 # Cycles spent accessing this TLB level system.sqc_tlb.page_table_cycles 0 # Cycles spent accessing the page table system.sqc_tlb.unique_pages 1 # Number of unique pages touched -system.sqc_tlb.local_cycles 60001 # Number of cycles spent in queue for all incoming reqs -system.sqc_tlb.local_latency 1000.016667 # Avg. latency over incoming coalesced reqs +system.sqc_tlb.local_cycles 50001 # Number of cycles spent in queue for all incoming reqs +system.sqc_tlb.local_latency 1000.020000 # Avg. latency over incoming coalesced reqs system.sqc_tlb.avg_reuse_distance 0 # avg. reuse distance over all pages (in ticks) -system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states -system.ruby.network.ext_links0.int_node.throttle0.link_utilization 0.005553 -system.ruby.network.ext_links0.int_node.throttle0.msg_count.Request_Control::0 1551 +system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 667407500 # Cumulative time (in ticks) in various power states +system.ruby.network.ext_links0.int_node.throttle0.link_utilization 0.005552 +system.ruby.network.ext_links0.int_node.throttle0.msg_count.Request_Control::0 1549 system.ruby.network.ext_links0.int_node.throttle0.msg_count.Response_Data::2 12 -system.ruby.network.ext_links0.int_node.throttle0.msg_count.Response_Control::2 1539 -system.ruby.network.ext_links0.int_node.throttle0.msg_count.Unblock_Control::4 1551 -system.ruby.network.ext_links0.int_node.throttle0.msg_bytes.Request_Control::0 12408 +system.ruby.network.ext_links0.int_node.throttle0.msg_count.Response_Control::2 1537 +system.ruby.network.ext_links0.int_node.throttle0.msg_count.Unblock_Control::4 1549 +system.ruby.network.ext_links0.int_node.throttle0.msg_bytes.Request_Control::0 12392 system.ruby.network.ext_links0.int_node.throttle0.msg_bytes.Response_Data::2 864 -system.ruby.network.ext_links0.int_node.throttle0.msg_bytes.Response_Control::2 12312 -system.ruby.network.ext_links0.int_node.throttle0.msg_bytes.Unblock_Control::4 12408 -system.ruby.network.ext_links0.int_node.throttle1.link_utilization 0.016173 -system.ruby.network.ext_links0.int_node.throttle1.msg_count.Control::0 16 +system.ruby.network.ext_links0.int_node.throttle0.msg_bytes.Response_Control::2 12296 +system.ruby.network.ext_links0.int_node.throttle0.msg_bytes.Unblock_Control::4 12392 +system.ruby.network.ext_links0.int_node.throttle1.link_utilization 0.016188 +system.ruby.network.ext_links0.int_node.throttle1.msg_count.Control::0 14 system.ruby.network.ext_links0.int_node.throttle1.msg_count.Response_Data::2 1535 -system.ruby.network.ext_links0.int_node.throttle1.msg_bytes.Control::0 128 +system.ruby.network.ext_links0.int_node.throttle1.msg_bytes.Control::0 112 system.ruby.network.ext_links0.int_node.throttle1.msg_bytes.Response_Data::2 110520 -system.ruby.network.ext_links0.int_node.throttle2.link_utilization 0.001963 +system.ruby.network.ext_links0.int_node.throttle2.link_utilization 0.001944 system.ruby.network.ext_links0.int_node.throttle2.msg_count.Control::0 1535 -system.ruby.network.ext_links0.int_node.throttle2.msg_count.Response_Data::2 16 +system.ruby.network.ext_links0.int_node.throttle2.msg_count.Response_Data::2 14 system.ruby.network.ext_links0.int_node.throttle2.msg_bytes.Control::0 12280 -system.ruby.network.ext_links0.int_node.throttle2.msg_bytes.Response_Data::2 1152 -system.ruby.network.ext_links1.int_node.throttle0.link_utilization 0.016173 -system.ruby.network.ext_links1.int_node.throttle0.msg_count.Control::0 16 +system.ruby.network.ext_links0.int_node.throttle2.msg_bytes.Response_Data::2 1008 +system.ruby.network.ext_links1.int_node.throttle0.link_utilization 0.016188 +system.ruby.network.ext_links1.int_node.throttle0.msg_count.Control::0 14 system.ruby.network.ext_links1.int_node.throttle0.msg_count.Response_Data::2 1535 -system.ruby.network.ext_links1.int_node.throttle0.msg_bytes.Control::0 128 +system.ruby.network.ext_links1.int_node.throttle0.msg_bytes.Control::0 112 system.ruby.network.ext_links1.int_node.throttle0.msg_bytes.Response_Data::2 110520 -system.ruby.network.ext_links1.int_node.throttle1.link_utilization 0.003627 +system.ruby.network.ext_links1.int_node.throttle1.link_utilization 0.003629 system.ruby.network.ext_links1.int_node.throttle1.msg_count.Request_Control::0 1535 system.ruby.network.ext_links1.int_node.throttle1.msg_count.Response_Data::2 2 -system.ruby.network.ext_links1.int_node.throttle1.msg_count.Response_Control::2 14 +system.ruby.network.ext_links1.int_node.throttle1.msg_count.Response_Control::2 12 system.ruby.network.ext_links1.int_node.throttle1.msg_count.Unblock_Control::4 1535 system.ruby.network.ext_links1.int_node.throttle1.msg_bytes.Request_Control::0 12280 system.ruby.network.ext_links1.int_node.throttle1.msg_bytes.Response_Data::2 144 -system.ruby.network.ext_links1.int_node.throttle1.msg_bytes.Response_Control::2 112 +system.ruby.network.ext_links1.int_node.throttle1.msg_bytes.Response_Control::2 96 system.ruby.network.ext_links1.int_node.throttle1.msg_bytes.Unblock_Control::4 12280 system.ruby.network.ext_links2.int_node.throttle0.link_utilization 0.000083 system.ruby.network.ext_links2.int_node.throttle0.msg_count.Control::1 8 @@ -2887,29 +2931,29 @@ system.ruby.network.ext_links2.int_node.throttle1.msg_count.Response_Data::3 system.ruby.network.ext_links2.int_node.throttle1.msg_bytes.Control::1 48 system.ruby.network.ext_links2.int_node.throttle1.msg_bytes.Response_Data::3 504 system.ruby.network.ext_links2.int_node.throttle2.link_utilization 0 -system.ruby.network.ext_links2.int_node.throttle3.link_utilization 0.002155 +system.ruby.network.ext_links2.int_node.throttle3.link_utilization 0.002132 system.ruby.network.ext_links2.int_node.throttle3.msg_count.Control::0 1535 -system.ruby.network.ext_links2.int_node.throttle3.msg_count.Request_Control::1 19 -system.ruby.network.ext_links2.int_node.throttle3.msg_count.Response_Data::2 16 +system.ruby.network.ext_links2.int_node.throttle3.msg_count.Request_Control::1 17 +system.ruby.network.ext_links2.int_node.throttle3.msg_count.Response_Data::2 14 system.ruby.network.ext_links2.int_node.throttle3.msg_count.Response_Data::3 14 -system.ruby.network.ext_links2.int_node.throttle3.msg_count.Unblock_Control::5 19 +system.ruby.network.ext_links2.int_node.throttle3.msg_count.Unblock_Control::5 17 system.ruby.network.ext_links2.int_node.throttle3.msg_bytes.Control::0 12280 -system.ruby.network.ext_links2.int_node.throttle3.msg_bytes.Request_Control::1 152 -system.ruby.network.ext_links2.int_node.throttle3.msg_bytes.Response_Data::2 1152 +system.ruby.network.ext_links2.int_node.throttle3.msg_bytes.Request_Control::1 136 +system.ruby.network.ext_links2.int_node.throttle3.msg_bytes.Response_Data::2 1008 system.ruby.network.ext_links2.int_node.throttle3.msg_bytes.Response_Data::3 1008 -system.ruby.network.ext_links2.int_node.throttle3.msg_bytes.Unblock_Control::5 152 -system.ruby.network.ext_links2.int_node.throttle4.link_utilization 0.000053 -system.ruby.network.ext_links2.int_node.throttle4.msg_count.Response_Data::3 5 -system.ruby.network.ext_links2.int_node.throttle4.msg_bytes.Response_Data::3 360 -system.ruby.network.ext_links2.int_node.throttle5.link_utilization 0.001926 -system.ruby.network.ext_links2.int_node.throttle5.msg_count.Request_Control::0 16 +system.ruby.network.ext_links2.int_node.throttle3.msg_bytes.Unblock_Control::5 136 +system.ruby.network.ext_links2.int_node.throttle4.link_utilization 0.000032 +system.ruby.network.ext_links2.int_node.throttle4.msg_count.Response_Data::3 3 +system.ruby.network.ext_links2.int_node.throttle4.msg_bytes.Response_Data::3 216 +system.ruby.network.ext_links2.int_node.throttle5.link_utilization 0.001923 +system.ruby.network.ext_links2.int_node.throttle5.msg_count.Request_Control::0 14 system.ruby.network.ext_links2.int_node.throttle5.msg_count.Response_Data::2 10 system.ruby.network.ext_links2.int_node.throttle5.msg_count.Response_Control::2 1525 -system.ruby.network.ext_links2.int_node.throttle5.msg_count.Unblock_Control::4 16 -system.ruby.network.ext_links2.int_node.throttle5.msg_bytes.Request_Control::0 128 +system.ruby.network.ext_links2.int_node.throttle5.msg_count.Unblock_Control::4 14 +system.ruby.network.ext_links2.int_node.throttle5.msg_bytes.Request_Control::0 112 system.ruby.network.ext_links2.int_node.throttle5.msg_bytes.Response_Data::2 720 system.ruby.network.ext_links2.int_node.throttle5.msg_bytes.Response_Control::2 12200 -system.ruby.network.ext_links2.int_node.throttle5.msg_bytes.Unblock_Control::4 128 +system.ruby.network.ext_links2.int_node.throttle5.msg_bytes.Unblock_Control::4 112 system.ruby.CorePair_Controller.C0_Load_L1miss 180 0.00% 0.00% system.ruby.CorePair_Controller.C0_Load_L1hit 16155 0.00% 0.00% system.ruby.CorePair_Controller.Ifetch0_L1hit 86007 0.00% 0.00% @@ -2924,12 +2968,12 @@ system.ruby.CorePair_Controller.L1D0_Repl 24 0.00% 0.00% system.ruby.CorePair_Controller.L2_to_L1D0 5 0.00% 0.00% system.ruby.CorePair_Controller.L2_to_L1I 54 0.00% 0.00% system.ruby.CorePair_Controller.PrbInvData 9 0.00% 0.00% -system.ruby.CorePair_Controller.PrbShrData 7 0.00% 0.00% +system.ruby.CorePair_Controller.PrbShrData 5 0.00% 0.00% system.ruby.CorePair_Controller.I.C0_Load_L1miss 175 0.00% 0.00% system.ruby.CorePair_Controller.I.Ifetch0_L1miss 1034 0.00% 0.00% system.ruby.CorePair_Controller.I.C0_Store_L1miss 325 0.00% 0.00% system.ruby.CorePair_Controller.I.PrbInvData 8 0.00% 0.00% -system.ruby.CorePair_Controller.I.PrbShrData 5 0.00% 0.00% +system.ruby.CorePair_Controller.I.PrbShrData 3 0.00% 0.00% system.ruby.CorePair_Controller.S.C0_Load_L1hit 635 0.00% 0.00% system.ruby.CorePair_Controller.S.Ifetch0_L1hit 86007 0.00% 0.00% system.ruby.CorePair_Controller.S.Ifetch0_L1miss 54 0.00% 0.00% @@ -2955,35 +2999,35 @@ system.ruby.CorePair_Controller.O_M0.NB_AckM 1 0.00% 0.00% system.ruby.CorePair_Controller.S0.NB_AckS 1034 0.00% 0.00% system.ruby.CorePair_Controller.E0_F.L2_to_L1D0 2 0.00% 0.00% system.ruby.CorePair_Controller.M0_F.L2_to_L1D0 3 0.00% 0.00% -system.ruby.Directory_Controller.RdBlkS 1039 0.00% 0.00% +system.ruby.Directory_Controller.RdBlkS 1037 0.00% 0.00% system.ruby.Directory_Controller.RdBlkM 335 0.00% 0.00% system.ruby.Directory_Controller.RdBlk 177 0.00% 0.00% -system.ruby.Directory_Controller.CPUPrbResp 1551 0.00% 0.00% -system.ruby.Directory_Controller.ProbeAcksComplete 1551 0.00% 0.00% -system.ruby.Directory_Controller.MemData 1551 0.00% 0.00% -system.ruby.Directory_Controller.CoreUnblock 1551 0.00% 0.00% -system.ruby.Directory_Controller.U.RdBlkS 1039 0.00% 0.00% +system.ruby.Directory_Controller.CPUPrbResp 1549 0.00% 0.00% +system.ruby.Directory_Controller.ProbeAcksComplete 1549 0.00% 0.00% +system.ruby.Directory_Controller.MemData 1549 0.00% 0.00% +system.ruby.Directory_Controller.CoreUnblock 1549 0.00% 0.00% +system.ruby.Directory_Controller.U.RdBlkS 1037 0.00% 0.00% system.ruby.Directory_Controller.U.RdBlkM 335 0.00% 0.00% system.ruby.Directory_Controller.U.RdBlk 177 0.00% 0.00% -system.ruby.Directory_Controller.BS_M.MemData 36 0.00% 0.00% -system.ruby.Directory_Controller.BM_M.MemData 13 0.00% 0.00% -system.ruby.Directory_Controller.B_M.MemData 12 0.00% 0.00% -system.ruby.Directory_Controller.BS_PM.CPUPrbResp 36 0.00% 0.00% -system.ruby.Directory_Controller.BS_PM.ProbeAcksComplete 36 0.00% 0.00% -system.ruby.Directory_Controller.BS_PM.MemData 1003 0.00% 0.00% -system.ruby.Directory_Controller.BM_PM.CPUPrbResp 14 0.00% 0.00% -system.ruby.Directory_Controller.BM_PM.ProbeAcksComplete 13 0.00% 0.00% -system.ruby.Directory_Controller.BM_PM.MemData 322 0.00% 0.00% -system.ruby.Directory_Controller.B_PM.CPUPrbResp 12 0.00% 0.00% -system.ruby.Directory_Controller.B_PM.ProbeAcksComplete 12 0.00% 0.00% -system.ruby.Directory_Controller.B_PM.MemData 165 0.00% 0.00% -system.ruby.Directory_Controller.BS_Pm.CPUPrbResp 1003 0.00% 0.00% -system.ruby.Directory_Controller.BS_Pm.ProbeAcksComplete 1003 0.00% 0.00% -system.ruby.Directory_Controller.BM_Pm.CPUPrbResp 321 0.00% 0.00% -system.ruby.Directory_Controller.BM_Pm.ProbeAcksComplete 322 0.00% 0.00% -system.ruby.Directory_Controller.B_Pm.CPUPrbResp 165 0.00% 0.00% -system.ruby.Directory_Controller.B_Pm.ProbeAcksComplete 165 0.00% 0.00% -system.ruby.Directory_Controller.B.CoreUnblock 1551 0.00% 0.00% +system.ruby.Directory_Controller.BS_M.MemData 35 0.00% 0.00% +system.ruby.Directory_Controller.BM_M.MemData 18 0.00% 0.00% +system.ruby.Directory_Controller.B_M.MemData 11 0.00% 0.00% +system.ruby.Directory_Controller.BS_PM.CPUPrbResp 35 0.00% 0.00% +system.ruby.Directory_Controller.BS_PM.ProbeAcksComplete 35 0.00% 0.00% +system.ruby.Directory_Controller.BS_PM.MemData 1002 0.00% 0.00% +system.ruby.Directory_Controller.BM_PM.CPUPrbResp 18 0.00% 0.00% +system.ruby.Directory_Controller.BM_PM.ProbeAcksComplete 18 0.00% 0.00% +system.ruby.Directory_Controller.BM_PM.MemData 317 0.00% 0.00% +system.ruby.Directory_Controller.B_PM.CPUPrbResp 11 0.00% 0.00% +system.ruby.Directory_Controller.B_PM.ProbeAcksComplete 11 0.00% 0.00% +system.ruby.Directory_Controller.B_PM.MemData 166 0.00% 0.00% +system.ruby.Directory_Controller.BS_Pm.CPUPrbResp 1002 0.00% 0.00% +system.ruby.Directory_Controller.BS_Pm.ProbeAcksComplete 1002 0.00% 0.00% +system.ruby.Directory_Controller.BM_Pm.CPUPrbResp 317 0.00% 0.00% +system.ruby.Directory_Controller.BM_Pm.ProbeAcksComplete 317 0.00% 0.00% +system.ruby.Directory_Controller.B_Pm.CPUPrbResp 166 0.00% 0.00% +system.ruby.Directory_Controller.B_Pm.ProbeAcksComplete 166 0.00% 0.00% +system.ruby.Directory_Controller.B.CoreUnblock 1549 0.00% 0.00% system.ruby.LD.latency_hist_seqr::bucket_size 64 system.ruby.LD.latency_hist_seqr::max_bucket 639 system.ruby.LD.latency_hist_seqr::samples 16335 @@ -2995,10 +3039,10 @@ system.ruby.LD.latency_hist_seqr::total 16335 system.ruby.LD.latency_hist_coalsr::bucket_size 64 system.ruby.LD.latency_hist_coalsr::max_bucket 639 system.ruby.LD.latency_hist_coalsr::samples 9 -system.ruby.LD.latency_hist_coalsr::mean 219.555556 -system.ruby.LD.latency_hist_coalsr::gmean 24.880500 -system.ruby.LD.latency_hist_coalsr::stdev 259.591078 -system.ruby.LD.latency_hist_coalsr | 5 55.56% 55.56% | 0 0.00% 55.56% | 0 0.00% 55.56% | 0 0.00% 55.56% | 0 0.00% 55.56% | 0 0.00% 55.56% | 1 11.11% 66.67% | 1 11.11% 77.78% | 2 22.22% 100.00% | 0 0.00% 100.00% +system.ruby.LD.latency_hist_coalsr::mean 133.666667 +system.ruby.LD.latency_hist_coalsr::gmean 19.860866 +system.ruby.LD.latency_hist_coalsr::stdev 158.801763 +system.ruby.LD.latency_hist_coalsr | 5 55.56% 55.56% | 0 0.00% 55.56% | 0 0.00% 55.56% | 1 11.11% 66.67% | 1 11.11% 77.78% | 2 22.22% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.LD.latency_hist_coalsr::total 9 system.ruby.LD.hit_latency_hist_seqr::bucket_size 64 system.ruby.LD.hit_latency_hist_seqr::max_bucket 639 @@ -3019,10 +3063,10 @@ system.ruby.LD.miss_latency_hist_seqr::total 16160 system.ruby.LD.miss_latency_hist_coalsr::bucket_size 64 system.ruby.LD.miss_latency_hist_coalsr::max_bucket 639 system.ruby.LD.miss_latency_hist_coalsr::samples 9 -system.ruby.LD.miss_latency_hist_coalsr::mean 219.555556 -system.ruby.LD.miss_latency_hist_coalsr::gmean 24.880500 -system.ruby.LD.miss_latency_hist_coalsr::stdev 259.591078 -system.ruby.LD.miss_latency_hist_coalsr | 5 55.56% 55.56% | 0 0.00% 55.56% | 0 0.00% 55.56% | 0 0.00% 55.56% | 0 0.00% 55.56% | 0 0.00% 55.56% | 1 11.11% 66.67% | 1 11.11% 77.78% | 2 22.22% 100.00% | 0 0.00% 100.00% +system.ruby.LD.miss_latency_hist_coalsr::mean 133.666667 +system.ruby.LD.miss_latency_hist_coalsr::gmean 19.860866 +system.ruby.LD.miss_latency_hist_coalsr::stdev 158.801763 +system.ruby.LD.miss_latency_hist_coalsr | 5 55.56% 55.56% | 0 0.00% 55.56% | 0 0.00% 55.56% | 1 11.11% 66.67% | 1 11.11% 77.78% | 2 22.22% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.LD.miss_latency_hist_coalsr::total 9 system.ruby.ST.latency_hist_seqr::bucket_size 64 system.ruby.ST.latency_hist_seqr::max_bucket 639 @@ -3032,13 +3076,13 @@ system.ruby.ST.latency_hist_seqr::gmean 2.309412 system.ruby.ST.latency_hist_seqr::stdev 36.833690 system.ruby.ST.latency_hist_seqr | 10090 96.91% 96.91% | 0 0.00% 96.91% | 0 0.00% 96.91% | 314 3.02% 99.92% | 1 0.01% 99.93% | 5 0.05% 99.98% | 0 0.00% 99.98% | 0 0.00% 99.98% | 0 0.00% 99.98% | 2 0.02% 100.00% system.ruby.ST.latency_hist_seqr::total 10412 -system.ruby.ST.latency_hist_coalsr::bucket_size 32 -system.ruby.ST.latency_hist_coalsr::max_bucket 319 +system.ruby.ST.latency_hist_coalsr::bucket_size 64 +system.ruby.ST.latency_hist_coalsr::max_bucket 639 system.ruby.ST.latency_hist_coalsr::samples 16 -system.ruby.ST.latency_hist_coalsr::mean 125.375000 -system.ruby.ST.latency_hist_coalsr::gmean 15.802815 -system.ruby.ST.latency_hist_coalsr::stdev 128.476133 -system.ruby.ST.latency_hist_coalsr | 8 50.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 7 43.75% 93.75% | 1 6.25% 100.00% | 0 0.00% 100.00% +system.ruby.ST.latency_hist_coalsr::mean 184.500000 +system.ruby.ST.latency_hist_coalsr::gmean 27.004823 +system.ruby.ST.latency_hist_coalsr::stdev 190.921974 +system.ruby.ST.latency_hist_coalsr | 8 50.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 4 25.00% 75.00% | 4 25.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.ST.latency_hist_coalsr::total 16 system.ruby.ST.hit_latency_hist_seqr::bucket_size 64 system.ruby.ST.hit_latency_hist_seqr::max_bucket 639 @@ -3055,28 +3099,28 @@ system.ruby.ST.miss_latency_hist_seqr::mean 2 system.ruby.ST.miss_latency_hist_seqr::gmean 2.000000 system.ruby.ST.miss_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 10090 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.ST.miss_latency_hist_seqr::total 10090 -system.ruby.ST.miss_latency_hist_coalsr::bucket_size 32 -system.ruby.ST.miss_latency_hist_coalsr::max_bucket 319 +system.ruby.ST.miss_latency_hist_coalsr::bucket_size 64 +system.ruby.ST.miss_latency_hist_coalsr::max_bucket 639 system.ruby.ST.miss_latency_hist_coalsr::samples 16 -system.ruby.ST.miss_latency_hist_coalsr::mean 125.375000 -system.ruby.ST.miss_latency_hist_coalsr::gmean 15.802815 -system.ruby.ST.miss_latency_hist_coalsr::stdev 128.476133 -system.ruby.ST.miss_latency_hist_coalsr | 8 50.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 7 43.75% 93.75% | 1 6.25% 100.00% | 0 0.00% 100.00% +system.ruby.ST.miss_latency_hist_coalsr::mean 184.500000 +system.ruby.ST.miss_latency_hist_coalsr::gmean 27.004823 +system.ruby.ST.miss_latency_hist_coalsr::stdev 190.921974 +system.ruby.ST.miss_latency_hist_coalsr | 8 50.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 4 25.00% 75.00% | 4 25.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.ST.miss_latency_hist_coalsr::total 16 system.ruby.ATOMIC.latency_hist_coalsr::bucket_size 64 system.ruby.ATOMIC.latency_hist_coalsr::max_bucket 639 system.ruby.ATOMIC.latency_hist_coalsr::samples 2 -system.ruby.ATOMIC.latency_hist_coalsr::mean 317.500000 -system.ruby.ATOMIC.latency_hist_coalsr::gmean 314.366029 -system.ruby.ATOMIC.latency_hist_coalsr::stdev 62.932504 +system.ruby.ATOMIC.latency_hist_coalsr::mean 295.500000 +system.ruby.ATOMIC.latency_hist_coalsr::gmean 293.237105 +system.ruby.ATOMIC.latency_hist_coalsr::stdev 51.618795 system.ruby.ATOMIC.latency_hist_coalsr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 50.00% 50.00% | 1 50.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.ATOMIC.latency_hist_coalsr::total 2 system.ruby.ATOMIC.miss_latency_hist_coalsr::bucket_size 64 system.ruby.ATOMIC.miss_latency_hist_coalsr::max_bucket 639 system.ruby.ATOMIC.miss_latency_hist_coalsr::samples 2 -system.ruby.ATOMIC.miss_latency_hist_coalsr::mean 317.500000 -system.ruby.ATOMIC.miss_latency_hist_coalsr::gmean 314.366029 -system.ruby.ATOMIC.miss_latency_hist_coalsr::stdev 62.932504 +system.ruby.ATOMIC.miss_latency_hist_coalsr::mean 295.500000 +system.ruby.ATOMIC.miss_latency_hist_coalsr::gmean 293.237105 +system.ruby.ATOMIC.miss_latency_hist_coalsr::stdev 51.618795 system.ruby.ATOMIC.miss_latency_hist_coalsr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 50.00% 50.00% | 1 50.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.ATOMIC.miss_latency_hist_coalsr::total 2 system.ruby.IFETCH.latency_hist_seqr::bucket_size 64 @@ -3178,26 +3222,26 @@ system.ruby.Directory.hit_mach_latency_hist_seqr::total 1535 system.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr::bucket_size 64 system.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr::max_bucket 639 system.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr::samples 3 -system.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr::mean 478.666667 -system.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr::gmean 470.839796 -system.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr::stdev 101.159939 -system.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 33.33% 33.33% | 0 0.00% 33.33% | 0 0.00% 33.33% | 2 66.67% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr::mean 338.666667 +system.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr::gmean 338.633640 +system.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr::stdev 5.773503 +system.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 3 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr::total 3 system.ruby.TCP.miss_mach_latency_hist_coalsr::bucket_size 1 system.ruby.TCP.miss_mach_latency_hist_coalsr::max_bucket 9 system.ruby.TCP.miss_mach_latency_hist_coalsr::samples 13 -system.ruby.TCP.miss_mach_latency_hist_coalsr::mean 1.538462 -system.ruby.TCP.miss_mach_latency_hist_coalsr::gmean 1.377009 -system.ruby.TCP.miss_mach_latency_hist_coalsr::stdev 0.877058 -system.ruby.TCP.miss_mach_latency_hist_coalsr | 0 0.00% 0.00% | 8 61.54% 61.54% | 4 30.77% 92.31% | 0 0.00% 92.31% | 1 7.69% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.TCP.miss_mach_latency_hist_coalsr::mean 2.153846 +system.ruby.TCP.miss_mach_latency_hist_coalsr::gmean 2.109532 +system.ruby.TCP.miss_mach_latency_hist_coalsr::stdev 0.554700 +system.ruby.TCP.miss_mach_latency_hist_coalsr | 0 0.00% 0.00% | 0 0.00% 0.00% | 12 92.31% 92.31% | 0 0.00% 92.31% | 1 7.69% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.TCP.miss_mach_latency_hist_coalsr::total 13 system.ruby.TCCdir.miss_mach_latency_hist_coalsr::bucket_size 64 system.ruby.TCCdir.miss_mach_latency_hist_coalsr::max_bucket 639 system.ruby.TCCdir.miss_mach_latency_hist_coalsr::samples 11 -system.ruby.TCCdir.miss_mach_latency_hist_coalsr::mean 287.363636 -system.ruby.TCCdir.miss_mach_latency_hist_coalsr::gmean 279.637814 -system.ruby.TCCdir.miss_mach_latency_hist_coalsr::stdev 78.345737 -system.ruby.TCCdir.miss_mach_latency_hist_coalsr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 7 63.64% 63.64% | 2 18.18% 81.82% | 0 0.00% 81.82% | 1 9.09% 90.91% | 1 9.09% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.TCCdir.miss_mach_latency_hist_coalsr::mean 336.545455 +system.ruby.TCCdir.miss_mach_latency_hist_coalsr::gmean 330.845159 +system.ruby.TCCdir.miss_mach_latency_hist_coalsr::stdev 64.151950 +system.ruby.TCCdir.miss_mach_latency_hist_coalsr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 9.09% 9.09% | 2 18.18% 27.27% | 4 36.36% 63.64% | 4 36.36% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.TCCdir.miss_mach_latency_hist_coalsr::total 11 system.ruby.LD.L1Cache.miss_type_mach_latency_hist_seqr::bucket_size 1 system.ruby.LD.L1Cache.miss_type_mach_latency_hist_seqr::max_bucket 9 @@ -3224,10 +3268,9 @@ system.ruby.LD.Directory.hit_type_mach_latency_hist_seqr::total 175 system.ruby.LD.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::bucket_size 64 system.ruby.LD.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::max_bucket 639 system.ruby.LD.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::samples 2 -system.ruby.LD.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::mean 537 -system.ruby.LD.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::gmean 536.976722 -system.ruby.LD.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::stdev 7.071068 -system.ruby.LD.L1Cache_wCC.miss_type_mach_latency_hist_coalsr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 2 100.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::mean 342 +system.ruby.LD.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::gmean 342.000000 +system.ruby.LD.L1Cache_wCC.miss_type_mach_latency_hist_coalsr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 2 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.LD.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::total 2 system.ruby.LD.TCP.miss_type_mach_latency_hist_coalsr::bucket_size 1 system.ruby.LD.TCP.miss_type_mach_latency_hist_coalsr::max_bucket 9 @@ -3237,13 +3280,13 @@ system.ruby.LD.TCP.miss_type_mach_latency_hist_coalsr::gmean 2.297397 system.ruby.LD.TCP.miss_type_mach_latency_hist_coalsr::stdev 0.894427 system.ruby.LD.TCP.miss_type_mach_latency_hist_coalsr | 0 0.00% 0.00% | 0 0.00% 0.00% | 4 80.00% 80.00% | 0 0.00% 80.00% | 1 20.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.LD.TCP.miss_type_mach_latency_hist_coalsr::total 5 -system.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr::bucket_size 64 -system.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr::max_bucket 639 +system.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr::bucket_size 32 +system.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr::max_bucket 319 system.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr::samples 2 -system.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr::mean 445 -system.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr::gmean 444.959549 -system.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr::stdev 8.485281 -system.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 50.00% 50.00% | 1 50.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr::mean 253.500000 +system.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr::gmean 253.440328 +system.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr::stdev 7.778175 +system.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 50.00% 50.00% | 1 50.00% 100.00% | 0 0.00% 100.00% system.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr::total 2 system.ruby.ST.L1Cache.miss_type_mach_latency_hist_seqr::bucket_size 1 system.ruby.ST.L1Cache.miss_type_mach_latency_hist_seqr::max_bucket 9 @@ -3263,31 +3306,31 @@ system.ruby.ST.Directory.hit_type_mach_latency_hist_seqr::total 322 system.ruby.ST.TCP.miss_type_mach_latency_hist_coalsr::bucket_size 1 system.ruby.ST.TCP.miss_type_mach_latency_hist_coalsr::max_bucket 9 system.ruby.ST.TCP.miss_type_mach_latency_hist_coalsr::samples 8 -system.ruby.ST.TCP.miss_type_mach_latency_hist_coalsr::mean 1 -system.ruby.ST.TCP.miss_type_mach_latency_hist_coalsr::gmean 1 -system.ruby.ST.TCP.miss_type_mach_latency_hist_coalsr | 0 0.00% 0.00% | 8 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.TCP.miss_type_mach_latency_hist_coalsr::mean 2 +system.ruby.ST.TCP.miss_type_mach_latency_hist_coalsr::gmean 2 +system.ruby.ST.TCP.miss_type_mach_latency_hist_coalsr | 0 0.00% 0.00% | 0 0.00% 0.00% | 8 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.ST.TCP.miss_type_mach_latency_hist_coalsr::total 8 -system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::bucket_size 32 -system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::max_bucket 319 +system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::bucket_size 64 +system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::max_bucket 639 system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::samples 8 -system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::mean 249.750000 -system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::gmean 249.728954 -system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::stdev 3.494894 -system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 7 87.50% 87.50% | 1 12.50% 100.00% | 0 0.00% 100.00% +system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::mean 367 +system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::gmean 364.630235 +system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::stdev 44.510031 +system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 4 50.00% 50.00% | 4 50.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::total 8 system.ruby.ATOMIC.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::bucket_size 64 system.ruby.ATOMIC.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::max_bucket 639 system.ruby.ATOMIC.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::samples 1 -system.ruby.ATOMIC.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::mean 362 -system.ruby.ATOMIC.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::gmean 362.000000 +system.ruby.ATOMIC.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::mean 332 +system.ruby.ATOMIC.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::gmean 332.000000 system.ruby.ATOMIC.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::stdev nan system.ruby.ATOMIC.L1Cache_wCC.miss_type_mach_latency_hist_coalsr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.ATOMIC.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::total 1 system.ruby.ATOMIC.TCCdir.miss_type_mach_latency_hist_coalsr::bucket_size 32 system.ruby.ATOMIC.TCCdir.miss_type_mach_latency_hist_coalsr::max_bucket 319 system.ruby.ATOMIC.TCCdir.miss_type_mach_latency_hist_coalsr::samples 1 -system.ruby.ATOMIC.TCCdir.miss_type_mach_latency_hist_coalsr::mean 273 -system.ruby.ATOMIC.TCCdir.miss_type_mach_latency_hist_coalsr::gmean 273 +system.ruby.ATOMIC.TCCdir.miss_type_mach_latency_hist_coalsr::mean 259 +system.ruby.ATOMIC.TCCdir.miss_type_mach_latency_hist_coalsr::gmean 259.000000 system.ruby.ATOMIC.TCCdir.miss_type_mach_latency_hist_coalsr::stdev nan system.ruby.ATOMIC.TCCdir.miss_type_mach_latency_hist_coalsr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% system.ruby.ATOMIC.TCCdir.miss_type_mach_latency_hist_coalsr::total 1 @@ -3341,25 +3384,25 @@ system.ruby.Locked_RMW_Write.L1Cache.miss_type_mach_latency_hist_seqr::mean system.ruby.Locked_RMW_Write.L1Cache.miss_type_mach_latency_hist_seqr::gmean 2 system.ruby.Locked_RMW_Write.L1Cache.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 10 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.Locked_RMW_Write.L1Cache.miss_type_mach_latency_hist_seqr::total 10 -system.ruby.SQC_Controller.Fetch 86 0.00% 0.00% -system.ruby.SQC_Controller.TCC_AckS 5 0.00% 0.00% -system.ruby.SQC_Controller.I.Fetch 5 0.00% 0.00% -system.ruby.SQC_Controller.S.Fetch 81 0.00% 0.00% -system.ruby.SQC_Controller.I_S.TCC_AckS 5 0.00% 0.00% -system.ruby.TCCdir_Controller.RdBlk 93 0.00% 0.00% -system.ruby.TCCdir_Controller.RdBlkM 37 0.00% 0.00% -system.ruby.TCCdir_Controller.RdBlkS 5 0.00% 0.00% +system.ruby.SQC_Controller.Fetch 70 0.00% 0.00% +system.ruby.SQC_Controller.TCC_AckS 3 0.00% 0.00% +system.ruby.SQC_Controller.I.Fetch 3 0.00% 0.00% +system.ruby.SQC_Controller.S.Fetch 67 0.00% 0.00% +system.ruby.SQC_Controller.I_S.TCC_AckS 3 0.00% 0.00% +system.ruby.TCCdir_Controller.RdBlk 54 0.00% 0.00% +system.ruby.TCCdir_Controller.RdBlkM 34 0.00% 0.00% +system.ruby.TCCdir_Controller.RdBlkS 3 0.00% 0.00% system.ruby.TCCdir_Controller.CPUPrbResp 14 0.00% 0.00% system.ruby.TCCdir_Controller.ProbeAcksComplete 13 0.00% 0.00% -system.ruby.TCCdir_Controller.CoreUnblock 17 0.00% 0.00% +system.ruby.TCCdir_Controller.CoreUnblock 15 0.00% 0.00% system.ruby.TCCdir_Controller.LastCoreUnblock 2 0.00% 0.00% -system.ruby.TCCdir_Controller.NB_AckS 7 0.00% 0.00% +system.ruby.TCCdir_Controller.NB_AckS 5 0.00% 0.00% system.ruby.TCCdir_Controller.NB_AckM 9 0.00% 0.00% system.ruby.TCCdir_Controller.PrbInvData 326 0.00% 0.00% system.ruby.TCCdir_Controller.PrbShrData 1209 0.00% 0.00% system.ruby.TCCdir_Controller.I.RdBlk 2 0.00% 0.00% system.ruby.TCCdir_Controller.I.RdBlkM 9 0.00% 0.00% -system.ruby.TCCdir_Controller.I.RdBlkS 5 0.00% 0.00% +system.ruby.TCCdir_Controller.I.RdBlkS 3 0.00% 0.00% system.ruby.TCCdir_Controller.I.PrbInvData 325 0.00% 0.00% system.ruby.TCCdir_Controller.I.PrbShrData 1200 0.00% 0.00% system.ruby.TCCdir_Controller.S.RdBlk 2 0.00% 0.00% @@ -3370,20 +3413,20 @@ system.ruby.TCCdir_Controller.CP_I.CPUPrbResp 2 0.00% 0.00% system.ruby.TCCdir_Controller.CP_I.ProbeAcksComplete 1 0.00% 0.00% system.ruby.TCCdir_Controller.CP_O.CPUPrbResp 9 0.00% 0.00% system.ruby.TCCdir_Controller.CP_O.ProbeAcksComplete 9 0.00% 0.00% -system.ruby.TCCdir_Controller.I_M.RdBlkM 22 0.00% 0.00% +system.ruby.TCCdir_Controller.I_M.RdBlkM 20 0.00% 0.00% system.ruby.TCCdir_Controller.I_M.NB_AckM 9 0.00% 0.00% -system.ruby.TCCdir_Controller.I_ES.RdBlk 79 0.00% 0.00% +system.ruby.TCCdir_Controller.I_ES.RdBlk 41 0.00% 0.00% system.ruby.TCCdir_Controller.I_ES.NB_AckS 2 0.00% 0.00% -system.ruby.TCCdir_Controller.I_S.NB_AckS 5 0.00% 0.00% +system.ruby.TCCdir_Controller.I_S.NB_AckS 3 0.00% 0.00% system.ruby.TCCdir_Controller.BBS_S.CPUPrbResp 2 0.00% 0.00% system.ruby.TCCdir_Controller.BBS_S.ProbeAcksComplete 2 0.00% 0.00% system.ruby.TCCdir_Controller.BBM_M.CPUPrbResp 1 0.00% 0.00% system.ruby.TCCdir_Controller.BBM_M.ProbeAcksComplete 1 0.00% 0.00% system.ruby.TCCdir_Controller.BB_M.CoreUnblock 1 0.00% 0.00% system.ruby.TCCdir_Controller.BB_S.LastCoreUnblock 2 0.00% 0.00% -system.ruby.TCCdir_Controller.BBB_S.RdBlk 10 0.00% 0.00% -system.ruby.TCCdir_Controller.BBB_S.CoreUnblock 7 0.00% 0.00% -system.ruby.TCCdir_Controller.BBB_M.RdBlkM 5 0.00% 0.00% +system.ruby.TCCdir_Controller.BBB_S.RdBlk 9 0.00% 0.00% +system.ruby.TCCdir_Controller.BBB_S.CoreUnblock 5 0.00% 0.00% +system.ruby.TCCdir_Controller.BBB_M.RdBlkM 4 0.00% 0.00% system.ruby.TCCdir_Controller.BBB_M.CoreUnblock 9 0.00% 0.00% system.ruby.TCP_Controller.Load | 4 44.44% 44.44% | 5 55.56% 100.00% system.ruby.TCP_Controller.Load::total 9 @@ -3393,9 +3436,9 @@ system.ruby.TCP_Controller.TCC_AckS | 2 50.00% 50.00% | system.ruby.TCP_Controller.TCC_AckS::total 4 system.ruby.TCP_Controller.TCC_AckM | 5 50.00% 50.00% | 5 50.00% 100.00% system.ruby.TCP_Controller.TCC_AckM::total 10 -system.ruby.TCP_Controller.PrbInvData | 1 33.33% 33.33% | 2 66.67% 100.00% +system.ruby.TCP_Controller.PrbInvData | 2 66.67% 66.67% | 1 33.33% 100.00% system.ruby.TCP_Controller.PrbInvData::total 3 -system.ruby.TCP_Controller.PrbShrData | 7 63.64% 63.64% | 4 36.36% 100.00% +system.ruby.TCP_Controller.PrbShrData | 6 54.55% 54.55% | 5 45.45% 100.00% system.ruby.TCP_Controller.PrbShrData::total 11 system.ruby.TCP_Controller.I.Load | 2 50.00% 50.00% | 2 50.00% 100.00% system.ruby.TCP_Controller.I.Load::total 4 @@ -3409,9 +3452,9 @@ system.ruby.TCP_Controller.S.PrbShrData | 2 100.00% 100.00% | system.ruby.TCP_Controller.S.PrbShrData::total 2 system.ruby.TCP_Controller.M.Store | 4 50.00% 50.00% | 4 50.00% 100.00% system.ruby.TCP_Controller.M.Store::total 8 -system.ruby.TCP_Controller.M.PrbInvData | 0 0.00% 0.00% | 1 100.00% 100.00% +system.ruby.TCP_Controller.M.PrbInvData | 1 100.00% 100.00% | 0 0.00% 100.00% system.ruby.TCP_Controller.M.PrbInvData::total 1 -system.ruby.TCP_Controller.M.PrbShrData | 5 55.56% 55.56% | 4 44.44% 100.00% +system.ruby.TCP_Controller.M.PrbShrData | 4 44.44% 44.44% | 5 55.56% 100.00% system.ruby.TCP_Controller.M.PrbShrData::total 9 system.ruby.TCP_Controller.I_M.TCC_AckM | 5 50.00% 50.00% | 5 50.00% 100.00% system.ruby.TCP_Controller.I_M.TCC_AckM::total 10 diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini index 5f60d059c..9b40462e7 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini @@ -177,10 +177,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0 assoc=4 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=false max_miss_count=0 mshrs=4 @@ -194,6 +194,7 @@ response_latency=2 sequential_access=false size=32768 system=system +tag_latency=2 tags=system.cpu0.dcache.tags tgts_per_mshr=20 write_buffers=8 @@ -206,15 +207,16 @@ type=LRU assoc=4 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=32768 +tag_latency=2 [system.cpu0.dtb] type=SparcTLB @@ -292,10 +294,10 @@ pipelined=true [system.cpu0.fuPool.FUList3] type=FUDesc -children=opList0 opList1 opList2 +children=opList0 opList1 opList2 opList3 opList4 count=2 eventq_index=0 -opList=system.cpu0.fuPool.FUList3.opList0 system.cpu0.fuPool.FUList3.opList1 system.cpu0.fuPool.FUList3.opList2 +opList=system.cpu0.fuPool.FUList3.opList0 system.cpu0.fuPool.FUList3.opList1 system.cpu0.fuPool.FUList3.opList2 system.cpu0.fuPool.FUList3.opList3 system.cpu0.fuPool.FUList3.opList4 [system.cpu0.fuPool.FUList3.opList0] type=OpDesc @@ -307,11 +309,25 @@ pipelined=true [system.cpu0.fuPool.FUList3.opList1] type=OpDesc eventq_index=0 +opClass=FloatMultAcc +opLat=5 +pipelined=true + +[system.cpu0.fuPool.FUList3.opList2] +type=OpDesc +eventq_index=0 +opClass=FloatMisc +opLat=3 +pipelined=true + +[system.cpu0.fuPool.FUList3.opList3] +type=OpDesc +eventq_index=0 opClass=FloatDiv opLat=12 pipelined=false -[system.cpu0.fuPool.FUList3.opList2] +[system.cpu0.fuPool.FUList3.opList4] type=OpDesc eventq_index=0 opClass=FloatSqrt @@ -320,18 +336,25 @@ pipelined=false [system.cpu0.fuPool.FUList4] type=FUDesc -children=opList +children=opList0 opList1 count=0 eventq_index=0 -opList=system.cpu0.fuPool.FUList4.opList +opList=system.cpu0.fuPool.FUList4.opList0 system.cpu0.fuPool.FUList4.opList1 -[system.cpu0.fuPool.FUList4.opList] +[system.cpu0.fuPool.FUList4.opList0] type=OpDesc eventq_index=0 opClass=MemRead opLat=1 pipelined=true +[system.cpu0.fuPool.FUList4.opList1] +type=OpDesc +eventq_index=0 +opClass=FloatMemRead +opLat=1 +pipelined=true + [system.cpu0.fuPool.FUList5] type=FUDesc children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 @@ -481,24 +504,31 @@ pipelined=true [system.cpu0.fuPool.FUList6] type=FUDesc -children=opList +children=opList0 opList1 count=0 eventq_index=0 -opList=system.cpu0.fuPool.FUList6.opList +opList=system.cpu0.fuPool.FUList6.opList0 system.cpu0.fuPool.FUList6.opList1 -[system.cpu0.fuPool.FUList6.opList] +[system.cpu0.fuPool.FUList6.opList0] type=OpDesc eventq_index=0 opClass=MemWrite opLat=1 pipelined=true +[system.cpu0.fuPool.FUList6.opList1] +type=OpDesc +eventq_index=0 +opClass=FloatMemWrite +opLat=1 +pipelined=true + [system.cpu0.fuPool.FUList7] type=FUDesc -children=opList0 opList1 +children=opList0 opList1 opList2 opList3 count=4 eventq_index=0 -opList=system.cpu0.fuPool.FUList7.opList0 system.cpu0.fuPool.FUList7.opList1 +opList=system.cpu0.fuPool.FUList7.opList0 system.cpu0.fuPool.FUList7.opList1 system.cpu0.fuPool.FUList7.opList2 system.cpu0.fuPool.FUList7.opList3 [system.cpu0.fuPool.FUList7.opList0] type=OpDesc @@ -514,6 +544,20 @@ opClass=MemWrite opLat=1 pipelined=true +[system.cpu0.fuPool.FUList7.opList2] +type=OpDesc +eventq_index=0 +opClass=FloatMemRead +opLat=1 +pipelined=true + +[system.cpu0.fuPool.FUList7.opList3] +type=OpDesc +eventq_index=0 +opClass=FloatMemWrite +opLat=1 +pipelined=true + [system.cpu0.fuPool.FUList8] type=FUDesc children=opList @@ -535,10 +579,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0 assoc=1 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=true max_miss_count=0 mshrs=4 @@ -552,6 +596,7 @@ response_latency=2 sequential_access=false size=32768 system=system +tag_latency=2 tags=system.cpu0.icache.tags tgts_per_mshr=20 write_buffers=8 @@ -564,15 +609,16 @@ type=LRU assoc=1 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=32768 +tag_latency=2 [system.cpu0.interrupts] type=SparcInterrupts @@ -601,7 +647,7 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/test-progs/m5threads/bin/sparc/linux/test_atomic +executable=/dist/m5/regression/test-progs/m5threads/bin/sparc/linux/test_atomic gid=100 input=cin kvmInSE=false @@ -738,10 +784,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0 assoc=4 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=false max_miss_count=0 mshrs=4 @@ -755,6 +801,7 @@ response_latency=2 sequential_access=false size=32768 system=system +tag_latency=2 tags=system.cpu1.dcache.tags tgts_per_mshr=20 write_buffers=8 @@ -767,15 +814,16 @@ type=LRU assoc=4 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=32768 +tag_latency=2 [system.cpu1.dtb] type=SparcTLB @@ -853,10 +901,10 @@ pipelined=true [system.cpu1.fuPool.FUList3] type=FUDesc -children=opList0 opList1 opList2 +children=opList0 opList1 opList2 opList3 opList4 count=2 eventq_index=0 -opList=system.cpu1.fuPool.FUList3.opList0 system.cpu1.fuPool.FUList3.opList1 system.cpu1.fuPool.FUList3.opList2 +opList=system.cpu1.fuPool.FUList3.opList0 system.cpu1.fuPool.FUList3.opList1 system.cpu1.fuPool.FUList3.opList2 system.cpu1.fuPool.FUList3.opList3 system.cpu1.fuPool.FUList3.opList4 [system.cpu1.fuPool.FUList3.opList0] type=OpDesc @@ -868,11 +916,25 @@ pipelined=true [system.cpu1.fuPool.FUList3.opList1] type=OpDesc eventq_index=0 +opClass=FloatMultAcc +opLat=5 +pipelined=true + +[system.cpu1.fuPool.FUList3.opList2] +type=OpDesc +eventq_index=0 +opClass=FloatMisc +opLat=3 +pipelined=true + +[system.cpu1.fuPool.FUList3.opList3] +type=OpDesc +eventq_index=0 opClass=FloatDiv opLat=12 pipelined=false -[system.cpu1.fuPool.FUList3.opList2] +[system.cpu1.fuPool.FUList3.opList4] type=OpDesc eventq_index=0 opClass=FloatSqrt @@ -881,18 +943,25 @@ pipelined=false [system.cpu1.fuPool.FUList4] type=FUDesc -children=opList +children=opList0 opList1 count=0 eventq_index=0 -opList=system.cpu1.fuPool.FUList4.opList +opList=system.cpu1.fuPool.FUList4.opList0 system.cpu1.fuPool.FUList4.opList1 -[system.cpu1.fuPool.FUList4.opList] +[system.cpu1.fuPool.FUList4.opList0] type=OpDesc eventq_index=0 opClass=MemRead opLat=1 pipelined=true +[system.cpu1.fuPool.FUList4.opList1] +type=OpDesc +eventq_index=0 +opClass=FloatMemRead +opLat=1 +pipelined=true + [system.cpu1.fuPool.FUList5] type=FUDesc children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 @@ -1042,24 +1111,31 @@ pipelined=true [system.cpu1.fuPool.FUList6] type=FUDesc -children=opList +children=opList0 opList1 count=0 eventq_index=0 -opList=system.cpu1.fuPool.FUList6.opList +opList=system.cpu1.fuPool.FUList6.opList0 system.cpu1.fuPool.FUList6.opList1 -[system.cpu1.fuPool.FUList6.opList] +[system.cpu1.fuPool.FUList6.opList0] type=OpDesc eventq_index=0 opClass=MemWrite opLat=1 pipelined=true +[system.cpu1.fuPool.FUList6.opList1] +type=OpDesc +eventq_index=0 +opClass=FloatMemWrite +opLat=1 +pipelined=true + [system.cpu1.fuPool.FUList7] type=FUDesc -children=opList0 opList1 +children=opList0 opList1 opList2 opList3 count=4 eventq_index=0 -opList=system.cpu1.fuPool.FUList7.opList0 system.cpu1.fuPool.FUList7.opList1 +opList=system.cpu1.fuPool.FUList7.opList0 system.cpu1.fuPool.FUList7.opList1 system.cpu1.fuPool.FUList7.opList2 system.cpu1.fuPool.FUList7.opList3 [system.cpu1.fuPool.FUList7.opList0] type=OpDesc @@ -1075,6 +1151,20 @@ opClass=MemWrite opLat=1 pipelined=true +[system.cpu1.fuPool.FUList7.opList2] +type=OpDesc +eventq_index=0 +opClass=FloatMemRead +opLat=1 +pipelined=true + +[system.cpu1.fuPool.FUList7.opList3] +type=OpDesc +eventq_index=0 +opClass=FloatMemWrite +opLat=1 +pipelined=true + [system.cpu1.fuPool.FUList8] type=FUDesc children=opList @@ -1096,10 +1186,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0 assoc=1 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=true max_miss_count=0 mshrs=4 @@ -1113,6 +1203,7 @@ response_latency=2 sequential_access=false size=32768 system=system +tag_latency=2 tags=system.cpu1.icache.tags tgts_per_mshr=20 write_buffers=8 @@ -1125,15 +1216,16 @@ type=LRU assoc=1 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=32768 +tag_latency=2 [system.cpu1.interrupts] type=SparcInterrupts @@ -1276,10 +1368,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0 assoc=4 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=false max_miss_count=0 mshrs=4 @@ -1293,6 +1385,7 @@ response_latency=2 sequential_access=false size=32768 system=system +tag_latency=2 tags=system.cpu2.dcache.tags tgts_per_mshr=20 write_buffers=8 @@ -1305,15 +1398,16 @@ type=LRU assoc=4 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=32768 +tag_latency=2 [system.cpu2.dtb] type=SparcTLB @@ -1391,10 +1485,10 @@ pipelined=true [system.cpu2.fuPool.FUList3] type=FUDesc -children=opList0 opList1 opList2 +children=opList0 opList1 opList2 opList3 opList4 count=2 eventq_index=0 -opList=system.cpu2.fuPool.FUList3.opList0 system.cpu2.fuPool.FUList3.opList1 system.cpu2.fuPool.FUList3.opList2 +opList=system.cpu2.fuPool.FUList3.opList0 system.cpu2.fuPool.FUList3.opList1 system.cpu2.fuPool.FUList3.opList2 system.cpu2.fuPool.FUList3.opList3 system.cpu2.fuPool.FUList3.opList4 [system.cpu2.fuPool.FUList3.opList0] type=OpDesc @@ -1406,11 +1500,25 @@ pipelined=true [system.cpu2.fuPool.FUList3.opList1] type=OpDesc eventq_index=0 +opClass=FloatMultAcc +opLat=5 +pipelined=true + +[system.cpu2.fuPool.FUList3.opList2] +type=OpDesc +eventq_index=0 +opClass=FloatMisc +opLat=3 +pipelined=true + +[system.cpu2.fuPool.FUList3.opList3] +type=OpDesc +eventq_index=0 opClass=FloatDiv opLat=12 pipelined=false -[system.cpu2.fuPool.FUList3.opList2] +[system.cpu2.fuPool.FUList3.opList4] type=OpDesc eventq_index=0 opClass=FloatSqrt @@ -1419,18 +1527,25 @@ pipelined=false [system.cpu2.fuPool.FUList4] type=FUDesc -children=opList +children=opList0 opList1 count=0 eventq_index=0 -opList=system.cpu2.fuPool.FUList4.opList +opList=system.cpu2.fuPool.FUList4.opList0 system.cpu2.fuPool.FUList4.opList1 -[system.cpu2.fuPool.FUList4.opList] +[system.cpu2.fuPool.FUList4.opList0] type=OpDesc eventq_index=0 opClass=MemRead opLat=1 pipelined=true +[system.cpu2.fuPool.FUList4.opList1] +type=OpDesc +eventq_index=0 +opClass=FloatMemRead +opLat=1 +pipelined=true + [system.cpu2.fuPool.FUList5] type=FUDesc children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 @@ -1580,24 +1695,31 @@ pipelined=true [system.cpu2.fuPool.FUList6] type=FUDesc -children=opList +children=opList0 opList1 count=0 eventq_index=0 -opList=system.cpu2.fuPool.FUList6.opList +opList=system.cpu2.fuPool.FUList6.opList0 system.cpu2.fuPool.FUList6.opList1 -[system.cpu2.fuPool.FUList6.opList] +[system.cpu2.fuPool.FUList6.opList0] type=OpDesc eventq_index=0 opClass=MemWrite opLat=1 pipelined=true +[system.cpu2.fuPool.FUList6.opList1] +type=OpDesc +eventq_index=0 +opClass=FloatMemWrite +opLat=1 +pipelined=true + [system.cpu2.fuPool.FUList7] type=FUDesc -children=opList0 opList1 +children=opList0 opList1 opList2 opList3 count=4 eventq_index=0 -opList=system.cpu2.fuPool.FUList7.opList0 system.cpu2.fuPool.FUList7.opList1 +opList=system.cpu2.fuPool.FUList7.opList0 system.cpu2.fuPool.FUList7.opList1 system.cpu2.fuPool.FUList7.opList2 system.cpu2.fuPool.FUList7.opList3 [system.cpu2.fuPool.FUList7.opList0] type=OpDesc @@ -1613,6 +1735,20 @@ opClass=MemWrite opLat=1 pipelined=true +[system.cpu2.fuPool.FUList7.opList2] +type=OpDesc +eventq_index=0 +opClass=FloatMemRead +opLat=1 +pipelined=true + +[system.cpu2.fuPool.FUList7.opList3] +type=OpDesc +eventq_index=0 +opClass=FloatMemWrite +opLat=1 +pipelined=true + [system.cpu2.fuPool.FUList8] type=FUDesc children=opList @@ -1634,10 +1770,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0 assoc=1 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=true max_miss_count=0 mshrs=4 @@ -1651,6 +1787,7 @@ response_latency=2 sequential_access=false size=32768 system=system +tag_latency=2 tags=system.cpu2.icache.tags tgts_per_mshr=20 write_buffers=8 @@ -1663,15 +1800,16 @@ type=LRU assoc=1 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=32768 +tag_latency=2 [system.cpu2.interrupts] type=SparcInterrupts @@ -1814,10 +1952,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0 assoc=4 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=false max_miss_count=0 mshrs=4 @@ -1831,6 +1969,7 @@ response_latency=2 sequential_access=false size=32768 system=system +tag_latency=2 tags=system.cpu3.dcache.tags tgts_per_mshr=20 write_buffers=8 @@ -1843,15 +1982,16 @@ type=LRU assoc=4 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=32768 +tag_latency=2 [system.cpu3.dtb] type=SparcTLB @@ -1929,10 +2069,10 @@ pipelined=true [system.cpu3.fuPool.FUList3] type=FUDesc -children=opList0 opList1 opList2 +children=opList0 opList1 opList2 opList3 opList4 count=2 eventq_index=0 -opList=system.cpu3.fuPool.FUList3.opList0 system.cpu3.fuPool.FUList3.opList1 system.cpu3.fuPool.FUList3.opList2 +opList=system.cpu3.fuPool.FUList3.opList0 system.cpu3.fuPool.FUList3.opList1 system.cpu3.fuPool.FUList3.opList2 system.cpu3.fuPool.FUList3.opList3 system.cpu3.fuPool.FUList3.opList4 [system.cpu3.fuPool.FUList3.opList0] type=OpDesc @@ -1944,11 +2084,25 @@ pipelined=true [system.cpu3.fuPool.FUList3.opList1] type=OpDesc eventq_index=0 +opClass=FloatMultAcc +opLat=5 +pipelined=true + +[system.cpu3.fuPool.FUList3.opList2] +type=OpDesc +eventq_index=0 +opClass=FloatMisc +opLat=3 +pipelined=true + +[system.cpu3.fuPool.FUList3.opList3] +type=OpDesc +eventq_index=0 opClass=FloatDiv opLat=12 pipelined=false -[system.cpu3.fuPool.FUList3.opList2] +[system.cpu3.fuPool.FUList3.opList4] type=OpDesc eventq_index=0 opClass=FloatSqrt @@ -1957,18 +2111,25 @@ pipelined=false [system.cpu3.fuPool.FUList4] type=FUDesc -children=opList +children=opList0 opList1 count=0 eventq_index=0 -opList=system.cpu3.fuPool.FUList4.opList +opList=system.cpu3.fuPool.FUList4.opList0 system.cpu3.fuPool.FUList4.opList1 -[system.cpu3.fuPool.FUList4.opList] +[system.cpu3.fuPool.FUList4.opList0] type=OpDesc eventq_index=0 opClass=MemRead opLat=1 pipelined=true +[system.cpu3.fuPool.FUList4.opList1] +type=OpDesc +eventq_index=0 +opClass=FloatMemRead +opLat=1 +pipelined=true + [system.cpu3.fuPool.FUList5] type=FUDesc children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 @@ -2118,24 +2279,31 @@ pipelined=true [system.cpu3.fuPool.FUList6] type=FUDesc -children=opList +children=opList0 opList1 count=0 eventq_index=0 -opList=system.cpu3.fuPool.FUList6.opList +opList=system.cpu3.fuPool.FUList6.opList0 system.cpu3.fuPool.FUList6.opList1 -[system.cpu3.fuPool.FUList6.opList] +[system.cpu3.fuPool.FUList6.opList0] type=OpDesc eventq_index=0 opClass=MemWrite opLat=1 pipelined=true +[system.cpu3.fuPool.FUList6.opList1] +type=OpDesc +eventq_index=0 +opClass=FloatMemWrite +opLat=1 +pipelined=true + [system.cpu3.fuPool.FUList7] type=FUDesc -children=opList0 opList1 +children=opList0 opList1 opList2 opList3 count=4 eventq_index=0 -opList=system.cpu3.fuPool.FUList7.opList0 system.cpu3.fuPool.FUList7.opList1 +opList=system.cpu3.fuPool.FUList7.opList0 system.cpu3.fuPool.FUList7.opList1 system.cpu3.fuPool.FUList7.opList2 system.cpu3.fuPool.FUList7.opList3 [system.cpu3.fuPool.FUList7.opList0] type=OpDesc @@ -2151,6 +2319,20 @@ opClass=MemWrite opLat=1 pipelined=true +[system.cpu3.fuPool.FUList7.opList2] +type=OpDesc +eventq_index=0 +opClass=FloatMemRead +opLat=1 +pipelined=true + +[system.cpu3.fuPool.FUList7.opList3] +type=OpDesc +eventq_index=0 +opClass=FloatMemWrite +opLat=1 +pipelined=true + [system.cpu3.fuPool.FUList8] type=FUDesc children=opList @@ -2172,10 +2354,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0 assoc=1 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=true max_miss_count=0 mshrs=4 @@ -2189,6 +2371,7 @@ response_latency=2 sequential_access=false size=32768 system=system +tag_latency=2 tags=system.cpu3.icache.tags tgts_per_mshr=20 write_buffers=8 @@ -2201,15 +2384,16 @@ type=LRU assoc=1 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=32768 +tag_latency=2 [system.cpu3.interrupts] type=SparcInterrupts @@ -2251,10 +2435,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0 assoc=8 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=20 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=20 is_read_only=false max_miss_count=0 mshrs=20 @@ -2268,6 +2452,7 @@ response_latency=20 sequential_access=false size=4194304 system=system +tag_latency=20 tags=system.l2c.tags tgts_per_mshr=12 write_buffers=8 @@ -2280,15 +2465,16 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=20 default_p_state=UNDEFINED eventq_index=0 -hit_latency=20 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=4194304 +tag_latency=20 [system.membus] type=CoherentXBar diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout index a478b858e..6cc08c955 100755 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout @@ -3,48 +3,48 @@ Redirecting stderr to build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sp gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Oct 13 2016 20:43:27 -gem5 started Oct 13 2016 20:47:19 -gem5 executing on e108600-lin, pid 17423 -command line: /work/curdun01/gem5-external.hg/build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp +gem5 compiled Nov 29 2016 18:44:12 +gem5 started Nov 29 2016 18:44:33 +gem5 executing on zizzer, pid 58826 +command line: /z/powerjg/gem5-upstream/build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp -re /z/powerjg/gem5-upstream/tests/testing/../run.py quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Init done [Iteration 1, Thread 1] Got lock [Iteration 1, Thread 1] Critical section done, previously next=0, now next=1 -[Iteration 1, Thread 3] Got lock -[Iteration 1, Thread 3] Critical section done, previously next=1, now next=3 [Iteration 1, Thread 2] Got lock -[Iteration 1, Thread 2] Critical section done, previously next=3, now next=2 +[Iteration 1, Thread 2] Critical section done, previously next=1, now next=2 +[Iteration 1, Thread 3] Got lock +[Iteration 1, Thread 3] Critical section done, previously next=2, now next=3 Iteration 1 completed -[Iteration 2, Thread 2] Got lock -[Iteration 2, Thread 2] Critical section done, previously next=0, now next=2 [Iteration 2, Thread 3] Got lock -[Iteration 2, Thread 3] Critical section done, previously next=2, now next=3 +[Iteration 2, Thread 3] Critical section done, previously next=0, now next=3 +[Iteration 2, Thread 2] Got lock +[Iteration 2, Thread 2] Critical section done, previously next=3, now next=2 [Iteration 2, Thread 1] Got lock -[Iteration 2, Thread 1] Critical section done, previously next=3, now next=1 +[Iteration 2, Thread 1] Critical section done, previously next=2, now next=1 Iteration 2 completed -[Iteration 3, Thread 3] Got lock -[Iteration 3, Thread 3] Critical section done, previously next=0, now next=3 [Iteration 3, Thread 1] Got lock -[Iteration 3, Thread 1] Critical section done, previously next=3, now next=1 +[Iteration 3, Thread 1] Critical section done, previously next=0, now next=1 [Iteration 3, Thread 2] Got lock [Iteration 3, Thread 2] Critical section done, previously next=1, now next=2 +[Iteration 3, Thread 3] Got lock +[Iteration 3, Thread 3] Critical section done, previously next=2, now next=3 Iteration 3 completed +[Iteration 4, Thread 3] Got lock +[Iteration 4, Thread 3] Critical section done, previously next=0, now next=3 [Iteration 4, Thread 2] Got lock -[Iteration 4, Thread 2] Critical section done, previously next=0, now next=2 +[Iteration 4, Thread 2] Critical section done, previously next=3, now next=2 [Iteration 4, Thread 1] Got lock [Iteration 4, Thread 1] Critical section done, previously next=2, now next=1 -[Iteration 4, Thread 3] Got lock -[Iteration 4, Thread 3] Critical section done, previously next=1, now next=3 Iteration 4 completed -[Iteration 5, Thread 2] Got lock -[Iteration 5, Thread 2] Critical section done, previously next=0, now next=2 [Iteration 5, Thread 1] Got lock -[Iteration 5, Thread 1] Critical section done, previously next=2, now next=1 +[Iteration 5, Thread 1] Critical section done, previously next=0, now next=1 +[Iteration 5, Thread 2] Got lock +[Iteration 5, Thread 2] Critical section done, previously next=1, now next=2 [Iteration 5, Thread 3] Got lock -[Iteration 5, Thread 3] Critical section done, previously next=1, now next=3 +[Iteration 5, Thread 3] Critical section done, previously next=2, now next=3 Iteration 5 completed [Iteration 6, Thread 3] Got lock [Iteration 6, Thread 3] Critical section done, previously next=0, now next=3 @@ -53,33 +53,33 @@ Iteration 5 completed [Iteration 6, Thread 2] Got lock [Iteration 6, Thread 2] Critical section done, previously next=1, now next=2 Iteration 6 completed +[Iteration 7, Thread 2] Got lock +[Iteration 7, Thread 2] Critical section done, previously next=0, now next=2 [Iteration 7, Thread 1] Got lock -[Iteration 7, Thread 1] Critical section done, previously next=0, now next=1 +[Iteration 7, Thread 1] Critical section done, previously next=2, now next=1 [Iteration 7, Thread 3] Got lock [Iteration 7, Thread 3] Critical section done, previously next=1, now next=3 -[Iteration 7, Thread 2] Got lock -[Iteration 7, Thread 2] Critical section done, previously next=3, now next=2 Iteration 7 completed -[Iteration 8, Thread 1] Got lock -[Iteration 8, Thread 1] Critical section done, previously next=0, now next=1 [Iteration 8, Thread 3] Got lock -[Iteration 8, Thread 3] Critical section done, previously next=1, now next=3 +[Iteration 8, Thread 3] Critical section done, previously next=0, now next=3 [Iteration 8, Thread 2] Got lock [Iteration 8, Thread 2] Critical section done, previously next=3, now next=2 +[Iteration 8, Thread 1] Got lock +[Iteration 8, Thread 1] Critical section done, previously next=2, now next=1 Iteration 8 completed -[Iteration 9, Thread 2] Got lock -[Iteration 9, Thread 2] Critical section done, previously next=0, now next=2 -[Iteration 9, Thread 3] Got lock -[Iteration 9, Thread 3] Critical section done, previously next=2, now next=3 [Iteration 9, Thread 1] Got lock -[Iteration 9, Thread 1] Critical section done, previously next=3, now next=1 +[Iteration 9, Thread 1] Critical section done, previously next=0, now next=1 +[Iteration 9, Thread 3] Got lock +[Iteration 9, Thread 3] Critical section done, previously next=1, now next=3 +[Iteration 9, Thread 2] Got lock +[Iteration 9, Thread 2] Critical section done, previously next=3, now next=2 Iteration 9 completed -[Iteration 10, Thread 1] Got lock -[Iteration 10, Thread 1] Critical section done, previously next=0, now next=1 -[Iteration 10, Thread 3] Got lock -[Iteration 10, Thread 3] Critical section done, previously next=1, now next=3 [Iteration 10, Thread 2] Got lock -[Iteration 10, Thread 2] Critical section done, previously next=3, now next=2 +[Iteration 10, Thread 2] Critical section done, previously next=0, now next=2 +[Iteration 10, Thread 3] Got lock +[Iteration 10, Thread 3] Critical section done, previously next=2, now next=3 +[Iteration 10, Thread 1] Got lock +[Iteration 10, Thread 1] Critical section done, previously next=3, now next=1 Iteration 10 completed PASSED :-) -Exiting @ tick 124830000 because target called exit() +Exiting @ tick 125996000 because target called exit() diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt index f26d1562f..bb1f2fc41 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt @@ -1,81 +1,81 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000125 # Number of seconds simulated -sim_ticks 124830000 # Number of ticks simulated -final_tick 124830000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000126 # Number of seconds simulated +sim_ticks 125996000 # Number of ticks simulated +final_tick 125996000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 284956 # Simulator instruction rate (inst/s) -host_op_rate 284955 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 30713692 # Simulator tick rate (ticks/s) -host_mem_usage 268476 # Number of bytes of host memory used -host_seconds 4.06 # Real time elapsed on the host -sim_insts 1158143 # Number of instructions simulated -sim_ops 1158143 # Number of ops (including micro ops) simulated +host_inst_rate 71299 # Simulator instruction rate (inst/s) +host_op_rate 71299 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 7711593 # Simulator tick rate (ticks/s) +host_mem_usage 250104 # Number of bytes of host memory used +host_seconds 16.34 # Real time elapsed on the host +sim_insts 1164916 # Number of instructions simulated +sim_ops 1164916 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 124830000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu0.inst 24000 # Number of bytes read from this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 125996000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu0.inst 23872 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.data 10880 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.inst 5888 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.data 1408 # Number of bytes read from this memory system.physmem.bytes_read::cpu2.inst 896 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 960 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3.inst 896 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3.data 896 # Number of bytes read from this memory -system.physmem.bytes_read::total 45824 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 24000 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu2.data 896 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3.inst 640 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3.data 960 # Number of bytes read from this memory +system.physmem.bytes_read::total 45440 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 23872 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::cpu1.inst 5888 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::cpu2.inst 896 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu3.inst 896 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 31680 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu0.inst 375 # Number of read requests responded to by this memory +system.physmem.bytes_inst_read::cpu3.inst 640 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 31296 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu0.inst 373 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.data 170 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.inst 92 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.data 22 # Number of read requests responded to by this memory system.physmem.num_reads::cpu2.inst 14 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 15 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3.inst 14 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3.data 14 # Number of read requests responded to by this memory -system.physmem.num_reads::total 716 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu0.inst 192261476 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 87158536 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 47168149 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 11279340 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 7177762 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 7690459 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.inst 7177762 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.data 7177762 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 367091244 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 192261476 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 47168149 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 7177762 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu3.inst 7177762 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 253785148 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 192261476 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 87158536 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 47168149 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 11279340 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 7177762 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 7690459 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.inst 7177762 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.data 7177762 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 367091244 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 716 # Number of read requests accepted +system.physmem.num_reads::cpu2.data 14 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3.inst 10 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3.data 15 # Number of read requests responded to by this memory +system.physmem.num_reads::total 710 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu0.inst 189466332 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 86351948 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 46731642 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 11174958 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 7111337 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 7111337 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.inst 5079526 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.data 7619290 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 360646370 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 189466332 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 46731642 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 7111337 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu3.inst 5079526 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 248388838 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 189466332 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 86351948 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 46731642 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 11174958 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 7111337 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 7111337 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.inst 5079526 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.data 7619290 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 360646370 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 710 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 716 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 710 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 45824 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 45440 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 45824 # Total read bytes from the system interface side +system.physmem.bytesReadSys 45440 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 120 # Per bank write bursts system.physmem.perBankRdBursts::1 44 # Per bank write bursts -system.physmem.perBankRdBursts::2 33 # Per bank write bursts -system.physmem.perBankRdBursts::3 63 # Per bank write bursts +system.physmem.perBankRdBursts::2 31 # Per bank write bursts +system.physmem.perBankRdBursts::3 62 # Per bank write bursts system.physmem.perBankRdBursts::4 69 # Per bank write bursts system.physmem.perBankRdBursts::5 28 # Per bank write bursts system.physmem.perBankRdBursts::6 19 # Per bank write bursts @@ -84,9 +84,9 @@ system.physmem.perBankRdBursts::8 7 # Pe system.physmem.perBankRdBursts::9 31 # Per bank write bursts system.physmem.perBankRdBursts::10 23 # Per bank write bursts system.physmem.perBankRdBursts::11 13 # Per bank write bursts -system.physmem.perBankRdBursts::12 72 # Per bank write bursts +system.physmem.perBankRdBursts::12 70 # Per bank write bursts system.physmem.perBankRdBursts::13 47 # Per bank write bursts -system.physmem.perBankRdBursts::14 19 # Per bank write bursts +system.physmem.perBankRdBursts::14 18 # Per bank write bursts system.physmem.perBankRdBursts::15 101 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts @@ -106,14 +106,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 124590000 # Total gap between requests +system.physmem.totGap 125756000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 716 # Read request sizes (log2) +system.physmem.readPktSize::6 710 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -121,10 +121,10 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 416 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 218 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 59 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 18 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 408 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 221 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 57 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 19 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see @@ -218,475 +218,475 @@ system.physmem.wrQLenPdf::61 0 # Wh system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see system.physmem.bytesPerActivate::samples 174 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 246.436782 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 161.758718 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 247.924177 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 67 38.51% 38.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 43 24.71% 63.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 26 14.94% 78.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 12 6.90% 85.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 7 4.02% 89.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 244.597701 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 161.475219 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 245.687167 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 66 37.93% 37.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 43 24.71% 62.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 29 16.67% 79.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 11 6.32% 85.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 6 3.45% 89.08% # Bytes accessed per row activation system.physmem.bytesPerActivate::640-767 8 4.60% 93.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 3 1.72% 95.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 2 1.15% 96.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 4 2.30% 95.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1 0.57% 96.55% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 6 3.45% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 174 # Bytes accessed per row activation -system.physmem.totQLat 12446750 # Total ticks spent queuing -system.physmem.totMemAccLat 25871750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 3580000 # Total ticks spent in databus transfers -system.physmem.avgQLat 17383.73 # Average queueing delay per DRAM burst +system.physmem.totQLat 13059500 # Total ticks spent queuing +system.physmem.totMemAccLat 26372000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 3550000 # Total ticks spent in databus transfers +system.physmem.avgQLat 18393.66 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 36133.73 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 367.09 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 37143.66 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 360.65 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 367.09 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 360.65 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 2.87 # Data bus utilization in percentage -system.physmem.busUtilRead 2.87 # Data bus utilization in percentage for reads +system.physmem.busUtil 2.82 # Data bus utilization in percentage +system.physmem.busUtilRead 2.82 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.26 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 530 # Number of row buffer hits during reads +system.physmem.readRowHits 525 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 74.02 # Row buffer hit rate for reads +system.physmem.readRowHitRate 73.94 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 174008.38 # Average gap between requests -system.physmem.pageHitRate 74.02 # Row buffer hit rate, read and write combined +system.physmem.avgGap 177121.13 # Average gap between requests +system.physmem.pageHitRate 73.94 # Row buffer hit rate, read and write combined system.physmem_0.actEnergy 856800 # Energy for activate commands per rank (pJ) system.physmem_0.preEnergy 432630 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 2877420 # Energy for read commands per rank (pJ) +system.physmem_0.readEnergy 2856000 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 9834240.000000 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 6410790 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 304320 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 34392090 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 13115040 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 649140.000000 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 68872470 # Total energy per rank (pJ) -system.physmem_0.averagePower 551.730113 # Core power per rank (mW) -system.physmem_0.totalIdleTime 109416750 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 358500 # Time in different power states -system.physmem_0.memoryStateTime::REF 4166000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 403000 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 34152000 # Time in different power states -system.physmem_0.memoryStateTime::ACT 10318500 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 75432000 # Time in different power states -system.physmem_1.actEnergy 471240 # Energy for activate commands per rank (pJ) +system.physmem_0.refreshEnergy 8604960.000000 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 6114390 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 284160 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 31286160 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 8898240 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 5367840 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 64701180 # Total energy per rank (pJ) +system.physmem_0.averagePower 513.516712 # Core power per rank (mW) +system.physmem_0.totalIdleTime 111273500 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 346500 # Time in different power states +system.physmem_0.memoryStateTime::REF 3646000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 20064750 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 23172500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 10159750 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 68606500 # Time in different power states +system.physmem_1.actEnergy 464100 # Energy for activate commands per rank (pJ) system.physmem_1.preEnergy 227700 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 2234820 # Energy for read commands per rank (pJ) +system.physmem_1.readEnergy 2213400 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 9834240.000000 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 5188140 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 617280 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 32401650 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 11725440 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 3565380 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 66265890 # Total energy per rank (pJ) -system.physmem_1.averagePower 530.849075 # Core power per rank (mW) -system.physmem_1.totalIdleTime 111659250 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 1125500 # Time in different power states -system.physmem_1.memoryStateTime::REF 4172000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 10253750 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 30535250 # Time in different power states -system.physmem_1.memoryStateTime::ACT 7679500 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 71064000 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 124830000 # Cumulative time (in ticks) in various power states -system.cpu0.branchPred.lookups 98509 # Number of BP lookups -system.cpu0.branchPred.condPredicted 93993 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 1599 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 95823 # Number of BTB lookups +system.physmem_1.refreshEnergy 8604960.000000 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 4959000 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 596640 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 28649910 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 9231840 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 7511880 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 62459430 # Total energy per rank (pJ) +system.physmem_1.averagePower 495.724516 # Core power per rank (mW) +system.physmem_1.totalIdleTime 113374250 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 1113500 # Time in different power states +system.physmem_1.memoryStateTime::REF 3652000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 26697750 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 24040500 # Time in different power states +system.physmem_1.memoryStateTime::ACT 7662500 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 62829750 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 125996000 # Cumulative time (in ticks) in various power states +system.cpu0.branchPred.lookups 99694 # Number of BP lookups +system.cpu0.branchPred.condPredicted 94929 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 1689 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 96632 # Number of BTB lookups system.cpu0.branchPred.BTBHits 0 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu0.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 1115 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.usedRAS 1210 # Number of times the RAS was used to get a target. system.cpu0.branchPred.RASInCorrect 128 # Number of incorrect RAS predictions. -system.cpu0.branchPred.indirectLookups 95823 # Number of indirect predictor lookups. -system.cpu0.branchPred.indirectHits 88367 # Number of indirect target hits. -system.cpu0.branchPred.indirectMisses 7456 # Number of indirect misses. -system.cpu0.branchPredindirectMispredicted 1077 # Number of mispredicted indirect branches. +system.cpu0.branchPred.indirectLookups 96632 # Number of indirect predictor lookups. +system.cpu0.branchPred.indirectHits 88884 # Number of indirect target hits. +system.cpu0.branchPred.indirectMisses 7748 # Number of indirect misses. +system.cpu0.branchPredindirectMispredicted 1163 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.workload.num_syscalls 89 # Number of system calls -system.cpu0.pwrStateResidencyTicks::ON 124830000 # Cumulative time (in ticks) in various power states -system.cpu0.numCycles 249661 # number of cpu cycles simulated +system.cpu0.pwrStateResidencyTicks::ON 125996000 # Cumulative time (in ticks) in various power states +system.cpu0.numCycles 251993 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 22650 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 581099 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 98509 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 89482 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 193985 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 3497 # Number of cycles fetch has spent squashing +system.cpu0.fetch.icacheStallCycles 23206 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 587602 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 99694 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 90094 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 195641 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 3677 # Number of cycles fetch has spent squashing system.cpu0.fetch.TlbCycles 78 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 2191 # Number of stall cycles due to pending traps -system.cpu0.fetch.IcacheWaitRetryStallCycles 8 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 7995 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 871 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 2245 # Number of stall cycles due to pending traps +system.cpu0.fetch.IcacheWaitRetryStallCycles 21 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 8355 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 903 # Number of outstanding Icache misses that were squashed system.cpu0.fetch.ItlbSquashes 1 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 220664 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 2.633411 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.264413 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::samples 223034 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 2.634585 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.272061 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 33866 15.35% 15.35% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 91353 41.40% 56.75% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 668 0.30% 57.05% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 983 0.45% 57.49% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 516 0.23% 57.73% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 86959 39.41% 97.14% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 734 0.33% 97.47% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 482 0.22% 97.69% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 5103 2.31% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 34543 15.49% 15.49% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 92075 41.28% 56.77% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 690 0.31% 57.08% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 1016 0.46% 57.54% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 496 0.22% 57.76% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 87579 39.27% 97.03% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 656 0.29% 97.32% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 548 0.25% 97.56% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 5431 2.44% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 220664 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.394571 # Number of branch fetches per cycle -system.cpu0.fetch.rate 2.327552 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 17658 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 19166 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 181260 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 832 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 1748 # Number of cycles decode is squashing -system.cpu0.decode.DecodedInsts 563638 # Number of instructions handled by decode -system.cpu0.rename.SquashCycles 1748 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 18349 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 2015 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 15764 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 181386 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 1402 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 558452 # Number of instructions processed by rename -system.cpu0.rename.IQFullEvents 11 # Number of times rename has blocked due to IQ full +system.cpu0.fetch.rateDist::total 223034 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.395622 # Number of branch fetches per cycle +system.cpu0.fetch.rate 2.331819 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 18204 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 19474 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 182674 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 844 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 1838 # Number of cycles decode is squashing +system.cpu0.decode.DecodedInsts 568807 # Number of instructions handled by decode +system.cpu0.rename.SquashCycles 1838 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 18897 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 2138 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 15951 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 182807 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 1403 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 563480 # Number of instructions processed by rename +system.cpu0.rename.IQFullEvents 12 # Number of times rename has blocked due to IQ full system.cpu0.rename.LQFullEvents 11 # Number of times rename has blocked due to LQ full system.cpu0.rename.SQFullEvents 925 # Number of times rename has blocked due to SQ full -system.cpu0.rename.RenamedOperands 382172 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 1112707 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 840550 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 4 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 362927 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 19245 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 1073 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 1102 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 5312 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 178069 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 89965 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 86828 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 86540 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 465662 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 1094 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 461556 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 118 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 16666 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 13597 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 535 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 220664 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 2.091669 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.110492 # Number of insts issued each cycle +system.cpu0.rename.RenamedOperands 385856 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 1122771 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 848321 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 8 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 365359 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 20497 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 1128 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 1160 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 5339 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 179490 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 90635 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 87474 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 87162 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 469651 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 1149 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 465284 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 130 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 17670 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 14278 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 590 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 223034 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 2.086157 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.115238 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 36803 16.68% 16.68% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 4402 1.99% 18.67% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 88094 39.92% 58.60% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 87764 39.77% 98.37% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 1699 0.77% 99.14% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 985 0.45% 99.58% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 568 0.26% 99.84% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 247 0.11% 99.95% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 102 0.05% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 37655 16.88% 16.88% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 4554 2.04% 18.92% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 88787 39.81% 58.73% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 88368 39.62% 98.35% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 1704 0.76% 99.12% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 1021 0.46% 99.58% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 603 0.27% 99.85% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 223 0.10% 99.95% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 119 0.05% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 220664 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 223034 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 129 39.09% 39.09% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 0 0.00% 39.09% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 39.09% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 39.09% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 39.09% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 39.09% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 39.09% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMultAcc 0 0.00% 39.09% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 39.09% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMisc 0 0.00% 39.09% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 39.09% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 39.09% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 39.09% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 39.09% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 39.09% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 39.09% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 39.09% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 39.09% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 39.09% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 39.09% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 39.09% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 39.09% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 39.09% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 39.09% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 39.09% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 39.09% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 39.09% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 39.09% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 39.09% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 39.09% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 39.09% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 77 23.33% 62.42% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 124 37.58% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 140 40.46% 40.46% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 0 0.00% 40.46% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 40.46% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 40.46% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 40.46% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 40.46% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 40.46% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMultAcc 0 0.00% 40.46% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 40.46% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMisc 0 0.00% 40.46% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 40.46% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 40.46% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 40.46% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 40.46% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 40.46% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 40.46% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 40.46% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 40.46% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 40.46% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 40.46% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 40.46% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 40.46% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 40.46% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 40.46% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 40.46% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 40.46% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 40.46% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 40.46% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 40.46% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 40.46% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 40.46% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 83 23.99% 64.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 123 35.55% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::FloatMemRead 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::FloatMemWrite 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 194924 42.23% 42.23% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 0 0.00% 42.23% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 42.23% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 42.23% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 42.23% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 42.23% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 42.23% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMultAcc 0 0.00% 42.23% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 42.23% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMisc 0 0.00% 42.23% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 42.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 42.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 42.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 42.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 42.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 42.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 42.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 42.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 42.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 42.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 42.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 42.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 42.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 42.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 42.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.23% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 177454 38.45% 80.68% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 89178 19.32% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 196646 42.26% 42.26% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 0 0.00% 42.26% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 42.26% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 42.26% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 42.26% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 42.26% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 42.26% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMultAcc 0 0.00% 42.26% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 42.26% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMisc 0 0.00% 42.26% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 42.26% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 42.26% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 42.26% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 42.26% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 42.26% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 42.26% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 42.26% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 42.26% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 42.26% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 42.26% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 42.26% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 42.26% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.26% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.26% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.26% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.26% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.26% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 42.26% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 42.26% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 42.26% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.26% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 178800 38.43% 80.69% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 89838 19.31% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::FloatMemRead 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::FloatMemWrite 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 461556 # Type of FU issued -system.cpu0.iq.rate 1.848731 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 330 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.000715 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 1144224 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 483466 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 458888 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.FU_type_0::total 465284 # Type of FU issued +system.cpu0.iq.rate 1.846416 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 346 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.000744 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 1154078 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 488506 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 462560 # Number of integer instruction queue wakeup accesses system.cpu0.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 8 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_writes 16 # Number of floating instruction queue writes system.cpu0.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 461886 # Number of integer alu accesses +system.cpu0.iq.int_alu_accesses 465630 # Number of integer alu accesses system.cpu0.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 86265 # Number of loads that had data forwarded from stores +system.cpu0.iew.lsq.thread0.forwLoads 86875 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 3016 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 7 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.squashedLoads 3221 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 9 # Number of memory responses ignored because the instruction is squashed system.cpu0.iew.lsq.thread0.memOrderViolation 54 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 1932 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedStores 1994 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu0.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu0.iew.lsq.thread0.cacheBlocked 12 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 1748 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 2015 # Number of cycles IEW is blocking +system.cpu0.iew.iewSquashCycles 1838 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 2137 # Number of cycles IEW is blocking system.cpu0.iew.iewUnblockCycles 29 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 554202 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 154 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 178069 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 89965 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 980 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewDispatchedInsts 558923 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 171 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 179490 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 90635 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 1033 # Number of dispatched non-speculative instructions system.cpu0.iew.iewIQFullEvents 30 # Number of times the IQ has become full, causing a stall system.cpu0.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu0.iew.memOrderViolationEvents 54 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 232 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 1714 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 1946 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 460023 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 177079 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 1533 # Number of squashed instructions skipped in execute +system.cpu0.iew.predictedTakenIncorrect 218 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 1860 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 2078 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 463731 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 178412 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 1553 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 87446 # number of nop insts executed -system.cpu0.iew.exec_refs 266047 # number of memory reference insts executed -system.cpu0.iew.exec_branches 91396 # Number of branches executed -system.cpu0.iew.exec_stores 88968 # Number of stores executed -system.cpu0.iew.exec_rate 1.842591 # Inst execution rate -system.cpu0.iew.wb_sent 459364 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 458888 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 272127 # num instructions producing a value -system.cpu0.iew.wb_consumers 275688 # num instructions consuming a value -system.cpu0.iew.wb_rate 1.838044 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.987083 # average fanout of values written-back -system.cpu0.commit.commitSquashedInsts 17379 # The number of squashed insts skipped by commit +system.cpu0.iew.exec_nop 88123 # number of nop insts executed +system.cpu0.iew.exec_refs 268032 # number of memory reference insts executed +system.cpu0.iew.exec_branches 92124 # Number of branches executed +system.cpu0.iew.exec_stores 89620 # Number of stores executed +system.cpu0.iew.exec_rate 1.840253 # Inst execution rate +system.cpu0.iew.wb_sent 463047 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 462560 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 274104 # num instructions producing a value +system.cpu0.iew.wb_consumers 277790 # num instructions consuming a value +system.cpu0.iew.wb_rate 1.835607 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.986731 # average fanout of values written-back +system.cpu0.commit.commitSquashedInsts 18452 # The number of squashed insts skipped by commit system.cpu0.commit.commitNonSpecStalls 559 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 1599 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 217244 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 2.470687 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 2.142582 # Number of insts commited each cycle +system.cpu0.commit.branchMispredicts 1689 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 219410 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 2.462923 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 2.143392 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 36715 16.90% 16.90% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 90144 41.49% 58.39% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 2018 0.93% 59.32% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 613 0.28% 59.61% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 486 0.22% 59.83% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 86051 39.61% 99.44% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 459 0.21% 99.65% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 294 0.14% 99.79% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 464 0.21% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 37598 17.14% 17.14% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 90827 41.40% 58.53% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 2058 0.94% 59.47% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 592 0.27% 59.74% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 460 0.21% 59.95% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 86620 39.48% 99.43% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 500 0.23% 99.66% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 309 0.14% 99.80% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 446 0.20% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 217244 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 536742 # Number of instructions committed -system.cpu0.commit.committedOps 536742 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 219410 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 540390 # Number of instructions committed +system.cpu0.commit.committedOps 540390 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 263086 # Number of memory references committed -system.cpu0.commit.loads 175053 # Number of loads committed +system.cpu0.commit.refs 264910 # Number of memory references committed +system.cpu0.commit.loads 176269 # Number of loads committed system.cpu0.commit.membars 84 # Number of memory barriers committed -system.cpu0.commit.branches 89920 # Number of branches committed +system.cpu0.commit.branches 90528 # Number of branches committed system.cpu0.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 361258 # Number of committed integer instructions. +system.cpu0.commit.int_insts 363690 # Number of committed integer instructions. system.cpu0.commit.function_calls 223 # Number of function calls committed. -system.cpu0.commit.op_class_0::No_OpClass 86652 16.14% 16.14% # Class of committed instruction -system.cpu0.commit.op_class_0::IntAlu 186920 34.82% 50.97% # Class of committed instruction -system.cpu0.commit.op_class_0::IntMult 0 0.00% 50.97% # Class of committed instruction -system.cpu0.commit.op_class_0::IntDiv 0 0.00% 50.97% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 50.97% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 50.97% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 50.97% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatMult 0 0.00% 50.97% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatMultAcc 0 0.00% 50.97% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 50.97% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatMisc 0 0.00% 50.97% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 50.97% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 50.97% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 50.97% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 50.97% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 50.97% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 50.97% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 50.97% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMult 0 0.00% 50.97% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 50.97% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShift 0 0.00% 50.97% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 50.97% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 50.97% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 50.97% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 50.97% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 50.97% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 50.97% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 50.97% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 50.97% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 50.97% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 50.97% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 50.97% # Class of committed instruction -system.cpu0.commit.op_class_0::MemRead 175137 32.63% 83.60% # Class of committed instruction -system.cpu0.commit.op_class_0::MemWrite 88033 16.40% 100.00% # Class of committed instruction +system.cpu0.commit.op_class_0::No_OpClass 87260 16.15% 16.15% # Class of committed instruction +system.cpu0.commit.op_class_0::IntAlu 188136 34.81% 50.96% # Class of committed instruction +system.cpu0.commit.op_class_0::IntMult 0 0.00% 50.96% # Class of committed instruction +system.cpu0.commit.op_class_0::IntDiv 0 0.00% 50.96% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 50.96% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 50.96% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 50.96% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMult 0 0.00% 50.96% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMultAcc 0 0.00% 50.96% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 50.96% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMisc 0 0.00% 50.96% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 50.96% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 50.96% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 50.96% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 50.96% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 50.96% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 50.96% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 50.96% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMult 0 0.00% 50.96% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 50.96% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShift 0 0.00% 50.96% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 50.96% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 50.96% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 50.96% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 50.96% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 50.96% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 50.96% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 50.96% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 50.96% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 50.96% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 50.96% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 50.96% # Class of committed instruction +system.cpu0.commit.op_class_0::MemRead 176353 32.63% 83.60% # Class of committed instruction +system.cpu0.commit.op_class_0::MemWrite 88641 16.40% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu0.commit.op_class_0::total 536742 # Class of committed instruction -system.cpu0.commit.bw_lim_events 464 # number cycles where commit BW limit reached -system.cpu0.rob.rob_reads 769740 # The number of ROB reads -system.cpu0.rob.rob_writes 1111721 # The number of ROB writes -system.cpu0.timesIdled 320 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 28997 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.committedInsts 450006 # Number of Instructions Simulated -system.cpu0.committedOps 450006 # Number of Ops (including micro ops) Simulated -system.cpu0.cpi 0.554795 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 0.554795 # CPI: Total CPI of All Threads -system.cpu0.ipc 1.802468 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 1.802468 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 822274 # number of integer regfile reads -system.cpu0.int_regfile_writes 370684 # number of integer regfile writes +system.cpu0.commit.op_class_0::total 540390 # Class of committed instruction +system.cpu0.commit.bw_lim_events 446 # number cycles where commit BW limit reached +system.cpu0.rob.rob_reads 776645 # The number of ROB reads +system.cpu0.rob.rob_writes 1121369 # The number of ROB writes +system.cpu0.timesIdled 318 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 28959 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.committedInsts 453046 # Number of Instructions Simulated +system.cpu0.committedOps 453046 # Number of Ops (including micro ops) Simulated +system.cpu0.cpi 0.556219 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 0.556219 # CPI: Total CPI of All Threads +system.cpu0.ipc 1.797852 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 1.797852 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 828824 # number of integer regfile reads +system.cpu0.int_regfile_writes 373673 # number of integer regfile writes system.cpu0.fp_regfile_reads 192 # number of floating regfile reads -system.cpu0.misc_regfile_reads 268168 # number of misc regfile reads +system.cpu0.misc_regfile_reads 270178 # number of misc regfile reads system.cpu0.misc_regfile_writes 564 # number of misc regfile writes -system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 124830000 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 125996000 # Cumulative time (in ticks) in various power states system.cpu0.dcache.tags.replacements 2 # number of replacements -system.cpu0.dcache.tags.tagsinuse 142.144997 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 177494 # Total number of references to valid blocks. +system.cpu0.dcache.tags.tagsinuse 142.283862 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 178830 # Total number of references to valid blocks. system.cpu0.dcache.tags.sampled_refs 172 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 1031.941860 # Average number of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 1039.709302 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 142.144997 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.277627 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.277627 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 142.283862 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.277898 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.277898 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 170 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::0 19 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::1 8 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::2 143 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 0.332031 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 715284 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 715284 # Number of data accesses -system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 124830000 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.ReadReq_hits::cpu0.data 90136 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 90136 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 87436 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 87436 # number of WriteReq hits +system.cpu0.dcache.tags.tag_accesses 720603 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 720603 # Number of data accesses +system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 125996000 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.ReadReq_hits::cpu0.data 90862 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 90862 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 88053 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 88053 # number of WriteReq hits system.cpu0.dcache.SwapReq_hits::cpu0.data 24 # number of SwapReq hits system.cpu0.dcache.SwapReq_hits::total 24 # number of SwapReq hits -system.cpu0.dcache.demand_hits::cpu0.data 177572 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 177572 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 177572 # number of overall hits -system.cpu0.dcache.overall_hits::total 177572 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 571 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 571 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 555 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 555 # number of WriteReq misses +system.cpu0.dcache.demand_hits::cpu0.data 178915 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 178915 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 178915 # number of overall hits +system.cpu0.dcache.overall_hits::total 178915 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 568 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 568 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 546 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 546 # number of WriteReq misses system.cpu0.dcache.SwapReq_misses::cpu0.data 18 # number of SwapReq misses system.cpu0.dcache.SwapReq_misses::total 18 # number of SwapReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1126 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1126 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1126 # number of overall misses -system.cpu0.dcache.overall_misses::total 1126 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 16338000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 16338000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 35699989 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 35699989 # number of WriteReq miss cycles -system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 501500 # number of SwapReq miss cycles -system.cpu0.dcache.SwapReq_miss_latency::total 501500 # number of SwapReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 52037989 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 52037989 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 52037989 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 52037989 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 90707 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 90707 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 87991 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 87991 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.demand_misses::cpu0.data 1114 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1114 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1114 # number of overall misses +system.cpu0.dcache.overall_misses::total 1114 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 16630000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 16630000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 35665989 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 35665989 # number of WriteReq miss cycles +system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 490500 # number of SwapReq miss cycles +system.cpu0.dcache.SwapReq_miss_latency::total 490500 # number of SwapReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 52295989 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 52295989 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 52295989 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 52295989 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 91430 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 91430 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 88599 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 88599 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses) system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 178698 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 178698 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 178698 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 178698 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.006295 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.006295 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.006307 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.006307 # miss rate for WriteReq accesses +system.cpu0.dcache.demand_accesses::cpu0.data 180029 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 180029 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 180029 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 180029 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.006212 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.006212 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.006163 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.006163 # miss rate for WriteReq accesses system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.428571 # miss rate for SwapReq accesses system.cpu0.dcache.SwapReq_miss_rate::total 0.428571 # miss rate for SwapReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.006301 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.006301 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.006301 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.006301 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 28612.959720 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 28612.959720 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 64324.304505 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 64324.304505 # average WriteReq miss latency -system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 27861.111111 # average SwapReq miss latency -system.cpu0.dcache.SwapReq_avg_miss_latency::total 27861.111111 # average SwapReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 46214.910302 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 46214.910302 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 46214.910302 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 46214.910302 # average overall miss latency +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.006188 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.006188 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.006188 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.006188 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 29278.169014 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 29278.169014 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 65322.324176 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 65322.324176 # average WriteReq miss latency +system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 27250 # average SwapReq miss latency +system.cpu0.dcache.SwapReq_avg_miss_latency::total 27250 # average SwapReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 46944.334829 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 46944.334829 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 46944.334829 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 46944.334829 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 885 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 21 # number of cycles access was blocked @@ -695,2000 +695,2005 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs 42.142857 system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.writebacks::writebacks 1 # number of writebacks system.cpu0.dcache.writebacks::total 1 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 369 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 369 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 385 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 385 # number of WriteReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 754 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 754 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 754 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 754 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 202 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 202 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 170 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 170 # number of WriteReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 370 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 370 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 375 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 375 # number of WriteReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 745 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 745 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 745 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 745 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 198 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 198 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 171 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 171 # number of WriteReq MSHR misses system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data 18 # number of SwapReq MSHR misses system.cpu0.dcache.SwapReq_mshr_misses::total 18 # number of SwapReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 372 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 372 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 372 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 372 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 7501000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 7501000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 8169500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 8169500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 483500 # number of SwapReq MSHR miss cycles -system.cpu0.dcache.SwapReq_mshr_miss_latency::total 483500 # number of SwapReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 15670500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 15670500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 15670500 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 15670500 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.002227 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.002227 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.001932 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.001932 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 369 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 369 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 369 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 369 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 7613500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 7613500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 8176500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 8176500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 472500 # number of SwapReq MSHR miss cycles +system.cpu0.dcache.SwapReq_mshr_miss_latency::total 472500 # number of SwapReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 15790000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 15790000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 15790000 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 15790000 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.002166 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.002166 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.001930 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.001930 # mshr miss rate for WriteReq accesses system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.428571 # mshr miss rate for SwapReq accesses system.cpu0.dcache.SwapReq_mshr_miss_rate::total 0.428571 # mshr miss rate for SwapReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.002082 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.002082 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.002082 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.002082 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 37133.663366 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 37133.663366 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 48055.882353 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 48055.882353 # average WriteReq mshr miss latency -system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 26861.111111 # average SwapReq mshr miss latency -system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 26861.111111 # average SwapReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 42125 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 42125 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 42125 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 42125 # average overall mshr miss latency -system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 124830000 # Cumulative time (in ticks) in various power states -system.cpu0.icache.tags.replacements 393 # number of replacements -system.cpu0.icache.tags.tagsinuse 248.700617 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 7078 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 695 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 10.184173 # Average number of references to valid blocks. +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.002050 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.002050 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.002050 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.002050 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 38452.020202 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 38452.020202 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 47815.789474 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 47815.789474 # average WriteReq mshr miss latency +system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 26250 # average SwapReq mshr miss latency +system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 26250 # average SwapReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 42791.327913 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 42791.327913 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 42791.327913 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 42791.327913 # average overall mshr miss latency +system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 125996000 # Cumulative time (in ticks) in various power states +system.cpu0.icache.tags.replacements 391 # number of replacements +system.cpu0.icache.tags.tagsinuse 249.990139 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 7433 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 696 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 10.679598 # Average number of references to valid blocks. system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 248.700617 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.485743 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.485743 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_task_id_blocks::1024 302 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 70 # Occupied blocks per task id +system.cpu0.icache.tags.occ_blocks::cpu0.inst 249.990139 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.488262 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.488262 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_task_id_blocks::1024 305 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 68 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::1 44 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 188 # Occupied blocks per task id -system.cpu0.icache.tags.occ_task_id_percent::1024 0.589844 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 8690 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 8690 # Number of data accesses -system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 124830000 # Cumulative time (in ticks) in various power states -system.cpu0.icache.ReadReq_hits::cpu0.inst 7078 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 7078 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 7078 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 7078 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 7078 # number of overall hits -system.cpu0.icache.overall_hits::total 7078 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 917 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 917 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 917 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 917 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 917 # number of overall misses -system.cpu0.icache.overall_misses::total 917 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 47775500 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 47775500 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 47775500 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 47775500 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 47775500 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 47775500 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 7995 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 7995 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 7995 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 7995 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 7995 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 7995 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.114697 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.114697 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.114697 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.114697 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.114697 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.114697 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 52099.781897 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 52099.781897 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 52099.781897 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 52099.781897 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 52099.781897 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 52099.781897 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 151 # number of cycles access was blocked +system.cpu0.icache.tags.age_task_id_blocks_1024::2 193 # Occupied blocks per task id +system.cpu0.icache.tags.occ_task_id_percent::1024 0.595703 # Percentage of cache occupancy per task id +system.cpu0.icache.tags.tag_accesses 9051 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 9051 # Number of data accesses +system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 125996000 # Cumulative time (in ticks) in various power states +system.cpu0.icache.ReadReq_hits::cpu0.inst 7433 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 7433 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 7433 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 7433 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 7433 # number of overall hits +system.cpu0.icache.overall_hits::total 7433 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 922 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 922 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 922 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 922 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 922 # number of overall misses +system.cpu0.icache.overall_misses::total 922 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 48154500 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 48154500 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 48154500 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 48154500 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 48154500 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 48154500 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 8355 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 8355 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 8355 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 8355 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 8355 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 8355 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.110353 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.110353 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.110353 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.110353 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.110353 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.110353 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 52228.308026 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 52228.308026 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 52228.308026 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 52228.308026 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 52228.308026 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 52228.308026 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 401 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 4 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 8 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 37.750000 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 50.125000 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.icache.writebacks::writebacks 393 # number of writebacks -system.cpu0.icache.writebacks::total 393 # number of writebacks -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 221 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 221 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 221 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 221 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 221 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 221 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 696 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 696 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 696 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 696 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 696 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 696 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 36615000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 36615000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 36615000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 36615000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 36615000 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 36615000 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.087054 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.087054 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.087054 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.087054 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.087054 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.087054 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 52607.758621 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 52607.758621 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 52607.758621 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 52607.758621 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 52607.758621 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 52607.758621 # average overall mshr miss latency -system.cpu1.branchPred.lookups 69942 # Number of BP lookups -system.cpu1.branchPred.condPredicted 62611 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 2168 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 62876 # Number of BTB lookups +system.cpu0.icache.writebacks::writebacks 391 # number of writebacks +system.cpu0.icache.writebacks::total 391 # number of writebacks +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 225 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 225 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 225 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 225 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 225 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 225 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 697 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 697 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 697 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 697 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 697 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 697 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 36741500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 36741500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 36741500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 36741500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 36741500 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 36741500 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.083423 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.083423 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.083423 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.083423 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.083423 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.083423 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 52713.773314 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 52713.773314 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 52713.773314 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 52713.773314 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 52713.773314 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 52713.773314 # average overall mshr miss latency +system.cpu1.branchPred.lookups 67120 # Number of BP lookups +system.cpu1.branchPred.condPredicted 59252 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 2530 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 59078 # Number of BTB lookups system.cpu1.branchPred.BTBHits 0 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu1.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 1880 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.usedRAS 2033 # Number of times the RAS was used to get a target. system.cpu1.branchPred.RASInCorrect 231 # Number of incorrect RAS predictions. -system.cpu1.branchPred.indirectLookups 62876 # Number of indirect predictor lookups. -system.cpu1.branchPred.indirectHits 52518 # Number of indirect target hits. -system.cpu1.branchPred.indirectMisses 10358 # Number of indirect misses. -system.cpu1.branchPredindirectMispredicted 1122 # Number of mispredicted indirect branches. -system.cpu1.pwrStateResidencyTicks::ON 124830000 # Cumulative time (in ticks) in various power states -system.cpu1.numCycles 191834 # number of cpu cycles simulated +system.cpu1.branchPred.indirectLookups 59078 # Number of indirect predictor lookups. +system.cpu1.branchPred.indirectHits 48199 # Number of indirect target hits. +system.cpu1.branchPred.indirectMisses 10879 # Number of indirect misses. +system.cpu1.branchPredindirectMispredicted 1412 # Number of mispredicted indirect branches. +system.cpu1.pwrStateResidencyTicks::ON 125996000 # Cumulative time (in ticks) in various power states +system.cpu1.numCycles 194937 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 35275 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 386727 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 69942 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 54398 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 146033 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 4493 # Number of cycles fetch has spent squashing -system.cpu1.fetch.MiscStallCycles 6 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.icacheStallCycles 38450 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 366689 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 67120 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 50232 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 144025 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 5215 # Number of cycles fetch has spent squashing +system.cpu1.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu1.fetch.NoActiveThreadStallCycles 10 # Number of stall cycles due to no active thread to fetch from -system.cpu1.fetch.PendingTrapStallCycles 1374 # Number of stall cycles due to pending traps -system.cpu1.fetch.IcacheWaitRetryStallCycles 38 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 23469 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 905 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.rateDist::samples 184982 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 2.090620 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.368236 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.PendingTrapStallCycles 1847 # Number of stall cycles due to pending traps +system.cpu1.fetch.IcacheWaitRetryStallCycles 22 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 26490 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 1009 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.rateDist::samples 186966 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 1.961260 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.371242 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 58784 31.78% 31.78% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 61509 33.25% 65.03% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 6216 3.36% 68.39% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 3423 1.85% 70.24% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 694 0.38% 70.62% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 43897 23.73% 94.35% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 1064 0.58% 94.92% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 1288 0.70% 95.62% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 8107 4.38% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 66801 35.73% 35.73% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 58781 31.44% 67.17% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 7398 3.96% 71.13% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 3358 1.80% 72.92% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 642 0.34% 73.26% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 38588 20.64% 93.90% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 1104 0.59% 94.49% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 1446 0.77% 95.27% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 8848 4.73% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 184982 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.364596 # Number of branch fetches per cycle -system.cpu1.fetch.rate 2.015946 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 21795 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 53545 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 103882 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 3504 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 2246 # Number of cycles decode is squashing -system.cpu1.decode.DecodedInsts 357234 # Number of instructions handled by decode -system.cpu1.rename.SquashCycles 2246 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 22757 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 24349 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 13357 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 104467 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 17796 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 350958 # Number of instructions processed by rename -system.cpu1.rename.IQFullEvents 15108 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LQFullEvents 17 # Number of times rename has blocked due to LQ full +system.cpu1.fetch.rateDist::total 186966 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.344316 # Number of branch fetches per cycle +system.cpu1.fetch.rate 1.881064 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 23546 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 62450 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 94215 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 4138 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 2607 # Number of cycles decode is squashing +system.cpu1.decode.DecodedInsts 335701 # Number of instructions handled by decode +system.cpu1.rename.SquashCycles 2607 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 24537 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 29865 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 13172 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 95090 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 21685 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 329147 # Number of instructions processed by rename +system.cpu1.rename.IQFullEvents 18681 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LQFullEvents 15 # Number of times rename has blocked due to LQ full system.cpu1.rename.FullRegisterEvents 3 # Number of times there has been no free registers -system.cpu1.rename.RenamedOperands 246923 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 678000 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 525614 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 22 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 220975 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 25948 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 1579 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 1706 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 23252 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 99419 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 48107 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 46982 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 41894 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 289725 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 6510 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 288968 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 96 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 22905 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 18076 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 1082 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 184982 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 1.562141 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.375121 # Number of insts issued each cycle +system.cpu1.rename.RenamedOperands 231661 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 629076 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 489741 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 26 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 200931 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 30730 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 1664 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 1812 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 26977 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 90636 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 43093 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 42743 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 36583 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 268793 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 7661 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 268125 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 136 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 26316 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 21262 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 1168 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 186966 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 1.434084 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.397924 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 62949 34.03% 34.03% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 21563 11.66% 45.69% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 46877 25.34% 71.03% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 46716 25.25% 96.28% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 3504 1.89% 98.18% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 1701 0.92% 99.10% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 999 0.54% 99.64% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 396 0.21% 99.85% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 277 0.15% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 71753 38.38% 38.38% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 24944 13.34% 51.72% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 41684 22.29% 74.01% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 41301 22.09% 96.10% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 3557 1.90% 98.01% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 1804 0.96% 98.97% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 1118 0.60% 99.57% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 486 0.26% 99.83% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 319 0.17% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 184982 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 186966 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 191 40.04% 40.04% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 0 0.00% 40.04% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 40.04% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 40.04% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 40.04% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 40.04% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 40.04% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMultAcc 0 0.00% 40.04% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 40.04% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMisc 0 0.00% 40.04% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 40.04% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 40.04% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 40.04% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 40.04% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 40.04% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 40.04% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 40.04% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 40.04% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 40.04% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 40.04% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 40.04% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 40.04% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 40.04% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 40.04% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 40.04% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 40.04% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 40.04% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 40.04% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 40.04% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 40.04% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 40.04% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 60 12.58% 52.62% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 226 47.38% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 231 42.39% 42.39% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 0 0.00% 42.39% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 42.39% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 42.39% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 42.39% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 42.39% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 42.39% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMultAcc 0 0.00% 42.39% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 42.39% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMisc 0 0.00% 42.39% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 42.39% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 42.39% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 42.39% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 42.39% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 42.39% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 42.39% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 42.39% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 42.39% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 42.39% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 42.39% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 42.39% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 42.39% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 42.39% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 42.39% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 42.39% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 42.39% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 42.39% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 42.39% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 42.39% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 42.39% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 42.39% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 72 13.21% 55.60% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 242 44.40% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::FloatMemRead 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::FloatMemWrite 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 138690 47.99% 47.99% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 0 0.00% 47.99% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 47.99% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 47.99% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 47.99% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 47.99% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 47.99% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMultAcc 0 0.00% 47.99% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 47.99% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMisc 0 0.00% 47.99% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 47.99% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 47.99% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 47.99% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 47.99% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 47.99% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 47.99% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 47.99% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 47.99% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 47.99% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 47.99% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 47.99% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 47.99% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.99% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.99% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.99% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.99% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.99% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 47.99% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 47.99% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.99% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.99% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 103154 35.70% 83.69% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 47124 16.31% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 130845 48.80% 48.80% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 0 0.00% 48.80% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 48.80% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 48.80% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 48.80% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 48.80% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 48.80% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMultAcc 0 0.00% 48.80% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 48.80% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMisc 0 0.00% 48.80% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 48.80% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 48.80% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 48.80% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 48.80% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 48.80% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 48.80% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 48.80% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 48.80% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 48.80% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 48.80% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.80% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 48.80% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 48.80% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.80% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 48.80% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 48.80% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 48.80% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.80% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 48.80% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.80% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.80% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 95251 35.52% 84.32% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 42029 15.68% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::FloatMemRead 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::FloatMemWrite 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 288968 # Type of FU issued -system.cpu1.iq.rate 1.506344 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 477 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.001651 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 763491 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 319139 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 285378 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.FU_type_0::total 268125 # Type of FU issued +system.cpu1.iq.rate 1.375444 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 545 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.002033 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 723897 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 302756 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 263753 # Number of integer instruction queue wakeup accesses system.cpu1.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 44 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_writes 52 # Number of floating instruction queue writes system.cpu1.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 289445 # Number of integer alu accesses +system.cpu1.iq.int_alu_accesses 268670 # Number of integer alu accesses system.cpu1.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 41785 # Number of loads that had data forwarded from stores +system.cpu1.iew.lsq.thread0.forwLoads 36498 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 4131 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 40 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 43 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 2566 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 4839 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 41 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 38 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 2826 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu1.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu1.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 2246 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 7047 # Number of cycles IEW is blocking +system.cpu1.iew.iewSquashCycles 2607 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 8495 # Number of cycles IEW is blocking system.cpu1.iew.iewUnblockCycles 53 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 344310 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 276 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 99419 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 48107 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 1464 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 36 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewDispatchedInsts 320469 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 297 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 90636 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 43093 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 1513 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 32 # Number of times the IQ has become full, causing a stall system.cpu1.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 43 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 462 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 2268 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 2730 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 286645 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 97925 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 2323 # Number of squashed instructions skipped in execute +system.cpu1.iew.memOrderViolationEvents 38 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 472 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 2728 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 3200 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 265301 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 88817 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 2824 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 48075 # number of nop insts executed -system.cpu1.iew.exec_refs 144750 # number of memory reference insts executed -system.cpu1.iew.exec_branches 58305 # Number of branches executed -system.cpu1.iew.exec_stores 46825 # Number of stores executed -system.cpu1.iew.exec_rate 1.494235 # Inst execution rate -system.cpu1.iew.wb_sent 285841 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 285378 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 162569 # num instructions producing a value -system.cpu1.iew.wb_consumers 170014 # num instructions consuming a value -system.cpu1.iew.wb_rate 1.487630 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.956209 # average fanout of values written-back -system.cpu1.commit.commitSquashedInsts 23932 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 5428 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 2168 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 180468 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 1.775063 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 2.087699 # Number of insts commited each cycle +system.cpu1.iew.exec_nop 44015 # number of nop insts executed +system.cpu1.iew.exec_refs 130506 # number of memory reference insts executed +system.cpu1.iew.exec_branches 54427 # Number of branches executed +system.cpu1.iew.exec_stores 41689 # Number of stores executed +system.cpu1.iew.exec_rate 1.360958 # Inst execution rate +system.cpu1.iew.wb_sent 264333 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 263753 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 148277 # num instructions producing a value +system.cpu1.iew.wb_consumers 156026 # num instructions consuming a value +system.cpu1.iew.wb_rate 1.353017 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.950335 # average fanout of values written-back +system.cpu1.commit.commitSquashedInsts 27498 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 6493 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 2530 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 181716 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 1.612048 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 2.042470 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 67886 37.62% 37.62% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 54714 30.32% 67.93% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 5489 3.04% 70.98% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 6162 3.41% 74.39% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 1291 0.72% 75.11% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 41971 23.26% 98.36% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 718 0.40% 98.76% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 1059 0.59% 99.35% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 1178 0.65% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 77632 42.72% 42.72% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 50511 27.80% 70.52% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 5466 3.01% 73.53% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 7144 3.93% 77.46% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 1253 0.69% 78.15% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 36670 20.18% 98.33% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 792 0.44% 98.76% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 1038 0.57% 99.33% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 1210 0.67% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 180468 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 320342 # Number of instructions committed -system.cpu1.commit.committedOps 320342 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 181716 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 292935 # Number of instructions committed +system.cpu1.commit.committedOps 292935 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 140829 # Number of memory references committed -system.cpu1.commit.loads 95288 # Number of loads committed -system.cpu1.commit.membars 4715 # Number of memory barriers committed -system.cpu1.commit.branches 56221 # Number of branches committed +system.cpu1.commit.refs 126064 # Number of memory references committed +system.cpu1.commit.loads 85797 # Number of loads committed +system.cpu1.commit.membars 5779 # Number of memory barriers committed +system.cpu1.commit.branches 52007 # Number of branches committed system.cpu1.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 219172 # Number of committed integer instructions. +system.cpu1.commit.int_insts 200194 # Number of committed integer instructions. system.cpu1.commit.function_calls 322 # Number of function calls committed. -system.cpu1.commit.op_class_0::No_OpClass 47012 14.68% 14.68% # Class of committed instruction -system.cpu1.commit.op_class_0::IntAlu 127786 39.89% 54.57% # Class of committed instruction -system.cpu1.commit.op_class_0::IntMult 0 0.00% 54.57% # Class of committed instruction -system.cpu1.commit.op_class_0::IntDiv 0 0.00% 54.57% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 54.57% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 54.57% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 54.57% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMult 0 0.00% 54.57% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMultAcc 0 0.00% 54.57% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 54.57% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMisc 0 0.00% 54.57% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 54.57% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 54.57% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 54.57% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 54.57% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 54.57% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 54.57% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 54.57% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMult 0 0.00% 54.57% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 54.57% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShift 0 0.00% 54.57% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 54.57% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 54.57% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 54.57% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 54.57% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 54.57% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 54.57% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 54.57% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 54.57% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 54.57% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 54.57% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 54.57% # Class of committed instruction -system.cpu1.commit.op_class_0::MemRead 100003 31.22% 85.78% # Class of committed instruction -system.cpu1.commit.op_class_0::MemWrite 45541 14.22% 100.00% # Class of committed instruction +system.cpu1.commit.op_class_0::No_OpClass 42797 14.61% 14.61% # Class of committed instruction +system.cpu1.commit.op_class_0::IntAlu 118295 40.38% 54.99% # Class of committed instruction +system.cpu1.commit.op_class_0::IntMult 0 0.00% 54.99% # Class of committed instruction +system.cpu1.commit.op_class_0::IntDiv 0 0.00% 54.99% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 54.99% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 54.99% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 54.99% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMult 0 0.00% 54.99% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMultAcc 0 0.00% 54.99% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 54.99% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMisc 0 0.00% 54.99% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 54.99% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 54.99% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 54.99% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 54.99% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 54.99% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 54.99% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 54.99% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMult 0 0.00% 54.99% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 54.99% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShift 0 0.00% 54.99% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 54.99% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 54.99% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 54.99% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 54.99% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 54.99% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 54.99% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 54.99% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 54.99% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 54.99% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 54.99% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 54.99% # Class of committed instruction +system.cpu1.commit.op_class_0::MemRead 91576 31.26% 86.25% # Class of committed instruction +system.cpu1.commit.op_class_0::MemWrite 40267 13.75% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu1.commit.op_class_0::total 320342 # Class of committed instruction -system.cpu1.commit.bw_lim_events 1178 # number cycles where commit BW limit reached -system.cpu1.rob.rob_reads 522978 # The number of ROB reads -system.cpu1.rob.rob_writes 693117 # The number of ROB writes -system.cpu1.timesIdled 233 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 6852 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 49387 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 268615 # Number of Instructions Simulated -system.cpu1.committedOps 268615 # Number of Ops (including micro ops) Simulated -system.cpu1.cpi 0.714160 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 0.714160 # CPI: Total CPI of All Threads -system.cpu1.ipc 1.400247 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 1.400247 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 497951 # number of integer regfile reads -system.cpu1.int_regfile_writes 231611 # number of integer regfile writes +system.cpu1.commit.op_class_0::total 292935 # Class of committed instruction +system.cpu1.commit.bw_lim_events 1210 # number cycles where commit BW limit reached +system.cpu1.rob.rob_reads 500353 # The number of ROB reads +system.cpu1.rob.rob_writes 646173 # The number of ROB writes +system.cpu1.timesIdled 229 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 7971 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 49399 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 244359 # Number of Instructions Simulated +system.cpu1.committedOps 244359 # Number of Ops (including micro ops) Simulated +system.cpu1.cpi 0.797748 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 0.797748 # CPI: Total CPI of All Threads +system.cpu1.ipc 1.253528 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 1.253528 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 456218 # number of integer regfile reads +system.cpu1.int_regfile_writes 213064 # number of integer regfile writes system.cpu1.fp_regfile_writes 64 # number of floating regfile writes -system.cpu1.misc_regfile_reads 146596 # number of misc regfile reads +system.cpu1.misc_regfile_reads 132445 # number of misc regfile reads system.cpu1.misc_regfile_writes 648 # number of misc regfile writes -system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 124830000 # Cumulative time (in ticks) in various power states +system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 125996000 # Cumulative time (in ticks) in various power states system.cpu1.dcache.tags.replacements 0 # number of replacements -system.cpu1.dcache.tags.tagsinuse 26.433606 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 52423 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 30 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 1747.433333 # Average number of references to valid blocks. +system.cpu1.dcache.tags.tagsinuse 27.060700 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 47652 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 31 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 1537.161290 # Average number of references to valid blocks. system.cpu1.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 26.433606 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.051628 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.051628 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 30 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::1 30 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.058594 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 406876 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 406876 # Number of data accesses -system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 124830000 # Cumulative time (in ticks) in various power states -system.cpu1.dcache.ReadReq_hits::cpu1.data 55612 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 55612 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 45312 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 45312 # number of WriteReq hits -system.cpu1.dcache.SwapReq_hits::cpu1.data 12 # number of SwapReq hits -system.cpu1.dcache.SwapReq_hits::total 12 # number of SwapReq hits -system.cpu1.dcache.demand_hits::cpu1.data 100924 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 100924 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 100924 # number of overall hits -system.cpu1.dcache.overall_hits::total 100924 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 502 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 502 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 162 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 162 # number of WriteReq misses -system.cpu1.dcache.SwapReq_misses::cpu1.data 55 # number of SwapReq misses -system.cpu1.dcache.SwapReq_misses::total 55 # number of SwapReq misses -system.cpu1.dcache.demand_misses::cpu1.data 664 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 664 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 664 # number of overall misses -system.cpu1.dcache.overall_misses::total 664 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 5584500 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 5584500 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 3659500 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 3659500 # number of WriteReq miss cycles -system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 374500 # number of SwapReq miss cycles -system.cpu1.dcache.SwapReq_miss_latency::total 374500 # number of SwapReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 9244000 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 9244000 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 9244000 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 9244000 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 56114 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 56114 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 45474 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 45474 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SwapReq_accesses::cpu1.data 67 # number of SwapReq accesses(hits+misses) -system.cpu1.dcache.SwapReq_accesses::total 67 # number of SwapReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 101588 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 101588 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 101588 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 101588 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.008946 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.008946 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.003562 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.003562 # miss rate for WriteReq accesses -system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.820896 # miss rate for SwapReq accesses -system.cpu1.dcache.SwapReq_miss_rate::total 0.820896 # miss rate for SwapReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.006536 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.006536 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.006536 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.006536 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 11124.501992 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 11124.501992 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 22589.506173 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 22589.506173 # average WriteReq miss latency -system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 6809.090909 # average SwapReq miss latency -system.cpu1.dcache.SwapReq_avg_miss_latency::total 6809.090909 # average SwapReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 13921.686747 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 13921.686747 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 13921.686747 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 13921.686747 # average overall miss latency +system.cpu1.dcache.tags.occ_blocks::cpu1.data 27.060700 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.052853 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.052853 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 31 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::1 23 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 7 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.060547 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 370474 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 370474 # Number of data accesses +system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 125996000 # Cumulative time (in ticks) in various power states +system.cpu1.dcache.ReadReq_hits::cpu1.data 51817 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 51817 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 40051 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 40051 # number of WriteReq hits +system.cpu1.dcache.SwapReq_hits::cpu1.data 14 # number of SwapReq hits +system.cpu1.dcache.SwapReq_hits::total 14 # number of SwapReq hits +system.cpu1.dcache.demand_hits::cpu1.data 91868 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 91868 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 91868 # number of overall hits +system.cpu1.dcache.overall_hits::total 91868 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 471 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 471 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 148 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 148 # number of WriteReq misses +system.cpu1.dcache.SwapReq_misses::cpu1.data 54 # number of SwapReq misses +system.cpu1.dcache.SwapReq_misses::total 54 # number of SwapReq misses +system.cpu1.dcache.demand_misses::cpu1.data 619 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 619 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 619 # number of overall misses +system.cpu1.dcache.overall_misses::total 619 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 4841500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 4841500 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 3638000 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 3638000 # number of WriteReq miss cycles +system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 309000 # number of SwapReq miss cycles +system.cpu1.dcache.SwapReq_miss_latency::total 309000 # number of SwapReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 8479500 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 8479500 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 8479500 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 8479500 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 52288 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 52288 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 40199 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 40199 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SwapReq_accesses::cpu1.data 68 # number of SwapReq accesses(hits+misses) +system.cpu1.dcache.SwapReq_accesses::total 68 # number of SwapReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 92487 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 92487 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 92487 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 92487 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.009008 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.009008 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.003682 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.003682 # miss rate for WriteReq accesses +system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.794118 # miss rate for SwapReq accesses +system.cpu1.dcache.SwapReq_miss_rate::total 0.794118 # miss rate for SwapReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.006693 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.006693 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.006693 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.006693 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 10279.193206 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 10279.193206 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 24581.081081 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 24581.081081 # average WriteReq miss latency +system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 5722.222222 # average SwapReq miss latency +system.cpu1.dcache.SwapReq_avg_miss_latency::total 5722.222222 # average SwapReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 13698.707593 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 13698.707593 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 13698.707593 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 13698.707593 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 340 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 340 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 55 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 55 # number of WriteReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 395 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 395 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 395 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 395 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 162 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 162 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 107 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 107 # number of WriteReq MSHR misses -system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 55 # number of SwapReq MSHR misses -system.cpu1.dcache.SwapReq_mshr_misses::total 55 # number of SwapReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 269 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 269 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 269 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 269 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2129000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2129000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1532000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1532000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 319500 # number of SwapReq MSHR miss cycles -system.cpu1.dcache.SwapReq_mshr_miss_latency::total 319500 # number of SwapReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3661000 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 3661000 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 3661000 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 3661000 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.002887 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.002887 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.002353 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.002353 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.820896 # mshr miss rate for SwapReq accesses -system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.820896 # mshr miss rate for SwapReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.002648 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.002648 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.002648 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.002648 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13141.975309 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13141.975309 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 14317.757009 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 14317.757009 # average WriteReq mshr miss latency -system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 5809.090909 # average SwapReq mshr miss latency -system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 5809.090909 # average SwapReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 13609.665428 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 13609.665428 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 13609.665428 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 13609.665428 # average overall mshr miss latency -system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 124830000 # Cumulative time (in ticks) in various power states -system.cpu1.icache.tags.replacements 556 # number of replacements -system.cpu1.icache.tags.tagsinuse 97.753950 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 22636 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 690 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 32.805797 # Average number of references to valid blocks. +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 312 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 312 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 44 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 44 # number of WriteReq MSHR hits +system.cpu1.dcache.SwapReq_mshr_hits::cpu1.data 1 # number of SwapReq MSHR hits +system.cpu1.dcache.SwapReq_mshr_hits::total 1 # number of SwapReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 356 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 356 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 356 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 356 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 159 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 159 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 104 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 104 # number of WriteReq MSHR misses +system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 53 # number of SwapReq MSHR misses +system.cpu1.dcache.SwapReq_mshr_misses::total 53 # number of SwapReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 263 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 263 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 263 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 263 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1599000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1599000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1536000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1536000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 255000 # number of SwapReq MSHR miss cycles +system.cpu1.dcache.SwapReq_mshr_miss_latency::total 255000 # number of SwapReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3135000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 3135000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 3135000 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 3135000 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.003041 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.003041 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.002587 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.002587 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.779412 # mshr miss rate for SwapReq accesses +system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.779412 # mshr miss rate for SwapReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.002844 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.002844 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.002844 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.002844 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10056.603774 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10056.603774 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 14769.230769 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 14769.230769 # average WriteReq mshr miss latency +system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 4811.320755 # average SwapReq mshr miss latency +system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 4811.320755 # average SwapReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 11920.152091 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 11920.152091 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 11920.152091 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 11920.152091 # average overall mshr miss latency +system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 125996000 # Cumulative time (in ticks) in various power states +system.cpu1.icache.tags.replacements 598 # number of replacements +system.cpu1.icache.tags.tagsinuse 99.304712 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 25606 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 733 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 34.933151 # Average number of references to valid blocks. system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 97.753950 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.190926 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.190926 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_task_id_blocks::1024 134 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::0 14 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::1 119 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id -system.cpu1.icache.tags.occ_task_id_percent::1024 0.261719 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 24159 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 24159 # Number of data accesses -system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 124830000 # Cumulative time (in ticks) in various power states -system.cpu1.icache.ReadReq_hits::cpu1.inst 22636 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 22636 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 22636 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 22636 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 22636 # number of overall hits -system.cpu1.icache.overall_hits::total 22636 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 833 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 833 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 833 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 833 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 833 # number of overall misses -system.cpu1.icache.overall_misses::total 833 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 20006500 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 20006500 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 20006500 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 20006500 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 20006500 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 20006500 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 23469 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 23469 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 23469 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 23469 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 23469 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 23469 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.035494 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.035494 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.035494 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.035494 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.035494 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.035494 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 24017.406963 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 24017.406963 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 24017.406963 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 24017.406963 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 24017.406963 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 24017.406963 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 207 # number of cycles access was blocked +system.cpu1.icache.tags.occ_blocks::cpu1.inst 99.304712 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.193955 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.193955 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_task_id_blocks::1024 135 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::0 19 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::1 102 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 14 # Occupied blocks per task id +system.cpu1.icache.tags.occ_task_id_percent::1024 0.263672 # Percentage of cache occupancy per task id +system.cpu1.icache.tags.tag_accesses 27223 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 27223 # Number of data accesses +system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 125996000 # Cumulative time (in ticks) in various power states +system.cpu1.icache.ReadReq_hits::cpu1.inst 25606 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 25606 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 25606 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 25606 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 25606 # number of overall hits +system.cpu1.icache.overall_hits::total 25606 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 884 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 884 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 884 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 884 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 884 # number of overall misses +system.cpu1.icache.overall_misses::total 884 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 21315000 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 21315000 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 21315000 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 21315000 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 21315000 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 21315000 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 26490 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 26490 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 26490 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 26490 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 26490 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 26490 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.033371 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.033371 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.033371 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.033371 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.033371 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.033371 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 24111.990950 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 24111.990950 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 24111.990950 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 24111.990950 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 24111.990950 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 24111.990950 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 175 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 6 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 5 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 34.500000 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 35 # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.icache.writebacks::writebacks 556 # number of writebacks -system.cpu1.icache.writebacks::total 556 # number of writebacks -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 143 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 143 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 143 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 143 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 143 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 143 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 690 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 690 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 690 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 690 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 690 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 690 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 15540500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 15540500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 15540500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 15540500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 15540500 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 15540500 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.029400 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.029400 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.029400 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.029400 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.029400 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.029400 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 22522.463768 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 22522.463768 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 22522.463768 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 22522.463768 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 22522.463768 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 22522.463768 # average overall mshr miss latency -system.cpu2.branchPred.lookups 60250 # Number of BP lookups -system.cpu2.branchPred.condPredicted 52369 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 2399 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 52178 # Number of BTB lookups +system.cpu1.icache.writebacks::writebacks 598 # number of writebacks +system.cpu1.icache.writebacks::total 598 # number of writebacks +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 151 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 151 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 151 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 151 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 151 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 151 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 733 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 733 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 733 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 733 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 733 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 733 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 16848000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 16848000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 16848000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 16848000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 16848000 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 16848000 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.027671 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.027671 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.027671 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.027671 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.027671 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.027671 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 22984.993179 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 22984.993179 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 22984.993179 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 22984.993179 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 22984.993179 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 22984.993179 # average overall mshr miss latency +system.cpu2.branchPred.lookups 65968 # Number of BP lookups +system.cpu2.branchPred.condPredicted 58235 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 2375 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 57871 # Number of BTB lookups system.cpu2.branchPred.BTBHits 0 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu2.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 1981 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.usedRAS 1935 # Number of times the RAS was used to get a target. system.cpu2.branchPred.RASInCorrect 231 # Number of incorrect RAS predictions. -system.cpu2.branchPred.indirectLookups 52178 # Number of indirect predictor lookups. -system.cpu2.branchPred.indirectHits 41452 # Number of indirect target hits. -system.cpu2.branchPred.indirectMisses 10726 # Number of indirect misses. -system.cpu2.branchPredindirectMispredicted 1295 # Number of mispredicted indirect branches. -system.cpu2.pwrStateResidencyTicks::ON 124830000 # Cumulative time (in ticks) in various power states -system.cpu2.numCycles 191431 # number of cpu cycles simulated +system.cpu2.branchPred.indirectLookups 57871 # Number of indirect predictor lookups. +system.cpu2.branchPred.indirectHits 47609 # Number of indirect target hits. +system.cpu2.branchPred.indirectMisses 10262 # Number of indirect misses. +system.cpu2.branchPredindirectMispredicted 1269 # Number of mispredicted indirect branches. +system.cpu2.pwrStateResidencyTicks::ON 125996000 # Cumulative time (in ticks) in various power states +system.cpu2.numCycles 194536 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 42696 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 319764 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 60250 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 43433 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 142400 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 4955 # Number of cycles fetch has spent squashing +system.cpu2.fetch.icacheStallCycles 39274 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 356927 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 65968 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 49544 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 148178 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 4907 # Number of cycles fetch has spent squashing system.cpu2.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu2.fetch.NoActiveThreadStallCycles 10 # Number of stall cycles due to no active thread to fetch from -system.cpu2.fetch.PendingTrapStallCycles 2218 # Number of stall cycles due to pending traps -system.cpu2.fetch.CacheLines 31580 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 988 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.rateDist::samples 189804 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.684706 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 2.290533 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.PendingTrapStallCycles 1834 # Number of stall cycles due to pending traps +system.cpu2.fetch.CacheLines 28474 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 909 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.rateDist::samples 191752 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.861399 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 2.326800 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 80855 42.60% 42.60% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 54436 28.68% 71.28% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 9994 5.27% 76.54% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 3383 1.78% 78.33% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 680 0.36% 78.69% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 29156 15.36% 94.05% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 1157 0.61% 94.66% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 1395 0.73% 95.39% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 8748 4.61% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 72282 37.70% 37.70% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 59093 30.82% 68.51% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 8567 4.47% 72.98% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 3453 1.80% 74.78% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 714 0.37% 75.15% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 36701 19.14% 94.29% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 1094 0.57% 94.86% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 1368 0.71% 95.58% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 8480 4.42% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 189804 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.314735 # Number of branch fetches per cycle -system.cpu2.fetch.rate 1.670388 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 22561 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 83775 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 75624 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 5357 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 2477 # Number of cycles decode is squashing -system.cpu2.decode.DecodedInsts 288545 # Number of instructions handled by decode -system.cpu2.rename.SquashCycles 2477 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 23562 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 41928 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 13956 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 76490 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 31381 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 281938 # Number of instructions processed by rename -system.cpu2.rename.IQFullEvents 27181 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LQFullEvents 13 # Number of times rename has blocked due to LQ full +system.cpu2.fetch.rateDist::total 191752 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.339104 # Number of branch fetches per cycle +system.cpu2.fetch.rate 1.834761 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 22274 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 72146 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 90170 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 4699 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 2453 # Number of cycles decode is squashing +system.cpu2.decode.DecodedInsts 325978 # Number of instructions handled by decode +system.cpu2.rename.SquashCycles 2453 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 23346 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 35274 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 13410 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 90655 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 26604 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 319217 # Number of instructions processed by rename +system.cpu2.rename.IQFullEvents 22687 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LQFullEvents 17 # Number of times rename has blocked due to LQ full system.cpu2.rename.FullRegisterEvents 2 # Number of times there has been no free registers -system.cpu2.rename.RenamedOperands 195781 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 524561 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 411315 # Number of integer rename lookups -system.cpu2.rename.fp_rename_lookups 32 # Number of floating rename lookups -system.cpu2.rename.CommittedMaps 166026 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 29755 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 1653 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 1783 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 36818 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 74139 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 33614 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 35848 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 27180 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 226553 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 10243 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 228568 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 140 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 25915 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 20426 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 1250 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 189804 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 1.204232 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 1.376602 # Number of insts issued each cycle +system.cpu2.rename.RenamedOperands 222060 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 604225 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 470469 # Number of integer rename lookups +system.cpu2.rename.fp_rename_lookups 26 # Number of floating rename lookups +system.cpu2.rename.CommittedMaps 194795 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 27265 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 1650 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 1793 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 32366 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 87706 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 41007 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 42125 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 34727 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 259651 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 8925 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 260809 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 82 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 24016 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 18768 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 1234 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 191752 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 1.360137 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 1.380681 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 85980 45.30% 45.30% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 32313 17.02% 62.32% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 32235 16.98% 79.31% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 31990 16.85% 96.16% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 3688 1.94% 98.10% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 1698 0.89% 99.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 1058 0.56% 99.56% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 511 0.27% 99.83% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 331 0.17% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 77057 40.19% 40.19% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 28387 14.80% 54.99% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 39839 20.78% 75.77% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 39454 20.58% 96.34% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 3531 1.84% 98.18% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 1665 0.87% 99.05% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 1093 0.57% 99.62% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 433 0.23% 99.85% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 293 0.15% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 189804 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 191752 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 232 44.96% 44.96% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 0 0.00% 44.96% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 0 0.00% 44.96% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 44.96% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 44.96% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 44.96% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 44.96% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMultAcc 0 0.00% 44.96% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 44.96% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMisc 0 0.00% 44.96% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 44.96% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 44.96% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 44.96% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 44.96% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 44.96% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 44.96% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 44.96% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 44.96% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 44.96% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 44.96% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 44.96% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 44.96% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 44.96% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 44.96% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 44.96% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 44.96% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 44.96% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 44.96% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 44.96% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 44.96% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 44.96% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 58 11.24% 56.20% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 226 43.80% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 214 43.32% 43.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 0 0.00% 43.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 0 0.00% 43.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 43.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 43.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 43.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 43.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMultAcc 0 0.00% 43.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 43.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMisc 0 0.00% 43.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 43.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 43.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 43.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 43.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 43.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 43.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 43.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 43.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 43.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 43.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 43.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 43.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 43.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 43.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 43.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 43.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 43.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 43.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 43.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 43.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 43.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 44 8.91% 52.23% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 236 47.77% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::FloatMemRead 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::FloatMemWrite 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 114651 50.16% 50.16% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 0 0.00% 50.16% # Type of FU issued -system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 50.16% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 50.16% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 50.16% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 50.16% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 50.16% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMultAcc 0 0.00% 50.16% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 50.16% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMisc 0 0.00% 50.16% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 50.16% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 50.16% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 50.16% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 50.16% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 50.16% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 50.16% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 50.16% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 50.16% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 50.16% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 50.16% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 50.16% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 50.16% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 50.16% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 50.16% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 50.16% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 50.16% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 50.16% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 50.16% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 50.16% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 50.16% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 50.16% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 81333 35.58% 85.74% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 32584 14.26% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 127216 48.78% 48.78% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 0 0.00% 48.78% # Type of FU issued +system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 48.78% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 48.78% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 48.78% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 48.78% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 48.78% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMultAcc 0 0.00% 48.78% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 48.78% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMisc 0 0.00% 48.78% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 48.78% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 48.78% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 48.78% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 48.78% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 48.78% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 48.78% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 48.78% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 48.78% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 48.78% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 48.78% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.78% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 48.78% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 48.78% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.78% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 48.78% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 48.78% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 48.78% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.78% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 48.78% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.78% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.78% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 93561 35.87% 84.65% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 40032 15.35% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::FloatMemRead 0 0.00% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::FloatMemWrite 0 0.00% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 228568 # Type of FU issued -system.cpu2.iq.rate 1.193997 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 516 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.002258 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 647596 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 262684 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 224391 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.FU_type_0::total 260809 # Type of FU issued +system.cpu2.iq.rate 1.340672 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 494 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.001894 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 713946 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 292577 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 257120 # Number of integer instruction queue wakeup accesses system.cpu2.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads -system.cpu2.iq.fp_inst_queue_writes 64 # Number of floating instruction queue writes +system.cpu2.iq.fp_inst_queue_writes 52 # Number of floating instruction queue writes system.cpu2.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 229084 # Number of integer alu accesses +system.cpu2.iq.int_alu_accesses 261303 # Number of integer alu accesses system.cpu2.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 27120 # Number of loads that had data forwarded from stores +system.cpu2.iew.lsq.thread0.forwLoads 34638 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 4546 # Number of loads squashed -system.cpu2.iew.lsq.thread0.ignoredResponses 31 # Number of memory responses ignored because the instruction is squashed +system.cpu2.iew.lsq.thread0.squashedLoads 4387 # Number of loads squashed +system.cpu2.iew.lsq.thread0.ignoredResponses 24 # Number of memory responses ignored because the instruction is squashed system.cpu2.iew.lsq.thread0.memOrderViolation 37 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 2695 # Number of stores squashed +system.cpu2.iew.lsq.thread0.squashedStores 2568 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu2.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu2.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 2477 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 10821 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 53 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 273857 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 388 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 74139 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 33614 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 1537 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 28 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewSquashCycles 2453 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 9291 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 57 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 312015 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 352 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 87706 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 41007 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 1521 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 36 # Number of times the IQ has become full, causing a stall system.cpu2.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu2.iew.memOrderViolationEvents 37 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 461 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 2611 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 3072 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 225860 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 72453 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 2708 # Number of squashed instructions skipped in execute +system.cpu2.iew.predictedTakenIncorrect 454 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 2525 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 2979 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 258429 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 86072 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 2380 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed -system.cpu2.iew.exec_nop 37061 # number of nop insts executed -system.cpu2.iew.exec_refs 104703 # number of memory reference insts executed -system.cpu2.iew.exec_branches 47570 # Number of branches executed -system.cpu2.iew.exec_stores 32250 # Number of stores executed -system.cpu2.iew.exec_rate 1.179851 # Inst execution rate -system.cpu2.iew.wb_sent 224905 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 224391 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 122751 # num instructions producing a value -system.cpu2.iew.wb_consumers 130504 # num instructions consuming a value -system.cpu2.iew.wb_rate 1.172177 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.940592 # average fanout of values written-back -system.cpu2.commit.commitSquashedInsts 27003 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 8993 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 2399 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 184731 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 1.336127 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 1.921991 # Number of insts commited each cycle +system.cpu2.iew.exec_nop 43439 # number of nop insts executed +system.cpu2.iew.exec_refs 125830 # number of memory reference insts executed +system.cpu2.iew.exec_branches 53606 # Number of branches executed +system.cpu2.iew.exec_stores 39758 # Number of stores executed +system.cpu2.iew.exec_rate 1.328438 # Inst execution rate +system.cpu2.iew.wb_sent 257596 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 257120 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 143610 # num instructions producing a value +system.cpu2.iew.wb_consumers 151220 # num instructions consuming a value +system.cpu2.iew.wb_rate 1.321709 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.949676 # average fanout of values written-back +system.cpu2.commit.commitSquashedInsts 25270 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 7691 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 2375 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 186904 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 1.534044 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 2.009689 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 94349 51.07% 51.07% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 43685 23.65% 74.72% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 5440 2.94% 77.67% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 9609 5.20% 82.87% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 1281 0.69% 83.56% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 27371 14.82% 98.38% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 737 0.40% 98.78% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 1041 0.56% 99.34% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 1218 0.66% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 84130 45.01% 45.01% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 49844 26.67% 71.68% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 5407 2.89% 74.57% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 8359 4.47% 79.05% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 1323 0.71% 79.75% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 34855 18.65% 98.40% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 714 0.38% 98.78% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 1043 0.56% 99.34% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 1229 0.66% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 184731 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 246824 # Number of instructions committed -system.cpu2.commit.committedOps 246824 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 186904 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 286719 # Number of instructions committed +system.cpu2.commit.committedOps 286719 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 100512 # Number of memory references committed -system.cpu2.commit.loads 69593 # Number of loads committed -system.cpu2.commit.membars 8278 # Number of memory barriers committed -system.cpu2.commit.branches 45154 # Number of branches committed +system.cpu2.commit.refs 121758 # Number of memory references committed +system.cpu2.commit.loads 83319 # Number of loads committed +system.cpu2.commit.membars 6971 # Number of memory barriers committed +system.cpu2.commit.branches 51375 # Number of branches committed system.cpu2.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 167790 # Number of committed integer instructions. +system.cpu2.commit.int_insts 195248 # Number of committed integer instructions. system.cpu2.commit.function_calls 322 # Number of function calls committed. -system.cpu2.commit.op_class_0::No_OpClass 35943 14.56% 14.56% # Class of committed instruction -system.cpu2.commit.op_class_0::IntAlu 102091 41.36% 55.92% # Class of committed instruction -system.cpu2.commit.op_class_0::IntMult 0 0.00% 55.92% # Class of committed instruction -system.cpu2.commit.op_class_0::IntDiv 0 0.00% 55.92% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 55.92% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 55.92% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 55.92% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatMult 0 0.00% 55.92% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatMultAcc 0 0.00% 55.92% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 55.92% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatMisc 0 0.00% 55.92% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 55.92% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 55.92% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 55.92% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 55.92% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 55.92% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 55.92% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 55.92% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMult 0 0.00% 55.92% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 55.92% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShift 0 0.00% 55.92% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 55.92% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 55.92% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 55.92% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 55.92% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 55.92% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 55.92% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 55.92% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 55.92% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 55.92% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 55.92% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 55.92% # Class of committed instruction -system.cpu2.commit.op_class_0::MemRead 77871 31.55% 87.47% # Class of committed instruction -system.cpu2.commit.op_class_0::MemWrite 30919 12.53% 100.00% # Class of committed instruction +system.cpu2.commit.op_class_0::No_OpClass 42159 14.70% 14.70% # Class of committed instruction +system.cpu2.commit.op_class_0::IntAlu 115831 40.40% 55.10% # Class of committed instruction +system.cpu2.commit.op_class_0::IntMult 0 0.00% 55.10% # Class of committed instruction +system.cpu2.commit.op_class_0::IntDiv 0 0.00% 55.10% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 55.10% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 55.10% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 55.10% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatMult 0 0.00% 55.10% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatMultAcc 0 0.00% 55.10% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 55.10% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatMisc 0 0.00% 55.10% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 55.10% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 55.10% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 55.10% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 55.10% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 55.10% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 55.10% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 55.10% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMult 0 0.00% 55.10% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 55.10% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShift 0 0.00% 55.10% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 55.10% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 55.10% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 55.10% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 55.10% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 55.10% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 55.10% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 55.10% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 55.10% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 55.10% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 55.10% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 55.10% # Class of committed instruction +system.cpu2.commit.op_class_0::MemRead 90290 31.49% 86.59% # Class of committed instruction +system.cpu2.commit.op_class_0::MemWrite 38439 13.41% 100.00% # Class of committed instruction system.cpu2.commit.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction system.cpu2.commit.op_class_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction system.cpu2.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu2.commit.op_class_0::total 246824 # Class of committed instruction -system.cpu2.commit.bw_lim_events 1218 # number cycles where commit BW limit reached -system.cpu2.rob.rob_reads 456754 # The number of ROB reads -system.cpu2.rob.rob_writes 552779 # The number of ROB writes -system.cpu2.timesIdled 204 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 1627 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 49789 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 202603 # Number of Instructions Simulated -system.cpu2.committedOps 202603 # Number of Ops (including micro ops) Simulated -system.cpu2.cpi 0.944858 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 0.944858 # CPI: Total CPI of All Threads -system.cpu2.ipc 1.058360 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 1.058360 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 379324 # number of integer regfile reads -system.cpu2.int_regfile_writes 178066 # number of integer regfile writes +system.cpu2.commit.op_class_0::total 286719 # Class of committed instruction +system.cpu2.commit.bw_lim_events 1229 # number cycles where commit BW limit reached +system.cpu2.rob.rob_reads 497078 # The number of ROB reads +system.cpu2.rob.rob_writes 628878 # The number of ROB writes +system.cpu2.timesIdled 227 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 2784 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 49801 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 237589 # Number of Instructions Simulated +system.cpu2.committedOps 237589 # Number of Ops (including micro ops) Simulated +system.cpu2.cpi 0.818792 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 0.818792 # CPI: Total CPI of All Threads +system.cpu2.ipc 1.221311 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 1.221311 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 441330 # number of integer regfile reads +system.cpu2.int_regfile_writes 205867 # number of integer regfile writes system.cpu2.fp_regfile_writes 64 # number of floating regfile writes -system.cpu2.misc_regfile_reads 106600 # number of misc regfile reads +system.cpu2.misc_regfile_reads 127741 # number of misc regfile reads system.cpu2.misc_regfile_writes 648 # number of misc regfile writes -system.cpu2.dcache.tags.pwrStateResidencyTicks::UNDEFINED 124830000 # Cumulative time (in ticks) in various power states +system.cpu2.dcache.tags.pwrStateResidencyTicks::UNDEFINED 125996000 # Cumulative time (in ticks) in various power states system.cpu2.dcache.tags.replacements 0 # number of replacements -system.cpu2.dcache.tags.tagsinuse 24.613342 # Cycle average of tags in use -system.cpu2.dcache.tags.total_refs 38229 # Total number of references to valid blocks. -system.cpu2.dcache.tags.sampled_refs 31 # Sample count of references to valid blocks. -system.cpu2.dcache.tags.avg_refs 1233.193548 # Average number of references to valid blocks. +system.cpu2.dcache.tags.tagsinuse 25.326014 # Cycle average of tags in use +system.cpu2.dcache.tags.total_refs 45457 # Total number of references to valid blocks. +system.cpu2.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks. +system.cpu2.dcache.tags.avg_refs 1567.482759 # Average number of references to valid blocks. system.cpu2.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.dcache.tags.occ_blocks::cpu2.data 24.613342 # Average occupied blocks per requestor -system.cpu2.dcache.tags.occ_percent::cpu2.data 0.048073 # Average percentage of cache occupancy -system.cpu2.dcache.tags.occ_percent::total 0.048073 # Average percentage of cache occupancy -system.cpu2.dcache.tags.occ_task_id_blocks::1024 31 # Occupied blocks per task id -system.cpu2.dcache.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id -system.cpu2.dcache.tags.age_task_id_blocks_1024::1 30 # Occupied blocks per task id -system.cpu2.dcache.tags.occ_task_id_percent::1024 0.060547 # Percentage of cache occupancy per task id -system.cpu2.dcache.tags.tag_accesses 305153 # Number of tag accesses -system.cpu2.dcache.tags.data_accesses 305153 # Number of data accesses -system.cpu2.dcache.pwrStateResidencyTicks::UNDEFINED 124830000 # Cumulative time (in ticks) in various power states -system.cpu2.dcache.ReadReq_hits::cpu2.data 44839 # number of ReadReq hits -system.cpu2.dcache.ReadReq_hits::total 44839 # number of ReadReq hits -system.cpu2.dcache.WriteReq_hits::cpu2.data 30714 # number of WriteReq hits -system.cpu2.dcache.WriteReq_hits::total 30714 # number of WriteReq hits -system.cpu2.dcache.SwapReq_hits::cpu2.data 16 # number of SwapReq hits -system.cpu2.dcache.SwapReq_hits::total 16 # number of SwapReq hits -system.cpu2.dcache.demand_hits::cpu2.data 75553 # number of demand (read+write) hits -system.cpu2.dcache.demand_hits::total 75553 # number of demand (read+write) hits -system.cpu2.dcache.overall_hits::cpu2.data 75553 # number of overall hits -system.cpu2.dcache.overall_hits::total 75553 # number of overall hits -system.cpu2.dcache.ReadReq_misses::cpu2.data 467 # number of ReadReq misses -system.cpu2.dcache.ReadReq_misses::total 467 # number of ReadReq misses -system.cpu2.dcache.WriteReq_misses::cpu2.data 136 # number of WriteReq misses -system.cpu2.dcache.WriteReq_misses::total 136 # number of WriteReq misses -system.cpu2.dcache.SwapReq_misses::cpu2.data 53 # number of SwapReq misses -system.cpu2.dcache.SwapReq_misses::total 53 # number of SwapReq misses -system.cpu2.dcache.demand_misses::cpu2.data 603 # number of demand (read+write) misses -system.cpu2.dcache.demand_misses::total 603 # number of demand (read+write) misses -system.cpu2.dcache.overall_misses::cpu2.data 603 # number of overall misses -system.cpu2.dcache.overall_misses::total 603 # number of overall misses -system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 3772500 # number of ReadReq miss cycles -system.cpu2.dcache.ReadReq_miss_latency::total 3772500 # number of ReadReq miss cycles -system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 3722500 # number of WriteReq miss cycles -system.cpu2.dcache.WriteReq_miss_latency::total 3722500 # number of WriteReq miss cycles -system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 339500 # number of SwapReq miss cycles -system.cpu2.dcache.SwapReq_miss_latency::total 339500 # number of SwapReq miss cycles -system.cpu2.dcache.demand_miss_latency::cpu2.data 7495000 # number of demand (read+write) miss cycles -system.cpu2.dcache.demand_miss_latency::total 7495000 # number of demand (read+write) miss cycles -system.cpu2.dcache.overall_miss_latency::cpu2.data 7495000 # number of overall miss cycles -system.cpu2.dcache.overall_miss_latency::total 7495000 # number of overall miss cycles -system.cpu2.dcache.ReadReq_accesses::cpu2.data 45306 # number of ReadReq accesses(hits+misses) -system.cpu2.dcache.ReadReq_accesses::total 45306 # number of ReadReq accesses(hits+misses) -system.cpu2.dcache.WriteReq_accesses::cpu2.data 30850 # number of WriteReq accesses(hits+misses) -system.cpu2.dcache.WriteReq_accesses::total 30850 # number of WriteReq accesses(hits+misses) -system.cpu2.dcache.SwapReq_accesses::cpu2.data 69 # number of SwapReq accesses(hits+misses) -system.cpu2.dcache.SwapReq_accesses::total 69 # number of SwapReq accesses(hits+misses) -system.cpu2.dcache.demand_accesses::cpu2.data 76156 # number of demand (read+write) accesses -system.cpu2.dcache.demand_accesses::total 76156 # number of demand (read+write) accesses -system.cpu2.dcache.overall_accesses::cpu2.data 76156 # number of overall (read+write) accesses -system.cpu2.dcache.overall_accesses::total 76156 # number of overall (read+write) accesses -system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.010308 # miss rate for ReadReq accesses -system.cpu2.dcache.ReadReq_miss_rate::total 0.010308 # miss rate for ReadReq accesses -system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.004408 # miss rate for WriteReq accesses -system.cpu2.dcache.WriteReq_miss_rate::total 0.004408 # miss rate for WriteReq accesses -system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.768116 # miss rate for SwapReq accesses -system.cpu2.dcache.SwapReq_miss_rate::total 0.768116 # miss rate for SwapReq accesses -system.cpu2.dcache.demand_miss_rate::cpu2.data 0.007918 # miss rate for demand accesses -system.cpu2.dcache.demand_miss_rate::total 0.007918 # miss rate for demand accesses -system.cpu2.dcache.overall_miss_rate::cpu2.data 0.007918 # miss rate for overall accesses -system.cpu2.dcache.overall_miss_rate::total 0.007918 # miss rate for overall accesses -system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 8078.158458 # average ReadReq miss latency -system.cpu2.dcache.ReadReq_avg_miss_latency::total 8078.158458 # average ReadReq miss latency -system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 27371.323529 # average WriteReq miss latency -system.cpu2.dcache.WriteReq_avg_miss_latency::total 27371.323529 # average WriteReq miss latency -system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 6405.660377 # average SwapReq miss latency -system.cpu2.dcache.SwapReq_avg_miss_latency::total 6405.660377 # average SwapReq miss latency -system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 12429.519071 # average overall miss latency -system.cpu2.dcache.demand_avg_miss_latency::total 12429.519071 # average overall miss latency -system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 12429.519071 # average overall miss latency -system.cpu2.dcache.overall_avg_miss_latency::total 12429.519071 # average overall miss latency +system.cpu2.dcache.tags.occ_blocks::cpu2.data 25.326014 # Average occupied blocks per requestor +system.cpu2.dcache.tags.occ_percent::cpu2.data 0.049465 # Average percentage of cache occupancy +system.cpu2.dcache.tags.occ_percent::total 0.049465 # Average percentage of cache occupancy +system.cpu2.dcache.tags.occ_task_id_blocks::1024 29 # Occupied blocks per task id +system.cpu2.dcache.tags.age_task_id_blocks_1024::1 25 # Occupied blocks per task id +system.cpu2.dcache.tags.age_task_id_blocks_1024::2 4 # Occupied blocks per task id +system.cpu2.dcache.tags.occ_task_id_percent::1024 0.056641 # Percentage of cache occupancy per task id +system.cpu2.dcache.tags.tag_accesses 359653 # Number of tag accesses +system.cpu2.dcache.tags.data_accesses 359653 # Number of data accesses +system.cpu2.dcache.pwrStateResidencyTicks::UNDEFINED 125996000 # Cumulative time (in ticks) in various power states +system.cpu2.dcache.ReadReq_hits::cpu2.data 50904 # number of ReadReq hits +system.cpu2.dcache.ReadReq_hits::total 50904 # number of ReadReq hits +system.cpu2.dcache.WriteReq_hits::cpu2.data 38221 # number of WriteReq hits +system.cpu2.dcache.WriteReq_hits::total 38221 # number of WriteReq hits +system.cpu2.dcache.SwapReq_hits::cpu2.data 12 # number of SwapReq hits +system.cpu2.dcache.SwapReq_hits::total 12 # number of SwapReq hits +system.cpu2.dcache.demand_hits::cpu2.data 89125 # number of demand (read+write) hits +system.cpu2.dcache.demand_hits::total 89125 # number of demand (read+write) hits +system.cpu2.dcache.overall_hits::cpu2.data 89125 # number of overall hits +system.cpu2.dcache.overall_hits::total 89125 # number of overall hits +system.cpu2.dcache.ReadReq_misses::cpu2.data 505 # number of ReadReq misses +system.cpu2.dcache.ReadReq_misses::total 505 # number of ReadReq misses +system.cpu2.dcache.WriteReq_misses::cpu2.data 144 # number of WriteReq misses +system.cpu2.dcache.WriteReq_misses::total 144 # number of WriteReq misses +system.cpu2.dcache.SwapReq_misses::cpu2.data 62 # number of SwapReq misses +system.cpu2.dcache.SwapReq_misses::total 62 # number of SwapReq misses +system.cpu2.dcache.demand_misses::cpu2.data 649 # number of demand (read+write) misses +system.cpu2.dcache.demand_misses::total 649 # number of demand (read+write) misses +system.cpu2.dcache.overall_misses::cpu2.data 649 # number of overall misses +system.cpu2.dcache.overall_misses::total 649 # number of overall misses +system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 3857000 # number of ReadReq miss cycles +system.cpu2.dcache.ReadReq_miss_latency::total 3857000 # number of ReadReq miss cycles +system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 3021500 # number of WriteReq miss cycles +system.cpu2.dcache.WriteReq_miss_latency::total 3021500 # number of WriteReq miss cycles +system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 367000 # number of SwapReq miss cycles +system.cpu2.dcache.SwapReq_miss_latency::total 367000 # number of SwapReq miss cycles +system.cpu2.dcache.demand_miss_latency::cpu2.data 6878500 # number of demand (read+write) miss cycles +system.cpu2.dcache.demand_miss_latency::total 6878500 # number of demand (read+write) miss cycles +system.cpu2.dcache.overall_miss_latency::cpu2.data 6878500 # number of overall miss cycles +system.cpu2.dcache.overall_miss_latency::total 6878500 # number of overall miss cycles +system.cpu2.dcache.ReadReq_accesses::cpu2.data 51409 # number of ReadReq accesses(hits+misses) +system.cpu2.dcache.ReadReq_accesses::total 51409 # number of ReadReq accesses(hits+misses) +system.cpu2.dcache.WriteReq_accesses::cpu2.data 38365 # number of WriteReq accesses(hits+misses) +system.cpu2.dcache.WriteReq_accesses::total 38365 # number of WriteReq accesses(hits+misses) +system.cpu2.dcache.SwapReq_accesses::cpu2.data 74 # number of SwapReq accesses(hits+misses) +system.cpu2.dcache.SwapReq_accesses::total 74 # number of SwapReq accesses(hits+misses) +system.cpu2.dcache.demand_accesses::cpu2.data 89774 # number of demand (read+write) accesses +system.cpu2.dcache.demand_accesses::total 89774 # number of demand (read+write) accesses +system.cpu2.dcache.overall_accesses::cpu2.data 89774 # number of overall (read+write) accesses +system.cpu2.dcache.overall_accesses::total 89774 # number of overall (read+write) accesses +system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.009823 # miss rate for ReadReq accesses +system.cpu2.dcache.ReadReq_miss_rate::total 0.009823 # miss rate for ReadReq accesses +system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.003753 # miss rate for WriteReq accesses +system.cpu2.dcache.WriteReq_miss_rate::total 0.003753 # miss rate for WriteReq accesses +system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.837838 # miss rate for SwapReq accesses +system.cpu2.dcache.SwapReq_miss_rate::total 0.837838 # miss rate for SwapReq accesses +system.cpu2.dcache.demand_miss_rate::cpu2.data 0.007229 # miss rate for demand accesses +system.cpu2.dcache.demand_miss_rate::total 0.007229 # miss rate for demand accesses +system.cpu2.dcache.overall_miss_rate::cpu2.data 0.007229 # miss rate for overall accesses +system.cpu2.dcache.overall_miss_rate::total 0.007229 # miss rate for overall accesses +system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 7637.623762 # average ReadReq miss latency +system.cpu2.dcache.ReadReq_avg_miss_latency::total 7637.623762 # average ReadReq miss latency +system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 20982.638889 # average WriteReq miss latency +system.cpu2.dcache.WriteReq_avg_miss_latency::total 20982.638889 # average WriteReq miss latency +system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 5919.354839 # average SwapReq miss latency +system.cpu2.dcache.SwapReq_avg_miss_latency::total 5919.354839 # average SwapReq miss latency +system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 10598.613251 # average overall miss latency +system.cpu2.dcache.demand_avg_miss_latency::total 10598.613251 # average overall miss latency +system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 10598.613251 # average overall miss latency +system.cpu2.dcache.overall_avg_miss_latency::total 10598.613251 # average overall miss latency system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data 301 # number of ReadReq MSHR hits -system.cpu2.dcache.ReadReq_mshr_hits::total 301 # number of ReadReq MSHR hits -system.cpu2.dcache.WriteReq_mshr_hits::cpu2.data 34 # number of WriteReq MSHR hits -system.cpu2.dcache.WriteReq_mshr_hits::total 34 # number of WriteReq MSHR hits -system.cpu2.dcache.SwapReq_mshr_hits::cpu2.data 1 # number of SwapReq MSHR hits -system.cpu2.dcache.SwapReq_mshr_hits::total 1 # number of SwapReq MSHR hits -system.cpu2.dcache.demand_mshr_hits::cpu2.data 335 # number of demand (read+write) MSHR hits -system.cpu2.dcache.demand_mshr_hits::total 335 # number of demand (read+write) MSHR hits -system.cpu2.dcache.overall_mshr_hits::cpu2.data 335 # number of overall MSHR hits -system.cpu2.dcache.overall_mshr_hits::total 335 # number of overall MSHR hits -system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 166 # number of ReadReq MSHR misses -system.cpu2.dcache.ReadReq_mshr_misses::total 166 # number of ReadReq MSHR misses -system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 102 # number of WriteReq MSHR misses -system.cpu2.dcache.WriteReq_mshr_misses::total 102 # number of WriteReq MSHR misses -system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 52 # number of SwapReq MSHR misses -system.cpu2.dcache.SwapReq_mshr_misses::total 52 # number of SwapReq MSHR misses -system.cpu2.dcache.demand_mshr_misses::cpu2.data 268 # number of demand (read+write) MSHR misses -system.cpu2.dcache.demand_mshr_misses::total 268 # number of demand (read+write) MSHR misses -system.cpu2.dcache.overall_mshr_misses::cpu2.data 268 # number of overall MSHR misses -system.cpu2.dcache.overall_mshr_misses::total 268 # number of overall MSHR misses -system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 1217000 # number of ReadReq MSHR miss cycles -system.cpu2.dcache.ReadReq_mshr_miss_latency::total 1217000 # number of ReadReq MSHR miss cycles -system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1941500 # number of WriteReq MSHR miss cycles -system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1941500 # number of WriteReq MSHR miss cycles -system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 286500 # number of SwapReq MSHR miss cycles -system.cpu2.dcache.SwapReq_mshr_miss_latency::total 286500 # number of SwapReq MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 3158500 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_latency::total 3158500 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 3158500 # number of overall MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_latency::total 3158500 # number of overall MSHR miss cycles -system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003664 # mshr miss rate for ReadReq accesses -system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003664 # mshr miss rate for ReadReq accesses -system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.003306 # mshr miss rate for WriteReq accesses -system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.003306 # mshr miss rate for WriteReq accesses -system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.753623 # mshr miss rate for SwapReq accesses -system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.753623 # mshr miss rate for SwapReq accesses -system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.003519 # mshr miss rate for demand accesses -system.cpu2.dcache.demand_mshr_miss_rate::total 0.003519 # mshr miss rate for demand accesses -system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.003519 # mshr miss rate for overall accesses -system.cpu2.dcache.overall_mshr_miss_rate::total 0.003519 # mshr miss rate for overall accesses -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 7331.325301 # average ReadReq mshr miss latency -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 7331.325301 # average ReadReq mshr miss latency -system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 19034.313725 # average WriteReq mshr miss latency -system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 19034.313725 # average WriteReq mshr miss latency -system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 5509.615385 # average SwapReq mshr miss latency -system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 5509.615385 # average SwapReq mshr miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 11785.447761 # average overall mshr miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency::total 11785.447761 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 11785.447761 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency::total 11785.447761 # average overall mshr miss latency -system.cpu2.icache.tags.pwrStateResidencyTicks::UNDEFINED 124830000 # Cumulative time (in ticks) in various power states -system.cpu2.icache.tags.replacements 564 # number of replacements -system.cpu2.icache.tags.tagsinuse 92.356205 # Cycle average of tags in use -system.cpu2.icache.tags.total_refs 30734 # Total number of references to valid blocks. -system.cpu2.icache.tags.sampled_refs 702 # Sample count of references to valid blocks. -system.cpu2.icache.tags.avg_refs 43.780627 # Average number of references to valid blocks. +system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data 337 # number of ReadReq MSHR hits +system.cpu2.dcache.ReadReq_mshr_hits::total 337 # number of ReadReq MSHR hits +system.cpu2.dcache.WriteReq_mshr_hits::cpu2.data 41 # number of WriteReq MSHR hits +system.cpu2.dcache.WriteReq_mshr_hits::total 41 # number of WriteReq MSHR hits +system.cpu2.dcache.demand_mshr_hits::cpu2.data 378 # number of demand (read+write) MSHR hits +system.cpu2.dcache.demand_mshr_hits::total 378 # number of demand (read+write) MSHR hits +system.cpu2.dcache.overall_mshr_hits::cpu2.data 378 # number of overall MSHR hits +system.cpu2.dcache.overall_mshr_hits::total 378 # number of overall MSHR hits +system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 168 # number of ReadReq MSHR misses +system.cpu2.dcache.ReadReq_mshr_misses::total 168 # number of ReadReq MSHR misses +system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 103 # number of WriteReq MSHR misses +system.cpu2.dcache.WriteReq_mshr_misses::total 103 # number of WriteReq MSHR misses +system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 62 # number of SwapReq MSHR misses +system.cpu2.dcache.SwapReq_mshr_misses::total 62 # number of SwapReq MSHR misses +system.cpu2.dcache.demand_mshr_misses::cpu2.data 271 # number of demand (read+write) MSHR misses +system.cpu2.dcache.demand_mshr_misses::total 271 # number of demand (read+write) MSHR misses +system.cpu2.dcache.overall_mshr_misses::cpu2.data 271 # number of overall MSHR misses +system.cpu2.dcache.overall_mshr_misses::total 271 # number of overall MSHR misses +system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 1115500 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_latency::total 1115500 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1450500 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1450500 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 305000 # number of SwapReq MSHR miss cycles +system.cpu2.dcache.SwapReq_mshr_miss_latency::total 305000 # number of SwapReq MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 2566000 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_latency::total 2566000 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 2566000 # number of overall MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_latency::total 2566000 # number of overall MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003268 # mshr miss rate for ReadReq accesses +system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003268 # mshr miss rate for ReadReq accesses +system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.002685 # mshr miss rate for WriteReq accesses +system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.002685 # mshr miss rate for WriteReq accesses +system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.837838 # mshr miss rate for SwapReq accesses +system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.837838 # mshr miss rate for SwapReq accesses +system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.003019 # mshr miss rate for demand accesses +system.cpu2.dcache.demand_mshr_miss_rate::total 0.003019 # mshr miss rate for demand accesses +system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.003019 # mshr miss rate for overall accesses +system.cpu2.dcache.overall_mshr_miss_rate::total 0.003019 # mshr miss rate for overall accesses +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 6639.880952 # average ReadReq mshr miss latency +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 6639.880952 # average ReadReq mshr miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 14082.524272 # average WriteReq mshr miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 14082.524272 # average WriteReq mshr miss latency +system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 4919.354839 # average SwapReq mshr miss latency +system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 4919.354839 # average SwapReq mshr miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 9468.634686 # average overall mshr miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency::total 9468.634686 # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 9468.634686 # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency::total 9468.634686 # average overall mshr miss latency +system.cpu2.icache.tags.pwrStateResidencyTicks::UNDEFINED 125996000 # Cumulative time (in ticks) in various power states +system.cpu2.icache.tags.replacements 551 # number of replacements +system.cpu2.icache.tags.tagsinuse 96.895068 # Cycle average of tags in use +system.cpu2.icache.tags.total_refs 27659 # Total number of references to valid blocks. +system.cpu2.icache.tags.sampled_refs 687 # Sample count of references to valid blocks. +system.cpu2.icache.tags.avg_refs 40.260553 # Average number of references to valid blocks. system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.icache.tags.occ_blocks::cpu2.inst 92.356205 # Average occupied blocks per requestor -system.cpu2.icache.tags.occ_percent::cpu2.inst 0.180383 # Average percentage of cache occupancy -system.cpu2.icache.tags.occ_percent::total 0.180383 # Average percentage of cache occupancy -system.cpu2.icache.tags.occ_task_id_blocks::1024 138 # Occupied blocks per task id -system.cpu2.icache.tags.age_task_id_blocks_1024::0 19 # Occupied blocks per task id -system.cpu2.icache.tags.age_task_id_blocks_1024::1 119 # Occupied blocks per task id -system.cpu2.icache.tags.occ_task_id_percent::1024 0.269531 # Percentage of cache occupancy per task id -system.cpu2.icache.tags.tag_accesses 32282 # Number of tag accesses -system.cpu2.icache.tags.data_accesses 32282 # Number of data accesses -system.cpu2.icache.pwrStateResidencyTicks::UNDEFINED 124830000 # Cumulative time (in ticks) in various power states -system.cpu2.icache.ReadReq_hits::cpu2.inst 30734 # number of ReadReq hits -system.cpu2.icache.ReadReq_hits::total 30734 # number of ReadReq hits -system.cpu2.icache.demand_hits::cpu2.inst 30734 # number of demand (read+write) hits -system.cpu2.icache.demand_hits::total 30734 # number of demand (read+write) hits -system.cpu2.icache.overall_hits::cpu2.inst 30734 # number of overall hits -system.cpu2.icache.overall_hits::total 30734 # number of overall hits -system.cpu2.icache.ReadReq_misses::cpu2.inst 846 # number of ReadReq misses -system.cpu2.icache.ReadReq_misses::total 846 # number of ReadReq misses -system.cpu2.icache.demand_misses::cpu2.inst 846 # number of demand (read+write) misses -system.cpu2.icache.demand_misses::total 846 # number of demand (read+write) misses -system.cpu2.icache.overall_misses::cpu2.inst 846 # number of overall misses -system.cpu2.icache.overall_misses::total 846 # number of overall misses -system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 12713000 # number of ReadReq miss cycles -system.cpu2.icache.ReadReq_miss_latency::total 12713000 # number of ReadReq miss cycles -system.cpu2.icache.demand_miss_latency::cpu2.inst 12713000 # number of demand (read+write) miss cycles -system.cpu2.icache.demand_miss_latency::total 12713000 # number of demand (read+write) miss cycles -system.cpu2.icache.overall_miss_latency::cpu2.inst 12713000 # number of overall miss cycles -system.cpu2.icache.overall_miss_latency::total 12713000 # number of overall miss cycles -system.cpu2.icache.ReadReq_accesses::cpu2.inst 31580 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.ReadReq_accesses::total 31580 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.demand_accesses::cpu2.inst 31580 # number of demand (read+write) accesses -system.cpu2.icache.demand_accesses::total 31580 # number of demand (read+write) accesses -system.cpu2.icache.overall_accesses::cpu2.inst 31580 # number of overall (read+write) accesses -system.cpu2.icache.overall_accesses::total 31580 # number of overall (read+write) accesses -system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.026789 # miss rate for ReadReq accesses -system.cpu2.icache.ReadReq_miss_rate::total 0.026789 # miss rate for ReadReq accesses -system.cpu2.icache.demand_miss_rate::cpu2.inst 0.026789 # miss rate for demand accesses -system.cpu2.icache.demand_miss_rate::total 0.026789 # miss rate for demand accesses -system.cpu2.icache.overall_miss_rate::cpu2.inst 0.026789 # miss rate for overall accesses -system.cpu2.icache.overall_miss_rate::total 0.026789 # miss rate for overall accesses -system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 15027.186761 # average ReadReq miss latency -system.cpu2.icache.ReadReq_avg_miss_latency::total 15027.186761 # average ReadReq miss latency -system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 15027.186761 # average overall miss latency -system.cpu2.icache.demand_avg_miss_latency::total 15027.186761 # average overall miss latency -system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 15027.186761 # average overall miss latency -system.cpu2.icache.overall_avg_miss_latency::total 15027.186761 # average overall miss latency +system.cpu2.icache.tags.occ_blocks::cpu2.inst 96.895068 # Average occupied blocks per requestor +system.cpu2.icache.tags.occ_percent::cpu2.inst 0.189248 # Average percentage of cache occupancy +system.cpu2.icache.tags.occ_percent::total 0.189248 # Average percentage of cache occupancy +system.cpu2.icache.tags.occ_task_id_blocks::1024 136 # Occupied blocks per task id +system.cpu2.icache.tags.age_task_id_blocks_1024::0 8 # Occupied blocks per task id +system.cpu2.icache.tags.age_task_id_blocks_1024::1 116 # Occupied blocks per task id +system.cpu2.icache.tags.age_task_id_blocks_1024::2 12 # Occupied blocks per task id +system.cpu2.icache.tags.occ_task_id_percent::1024 0.265625 # Percentage of cache occupancy per task id +system.cpu2.icache.tags.tag_accesses 29161 # Number of tag accesses +system.cpu2.icache.tags.data_accesses 29161 # Number of data accesses +system.cpu2.icache.pwrStateResidencyTicks::UNDEFINED 125996000 # Cumulative time (in ticks) in various power states +system.cpu2.icache.ReadReq_hits::cpu2.inst 27659 # number of ReadReq hits +system.cpu2.icache.ReadReq_hits::total 27659 # number of ReadReq hits +system.cpu2.icache.demand_hits::cpu2.inst 27659 # number of demand (read+write) hits +system.cpu2.icache.demand_hits::total 27659 # number of demand (read+write) hits +system.cpu2.icache.overall_hits::cpu2.inst 27659 # number of overall hits +system.cpu2.icache.overall_hits::total 27659 # number of overall hits +system.cpu2.icache.ReadReq_misses::cpu2.inst 815 # number of ReadReq misses +system.cpu2.icache.ReadReq_misses::total 815 # number of ReadReq misses +system.cpu2.icache.demand_misses::cpu2.inst 815 # number of demand (read+write) misses +system.cpu2.icache.demand_misses::total 815 # number of demand (read+write) misses +system.cpu2.icache.overall_misses::cpu2.inst 815 # number of overall misses +system.cpu2.icache.overall_misses::total 815 # number of overall misses +system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 12882000 # number of ReadReq miss cycles +system.cpu2.icache.ReadReq_miss_latency::total 12882000 # number of ReadReq miss cycles +system.cpu2.icache.demand_miss_latency::cpu2.inst 12882000 # number of demand (read+write) miss cycles +system.cpu2.icache.demand_miss_latency::total 12882000 # number of demand (read+write) miss cycles +system.cpu2.icache.overall_miss_latency::cpu2.inst 12882000 # number of overall miss cycles +system.cpu2.icache.overall_miss_latency::total 12882000 # number of overall miss cycles +system.cpu2.icache.ReadReq_accesses::cpu2.inst 28474 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.ReadReq_accesses::total 28474 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.demand_accesses::cpu2.inst 28474 # number of demand (read+write) accesses +system.cpu2.icache.demand_accesses::total 28474 # number of demand (read+write) accesses +system.cpu2.icache.overall_accesses::cpu2.inst 28474 # number of overall (read+write) accesses +system.cpu2.icache.overall_accesses::total 28474 # number of overall (read+write) accesses +system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.028623 # miss rate for ReadReq accesses +system.cpu2.icache.ReadReq_miss_rate::total 0.028623 # miss rate for ReadReq accesses +system.cpu2.icache.demand_miss_rate::cpu2.inst 0.028623 # miss rate for demand accesses +system.cpu2.icache.demand_miss_rate::total 0.028623 # miss rate for demand accesses +system.cpu2.icache.overall_miss_rate::cpu2.inst 0.028623 # miss rate for overall accesses +system.cpu2.icache.overall_miss_rate::total 0.028623 # miss rate for overall accesses +system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 15806.134969 # average ReadReq miss latency +system.cpu2.icache.ReadReq_avg_miss_latency::total 15806.134969 # average ReadReq miss latency +system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 15806.134969 # average overall miss latency +system.cpu2.icache.demand_avg_miss_latency::total 15806.134969 # average overall miss latency +system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 15806.134969 # average overall miss latency +system.cpu2.icache.overall_avg_miss_latency::total 15806.134969 # average overall miss latency system.cpu2.icache.blocked_cycles::no_mshrs 48 # number of cycles access was blocked system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.icache.blocked::no_mshrs 2 # number of cycles access was blocked system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu2.icache.avg_blocked_cycles::no_mshrs 24 # average number of cycles each access was blocked system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu2.icache.writebacks::writebacks 564 # number of writebacks -system.cpu2.icache.writebacks::total 564 # number of writebacks -system.cpu2.icache.ReadReq_mshr_hits::cpu2.inst 144 # number of ReadReq MSHR hits -system.cpu2.icache.ReadReq_mshr_hits::total 144 # number of ReadReq MSHR hits -system.cpu2.icache.demand_mshr_hits::cpu2.inst 144 # number of demand (read+write) MSHR hits -system.cpu2.icache.demand_mshr_hits::total 144 # number of demand (read+write) MSHR hits -system.cpu2.icache.overall_mshr_hits::cpu2.inst 144 # number of overall MSHR hits -system.cpu2.icache.overall_mshr_hits::total 144 # number of overall MSHR hits -system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst 702 # number of ReadReq MSHR misses -system.cpu2.icache.ReadReq_mshr_misses::total 702 # number of ReadReq MSHR misses -system.cpu2.icache.demand_mshr_misses::cpu2.inst 702 # number of demand (read+write) MSHR misses -system.cpu2.icache.demand_mshr_misses::total 702 # number of demand (read+write) MSHR misses -system.cpu2.icache.overall_mshr_misses::cpu2.inst 702 # number of overall MSHR misses -system.cpu2.icache.overall_mshr_misses::total 702 # number of overall MSHR misses -system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 10591000 # number of ReadReq MSHR miss cycles -system.cpu2.icache.ReadReq_mshr_miss_latency::total 10591000 # number of ReadReq MSHR miss cycles -system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 10591000 # number of demand (read+write) MSHR miss cycles -system.cpu2.icache.demand_mshr_miss_latency::total 10591000 # number of demand (read+write) MSHR miss cycles -system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 10591000 # number of overall MSHR miss cycles -system.cpu2.icache.overall_mshr_miss_latency::total 10591000 # number of overall MSHR miss cycles -system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.022229 # mshr miss rate for ReadReq accesses -system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.022229 # mshr miss rate for ReadReq accesses -system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.022229 # mshr miss rate for demand accesses -system.cpu2.icache.demand_mshr_miss_rate::total 0.022229 # mshr miss rate for demand accesses -system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.022229 # mshr miss rate for overall accesses -system.cpu2.icache.overall_mshr_miss_rate::total 0.022229 # mshr miss rate for overall accesses -system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 15086.894587 # average ReadReq mshr miss latency -system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 15086.894587 # average ReadReq mshr miss latency -system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 15086.894587 # average overall mshr miss latency -system.cpu2.icache.demand_avg_mshr_miss_latency::total 15086.894587 # average overall mshr miss latency -system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 15086.894587 # average overall mshr miss latency -system.cpu2.icache.overall_avg_mshr_miss_latency::total 15086.894587 # average overall mshr miss latency -system.cpu3.branchPred.lookups 65607 # Number of BP lookups -system.cpu3.branchPred.condPredicted 57989 # Number of conditional branches predicted -system.cpu3.branchPred.condIncorrect 2329 # Number of conditional branches incorrect -system.cpu3.branchPred.BTBLookups 57945 # Number of BTB lookups +system.cpu2.icache.writebacks::writebacks 551 # number of writebacks +system.cpu2.icache.writebacks::total 551 # number of writebacks +system.cpu2.icache.ReadReq_mshr_hits::cpu2.inst 128 # number of ReadReq MSHR hits +system.cpu2.icache.ReadReq_mshr_hits::total 128 # number of ReadReq MSHR hits +system.cpu2.icache.demand_mshr_hits::cpu2.inst 128 # number of demand (read+write) MSHR hits +system.cpu2.icache.demand_mshr_hits::total 128 # number of demand (read+write) MSHR hits +system.cpu2.icache.overall_mshr_hits::cpu2.inst 128 # number of overall MSHR hits +system.cpu2.icache.overall_mshr_hits::total 128 # number of overall MSHR hits +system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst 687 # number of ReadReq MSHR misses +system.cpu2.icache.ReadReq_mshr_misses::total 687 # number of ReadReq MSHR misses +system.cpu2.icache.demand_mshr_misses::cpu2.inst 687 # number of demand (read+write) MSHR misses +system.cpu2.icache.demand_mshr_misses::total 687 # number of demand (read+write) MSHR misses +system.cpu2.icache.overall_mshr_misses::cpu2.inst 687 # number of overall MSHR misses +system.cpu2.icache.overall_mshr_misses::total 687 # number of overall MSHR misses +system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 10903000 # number of ReadReq MSHR miss cycles +system.cpu2.icache.ReadReq_mshr_miss_latency::total 10903000 # number of ReadReq MSHR miss cycles +system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 10903000 # number of demand (read+write) MSHR miss cycles +system.cpu2.icache.demand_mshr_miss_latency::total 10903000 # number of demand (read+write) MSHR miss cycles +system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 10903000 # number of overall MSHR miss cycles +system.cpu2.icache.overall_mshr_miss_latency::total 10903000 # number of overall MSHR miss cycles +system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.024127 # mshr miss rate for ReadReq accesses +system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.024127 # mshr miss rate for ReadReq accesses +system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.024127 # mshr miss rate for demand accesses +system.cpu2.icache.demand_mshr_miss_rate::total 0.024127 # mshr miss rate for demand accesses +system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.024127 # mshr miss rate for overall accesses +system.cpu2.icache.overall_mshr_miss_rate::total 0.024127 # mshr miss rate for overall accesses +system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 15870.451237 # average ReadReq mshr miss latency +system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 15870.451237 # average ReadReq mshr miss latency +system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 15870.451237 # average overall mshr miss latency +system.cpu2.icache.demand_avg_mshr_miss_latency::total 15870.451237 # average overall mshr miss latency +system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 15870.451237 # average overall mshr miss latency +system.cpu2.icache.overall_avg_mshr_miss_latency::total 15870.451237 # average overall mshr miss latency +system.cpu3.branchPred.lookups 64271 # Number of BP lookups +system.cpu3.branchPred.condPredicted 56758 # Number of conditional branches predicted +system.cpu3.branchPred.condIncorrect 2271 # Number of conditional branches incorrect +system.cpu3.branchPred.BTBLookups 55794 # Number of BTB lookups system.cpu3.branchPred.BTBHits 0 # Number of BTB hits system.cpu3.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu3.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage -system.cpu3.branchPred.usedRAS 1972 # Number of times the RAS was used to get a target. +system.cpu3.branchPred.usedRAS 1884 # Number of times the RAS was used to get a target. system.cpu3.branchPred.RASInCorrect 231 # Number of incorrect RAS predictions. -system.cpu3.branchPred.indirectLookups 57945 # Number of indirect predictor lookups. -system.cpu3.branchPred.indirectHits 47394 # Number of indirect target hits. -system.cpu3.branchPred.indirectMisses 10551 # Number of indirect misses. -system.cpu3.branchPredindirectMispredicted 1239 # Number of mispredicted indirect branches. -system.cpu3.pwrStateResidencyTicks::ON 124830000 # Cumulative time (in ticks) in various power states -system.cpu3.numCycles 191064 # number of cpu cycles simulated +system.cpu3.branchPred.indirectLookups 55794 # Number of indirect predictor lookups. +system.cpu3.branchPred.indirectHits 46245 # Number of indirect target hits. +system.cpu3.branchPred.indirectMisses 9549 # Number of indirect misses. +system.cpu3.branchPredindirectMispredicted 1200 # Number of mispredicted indirect branches. +system.cpu3.pwrStateResidencyTicks::ON 125996000 # Cumulative time (in ticks) in various power states +system.cpu3.numCycles 194168 # number of cpu cycles simulated system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu3.fetch.icacheStallCycles 38959 # Number of cycles fetch is stalled on an Icache miss -system.cpu3.fetch.Insts 355945 # Number of instructions fetch has processed -system.cpu3.fetch.Branches 65607 # Number of branches that fetch encountered -system.cpu3.fetch.predictedBranches 49366 # Number of branches that fetch has predicted taken -system.cpu3.fetch.Cycles 146283 # Number of cycles fetch has run and was not squashing or blocked -system.cpu3.fetch.SquashCycles 4811 # Number of cycles fetch has spent squashing +system.cpu3.fetch.icacheStallCycles 40168 # Number of cycles fetch is stalled on an Icache miss +system.cpu3.fetch.Insts 346607 # Number of instructions fetch has processed +system.cpu3.fetch.Branches 64271 # Number of branches that fetch encountered +system.cpu3.fetch.predictedBranches 48129 # Number of branches that fetch has predicted taken +system.cpu3.fetch.Cycles 146969 # Number of cycles fetch has run and was not squashing or blocked +system.cpu3.fetch.SquashCycles 4697 # Number of cycles fetch has spent squashing system.cpu3.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu3.fetch.NoActiveThreadStallCycles 10 # Number of stall cycles due to no active thread to fetch from -system.cpu3.fetch.PendingTrapStallCycles 1648 # Number of stall cycles due to pending traps -system.cpu3.fetch.CacheLines 27872 # Number of cache lines fetched -system.cpu3.fetch.IcacheSquashes 954 # Number of outstanding Icache misses that were squashed -system.cpu3.fetch.rateDist::samples 189308 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::mean 1.880243 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::stdev 2.334212 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.PendingTrapStallCycles 1673 # Number of stall cycles due to pending traps +system.cpu3.fetch.CacheLines 29039 # Number of cache lines fetched +system.cpu3.fetch.IcacheSquashes 911 # Number of outstanding Icache misses that were squashed +system.cpu3.fetch.rateDist::samples 191171 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::mean 1.813073 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::stdev 2.312592 # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::0 70601 37.29% 37.29% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::1 58551 30.93% 68.22% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::2 8289 4.38% 72.60% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::3 3543 1.87% 74.47% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::4 620 0.33% 74.80% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::5 36795 19.44% 94.24% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::6 1123 0.59% 94.83% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::7 1294 0.68% 95.51% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::8 8492 4.49% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::0 74400 38.92% 38.92% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::1 57993 30.34% 69.25% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::2 8887 4.65% 73.90% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::3 3426 1.79% 75.69% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::4 613 0.32% 76.02% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::5 35081 18.35% 94.37% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::6 1105 0.58% 94.94% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::7 1253 0.66% 95.60% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::8 8413 4.40% 100.00% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::total 189308 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.branchRate 0.343377 # Number of branch fetches per cycle -system.cpu3.fetch.rate 1.862962 # Number of inst fetches per cycle -system.cpu3.decode.IdleCycles 22011 # Number of cycles decode is idle -system.cpu3.decode.BlockedCycles 70196 # Number of cycles decode is blocked -system.cpu3.decode.RunCycles 90137 # Number of cycles decode is running -system.cpu3.decode.UnblockCycles 4549 # Number of cycles decode is unblocking -system.cpu3.decode.SquashCycles 2405 # Number of cycles decode is squashing -system.cpu3.decode.DecodedInsts 325577 # Number of instructions handled by decode -system.cpu3.rename.SquashCycles 2405 # Number of cycles rename is squashing -system.cpu3.rename.IdleCycles 23040 # Number of cycles rename is idle -system.cpu3.rename.BlockCycles 34162 # Number of cycles rename is blocking -system.cpu3.rename.serializeStallCycles 13425 # count of cycles rename stalled for serializing inst -system.cpu3.rename.RunCycles 90919 # Number of cycles rename is running -system.cpu3.rename.UnblockCycles 25347 # Number of cycles rename is unblocking -system.cpu3.rename.RenamedInsts 318974 # Number of instructions processed by rename -system.cpu3.rename.IQFullEvents 21885 # Number of times rename has blocked due to IQ full -system.cpu3.rename.LQFullEvents 17 # Number of times rename has blocked due to LQ full -system.cpu3.rename.RenamedOperands 222576 # Number of destination operands rename has renamed -system.cpu3.rename.RenameLookups 605183 # Number of register rename lookups that rename has made -system.cpu3.rename.int_rename_lookups 471258 # Number of integer rename lookups -system.cpu3.rename.fp_rename_lookups 38 # Number of floating rename lookups -system.cpu3.rename.CommittedMaps 194403 # Number of HB maps that are committed -system.cpu3.rename.UndoneMaps 28173 # Number of HB maps that are undone due to squashing -system.cpu3.rename.serializingInsts 1623 # count of serializing insts renamed -system.cpu3.rename.tempSerializingInsts 1757 # count of temporary serializing insts renamed -system.cpu3.rename.skidInsts 30798 # count of insts added to the skid buffer -system.cpu3.memDep0.insertedLoads 87479 # Number of loads inserted to the mem dependence unit. -system.cpu3.memDep0.insertedStores 41118 # Number of stores inserted to the mem dependence unit. -system.cpu3.memDep0.conflictingLoads 41854 # Number of conflicting loads. -system.cpu3.memDep0.conflictingStores 34728 # Number of conflicting stores. -system.cpu3.iq.iqInstsAdded 259350 # Number of instructions added to the IQ (excludes non-spec) -system.cpu3.iq.iqNonSpecInstsAdded 8662 # Number of non-speculative instructions added to the IQ -system.cpu3.iq.iqInstsIssued 260097 # Number of instructions issued -system.cpu3.iq.iqSquashedInstsIssued 100 # Number of squashed instructions issued -system.cpu3.iq.iqSquashedInstsExamined 24362 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu3.iq.iqSquashedOperandsExamined 19655 # Number of squashed operands that are examined and possibly removed from graph -system.cpu3.iq.iqSquashedNonSpecRemoved 1213 # Number of squashed non-spec instructions that were removed -system.cpu3.iq.issued_per_cycle::samples 189308 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::mean 1.373936 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::stdev 1.388628 # Number of insts issued each cycle +system.cpu3.fetch.rateDist::total 191171 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.branchRate 0.331007 # Number of branch fetches per cycle +system.cpu3.fetch.rate 1.785088 # Number of inst fetches per cycle +system.cpu3.decode.IdleCycles 21895 # Number of cycles decode is idle +system.cpu3.decode.BlockedCycles 75534 # Number of cycles decode is blocked +system.cpu3.decode.RunCycles 86562 # Number of cycles decode is running +system.cpu3.decode.UnblockCycles 4822 # Number of cycles decode is unblocking +system.cpu3.decode.SquashCycles 2348 # Number of cycles decode is squashing +system.cpu3.decode.DecodedInsts 316867 # Number of instructions handled by decode +system.cpu3.rename.SquashCycles 2348 # Number of cycles rename is squashing +system.cpu3.rename.IdleCycles 22878 # Number of cycles rename is idle +system.cpu3.rename.BlockCycles 37474 # Number of cycles rename is blocking +system.cpu3.rename.serializeStallCycles 13003 # count of cycles rename stalled for serializing inst +system.cpu3.rename.RunCycles 86814 # Number of cycles rename is running +system.cpu3.rename.UnblockCycles 28644 # Number of cycles rename is unblocking +system.cpu3.rename.RenamedInsts 310654 # Number of instructions processed by rename +system.cpu3.rename.IQFullEvents 24310 # Number of times rename has blocked due to IQ full +system.cpu3.rename.LQFullEvents 15 # Number of times rename has blocked due to LQ full +system.cpu3.rename.RenamedOperands 215725 # Number of destination operands rename has renamed +system.cpu3.rename.RenameLookups 585696 # Number of register rename lookups that rename has made +system.cpu3.rename.int_rename_lookups 456528 # Number of integer rename lookups +system.cpu3.rename.fp_rename_lookups 32 # Number of floating rename lookups +system.cpu3.rename.CommittedMaps 188410 # Number of HB maps that are committed +system.cpu3.rename.UndoneMaps 27315 # Number of HB maps that are undone due to squashing +system.cpu3.rename.serializingInsts 1561 # count of serializing insts renamed +system.cpu3.rename.tempSerializingInsts 1705 # count of temporary serializing insts renamed +system.cpu3.rename.skidInsts 33909 # count of insts added to the skid buffer +system.cpu3.memDep0.insertedLoads 84645 # Number of loads inserted to the mem dependence unit. +system.cpu3.memDep0.insertedStores 39227 # Number of stores inserted to the mem dependence unit. +system.cpu3.memDep0.conflictingLoads 40799 # Number of conflicting loads. +system.cpu3.memDep0.conflictingStores 33015 # Number of conflicting stores. +system.cpu3.iq.iqInstsAdded 251387 # Number of instructions added to the IQ (excludes non-spec) +system.cpu3.iq.iqNonSpecInstsAdded 9227 # Number of non-speculative instructions added to the IQ +system.cpu3.iq.iqInstsIssued 253114 # Number of instructions issued +system.cpu3.iq.iqSquashedInstsIssued 79 # Number of squashed instructions issued +system.cpu3.iq.iqSquashedInstsExamined 23294 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu3.iq.iqSquashedOperandsExamined 18618 # Number of squashed operands that are examined and possibly removed from graph +system.cpu3.iq.iqSquashedNonSpecRemoved 1117 # Number of squashed non-spec instructions that were removed +system.cpu3.iq.issued_per_cycle::samples 191171 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::mean 1.324019 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::stdev 1.377234 # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::0 75622 39.95% 39.95% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::1 27531 14.54% 54.49% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::2 39579 20.91% 75.40% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::3 39359 20.79% 96.19% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::4 3671 1.94% 98.13% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::5 1727 0.91% 99.04% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::6 1045 0.55% 99.59% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::7 450 0.24% 99.83% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::8 324 0.17% 100.00% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::0 78925 41.29% 41.29% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::1 29485 15.42% 56.71% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::2 37890 19.82% 76.53% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::3 37772 19.76% 96.29% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::4 3652 1.91% 98.20% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::5 1740 0.91% 99.11% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::6 1013 0.53% 99.64% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::7 405 0.21% 99.85% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::8 289 0.15% 100.00% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::total 189308 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::total 191171 # Number of insts issued each cycle system.cpu3.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntAlu 198 41.42% 41.42% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntMult 0 0.00% 41.42% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntDiv 0 0.00% 41.42% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatAdd 0 0.00% 41.42% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatCmp 0 0.00% 41.42% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatCvt 0 0.00% 41.42% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatMult 0 0.00% 41.42% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatMultAcc 0 0.00% 41.42% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatDiv 0 0.00% 41.42% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatMisc 0 0.00% 41.42% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 41.42% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAdd 0 0.00% 41.42% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 41.42% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAlu 0 0.00% 41.42% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdCmp 0 0.00% 41.42% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdCvt 0 0.00% 41.42% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMisc 0 0.00% 41.42% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMult 0 0.00% 41.42% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 41.42% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdShift 0 0.00% 41.42% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 41.42% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 41.42% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 41.42% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 41.42% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 41.42% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 41.42% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 41.42% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 41.42% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 41.42% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 41.42% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 41.42% # attempts to use FU when none available -system.cpu3.iq.fu_full::MemRead 48 10.04% 51.46% # attempts to use FU when none available -system.cpu3.iq.fu_full::MemWrite 232 48.54% 100.00% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntAlu 186 40.88% 40.88% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntMult 0 0.00% 40.88% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntDiv 0 0.00% 40.88% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatAdd 0 0.00% 40.88% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatCmp 0 0.00% 40.88% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatCvt 0 0.00% 40.88% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatMult 0 0.00% 40.88% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatMultAcc 0 0.00% 40.88% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatDiv 0 0.00% 40.88% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatMisc 0 0.00% 40.88% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 40.88% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAdd 0 0.00% 40.88% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 40.88% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAlu 0 0.00% 40.88% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdCmp 0 0.00% 40.88% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdCvt 0 0.00% 40.88% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMisc 0 0.00% 40.88% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMult 0 0.00% 40.88% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 40.88% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdShift 0 0.00% 40.88% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 40.88% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 40.88% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 40.88% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 40.88% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 40.88% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 40.88% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 40.88% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 40.88% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 40.88% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 40.88% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 40.88% # attempts to use FU when none available +system.cpu3.iq.fu_full::MemRead 39 8.57% 49.45% # attempts to use FU when none available +system.cpu3.iq.fu_full::MemWrite 230 50.55% 100.00% # attempts to use FU when none available system.cpu3.iq.fu_full::FloatMemRead 0 0.00% 100.00% # attempts to use FU when none available system.cpu3.iq.fu_full::FloatMemWrite 0 0.00% 100.00% # attempts to use FU when none available system.cpu3.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu3.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu3.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu3.iq.FU_type_0::IntAlu 126919 48.80% 48.80% # Type of FU issued -system.cpu3.iq.FU_type_0::IntMult 0 0.00% 48.80% # Type of FU issued -system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 48.80% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 48.80% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 48.80% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 48.80% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 48.80% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatMultAcc 0 0.00% 48.80% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 48.80% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatMisc 0 0.00% 48.80% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 48.80% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 48.80% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 48.80% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 48.80% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 48.80% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 48.80% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 48.80% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 48.80% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 48.80% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 48.80% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.80% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 48.80% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 48.80% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.80% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 48.80% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 48.80% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 48.80% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.80% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 48.80% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.80% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.80% # Type of FU issued -system.cpu3.iq.FU_type_0::MemRead 93130 35.81% 84.60% # Type of FU issued -system.cpu3.iq.FU_type_0::MemWrite 40048 15.40% 100.00% # Type of FU issued +system.cpu3.iq.FU_type_0::IntAlu 123835 48.92% 48.92% # Type of FU issued +system.cpu3.iq.FU_type_0::IntMult 0 0.00% 48.92% # Type of FU issued +system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 48.92% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 48.92% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 48.92% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 48.92% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 48.92% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatMultAcc 0 0.00% 48.92% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 48.92% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatMisc 0 0.00% 48.92% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 48.92% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 48.92% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 48.92% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 48.92% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 48.92% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 48.92% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 48.92% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 48.92% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 48.92% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 48.92% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.92% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 48.92% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 48.92% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.92% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 48.92% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 48.92% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 48.92% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.92% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 48.92% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.92% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.92% # Type of FU issued +system.cpu3.iq.FU_type_0::MemRead 91015 35.96% 84.88% # Type of FU issued +system.cpu3.iq.FU_type_0::MemWrite 38264 15.12% 100.00% # Type of FU issued system.cpu3.iq.FU_type_0::FloatMemRead 0 0.00% 100.00% # Type of FU issued system.cpu3.iq.FU_type_0::FloatMemWrite 0 0.00% 100.00% # Type of FU issued system.cpu3.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu3.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu3.iq.FU_type_0::total 260097 # Type of FU issued -system.cpu3.iq.rate 1.361308 # Inst issue rate -system.cpu3.iq.fu_busy_cnt 478 # FU busy when requested -system.cpu3.iq.fu_busy_rate 0.001838 # FU busy rate (busy events/executed inst) -system.cpu3.iq.int_inst_queue_reads 710080 # Number of integer instruction queue reads -system.cpu3.iq.int_inst_queue_writes 292336 # Number of integer instruction queue writes -system.cpu3.iq.int_inst_queue_wakeup_accesses 256163 # Number of integer instruction queue wakeup accesses +system.cpu3.iq.FU_type_0::total 253114 # Type of FU issued +system.cpu3.iq.rate 1.303582 # Inst issue rate +system.cpu3.iq.fu_busy_cnt 455 # FU busy when requested +system.cpu3.iq.fu_busy_rate 0.001798 # FU busy rate (busy events/executed inst) +system.cpu3.iq.int_inst_queue_reads 697933 # Number of integer instruction queue reads +system.cpu3.iq.int_inst_queue_writes 283879 # Number of integer instruction queue writes +system.cpu3.iq.int_inst_queue_wakeup_accesses 249400 # Number of integer instruction queue wakeup accesses system.cpu3.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads -system.cpu3.iq.fp_inst_queue_writes 76 # Number of floating instruction queue writes +system.cpu3.iq.fp_inst_queue_writes 64 # Number of floating instruction queue writes system.cpu3.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu3.iq.int_alu_accesses 260575 # Number of integer alu accesses +system.cpu3.iq.int_alu_accesses 253569 # Number of integer alu accesses system.cpu3.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu3.iew.lsq.thread0.forwLoads 34620 # Number of loads that had data forwarded from stores +system.cpu3.iew.lsq.thread0.forwLoads 32960 # Number of loads that had data forwarded from stores system.cpu3.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu3.iew.lsq.thread0.squashedLoads 4474 # Number of loads squashed +system.cpu3.iew.lsq.thread0.squashedLoads 4297 # Number of loads squashed system.cpu3.iew.lsq.thread0.ignoredResponses 40 # Number of memory responses ignored because the instruction is squashed -system.cpu3.iew.lsq.thread0.memOrderViolation 38 # Number of memory ordering violations -system.cpu3.iew.lsq.thread0.squashedStores 2718 # Number of stores squashed +system.cpu3.iew.lsq.thread0.memOrderViolation 35 # Number of memory ordering violations +system.cpu3.iew.lsq.thread0.squashedStores 2496 # Number of stores squashed system.cpu3.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu3.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu3.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu3.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu3.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu3.iew.iewSquashCycles 2405 # Number of cycles IEW is squashing -system.cpu3.iew.iewBlockCycles 9114 # Number of cycles IEW is blocking -system.cpu3.iew.iewUnblockCycles 55 # Number of cycles IEW is unblocking -system.cpu3.iew.iewDispatchedInsts 311067 # Number of instructions dispatched to IQ -system.cpu3.iew.iewDispSquashedInsts 408 # Number of squashed instructions skipped by dispatch -system.cpu3.iew.iewDispLoadInsts 87479 # Number of dispatched load instructions -system.cpu3.iew.iewDispStoreInsts 41118 # Number of dispatched store instructions -system.cpu3.iew.iewDispNonSpecInsts 1508 # Number of dispatched non-speculative instructions -system.cpu3.iew.iewIQFullEvents 34 # Number of times the IQ has become full, causing a stall +system.cpu3.iew.iewSquashCycles 2348 # Number of cycles IEW is squashing +system.cpu3.iew.iewBlockCycles 9647 # Number of cycles IEW is blocking +system.cpu3.iew.iewUnblockCycles 50 # Number of cycles IEW is unblocking +system.cpu3.iew.iewDispatchedInsts 302650 # Number of instructions dispatched to IQ +system.cpu3.iew.iewDispSquashedInsts 426 # Number of squashed instructions skipped by dispatch +system.cpu3.iew.iewDispLoadInsts 84645 # Number of dispatched load instructions +system.cpu3.iew.iewDispStoreInsts 39227 # Number of dispatched store instructions +system.cpu3.iew.iewDispNonSpecInsts 1449 # Number of dispatched non-speculative instructions +system.cpu3.iew.iewIQFullEvents 30 # Number of times the IQ has become full, causing a stall system.cpu3.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu3.iew.memOrderViolationEvents 38 # Number of memory order violations -system.cpu3.iew.predictedTakenIncorrect 450 # Number of branches that were predicted taken incorrectly -system.cpu3.iew.predictedNotTakenIncorrect 2479 # Number of branches that were predicted not taken incorrectly -system.cpu3.iew.branchMispredicts 2929 # Number of branch mispredicts detected at execute -system.cpu3.iew.iewExecutedInsts 257518 # Number of executed instructions -system.cpu3.iew.iewExecLoadInsts 85797 # Number of load instructions executed -system.cpu3.iew.iewExecSquashedInsts 2579 # Number of squashed instructions skipped in execute +system.cpu3.iew.memOrderViolationEvents 35 # Number of memory order violations +system.cpu3.iew.predictedTakenIncorrect 408 # Number of branches that were predicted taken incorrectly +system.cpu3.iew.predictedNotTakenIncorrect 2445 # Number of branches that were predicted not taken incorrectly +system.cpu3.iew.branchMispredicts 2853 # Number of branch mispredicts detected at execute +system.cpu3.iew.iewExecutedInsts 250680 # Number of executed instructions +system.cpu3.iew.iewExecLoadInsts 83030 # Number of load instructions executed +system.cpu3.iew.iewExecSquashedInsts 2434 # Number of squashed instructions skipped in execute system.cpu3.iew.exec_swp 0 # number of swp insts executed -system.cpu3.iew.exec_nop 43055 # number of nop insts executed -system.cpu3.iew.exec_refs 125534 # number of memory reference insts executed -system.cpu3.iew.exec_branches 53219 # Number of branches executed -system.cpu3.iew.exec_stores 39737 # Number of stores executed -system.cpu3.iew.exec_rate 1.347810 # Inst execution rate -system.cpu3.iew.wb_sent 256666 # cumulative count of insts sent to commit -system.cpu3.iew.wb_count 256163 # cumulative count of insts written-back -system.cpu3.iew.wb_producers 143359 # num instructions producing a value -system.cpu3.iew.wb_consumers 150866 # num instructions consuming a value -system.cpu3.iew.wb_rate 1.340718 # insts written-back per cycle -system.cpu3.iew.wb_fanout 0.950241 # average fanout of values written-back -system.cpu3.commit.commitSquashedInsts 25509 # The number of squashed insts skipped by commit -system.cpu3.commit.commitNonSpecStalls 7449 # The number of times commit has been forced to stall to communicate backwards -system.cpu3.commit.branchMispredicts 2329 # The number of times a branch was mispredicted -system.cpu3.commit.committed_per_cycle::samples 184454 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::mean 1.547985 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::stdev 2.017686 # Number of insts commited each cycle +system.cpu3.iew.exec_nop 42036 # number of nop insts executed +system.cpu3.iew.exec_refs 121032 # number of memory reference insts executed +system.cpu3.iew.exec_branches 52206 # Number of branches executed +system.cpu3.iew.exec_stores 38002 # Number of stores executed +system.cpu3.iew.exec_rate 1.291047 # Inst execution rate +system.cpu3.iew.wb_sent 249859 # cumulative count of insts sent to commit +system.cpu3.iew.wb_count 249400 # cumulative count of insts written-back +system.cpu3.iew.wb_producers 138774 # num instructions producing a value +system.cpu3.iew.wb_consumers 146167 # num instructions consuming a value +system.cpu3.iew.wb_rate 1.284455 # insts written-back per cycle +system.cpu3.iew.wb_fanout 0.949421 # average fanout of values written-back +system.cpu3.commit.commitSquashedInsts 24422 # The number of squashed insts skipped by commit +system.cpu3.commit.commitNonSpecStalls 8110 # The number of times commit has been forced to stall to communicate backwards +system.cpu3.commit.branchMispredicts 2271 # The number of times a branch was mispredicted +system.cpu3.commit.committed_per_cycle::samples 186514 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::mean 1.491588 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::stdev 1.991895 # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::0 82386 44.66% 44.66% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::1 49463 26.82% 71.48% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::2 5369 2.91% 74.39% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::3 8071 4.38% 78.77% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::4 1252 0.68% 79.45% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::5 34869 18.90% 98.35% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::6 786 0.43% 98.78% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::7 1015 0.55% 99.33% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::8 1243 0.67% 100.00% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::0 86424 46.34% 46.34% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::1 48393 25.95% 72.28% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::2 5395 2.89% 75.18% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::3 8809 4.72% 79.90% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::4 1333 0.71% 80.61% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::5 33156 17.78% 98.39% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::6 761 0.41% 98.80% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::7 1030 0.55% 99.35% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::8 1213 0.65% 100.00% # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::total 184454 # Number of insts commited each cycle -system.cpu3.commit.committedInsts 285532 # Number of instructions committed -system.cpu3.commit.committedOps 285532 # Number of ops (including micro ops) committed +system.cpu3.commit.committed_per_cycle::total 186514 # Number of insts commited each cycle +system.cpu3.commit.committedInsts 278202 # Number of instructions committed +system.cpu3.commit.committedOps 278202 # Number of ops (including micro ops) committed system.cpu3.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu3.commit.refs 121405 # Number of memory references committed -system.cpu3.commit.loads 83005 # Number of loads committed -system.cpu3.commit.membars 6731 # Number of memory barriers committed -system.cpu3.commit.branches 51096 # Number of branches committed +system.cpu3.commit.refs 117079 # Number of memory references committed +system.cpu3.commit.loads 80348 # Number of loads committed +system.cpu3.commit.membars 7398 # Number of memory barriers committed +system.cpu3.commit.branches 50090 # Number of branches committed system.cpu3.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu3.commit.int_insts 194617 # Number of committed integer instructions. +system.cpu3.commit.int_insts 189293 # Number of committed integer instructions. system.cpu3.commit.function_calls 322 # Number of function calls committed. -system.cpu3.commit.op_class_0::No_OpClass 41882 14.67% 14.67% # Class of committed instruction -system.cpu3.commit.op_class_0::IntAlu 115514 40.46% 55.12% # Class of committed instruction -system.cpu3.commit.op_class_0::IntMult 0 0.00% 55.12% # Class of committed instruction -system.cpu3.commit.op_class_0::IntDiv 0 0.00% 55.12% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatAdd 0 0.00% 55.12% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatCmp 0 0.00% 55.12% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatCvt 0 0.00% 55.12% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatMult 0 0.00% 55.12% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatMultAcc 0 0.00% 55.12% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatDiv 0 0.00% 55.12% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatMisc 0 0.00% 55.12% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatSqrt 0 0.00% 55.12% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdAdd 0 0.00% 55.12% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdAddAcc 0 0.00% 55.12% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdAlu 0 0.00% 55.12% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdCmp 0 0.00% 55.12% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdCvt 0 0.00% 55.12% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdMisc 0 0.00% 55.12% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdMult 0 0.00% 55.12% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdMultAcc 0 0.00% 55.12% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdShift 0 0.00% 55.12% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdShiftAcc 0 0.00% 55.12% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdSqrt 0 0.00% 55.12% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatAdd 0 0.00% 55.12% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatAlu 0 0.00% 55.12% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatCmp 0 0.00% 55.12% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatCvt 0 0.00% 55.12% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatDiv 0 0.00% 55.12% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatMisc 0 0.00% 55.12% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatMult 0 0.00% 55.12% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatMultAcc 0 0.00% 55.12% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatSqrt 0 0.00% 55.12% # Class of committed instruction -system.cpu3.commit.op_class_0::MemRead 89736 31.43% 86.55% # Class of committed instruction -system.cpu3.commit.op_class_0::MemWrite 38400 13.45% 100.00% # Class of committed instruction +system.cpu3.commit.op_class_0::No_OpClass 40882 14.70% 14.70% # Class of committed instruction +system.cpu3.commit.op_class_0::IntAlu 112843 40.56% 55.26% # Class of committed instruction +system.cpu3.commit.op_class_0::IntMult 0 0.00% 55.26% # Class of committed instruction +system.cpu3.commit.op_class_0::IntDiv 0 0.00% 55.26% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatAdd 0 0.00% 55.26% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatCmp 0 0.00% 55.26% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatCvt 0 0.00% 55.26% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatMult 0 0.00% 55.26% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatMultAcc 0 0.00% 55.26% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatDiv 0 0.00% 55.26% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatMisc 0 0.00% 55.26% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatSqrt 0 0.00% 55.26% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdAdd 0 0.00% 55.26% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdAddAcc 0 0.00% 55.26% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdAlu 0 0.00% 55.26% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdCmp 0 0.00% 55.26% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdCvt 0 0.00% 55.26% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdMisc 0 0.00% 55.26% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdMult 0 0.00% 55.26% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdMultAcc 0 0.00% 55.26% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdShift 0 0.00% 55.26% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdShiftAcc 0 0.00% 55.26% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdSqrt 0 0.00% 55.26% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatAdd 0 0.00% 55.26% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatAlu 0 0.00% 55.26% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatCmp 0 0.00% 55.26% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatCvt 0 0.00% 55.26% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatDiv 0 0.00% 55.26% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatMisc 0 0.00% 55.26% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatMult 0 0.00% 55.26% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatMultAcc 0 0.00% 55.26% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatSqrt 0 0.00% 55.26% # Class of committed instruction +system.cpu3.commit.op_class_0::MemRead 87746 31.54% 86.80% # Class of committed instruction +system.cpu3.commit.op_class_0::MemWrite 36731 13.20% 100.00% # Class of committed instruction system.cpu3.commit.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction system.cpu3.commit.op_class_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction system.cpu3.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu3.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu3.commit.op_class_0::total 285532 # Class of committed instruction -system.cpu3.commit.bw_lim_events 1243 # number cycles where commit BW limit reached -system.cpu3.rob.rob_reads 493666 # The number of ROB reads -system.cpu3.rob.rob_writes 626988 # The number of ROB writes -system.cpu3.timesIdled 229 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu3.idleCycles 1756 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu3.quiesceCycles 50157 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu3.committedInsts 236919 # Number of Instructions Simulated -system.cpu3.committedOps 236919 # Number of Ops (including micro ops) Simulated -system.cpu3.cpi 0.806453 # CPI: Cycles Per Instruction -system.cpu3.cpi_total 0.806453 # CPI: Total CPI of All Threads -system.cpu3.ipc 1.239998 # IPC: Instructions Per Cycle -system.cpu3.ipc_total 1.239998 # IPC: Total IPC of All Threads -system.cpu3.int_regfile_reads 440410 # number of integer regfile reads -system.cpu3.int_regfile_writes 205469 # number of integer regfile writes +system.cpu3.commit.op_class_0::total 278202 # Class of committed instruction +system.cpu3.commit.bw_lim_events 1213 # number cycles where commit BW limit reached +system.cpu3.rob.rob_reads 487339 # The number of ROB reads +system.cpu3.rob.rob_writes 609957 # The number of ROB writes +system.cpu3.timesIdled 210 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu3.idleCycles 2997 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu3.quiesceCycles 50169 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu3.committedInsts 229922 # Number of Instructions Simulated +system.cpu3.committedOps 229922 # Number of Ops (including micro ops) Simulated +system.cpu3.cpi 0.844495 # CPI: Cycles Per Instruction +system.cpu3.cpi_total 0.844495 # CPI: Total CPI of All Threads +system.cpu3.ipc 1.184140 # IPC: Instructions Per Cycle +system.cpu3.ipc_total 1.184140 # IPC: Total IPC of All Threads +system.cpu3.int_regfile_reads 426644 # number of integer regfile reads +system.cpu3.int_regfile_writes 199085 # number of integer regfile writes system.cpu3.fp_regfile_writes 64 # number of floating regfile writes -system.cpu3.misc_regfile_reads 127408 # number of misc regfile reads +system.cpu3.misc_regfile_reads 122920 # number of misc regfile reads system.cpu3.misc_regfile_writes 648 # number of misc regfile writes -system.cpu3.dcache.tags.pwrStateResidencyTicks::UNDEFINED 124830000 # Cumulative time (in ticks) in various power states +system.cpu3.dcache.tags.pwrStateResidencyTicks::UNDEFINED 125996000 # Cumulative time (in ticks) in various power states system.cpu3.dcache.tags.replacements 0 # number of replacements -system.cpu3.dcache.tags.tagsinuse 25.184575 # Cycle average of tags in use -system.cpu3.dcache.tags.total_refs 45468 # Total number of references to valid blocks. -system.cpu3.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks. -system.cpu3.dcache.tags.avg_refs 1567.862069 # Average number of references to valid blocks. +system.cpu3.dcache.tags.tagsinuse 24.889715 # Cycle average of tags in use +system.cpu3.dcache.tags.total_refs 43728 # Total number of references to valid blocks. +system.cpu3.dcache.tags.sampled_refs 30 # Sample count of references to valid blocks. +system.cpu3.dcache.tags.avg_refs 1457.600000 # Average number of references to valid blocks. system.cpu3.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.dcache.tags.occ_blocks::cpu3.data 25.184575 # Average occupied blocks per requestor -system.cpu3.dcache.tags.occ_percent::cpu3.data 0.049189 # Average percentage of cache occupancy -system.cpu3.dcache.tags.occ_percent::total 0.049189 # Average percentage of cache occupancy -system.cpu3.dcache.tags.occ_task_id_blocks::1024 29 # Occupied blocks per task id -system.cpu3.dcache.tags.age_task_id_blocks_1024::1 29 # Occupied blocks per task id -system.cpu3.dcache.tags.occ_task_id_percent::1024 0.056641 # Percentage of cache occupancy per task id -system.cpu3.dcache.tags.tag_accesses 358446 # Number of tag accesses -system.cpu3.dcache.tags.data_accesses 358446 # Number of data accesses -system.cpu3.dcache.pwrStateResidencyTicks::UNDEFINED 124830000 # Cumulative time (in ticks) in various power states -system.cpu3.dcache.ReadReq_hits::cpu3.data 50650 # number of ReadReq hits -system.cpu3.dcache.ReadReq_hits::total 50650 # number of ReadReq hits -system.cpu3.dcache.WriteReq_hits::cpu3.data 38188 # number of WriteReq hits -system.cpu3.dcache.WriteReq_hits::total 38188 # number of WriteReq hits -system.cpu3.dcache.SwapReq_hits::cpu3.data 12 # number of SwapReq hits -system.cpu3.dcache.SwapReq_hits::total 12 # number of SwapReq hits -system.cpu3.dcache.demand_hits::cpu3.data 88838 # number of demand (read+write) hits -system.cpu3.dcache.demand_hits::total 88838 # number of demand (read+write) hits -system.cpu3.dcache.overall_hits::cpu3.data 88838 # number of overall hits -system.cpu3.dcache.overall_hits::total 88838 # number of overall hits -system.cpu3.dcache.ReadReq_misses::cpu3.data 496 # number of ReadReq misses -system.cpu3.dcache.ReadReq_misses::total 496 # number of ReadReq misses -system.cpu3.dcache.WriteReq_misses::cpu3.data 140 # number of WriteReq misses -system.cpu3.dcache.WriteReq_misses::total 140 # number of WriteReq misses -system.cpu3.dcache.SwapReq_misses::cpu3.data 60 # number of SwapReq misses -system.cpu3.dcache.SwapReq_misses::total 60 # number of SwapReq misses -system.cpu3.dcache.demand_misses::cpu3.data 636 # number of demand (read+write) misses -system.cpu3.dcache.demand_misses::total 636 # number of demand (read+write) misses -system.cpu3.dcache.overall_misses::cpu3.data 636 # number of overall misses -system.cpu3.dcache.overall_misses::total 636 # number of overall misses -system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 3601500 # number of ReadReq miss cycles -system.cpu3.dcache.ReadReq_miss_latency::total 3601500 # number of ReadReq miss cycles -system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 2913500 # number of WriteReq miss cycles -system.cpu3.dcache.WriteReq_miss_latency::total 2913500 # number of WriteReq miss cycles -system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 356500 # number of SwapReq miss cycles -system.cpu3.dcache.SwapReq_miss_latency::total 356500 # number of SwapReq miss cycles -system.cpu3.dcache.demand_miss_latency::cpu3.data 6515000 # number of demand (read+write) miss cycles -system.cpu3.dcache.demand_miss_latency::total 6515000 # number of demand (read+write) miss cycles -system.cpu3.dcache.overall_miss_latency::cpu3.data 6515000 # number of overall miss cycles -system.cpu3.dcache.overall_miss_latency::total 6515000 # number of overall miss cycles -system.cpu3.dcache.ReadReq_accesses::cpu3.data 51146 # number of ReadReq accesses(hits+misses) -system.cpu3.dcache.ReadReq_accesses::total 51146 # number of ReadReq accesses(hits+misses) -system.cpu3.dcache.WriteReq_accesses::cpu3.data 38328 # number of WriteReq accesses(hits+misses) -system.cpu3.dcache.WriteReq_accesses::total 38328 # number of WriteReq accesses(hits+misses) -system.cpu3.dcache.SwapReq_accesses::cpu3.data 72 # number of SwapReq accesses(hits+misses) -system.cpu3.dcache.SwapReq_accesses::total 72 # number of SwapReq accesses(hits+misses) -system.cpu3.dcache.demand_accesses::cpu3.data 89474 # number of demand (read+write) accesses -system.cpu3.dcache.demand_accesses::total 89474 # number of demand (read+write) accesses -system.cpu3.dcache.overall_accesses::cpu3.data 89474 # number of overall (read+write) accesses -system.cpu3.dcache.overall_accesses::total 89474 # number of overall (read+write) accesses -system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.009698 # miss rate for ReadReq accesses -system.cpu3.dcache.ReadReq_miss_rate::total 0.009698 # miss rate for ReadReq accesses -system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.003653 # miss rate for WriteReq accesses -system.cpu3.dcache.WriteReq_miss_rate::total 0.003653 # miss rate for WriteReq accesses -system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.833333 # miss rate for SwapReq accesses -system.cpu3.dcache.SwapReq_miss_rate::total 0.833333 # miss rate for SwapReq accesses -system.cpu3.dcache.demand_miss_rate::cpu3.data 0.007108 # miss rate for demand accesses -system.cpu3.dcache.demand_miss_rate::total 0.007108 # miss rate for demand accesses -system.cpu3.dcache.overall_miss_rate::cpu3.data 0.007108 # miss rate for overall accesses -system.cpu3.dcache.overall_miss_rate::total 0.007108 # miss rate for overall accesses -system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 7261.088710 # average ReadReq miss latency -system.cpu3.dcache.ReadReq_avg_miss_latency::total 7261.088710 # average ReadReq miss latency -system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 20810.714286 # average WriteReq miss latency -system.cpu3.dcache.WriteReq_avg_miss_latency::total 20810.714286 # average WriteReq miss latency -system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 5941.666667 # average SwapReq miss latency -system.cpu3.dcache.SwapReq_avg_miss_latency::total 5941.666667 # average SwapReq miss latency -system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 10243.710692 # average overall miss latency -system.cpu3.dcache.demand_avg_miss_latency::total 10243.710692 # average overall miss latency -system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 10243.710692 # average overall miss latency -system.cpu3.dcache.overall_avg_miss_latency::total 10243.710692 # average overall miss latency +system.cpu3.dcache.tags.occ_blocks::cpu3.data 24.889715 # Average occupied blocks per requestor +system.cpu3.dcache.tags.occ_percent::cpu3.data 0.048613 # Average percentage of cache occupancy +system.cpu3.dcache.tags.occ_percent::total 0.048613 # Average percentage of cache occupancy +system.cpu3.dcache.tags.occ_task_id_blocks::1024 30 # Occupied blocks per task id +system.cpu3.dcache.tags.age_task_id_blocks_1024::1 26 # Occupied blocks per task id +system.cpu3.dcache.tags.age_task_id_blocks_1024::2 4 # Occupied blocks per task id +system.cpu3.dcache.tags.occ_task_id_percent::1024 0.058594 # Percentage of cache occupancy per task id +system.cpu3.dcache.tags.tag_accesses 347346 # Number of tag accesses +system.cpu3.dcache.tags.data_accesses 347346 # Number of data accesses +system.cpu3.dcache.pwrStateResidencyTicks::UNDEFINED 125996000 # Cumulative time (in ticks) in various power states +system.cpu3.dcache.ReadReq_hits::cpu3.data 49561 # number of ReadReq hits +system.cpu3.dcache.ReadReq_hits::total 49561 # number of ReadReq hits +system.cpu3.dcache.WriteReq_hits::cpu3.data 36521 # number of WriteReq hits +system.cpu3.dcache.WriteReq_hits::total 36521 # number of WriteReq hits +system.cpu3.dcache.SwapReq_hits::cpu3.data 14 # number of SwapReq hits +system.cpu3.dcache.SwapReq_hits::total 14 # number of SwapReq hits +system.cpu3.dcache.demand_hits::cpu3.data 86082 # number of demand (read+write) hits +system.cpu3.dcache.demand_hits::total 86082 # number of demand (read+write) hits +system.cpu3.dcache.overall_hits::cpu3.data 86082 # number of overall hits +system.cpu3.dcache.overall_hits::total 86082 # number of overall hits +system.cpu3.dcache.ReadReq_misses::cpu3.data 482 # number of ReadReq misses +system.cpu3.dcache.ReadReq_misses::total 482 # number of ReadReq misses +system.cpu3.dcache.WriteReq_misses::cpu3.data 144 # number of WriteReq misses +system.cpu3.dcache.WriteReq_misses::total 144 # number of WriteReq misses +system.cpu3.dcache.SwapReq_misses::cpu3.data 52 # number of SwapReq misses +system.cpu3.dcache.SwapReq_misses::total 52 # number of SwapReq misses +system.cpu3.dcache.demand_misses::cpu3.data 626 # number of demand (read+write) misses +system.cpu3.dcache.demand_misses::total 626 # number of demand (read+write) misses +system.cpu3.dcache.overall_misses::cpu3.data 626 # number of overall misses +system.cpu3.dcache.overall_misses::total 626 # number of overall misses +system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 4340000 # number of ReadReq miss cycles +system.cpu3.dcache.ReadReq_miss_latency::total 4340000 # number of ReadReq miss cycles +system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 3297000 # number of WriteReq miss cycles +system.cpu3.dcache.WriteReq_miss_latency::total 3297000 # number of WriteReq miss cycles +system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 320500 # number of SwapReq miss cycles +system.cpu3.dcache.SwapReq_miss_latency::total 320500 # number of SwapReq miss cycles +system.cpu3.dcache.demand_miss_latency::cpu3.data 7637000 # number of demand (read+write) miss cycles +system.cpu3.dcache.demand_miss_latency::total 7637000 # number of demand (read+write) miss cycles +system.cpu3.dcache.overall_miss_latency::cpu3.data 7637000 # number of overall miss cycles +system.cpu3.dcache.overall_miss_latency::total 7637000 # number of overall miss cycles +system.cpu3.dcache.ReadReq_accesses::cpu3.data 50043 # number of ReadReq accesses(hits+misses) +system.cpu3.dcache.ReadReq_accesses::total 50043 # number of ReadReq accesses(hits+misses) +system.cpu3.dcache.WriteReq_accesses::cpu3.data 36665 # number of WriteReq accesses(hits+misses) +system.cpu3.dcache.WriteReq_accesses::total 36665 # number of WriteReq accesses(hits+misses) +system.cpu3.dcache.SwapReq_accesses::cpu3.data 66 # number of SwapReq accesses(hits+misses) +system.cpu3.dcache.SwapReq_accesses::total 66 # number of SwapReq accesses(hits+misses) +system.cpu3.dcache.demand_accesses::cpu3.data 86708 # number of demand (read+write) accesses +system.cpu3.dcache.demand_accesses::total 86708 # number of demand (read+write) accesses +system.cpu3.dcache.overall_accesses::cpu3.data 86708 # number of overall (read+write) accesses +system.cpu3.dcache.overall_accesses::total 86708 # number of overall (read+write) accesses +system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.009632 # miss rate for ReadReq accesses +system.cpu3.dcache.ReadReq_miss_rate::total 0.009632 # miss rate for ReadReq accesses +system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.003927 # miss rate for WriteReq accesses +system.cpu3.dcache.WriteReq_miss_rate::total 0.003927 # miss rate for WriteReq accesses +system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.787879 # miss rate for SwapReq accesses +system.cpu3.dcache.SwapReq_miss_rate::total 0.787879 # miss rate for SwapReq accesses +system.cpu3.dcache.demand_miss_rate::cpu3.data 0.007220 # miss rate for demand accesses +system.cpu3.dcache.demand_miss_rate::total 0.007220 # miss rate for demand accesses +system.cpu3.dcache.overall_miss_rate::cpu3.data 0.007220 # miss rate for overall accesses +system.cpu3.dcache.overall_miss_rate::total 0.007220 # miss rate for overall accesses +system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 9004.149378 # average ReadReq miss latency +system.cpu3.dcache.ReadReq_avg_miss_latency::total 9004.149378 # average ReadReq miss latency +system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 22895.833333 # average WriteReq miss latency +system.cpu3.dcache.WriteReq_avg_miss_latency::total 22895.833333 # average WriteReq miss latency +system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 6163.461538 # average SwapReq miss latency +system.cpu3.dcache.SwapReq_avg_miss_latency::total 6163.461538 # average SwapReq miss latency +system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 12199.680511 # average overall miss latency +system.cpu3.dcache.demand_avg_miss_latency::total 12199.680511 # average overall miss latency +system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 12199.680511 # average overall miss latency +system.cpu3.dcache.overall_avg_miss_latency::total 12199.680511 # average overall miss latency system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu3.dcache.ReadReq_mshr_hits::cpu3.data 326 # number of ReadReq MSHR hits -system.cpu3.dcache.ReadReq_mshr_hits::total 326 # number of ReadReq MSHR hits -system.cpu3.dcache.WriteReq_mshr_hits::cpu3.data 35 # number of WriteReq MSHR hits -system.cpu3.dcache.WriteReq_mshr_hits::total 35 # number of WriteReq MSHR hits +system.cpu3.dcache.ReadReq_mshr_hits::cpu3.data 322 # number of ReadReq MSHR hits +system.cpu3.dcache.ReadReq_mshr_hits::total 322 # number of ReadReq MSHR hits +system.cpu3.dcache.WriteReq_mshr_hits::cpu3.data 40 # number of WriteReq MSHR hits +system.cpu3.dcache.WriteReq_mshr_hits::total 40 # number of WriteReq MSHR hits system.cpu3.dcache.SwapReq_mshr_hits::cpu3.data 1 # number of SwapReq MSHR hits system.cpu3.dcache.SwapReq_mshr_hits::total 1 # number of SwapReq MSHR hits -system.cpu3.dcache.demand_mshr_hits::cpu3.data 361 # number of demand (read+write) MSHR hits -system.cpu3.dcache.demand_mshr_hits::total 361 # number of demand (read+write) MSHR hits -system.cpu3.dcache.overall_mshr_hits::cpu3.data 361 # number of overall MSHR hits -system.cpu3.dcache.overall_mshr_hits::total 361 # number of overall MSHR hits -system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 170 # number of ReadReq MSHR misses -system.cpu3.dcache.ReadReq_mshr_misses::total 170 # number of ReadReq MSHR misses -system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 105 # number of WriteReq MSHR misses -system.cpu3.dcache.WriteReq_mshr_misses::total 105 # number of WriteReq MSHR misses -system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 59 # number of SwapReq MSHR misses -system.cpu3.dcache.SwapReq_mshr_misses::total 59 # number of SwapReq MSHR misses -system.cpu3.dcache.demand_mshr_misses::cpu3.data 275 # number of demand (read+write) MSHR misses -system.cpu3.dcache.demand_mshr_misses::total 275 # number of demand (read+write) MSHR misses -system.cpu3.dcache.overall_mshr_misses::cpu3.data 275 # number of overall MSHR misses -system.cpu3.dcache.overall_mshr_misses::total 275 # number of overall MSHR misses -system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 1125000 # number of ReadReq MSHR miss cycles -system.cpu3.dcache.ReadReq_mshr_miss_latency::total 1125000 # number of ReadReq MSHR miss cycles -system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1450500 # number of WriteReq MSHR miss cycles -system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1450500 # number of WriteReq MSHR miss cycles -system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 296500 # number of SwapReq MSHR miss cycles -system.cpu3.dcache.SwapReq_mshr_miss_latency::total 296500 # number of SwapReq MSHR miss cycles -system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 2575500 # number of demand (read+write) MSHR miss cycles -system.cpu3.dcache.demand_mshr_miss_latency::total 2575500 # number of demand (read+write) MSHR miss cycles -system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 2575500 # number of overall MSHR miss cycles -system.cpu3.dcache.overall_mshr_miss_latency::total 2575500 # number of overall MSHR miss cycles -system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.003324 # mshr miss rate for ReadReq accesses -system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.003324 # mshr miss rate for ReadReq accesses -system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.002740 # mshr miss rate for WriteReq accesses -system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.002740 # mshr miss rate for WriteReq accesses -system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.819444 # mshr miss rate for SwapReq accesses -system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.819444 # mshr miss rate for SwapReq accesses -system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.003074 # mshr miss rate for demand accesses -system.cpu3.dcache.demand_mshr_miss_rate::total 0.003074 # mshr miss rate for demand accesses -system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.003074 # mshr miss rate for overall accesses -system.cpu3.dcache.overall_mshr_miss_rate::total 0.003074 # mshr miss rate for overall accesses -system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 6617.647059 # average ReadReq mshr miss latency -system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 6617.647059 # average ReadReq mshr miss latency -system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 13814.285714 # average WriteReq mshr miss latency -system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 13814.285714 # average WriteReq mshr miss latency -system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 5025.423729 # average SwapReq mshr miss latency -system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 5025.423729 # average SwapReq mshr miss latency -system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 9365.454545 # average overall mshr miss latency -system.cpu3.dcache.demand_avg_mshr_miss_latency::total 9365.454545 # average overall mshr miss latency -system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 9365.454545 # average overall mshr miss latency -system.cpu3.dcache.overall_avg_mshr_miss_latency::total 9365.454545 # average overall mshr miss latency -system.cpu3.icache.tags.pwrStateResidencyTicks::UNDEFINED 124830000 # Cumulative time (in ticks) in various power states -system.cpu3.icache.tags.replacements 586 # number of replacements -system.cpu3.icache.tags.tagsinuse 96.347148 # Cycle average of tags in use -system.cpu3.icache.tags.total_refs 27016 # Total number of references to valid blocks. -system.cpu3.icache.tags.sampled_refs 724 # Sample count of references to valid blocks. -system.cpu3.icache.tags.avg_refs 37.314917 # Average number of references to valid blocks. +system.cpu3.dcache.demand_mshr_hits::cpu3.data 362 # number of demand (read+write) MSHR hits +system.cpu3.dcache.demand_mshr_hits::total 362 # number of demand (read+write) MSHR hits +system.cpu3.dcache.overall_mshr_hits::cpu3.data 362 # number of overall MSHR hits +system.cpu3.dcache.overall_mshr_hits::total 362 # number of overall MSHR hits +system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 160 # number of ReadReq MSHR misses +system.cpu3.dcache.ReadReq_mshr_misses::total 160 # number of ReadReq MSHR misses +system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 104 # number of WriteReq MSHR misses +system.cpu3.dcache.WriteReq_mshr_misses::total 104 # number of WriteReq MSHR misses +system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 51 # number of SwapReq MSHR misses +system.cpu3.dcache.SwapReq_mshr_misses::total 51 # number of SwapReq MSHR misses +system.cpu3.dcache.demand_mshr_misses::cpu3.data 264 # number of demand (read+write) MSHR misses +system.cpu3.dcache.demand_mshr_misses::total 264 # number of demand (read+write) MSHR misses +system.cpu3.dcache.overall_mshr_misses::cpu3.data 264 # number of overall MSHR misses +system.cpu3.dcache.overall_mshr_misses::total 264 # number of overall MSHR misses +system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 1241000 # number of ReadReq MSHR miss cycles +system.cpu3.dcache.ReadReq_mshr_miss_latency::total 1241000 # number of ReadReq MSHR miss cycles +system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1631000 # number of WriteReq MSHR miss cycles +system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1631000 # number of WriteReq MSHR miss cycles +system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 268500 # number of SwapReq MSHR miss cycles +system.cpu3.dcache.SwapReq_mshr_miss_latency::total 268500 # number of SwapReq MSHR miss cycles +system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 2872000 # number of demand (read+write) MSHR miss cycles +system.cpu3.dcache.demand_mshr_miss_latency::total 2872000 # number of demand (read+write) MSHR miss cycles +system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 2872000 # number of overall MSHR miss cycles +system.cpu3.dcache.overall_mshr_miss_latency::total 2872000 # number of overall MSHR miss cycles +system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.003197 # mshr miss rate for ReadReq accesses +system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.003197 # mshr miss rate for ReadReq accesses +system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.002836 # mshr miss rate for WriteReq accesses +system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.002836 # mshr miss rate for WriteReq accesses +system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.772727 # mshr miss rate for SwapReq accesses +system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.772727 # mshr miss rate for SwapReq accesses +system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.003045 # mshr miss rate for demand accesses +system.cpu3.dcache.demand_mshr_miss_rate::total 0.003045 # mshr miss rate for demand accesses +system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.003045 # mshr miss rate for overall accesses +system.cpu3.dcache.overall_mshr_miss_rate::total 0.003045 # mshr miss rate for overall accesses +system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 7756.250000 # average ReadReq mshr miss latency +system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 7756.250000 # average ReadReq mshr miss latency +system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 15682.692308 # average WriteReq mshr miss latency +system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 15682.692308 # average WriteReq mshr miss latency +system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 5264.705882 # average SwapReq mshr miss latency +system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 5264.705882 # average SwapReq mshr miss latency +system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 10878.787879 # average overall mshr miss latency +system.cpu3.dcache.demand_avg_mshr_miss_latency::total 10878.787879 # average overall mshr miss latency +system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 10878.787879 # average overall mshr miss latency +system.cpu3.dcache.overall_avg_mshr_miss_latency::total 10878.787879 # average overall mshr miss latency +system.cpu3.icache.tags.pwrStateResidencyTicks::UNDEFINED 125996000 # Cumulative time (in ticks) in various power states +system.cpu3.icache.tags.replacements 575 # number of replacements +system.cpu3.icache.tags.tagsinuse 93.289458 # Cycle average of tags in use +system.cpu3.icache.tags.total_refs 28201 # Total number of references to valid blocks. +system.cpu3.icache.tags.sampled_refs 712 # Sample count of references to valid blocks. +system.cpu3.icache.tags.avg_refs 39.608146 # Average number of references to valid blocks. system.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.icache.tags.occ_blocks::cpu3.inst 96.347148 # Average occupied blocks per requestor -system.cpu3.icache.tags.occ_percent::cpu3.inst 0.188178 # Average percentage of cache occupancy -system.cpu3.icache.tags.occ_percent::total 0.188178 # Average percentage of cache occupancy -system.cpu3.icache.tags.occ_task_id_blocks::1024 138 # Occupied blocks per task id -system.cpu3.icache.tags.age_task_id_blocks_1024::0 19 # Occupied blocks per task id -system.cpu3.icache.tags.age_task_id_blocks_1024::1 119 # Occupied blocks per task id -system.cpu3.icache.tags.occ_task_id_percent::1024 0.269531 # Percentage of cache occupancy per task id -system.cpu3.icache.tags.tag_accesses 28596 # Number of tag accesses -system.cpu3.icache.tags.data_accesses 28596 # Number of data accesses -system.cpu3.icache.pwrStateResidencyTicks::UNDEFINED 124830000 # Cumulative time (in ticks) in various power states -system.cpu3.icache.ReadReq_hits::cpu3.inst 27016 # number of ReadReq hits -system.cpu3.icache.ReadReq_hits::total 27016 # number of ReadReq hits -system.cpu3.icache.demand_hits::cpu3.inst 27016 # number of demand (read+write) hits -system.cpu3.icache.demand_hits::total 27016 # number of demand (read+write) hits -system.cpu3.icache.overall_hits::cpu3.inst 27016 # number of overall hits -system.cpu3.icache.overall_hits::total 27016 # number of overall hits -system.cpu3.icache.ReadReq_misses::cpu3.inst 856 # number of ReadReq misses -system.cpu3.icache.ReadReq_misses::total 856 # number of ReadReq misses -system.cpu3.icache.demand_misses::cpu3.inst 856 # number of demand (read+write) misses -system.cpu3.icache.demand_misses::total 856 # number of demand (read+write) misses -system.cpu3.icache.overall_misses::cpu3.inst 856 # number of overall misses -system.cpu3.icache.overall_misses::total 856 # number of overall misses -system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 12888000 # number of ReadReq miss cycles -system.cpu3.icache.ReadReq_miss_latency::total 12888000 # number of ReadReq miss cycles -system.cpu3.icache.demand_miss_latency::cpu3.inst 12888000 # number of demand (read+write) miss cycles -system.cpu3.icache.demand_miss_latency::total 12888000 # number of demand (read+write) miss cycles -system.cpu3.icache.overall_miss_latency::cpu3.inst 12888000 # number of overall miss cycles -system.cpu3.icache.overall_miss_latency::total 12888000 # number of overall miss cycles -system.cpu3.icache.ReadReq_accesses::cpu3.inst 27872 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.ReadReq_accesses::total 27872 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.demand_accesses::cpu3.inst 27872 # number of demand (read+write) accesses -system.cpu3.icache.demand_accesses::total 27872 # number of demand (read+write) accesses -system.cpu3.icache.overall_accesses::cpu3.inst 27872 # number of overall (read+write) accesses -system.cpu3.icache.overall_accesses::total 27872 # number of overall (read+write) accesses -system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.030712 # miss rate for ReadReq accesses -system.cpu3.icache.ReadReq_miss_rate::total 0.030712 # miss rate for ReadReq accesses -system.cpu3.icache.demand_miss_rate::cpu3.inst 0.030712 # miss rate for demand accesses -system.cpu3.icache.demand_miss_rate::total 0.030712 # miss rate for demand accesses -system.cpu3.icache.overall_miss_rate::cpu3.inst 0.030712 # miss rate for overall accesses -system.cpu3.icache.overall_miss_rate::total 0.030712 # miss rate for overall accesses -system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 15056.074766 # average ReadReq miss latency -system.cpu3.icache.ReadReq_avg_miss_latency::total 15056.074766 # average ReadReq miss latency -system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 15056.074766 # average overall miss latency -system.cpu3.icache.demand_avg_miss_latency::total 15056.074766 # average overall miss latency -system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 15056.074766 # average overall miss latency -system.cpu3.icache.overall_avg_miss_latency::total 15056.074766 # average overall miss latency -system.cpu3.icache.blocked_cycles::no_mshrs 17 # number of cycles access was blocked +system.cpu3.icache.tags.occ_blocks::cpu3.inst 93.289458 # Average occupied blocks per requestor +system.cpu3.icache.tags.occ_percent::cpu3.inst 0.182206 # Average percentage of cache occupancy +system.cpu3.icache.tags.occ_percent::total 0.182206 # Average percentage of cache occupancy +system.cpu3.icache.tags.occ_task_id_blocks::1024 137 # Occupied blocks per task id +system.cpu3.icache.tags.age_task_id_blocks_1024::0 16 # Occupied blocks per task id +system.cpu3.icache.tags.age_task_id_blocks_1024::1 109 # Occupied blocks per task id +system.cpu3.icache.tags.age_task_id_blocks_1024::2 12 # Occupied blocks per task id +system.cpu3.icache.tags.occ_task_id_percent::1024 0.267578 # Percentage of cache occupancy per task id +system.cpu3.icache.tags.tag_accesses 29751 # Number of tag accesses +system.cpu3.icache.tags.data_accesses 29751 # Number of data accesses +system.cpu3.icache.pwrStateResidencyTicks::UNDEFINED 125996000 # Cumulative time (in ticks) in various power states +system.cpu3.icache.ReadReq_hits::cpu3.inst 28201 # number of ReadReq hits +system.cpu3.icache.ReadReq_hits::total 28201 # number of ReadReq hits +system.cpu3.icache.demand_hits::cpu3.inst 28201 # number of demand (read+write) hits +system.cpu3.icache.demand_hits::total 28201 # number of demand (read+write) hits +system.cpu3.icache.overall_hits::cpu3.inst 28201 # number of overall hits +system.cpu3.icache.overall_hits::total 28201 # number of overall hits +system.cpu3.icache.ReadReq_misses::cpu3.inst 838 # number of ReadReq misses +system.cpu3.icache.ReadReq_misses::total 838 # number of ReadReq misses +system.cpu3.icache.demand_misses::cpu3.inst 838 # number of demand (read+write) misses +system.cpu3.icache.demand_misses::total 838 # number of demand (read+write) misses +system.cpu3.icache.overall_misses::cpu3.inst 838 # number of overall misses +system.cpu3.icache.overall_misses::total 838 # number of overall misses +system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 13273000 # number of ReadReq miss cycles +system.cpu3.icache.ReadReq_miss_latency::total 13273000 # number of ReadReq miss cycles +system.cpu3.icache.demand_miss_latency::cpu3.inst 13273000 # number of demand (read+write) miss cycles +system.cpu3.icache.demand_miss_latency::total 13273000 # number of demand (read+write) miss cycles +system.cpu3.icache.overall_miss_latency::cpu3.inst 13273000 # number of overall miss cycles +system.cpu3.icache.overall_miss_latency::total 13273000 # number of overall miss cycles +system.cpu3.icache.ReadReq_accesses::cpu3.inst 29039 # number of ReadReq accesses(hits+misses) +system.cpu3.icache.ReadReq_accesses::total 29039 # number of ReadReq accesses(hits+misses) +system.cpu3.icache.demand_accesses::cpu3.inst 29039 # number of demand (read+write) accesses +system.cpu3.icache.demand_accesses::total 29039 # number of demand (read+write) accesses +system.cpu3.icache.overall_accesses::cpu3.inst 29039 # number of overall (read+write) accesses +system.cpu3.icache.overall_accesses::total 29039 # number of overall (read+write) accesses +system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.028858 # miss rate for ReadReq accesses +system.cpu3.icache.ReadReq_miss_rate::total 0.028858 # miss rate for ReadReq accesses +system.cpu3.icache.demand_miss_rate::cpu3.inst 0.028858 # miss rate for demand accesses +system.cpu3.icache.demand_miss_rate::total 0.028858 # miss rate for demand accesses +system.cpu3.icache.overall_miss_rate::cpu3.inst 0.028858 # miss rate for overall accesses +system.cpu3.icache.overall_miss_rate::total 0.028858 # miss rate for overall accesses +system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 15838.902148 # average ReadReq miss latency +system.cpu3.icache.ReadReq_avg_miss_latency::total 15838.902148 # average ReadReq miss latency +system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 15838.902148 # average overall miss latency +system.cpu3.icache.demand_avg_miss_latency::total 15838.902148 # average overall miss latency +system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 15838.902148 # average overall miss latency +system.cpu3.icache.overall_avg_miss_latency::total 15838.902148 # average overall miss latency +system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu3.icache.blocked::no_mshrs 1 # number of cycles access was blocked +system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu3.icache.avg_blocked_cycles::no_mshrs 17 # average number of cycles each access was blocked +system.cpu3.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu3.icache.writebacks::writebacks 586 # number of writebacks -system.cpu3.icache.writebacks::total 586 # number of writebacks -system.cpu3.icache.ReadReq_mshr_hits::cpu3.inst 132 # number of ReadReq MSHR hits -system.cpu3.icache.ReadReq_mshr_hits::total 132 # number of ReadReq MSHR hits -system.cpu3.icache.demand_mshr_hits::cpu3.inst 132 # number of demand (read+write) MSHR hits -system.cpu3.icache.demand_mshr_hits::total 132 # number of demand (read+write) MSHR hits -system.cpu3.icache.overall_mshr_hits::cpu3.inst 132 # number of overall MSHR hits -system.cpu3.icache.overall_mshr_hits::total 132 # number of overall MSHR hits -system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst 724 # number of ReadReq MSHR misses -system.cpu3.icache.ReadReq_mshr_misses::total 724 # number of ReadReq MSHR misses -system.cpu3.icache.demand_mshr_misses::cpu3.inst 724 # number of demand (read+write) MSHR misses -system.cpu3.icache.demand_mshr_misses::total 724 # number of demand (read+write) MSHR misses -system.cpu3.icache.overall_mshr_misses::cpu3.inst 724 # number of overall MSHR misses -system.cpu3.icache.overall_mshr_misses::total 724 # number of overall MSHR misses -system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 11106000 # number of ReadReq MSHR miss cycles -system.cpu3.icache.ReadReq_mshr_miss_latency::total 11106000 # number of ReadReq MSHR miss cycles -system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 11106000 # number of demand (read+write) MSHR miss cycles -system.cpu3.icache.demand_mshr_miss_latency::total 11106000 # number of demand (read+write) MSHR miss cycles -system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 11106000 # number of overall MSHR miss cycles -system.cpu3.icache.overall_mshr_miss_latency::total 11106000 # number of overall MSHR miss cycles -system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.025976 # mshr miss rate for ReadReq accesses -system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.025976 # mshr miss rate for ReadReq accesses -system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.025976 # mshr miss rate for demand accesses -system.cpu3.icache.demand_mshr_miss_rate::total 0.025976 # mshr miss rate for demand accesses -system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.025976 # mshr miss rate for overall accesses -system.cpu3.icache.overall_mshr_miss_rate::total 0.025976 # mshr miss rate for overall accesses -system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 15339.779006 # average ReadReq mshr miss latency -system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 15339.779006 # average ReadReq mshr miss latency -system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 15339.779006 # average overall mshr miss latency -system.cpu3.icache.demand_avg_mshr_miss_latency::total 15339.779006 # average overall mshr miss latency -system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 15339.779006 # average overall mshr miss latency -system.cpu3.icache.overall_avg_mshr_miss_latency::total 15339.779006 # average overall mshr miss latency -system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 124830000 # Cumulative time (in ticks) in various power states +system.cpu3.icache.writebacks::writebacks 575 # number of writebacks +system.cpu3.icache.writebacks::total 575 # number of writebacks +system.cpu3.icache.ReadReq_mshr_hits::cpu3.inst 126 # number of ReadReq MSHR hits +system.cpu3.icache.ReadReq_mshr_hits::total 126 # number of ReadReq MSHR hits +system.cpu3.icache.demand_mshr_hits::cpu3.inst 126 # number of demand (read+write) MSHR hits +system.cpu3.icache.demand_mshr_hits::total 126 # number of demand (read+write) MSHR hits +system.cpu3.icache.overall_mshr_hits::cpu3.inst 126 # number of overall MSHR hits +system.cpu3.icache.overall_mshr_hits::total 126 # number of overall MSHR hits +system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst 712 # number of ReadReq MSHR misses +system.cpu3.icache.ReadReq_mshr_misses::total 712 # number of ReadReq MSHR misses +system.cpu3.icache.demand_mshr_misses::cpu3.inst 712 # number of demand (read+write) MSHR misses +system.cpu3.icache.demand_mshr_misses::total 712 # number of demand (read+write) MSHR misses +system.cpu3.icache.overall_mshr_misses::cpu3.inst 712 # number of overall MSHR misses +system.cpu3.icache.overall_mshr_misses::total 712 # number of overall MSHR misses +system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 11453500 # number of ReadReq MSHR miss cycles +system.cpu3.icache.ReadReq_mshr_miss_latency::total 11453500 # number of ReadReq MSHR miss cycles +system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 11453500 # number of demand (read+write) MSHR miss cycles +system.cpu3.icache.demand_mshr_miss_latency::total 11453500 # number of demand (read+write) MSHR miss cycles +system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 11453500 # number of overall MSHR miss cycles +system.cpu3.icache.overall_mshr_miss_latency::total 11453500 # number of overall MSHR miss cycles +system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.024519 # mshr miss rate for ReadReq accesses +system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.024519 # mshr miss rate for ReadReq accesses +system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.024519 # mshr miss rate for demand accesses +system.cpu3.icache.demand_mshr_miss_rate::total 0.024519 # mshr miss rate for demand accesses +system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.024519 # mshr miss rate for overall accesses +system.cpu3.icache.overall_mshr_miss_rate::total 0.024519 # mshr miss rate for overall accesses +system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 16086.376404 # average ReadReq mshr miss latency +system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 16086.376404 # average ReadReq mshr miss latency +system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 16086.376404 # average overall mshr miss latency +system.cpu3.icache.demand_avg_mshr_miss_latency::total 16086.376404 # average overall mshr miss latency +system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 16086.376404 # average overall mshr miss latency +system.cpu3.icache.overall_avg_mshr_miss_latency::total 16086.376404 # average overall mshr miss latency +system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 125996000 # Cumulative time (in ticks) in various power states system.l2c.tags.replacements 0 # number of replacements -system.l2c.tags.tagsinuse 566.391309 # Cycle average of tags in use -system.l2c.tags.total_refs 3152 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 716 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 4.402235 # Average number of references to valid blocks. +system.l2c.tags.tagsinuse 566.450222 # Cycle average of tags in use +system.l2c.tags.total_refs 3196 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 710 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 4.501408 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::cpu0.inst 300.631868 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 144.597180 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 70.863487 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 15.770640 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 7.294857 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 10.082216 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.inst 7.192526 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.data 9.958536 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::cpu0.inst 0.004587 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.002206 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.001081 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.000241 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.inst 0.000111 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::cpu0.inst 300.277327 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 144.720872 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 69.261985 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 16.352170 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.inst 9.533779 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.data 10.075907 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3.inst 5.908934 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3.data 10.319248 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::cpu0.inst 0.004582 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.002208 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.001057 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.000250 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.inst 0.000145 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu2.data 0.000154 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3.inst 0.000110 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3.data 0.000152 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.008642 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1024 716 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 177 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 484 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1024 0.010925 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 31812 # Number of tag accesses -system.l2c.tags.data_accesses 31812 # Number of data accesses -system.l2c.pwrStateResidencyTicks::UNDEFINED 124830000 # Cumulative time (in ticks) in various power states +system.l2c.tags.occ_percent::cpu3.inst 0.000090 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu3.data 0.000157 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.008643 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1024 710 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 145 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 513 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1024 0.010834 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 32110 # Number of tag accesses +system.l2c.tags.data_accesses 32110 # Number of data accesses +system.l2c.pwrStateResidencyTicks::UNDEFINED 125996000 # Cumulative time (in ticks) in various power states system.l2c.WritebackDirty_hits::writebacks 1 # number of WritebackDirty hits system.l2c.WritebackDirty_hits::total 1 # number of WritebackDirty hits -system.l2c.WritebackClean_hits::writebacks 730 # number of WritebackClean hits -system.l2c.WritebackClean_hits::total 730 # number of WritebackClean hits -system.l2c.UpgradeReq_hits::cpu0.data 23 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 22 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu2.data 25 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu3.data 20 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 90 # number of UpgradeReq hits -system.l2c.ReadCleanReq_hits::cpu0.inst 318 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::cpu1.inst 594 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::cpu2.inst 679 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::cpu3.inst 707 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::total 2298 # number of ReadCleanReq hits +system.l2c.WritebackClean_hits::writebacks 757 # number of WritebackClean hits +system.l2c.WritebackClean_hits::total 757 # number of WritebackClean hits +system.l2c.UpgradeReq_hits::cpu0.data 22 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 20 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu2.data 21 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu3.data 21 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 84 # number of UpgradeReq hits +system.l2c.ReadCleanReq_hits::cpu0.inst 321 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::cpu1.inst 637 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::cpu2.inst 664 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::cpu3.inst 699 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::total 2321 # number of ReadCleanReq hits system.l2c.ReadSharedReq_hits::cpu0.data 5 # number of ReadSharedReq hits system.l2c.ReadSharedReq_hits::cpu1.data 5 # number of ReadSharedReq hits system.l2c.ReadSharedReq_hits::cpu2.data 11 # number of ReadSharedReq hits system.l2c.ReadSharedReq_hits::cpu3.data 11 # number of ReadSharedReq hits system.l2c.ReadSharedReq_hits::total 32 # number of ReadSharedReq hits -system.l2c.demand_hits::cpu0.inst 318 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 321 # number of demand (read+write) hits system.l2c.demand_hits::cpu0.data 5 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 594 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 637 # number of demand (read+write) hits system.l2c.demand_hits::cpu1.data 5 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.inst 679 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.inst 664 # number of demand (read+write) hits system.l2c.demand_hits::cpu2.data 11 # number of demand (read+write) hits -system.l2c.demand_hits::cpu3.inst 707 # number of demand (read+write) hits +system.l2c.demand_hits::cpu3.inst 699 # number of demand (read+write) hits system.l2c.demand_hits::cpu3.data 11 # number of demand (read+write) hits -system.l2c.demand_hits::total 2330 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.inst 318 # number of overall hits +system.l2c.demand_hits::total 2353 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.inst 321 # number of overall hits system.l2c.overall_hits::cpu0.data 5 # number of overall hits -system.l2c.overall_hits::cpu1.inst 594 # number of overall hits +system.l2c.overall_hits::cpu1.inst 637 # number of overall hits system.l2c.overall_hits::cpu1.data 5 # number of overall hits -system.l2c.overall_hits::cpu2.inst 679 # number of overall hits +system.l2c.overall_hits::cpu2.inst 664 # number of overall hits system.l2c.overall_hits::cpu2.data 11 # number of overall hits -system.l2c.overall_hits::cpu3.inst 707 # number of overall hits +system.l2c.overall_hits::cpu3.inst 699 # number of overall hits system.l2c.overall_hits::cpu3.data 11 # number of overall hits -system.l2c.overall_hits::total 2330 # number of overall hits +system.l2c.overall_hits::total 2353 # number of overall hits system.l2c.ReadExReq_misses::cpu0.data 94 # number of ReadExReq misses system.l2c.ReadExReq_misses::cpu1.data 13 # number of ReadExReq misses system.l2c.ReadExReq_misses::cpu2.data 12 # number of ReadExReq misses system.l2c.ReadExReq_misses::cpu3.data 12 # number of ReadExReq misses system.l2c.ReadExReq_misses::total 131 # number of ReadExReq misses -system.l2c.ReadCleanReq_misses::cpu0.inst 378 # number of ReadCleanReq misses +system.l2c.ReadCleanReq_misses::cpu0.inst 376 # number of ReadCleanReq misses system.l2c.ReadCleanReq_misses::cpu1.inst 96 # number of ReadCleanReq misses system.l2c.ReadCleanReq_misses::cpu2.inst 23 # number of ReadCleanReq misses -system.l2c.ReadCleanReq_misses::cpu3.inst 17 # number of ReadCleanReq misses -system.l2c.ReadCleanReq_misses::total 514 # number of ReadCleanReq misses +system.l2c.ReadCleanReq_misses::cpu3.inst 13 # number of ReadCleanReq misses +system.l2c.ReadCleanReq_misses::total 508 # number of ReadCleanReq misses system.l2c.ReadSharedReq_misses::cpu0.data 76 # number of ReadSharedReq misses system.l2c.ReadSharedReq_misses::cpu1.data 9 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu2.data 3 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu3.data 2 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu2.data 2 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu3.data 3 # number of ReadSharedReq misses system.l2c.ReadSharedReq_misses::total 90 # number of ReadSharedReq misses -system.l2c.demand_misses::cpu0.inst 378 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 376 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.data 170 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.inst 96 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.data 22 # number of demand (read+write) misses system.l2c.demand_misses::cpu2.inst 23 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.data 15 # number of demand (read+write) misses -system.l2c.demand_misses::cpu3.inst 17 # number of demand (read+write) misses -system.l2c.demand_misses::cpu3.data 14 # number of demand (read+write) misses -system.l2c.demand_misses::total 735 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.inst 378 # number of overall misses +system.l2c.demand_misses::cpu2.data 14 # number of demand (read+write) misses +system.l2c.demand_misses::cpu3.inst 13 # number of demand (read+write) misses +system.l2c.demand_misses::cpu3.data 15 # number of demand (read+write) misses +system.l2c.demand_misses::total 729 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.inst 376 # number of overall misses system.l2c.overall_misses::cpu0.data 170 # number of overall misses system.l2c.overall_misses::cpu1.inst 96 # number of overall misses system.l2c.overall_misses::cpu1.data 22 # number of overall misses system.l2c.overall_misses::cpu2.inst 23 # number of overall misses -system.l2c.overall_misses::cpu2.data 15 # number of overall misses -system.l2c.overall_misses::cpu3.inst 17 # number of overall misses -system.l2c.overall_misses::cpu3.data 14 # number of overall misses -system.l2c.overall_misses::total 735 # number of overall misses -system.l2c.ReadExReq_miss_latency::cpu0.data 7962000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 1092000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu2.data 1485500 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu3.data 1007500 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 11547000 # number of ReadExReq miss cycles -system.l2c.ReadCleanReq_miss_latency::cpu0.inst 32045000 # number of ReadCleanReq miss cycles -system.l2c.ReadCleanReq_miss_latency::cpu1.inst 7767000 # number of ReadCleanReq miss cycles -system.l2c.ReadCleanReq_miss_latency::cpu2.inst 1841000 # number of ReadCleanReq miss cycles -system.l2c.ReadCleanReq_miss_latency::cpu3.inst 2001000 # number of ReadCleanReq miss cycles -system.l2c.ReadCleanReq_miss_latency::total 43654000 # number of ReadCleanReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu0.data 6727000 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu1.data 1292500 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu2.data 289000 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu3.data 179500 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::total 8488000 # number of ReadSharedReq miss cycles -system.l2c.demand_miss_latency::cpu0.inst 32045000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 14689000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 7767000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 2384500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.inst 1841000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.data 1774500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu3.inst 2001000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu3.data 1187000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 63689000 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.inst 32045000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 14689000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 7767000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 2384500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.inst 1841000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.data 1774500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu3.inst 2001000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu3.data 1187000 # number of overall miss cycles -system.l2c.overall_miss_latency::total 63689000 # number of overall miss cycles +system.l2c.overall_misses::cpu2.data 14 # number of overall misses +system.l2c.overall_misses::cpu3.inst 13 # number of overall misses +system.l2c.overall_misses::cpu3.data 15 # number of overall misses +system.l2c.overall_misses::total 729 # number of overall misses +system.l2c.ReadExReq_miss_latency::cpu0.data 7962500 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 1106000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu2.data 1022500 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu3.data 1199500 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 11290500 # number of ReadExReq miss cycles +system.l2c.ReadCleanReq_miss_latency::cpu0.inst 32133500 # number of ReadCleanReq miss cycles +system.l2c.ReadCleanReq_miss_latency::cpu1.inst 8531500 # number of ReadCleanReq miss cycles +system.l2c.ReadCleanReq_miss_latency::cpu2.inst 2347000 # number of ReadCleanReq miss cycles +system.l2c.ReadCleanReq_miss_latency::cpu3.inst 2460500 # number of ReadCleanReq miss cycles +system.l2c.ReadCleanReq_miss_latency::total 45472500 # number of ReadCleanReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu0.data 6902500 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu1.data 767000 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu2.data 179000 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu3.data 339000 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::total 8187500 # number of ReadSharedReq miss cycles +system.l2c.demand_miss_latency::cpu0.inst 32133500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 14865000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 8531500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 1873000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.inst 2347000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.data 1201500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu3.inst 2460500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu3.data 1538500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 64950500 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.inst 32133500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 14865000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 8531500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 1873000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.inst 2347000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.data 1201500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu3.inst 2460500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu3.data 1538500 # number of overall miss cycles +system.l2c.overall_miss_latency::total 64950500 # number of overall miss cycles system.l2c.WritebackDirty_accesses::writebacks 1 # number of WritebackDirty accesses(hits+misses) system.l2c.WritebackDirty_accesses::total 1 # number of WritebackDirty accesses(hits+misses) -system.l2c.WritebackClean_accesses::writebacks 730 # number of WritebackClean accesses(hits+misses) -system.l2c.WritebackClean_accesses::total 730 # number of WritebackClean accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 23 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 22 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu2.data 25 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu3.data 20 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 90 # number of UpgradeReq accesses(hits+misses) +system.l2c.WritebackClean_accesses::writebacks 757 # number of WritebackClean accesses(hits+misses) +system.l2c.WritebackClean_accesses::total 757 # number of WritebackClean accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 22 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 20 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu2.data 21 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu3.data 21 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 84 # number of UpgradeReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu0.data 94 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu1.data 13 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu2.data 12 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu3.data 12 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::total 131 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadCleanReq_accesses::cpu0.inst 696 # number of ReadCleanReq accesses(hits+misses) -system.l2c.ReadCleanReq_accesses::cpu1.inst 690 # number of ReadCleanReq accesses(hits+misses) -system.l2c.ReadCleanReq_accesses::cpu2.inst 702 # number of ReadCleanReq accesses(hits+misses) -system.l2c.ReadCleanReq_accesses::cpu3.inst 724 # number of ReadCleanReq accesses(hits+misses) -system.l2c.ReadCleanReq_accesses::total 2812 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::cpu0.inst 697 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::cpu1.inst 733 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::cpu2.inst 687 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::cpu3.inst 712 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::total 2829 # number of ReadCleanReq accesses(hits+misses) system.l2c.ReadSharedReq_accesses::cpu0.data 81 # number of ReadSharedReq accesses(hits+misses) system.l2c.ReadSharedReq_accesses::cpu1.data 14 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu2.data 14 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu3.data 13 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu2.data 13 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu3.data 14 # number of ReadSharedReq accesses(hits+misses) system.l2c.ReadSharedReq_accesses::total 122 # number of ReadSharedReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.inst 696 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 697 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu0.data 175 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 690 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 733 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu1.data 27 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.inst 702 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.data 26 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu3.inst 724 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu3.data 25 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 3065 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 696 # number of overall (read+write) accesses +system.l2c.demand_accesses::cpu2.inst 687 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.data 25 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu3.inst 712 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu3.data 26 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 3082 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 697 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu0.data 175 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 690 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 733 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu1.data 27 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.inst 702 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.data 26 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu3.inst 724 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu3.data 25 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 3065 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.inst 687 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.data 25 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu3.inst 712 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu3.data 26 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 3082 # number of overall (read+write) accesses system.l2c.ReadExReq_miss_rate::cpu0.data 1 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::cpu1.data 1 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::cpu3.data 1 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses -system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.543103 # miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.139130 # miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_miss_rate::cpu2.inst 0.032764 # miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_miss_rate::cpu3.inst 0.023481 # miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_miss_rate::total 0.182788 # miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.539455 # miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.130969 # miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_miss_rate::cpu2.inst 0.033479 # miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_miss_rate::cpu3.inst 0.018258 # miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_miss_rate::total 0.179569 # miss rate for ReadCleanReq accesses system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.938272 # miss rate for ReadSharedReq accesses system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.642857 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu2.data 0.214286 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu3.data 0.153846 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu2.data 0.153846 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu3.data 0.214286 # miss rate for ReadSharedReq accesses system.l2c.ReadSharedReq_miss_rate::total 0.737705 # miss rate for ReadSharedReq accesses -system.l2c.demand_miss_rate::cpu0.inst 0.543103 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.539455 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu0.data 0.971429 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.139130 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.130969 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu1.data 0.814815 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.inst 0.032764 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.data 0.576923 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu3.inst 0.023481 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu3.data 0.560000 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.239804 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.inst 0.543103 # miss rate for overall accesses +system.l2c.demand_miss_rate::cpu2.inst 0.033479 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.data 0.560000 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu3.inst 0.018258 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu3.data 0.576923 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.236535 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.inst 0.539455 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu0.data 0.971429 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.139130 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.130969 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu1.data 0.814815 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.inst 0.032764 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.data 0.576923 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu3.inst 0.023481 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu3.data 0.560000 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.239804 # miss rate for overall accesses -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 84702.127660 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 84000 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu2.data 123791.666667 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu3.data 83958.333333 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 88145.038168 # average ReadExReq miss latency -system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 84775.132275 # average ReadCleanReq miss latency -system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 80906.250000 # average ReadCleanReq miss latency -system.l2c.ReadCleanReq_avg_miss_latency::cpu2.inst 80043.478261 # average ReadCleanReq miss latency -system.l2c.ReadCleanReq_avg_miss_latency::cpu3.inst 117705.882353 # average ReadCleanReq miss latency -system.l2c.ReadCleanReq_avg_miss_latency::total 84929.961089 # average ReadCleanReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 88513.157895 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 143611.111111 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu2.data 96333.333333 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu3.data 89750 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::total 94311.111111 # average ReadSharedReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 84775.132275 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 86405.882353 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 80906.250000 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 108386.363636 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.inst 80043.478261 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.data 118300 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu3.inst 117705.882353 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu3.data 84785.714286 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 86651.700680 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 84775.132275 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 86405.882353 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 80906.250000 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 108386.363636 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.inst 80043.478261 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.data 118300 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu3.inst 117705.882353 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu3.data 84785.714286 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 86651.700680 # average overall miss latency +system.l2c.overall_miss_rate::cpu2.inst 0.033479 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.data 0.560000 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu3.inst 0.018258 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu3.data 0.576923 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.236535 # miss rate for overall accesses +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 84707.446809 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 85076.923077 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu2.data 85208.333333 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu3.data 99958.333333 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 86187.022901 # average ReadExReq miss latency +system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 85461.436170 # average ReadCleanReq miss latency +system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 88869.791667 # average ReadCleanReq miss latency +system.l2c.ReadCleanReq_avg_miss_latency::cpu2.inst 102043.478261 # average ReadCleanReq miss latency +system.l2c.ReadCleanReq_avg_miss_latency::cpu3.inst 189269.230769 # average ReadCleanReq miss latency +system.l2c.ReadCleanReq_avg_miss_latency::total 89512.795276 # average ReadCleanReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 90822.368421 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 85222.222222 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu2.data 89500 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu3.data 113000 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::total 90972.222222 # average ReadSharedReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 85461.436170 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 87441.176471 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 88869.791667 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 85136.363636 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.inst 102043.478261 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.data 85821.428571 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu3.inst 189269.230769 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu3.data 102566.666667 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 89095.336077 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 85461.436170 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 87441.176471 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 88869.791667 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 85136.363636 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.inst 102043.478261 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.data 85821.428571 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu3.inst 189269.230769 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu3.data 102566.666667 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 89095.336077 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -2715,211 +2720,211 @@ system.l2c.ReadExReq_mshr_misses::cpu1.data 13 # system.l2c.ReadExReq_mshr_misses::cpu2.data 12 # number of ReadExReq MSHR misses system.l2c.ReadExReq_mshr_misses::cpu3.data 12 # number of ReadExReq MSHR misses system.l2c.ReadExReq_mshr_misses::total 131 # number of ReadExReq MSHR misses -system.l2c.ReadCleanReq_mshr_misses::cpu0.inst 376 # number of ReadCleanReq MSHR misses +system.l2c.ReadCleanReq_mshr_misses::cpu0.inst 374 # number of ReadCleanReq MSHR misses system.l2c.ReadCleanReq_mshr_misses::cpu1.inst 92 # number of ReadCleanReq MSHR misses system.l2c.ReadCleanReq_mshr_misses::cpu2.inst 14 # number of ReadCleanReq MSHR misses -system.l2c.ReadCleanReq_mshr_misses::cpu3.inst 14 # number of ReadCleanReq MSHR misses -system.l2c.ReadCleanReq_mshr_misses::total 496 # number of ReadCleanReq MSHR misses +system.l2c.ReadCleanReq_mshr_misses::cpu3.inst 10 # number of ReadCleanReq MSHR misses +system.l2c.ReadCleanReq_mshr_misses::total 490 # number of ReadCleanReq MSHR misses system.l2c.ReadSharedReq_mshr_misses::cpu0.data 76 # number of ReadSharedReq MSHR misses system.l2c.ReadSharedReq_mshr_misses::cpu1.data 9 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu2.data 3 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu3.data 2 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu2.data 2 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu3.data 3 # number of ReadSharedReq MSHR misses system.l2c.ReadSharedReq_mshr_misses::total 90 # number of ReadSharedReq MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 376 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 374 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu0.data 170 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu1.inst 92 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu1.data 22 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu2.inst 14 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2.data 15 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu3.inst 14 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu3.data 14 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 717 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 376 # number of overall MSHR misses +system.l2c.demand_mshr_misses::cpu2.data 14 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu3.inst 10 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu3.data 15 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 711 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0.inst 374 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu0.data 170 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu1.inst 92 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu1.data 22 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu2.inst 14 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2.data 15 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu3.inst 14 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu3.data 14 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 717 # number of overall MSHR misses -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 7022000 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 962000 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 1365500 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu3.data 887500 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 10237000 # number of ReadExReq MSHR miss cycles -system.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst 28190500 # number of ReadCleanReq MSHR miss cycles -system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst 6632500 # number of ReadCleanReq MSHR miss cycles -system.l2c.ReadCleanReq_mshr_miss_latency::cpu2.inst 1096000 # number of ReadCleanReq MSHR miss cycles -system.l2c.ReadCleanReq_mshr_miss_latency::cpu3.inst 1627000 # number of ReadCleanReq MSHR miss cycles -system.l2c.ReadCleanReq_mshr_miss_latency::total 37546000 # number of ReadCleanReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 5967000 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 1202500 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu2.data 259000 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu3.data 159500 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::total 7588000 # number of ReadSharedReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 28190500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 12989000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 6632500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 2164500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2.inst 1096000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2.data 1624500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu3.inst 1627000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu3.data 1047000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 55371000 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 28190500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 12989000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 6632500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 2164500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.inst 1096000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.data 1624500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu3.inst 1627000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu3.data 1047000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 55371000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_misses::cpu2.data 14 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu3.inst 10 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu3.data 15 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 711 # number of overall MSHR misses +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 7022500 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 976000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 902500 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu3.data 1079500 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 9980500 # number of ReadExReq MSHR miss cycles +system.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst 28295000 # number of ReadCleanReq MSHR miss cycles +system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst 7392500 # number of ReadCleanReq MSHR miss cycles +system.l2c.ReadCleanReq_mshr_miss_latency::cpu2.inst 1074500 # number of ReadCleanReq MSHR miss cycles +system.l2c.ReadCleanReq_mshr_miss_latency::cpu3.inst 1591500 # number of ReadCleanReq MSHR miss cycles +system.l2c.ReadCleanReq_mshr_miss_latency::total 38353500 # number of ReadCleanReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 6142500 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 677000 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu2.data 159000 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu3.data 309000 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::total 7287500 # number of ReadSharedReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 28295000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 13165000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 7392500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 1653000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.inst 1074500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.data 1061500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu3.inst 1591500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu3.data 1388500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 55621500 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 28295000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 13165000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 7392500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 1653000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.inst 1074500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.data 1061500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu3.inst 1591500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu3.data 1388500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 55621500 # number of overall MSHR miss cycles system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.540230 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.133333 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst 0.019943 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::cpu3.inst 0.019337 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::total 0.176387 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.536585 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.125512 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst 0.020378 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu3.inst 0.014045 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::total 0.173206 # mshr miss rate for ReadCleanReq accesses system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.938272 # mshr miss rate for ReadSharedReq accesses system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.642857 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu2.data 0.214286 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu3.data 0.153846 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu2.data 0.153846 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu3.data 0.214286 # mshr miss rate for ReadSharedReq accesses system.l2c.ReadSharedReq_mshr_miss_rate::total 0.737705 # mshr miss rate for ReadSharedReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.540230 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.536585 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu0.data 0.971429 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.133333 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.125512 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu1.data 0.814815 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.inst 0.019943 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.data 0.576923 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu3.inst 0.019337 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu3.data 0.560000 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.233931 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.540230 # mshr miss rate for overall accesses +system.l2c.demand_mshr_miss_rate::cpu2.inst 0.020378 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.data 0.560000 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3.inst 0.014045 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3.data 0.576923 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.230694 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.536585 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu0.data 0.971429 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.133333 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.125512 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu1.data 0.814815 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.inst 0.019943 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.data 0.576923 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu3.inst 0.019337 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu3.data 0.560000 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.233931 # mshr miss rate for overall accesses -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 74702.127660 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 74000 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 113791.666667 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 73958.333333 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 78145.038168 # average ReadExReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 74974.734043 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 72092.391304 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 78285.714286 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu3.inst 116214.285714 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 75697.580645 # average ReadCleanReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 78513.157895 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 133611.111111 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 86333.333333 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3.data 79750 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 84311.111111 # average ReadSharedReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 74974.734043 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 76405.882353 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 72092.391304 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 98386.363636 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 78285.714286 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.data 108300 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 116214.285714 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3.data 74785.714286 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 77225.941423 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 74974.734043 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 76405.882353 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 72092.391304 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 98386.363636 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 78285.714286 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.data 108300 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 116214.285714 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3.data 74785.714286 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 77225.941423 # average overall mshr miss latency -system.membus.snoop_filter.tot_requests 969 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 253 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.l2c.overall_mshr_miss_rate::cpu2.inst 0.020378 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.data 0.560000 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3.inst 0.014045 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3.data 0.576923 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.230694 # mshr miss rate for overall accesses +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 74707.446809 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 75076.923077 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 75208.333333 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 89958.333333 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 76187.022901 # average ReadExReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 75655.080214 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 80353.260870 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 76750 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu3.inst 159150 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 78272.448980 # average ReadCleanReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 80822.368421 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 75222.222222 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 79500 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3.data 103000 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 80972.222222 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 75655.080214 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 77441.176471 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 80353.260870 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 75136.363636 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 76750 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 75821.428571 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 159150 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.data 92566.666667 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 78229.957806 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 75655.080214 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 77441.176471 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 80353.260870 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 75136.363636 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 76750 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 75821.428571 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 159150 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.data 92566.666667 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 78229.957806 # average overall mshr miss latency +system.membus.snoop_filter.tot_requests 961 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 251 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 124830000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 585 # Transaction distribution -system.membus.trans_dist::UpgradeReq 194 # Transaction distribution -system.membus.trans_dist::ReadExReq 190 # Transaction distribution +system.membus.pwrStateResidencyTicks::UNDEFINED 125996000 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 579 # Transaction distribution +system.membus.trans_dist::UpgradeReq 193 # Transaction distribution +system.membus.trans_dist::ReadExReq 189 # Transaction distribution system.membus.trans_dist::ReadExResp 131 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 585 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1685 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1685 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 45824 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 45824 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 253 # Total snoops (count) +system.membus.trans_dist::ReadSharedReq 579 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1671 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1671 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 45440 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 45440 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 251 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 969 # Request fanout histogram +system.membus.snoop_fanout::samples 961 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 969 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 961 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 969 # Request fanout histogram -system.membus.reqLayer0.occupancy 889500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 961 # Request fanout histogram +system.membus.reqLayer0.occupancy 879000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 3809250 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 3.1 # Layer utilization (%) -system.toL2Bus.snoop_filter.tot_requests 6292 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 1720 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 3250 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.respLayer1.occupancy 3778500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 3.0 # Layer utilization (%) +system.toL2Bus.snoop_filter.tot_requests 6307 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 1738 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 3220 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 124830000 # Cumulative time (in ticks) in various power states -system.toL2Bus.trans_dist::ReadResp 3503 # Transaction distribution -system.toL2Bus.trans_dist::ReadRespWithInvalidate 8 # Transaction distribution +system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 125996000 # Cumulative time (in ticks) in various power states +system.toL2Bus.trans_dist::ReadResp 3510 # Transaction distribution +system.toL2Bus.trans_dist::ReadRespWithInvalidate 3 # Transaction distribution system.toL2Bus.trans_dist::WritebackDirty 1 # Transaction distribution -system.toL2Bus.trans_dist::WritebackClean 2099 # Transaction distribution +system.toL2Bus.trans_dist::WritebackClean 2115 # Transaction distribution system.toL2Bus.trans_dist::CleanEvict 1 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 284 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 284 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 395 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 395 # Transaction distribution -system.toL2Bus.trans_dist::ReadCleanReq 2812 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 700 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 277 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 277 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 399 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 399 # Transaction distribution +system.toL2Bus.trans_dist::ReadCleanReq 2829 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 685 # Transaction distribution system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1784 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 599 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 1936 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 373 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 1968 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 372 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 2034 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 380 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 9446 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 69632 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 594 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 2064 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 364 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 1925 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 379 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 1999 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 363 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 9472 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 69568 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 11264 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 79744 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 85184 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 1728 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 81024 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side 1664 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 83840 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side 1600 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 330496 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 1036 # Total snoops (count) -system.toL2Bus.snoopTraffic 53888 # Total snoop traffic (bytes) -system.toL2Bus.snoop_fanout::samples 4191 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.288475 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 1.109326 # Request fanout histogram +system.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 79232 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side 1600 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 82368 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side 1664 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 332608 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 1024 # Total snoops (count) +system.toL2Bus.snoopTraffic 53184 # Total snoop traffic (bytes) +system.toL2Bus.snoop_fanout::samples 4190 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.288067 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 1.121770 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 1322 31.54% 31.54% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 1164 27.77% 59.32% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 879 20.97% 80.29% # Request fanout histogram -system.toL2Bus.snoop_fanout::3 826 19.71% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 1349 32.20% 32.20% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 1142 27.26% 59.45% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 842 20.10% 79.55% # Request fanout histogram +system.toL2Bus.snoop_fanout::3 857 20.45% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::5 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram @@ -2928,24 +2933,24 @@ system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Re system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 4191 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 5261968 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 4190 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 5284470 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 4.2 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 1043496 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 1044996 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.8 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 528992 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 522995 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 1037993 # Layer occupancy (ticks) -system.toL2Bus.respLayer2.utilization 0.8 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 434459 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 1103492 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.utilization 0.9 # Layer utilization (%) +system.toL2Bus.respLayer3.occupancy 425474 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.3 # Layer utilization (%) -system.toL2Bus.respLayer4.occupancy 1056988 # Layer occupancy (ticks) +system.toL2Bus.respLayer4.occupancy 1034985 # Layer occupancy (ticks) system.toL2Bus.respLayer4.utilization 0.8 # Layer utilization (%) -system.toL2Bus.respLayer5.occupancy 424982 # Layer occupancy (ticks) -system.toL2Bus.respLayer5.utilization 0.3 # Layer utilization (%) -system.toL2Bus.respLayer6.occupancy 1087497 # Layer occupancy (ticks) +system.toL2Bus.respLayer5.occupancy 441461 # Layer occupancy (ticks) +system.toL2Bus.respLayer5.utilization 0.4 # Layer utilization (%) +system.toL2Bus.respLayer6.occupancy 1070994 # Layer occupancy (ticks) system.toL2Bus.respLayer6.utilization 0.9 # Layer utilization (%) -system.toL2Bus.respLayer7.occupancy 445966 # Layer occupancy (ticks) -system.toL2Bus.respLayer7.utilization 0.4 # Layer utilization (%) +system.toL2Bus.respLayer7.occupancy 421970 # Layer occupancy (ticks) +system.toL2Bus.respLayer7.utilization 0.3 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/config.ini b/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/config.ini index e7e819a35..6aaddcbd1 100644 --- a/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/config.ini +++ b/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/config.ini @@ -96,14 +96,14 @@ icache_port=system.cpu.icache.cpu_side [system.cpu.dcache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=false max_miss_count=0 mshrs=4 @@ -117,6 +117,7 @@ response_latency=2 sequential_access=false size=262144 system=system +tag_latency=2 tags=system.cpu.dcache.tags tgts_per_mshr=20 write_buffers=8 @@ -129,15 +130,16 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=262144 +tag_latency=2 [system.cpu.dstage2_mmu] type=ArmStage2MMU @@ -193,14 +195,14 @@ port=system.cpu.toL2Bus.slave[3] [system.cpu.icache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=true max_miss_count=0 mshrs=4 @@ -214,6 +216,7 @@ response_latency=2 sequential_access=false size=131072 system=system +tag_latency=2 tags=system.cpu.icache.tags tgts_per_mshr=20 write_buffers=8 @@ -226,15 +229,16 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=131072 +tag_latency=2 [system.cpu.interrupts] type=ArmInterrupts @@ -253,7 +257,7 @@ id_aa64isar0_el1=0 id_aa64isar1_el1=0 id_aa64mmfr0_el1=15728642 id_aa64mmfr1_el1=0 -id_aa64pfr0_el1=17 +id_aa64pfr0_el1=34 id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 @@ -325,14 +329,14 @@ port=system.cpu.toL2Bus.slave[2] [system.cpu.l2cache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=8 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=20 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=20 is_read_only=false max_miss_count=0 mshrs=20 @@ -346,6 +350,7 @@ response_latency=20 sequential_access=false size=2097152 system=system +tag_latency=20 tags=system.cpu.l2cache.tags tgts_per_mshr=12 write_buffers=8 @@ -358,15 +363,16 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=20 default_p_state=UNDEFINED eventq_index=0 -hit_latency=20 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=2097152 +tag_latency=20 [system.cpu.toL2Bus] type=CoherentXBar @@ -411,7 +417,7 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/arm/linux/vortex +executable=/dist/m5/cpu2000/binaries/arm/linux/vortex gid=100 input=cin kvmInSE=false @@ -442,6 +448,7 @@ transition_latency=100000000 [system.membus] type=CoherentXBar +children=snoop_filter clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 @@ -453,7 +460,7 @@ p_state_clk_gate_min=1000 point_of_coherency=true power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -461,6 +468,13 @@ width=16 master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + [system.physmem] type=SimpleMemory bandwidth=73.000000 @@ -469,6 +483,7 @@ conf_table_reported=true default_p_state=UNDEFINED eventq_index=0 in_addr_map=true +kvm_map=true latency=30000 latency_var=0 null=false @@ -476,7 +491,7 @@ p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null -range=0:134217727 +range=0:134217727:0:0:0:0 port=system.membus.master[0] [system.voltage_domain] diff --git a/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/simout b/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/simout index 34991f400..c41441e64 100755 --- a/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/simout +++ b/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/simout @@ -3,12 +3,12 @@ Redirecting stderr to build/ARM/tests/opt/quick/se/50.vortex/arm/linux/simple-ti gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 21 2016 14:37:41 -gem5 started Jul 21 2016 14:38:22 -gem5 executing on e108600-lin, pid 23076 -command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/50.vortex/arm/linux/simple-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/50.vortex/arm/linux/simple-timing +gem5 compiled Nov 29 2016 19:03:48 +gem5 started Nov 29 2016 19:04:15 +gem5 executing on zizzer, pid 5745 +command line: /z/powerjg/gem5-upstream/build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/50.vortex/arm/linux/simple-timing -re /z/powerjg/gem5-upstream/tests/testing/../run.py quick/se/50.vortex/arm/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. -Exiting @ tick 128076834500 because target called exit() +Exiting @ tick 128204299500 because target called exit() diff --git a/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/stats.txt b/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/stats.txt index ae3fac096..8b755992a 100644 --- a/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/stats.txt +++ b/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/stats.txt @@ -1,19 +1,19 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.128202 # Number of seconds simulated -sim_ticks 128202163500 # Number of ticks simulated -final_tick 128202163500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.128204 # Number of seconds simulated +sim_ticks 128204299500 # Number of ticks simulated +final_tick 128204299500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1220543 # Simulator instruction rate (inst/s) -host_op_rate 1558290 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2223504943 # Simulator tick rate (ticks/s) -host_mem_usage 279580 # Number of bytes of host memory used -host_seconds 57.66 # Real time elapsed on the host +host_inst_rate 442445 # Simulator instruction rate (inst/s) +host_op_rate 564877 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 806030069 # Simulator tick rate (ticks/s) +host_mem_usage 262052 # Number of bytes of host memory used +host_seconds 159.06 # Real time elapsed on the host sim_insts 70373651 # Number of instructions simulated sim_ops 89847385 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 128202163500 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 128204299500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 233344 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 7939200 # Number of bytes read from this memory system.physmem.bytes_read::total 8172544 # Number of bytes read from this memory @@ -26,20 +26,20 @@ system.physmem.num_reads::cpu.data 124050 # Nu system.physmem.num_reads::total 127696 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 86477 # Number of write requests responded to by this memory system.physmem.num_writes::total 86477 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 1820125 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 61927192 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 63747317 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1820125 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1820125 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 43170317 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 43170317 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 43170317 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1820125 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 61927192 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 106917634 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 128202163500 # Cumulative time (in ticks) in various power states +system.physmem.bw_read::cpu.inst 1820095 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 61926160 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 63746255 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1820095 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1820095 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 43169597 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 43169597 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 43169597 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1820095 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 61926160 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 106915853 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 128204299500 # Cumulative time (in ticks) in various power states system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 128202163500 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 128204299500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -69,7 +69,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 128202163500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 128204299500 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -99,7 +99,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 128202163500 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 128204299500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -129,7 +129,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 128202163500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 128204299500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -160,8 +160,8 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1946 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 128202163500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 256404327 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 128204299500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 256408599 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 70373651 # Number of instructions committed @@ -182,7 +182,7 @@ system.cpu.num_mem_refs 43422001 # nu system.cpu.num_load_insts 22866262 # Number of load instructions system.cpu.num_store_insts 20555739 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 256404326.998000 # Number of busy cycles +system.cpu.num_busy_cycles 256408598.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 13741468 # Number of branches fetched @@ -225,14 +225,14 @@ system.cpu.op_class::FloatMemWrite 32 0.00% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 90690106 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 128202163500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 128204299500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 155902 # number of replacements -system.cpu.dcache.tags.tagsinuse 4075.863858 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 4075.864194 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 42601590 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 159998 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 266.263266 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 1116590500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4075.863858 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 4075.864194 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.995084 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.995084 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id @@ -242,7 +242,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::2 3277 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 85731098 # Number of tag accesses system.cpu.dcache.tags.data_accesses 85731098 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 128202163500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 128204299500 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 22743326 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 22743326 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 19742869 # number of WriteReq hits @@ -361,16 +361,16 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 50731.126047 system.cpu.dcache.demand_avg_mshr_miss_latency::total 50731.126047 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 50797.056838 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 50797.056838 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 128202163500 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 128204299500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 16890 # number of replacements -system.cpu.icache.tags.tagsinuse 1732.172375 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 1732.169683 # Cycle average of tags in use system.cpu.icache.tags.total_refs 78126184 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 18908 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 4131.911572 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1732.172375 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.845787 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.845787 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1732.169683 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.845786 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.845786 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 2018 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 22 # Occupied blocks per task id @@ -379,7 +379,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::4 1645 system.cpu.icache.tags.occ_task_id_percent::1024 0.985352 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 156309092 # Number of tag accesses system.cpu.icache.tags.data_accesses 156309092 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 128202163500 # Cumulative time (in ticks) in various power states +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 128204299500 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 78126184 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 78126184 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 78126184 # number of demand (read+write) hits @@ -448,16 +448,16 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21739.105141 system.cpu.icache.demand_avg_mshr_miss_latency::total 21739.105141 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21739.105141 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 21739.105141 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 128202163500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 128204299500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 96062 # number of replacements -system.cpu.l2cache.tags.tagsinuse 31698.820174 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 31698.825375 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 219067 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 128830 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 1.700435 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 20553705000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 380.243921 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 1041.373654 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 30277.202598 # Average occupied blocks per requestor +system.cpu.l2cache.tags.warmup_cycle 20554489000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 380.240484 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 1041.373230 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 30277.211662 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.011604 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.031780 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.923987 # Average percentage of cache occupancy @@ -471,7 +471,7 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4 800 system.cpu.l2cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 2912846 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 2912846 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 128202163500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 128204299500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackDirty_hits::writebacks 127926 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 127926 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 15790 # number of WritebackClean hits @@ -618,7 +618,7 @@ system.cpu.toL2Bus.snoop_filter.hit_multi_requests 3696 system.cpu.toL2Bus.snoop_filter.tot_snoops 3224 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3194 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 30 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 128202163500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 128204299500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 71874 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 214403 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 16890 # Transaction distribution @@ -658,7 +658,7 @@ system.membus.snoop_filter.hit_multi_requests 0 system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 128202163500 # Cumulative time (in ticks) in various power states +system.membus.pwrStateResidencyTicks::UNDEFINED 128204299500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 25376 # Transaction distribution system.membus.trans_dist::WritebackDirty 86477 # Transaction distribution system.membus.trans_dist::CleanEvict 6466 # Transaction distribution |