diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2013-06-27 05:49:51 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2013-06-27 05:49:51 -0400 |
| commit | 5a15909bac241dc795c691d49c4e2c68cab745f4 (patch) | |
| tree | d0ae694e320c725ed8116943c7179516567279f3 /tests/quick/se | |
| parent | ac515d7a9b131ffc9e128bd209fcddb2f383808b (diff) | |
| download | gem5-5a15909bac241dc795c691d49c4e2c68cab745f4.tar.xz | |
stats: Update stats for monitor, cache and bus changes
This patch removes the sparse histogram total from the CommMonitor
stats. It also bumps the stats after the unit fixes in the atomic
cache access. Lastly, it updates the stats to match the new port
ordering. All numbers are the same, and the only thing that changes is
which master corresponds to what port index.
Diffstat (limited to 'tests/quick/se')
29 files changed, 9546 insertions, 9551 deletions
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt index 35c6d79b2..9728f1e09 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000025 # Number of seconds simulated -sim_ticks 24560000 # Number of ticks simulated -final_tick 24560000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 25046000 # Number of ticks simulated +final_tick 25046000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1785 # Simulator instruction rate (inst/s) -host_op_rate 1785 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 6860090 # Simulator tick rate (ticks/s) -host_mem_usage 225432 # Number of bytes of host memory used -host_seconds 3.58 # Real time elapsed on the host +host_inst_rate 25238 # Simulator instruction rate (inst/s) +host_op_rate 25236 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 98905790 # Simulator tick rate (ticks/s) +host_mem_usage 225424 # Number of bytes of host memory used +host_seconds 0.25 # Real time elapsed on the host sim_insts 6390 # Number of instructions simulated sim_ops 6390 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 19200 # Number of bytes read from this memory @@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 19200 # Nu system.physmem.num_reads::cpu.inst 300 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 168 # Number of read requests responded to by this memory system.physmem.num_reads::total 468 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 781758958 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 437785016 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1219543974 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 781758958 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 781758958 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 781758958 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 437785016 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1219543974 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 766589475 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 429290106 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1195879582 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 766589475 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 766589475 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 766589475 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 429290106 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1195879582 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 469 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen system.physmem.cpureqs 469 # Reqs generatd by CPU via cache - shady @@ -70,7 +70,7 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 24545500 # Total gap between requests +system.physmem.totGap 25031500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes @@ -85,8 +85,8 @@ system.physmem.writePktSize::3 0 # Ca system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes system.physmem.writePktSize::6 0 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 317 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 124 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 318 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 123 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 20 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 8 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -169,28 +169,28 @@ system.physmem.bytesPerActivate::1856 1 1.49% 97.01% # By system.physmem.bytesPerActivate::2368 1 1.49% 98.51% # Bytes accessed per row activation system.physmem.bytesPerActivate::2496 1 1.49% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 67 # Bytes accessed per row activation -system.physmem.totQLat 1607750 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 11529000 # Sum of mem lat for all requests +system.physmem.totQLat 1857500 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 11820000 # Sum of mem lat for all requests system.physmem.totBusLat 2345000 # Total cycles spent in databus access -system.physmem.totBankLat 7576250 # Total cycles spent in bank access -system.physmem.avgQLat 3428.04 # Average queueing delay per request -system.physmem.avgBankLat 16154.05 # Average bank access latency per request +system.physmem.totBankLat 7617500 # Total cycles spent in bank access +system.physmem.avgQLat 3960.55 # Average queueing delay per request +system.physmem.avgBankLat 16242.00 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 24582.09 # Average memory access latency -system.physmem.avgRdBW 1219.54 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 25202.56 # Average memory access latency +system.physmem.avgRdBW 1195.88 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 1219.54 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 1195.88 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 9.53 # Data bus utilization in percentage +system.physmem.busUtil 9.34 # Data bus utilization in percentage system.physmem.avgRdQLen 0.47 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time system.physmem.readRowHits 402 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 85.71 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 52335.82 # Average gap between requests -system.membus.throughput 1219543974 # Throughput (bytes/s) +system.physmem.avgGap 53372.07 # Average gap between requests +system.membus.throughput 1195879582 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 396 # Transaction distribution system.membus.trans_dist::ReadResp 395 # Transaction distribution system.membus.trans_dist::ReadExReq 73 # Transaction distribution @@ -201,10 +201,10 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 29952 system.membus.tot_pkt_size 29952 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 29952 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 563500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 2.3 # Layer utilization (%) -system.membus.respLayer1.occupancy 4381500 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 17.8 # Layer utilization (%) +system.membus.reqLayer0.occupancy 559000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 2.2 # Layer utilization (%) +system.membus.respLayer1.occupancy 4378000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 17.5 # Layer utilization (%) system.cpu.branchPred.lookups 1632 # Number of BP lookups system.cpu.branchPred.condPredicted 1160 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 706 # Number of conditional branches incorrect @@ -247,7 +247,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 49121 # number of cpu cycles simulated +system.cpu.numCycles 50093 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.branch_predictor.predictedTaken 502 # Number of Branches Predicted As Taken (True). @@ -269,12 +269,12 @@ system.cpu.execution_unit.executions 4448 # Nu system.cpu.mult_div_unit.multiplies 1 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 11658 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 11606 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 510 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 41745 # Number of cycles cpu's stages were not processed +system.cpu.timesIdled 460 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 42717 # Number of cycles cpu's stages were not processed system.cpu.runCycles 7376 # Number of cycles cpu stages are processed. -system.cpu.activity 15.015981 # Percentage of cycles cpu is active +system.cpu.activity 14.724612 # Percentage of cycles cpu is active system.cpu.comLoads 1183 # Number of Load instructions committed system.cpu.comStores 865 # Number of Store instructions committed system.cpu.comBranches 1050 # Number of Branches instructions committed @@ -286,36 +286,36 @@ system.cpu.committedInsts 6390 # Nu system.cpu.committedOps 6390 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 6390 # Number of Instructions committed (Total) -system.cpu.cpi 7.687167 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 7.839280 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 7.687167 # CPI: Total CPI of All Threads -system.cpu.ipc 0.130087 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 7.839280 # CPI: Total CPI of All Threads +system.cpu.ipc 0.127563 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 0.130087 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 44197 # Number of cycles 0 instructions are processed. +system.cpu.ipc_total 0.127563 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 45169 # Number of cycles 0 instructions are processed. system.cpu.stage0.runCycles 4924 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 10.024226 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 45228 # Number of cycles 0 instructions are processed. +system.cpu.stage0.utilization 9.829717 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 46200 # Number of cycles 0 instructions are processed. system.cpu.stage1.runCycles 3893 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 7.925327 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 44960 # Number of cycles 0 instructions are processed. +system.cpu.stage1.utilization 7.771545 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 45932 # Number of cycles 0 instructions are processed. system.cpu.stage2.runCycles 4161 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 8.470919 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 47787 # Number of cycles 0 instructions are processed. +system.cpu.stage2.utilization 8.306550 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 48759 # Number of cycles 0 instructions are processed. system.cpu.stage3.runCycles 1334 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 2.715743 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 44663 # Number of cycles 0 instructions are processed. +system.cpu.stage3.utilization 2.663047 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 45635 # Number of cycles 0 instructions are processed. system.cpu.stage4.runCycles 4458 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 9.075548 # Percentage of cycles stage was utilized (processing insts). -system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 140.779037 # Cycle average of tags in use -system.cpu.icache.total_refs 560 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 301 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 1.860465 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 140.779037 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.068740 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.068740 # Average percentage of cache occupancy +system.cpu.stage4.utilization 8.899447 # Percentage of cycles stage was utilized (processing insts). +system.cpu.icache.tags.replacements 0 # number of replacements +system.cpu.icache.tags.tagsinuse 141.294375 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 560 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 301 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 1.860465 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 141.294375 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.068991 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.068991 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 560 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 560 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 560 # number of demand (read+write) hits @@ -328,12 +328,12 @@ system.cpu.icache.demand_misses::cpu.inst 355 # n system.cpu.icache.demand_misses::total 355 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 355 # number of overall misses system.cpu.icache.overall_misses::total 355 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 24103000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 24103000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 24103000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 24103000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 24103000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 24103000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 24600000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 24600000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 24600000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 24600000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 24600000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 24600000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 915 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 915 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 915 # number of demand (read+write) accesses @@ -346,17 +346,17 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.387978 system.cpu.icache.demand_miss_rate::total 0.387978 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.387978 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.387978 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 67895.774648 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 67895.774648 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 67895.774648 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 67895.774648 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 67895.774648 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 67895.774648 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 88 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69295.774648 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 69295.774648 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 69295.774648 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 69295.774648 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 69295.774648 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 69295.774648 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 89 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 88 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 89 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed @@ -372,26 +372,26 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 302 system.cpu.icache.demand_mshr_misses::total 302 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 302 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 302 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 20462500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 20462500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 20462500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 20462500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 20462500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 20462500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 20800250 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 20800250 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 20800250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 20800250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 20800250 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 20800250 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.330055 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.330055 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.330055 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.330055 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.330055 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.330055 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 67756.622517 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 67756.622517 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 67756.622517 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 67756.622517 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 67756.622517 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 67756.622517 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 68875 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 68875 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 68875 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 68875 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 68875 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 68875 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 1222149837 # Throughput (bytes/s) +system.cpu.toL2Bus.throughput 1198434880 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 397 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 396 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 73 # Transaction distribution @@ -405,22 +405,22 @@ system.cpu.toL2Bus.tot_pkt_size 30016 # Cu system.cpu.toL2Bus.data_through_bus 30016 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 235000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 1.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 451500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 1.8 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 252000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%) -system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 197.103662 # Cycle average of tags in use -system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 395 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.002532 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 140.828803 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 56.274859 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.004298 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.001717 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.006015 # Average percentage of cache occupancy +system.cpu.toL2Bus.reqLayer0.utilization 0.9 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 512750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 2.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 278750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 1.1 # Layer utilization (%) +system.cpu.l2cache.tags.replacements 0 # number of replacements +system.cpu.l2cache.tags.tagsinuse 197.784355 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 395 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.002532 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::cpu.inst 141.343624 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 56.440731 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004313 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.001722 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.006036 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits @@ -438,17 +438,17 @@ system.cpu.l2cache.demand_misses::total 469 # nu system.cpu.l2cache.overall_misses::cpu.inst 301 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 168 # number of overall misses system.cpu.l2cache.overall_misses::total 469 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 20144000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 6932500 # 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number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 27443250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4890250 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 4890250 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 20481750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 11851750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 32333500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 20481750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 11851750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 32333500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 302 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 95 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 397 # number of ReadReq accesses(hits+misses) @@ -471,17 +471,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.997872 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996689 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.997872 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 66923.588040 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 72973.684211 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 68375 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 66815.068493 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 66815.068493 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66923.588040 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70297.619048 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 68132.196162 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66923.588040 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70297.619048 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 68132.196162 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68045.681063 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 73278.947368 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 69301.136364 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 66989.726027 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 66989.726027 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68045.681063 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70546.130952 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 68941.364606 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68045.681063 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70546.130952 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 68941.364606 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -501,17 +501,17 @@ system.cpu.l2cache.demand_mshr_misses::total 469 system.cpu.l2cache.overall_mshr_misses::cpu.inst 301 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 469 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 16417750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 5764000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 22181750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 16699250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 5777500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 22476750 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3986750 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3986750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 16417750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9750750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 26168500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 16417750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9750750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 26168500 # number of overall MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 16699250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9764250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 26463500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 16699250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9764250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 26463500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996689 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997481 # mshr miss rate for ReadReq accesses @@ -523,27 +523,27 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.997872 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996689 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.997872 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 54544.019934 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60673.684211 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56014.520202 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55479.235880 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60815.789474 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56759.469697 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 54613.013699 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54613.013699 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54544.019934 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 58040.178571 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55796.375267 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54544.019934 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 58040.178571 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55796.375267 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55479.235880 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 58120.535714 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56425.373134 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55479.235880 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 58120.535714 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56425.373134 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 102.747723 # Cycle average of tags in use -system.cpu.dcache.total_refs 1601 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 168 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 9.529762 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 102.747723 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.025085 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.025085 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 0 # number of replacements +system.cpu.dcache.tags.tagsinuse 103.103023 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 1601 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 168 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 9.529762 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 103.103023 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.025172 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.025172 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 1086 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1086 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 515 # number of WriteReq hits @@ -560,14 +560,14 @@ system.cpu.dcache.demand_misses::cpu.data 447 # n system.cpu.dcache.demand_misses::total 447 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 447 # number of overall misses system.cpu.dcache.overall_misses::total 447 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 7336500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 7336500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 21108000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 21108000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 28444500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 28444500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 28444500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 28444500 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 7410000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 7410000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 21312750 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 21312750 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 28722750 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 28722750 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 28722750 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 28722750 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 1183 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1183 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses) @@ -584,19 +584,19 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.218262 system.cpu.dcache.demand_miss_rate::total 0.218262 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.218262 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.218262 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 75634.020619 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 75634.020619 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60308.571429 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 60308.571429 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 63634.228188 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 63634.228188 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 63634.228188 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 63634.228188 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 467 # number of cycles access was blocked +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 76391.752577 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 76391.752577 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60893.571429 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 60893.571429 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 64256.711409 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 64256.711409 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 64256.711409 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 64256.711409 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 496 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 30 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 15.566667 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 16.533333 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed @@ -616,14 +616,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 168 system.cpu.dcache.demand_mshr_misses::total 168 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 168 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7034000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 7034000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4955000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4955000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11989000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 11989000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11989000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 11989000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7063000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 7063000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4967750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4967750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12030750 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 12030750 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12030750 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 12030750 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.080304 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.080304 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses @@ -632,14 +632,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.082031 system.cpu.dcache.demand_mshr_miss_rate::total 0.082031 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.082031 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.082031 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 74042.105263 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 74042.105263 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 67876.712329 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 67876.712329 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 71363.095238 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 71363.095238 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 71363.095238 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 71363.095238 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 74347.368421 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 74347.368421 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 68051.369863 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 68051.369863 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 71611.607143 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 71611.607143 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 71611.607143 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 71611.607143 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt index 9e4861fce..38483afa5 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000021 # Number of seconds simulated -sim_ticks 20632000 # Number of ticks simulated -final_tick 20632000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 20671000 # Number of ticks simulated +final_tick 20671000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1782 # Simulator instruction rate (inst/s) -host_op_rate 1782 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5769044 # Simulator tick rate (ticks/s) -host_mem_usage 227476 # Number of bytes of host memory used -host_seconds 3.58 # Real time elapsed on the host +host_inst_rate 25591 # Simulator instruction rate (inst/s) +host_op_rate 25589 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 83008053 # Simulator tick rate (ticks/s) +host_mem_usage 227468 # Number of bytes of host memory used +host_seconds 0.25 # Real time elapsed on the host sim_insts 6372 # Number of instructions simulated sim_ops 6372 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 20032 # Number of bytes read from this memory @@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 20032 # Nu system.physmem.num_reads::cpu.inst 313 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 174 # Number of read requests responded to by this memory system.physmem.num_reads::total 487 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 970918961 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 539744087 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1510663048 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 970918961 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 970918961 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 970918961 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 539744087 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1510663048 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 969087127 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 538725751 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1507812878 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 969087127 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 969087127 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 969087127 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 538725751 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1507812878 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 488 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen system.physmem.cpureqs 488 # Reqs generatd by CPU via cache - shady @@ -70,7 +70,7 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 20599000 # Total gap between requests +system.physmem.totGap 20638000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes @@ -85,8 +85,8 @@ system.physmem.writePktSize::3 0 # Ca system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes system.physmem.writePktSize::6 0 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 285 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 139 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 286 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 138 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 46 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 13 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see @@ -168,28 +168,28 @@ system.physmem.bytesPerActivate::1920 1 1.45% 97.10% # By system.physmem.bytesPerActivate::2496 1 1.45% 98.55% # Bytes accessed per row activation system.physmem.bytesPerActivate::2880 1 1.45% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 69 # Bytes accessed per row activation -system.physmem.totQLat 2633750 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 12636250 # Sum of mem lat for all requests +system.physmem.totQLat 2449250 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 12424250 # Sum of mem lat for all requests system.physmem.totBusLat 2440000 # Total cycles spent in databus access -system.physmem.totBankLat 7562500 # Total cycles spent in bank access -system.physmem.avgQLat 5397.03 # Average queueing delay per request -system.physmem.avgBankLat 15496.93 # Average bank access latency per request +system.physmem.totBankLat 7535000 # Total cycles spent in bank access +system.physmem.avgQLat 5018.95 # Average queueing delay per request +system.physmem.avgBankLat 15440.57 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 25893.95 # Average memory access latency -system.physmem.avgRdBW 1510.66 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 25459.53 # Average memory access latency +system.physmem.avgRdBW 1507.81 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 1510.66 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 1507.81 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 11.80 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.61 # Average read queue length over time +system.physmem.busUtil 11.78 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.60 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time system.physmem.readRowHits 419 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 85.86 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 42211.07 # Average gap between requests -system.membus.throughput 1510663048 # Throughput (bytes/s) +system.physmem.avgGap 42290.98 # Average gap between requests +system.membus.throughput 1507812878 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 415 # Transaction distribution system.membus.trans_dist::ReadResp 414 # Transaction distribution system.membus.trans_dist::ReadExReq 73 # Transaction distribution @@ -200,39 +200,39 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 31168 system.membus.tot_pkt_size 31168 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 31168 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 600000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 2.9 # Layer utilization (%) -system.membus.respLayer1.occupancy 4550500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 619500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 3.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 4561500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 22.1 # Layer utilization (%) -system.cpu.branchPred.lookups 2906 # Number of BP lookups -system.cpu.branchPred.condPredicted 1709 # Number of conditional branches predicted +system.cpu.branchPred.lookups 2888 # Number of BP lookups +system.cpu.branchPred.condPredicted 1700 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 511 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 2211 # Number of BTB lookups -system.cpu.branchPred.BTBHits 759 # Number of BTB hits +system.cpu.branchPred.BTBLookups 2201 # Number of BTB lookups +system.cpu.branchPred.BTBHits 757 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 34.328358 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 420 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 34.393458 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 418 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 74 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 2097 # DTB read hits +system.cpu.dtb.read_hits 2082 # DTB read hits system.cpu.dtb.read_misses 47 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 2144 # DTB read accesses +system.cpu.dtb.read_accesses 2129 # DTB read accesses system.cpu.dtb.write_hits 1063 # DTB write hits system.cpu.dtb.write_misses 31 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations system.cpu.dtb.write_accesses 1094 # DTB write accesses -system.cpu.dtb.data_hits 3160 # DTB hits +system.cpu.dtb.data_hits 3145 # DTB hits system.cpu.dtb.data_misses 78 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 3238 # DTB accesses -system.cpu.itb.fetch_hits 2393 # ITB hits +system.cpu.dtb.data_accesses 3223 # DTB accesses +system.cpu.itb.fetch_hits 2387 # ITB hits system.cpu.itb.fetch_misses 39 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 2432 # ITB accesses +system.cpu.itb.fetch_accesses 2426 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -246,237 +246,237 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 41265 # number of cpu cycles simulated +system.cpu.numCycles 41343 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 8511 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 16675 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2906 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 1179 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 2982 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1908 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 1525 # Number of cycles fetch has spent blocked +system.cpu.fetch.icacheStallCycles 8507 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 16592 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2888 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 1175 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 2970 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1903 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 1523 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 25 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 759 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 2393 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 379 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 15107 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.103793 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.501598 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.PendingTrapStallCycles 747 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 2387 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 382 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 15073 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.100776 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.497742 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 12125 80.26% 80.26% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 320 2.12% 82.38% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 234 1.55% 83.93% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 215 1.42% 85.35% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 256 1.69% 87.05% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 241 1.60% 88.64% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 264 1.75% 90.39% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 187 1.24% 91.63% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1265 8.37% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 12103 80.30% 80.30% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 318 2.11% 82.41% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 234 1.55% 83.96% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 215 1.43% 85.38% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 257 1.71% 87.09% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 241 1.60% 88.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 264 1.75% 90.44% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 184 1.22% 91.66% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1257 8.34% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 15107 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.070423 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.404095 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 9355 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 1672 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2793 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 63 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1224 # Number of cycles decode is squashing +system.cpu.fetch.rateDist::total 15073 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.069855 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.401325 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 9323 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 1686 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 2770 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 74 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1220 # Number of cycles decode is squashing system.cpu.decode.BranchResolved 242 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 85 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 15419 # Number of instructions handled by decode +system.cpu.decode.DecodedInsts 15336 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 223 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1224 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 9566 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 693 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 555 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2621 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 448 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 14692 # Number of instructions processed by rename +system.cpu.rename.SquashCycles 1220 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 9534 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 784 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 553 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 2627 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 355 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 14625 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 10 # Number of times rename has blocked due to ROB full system.cpu.rename.IQFullEvents 5 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 388 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 11020 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 18321 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 18304 # Number of integer rename lookups +system.cpu.rename.LSQFullEvents 313 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 10969 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 18250 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 18233 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 17 # Number of floating rename lookups system.cpu.rename.CommittedMaps 4570 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 6450 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 30 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 24 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 976 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2777 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1360 # Number of stores inserted to the mem dependence unit. +system.cpu.rename.UndoneMaps 6399 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 29 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 23 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 808 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2769 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1356 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 3 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 12985 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 30 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 10814 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 53 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 6280 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 3603 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 13 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 15107 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.715827 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.359683 # Number of insts issued each cycle +system.cpu.iq.iqInstsAdded 12962 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 29 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 10787 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 54 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 6234 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 3590 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 12 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 15073 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.715651 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.357561 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 10552 69.85% 69.85% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1715 11.35% 81.20% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 1107 7.33% 88.53% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 773 5.12% 93.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 494 3.27% 96.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 269 1.78% 98.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 148 0.98% 99.68% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 35 0.23% 99.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 10531 69.87% 69.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1674 11.11% 80.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 1174 7.79% 88.76% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 731 4.85% 93.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 498 3.30% 96.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 271 1.80% 98.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 147 0.98% 99.69% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 33 0.22% 99.91% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 14 0.09% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 15107 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 15073 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 14 12.61% 12.61% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 12.61% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 12.61% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 12.61% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 12.61% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 12.61% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 12.61% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 12.61% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 12.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 12.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 12.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 12.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 12.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 12.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 12.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 12.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 12.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 12.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 12.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 12.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 12.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 12.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 12.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 12.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 12.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 12.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 12.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 12.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 12.61% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 59 53.15% 65.77% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 38 34.23% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 15 13.27% 13.27% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 13.27% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 13.27% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 13.27% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 13.27% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 13.27% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 13.27% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 13.27% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 13.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 13.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 13.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 13.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 13.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 13.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 13.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 13.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 13.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 13.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 13.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 13.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 13.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 13.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 13.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 13.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 13.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 13.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 13.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 13.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 13.27% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 60 53.10% 66.37% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 38 33.63% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 7260 67.14% 67.15% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 1 0.01% 67.16% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.16% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 67.18% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.18% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.18% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.18% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.18% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.18% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2415 22.33% 89.51% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1134 10.49% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 7249 67.20% 67.22% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 1 0.01% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 67.25% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.25% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.25% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.25% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.25% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.25% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2400 22.25% 89.50% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1133 10.50% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 10814 # Type of FU issued -system.cpu.iq.rate 0.262062 # Inst issue rate -system.cpu.iq.fu_busy_cnt 111 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.010264 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 36878 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 19300 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 9631 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 10787 # Type of FU issued +system.cpu.iq.rate 0.260915 # Inst issue rate +system.cpu.iq.fu_busy_cnt 113 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.010476 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 36793 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 19230 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 9615 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 21 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 10 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 10 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 10912 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 10887 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 11 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 73 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1594 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1586 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 17 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 495 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 491 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 136 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 131 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1224 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 218 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 10 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 13104 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 177 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2777 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1360 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 30 # Number of dispatched non-speculative instructions +system.cpu.iew.iewSquashCycles 1220 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 240 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 22 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 13080 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 175 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2769 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1356 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 29 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 2 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 17 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 124 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 385 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 509 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 10116 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 2155 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 698 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedTakenIncorrect 123 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 382 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 505 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 10087 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 2140 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 700 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 89 # number of nop insts executed -system.cpu.iew.exec_refs 3251 # number of memory reference insts executed -system.cpu.iew.exec_branches 1595 # Number of branches executed +system.cpu.iew.exec_refs 3236 # number of memory reference insts executed +system.cpu.iew.exec_branches 1591 # Number of branches executed system.cpu.iew.exec_stores 1096 # Number of stores executed -system.cpu.iew.exec_rate 0.245147 # Inst execution rate -system.cpu.iew.wb_sent 9787 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 9641 # cumulative count of insts written-back -system.cpu.iew.wb_producers 5053 # num instructions producing a value -system.cpu.iew.wb_consumers 6805 # num instructions consuming a value +system.cpu.iew.exec_rate 0.243983 # Inst execution rate +system.cpu.iew.wb_sent 9767 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 9625 # cumulative count of insts written-back +system.cpu.iew.wb_producers 5058 # num instructions producing a value +system.cpu.iew.wb_consumers 6775 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.233636 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.742542 # average fanout of values written-back +system.cpu.iew.wb_rate 0.232808 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.746568 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 6713 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 6689 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 430 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 13883 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.460203 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.266435 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 13853 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.461200 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.266599 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 11056 79.64% 79.64% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1544 11.12% 90.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 511 3.68% 94.44% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 249 1.79% 96.23% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 151 1.09% 97.32% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 81 0.58% 97.90% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 113 0.81% 98.72% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 35 0.25% 98.97% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 143 1.03% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 11035 79.66% 79.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1522 10.99% 90.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 530 3.83% 94.47% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 235 1.70% 96.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 147 1.06% 97.23% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 108 0.78% 98.01% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 103 0.74% 98.75% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 28 0.20% 98.95% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 145 1.05% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 13883 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 13853 # Number of insts commited each cycle system.cpu.commit.committedInsts 6389 # Number of instructions committed system.cpu.commit.committedOps 6389 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -487,26 +487,26 @@ system.cpu.commit.branches 1050 # Nu system.cpu.commit.fp_insts 10 # Number of committed floating point instructions. system.cpu.commit.int_insts 6307 # Number of committed integer instructions. system.cpu.commit.function_calls 127 # Number of function calls committed. -system.cpu.commit.bw_lim_events 143 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 145 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 26491 # The number of ROB reads -system.cpu.rob.rob_writes 27437 # The number of ROB writes -system.cpu.timesIdled 274 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 26158 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 26435 # The number of ROB reads +system.cpu.rob.rob_writes 27385 # The number of ROB writes +system.cpu.timesIdled 269 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 26270 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 6372 # Number of Instructions Simulated system.cpu.committedOps 6372 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 6372 # Number of Instructions Simulated -system.cpu.cpi 6.475989 # CPI: Cycles Per Instruction -system.cpu.cpi_total 6.475989 # CPI: Total CPI of All Threads -system.cpu.ipc 0.154417 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.154417 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 12831 # number of integer regfile reads -system.cpu.int_regfile_writes 7294 # number of integer regfile writes +system.cpu.cpi 6.488230 # CPI: Cycles Per Instruction +system.cpu.cpi_total 6.488230 # CPI: Total CPI of All Threads +system.cpu.ipc 0.154125 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.154125 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 12801 # number of integer regfile reads +system.cpu.int_regfile_writes 7277 # number of integer regfile writes system.cpu.fp_regfile_reads 8 # number of floating regfile reads system.cpu.fp_regfile_writes 2 # number of floating regfile writes system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.toL2Bus.throughput 1513765025 # Throughput (bytes/s) +system.cpu.toL2Bus.throughput 1510909003 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 416 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 415 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 73 # Transaction distribution @@ -521,55 +521,55 @@ system.cpu.toL2Bus.data_through_bus 31232 # To system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 244500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 471000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 2.3 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 261000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 1.3 # Layer utilization (%) -system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 159.617277 # Cycle average of tags in use -system.cpu.icache.total_refs 1903 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 314 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 6.060510 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 159.617277 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.077938 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.077938 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 1903 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1903 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1903 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1903 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1903 # number of overall hits -system.cpu.icache.overall_hits::total 1903 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 490 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 490 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 490 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 490 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 490 # number of overall misses -system.cpu.icache.overall_misses::total 490 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 30064500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 30064500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 30064500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 30064500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 30064500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 30064500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 2393 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 2393 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 2393 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 2393 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 2393 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 2393 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.204764 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.204764 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.204764 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.204764 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.204764 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.204764 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61356.122449 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 61356.122449 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 61356.122449 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 61356.122449 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 61356.122449 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 61356.122449 # average overall miss latency +system.cpu.toL2Bus.respLayer0.occupancy 531250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 2.6 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 281250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 1.4 # Layer utilization (%) +system.cpu.icache.tags.replacements 0 # number of replacements +system.cpu.icache.tags.tagsinuse 159.268512 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 1898 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 314 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 6.044586 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 159.268512 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.077768 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.077768 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 1898 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1898 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1898 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1898 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1898 # number of overall hits +system.cpu.icache.overall_hits::total 1898 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 489 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 489 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 489 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 489 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 489 # number of overall misses +system.cpu.icache.overall_misses::total 489 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 30301750 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 30301750 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 30301750 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 30301750 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 30301750 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 30301750 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 2387 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 2387 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 2387 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 2387 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 2387 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 2387 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.204860 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.204860 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.204860 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.204860 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.204860 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.204860 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61966.768916 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 61966.768916 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 61966.768916 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 61966.768916 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 61966.768916 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 61966.768916 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -578,48 +578,48 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 175 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 175 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 175 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 175 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 175 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 175 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 174 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 174 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 174 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 174 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 174 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 174 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 315 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 315 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 315 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 315 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 315 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 315 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 21382000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 21382000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 21382000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 21382000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 21382000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 21382000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.131634 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.131634 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.131634 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.131634 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.131634 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.131634 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 67879.365079 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 67879.365079 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 67879.365079 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 67879.365079 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 67879.365079 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 67879.365079 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 21363250 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 21363250 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 21363250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 21363250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 21363250 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 21363250 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.131965 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.131965 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.131965 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.131965 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.131965 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.131965 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 67819.841270 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 67819.841270 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 67819.841270 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 67819.841270 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 67819.841270 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 67819.841270 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 219.419406 # Cycle average of tags in use -system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 414 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.002415 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 159.699673 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 59.719733 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.004874 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.001823 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.006696 # Average percentage of cache occupancy +system.cpu.l2cache.tags.replacements 0 # number of replacements +system.cpu.l2cache.tags.tagsinuse 218.982908 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 414 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.002415 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::cpu.inst 159.353389 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 59.629519 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004863 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.001820 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.006683 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits @@ -637,17 +637,17 @@ system.cpu.l2cache.demand_misses::total 488 # nu system.cpu.l2cache.overall_misses::cpu.inst 314 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 174 # number of overall misses system.cpu.l2cache.overall_misses::total 488 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 21056000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 8037000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 29093000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5106500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 5106500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 21056000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 13143500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 34199500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 21056000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 13143500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 34199500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 21037250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 7945250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 28982500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5109500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 5109500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 21037250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 13054750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 34092000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 21037250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 13054750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 34092000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 315 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 101 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 416 # number of ReadReq accesses(hits+misses) @@ -670,17 +670,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.997955 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996825 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.997955 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67057.324841 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 79574.257426 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 70103.614458 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 69952.054795 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69952.054795 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67057.324841 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75537.356322 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 70080.942623 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67057.324841 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75537.356322 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 70080.942623 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 66997.611465 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 78665.841584 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 69837.349398 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 69993.150685 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69993.150685 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66997.611465 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75027.298851 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 69860.655738 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66997.611465 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75027.298851 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 69860.655738 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -700,17 +700,17 @@ system.cpu.l2cache.demand_mshr_misses::total 488 system.cpu.l2cache.overall_mshr_misses::cpu.inst 314 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 174 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 488 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 17174500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 6801500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 23976000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4212000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4212000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 17174500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11013500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 28188000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 17174500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11013500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 28188000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 17080250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 6700750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 23781000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4208000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4208000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 17080250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10908750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 27989000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 17080250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10908750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 27989000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996825 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997596 # mshr miss rate for ReadReq accesses @@ -722,35 +722,35 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.997955 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996825 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.997955 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 54695.859873 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 67341.584158 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57773.493976 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 57698.630137 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57698.630137 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54695.859873 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63295.977011 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57762.295082 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54695.859873 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63295.977011 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57762.295082 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 54395.700637 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 66344.059406 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57303.614458 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 57643.835616 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57643.835616 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54395.700637 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62693.965517 # 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Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 1730 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1730 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 506 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 506 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 2246 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2246 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2246 # number of overall hits -system.cpu.dcache.overall_hits::total 2246 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 2236 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2236 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2236 # number of overall hits +system.cpu.dcache.overall_hits::total 2236 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 170 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 170 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 359 # number of WriteReq misses @@ -759,43 +759,43 @@ system.cpu.dcache.demand_misses::cpu.data 529 # n system.cpu.dcache.demand_misses::total 529 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 529 # number of overall misses system.cpu.dcache.overall_misses::total 529 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 11698500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 11698500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 21723478 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 21723478 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 33421978 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 33421978 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 33421978 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 33421978 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1910 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1910 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_miss_latency::cpu.data 11600250 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 11600250 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 21979228 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 21979228 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 33579478 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 33579478 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 33579478 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 33579478 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1900 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1900 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2775 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2775 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2775 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2775 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.089005 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.089005 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 2765 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2765 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2765 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2765 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.089474 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.089474 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.415029 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.415029 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.190631 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.190631 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.190631 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.190631 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 68814.705882 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 68814.705882 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60511.080780 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 60511.080780 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 63179.542533 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 63179.542533 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 63179.542533 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 63179.542533 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 1568 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.191320 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.191320 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.191320 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.191320 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 68236.764706 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 68236.764706 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61223.476323 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 61223.476323 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 63477.274102 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 63477.274102 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 63477.274102 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 63477.274102 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 1567 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 33 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 47.515152 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 47.484848 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed @@ -815,30 +815,30 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 174 system.cpu.dcache.demand_mshr_misses::total 174 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 174 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 174 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 8145500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 8145500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5182500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5182500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13328000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 13328000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13328000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 13328000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.052880 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.052880 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 8053750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 8053750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5185500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5185500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13239250 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 13239250 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13239250 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 13239250 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.053158 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.053158 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.062703 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.062703 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.062703 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.062703 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 80648.514851 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 80648.514851 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 70993.150685 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 70993.150685 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76597.701149 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 76597.701149 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76597.701149 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 76597.701149 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.062929 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.062929 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.062929 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.062929 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 79740.099010 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 79740.099010 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71034.246575 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71034.246575 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76087.643678 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 76087.643678 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76087.643678 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 76087.643678 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt index ece7545ec..2ce4c669d 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt @@ -97,15 +97,15 @@ system.cpu.num_idle_cycles 0 # Nu system.cpu.num_busy_cycles 65088 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 127.998991 # Cycle average of tags in use -system.cpu.icache.total_refs 6122 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 279 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 21.942652 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 127.998991 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.062500 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.062500 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 0 # number of replacements +system.cpu.icache.tags.tagsinuse 127.998991 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 6122 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 279 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 21.942652 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 127.998991 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.062500 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.062500 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 6122 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 6122 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 6122 # number of demand (read+write) hits @@ -175,17 +175,17 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 52849.462366 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52849.462366 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 52849.462366 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 184.497210 # Cycle average of tags in use -system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 373 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.002681 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 128.017765 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 56.479444 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.003907 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.001724 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.005630 # Average percentage of cache occupancy +system.cpu.l2cache.tags.replacements 0 # number of replacements +system.cpu.l2cache.tags.tagsinuse 184.497210 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 373 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.002681 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::cpu.inst 128.017765 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 56.479444 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003907 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.001724 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.005630 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits @@ -300,15 +300,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 103.762109 # Cycle average of tags in use -system.cpu.dcache.total_refs 1880 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 168 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 11.190476 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 103.762109 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.025333 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.025333 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 0 # number of replacements +system.cpu.dcache.tags.tagsinuse 103.762109 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 1880 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 168 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 11.190476 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 103.762109 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.025333 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.025333 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 1088 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1088 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 792 # number of WriteReq hits diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt index efc4a5915..07e82d1ad 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt @@ -1,38 +1,38 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000012 # Number of seconds simulated -sim_ticks 11848000 # Number of ticks simulated -final_tick 11848000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 11933500 # Number of ticks simulated +final_tick 11933500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 800 # Simulator instruction rate (inst/s) -host_op_rate 800 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3968846 # Simulator tick rate (ticks/s) -host_mem_usage 226160 # Number of bytes of host memory used -host_seconds 2.99 # Real time elapsed on the host +host_inst_rate 492 # Simulator instruction rate (inst/s) +host_op_rate 492 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2461163 # Simulator tick rate (ticks/s) +host_mem_usage 226156 # Number of bytes of host memory used +host_seconds 4.85 # Real time elapsed on the host sim_insts 2387 # Number of instructions simulated sim_ops 2387 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 11968 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 12032 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 5440 # Number of bytes read from this memory -system.physmem.bytes_read::total 17408 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 11968 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 11968 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 187 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 17472 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 12032 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 12032 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 188 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 85 # Number of read requests responded to by this memory -system.physmem.num_reads::total 272 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1010128292 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 459149223 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1469277515 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1010128292 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1010128292 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1010128292 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 459149223 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1469277515 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 272 # Total number of read requests seen +system.physmem.num_reads::total 273 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1008254075 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 455859555 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1464113630 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1008254075 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1008254075 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1008254075 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 455859555 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1464113630 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 273 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen -system.physmem.cpureqs 272 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 17408 # Total number of bytes read from memory +system.physmem.cpureqs 273 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 17472 # Total number of bytes read from memory system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 17408 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedRd 17472 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed @@ -44,7 +44,7 @@ system.physmem.perBankRdReqs::4 18 # Tr system.physmem.perBankRdReqs::5 0 # Track reads on a per bank basis system.physmem.perBankRdReqs::6 24 # Track reads on a per bank basis system.physmem.perBankRdReqs::7 37 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 60 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 61 # Track reads on a per bank basis system.physmem.perBankRdReqs::9 2 # Track reads on a per bank basis system.physmem.perBankRdReqs::10 14 # Track reads on a per bank basis system.physmem.perBankRdReqs::11 9 # Track reads on a per bank basis @@ -70,14 +70,14 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 11758500 # Total gap between requests +system.physmem.totGap 11844000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 272 # Categorize read packet sizes +system.physmem.readPktSize::6 273 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes @@ -85,7 +85,7 @@ system.physmem.writePktSize::3 0 # Ca system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes system.physmem.writePktSize::6 0 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 158 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 159 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 83 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 26 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 5 # What read queue length does an incoming req see @@ -164,71 +164,71 @@ system.physmem.bytesPerActivate::768 2 6.06% 93.94% # By system.physmem.bytesPerActivate::1152 1 3.03% 96.97% # Bytes accessed per row activation system.physmem.bytesPerActivate::2304 1 3.03% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 33 # Bytes accessed per row activation -system.physmem.totQLat 1380750 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 6920750 # Sum of mem lat for all requests -system.physmem.totBusLat 1360000 # Total cycles spent in databus access +system.physmem.totQLat 1190000 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 6735000 # Sum of mem lat for all requests +system.physmem.totBusLat 1365000 # Total cycles spent in databus access system.physmem.totBankLat 4180000 # Total cycles spent in bank access -system.physmem.avgQLat 5076.29 # Average queueing delay per request -system.physmem.avgBankLat 15367.65 # Average bank access latency per request +system.physmem.avgQLat 4358.97 # Average queueing delay per request +system.physmem.avgBankLat 15311.36 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 25443.93 # Average memory access latency -system.physmem.avgRdBW 1469.28 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 24670.33 # Average memory access latency +system.physmem.avgRdBW 1464.11 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 1469.28 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 1464.11 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 11.48 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.58 # Average read queue length over time +system.physmem.busUtil 11.44 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.56 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 239 # Number of row buffer hits during reads +system.physmem.readRowHits 240 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 87.87 # Row buffer hit rate for reads +system.physmem.readRowHitRate 87.91 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 43229.78 # Average gap between requests -system.membus.throughput 1469277515 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 248 # Transaction distribution -system.membus.trans_dist::ReadResp 248 # Transaction distribution +system.physmem.avgGap 43384.62 # Average gap between requests +system.membus.throughput 1464113630 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 249 # Transaction distribution +system.membus.trans_dist::ReadResp 249 # Transaction distribution system.membus.trans_dist::ReadExReq 24 # Transaction distribution system.membus.trans_dist::ReadExResp 24 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side 544 # Packet count per connected master and slave (bytes) -system.membus.pkt_count 544 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 17408 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size 17408 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 17408 # Total data (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side 546 # Packet count per connected master and slave (bytes) +system.membus.pkt_count 546 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 17472 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size 17472 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 17472 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 337000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 2.8 # Layer utilization (%) -system.membus.respLayer1.occupancy 2542750 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 21.5 # Layer utilization (%) -system.cpu.branchPred.lookups 1157 # Number of BP lookups -system.cpu.branchPred.condPredicted 604 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 257 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 791 # Number of BTB lookups -system.cpu.branchPred.BTBHits 240 # Number of BTB hits +system.membus.reqLayer0.occupancy 344000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 2.9 # Layer utilization (%) +system.membus.respLayer1.occupancy 2554500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 21.4 # Layer utilization (%) +system.cpu.branchPred.lookups 1175 # Number of BP lookups +system.cpu.branchPred.condPredicted 618 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 258 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 804 # Number of BTB lookups +system.cpu.branchPred.BTBHits 253 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 30.341340 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 31.467662 # BTB Hit Percentage system.cpu.branchPred.usedRAS 212 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 37 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 704 # DTB read hits -system.cpu.dtb.read_misses 28 # DTB read misses +system.cpu.dtb.read_hits 707 # DTB read hits +system.cpu.dtb.read_misses 31 # DTB read misses system.cpu.dtb.read_acv 1 # DTB read access violations -system.cpu.dtb.read_accesses 732 # DTB read accesses -system.cpu.dtb.write_hits 354 # DTB write hits -system.cpu.dtb.write_misses 19 # DTB write misses +system.cpu.dtb.read_accesses 738 # DTB read accesses +system.cpu.dtb.write_hits 371 # DTB write hits +system.cpu.dtb.write_misses 20 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 373 # DTB write accesses -system.cpu.dtb.data_hits 1058 # DTB hits -system.cpu.dtb.data_misses 47 # DTB misses +system.cpu.dtb.write_accesses 391 # DTB write accesses +system.cpu.dtb.data_hits 1078 # DTB hits +system.cpu.dtb.data_misses 51 # DTB misses system.cpu.dtb.data_acv 1 # DTB access violations -system.cpu.dtb.data_accesses 1105 # DTB accesses -system.cpu.itb.fetch_hits 1045 # ITB hits +system.cpu.dtb.data_accesses 1129 # DTB accesses +system.cpu.itb.fetch_hits 1067 # ITB hits system.cpu.itb.fetch_misses 30 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 1075 # ITB accesses +system.cpu.itb.fetch_accesses 1097 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -242,238 +242,238 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4 # Number of system calls -system.cpu.numCycles 23697 # number of cpu cycles simulated +system.cpu.numCycles 23868 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 4326 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 6897 # Number of instructions fetch has processed -system.cpu.fetch.Branches 1157 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 452 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 1190 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 858 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 471 # Number of cycles fetch has spent blocked +system.cpu.fetch.icacheStallCycles 4327 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 7029 # Number of instructions fetch has processed +system.cpu.fetch.Branches 1175 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 465 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 1212 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 873 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 541 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 18 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1121 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingTrapStallCycles 1118 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 11 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 1045 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 182 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 7700 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.895714 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.301681 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 1067 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 189 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 7803 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.900807 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.307084 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 6510 84.55% 84.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 52 0.68% 85.22% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 117 1.52% 86.74% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 91 1.18% 87.92% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 172 2.23% 90.16% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 75 0.97% 91.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 61 0.79% 91.92% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 67 0.87% 92.79% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 555 7.21% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 6591 84.47% 84.47% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 53 0.68% 85.15% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 115 1.47% 86.62% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 95 1.22% 87.84% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 179 2.29% 90.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 74 0.95% 91.08% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 64 0.82% 91.90% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 65 0.83% 92.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 567 7.27% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 7700 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.048825 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.291049 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 5567 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 499 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 1144 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 5 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 485 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 163 # Number of times decode resolved a branch +system.cpu.fetch.rateDist::total 7803 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.049229 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.294495 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 5563 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 577 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 1156 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 9 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 498 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 165 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 81 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 6120 # Number of instructions handled by decode +system.cpu.decode.DecodedInsts 6218 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 292 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 485 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 5671 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 178 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 290 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 1044 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 32 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 5812 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 3 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 9 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 10 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 4232 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 6563 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 6551 # Number of integer rename lookups +system.cpu.rename.SquashCycles 498 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 5662 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 254 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 288 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 1065 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 36 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 5911 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 1 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 14 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 13 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 4285 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 6686 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 6674 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 12 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1768 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 2464 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 2517 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 8 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 6 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 121 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 948 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 455 # Number of stores inserted to the mem dependence unit. +system.cpu.rename.skidInsts 139 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 957 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 471 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 3 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 4912 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.memDep0.conflictingStores 3 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 4973 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 6 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 4000 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 63 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 2288 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1369 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 4046 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 54 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 2348 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1391 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 7700 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.519481 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.232756 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 7803 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.518519 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.233664 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 6104 79.27% 79.27% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 546 7.09% 86.36% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 391 5.08% 91.44% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 259 3.36% 94.81% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 207 2.69% 97.49% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 122 1.58% 99.08% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 48 0.62% 99.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 15 0.19% 99.90% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 8 0.10% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 6178 79.17% 79.17% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 567 7.27% 86.44% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 400 5.13% 91.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 263 3.37% 94.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 199 2.55% 97.49% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 121 1.55% 99.04% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 47 0.60% 99.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 17 0.22% 99.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 11 0.14% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 7700 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 7803 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 2 4.55% 4.55% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 4.55% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 4.55% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.55% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.55% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.55% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 4.55% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.55% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 4.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 4.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.55% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 19 43.18% 47.73% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 23 52.27% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 3 6.82% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 19 43.18% 50.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 22 50.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 2840 71.00% 71.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 1 0.03% 71.02% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 71.02% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 71.02% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 71.02% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 71.02% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 71.02% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 71.02% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 71.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 71.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 71.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 71.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 71.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 71.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 71.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 71.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 71.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 71.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 71.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 71.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 71.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 71.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 71.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 71.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 71.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 71.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 71.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 71.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 71.02% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 778 19.45% 90.47% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 381 9.53% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 2864 70.79% 70.79% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 1 0.02% 70.81% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.81% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.81% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.81% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 70.81% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 70.81% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 70.81% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 70.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 70.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 70.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 70.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 70.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 70.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 70.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 70.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 70.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 70.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 70.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 70.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 70.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 70.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 70.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.81% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 783 19.35% 90.16% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 398 9.84% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 4000 # Type of FU issued -system.cpu.iq.rate 0.168798 # Inst issue rate +system.cpu.iq.FU_type_0::total 4046 # Type of FU issued +system.cpu.iq.rate 0.169516 # Inst issue rate system.cpu.iq.fu_busy_cnt 44 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.011000 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 15794 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 7204 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 3598 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fu_busy_rate 0.010875 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 15980 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 7325 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 3655 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 13 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 6 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 6 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 4037 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 4083 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 7 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 32 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 33 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 533 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 5 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 161 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 542 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 1 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 4 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 177 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 15 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 16 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 485 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 153 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 2 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 5240 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 498 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 228 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 4 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 5317 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 162 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 948 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 455 # Number of dispatched store instructions +system.cpu.iew.iewDispLoadInsts 957 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 471 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 6 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewIQFullEvents 2 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 5 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 53 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 159 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 212 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 3798 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 733 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 202 # Number of squashed instructions skipped in execute +system.cpu.iew.memOrderViolationEvents 4 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 52 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 162 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 214 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 3855 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 739 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 191 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 322 # number of nop insts executed -system.cpu.iew.exec_refs 1106 # number of memory reference insts executed -system.cpu.iew.exec_branches 638 # Number of branches executed -system.cpu.iew.exec_stores 373 # Number of stores executed -system.cpu.iew.exec_rate 0.160273 # Inst execution rate -system.cpu.iew.wb_sent 3682 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 3604 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1694 # num instructions producing a value -system.cpu.iew.wb_consumers 2179 # num instructions consuming a value +system.cpu.iew.exec_nop 338 # number of nop insts executed +system.cpu.iew.exec_refs 1130 # number of memory reference insts executed +system.cpu.iew.exec_branches 644 # Number of branches executed +system.cpu.iew.exec_stores 391 # Number of stores executed +system.cpu.iew.exec_rate 0.161513 # Inst execution rate +system.cpu.iew.wb_sent 3741 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 3661 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1709 # num instructions producing a value +system.cpu.iew.wb_consumers 2209 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.152087 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.777421 # average fanout of values written-back +system.cpu.iew.wb_rate 0.153385 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.773653 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 2655 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 2732 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 4 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 179 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 7215 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.357034 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.202430 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 180 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 7305 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.352635 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.192667 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 6348 87.98% 87.98% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 203 2.81% 90.80% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 309 4.28% 95.08% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 113 1.57% 96.65% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 69 0.96% 97.60% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 52 0.72% 98.32% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 33 0.46% 98.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 22 0.30% 99.09% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 66 0.91% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 6436 88.10% 88.10% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 204 2.79% 90.90% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 308 4.22% 95.11% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 114 1.56% 96.67% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 72 0.99% 97.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 51 0.70% 98.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 32 0.44% 98.80% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 25 0.34% 99.14% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 63 0.86% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 7215 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 7305 # Number of insts commited each cycle system.cpu.commit.committedInsts 2576 # Number of instructions committed system.cpu.commit.committedOps 2576 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -484,93 +484,93 @@ system.cpu.commit.branches 396 # Nu system.cpu.commit.fp_insts 6 # Number of committed floating point instructions. system.cpu.commit.int_insts 2367 # Number of committed integer instructions. system.cpu.commit.function_calls 71 # Number of function calls committed. -system.cpu.commit.bw_lim_events 66 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 63 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 12133 # The number of ROB reads -system.cpu.rob.rob_writes 10960 # The number of ROB writes -system.cpu.timesIdled 164 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 15997 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 12303 # The number of ROB reads +system.cpu.rob.rob_writes 11127 # The number of ROB writes +system.cpu.timesIdled 159 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 16065 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 2387 # Number of Instructions Simulated system.cpu.committedOps 2387 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 2387 # Number of Instructions Simulated -system.cpu.cpi 9.927524 # CPI: Cycles Per Instruction -system.cpu.cpi_total 9.927524 # CPI: Total CPI of All Threads -system.cpu.ipc 0.100730 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.100730 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 4598 # number of integer regfile reads -system.cpu.int_regfile_writes 2789 # number of integer regfile writes +system.cpu.cpi 9.999162 # CPI: Cycles Per Instruction +system.cpu.cpi_total 9.999162 # CPI: Total CPI of All Threads +system.cpu.ipc 0.100008 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.100008 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 4674 # number of integer regfile reads +system.cpu.int_regfile_writes 2826 # number of integer regfile writes system.cpu.fp_regfile_reads 6 # number of floating regfile reads system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.toL2Bus.throughput 1469277515 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 248 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 248 # Transaction distribution +system.cpu.toL2Bus.throughput 1464113630 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 249 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 249 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 24 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 24 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 374 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 376 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 170 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count 544 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 11968 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count 546 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 12032 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 5440 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size 17408 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 17408 # Total data (bytes) +system.cpu.toL2Bus.tot_pkt_size 17472 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 17472 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 136000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.occupancy 136500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 280500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 2.4 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 127500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 318000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 2.7 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 135500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.1 # Layer utilization (%) -system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 91.300481 # Cycle average of tags in use -system.cpu.icache.total_refs 795 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 187 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 4.251337 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 91.300481 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.044580 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.044580 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 795 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 795 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 795 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 795 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 795 # number of overall hits -system.cpu.icache.overall_hits::total 795 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 250 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 250 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 250 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 250 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 250 # number of overall misses -system.cpu.icache.overall_misses::total 250 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 16821499 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 16821499 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 16821499 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 16821499 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 16821499 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 16821499 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1045 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1045 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1045 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1045 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1045 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1045 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.239234 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.239234 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.239234 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.239234 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.239234 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.239234 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 67285.996000 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 67285.996000 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 67285.996000 # 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number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1421000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1421000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10328500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5278250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 15606750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10328500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5278250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 15606750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_misses::total 273 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10234500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3797750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14032250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1425250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1425250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10234500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5223000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 15457500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10234500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5223000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 15457500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -712,91 +712,91 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 1 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55232.620321 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63233.606557 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57200.604839 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 59208.333333 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 59208.333333 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55232.620321 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62097.058824 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57377.757353 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55232.620321 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62097.058824 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57377.757353 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 54438.829787 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62258.196721 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56354.417671 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 59385.416667 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 59385.416667 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54438.829787 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61447.058824 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56620.879121 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54438.829787 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61447.058824 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56620.879121 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 44.834743 # Cycle average of tags in use -system.cpu.dcache.total_refs 761 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 85 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 8.952941 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 44.834743 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.010946 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.010946 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 548 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 548 # number of ReadReq hits +system.cpu.dcache.tags.replacements 0 # number of replacements +system.cpu.dcache.tags.tagsinuse 44.879167 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 758 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 85 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 8.917647 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 44.879167 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.010957 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.010957 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 545 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 545 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 213 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 213 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 761 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 761 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 761 # number of overall hits -system.cpu.dcache.overall_hits::total 761 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 109 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 109 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 758 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 758 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 758 # number of overall hits +system.cpu.dcache.overall_hits::total 758 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 113 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 113 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 81 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 81 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 190 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 190 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 190 # number of overall misses -system.cpu.dcache.overall_misses::total 190 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 7852000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 7852000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 5307500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 5307500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 13159500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 13159500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 13159500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 13159500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 657 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 657 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 194 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 194 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 194 # number of overall misses +system.cpu.dcache.overall_misses::total 194 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 7467750 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 7467750 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 5336000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 5336000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 12803750 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 12803750 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 12803750 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 12803750 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 658 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 658 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 294 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 294 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 951 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 951 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 951 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 951 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.165906 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.165906 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 952 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 952 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 952 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 952 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.171733 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.171733 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.275510 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.275510 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.199790 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.199790 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.199790 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.199790 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 72036.697248 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 72036.697248 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65524.691358 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 65524.691358 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 69260.526316 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 69260.526316 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 69260.526316 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 69260.526316 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 144 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.203782 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.203782 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.203782 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.203782 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 66086.283186 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 66086.283186 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65876.543210 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 65876.543210 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 65998.711340 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 65998.711340 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 65998.711340 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 65998.711340 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 145 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 4 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 36 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 36.250000 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 48 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 48 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 52 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 52 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 57 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 57 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 105 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 105 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 105 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 105 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 109 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 109 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 109 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 109 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 61 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 61 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 24 # number of WriteReq MSHR misses @@ -805,30 +805,30 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 85 system.cpu.dcache.demand_mshr_misses::total 85 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 85 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 85 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4662500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4662500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1739500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1739500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6402000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6402000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6402000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6402000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.092846 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.092846 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4608250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4608250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1746250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1746250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6354500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6354500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6354500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6354500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.092705 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.092705 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.081633 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.081633 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.089380 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.089380 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.089380 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.089380 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 76434.426230 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 76434.426230 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 72479.166667 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 72479.166667 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75317.647059 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 75317.647059 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75317.647059 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 75317.647059 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.089286 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.089286 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.089286 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.089286 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 75545.081967 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 75545.081967 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 72760.416667 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 72760.416667 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 74758.823529 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 74758.823529 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74758.823529 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 74758.823529 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt index cb629b252..034aea3e9 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt @@ -97,15 +97,15 @@ system.cpu.num_idle_cycles 0 # Nu system.cpu.num_busy_cycles 33048 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 80.050296 # Cycle average of tags in use -system.cpu.icache.total_refs 2423 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 163 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 14.865031 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 80.050296 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.039087 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.039087 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 0 # number of replacements +system.cpu.icache.tags.tagsinuse 80.050296 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 2423 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 163 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 14.865031 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 80.050296 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.039087 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.039087 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 2423 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 2423 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 2423 # number of demand (read+write) hits @@ -175,17 +175,17 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 53000 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 107.162861 # Cycle average of tags in use -system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 218 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 80.168669 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 26.994192 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.002447 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.000824 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.003270 # Average percentage of cache occupancy +system.cpu.l2cache.tags.replacements 0 # number of replacements +system.cpu.l2cache.tags.tagsinuse 107.162861 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 0 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 218 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::cpu.inst 80.168669 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 26.994192 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002447 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.000824 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.003270 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_misses::cpu.inst 163 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.data 55 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::total 218 # number of ReadReq misses @@ -294,15 +294,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 47.437790 # Cycle average of tags in use -system.cpu.dcache.total_refs 627 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 82 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 7.646341 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 47.437790 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.011581 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.011581 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 0 # number of replacements +system.cpu.dcache.tags.tagsinuse 47.437790 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 627 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 82 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 7.646341 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 47.437790 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.011581 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.011581 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 360 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 360 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 267 # number of WriteReq hits diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt index 6938f2714..22dbcae6d 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000016 # Number of seconds simulated -sim_ticks 16387000 # Number of ticks simulated -final_tick 16387000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 16494000 # Number of ticks simulated +final_tick 16494000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 31359 # Simulator instruction rate (inst/s) -host_op_rate 39125 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 111893890 # Simulator tick rate (ticks/s) -host_mem_usage 244352 # Number of bytes of host memory used +host_inst_rate 31208 # Simulator instruction rate (inst/s) +host_op_rate 38937 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 112083077 # Simulator tick rate (ticks/s) +host_mem_usage 244336 # Number of bytes of host memory used host_seconds 0.15 # Real time elapsed on the host sim_insts 4591 # Number of instructions simulated sim_ops 5729 # Number of ops (including micro ops) simulated @@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 17344 # Nu system.physmem.num_reads::cpu.inst 271 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 122 # Number of read requests responded to by this memory system.physmem.num_reads::total 393 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1058399951 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 476475255 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1534875206 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1058399951 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1058399951 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1058399951 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 476475255 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1534875206 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1051533891 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 473384261 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1524918152 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1051533891 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1051533891 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1051533891 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 473384261 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1524918152 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 393 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen system.physmem.cpureqs 393 # Reqs generatd by CPU via cache - shady @@ -70,7 +70,7 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 16329500 # Total gap between requests +system.physmem.totGap 16436500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes @@ -85,11 +85,11 @@ system.physmem.writePktSize::3 0 # Ca system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes system.physmem.writePktSize::6 0 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 213 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 118 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 42 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 16 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 210 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 120 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 43 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 15 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -168,28 +168,28 @@ system.physmem.bytesPerActivate::1216 1 2.22% 93.33% # By system.physmem.bytesPerActivate::1536 2 4.44% 97.78% # Bytes accessed per row activation system.physmem.bytesPerActivate::1856 1 2.22% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 45 # Bytes accessed per row activation -system.physmem.totQLat 2029000 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 9466500 # Sum of mem lat for all requests +system.physmem.totQLat 2047500 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 9457500 # Sum of mem lat for all requests system.physmem.totBusLat 1965000 # Total cycles spent in databus access -system.physmem.totBankLat 5472500 # Total cycles spent in bank access -system.physmem.avgQLat 5162.85 # Average queueing delay per request -system.physmem.avgBankLat 13924.94 # Average bank access latency per request +system.physmem.totBankLat 5445000 # Total cycles spent in bank access +system.physmem.avgQLat 5209.92 # Average queueing delay per request +system.physmem.avgBankLat 13854.96 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 24087.79 # Average memory access latency -system.physmem.avgRdBW 1534.88 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 24064.89 # Average memory access latency +system.physmem.avgRdBW 1524.92 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 1534.88 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 1524.92 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 11.99 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.58 # Average read queue length over time +system.physmem.busUtil 11.91 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.57 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time system.physmem.readRowHits 348 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 88.55 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 41550.89 # Average gap between requests -system.membus.throughput 1534875206 # Throughput (bytes/s) +system.physmem.avgGap 41823.16 # Average gap between requests +system.membus.throughput 1524918152 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 352 # Transaction distribution system.membus.trans_dist::ReadResp 352 # Transaction distribution system.membus.trans_dist::ReadExReq 41 # Transaction distribution @@ -200,18 +200,18 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 25152 system.membus.tot_pkt_size 25152 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 25152 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 480500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 2.9 # Layer utilization (%) -system.membus.respLayer1.occupancy 3664000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 22.4 # Layer utilization (%) -system.cpu.branchPred.lookups 2471 # Number of BP lookups -system.cpu.branchPred.condPredicted 1774 # Number of conditional branches predicted +system.membus.reqLayer0.occupancy 487500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 3.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 3671250 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 22.3 # Layer utilization (%) +system.cpu.branchPred.lookups 2479 # Number of BP lookups +system.cpu.branchPred.condPredicted 1778 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 482 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 1960 # Number of BTB lookups -system.cpu.branchPred.BTBHits 695 # Number of BTB hits +system.cpu.branchPred.BTBLookups 1966 # Number of BTB lookups +system.cpu.branchPred.BTBHits 697 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 35.459184 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 292 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 35.452696 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 293 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 71 # Number of incorrect RAS predictions. system.cpu.checker.dtb.inst_hits 0 # ITB inst hits system.cpu.checker.dtb.inst_misses 0 # ITB inst misses @@ -301,129 +301,129 @@ system.cpu.itb.inst_accesses 0 # IT system.cpu.itb.hits 0 # DTB hits system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses -system.cpu.numCycles 32775 # number of cpu cycles simulated +system.cpu.numCycles 32989 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 6975 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 11884 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2471 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 987 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 2620 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1611 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 2625 # Number of cycles fetch has spent blocked -system.cpu.fetch.CacheLines 1942 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 283 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 13325 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.128105 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.544240 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 6948 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 11906 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2479 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 990 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 2625 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1612 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 2605 # Number of cycles fetch has spent blocked +system.cpu.fetch.CacheLines 1947 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 285 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 13284 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.132565 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.547443 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 10705 80.34% 80.34% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 226 1.70% 82.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 201 1.51% 83.54% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 224 1.68% 85.22% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 220 1.65% 86.87% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 270 2.03% 88.90% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 92 0.69% 89.59% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 146 1.10% 90.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1241 9.31% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 10659 80.24% 80.24% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 226 1.70% 81.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 203 1.53% 83.47% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 226 1.70% 85.17% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 222 1.67% 86.84% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 269 2.02% 88.87% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 92 0.69% 89.56% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 146 1.10% 90.66% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1241 9.34% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 13325 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.075393 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.362593 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 6989 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 2898 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2415 # Number of cycles decode is running +system.cpu.fetch.rateDist::total 13284 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.075146 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.360908 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 6958 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 2882 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 2420 # Number of cycles decode is running system.cpu.decode.UnblockCycles 73 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 950 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 382 # Number of times decode resolved a branch +system.cpu.decode.SquashCycles 951 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 384 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 159 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 13178 # Number of instructions handled by decode +system.cpu.decode.DecodedInsts 13206 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 538 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 950 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 7255 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 368 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 2315 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2217 # Number of cycles rename is running +system.cpu.rename.SquashCycles 951 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 7225 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 370 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 2297 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 2221 # Number of cycles rename is running system.cpu.rename.UnblockCycles 220 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 12419 # Number of instructions processed by rename +system.cpu.rename.RenamedInsts 12443 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 2 # Number of times rename has blocked due to ROB full system.cpu.rename.IQFullEvents 9 # Number of times rename has blocked due to IQ full system.cpu.rename.LSQFullEvents 174 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 12443 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 56366 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 56110 # Number of integer rename lookups +system.cpu.rename.RenamedOperands 12464 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 56458 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 56202 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 256 # Number of floating rename lookups system.cpu.rename.CommittedMaps 5673 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 6770 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 6791 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 41 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 38 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 688 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2784 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1569 # Number of stores inserted to the mem dependence unit. +system.cpu.rename.skidInsts 682 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2779 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1570 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 37 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 14 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 11162 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 11163 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 49 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 8921 # Number of instructions issued +system.cpu.iq.iqInstsIssued 8917 # Number of instructions issued system.cpu.iq.iqSquashedInstsIssued 111 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 5126 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 14148 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedInstsExamined 5116 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 14167 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 12 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 13325 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.669493 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.373683 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 13284 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.671259 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.374349 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 9737 73.07% 73.07% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1330 9.98% 83.05% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 808 6.06% 89.12% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 537 4.03% 93.15% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 465 3.49% 96.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 260 1.95% 98.59% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 124 0.93% 99.52% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 52 0.39% 99.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 9700 73.02% 73.02% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1316 9.91% 82.93% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 817 6.15% 89.08% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 549 4.13% 93.21% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 456 3.43% 96.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 257 1.93% 98.58% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 124 0.93% 99.51% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 53 0.40% 99.91% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 12 0.09% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 13325 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 13284 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 6 2.69% 2.69% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 2.69% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 2.69% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.69% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.69% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.69% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 2.69% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.69% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 2.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 2.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.69% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 139 62.33% 65.02% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 78 34.98% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 6 2.70% 2.70% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 2.70% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 2.70% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.70% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.70% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.70% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 2.70% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.70% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 2.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 2.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.70% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 138 62.16% 64.86% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 78 35.14% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 5362 60.11% 60.11% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 5360 60.11% 60.11% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 9 0.10% 60.21% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.21% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.21% # Type of FU issued @@ -452,84 +452,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.24% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.24% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.24% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.24% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2334 26.16% 86.40% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2332 26.15% 86.40% # Type of FU issued system.cpu.iq.FU_type_0::MemWrite 1213 13.60% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 8921 # Type of FU issued -system.cpu.iq.rate 0.272189 # Inst issue rate -system.cpu.iq.fu_busy_cnt 223 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.024997 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 31465 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 16306 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 8052 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 8917 # Type of FU issued +system.cpu.iq.rate 0.270302 # Inst issue rate +system.cpu.iq.fu_busy_cnt 222 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.024896 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 31415 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 16297 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 8051 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 48 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 9124 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 9119 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 60 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1584 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1579 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 21 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 631 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 632 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 3 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 950 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 232 # Number of cycles IEW is blocking +system.cpu.iew.iewSquashCycles 951 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 234 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 18 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 11211 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 120 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2784 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1569 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 11212 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 126 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2779 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1570 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 37 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 10 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 21 # Number of memory order violations system.cpu.iew.predictedTakenIncorrect 108 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 269 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 377 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 8517 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 2134 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 404 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedNotTakenIncorrect 270 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 378 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 8520 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 2136 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 397 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 3294 # number of memory reference insts executed -system.cpu.iew.exec_branches 1436 # Number of branches executed +system.cpu.iew.exec_refs 3296 # number of memory reference insts executed +system.cpu.iew.exec_branches 1437 # Number of branches executed system.cpu.iew.exec_stores 1160 # Number of stores executed -system.cpu.iew.exec_rate 0.259863 # Inst execution rate +system.cpu.iew.exec_rate 0.258268 # Inst execution rate system.cpu.iew.wb_sent 8224 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 8068 # cumulative count of insts written-back -system.cpu.iew.wb_producers 3885 # num instructions producing a value -system.cpu.iew.wb_consumers 7780 # num instructions consuming a value +system.cpu.iew.wb_count 8067 # cumulative count of insts written-back +system.cpu.iew.wb_producers 3881 # num instructions producing a value +system.cpu.iew.wb_consumers 7779 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.246163 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.499357 # average fanout of values written-back +system.cpu.iew.wb_rate 0.244536 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.498907 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 5487 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 5488 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 327 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 12375 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.462949 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.295788 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 12333 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.464526 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.297335 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 10091 81.54% 81.54% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1074 8.68% 90.22% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 396 3.20% 93.42% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 256 2.07% 95.49% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 180 1.45% 96.95% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 172 1.39% 98.34% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 49 0.40% 98.73% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 35 0.28% 99.01% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 10050 81.49% 81.49% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1067 8.65% 90.14% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 402 3.26% 93.40% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 262 2.12% 95.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 174 1.41% 96.94% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 172 1.39% 98.33% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 48 0.39% 98.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 36 0.29% 99.01% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::8 122 0.99% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 12375 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 12333 # Number of insts commited each cycle system.cpu.commit.committedInsts 4591 # Number of instructions committed system.cpu.commit.committedOps 5729 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -542,23 +542,23 @@ system.cpu.commit.int_insts 4976 # Nu system.cpu.commit.function_calls 82 # Number of function calls committed. system.cpu.commit.bw_lim_events 122 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 23312 # The number of ROB reads -system.cpu.rob.rob_writes 23396 # The number of ROB writes -system.cpu.timesIdled 224 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 19450 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 23271 # The number of ROB reads +system.cpu.rob.rob_writes 23399 # The number of ROB writes +system.cpu.timesIdled 219 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 19705 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 4591 # Number of Instructions Simulated system.cpu.committedOps 5729 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 4591 # Number of Instructions Simulated -system.cpu.cpi 7.138968 # CPI: Cycles Per Instruction -system.cpu.cpi_total 7.138968 # CPI: Total CPI of All Threads -system.cpu.ipc 0.140076 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.140076 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 39187 # number of integer regfile reads -system.cpu.int_regfile_writes 7985 # number of integer regfile writes +system.cpu.cpi 7.185580 # CPI: Cycles Per Instruction +system.cpu.cpi_total 7.185580 # CPI: Total CPI of All Threads +system.cpu.ipc 0.139168 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.139168 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 39193 # number of integer regfile reads +system.cpu.int_regfile_writes 7983 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.misc_regfile_reads 2976 # number of misc regfile reads +system.cpu.misc_regfile_reads 2975 # number of misc regfile reads system.cpu.misc_regfile_writes 24 # number of misc regfile writes -system.cpu.toL2Bus.throughput 1706718740 # Throughput (bytes/s) +system.cpu.toL2Bus.throughput 1695646902 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 397 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 396 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 41 # Transaction distribution @@ -573,60 +573,60 @@ system.cpu.toL2Bus.data_through_bus 27968 # To system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 219000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.3 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 436500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 2.7 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 221495 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 485250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 2.9 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 231495 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.4 # Layer utilization (%) -system.cpu.icache.replacements 4 # number of replacements -system.cpu.icache.tagsinuse 145.578272 # Cycle average of tags in use -system.cpu.icache.total_refs 1578 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 291 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 5.422680 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 145.578272 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.071083 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.071083 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 1578 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1578 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1578 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1578 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1578 # number of overall hits -system.cpu.icache.overall_hits::total 1578 # number of overall hits +system.cpu.icache.tags.replacements 4 # number of replacements +system.cpu.icache.tags.tagsinuse 145.483199 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 1583 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 291 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 5.439863 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 145.483199 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.071037 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.071037 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 1583 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1583 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1583 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1583 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1583 # number of overall hits +system.cpu.icache.overall_hits::total 1583 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 364 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 364 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 364 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 364 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 364 # number of overall misses system.cpu.icache.overall_misses::total 364 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 22955000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 22955000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 22955000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 22955000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 22955000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 22955000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1942 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1942 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1942 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1942 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1942 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1942 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.187436 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.187436 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.187436 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.187436 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.187436 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.187436 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 63063.186813 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 63063.186813 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 63063.186813 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 63063.186813 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 63063.186813 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 63063.186813 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 121 # number of cycles access was blocked +system.cpu.icache.ReadReq_miss_latency::cpu.inst 23224750 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 23224750 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 23224750 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 23224750 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 23224750 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 23224750 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1947 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1947 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1947 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1947 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1947 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1947 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.186954 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.186954 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.186954 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.186954 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.186954 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.186954 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 63804.258242 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 63804.258242 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 63804.258242 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 63804.258242 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 63804.258242 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 63804.258242 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 126 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 3 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 40.333333 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 42 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed @@ -642,36 +642,36 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 291 system.cpu.icache.demand_mshr_misses::total 291 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 291 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 291 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 18642000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 18642000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 18642000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 18642000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 18642000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 18642000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.149846 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.149846 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.149846 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.149846 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.149846 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.149846 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 64061.855670 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 64061.855670 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 64061.855670 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 64061.855670 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 64061.855670 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 64061.855670 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 18700750 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 18700750 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 18700750 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 18700750 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 18700750 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 18700750 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.149461 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.149461 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.149461 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.149461 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.149461 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.149461 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 64263.745704 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 64263.745704 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 64263.745704 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 64263.745704 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 64263.745704 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 64263.745704 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 183.439490 # Cycle average of tags in use -system.cpu.l2cache.total_refs 40 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 352 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.113636 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 137.046036 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 46.393454 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.004182 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.001416 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.005598 # Average percentage of cache occupancy +system.cpu.l2cache.tags.replacements 0 # number of replacements +system.cpu.l2cache.tags.tagsinuse 183.328645 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 40 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 352 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.113636 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::cpu.inst 136.957008 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 46.371637 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004180 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.001415 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.005595 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 20 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 20 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 40 # number of ReadReq hits @@ -692,17 +692,17 @@ system.cpu.l2cache.demand_misses::total 398 # nu system.cpu.l2cache.overall_misses::cpu.inst 271 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 127 # number of overall misses system.cpu.l2cache.overall_misses::total 398 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 18145000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 6188500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 24333500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2992500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 2992500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 18145000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 9181000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 27326000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 18145000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 9181000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 27326000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 18203750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 6199500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 24403250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2997250 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 2997250 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 18203750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 9196750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 27400500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 18203750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 9196750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 27400500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 291 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 106 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 397 # number of ReadReq accesses(hits+misses) @@ -725,17 +725,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.908676 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.931271 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.863946 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.908676 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 66955.719557 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 71959.302326 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 68161.064426 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72987.804878 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72987.804878 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66955.719557 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 72291.338583 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 68658.291457 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66955.719557 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 72291.338583 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 68658.291457 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67172.509225 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 72087.209302 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 68356.442577 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73103.658537 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73103.658537 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67172.509225 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 72415.354331 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 68845.477387 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67172.509225 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 72415.354331 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 68845.477387 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -761,17 +761,17 @@ system.cpu.l2cache.demand_mshr_misses::total 393 system.cpu.l2cache.overall_mshr_misses::cpu.inst 271 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 122 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 393 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 14791750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4905500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 19697250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2490250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2490250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 14791750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7395750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 22187500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 14791750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7395750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 22187500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 14794250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4906250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 19700500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2492250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2492250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 14794250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7398500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 22192750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 14794250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7398500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 22192750 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.931271 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.764151 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.886650 # mshr miss rate for ReadReq accesses @@ -783,39 +783,39 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.897260 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.931271 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.829932 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.897260 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 54582.103321 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60561.728395 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55958.096591 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60737.804878 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60737.804878 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54582.103321 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60620.901639 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56456.743003 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54582.103321 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60620.901639 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56456.743003 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 54591.328413 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60570.987654 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55967.329545 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60786.585366 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60786.585366 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54591.328413 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60643.442623 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56470.101781 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54591.328413 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60643.442623 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56470.101781 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 85.937637 # Cycle average of tags in use -system.cpu.dcache.total_refs 2388 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 146 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 16.356164 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 85.937637 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.020981 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.020981 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 1760 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1760 # number of ReadReq hits +system.cpu.dcache.tags.replacements 0 # number of replacements +system.cpu.dcache.tags.tagsinuse 85.893510 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 2390 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 146 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 16.369863 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 85.893510 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.020970 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.020970 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 1763 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1763 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 606 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 606 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 11 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 11 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 10 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 10 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 2366 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2366 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2366 # number of overall hits -system.cpu.dcache.overall_hits::total 2366 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 2369 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2369 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2369 # number of overall hits +system.cpu.dcache.overall_hits::total 2369 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 190 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 190 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 307 # number of WriteReq misses @@ -826,53 +826,53 @@ system.cpu.dcache.demand_misses::cpu.data 497 # n system.cpu.dcache.demand_misses::total 497 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 497 # number of overall misses system.cpu.dcache.overall_misses::total 497 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 10638500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 10638500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 19663000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 19663000 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 127500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 127500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 30301500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 30301500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 30301500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 30301500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1950 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1950 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_miss_latency::cpu.data 10660493 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 10660493 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 19773250 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 19773250 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 130000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 130000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 30433743 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 30433743 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 30433743 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 30433743 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1953 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1953 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 13 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 13 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 12 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 12 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2863 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2863 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2863 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2863 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.097436 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.097436 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 2866 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2866 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2866 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2866 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.097286 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.097286 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.336254 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.336254 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.153846 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.153846 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.173594 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.173594 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.173594 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.173594 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55992.105263 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 55992.105263 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64048.859935 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 64048.859935 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 63750 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 63750 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 60968.812877 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 60968.812877 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 60968.812877 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 60968.812877 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 103 # number of cycles access was blocked +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.166667 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.166667 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.173412 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.173412 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.173412 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.173412 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56107.857895 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 56107.857895 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64407.980456 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 64407.980456 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 65000 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 65000 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 61234.895372 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 61234.895372 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 61234.895372 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 61234.895372 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 98 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 34.333333 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 32.666667 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed @@ -894,30 +894,30 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 147 system.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6438005 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 6438005 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3034500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3034500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9472505 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 9472505 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9472505 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 9472505 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.054359 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.054359 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6447755 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 6447755 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3039250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3039250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9487005 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 9487005 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9487005 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 9487005 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.054275 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.054275 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044907 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.044907 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.051345 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.051345 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.051345 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.051345 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 60735.896226 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 60735.896226 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74012.195122 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74012.195122 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 64438.809524 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 64438.809524 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 64438.809524 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 64438.809524 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.051291 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.051291 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.051291 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.051291 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 60827.877358 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 60827.877358 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74128.048780 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74128.048780 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 64537.448980 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 64537.448980 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 64537.448980 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 64537.448980 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt index 42ebdbb61..3ccfc050f 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000016 # Number of seconds simulated -sim_ticks 16387000 # Number of ticks simulated -final_tick 16387000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 16494000 # Number of ticks simulated +final_tick 16494000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 36614 # Simulator instruction rate (inst/s) -host_op_rate 45680 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 130634561 # Simulator tick rate (ticks/s) -host_mem_usage 244344 # Number of bytes of host memory used -host_seconds 0.13 # Real time elapsed on the host +host_inst_rate 66928 # Simulator instruction rate (inst/s) +host_op_rate 83502 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 240363471 # Simulator tick rate (ticks/s) +host_mem_usage 244336 # Number of bytes of host memory used +host_seconds 0.07 # Real time elapsed on the host sim_insts 4591 # Number of instructions simulated sim_ops 5729 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 17344 # Number of bytes read from this memory @@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 17344 # Nu system.physmem.num_reads::cpu.inst 271 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 122 # Number of read requests responded to by this memory system.physmem.num_reads::total 393 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1058399951 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 476475255 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1534875206 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1058399951 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1058399951 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1058399951 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 476475255 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1534875206 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1051533891 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 473384261 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1524918152 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1051533891 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1051533891 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1051533891 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 473384261 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1524918152 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 393 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen system.physmem.cpureqs 393 # Reqs generatd by CPU via cache - shady @@ -70,7 +70,7 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 16329500 # Total gap between requests +system.physmem.totGap 16436500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes @@ -85,11 +85,11 @@ system.physmem.writePktSize::3 0 # Ca system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes system.physmem.writePktSize::6 0 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 213 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 118 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 42 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 16 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 210 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 120 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 43 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 15 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -168,28 +168,28 @@ system.physmem.bytesPerActivate::1216 1 2.22% 93.33% # By system.physmem.bytesPerActivate::1536 2 4.44% 97.78% # Bytes accessed per row activation system.physmem.bytesPerActivate::1856 1 2.22% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 45 # Bytes accessed per row activation -system.physmem.totQLat 2029000 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 9466500 # Sum of mem lat for all requests +system.physmem.totQLat 2047500 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 9457500 # Sum of mem lat for all requests system.physmem.totBusLat 1965000 # Total cycles spent in databus access -system.physmem.totBankLat 5472500 # Total cycles spent in bank access -system.physmem.avgQLat 5162.85 # Average queueing delay per request -system.physmem.avgBankLat 13924.94 # Average bank access latency per request +system.physmem.totBankLat 5445000 # Total cycles spent in bank access +system.physmem.avgQLat 5209.92 # Average queueing delay per request +system.physmem.avgBankLat 13854.96 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 24087.79 # Average memory access latency -system.physmem.avgRdBW 1534.88 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 24064.89 # Average memory access latency +system.physmem.avgRdBW 1524.92 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 1534.88 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 1524.92 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 11.99 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.58 # Average read queue length over time +system.physmem.busUtil 11.91 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.57 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time system.physmem.readRowHits 348 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 88.55 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 41550.89 # Average gap between requests -system.membus.throughput 1534875206 # Throughput (bytes/s) +system.physmem.avgGap 41823.16 # Average gap between requests +system.membus.throughput 1524918152 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 352 # Transaction distribution system.membus.trans_dist::ReadResp 352 # Transaction distribution system.membus.trans_dist::ReadExReq 41 # Transaction distribution @@ -200,18 +200,18 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 25152 system.membus.tot_pkt_size 25152 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 25152 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 480500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 2.9 # Layer utilization (%) -system.membus.respLayer1.occupancy 3664000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 22.4 # Layer utilization (%) -system.cpu.branchPred.lookups 2471 # Number of BP lookups -system.cpu.branchPred.condPredicted 1774 # Number of conditional branches predicted +system.membus.reqLayer0.occupancy 487500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 3.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 3671250 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 22.3 # Layer utilization (%) +system.cpu.branchPred.lookups 2479 # Number of BP lookups +system.cpu.branchPred.condPredicted 1778 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 482 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 1960 # Number of BTB lookups -system.cpu.branchPred.BTBHits 695 # Number of BTB hits +system.cpu.branchPred.BTBLookups 1966 # Number of BTB lookups +system.cpu.branchPred.BTBHits 697 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 35.459184 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 292 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 35.452696 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 293 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 71 # Number of incorrect RAS predictions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses @@ -256,129 +256,129 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 13 # Number of system calls -system.cpu.numCycles 32775 # number of cpu cycles simulated +system.cpu.numCycles 32989 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 6975 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 11884 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2471 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 987 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 2620 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1611 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 2625 # Number of cycles fetch has spent blocked -system.cpu.fetch.CacheLines 1942 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 283 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 13325 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.128105 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.544240 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 6948 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 11906 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2479 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 990 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 2625 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1612 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 2605 # Number of cycles fetch has spent blocked +system.cpu.fetch.CacheLines 1947 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 285 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 13284 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.132565 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.547443 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 10705 80.34% 80.34% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 226 1.70% 82.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 201 1.51% 83.54% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 224 1.68% 85.22% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 220 1.65% 86.87% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 270 2.03% 88.90% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 92 0.69% 89.59% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 146 1.10% 90.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1241 9.31% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 10659 80.24% 80.24% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 226 1.70% 81.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 203 1.53% 83.47% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 226 1.70% 85.17% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 222 1.67% 86.84% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 269 2.02% 88.87% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 92 0.69% 89.56% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 146 1.10% 90.66% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1241 9.34% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 13325 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.075393 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.362593 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 6989 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 2898 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2415 # Number of cycles decode is running +system.cpu.fetch.rateDist::total 13284 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.075146 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.360908 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 6958 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 2882 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 2420 # Number of cycles decode is running system.cpu.decode.UnblockCycles 73 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 950 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 382 # Number of times decode resolved a branch +system.cpu.decode.SquashCycles 951 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 384 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 159 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 13178 # Number of instructions handled by decode +system.cpu.decode.DecodedInsts 13206 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 538 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 950 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 7255 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 368 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 2315 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2217 # Number of cycles rename is running +system.cpu.rename.SquashCycles 951 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 7225 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 370 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 2297 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 2221 # Number of cycles rename is running system.cpu.rename.UnblockCycles 220 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 12419 # Number of instructions processed by rename +system.cpu.rename.RenamedInsts 12443 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 2 # Number of times rename has blocked due to ROB full system.cpu.rename.IQFullEvents 9 # Number of times rename has blocked due to IQ full system.cpu.rename.LSQFullEvents 174 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 12443 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 56366 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 56110 # Number of integer rename lookups +system.cpu.rename.RenamedOperands 12464 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 56458 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 56202 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 256 # Number of floating rename lookups system.cpu.rename.CommittedMaps 5673 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 6770 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 6791 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 41 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 38 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 688 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2784 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1569 # Number of stores inserted to the mem dependence unit. +system.cpu.rename.skidInsts 682 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2779 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1570 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 37 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 14 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 11162 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 11163 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 49 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 8921 # Number of instructions issued +system.cpu.iq.iqInstsIssued 8917 # Number of instructions issued system.cpu.iq.iqSquashedInstsIssued 111 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 5126 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 14148 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedInstsExamined 5116 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 14167 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 12 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 13325 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.669493 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.373683 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 13284 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.671259 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.374349 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 9737 73.07% 73.07% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1330 9.98% 83.05% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 808 6.06% 89.12% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 537 4.03% 93.15% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 465 3.49% 96.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 260 1.95% 98.59% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 124 0.93% 99.52% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 52 0.39% 99.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 9700 73.02% 73.02% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1316 9.91% 82.93% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 817 6.15% 89.08% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 549 4.13% 93.21% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 456 3.43% 96.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 257 1.93% 98.58% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 124 0.93% 99.51% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 53 0.40% 99.91% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 12 0.09% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 13325 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 13284 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 6 2.69% 2.69% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 2.69% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 2.69% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.69% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.69% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.69% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 2.69% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.69% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 2.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 2.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.69% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 139 62.33% 65.02% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 78 34.98% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 6 2.70% 2.70% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 2.70% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 2.70% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.70% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.70% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.70% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 2.70% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.70% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 2.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 2.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.70% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 138 62.16% 64.86% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 78 35.14% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 5362 60.11% 60.11% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 5360 60.11% 60.11% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 9 0.10% 60.21% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.21% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.21% # Type of FU issued @@ -407,84 +407,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.24% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.24% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.24% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.24% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2334 26.16% 86.40% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2332 26.15% 86.40% # Type of FU issued system.cpu.iq.FU_type_0::MemWrite 1213 13.60% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 8921 # Type of FU issued -system.cpu.iq.rate 0.272189 # Inst issue rate -system.cpu.iq.fu_busy_cnt 223 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.024997 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 31465 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 16306 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 8052 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 8917 # Type of FU issued +system.cpu.iq.rate 0.270302 # Inst issue rate +system.cpu.iq.fu_busy_cnt 222 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.024896 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 31415 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 16297 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 8051 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 48 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 9124 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 9119 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 60 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1584 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1579 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 21 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 631 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 632 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 3 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 950 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 232 # Number of cycles IEW is blocking +system.cpu.iew.iewSquashCycles 951 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 234 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 18 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 11211 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 120 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2784 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1569 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 11212 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 126 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2779 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1570 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 37 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 10 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 21 # Number of memory order violations system.cpu.iew.predictedTakenIncorrect 108 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 269 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 377 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 8517 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 2134 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 404 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedNotTakenIncorrect 270 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 378 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 8520 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 2136 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 397 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 3294 # number of memory reference insts executed -system.cpu.iew.exec_branches 1436 # Number of branches executed +system.cpu.iew.exec_refs 3296 # number of memory reference insts executed +system.cpu.iew.exec_branches 1437 # Number of branches executed system.cpu.iew.exec_stores 1160 # Number of stores executed -system.cpu.iew.exec_rate 0.259863 # Inst execution rate +system.cpu.iew.exec_rate 0.258268 # Inst execution rate system.cpu.iew.wb_sent 8224 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 8068 # cumulative count of insts written-back -system.cpu.iew.wb_producers 3885 # num instructions producing a value -system.cpu.iew.wb_consumers 7780 # num instructions consuming a value +system.cpu.iew.wb_count 8067 # cumulative count of insts written-back +system.cpu.iew.wb_producers 3881 # num instructions producing a value +system.cpu.iew.wb_consumers 7779 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.246163 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.499357 # average fanout of values written-back +system.cpu.iew.wb_rate 0.244536 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.498907 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 5487 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 5488 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 327 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 12375 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.462949 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.295788 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 12333 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.464526 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.297335 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 10091 81.54% 81.54% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1074 8.68% 90.22% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 396 3.20% 93.42% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 256 2.07% 95.49% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 180 1.45% 96.95% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 172 1.39% 98.34% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 49 0.40% 98.73% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 35 0.28% 99.01% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 10050 81.49% 81.49% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1067 8.65% 90.14% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 402 3.26% 93.40% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 262 2.12% 95.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 174 1.41% 96.94% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 172 1.39% 98.33% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 48 0.39% 98.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 36 0.29% 99.01% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::8 122 0.99% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 12375 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 12333 # Number of insts commited each cycle system.cpu.commit.committedInsts 4591 # Number of instructions committed system.cpu.commit.committedOps 5729 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -497,23 +497,23 @@ system.cpu.commit.int_insts 4976 # Nu system.cpu.commit.function_calls 82 # Number of function calls committed. system.cpu.commit.bw_lim_events 122 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 23312 # The number of ROB reads -system.cpu.rob.rob_writes 23396 # The number of ROB writes -system.cpu.timesIdled 224 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 19450 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 23271 # The number of ROB reads +system.cpu.rob.rob_writes 23399 # The number of ROB writes +system.cpu.timesIdled 219 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 19705 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 4591 # Number of Instructions Simulated system.cpu.committedOps 5729 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 4591 # Number of Instructions Simulated -system.cpu.cpi 7.138968 # CPI: Cycles Per Instruction -system.cpu.cpi_total 7.138968 # CPI: Total CPI of All Threads -system.cpu.ipc 0.140076 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.140076 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 39187 # number of integer regfile reads -system.cpu.int_regfile_writes 7985 # number of integer regfile writes +system.cpu.cpi 7.185580 # CPI: Cycles Per Instruction +system.cpu.cpi_total 7.185580 # CPI: Total CPI of All Threads +system.cpu.ipc 0.139168 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.139168 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 39193 # number of integer regfile reads +system.cpu.int_regfile_writes 7983 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.misc_regfile_reads 2976 # number of misc regfile reads +system.cpu.misc_regfile_reads 2975 # number of misc regfile reads system.cpu.misc_regfile_writes 24 # number of misc regfile writes -system.cpu.toL2Bus.throughput 1706718740 # Throughput (bytes/s) +system.cpu.toL2Bus.throughput 1695646902 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 397 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 396 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 41 # Transaction distribution @@ -528,60 +528,60 @@ system.cpu.toL2Bus.data_through_bus 27968 # To system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 219000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.3 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 436500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 2.7 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 221495 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 485250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 2.9 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 231495 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.4 # Layer utilization (%) -system.cpu.icache.replacements 4 # number of replacements -system.cpu.icache.tagsinuse 145.578272 # Cycle average of tags in use -system.cpu.icache.total_refs 1578 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 291 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 5.422680 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 145.578272 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.071083 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.071083 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 1578 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1578 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1578 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1578 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1578 # number of overall hits -system.cpu.icache.overall_hits::total 1578 # number of overall hits +system.cpu.icache.tags.replacements 4 # number of replacements +system.cpu.icache.tags.tagsinuse 145.483199 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 1583 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 291 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 5.439863 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 145.483199 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.071037 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.071037 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 1583 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1583 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1583 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1583 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1583 # number of overall hits +system.cpu.icache.overall_hits::total 1583 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 364 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 364 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 364 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 364 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 364 # number of overall misses system.cpu.icache.overall_misses::total 364 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 22955000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 22955000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 22955000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 22955000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 22955000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 22955000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1942 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1942 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1942 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1942 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1942 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1942 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.187436 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.187436 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.187436 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.187436 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.187436 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.187436 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 63063.186813 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 63063.186813 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 63063.186813 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 63063.186813 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 63063.186813 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 63063.186813 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 121 # number of cycles access was blocked +system.cpu.icache.ReadReq_miss_latency::cpu.inst 23224750 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 23224750 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 23224750 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 23224750 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 23224750 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 23224750 # 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number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2490250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 14791750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7395750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 22187500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 14791750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7395750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 22187500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 14794250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4906250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 19700500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2492250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2492250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 14794250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7398500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 22192750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 14794250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7398500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 22192750 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.931271 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.764151 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.886650 # mshr miss rate for ReadReq accesses @@ -738,39 +738,39 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.897260 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.931271 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.829932 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.897260 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 54582.103321 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60561.728395 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55958.096591 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60737.804878 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60737.804878 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54582.103321 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60620.901639 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56456.743003 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54582.103321 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60620.901639 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56456.743003 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 54591.328413 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60570.987654 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55967.329545 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60786.585366 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60786.585366 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54591.328413 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60643.442623 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56470.101781 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54591.328413 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60643.442623 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56470.101781 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 85.937637 # Cycle average of tags in use -system.cpu.dcache.total_refs 2388 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 146 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 16.356164 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 85.937637 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.020981 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.020981 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 1760 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1760 # number of ReadReq hits +system.cpu.dcache.tags.replacements 0 # number of replacements +system.cpu.dcache.tags.tagsinuse 85.893510 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 2390 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 146 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 16.369863 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 85.893510 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.020970 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.020970 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 1763 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1763 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 606 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 606 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 11 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 11 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 10 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 10 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 2366 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2366 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2366 # number of overall hits -system.cpu.dcache.overall_hits::total 2366 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 2369 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2369 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2369 # number of overall hits +system.cpu.dcache.overall_hits::total 2369 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 190 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 190 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 307 # number of WriteReq misses @@ -781,53 +781,53 @@ system.cpu.dcache.demand_misses::cpu.data 497 # n system.cpu.dcache.demand_misses::total 497 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 497 # number of overall misses system.cpu.dcache.overall_misses::total 497 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 10638500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 10638500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 19663000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 19663000 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 127500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 127500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 30301500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 30301500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 30301500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 30301500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1950 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1950 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_miss_latency::cpu.data 10660493 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 10660493 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 19773250 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 19773250 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 130000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 130000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 30433743 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 30433743 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 30433743 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 30433743 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1953 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1953 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 13 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 13 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 12 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 12 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2863 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2863 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2863 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2863 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.097436 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.097436 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 2866 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2866 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2866 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2866 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.097286 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.097286 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.336254 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.336254 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.153846 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.153846 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.173594 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.173594 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.173594 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.173594 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55992.105263 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 55992.105263 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64048.859935 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 64048.859935 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 63750 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 63750 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 60968.812877 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 60968.812877 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 60968.812877 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 60968.812877 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 103 # number of cycles access was blocked +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.166667 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.166667 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.173412 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.173412 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.173412 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.173412 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56107.857895 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 56107.857895 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64407.980456 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 64407.980456 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 65000 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 65000 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 61234.895372 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 61234.895372 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 61234.895372 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 61234.895372 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 98 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 34.333333 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 32.666667 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed @@ -849,30 +849,30 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 147 system.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6438005 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 6438005 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3034500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3034500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9472505 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 9472505 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9472505 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 9472505 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.054359 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.054359 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6447755 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 6447755 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3039250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3039250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9487005 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 9487005 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9487005 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 9487005 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.054275 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.054275 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044907 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.044907 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.051345 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.051345 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.051345 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.051345 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 60735.896226 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 60735.896226 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74012.195122 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74012.195122 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 64438.809524 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 64438.809524 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 64438.809524 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 64438.809524 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.051291 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.051291 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.051291 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.051291 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 60827.877358 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 60827.877358 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74128.048780 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74128.048780 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 64537.448980 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 64537.448980 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 64537.448980 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 64537.448980 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt index 744017c0b..7a58b161f 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt @@ -107,15 +107,15 @@ system.cpu.num_idle_cycles 0 # Nu system.cpu.num_busy_cycles 51938 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.icache.replacements 1 # number of replacements -system.cpu.icache.tagsinuse 114.614391 # Cycle average of tags in use -system.cpu.icache.total_refs 4364 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 241 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 18.107884 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 114.614391 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.055964 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.055964 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 1 # number of replacements +system.cpu.icache.tags.tagsinuse 114.614391 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 4364 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 241 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 18.107884 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 114.614391 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.055964 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.055964 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 4364 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 4364 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 4364 # number of demand (read+write) hits @@ -185,17 +185,17 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 50211.618257 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50211.618257 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 50211.618257 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 154.071129 # Cycle average of tags in use -system.cpu.l2cache.total_refs 32 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 307 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.104235 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 105.889758 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 48.181371 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.003231 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.001470 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.004702 # Average percentage of cache occupancy +system.cpu.l2cache.tags.replacements 0 # number of replacements +system.cpu.l2cache.tags.tagsinuse 154.071129 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 32 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 307 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.104235 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::cpu.inst 105.889758 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 48.181371 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003231 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.001470 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.004702 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 16 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 16 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 32 # number of ReadReq hits @@ -313,15 +313,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 83.000387 # Cycle average of tags in use -system.cpu.dcache.total_refs 1940 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 141 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 13.758865 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 83.000387 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.020264 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.020264 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 0 # number of replacements +system.cpu.dcache.tags.tagsinuse 83.000387 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 1940 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 141 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 13.758865 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 83.000387 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.020264 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.020264 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 1048 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1048 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 870 # number of WriteReq hits diff --git a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt index 4cccc3a14..b2a150376 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000025 # Number of seconds simulated -sim_ticks 24539000 # Number of ticks simulated -final_tick 24539000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 24587000 # Number of ticks simulated +final_tick 24587000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 40560 # Simulator instruction rate (inst/s) -host_op_rate 40552 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 171130571 # Simulator tick rate (ticks/s) -host_mem_usage 226208 # Number of bytes of host memory used +host_inst_rate 41260 # Simulator instruction rate (inst/s) +host_op_rate 41253 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 174426700 # Simulator tick rate (ticks/s) +host_mem_usage 226212 # Number of bytes of host memory used host_seconds 0.14 # Real time elapsed on the host sim_insts 5814 # Number of instructions simulated sim_ops 5814 # Number of ops (including micro ops) simulated @@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 20288 # Nu system.physmem.num_reads::cpu.inst 317 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 138 # Number of read requests responded to by this memory system.physmem.num_reads::total 455 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 826765557 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 359916867 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1186682424 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 826765557 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 826765557 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 826765557 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 359916867 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1186682424 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 825151503 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 359214219 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1184365722 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 825151503 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 825151503 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 825151503 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 359214219 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1184365722 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 455 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen system.physmem.cpureqs 455 # Reqs generatd by CPU via cache - shady @@ -70,7 +70,7 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 24472000 # Total gap between requests +system.physmem.totGap 24519000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes @@ -169,28 +169,28 @@ system.physmem.bytesPerActivate::960 1 1.06% 97.87% # By system.physmem.bytesPerActivate::1024 1 1.06% 98.94% # Bytes accessed per row activation system.physmem.bytesPerActivate::2240 1 1.06% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 94 # Bytes accessed per row activation -system.physmem.totQLat 2632000 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 13115750 # Sum of mem lat for all requests +system.physmem.totQLat 2305250 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 12775250 # Sum of mem lat for all requests system.physmem.totBusLat 2275000 # Total cycles spent in databus access -system.physmem.totBankLat 8208750 # Total cycles spent in bank access -system.physmem.avgQLat 5784.62 # Average queueing delay per request -system.physmem.avgBankLat 18041.21 # Average bank access latency per request +system.physmem.totBankLat 8195000 # Total cycles spent in bank access +system.physmem.avgQLat 5066.48 # Average queueing delay per request +system.physmem.avgBankLat 18010.99 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 28825.82 # Average memory access latency -system.physmem.avgRdBW 1186.68 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 28077.47 # Average memory access latency +system.physmem.avgRdBW 1184.37 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 1186.68 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 1184.37 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 9.27 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.53 # Average read queue length over time +system.physmem.busUtil 9.25 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.52 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time system.physmem.readRowHits 361 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 79.34 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 53784.62 # Average gap between requests -system.membus.throughput 1186682424 # Throughput (bytes/s) +system.physmem.avgGap 53887.91 # Average gap between requests +system.membus.throughput 1184365722 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 404 # Transaction distribution system.membus.trans_dist::ReadResp 404 # Transaction distribution system.membus.trans_dist::ReadExReq 51 # Transaction distribution @@ -201,9 +201,9 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 29120 system.membus.tot_pkt_size 29120 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 29120 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 551000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 551500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 4265750 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 4266000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 17.4 # Layer utilization (%) system.cpu.branchPred.lookups 1157 # Number of BP lookups system.cpu.branchPred.condPredicted 861 # Number of conditional branches predicted @@ -233,7 +233,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 8 # Number of system calls -system.cpu.numCycles 49079 # number of cpu cycles simulated +system.cpu.numCycles 49175 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.branch_predictor.predictedTaken 432 # Number of Branches Predicted As Taken (True). @@ -255,12 +255,12 @@ system.cpu.execution_unit.executions 3133 # Nu system.cpu.mult_div_unit.multiplies 3 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 1 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 9516 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 9486 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 488 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 43696 # Number of cycles cpu's stages were not processed +system.cpu.timesIdled 462 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 43792 # Number of cycles cpu's stages were not processed system.cpu.runCycles 5383 # Number of cycles cpu stages are processed. -system.cpu.activity 10.968031 # Percentage of cycles cpu is active +system.cpu.activity 10.946619 # Percentage of cycles cpu is active system.cpu.comLoads 1163 # Number of Load instructions committed system.cpu.comStores 925 # Number of Store instructions committed system.cpu.comBranches 915 # Number of Branches instructions committed @@ -272,36 +272,36 @@ system.cpu.committedInsts 5814 # Nu system.cpu.committedOps 5814 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 5814 # Number of Instructions committed (Total) -system.cpu.cpi 8.441520 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 8.458032 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 8.441520 # CPI: Total CPI of All Threads -system.cpu.ipc 0.118462 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 8.458032 # CPI: Total CPI of All Threads +system.cpu.ipc 0.118231 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 0.118462 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 45429 # Number of cycles 0 instructions are processed. +system.cpu.ipc_total 0.118231 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 45525 # Number of cycles 0 instructions are processed. system.cpu.stage0.runCycles 3650 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 7.436989 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 46265 # Number of cycles 0 instructions are processed. +system.cpu.stage0.utilization 7.422471 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 46361 # Number of cycles 0 instructions are processed. system.cpu.stage1.runCycles 2814 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 5.733613 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 46314 # Number of cycles 0 instructions are processed. +system.cpu.stage1.utilization 5.722420 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 46410 # Number of cycles 0 instructions are processed. system.cpu.stage2.runCycles 2765 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 5.633774 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 47841 # Number of cycles 0 instructions are processed. +system.cpu.stage2.utilization 5.622776 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 47937 # Number of cycles 0 instructions are processed. system.cpu.stage3.runCycles 1238 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 2.522464 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 46189 # Number of cycles 0 instructions are processed. +system.cpu.stage3.utilization 2.517539 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 46285 # Number of cycles 0 instructions are processed. system.cpu.stage4.runCycles 2890 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 5.888466 # Percentage of cycles stage was utilized (processing insts). -system.cpu.icache.replacements 13 # number of replacements -system.cpu.icache.tagsinuse 150.599216 # Cycle average of tags in use -system.cpu.icache.total_refs 428 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 319 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 1.341693 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 150.599216 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.073535 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.073535 # Average percentage of cache occupancy +system.cpu.stage4.utilization 5.876970 # Percentage of cycles stage was utilized (processing insts). +system.cpu.icache.tags.replacements 13 # number of replacements +system.cpu.icache.tags.tagsinuse 150.350232 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 428 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 319 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 1.341693 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 150.350232 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.073413 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.073413 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 428 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 428 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 428 # number of demand (read+write) hits @@ -314,12 +314,12 @@ system.cpu.icache.demand_misses::cpu.inst 350 # n system.cpu.icache.demand_misses::total 350 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 350 # number of overall misses system.cpu.icache.overall_misses::total 350 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 25149500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 25149500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 25149500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 25149500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 25149500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 25149500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 25010250 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 25010250 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 25010250 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 25010250 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 25010250 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 25010250 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 778 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 778 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 778 # number of demand (read+write) accesses @@ -332,12 +332,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.449871 system.cpu.icache.demand_miss_rate::total 0.449871 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.449871 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.449871 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 71855.714286 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 71855.714286 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 71855.714286 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 71855.714286 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 71855.714286 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 71855.714286 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 71457.857143 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 71457.857143 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 71457.857143 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 71457.857143 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 71457.857143 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 71457.857143 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -358,26 +358,26 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 319 system.cpu.icache.demand_mshr_misses::total 319 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 319 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 319 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22969000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 22969000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22969000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 22969000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22969000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 22969000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22679000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 22679000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22679000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 22679000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22679000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 22679000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.410026 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.410026 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.410026 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.410026 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.410026 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.410026 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 72003.134796 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 72003.134796 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 72003.134796 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 72003.134796 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 72003.134796 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 72003.134796 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 71094.043887 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 71094.043887 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 71094.043887 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 71094.043887 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 71094.043887 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 71094.043887 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 1191898610 # Throughput (bytes/s) +system.cpu.toL2Bus.throughput 1189571725 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 406 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 406 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 51 # Transaction distribution @@ -392,21 +392,21 @@ system.cpu.toL2Bus.data_through_bus 29248 # To system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 228500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.9 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 478500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 1.9 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 207000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) -system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 208.333773 # Cycle average of tags in use -system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 404 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.004950 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 152.278645 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 56.055128 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.004647 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.001711 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.006358 # Average percentage of cache occupancy +system.cpu.toL2Bus.respLayer0.occupancy 543000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 2.2 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 228000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) +system.cpu.l2cache.tags.replacements 0 # number of replacements +system.cpu.l2cache.tags.tagsinuse 208.008874 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 404 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.004950 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::cpu.inst 152.043119 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 55.965756 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004640 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.001708 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.006348 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits @@ -424,17 +424,17 @@ system.cpu.l2cache.demand_misses::total 455 # nu system.cpu.l2cache.overall_misses::cpu.inst 317 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 138 # number of overall misses system.cpu.l2cache.overall_misses::total 455 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 22623500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 6716000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 29339500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3640500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 3640500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 22623500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 10356500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 32980000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 22623500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 10356500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 32980000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 22333500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 6742000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 29075500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3650000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 3650000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 22333500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 10392000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 32725500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 22333500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 10392000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 32725500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 319 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 87 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 406 # number of ReadReq accesses(hits+misses) @@ -457,17 +457,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.995624 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993730 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.995624 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71367.507886 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 77195.402299 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 72622.524752 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 71382.352941 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71382.352941 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71367.507886 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75047.101449 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 72483.516484 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71367.507886 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75047.101449 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 72483.516484 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70452.681388 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 77494.252874 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 71969.059406 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 71568.627451 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71568.627451 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70452.681388 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75304.347826 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 71924.175824 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70452.681388 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75304.347826 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 71924.175824 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -487,17 +487,17 @@ system.cpu.l2cache.demand_mshr_misses::total 455 system.cpu.l2cache.overall_mshr_misses::cpu.inst 317 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 455 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 18696000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 5647250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 24343250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 18342000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 5661000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 24003000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3006000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3006000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 18696000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8653250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 27349250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 18696000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8653250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 27349250 # number of overall MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 18342000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8667000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 27009000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 18342000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8667000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 27009000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993730 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.995074 # mshr miss rate for ReadReq accesses @@ -509,51 +509,51 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.995624 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993730 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.995624 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58977.917981 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64910.919540 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60255.569307 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57861.198738 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 65068.965517 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59413.366337 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58941.176471 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58941.176471 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58977.917981 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62704.710145 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60108.241758 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58977.917981 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62704.710145 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60108.241758 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57861.198738 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62804.347826 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59360.439560 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57861.198738 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62804.347826 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59360.439560 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 90.129103 # Cycle average of tags in use -system.cpu.dcache.total_refs 1637 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 138 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 11.862319 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 90.129103 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.022004 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.022004 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 1065 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1065 # number of ReadReq hits +system.cpu.dcache.tags.replacements 0 # number of replacements +system.cpu.dcache.tags.tagsinuse 89.984709 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 1638 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 138 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 11.869565 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 89.984709 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.021969 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.021969 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 1066 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1066 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 572 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 572 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 1637 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 1637 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 1637 # number of overall hits -system.cpu.dcache.overall_hits::total 1637 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 98 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 98 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 1638 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 1638 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 1638 # number of overall hits +system.cpu.dcache.overall_hits::total 1638 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 97 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 97 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 353 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 353 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 451 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 451 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 451 # number of overall misses -system.cpu.dcache.overall_misses::total 451 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 7478500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 7478500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 21383500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 21383500 # 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number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 29113750 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 29113750 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 29113750 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 29113750 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 1163 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1163 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 925 # number of WriteReq accesses(hits+misses) @@ -562,38 +562,38 @@ system.cpu.dcache.demand_accesses::cpu.data 2088 # system.cpu.dcache.demand_accesses::total 2088 # number of demand (read+write) accesses system.cpu.dcache.overall_accesses::cpu.data 2088 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 2088 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.084265 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.084265 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.083405 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.083405 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.381622 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.381622 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.215996 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.215996 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.215996 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.215996 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 76311.224490 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 76311.224490 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60576.487252 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 60576.487252 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 63995.565410 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 63995.565410 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 63995.565410 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 63995.565410 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 253 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.215517 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.215517 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.215517 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.215517 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 77556.701031 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 77556.701031 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61163.597734 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 61163.597734 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 64697.222222 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 64697.222222 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 64697.222222 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 64697.222222 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 265 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 13 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 19.461538 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 20.384615 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 11 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 11 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 10 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 10 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 302 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 302 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 313 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 313 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 313 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 313 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 312 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 312 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 312 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 312 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 87 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 87 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 51 # number of WriteReq MSHR misses @@ -602,14 +602,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 138 system.cpu.dcache.demand_mshr_misses::total 138 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 138 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6809500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 6809500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3694500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3694500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10504000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 10504000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10504000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 10504000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6835500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 6835500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3704000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3704000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10539500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 10539500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10539500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 10539500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.074807 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.074807 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055135 # mshr miss rate for WriteReq accesses @@ -618,14 +618,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.066092 system.cpu.dcache.demand_mshr_miss_rate::total 0.066092 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.066092 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.066092 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78270.114943 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78270.114943 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 72441.176471 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 72441.176471 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76115.942029 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 76115.942029 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76115.942029 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 76115.942029 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78568.965517 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78568.965517 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 72627.450980 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 72627.450980 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76373.188406 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 76373.188406 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76373.188406 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 76373.188406 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt index 37ca97b46..6a930873f 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt @@ -1,38 +1,38 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000022 # Number of seconds simulated -sim_ticks 21759500 # Number of ticks simulated -final_tick 21759500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 21805500 # Number of ticks simulated +final_tick 21805500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 43168 # Simulator instruction rate (inst/s) -host_op_rate 43158 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 182102261 # Simulator tick rate (ticks/s) -host_mem_usage 228268 # Number of bytes of host memory used -host_seconds 0.12 # Real time elapsed on the host +host_inst_rate 79844 # Simulator instruction rate (inst/s) +host_op_rate 79828 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 337538221 # Simulator tick rate (ticks/s) +host_mem_usage 228256 # Number of bytes of host memory used +host_seconds 0.06 # Real time elapsed on the host sim_insts 5156 # Number of instructions simulated sim_ops 5156 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 21504 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 21440 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 9088 # Number of bytes read from this memory -system.physmem.bytes_read::total 30592 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 21504 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 21504 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 336 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 30528 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 21440 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 21440 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 335 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 142 # Number of read requests responded to by this memory -system.physmem.num_reads::total 478 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 988258002 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 417656656 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1405914658 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 988258002 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 988258002 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 988258002 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 417656656 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1405914658 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 478 # Total number of read requests seen +system.physmem.num_reads::total 477 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 983238174 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 416775584 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1400013758 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 983238174 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 983238174 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 983238174 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 416775584 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1400013758 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 477 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen -system.physmem.cpureqs 478 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 30592 # Total number of bytes read from memory +system.physmem.cpureqs 477 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 30528 # Total number of bytes read from memory system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 30592 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedRd 30528 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed @@ -44,7 +44,7 @@ system.physmem.perBankRdReqs::4 7 # Tr system.physmem.perBankRdReqs::5 3 # Track reads on a per bank basis system.physmem.perBankRdReqs::6 13 # Track reads on a per bank basis system.physmem.perBankRdReqs::7 54 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 64 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 63 # Track reads on a per bank basis system.physmem.perBankRdReqs::9 77 # Track reads on a per bank basis system.physmem.perBankRdReqs::10 44 # Track reads on a per bank basis system.physmem.perBankRdReqs::11 20 # Track reads on a per bank basis @@ -70,14 +70,14 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 21680500 # Total gap between requests +system.physmem.totGap 21726000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 478 # Categorize read packet sizes +system.physmem.readPktSize::6 477 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes @@ -85,9 +85,9 @@ system.physmem.writePktSize::3 0 # Ca system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes system.physmem.writePktSize::6 0 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 284 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 132 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 43 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 283 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 133 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 42 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 16 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -150,16 +150,16 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.bytesPerActivate::samples 103 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 242.330097 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 156.624939 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 303.862985 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 241.708738 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 156.390708 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 303.503517 # Bytes accessed per row activation system.physmem.bytesPerActivate::64 39 37.86% 37.86% # Bytes accessed per row activation system.physmem.bytesPerActivate::128 15 14.56% 52.43% # Bytes accessed per row activation system.physmem.bytesPerActivate::192 16 15.53% 67.96% # Bytes accessed per row activation system.physmem.bytesPerActivate::256 7 6.80% 74.76% # Bytes accessed per row activation system.physmem.bytesPerActivate::320 8 7.77% 82.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384 2 1.94% 84.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448 4 3.88% 88.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384 3 2.91% 85.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448 3 2.91% 88.35% # Bytes accessed per row activation system.physmem.bytesPerActivate::512 1 0.97% 89.32% # Bytes accessed per row activation system.physmem.bytesPerActivate::576 4 3.88% 93.20% # Bytes accessed per row activation system.physmem.bytesPerActivate::704 1 0.97% 94.17% # Bytes accessed per row activation @@ -168,51 +168,51 @@ system.physmem.bytesPerActivate::960 1 0.97% 97.09% # By system.physmem.bytesPerActivate::1024 2 1.94% 99.03% # Bytes accessed per row activation system.physmem.bytesPerActivate::2368 1 0.97% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 103 # Bytes accessed per row activation -system.physmem.totQLat 2435500 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 13501750 # Sum of mem lat for all requests -system.physmem.totBusLat 2390000 # Total cycles spent in databus access +system.physmem.totQLat 2353250 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 13414500 # Sum of mem lat for all requests +system.physmem.totBusLat 2385000 # Total cycles spent in databus access system.physmem.totBankLat 8676250 # Total cycles spent in bank access -system.physmem.avgQLat 5095.19 # Average queueing delay per request -system.physmem.avgBankLat 18151.15 # Average bank access latency per request +system.physmem.avgQLat 4933.44 # Average queueing delay per request +system.physmem.avgBankLat 18189.20 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 28246.34 # Average memory access latency -system.physmem.avgRdBW 1405.91 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 28122.64 # Average memory access latency +system.physmem.avgRdBW 1400.01 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 1405.91 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 1400.01 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 10.98 # Data bus utilization in percentage +system.physmem.busUtil 10.94 # Data bus utilization in percentage system.physmem.avgRdQLen 0.62 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 375 # Number of row buffer hits during reads +system.physmem.readRowHits 374 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 78.45 # Row buffer hit rate for reads +system.physmem.readRowHitRate 78.41 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 45356.69 # Average gap between requests -system.membus.throughput 1405914658 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 427 # Transaction distribution -system.membus.trans_dist::ReadResp 427 # Transaction distribution +system.physmem.avgGap 45547.17 # Average gap between requests +system.membus.throughput 1400013758 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 426 # Transaction distribution +system.membus.trans_dist::ReadResp 426 # Transaction distribution system.membus.trans_dist::ReadExReq 51 # Transaction distribution system.membus.trans_dist::ReadExResp 51 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side 956 # Packet count per connected master and slave (bytes) -system.membus.pkt_count 956 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 30592 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size 30592 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 30592 # Total data (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side 954 # Packet count per connected master and slave (bytes) +system.membus.pkt_count 954 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 30528 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size 30528 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 30528 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 590000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 2.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 4475750 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 20.6 # Layer utilization (%) -system.cpu.branchPred.lookups 2196 # Number of BP lookups -system.cpu.branchPred.condPredicted 1494 # Number of conditional branches predicted +system.membus.reqLayer0.occupancy 605000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 2.8 # Layer utilization (%) +system.membus.respLayer1.occupancy 4480000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 20.5 # Layer utilization (%) +system.cpu.branchPred.lookups 2187 # Number of BP lookups +system.cpu.branchPred.condPredicted 1490 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 438 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 1671 # Number of BTB lookups -system.cpu.branchPred.BTBHits 505 # Number of BTB hits +system.cpu.branchPred.BTBLookups 1664 # Number of BTB lookups +system.cpu.branchPred.BTBHits 502 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 30.221424 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 262 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 68 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 30.168269 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 261 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 67 # Number of incorrect RAS predictions. system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses system.cpu.dtb.read_accesses 0 # DTB read accesses @@ -232,132 +232,132 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 8 # Number of system calls -system.cpu.numCycles 43520 # number of cpu cycles simulated +system.cpu.numCycles 43612 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 8865 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 13232 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2196 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 767 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 3240 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1388 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 1327 # Number of cycles fetch has spent blocked +system.cpu.fetch.icacheStallCycles 8859 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 13212 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2187 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 763 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 3230 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1384 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 1326 # Number of cycles fetch has spent blocked system.cpu.fetch.PendingTrapStallCycles 143 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 1994 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 285 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 14495 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.912867 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.222713 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 1985 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 280 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 14475 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.912746 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.223376 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 11255 77.65% 77.65% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1338 9.23% 86.88% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 11245 77.69% 77.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1331 9.20% 86.88% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::2 104 0.72% 87.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 132 0.91% 88.51% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 307 2.12% 90.62% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 118 0.81% 91.44% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 149 1.03% 92.47% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 158 1.09% 93.56% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 934 6.44% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 131 0.91% 88.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 305 2.11% 90.61% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 118 0.82% 91.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 150 1.04% 92.46% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 158 1.09% 93.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 933 6.45% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 14495 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.050460 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.304044 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 8953 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 1558 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 3054 # Number of cycles decode is running +system.cpu.fetch.rateDist::total 14475 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.050147 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.302944 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 8926 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 1578 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 3043 # Number of cycles decode is running system.cpu.decode.UnblockCycles 53 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 877 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 168 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 44 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 12351 # Number of instructions handled by decode +system.cpu.decode.SquashCycles 875 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 167 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 43 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 12329 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 174 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 877 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 9138 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 511 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 897 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2924 # Number of cycles rename is running +system.cpu.rename.SquashCycles 875 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 9108 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 527 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 901 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 2916 # Number of cycles rename is running system.cpu.rename.UnblockCycles 148 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 11915 # Number of instructions processed by rename +system.cpu.rename.RenamedInsts 11899 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 7 # Number of times rename has blocked due to ROB full system.cpu.rename.IQFullEvents 6 # Number of times rename has blocked due to IQ full system.cpu.rename.LSQFullEvents 124 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 7195 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 14132 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 14128 # Number of integer rename lookups +system.cpu.rename.RenamedOperands 7186 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 14116 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 14112 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 4 # Number of floating rename lookups system.cpu.rename.CommittedMaps 3398 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 3797 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 17 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 11 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 333 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2463 # Number of loads inserted to the mem dependence unit. +system.cpu.rename.UndoneMaps 3788 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 16 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 10 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 328 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2460 # Number of loads inserted to the mem dependence unit. system.cpu.memDep0.insertedStores 1193 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 1 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 1 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 9245 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 9226 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 12 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 8313 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 42 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 3584 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 2108 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 8306 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 39 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 3428 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 2082 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 14495 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.573508 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.239818 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 14475 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.573817 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.241522 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 10895 75.16% 75.16% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1434 9.89% 85.06% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 892 6.15% 91.21% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 557 3.84% 95.05% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 358 2.47% 97.52% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 226 1.56% 99.08% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 86 0.59% 99.68% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 30 0.21% 99.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 10881 75.17% 75.17% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1431 9.89% 85.06% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 893 6.17% 91.23% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 553 3.82% 95.05% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 356 2.46% 97.51% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 225 1.55% 99.06% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 88 0.61% 99.67% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 31 0.21% 99.88% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 17 0.12% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 14495 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 14475 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 5 3.14% 3.14% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 3.14% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 3.14% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.14% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.14% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.14% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 3.14% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.14% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 3.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 3.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.14% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 100 62.89% 66.04% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 54 33.96% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 5 3.12% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 101 63.12% 66.25% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 54 33.75% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 4947 59.51% 59.51% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 4943 59.51% 59.51% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 5 0.06% 59.57% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 2 0.02% 59.59% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 2 0.02% 59.60% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 59.62% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 59.62% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 59.62% # Type of FU issued @@ -384,84 +384,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.62% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.62% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.62% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.62% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2253 27.10% 86.72% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1104 13.28% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2250 27.09% 86.71% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1104 13.29% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 8313 # Type of FU issued -system.cpu.iq.rate 0.191016 # Inst issue rate -system.cpu.iq.fu_busy_cnt 159 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.019127 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 31318 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 12850 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 7467 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 8306 # Type of FU issued +system.cpu.iq.rate 0.190452 # Inst issue rate +system.cpu.iq.fu_busy_cnt 160 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.019263 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 31282 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 12675 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 7463 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 4 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 2 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 2 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 8470 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 8464 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 2 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 69 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1300 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1297 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 12 # Number of memory ordering violations system.cpu.iew.lsq.thread0.squashedStores 268 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 38 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 35 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 877 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 334 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 17 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 10786 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 86 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2463 # Number of dispatched load instructions +system.cpu.iew.iewSquashCycles 875 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 349 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 16 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 10763 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 93 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2460 # Number of dispatched load instructions system.cpu.iew.iewDispStoreInsts 1193 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 12 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 2 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewIQFullEvents 1 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 12 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 102 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 359 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 461 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 7936 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 2118 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 377 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedTakenIncorrect 101 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 362 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 463 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 7925 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 2110 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 381 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1529 # number of nop insts executed -system.cpu.iew.exec_refs 3196 # number of memory reference insts executed -system.cpu.iew.exec_branches 1356 # Number of branches executed -system.cpu.iew.exec_stores 1078 # Number of stores executed -system.cpu.iew.exec_rate 0.182353 # Inst execution rate -system.cpu.iew.wb_sent 7562 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 7469 # cumulative count of insts written-back -system.cpu.iew.wb_producers 2922 # num instructions producing a value -system.cpu.iew.wb_consumers 4200 # num instructions consuming a value +system.cpu.iew.exec_nop 1525 # number of nop insts executed +system.cpu.iew.exec_refs 3189 # number of memory reference insts executed +system.cpu.iew.exec_branches 1354 # Number of branches executed +system.cpu.iew.exec_stores 1079 # Number of stores executed +system.cpu.iew.exec_rate 0.181716 # Inst execution rate +system.cpu.iew.wb_sent 7555 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 7465 # cumulative count of insts written-back +system.cpu.iew.wb_producers 2921 # num instructions producing a value +system.cpu.iew.wb_consumers 4197 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.171622 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.695714 # average fanout of values written-back +system.cpu.iew.wb_rate 0.171168 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.695973 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 4965 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 4943 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 10 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 395 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 13618 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.426862 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.205287 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 396 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 13600 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.427426 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.207995 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 11210 82.32% 82.32% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1002 7.36% 89.68% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 633 4.65% 94.32% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 319 2.34% 96.67% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 147 1.08% 97.75% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 94 0.69% 98.44% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 67 0.49% 98.93% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 40 0.29% 99.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 11198 82.34% 82.34% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 999 7.35% 89.68% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 630 4.63% 94.32% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 315 2.32% 96.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 149 1.10% 97.73% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 94 0.69% 98.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 68 0.50% 98.92% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 41 0.30% 99.22% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::8 106 0.78% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 13618 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 13600 # Number of insts commited each cycle system.cpu.commit.committedInsts 5813 # Number of instructions committed system.cpu.commit.committedOps 5813 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -474,197 +474,197 @@ system.cpu.commit.int_insts 5111 # Nu system.cpu.commit.function_calls 87 # Number of function calls committed. system.cpu.commit.bw_lim_events 106 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 24277 # The number of ROB reads -system.cpu.rob.rob_writes 22442 # The number of ROB writes -system.cpu.timesIdled 289 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 29025 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 24237 # The number of ROB reads +system.cpu.rob.rob_writes 22398 # The number of ROB writes +system.cpu.timesIdled 285 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 29137 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 5156 # Number of Instructions Simulated system.cpu.committedOps 5156 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 5156 # Number of Instructions Simulated -system.cpu.cpi 8.440652 # CPI: Cycles Per Instruction -system.cpu.cpi_total 8.440652 # CPI: Total CPI of All Threads -system.cpu.ipc 0.118474 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.118474 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 10757 # number of integer regfile reads -system.cpu.int_regfile_writes 5239 # number of integer regfile writes +system.cpu.cpi 8.458495 # CPI: Cycles Per Instruction +system.cpu.cpi_total 8.458495 # CPI: Total CPI of All Threads +system.cpu.ipc 0.118224 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.118224 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 10746 # number of integer regfile reads +system.cpu.int_regfile_writes 5233 # number of integer regfile writes system.cpu.fp_regfile_reads 3 # number of floating regfile reads system.cpu.fp_regfile_writes 1 # number of floating regfile writes system.cpu.misc_regfile_reads 148 # number of misc regfile reads -system.cpu.toL2Bus.throughput 1414738390 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 430 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 430 # Transaction distribution +system.cpu.toL2Bus.throughput 1408818876 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 429 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 429 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 51 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 51 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 678 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 676 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 284 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count 962 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 21696 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count 960 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 21632 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 9088 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size 30784 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 30784 # Total data (bytes) +system.cpu.toL2Bus.tot_pkt_size 30720 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 30720 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 240500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.occupancy 240000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 508500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 2.3 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 213000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%) -system.cpu.icache.replacements 17 # number of replacements -system.cpu.icache.tagsinuse 161.130962 # Cycle average of tags in use -system.cpu.icache.total_refs 1541 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 339 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 4.545723 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 161.130962 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.078677 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.078677 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 1541 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1541 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1541 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1541 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1541 # number of overall hits -system.cpu.icache.overall_hits::total 1541 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 453 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 453 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 453 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 453 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 453 # number of overall misses -system.cpu.icache.overall_misses::total 453 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 30806000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 30806000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 30806000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 30806000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 30806000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 30806000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1994 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1994 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1994 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1994 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1994 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1994 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.227182 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.227182 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.227182 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.227182 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.227182 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.227182 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68004.415011 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 68004.415011 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 68004.415011 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 68004.415011 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 68004.415011 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 68004.415011 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 46 # number of cycles access was blocked +system.cpu.toL2Bus.respLayer0.occupancy 573500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 2.6 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 230000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 1.1 # Layer utilization (%) +system.cpu.icache.tags.replacements 17 # number of replacements +system.cpu.icache.tags.tagsinuse 160.845390 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 1531 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 338 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 4.529586 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 160.845390 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.078538 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.078538 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 1531 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1531 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1531 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1531 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1531 # number of overall hits +system.cpu.icache.overall_hits::total 1531 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 454 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 454 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 454 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 454 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 454 # number of overall misses +system.cpu.icache.overall_misses::total 454 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 31019250 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 31019250 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 31019250 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 31019250 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 31019250 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 31019250 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1985 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1985 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1985 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1985 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1985 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1985 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.228715 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.228715 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.228715 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.228715 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.228715 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.228715 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68324.339207 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 68324.339207 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 68324.339207 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 68324.339207 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 68324.339207 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 68324.339207 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 47 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 46 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 47 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 114 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 114 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 114 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 114 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 114 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 114 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 339 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 339 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 339 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 339 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 339 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 339 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23945500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 23945500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23945500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 23945500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23945500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 23945500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.170010 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.170010 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.170010 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.170010 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.170010 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.170010 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 70635.693215 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 70635.693215 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 70635.693215 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 70635.693215 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 70635.693215 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 70635.693215 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 116 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 116 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 116 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 116 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 116 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 116 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 338 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 338 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 338 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 338 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 338 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 338 # 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number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 511 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 511 # number of overall misses -system.cpu.dcache.overall_misses::total 511 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 10242000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 10242000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 22669999 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 22669999 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 32911999 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 32911999 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 32911999 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 32911999 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1986 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1986 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 510 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 510 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 510 # number of overall misses +system.cpu.dcache.overall_misses::total 510 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 10243000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 10243000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 22828749 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 22828749 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 33071749 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 33071749 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 33071749 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 33071749 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1980 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1980 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 925 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 925 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2911 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2911 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2911 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2911 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.075025 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.075025 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 2905 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2905 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2905 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2905 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.074747 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.074747 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.391351 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.391351 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.175541 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.175541 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.175541 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.175541 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 68738.255034 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 68738.255034 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62624.306630 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 62624.306630 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 64407.043053 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 64407.043053 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 64407.043053 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 64407.043053 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 642 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.175559 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.175559 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.175559 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.175559 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 69209.459459 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 69209.459459 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63062.842541 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 63062.842541 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 64846.566667 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 64846.566667 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 64846.566667 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 64846.566667 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 635 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 11 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 58.363636 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 57.727273 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 58 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 58 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 57 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 57 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 311 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 311 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 369 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 369 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 369 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 369 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 368 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 368 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 368 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 368 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 91 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 91 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 51 # number of WriteReq MSHR misses @@ -799,30 +799,30 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 142 system.cpu.dcache.demand_mshr_misses::total 142 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 142 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 142 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7164000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 7164000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3895999 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3895999 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11059999 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 11059999 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11059999 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 11059999 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.045821 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.045821 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7196250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 7196250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3914249 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3914249 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11110499 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 11110499 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11110499 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 11110499 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.045960 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.045960 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055135 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.055135 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.048780 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.048780 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.048780 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.048780 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78725.274725 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78725.274725 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76392.137255 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76392.137255 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 77887.316901 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 77887.316901 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 77887.316901 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 77887.316901 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.048881 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.048881 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.048881 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.048881 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 79079.670330 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 79079.670330 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76749.980392 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76749.980392 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 78242.950704 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 78242.950704 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78242.950704 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 78242.950704 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt index 0d57ed336..bfb8470a6 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt @@ -83,15 +83,15 @@ system.cpu.num_idle_cycles 0 # Nu system.cpu.num_busy_cycles 63266 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.icache.replacements 13 # number of replacements -system.cpu.icache.tagsinuse 132.545353 # Cycle average of tags in use -system.cpu.icache.total_refs 5513 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 303 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 18.194719 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 132.545353 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.064719 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.064719 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 13 # number of replacements +system.cpu.icache.tags.tagsinuse 132.545353 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 5513 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 303 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 18.194719 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 132.545353 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.064719 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.064719 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 5513 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 5513 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 5513 # number of demand (read+write) hits @@ -161,17 +161,17 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 52722.772277 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52722.772277 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 52722.772277 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 188.114191 # Cycle average of tags in use -system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 388 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.005155 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 133.890657 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 54.223533 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.004086 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.001655 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.005741 # Average percentage of cache occupancy +system.cpu.l2cache.tags.replacements 0 # number of replacements +system.cpu.l2cache.tags.tagsinuse 188.114191 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 388 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.005155 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::cpu.inst 133.890657 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 54.223533 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004086 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.001655 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.005741 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits @@ -286,15 +286,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 87.492114 # Cycle average of tags in use -system.cpu.dcache.total_refs 1950 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 138 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 14.130435 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 87.492114 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.021360 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.021360 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 0 # number of replacements +system.cpu.dcache.tags.tagsinuse 87.492114 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 1950 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 138 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 14.130435 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 87.492114 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.021360 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.021360 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 1076 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1076 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 874 # number of WriteReq hits diff --git a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt index 43017685d..50311c18c 100644 --- a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000018 # Number of seconds simulated -sim_ticks 18326500 # Number of ticks simulated -final_tick 18326500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 18469500 # Number of ticks simulated +final_tick 18469500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 41507 # Simulator instruction rate (inst/s) -host_op_rate 41499 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 131284333 # Simulator tick rate (ticks/s) -host_mem_usage 224304 # Number of bytes of host memory used -host_seconds 0.14 # Real time elapsed on the host +host_inst_rate 54927 # Simulator instruction rate (inst/s) +host_op_rate 54916 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 175080000 # Simulator tick rate (ticks/s) +host_mem_usage 224296 # Number of bytes of host memory used +host_seconds 0.11 # Real time elapsed on the host sim_insts 5792 # Number of instructions simulated sim_ops 5792 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 22080 # Number of bytes read from this memory @@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 22080 # Nu system.physmem.num_reads::cpu.inst 345 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 101 # Number of read requests responded to by this memory system.physmem.num_reads::total 446 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1204812703 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 352713284 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1557525987 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1204812703 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1204812703 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1204812703 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 352713284 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1557525987 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1195484447 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 349982403 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1545466851 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1195484447 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1195484447 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1195484447 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 349982403 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1545466851 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 446 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen system.physmem.cpureqs 446 # Reqs generatd by CPU via cache - shady @@ -70,7 +70,7 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 18199000 # Total gap between requests +system.physmem.totGap 18341000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes @@ -169,28 +169,28 @@ system.physmem.bytesPerActivate::1920 1 1.52% 96.97% # By system.physmem.bytesPerActivate::1984 1 1.52% 98.48% # Bytes accessed per row activation system.physmem.bytesPerActivate::2304 1 1.52% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 66 # Bytes accessed per row activation -system.physmem.totQLat 2004500 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 10972000 # Sum of mem lat for all requests +system.physmem.totQLat 1996500 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 10991500 # Sum of mem lat for all requests system.physmem.totBusLat 2230000 # Total cycles spent in databus access -system.physmem.totBankLat 6737500 # Total cycles spent in bank access -system.physmem.avgQLat 4494.39 # Average queueing delay per request -system.physmem.avgBankLat 15106.50 # Average bank access latency per request +system.physmem.totBankLat 6765000 # Total cycles spent in bank access +system.physmem.avgQLat 4476.46 # Average queueing delay per request +system.physmem.avgBankLat 15168.16 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 24600.90 # Average memory access latency -system.physmem.avgRdBW 1557.53 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 24644.62 # Average memory access latency +system.physmem.avgRdBW 1545.47 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 1557.53 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 1545.47 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 12.17 # Data bus utilization in percentage +system.physmem.busUtil 12.07 # Data bus utilization in percentage system.physmem.avgRdQLen 0.60 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time system.physmem.readRowHits 380 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 85.20 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 40804.93 # Average gap between requests -system.membus.throughput 1557525987 # Throughput (bytes/s) +system.physmem.avgGap 41123.32 # Average gap between requests +system.membus.throughput 1545466851 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 399 # Transaction distribution system.membus.trans_dist::ReadResp 399 # Transaction distribution system.membus.trans_dist::ReadExReq 47 # Transaction distribution @@ -201,10 +201,10 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 28544 system.membus.tot_pkt_size 28544 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 28544 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 559500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 565000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 3.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 4174500 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 22.8 # Layer utilization (%) +system.membus.respLayer1.occupancy 4183750 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 22.7 # Layer utilization (%) system.cpu.branchPred.lookups 2238 # Number of BP lookups system.cpu.branchPred.condPredicted 1804 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 419 # Number of conditional branches incorrect @@ -233,92 +233,92 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 9 # Number of system calls -system.cpu.numCycles 36654 # number of cpu cycles simulated +system.cpu.numCycles 36940 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 7507 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 13158 # Number of instructions fetch has processed +system.cpu.fetch.icacheStallCycles 7468 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 13161 # Number of instructions fetch has processed system.cpu.fetch.Branches 2238 # Number of branches that fetch encountered system.cpu.fetch.predictedBranches 802 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 2262 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1292 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 1225 # Number of cycles fetch has spent blocked -system.cpu.fetch.CacheLines 1813 # Number of cache lines fetched +system.cpu.fetch.Cycles 2263 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1291 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 1215 # Number of cycles fetch has spent blocked +system.cpu.fetch.CacheLines 1814 # Number of cache lines fetched system.cpu.fetch.IcacheSquashes 312 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 11857 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.109724 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.526984 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::samples 11808 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.114583 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.531247 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 9595 80.92% 80.92% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 178 1.50% 82.42% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 176 1.48% 83.91% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 141 1.19% 85.10% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 227 1.91% 87.01% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 133 1.12% 88.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 257 2.17% 90.30% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 110 0.93% 91.23% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1040 8.77% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 9545 80.84% 80.84% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 178 1.51% 82.34% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 176 1.49% 83.83% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 142 1.20% 85.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 227 1.92% 86.96% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 133 1.13% 88.08% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 257 2.18% 90.26% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 110 0.93% 91.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1040 8.81% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 11857 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.061057 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.358979 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 7580 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 1390 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2096 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 81 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 710 # Number of cycles decode is squashing +system.cpu.fetch.rateDist::total 11808 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.060585 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.356280 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 7545 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 1376 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 2098 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 80 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 709 # Number of cycles decode is squashing system.cpu.decode.BranchResolved 341 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 154 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 11719 # Number of instructions handled by decode +system.cpu.decode.DecodedInsts 11726 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 436 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 710 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 7768 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 673 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 449 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 1984 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 273 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 11300 # Number of instructions processed by rename -system.cpu.rename.IQFullEvents 6 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 232 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 9692 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 18178 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 18123 # Number of integer rename lookups +system.cpu.rename.SquashCycles 709 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 7731 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 670 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 446 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 1987 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 265 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 11308 # Number of instructions processed by rename +system.cpu.rename.IQFullEvents 4 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 226 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 9701 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 18192 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 18137 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 55 # Number of floating rename lookups system.cpu.rename.CommittedMaps 4998 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 4694 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 4703 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 27 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 27 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 580 # count of insts added to the skid buffer +system.cpu.rename.skidInsts 575 # count of insts added to the skid buffer system.cpu.memDep0.insertedLoads 2023 # Number of loads inserted to the mem dependence unit. system.cpu.memDep0.insertedStores 1831 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 52 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 33 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 10310 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 10305 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 57 # Number of non-speculative instructions added to the IQ system.cpu.iq.iqInstsIssued 8903 # Number of instructions issued system.cpu.iq.iqSquashedInstsIssued 241 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 4245 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 3499 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedInstsExamined 4250 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 3488 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 41 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 11857 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.750864 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.481785 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 11808 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.753980 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.485434 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 8486 71.57% 71.57% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1113 9.39% 80.96% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 789 6.65% 87.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 496 4.18% 91.79% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 461 3.89% 95.68% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 303 2.56% 98.24% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 131 1.10% 99.34% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 8446 71.53% 71.53% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1102 9.33% 80.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 787 6.66% 87.53% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 501 4.24% 91.77% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 457 3.87% 95.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 305 2.58% 98.22% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 132 1.12% 99.34% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 45 0.38% 99.72% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 33 0.28% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 11857 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 11808 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 8 4.68% 4.68% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 4.68% # attempts to use FU when none available @@ -388,10 +388,10 @@ system.cpu.iq.FU_type_0::MemWrite 1627 18.27% 100.00% # Ty system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::total 8903 # Type of FU issued -system.cpu.iq.rate 0.242893 # Inst issue rate +system.cpu.iq.rate 0.241012 # Inst issue rate system.cpu.iq.fu_busy_cnt 171 # FU busy when requested system.cpu.iq.fu_busy_rate 0.019207 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 30013 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_reads 29964 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_writes 14583 # Number of integer instruction queue writes system.cpu.iq.int_inst_queue_wakeup_accesses 8130 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 62 # Number of floating instruction queue reads @@ -408,12 +408,12 @@ system.cpu.iew.lsq.thread0.squashedStores 785 # N system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 8 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 9 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 710 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 456 # Number of cycles IEW is blocking +system.cpu.iew.iewSquashCycles 709 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 457 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 22 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 10367 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispatchedInsts 10362 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 55 # Number of squashed instructions skipped by dispatch system.cpu.iew.iewDispLoadInsts 2023 # Number of dispatched load instructions system.cpu.iew.iewDispStoreInsts 1831 # Number of dispatched store instructions @@ -432,35 +432,35 @@ system.cpu.iew.exec_nop 0 # nu system.cpu.iew.exec_refs 3201 # number of memory reference insts executed system.cpu.iew.exec_branches 1351 # Number of branches executed system.cpu.iew.exec_stores 1523 # Number of stores executed -system.cpu.iew.exec_rate 0.231953 # Inst execution rate +system.cpu.iew.exec_rate 0.230157 # Inst execution rate system.cpu.iew.wb_sent 8272 # cumulative count of insts sent to commit system.cpu.iew.wb_count 8157 # cumulative count of insts written-back -system.cpu.iew.wb_producers 4222 # num instructions producing a value -system.cpu.iew.wb_consumers 6684 # num instructions consuming a value +system.cpu.iew.wb_producers 4221 # num instructions producing a value +system.cpu.iew.wb_consumers 6683 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.222541 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.631658 # average fanout of values written-back +system.cpu.iew.wb_rate 0.220818 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.631603 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 4581 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 4576 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 16 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 266 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 11147 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.519602 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.320329 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 11099 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.521849 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.323963 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 8765 78.63% 78.63% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1011 9.07% 87.70% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 612 5.49% 93.19% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 265 2.38% 95.57% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 170 1.53% 97.09% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 108 0.97% 98.06% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 71 0.64% 98.70% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 44 0.39% 99.09% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 8724 78.60% 78.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1004 9.05% 87.65% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 606 5.46% 93.11% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 271 2.44% 95.55% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 170 1.53% 97.08% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 108 0.97% 98.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 70 0.63% 98.68% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 45 0.41% 99.09% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::8 101 0.91% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 11147 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 11099 # Number of insts commited each cycle system.cpu.commit.committedInsts 5792 # Number of instructions committed system.cpu.commit.committedOps 5792 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -473,22 +473,22 @@ system.cpu.commit.int_insts 5698 # Nu system.cpu.commit.function_calls 103 # Number of function calls committed. system.cpu.commit.bw_lim_events 101 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 21419 # The number of ROB reads -system.cpu.rob.rob_writes 21457 # The number of ROB writes -system.cpu.timesIdled 250 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 24797 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 21366 # The number of ROB reads +system.cpu.rob.rob_writes 21446 # The number of ROB writes +system.cpu.timesIdled 245 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 25132 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 5792 # Number of Instructions Simulated system.cpu.committedOps 5792 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 5792 # Number of Instructions Simulated -system.cpu.cpi 6.328384 # CPI: Cycles Per Instruction -system.cpu.cpi_total 6.328384 # CPI: Total CPI of All Threads -system.cpu.ipc 0.158018 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.158018 # IPC: Total IPC of All Threads +system.cpu.cpi 6.377762 # CPI: Cycles Per Instruction +system.cpu.cpi_total 6.377762 # CPI: Total CPI of All Threads +system.cpu.ipc 0.156795 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.156795 # IPC: Total IPC of All Threads system.cpu.int_regfile_reads 13474 # number of integer regfile reads system.cpu.int_regfile_writes 7049 # number of integer regfile writes system.cpu.fp_regfile_reads 25 # number of floating regfile reads system.cpu.fp_regfile_writes 2 # number of floating regfile writes -system.cpu.toL2Bus.throughput 1581971462 # Throughput (bytes/s) +system.cpu.toL2Bus.throughput 1569723057 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 406 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 406 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 47 # Transaction distribution @@ -503,60 +503,60 @@ system.cpu.toL2Bus.data_through_bus 28992 # To system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 226500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 526500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 2.9 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 153000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) -system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 167.412828 # Cycle average of tags in use -system.cpu.icache.total_refs 1371 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 351 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 3.905983 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 167.412828 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.081745 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.081745 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 1371 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1371 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1371 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1371 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1371 # number of overall hits -system.cpu.icache.overall_hits::total 1371 # number of overall hits +system.cpu.toL2Bus.respLayer0.occupancy 590750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 3.2 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 163000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) +system.cpu.icache.tags.replacements 0 # number of replacements +system.cpu.icache.tags.tagsinuse 167.253035 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 1372 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 351 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 3.908832 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 167.253035 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.081667 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.081667 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 1372 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1372 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1372 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1372 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1372 # number of overall hits +system.cpu.icache.overall_hits::total 1372 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 442 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 442 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 442 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 442 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 442 # number of overall misses system.cpu.icache.overall_misses::total 442 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 28629500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 28629500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 28629500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 28629500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 28629500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 28629500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1813 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1813 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1813 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1813 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1813 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1813 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.243795 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.243795 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.243795 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.243795 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.243795 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.243795 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 64772.624434 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 64772.624434 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 64772.624434 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 64772.624434 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 64772.624434 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 64772.624434 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 425 # number of cycles access was blocked +system.cpu.icache.ReadReq_miss_latency::cpu.inst 28917500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 28917500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 28917500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 28917500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 28917500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 28917500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1814 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1814 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1814 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1814 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1814 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1814 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.243660 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.243660 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.243660 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.243660 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.243660 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.243660 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 65424.208145 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 65424.208145 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 65424.208145 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 65424.208145 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 65424.208145 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 65424.208145 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 433 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 6 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 70.833333 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 72.166667 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed @@ -572,36 +572,36 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 351 system.cpu.icache.demand_mshr_misses::total 351 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 351 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 351 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23362000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 23362000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23362000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 23362000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23362000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 23362000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.193602 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.193602 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.193602 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.193602 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.193602 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.193602 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66558.404558 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66558.404558 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66558.404558 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 66558.404558 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66558.404558 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 66558.404558 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23457750 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 23457750 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23457750 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 23457750 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23457750 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 23457750 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.193495 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.193495 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.193495 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.193495 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.193495 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.193495 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66831.196581 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66831.196581 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66831.196581 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 66831.196581 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66831.196581 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 66831.196581 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 197.575721 # Cycle average of tags in use -system.cpu.l2cache.total_refs 7 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 399 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.017544 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 166.296629 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 31.279092 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.005075 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.000955 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.006030 # Average percentage of cache occupancy +system.cpu.l2cache.tags.replacements 0 # number of replacements +system.cpu.l2cache.tags.tagsinuse 197.401673 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 7 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 399 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.017544 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::cpu.inst 166.141608 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 31.260065 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005070 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.000954 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.006024 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 6 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 1 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 7 # number of ReadReq hits @@ -622,17 +622,17 @@ system.cpu.l2cache.demand_misses::total 446 # nu system.cpu.l2cache.overall_misses::cpu.inst 345 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 101 # number of overall misses system.cpu.l2cache.overall_misses::total 446 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 22950500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4123000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 27073500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3627500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 3627500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 22950500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 7750500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 30701000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 22950500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 7750500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 30701000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 23046250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4132250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 27178500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3637250 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 3637250 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 23046250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 7769500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 30815750 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 23046250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 7769500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 30815750 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 351 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 55 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 406 # number of ReadReq accesses(hits+misses) @@ -655,17 +655,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.984547 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.982906 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.990196 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.984547 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 66523.188406 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76351.851852 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 67853.383459 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77180.851064 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 77180.851064 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66523.188406 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76737.623762 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 68836.322870 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66523.188406 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76737.623762 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 68836.322870 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 66800.724638 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76523.148148 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 68116.541353 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77388.297872 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 77388.297872 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66800.724638 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76925.742574 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 69093.609865 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66800.724638 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76925.742574 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 69093.609865 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -685,17 +685,17 @@ system.cpu.l2cache.demand_mshr_misses::total 446 system.cpu.l2cache.overall_mshr_misses::cpu.inst 345 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 101 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 446 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 18670000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3463750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 22133750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3054750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3054750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 18670000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6518500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 25188500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 18670000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6518500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 25188500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 18694250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3465750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 22160000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3059750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3059750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 18694250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6525500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 25219750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 18694250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6525500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 25219750 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.982906 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.981818 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.982759 # mshr miss rate for ReadReq accesses @@ -707,51 +707,51 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.984547 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.982906 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.990196 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.984547 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 54115.942029 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64143.518519 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55473.057644 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64994.680851 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64994.680851 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54115.942029 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64539.603960 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56476.457399 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54115.942029 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64539.603960 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56476.457399 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 54186.231884 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64180.555556 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55538.847118 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 65101.063830 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 65101.063830 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54186.231884 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64608.910891 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56546.524664 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54186.231884 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64608.910891 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56546.524664 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 63.158434 # Cycle average of tags in use -system.cpu.dcache.total_refs 2188 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 102 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 21.450980 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 63.158434 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.015420 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.015420 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 0 # number of replacements +system.cpu.dcache.tags.tagsinuse 63.117277 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 2192 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 102 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 21.490196 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 63.117277 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.015409 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.015409 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 1473 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1473 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 715 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 715 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 2188 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2188 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2188 # number of overall hits -system.cpu.dcache.overall_hits::total 2188 # number of overall hits +system.cpu.dcache.WriteReq_hits::cpu.data 719 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 719 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 2192 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2192 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2192 # number of overall hits +system.cpu.dcache.overall_hits::total 2192 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 104 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 104 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 331 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 331 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 435 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 435 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 435 # number of overall misses -system.cpu.dcache.overall_misses::total 435 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 7358500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 7358500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 19767997 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 19767997 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 27126497 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 27126497 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 27126497 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 27126497 # number of overall miss cycles +system.cpu.dcache.WriteReq_misses::cpu.data 327 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 327 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 431 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 431 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 431 # number of overall misses +system.cpu.dcache.overall_misses::total 431 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 7388000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 7388000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 19896996 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 19896996 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 27284996 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 27284996 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 27284996 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 27284996 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 1577 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1577 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 1046 # number of WriteReq accesses(hits+misses) @@ -762,36 +762,36 @@ system.cpu.dcache.overall_accesses::cpu.data 2623 system.cpu.dcache.overall_accesses::total 2623 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.065948 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.065948 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.316444 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.316444 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.165841 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.165841 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.165841 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.165841 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 70754.807692 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 70754.807692 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 59722.045317 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 59722.045317 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 62359.763218 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 62359.763218 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 62359.763218 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 62359.763218 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 500 # number of cycles access was blocked +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.312620 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.312620 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.164316 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.164316 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.164316 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.164316 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 71038.461538 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 71038.461538 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60847.082569 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 60847.082569 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 63306.255220 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 63306.255220 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 63306.255220 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 63306.255220 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 501 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 5 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 100 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 100.200000 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.ReadReq_mshr_hits::cpu.data 49 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 49 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 284 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 284 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 333 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 333 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 333 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 333 # number of overall MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 280 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 280 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 329 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 329 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 329 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 329 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 55 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 47 # number of WriteReq MSHR misses @@ -800,14 +800,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 102 system.cpu.dcache.demand_mshr_misses::total 102 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 102 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 102 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4188500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4188500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3676999 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3676999 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7865499 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 7865499 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7865499 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 7865499 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4197750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4197750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3687248 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3687248 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7884998 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 7884998 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7884998 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 7884998 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.034876 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.034876 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044933 # mshr miss rate for WriteReq accesses @@ -816,14 +816,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.038887 system.cpu.dcache.demand_mshr_miss_rate::total 0.038887 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.038887 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.038887 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 76154.545455 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 76154.545455 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 78234.021277 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 78234.021277 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 77112.735294 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 77112.735294 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 77112.735294 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 77112.735294 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 76322.727273 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 76322.727273 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 78452.085106 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 78452.085106 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 77303.901961 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 77303.901961 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 77303.901961 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 77303.901961 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt index 45ae1e677..6e991864c 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000021 # Number of seconds simulated -sim_ticks 20764500 # Number of ticks simulated -final_tick 20764500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 20802500 # Number of ticks simulated +final_tick 20802500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 44697 # Simulator instruction rate (inst/s) -host_op_rate 44687 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 174155494 # Simulator tick rate (ticks/s) -host_mem_usage 232524 # Number of bytes of host memory used -host_seconds 0.12 # Real time elapsed on the host +host_inst_rate 39959 # Simulator instruction rate (inst/s) +host_op_rate 39952 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 155990706 # Simulator tick rate (ticks/s) +host_mem_usage 232536 # Number of bytes of host memory used +host_seconds 0.13 # Real time elapsed on the host sim_insts 5327 # Number of instructions simulated sim_ops 5327 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 18496 # Number of bytes read from this memory @@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 18496 # Nu system.physmem.num_reads::cpu.inst 289 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 134 # Number of read requests responded to by this memory system.physmem.num_reads::total 423 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 890751041 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 413012594 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1303763635 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 890751041 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 890751041 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 890751041 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 413012594 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1303763635 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 889123903 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 412258142 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1301382045 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 889123903 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 889123903 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 889123903 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 412258142 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1301382045 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 423 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen system.physmem.cpureqs 423 # Reqs generatd by CPU via cache - shady @@ -70,7 +70,7 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 20696000 # Total gap between requests +system.physmem.totGap 20733000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes @@ -85,9 +85,9 @@ system.physmem.writePktSize::3 0 # Ca system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes system.physmem.writePktSize::6 0 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 251 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 252 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 132 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 29 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 28 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 8 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -169,28 +169,28 @@ system.physmem.bytesPerActivate::1536 1 1.54% 96.92% # By system.physmem.bytesPerActivate::1728 1 1.54% 98.46% # Bytes accessed per row activation system.physmem.bytesPerActivate::3008 1 1.54% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 65 # Bytes accessed per row activation -system.physmem.totQLat 3131250 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 11791250 # Sum of mem lat for all requests +system.physmem.totQLat 2859500 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 11464500 # Sum of mem lat for all requests system.physmem.totBusLat 2115000 # Total cycles spent in databus access -system.physmem.totBankLat 6545000 # Total cycles spent in bank access -system.physmem.avgQLat 7402.48 # Average queueing delay per request -system.physmem.avgBankLat 15472.81 # Average bank access latency per request +system.physmem.totBankLat 6490000 # Total cycles spent in bank access +system.physmem.avgQLat 6760.05 # Average queueing delay per request +system.physmem.avgBankLat 15342.79 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 27875.30 # Average memory access latency -system.physmem.avgRdBW 1303.76 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 27102.84 # Average memory access latency +system.physmem.avgRdBW 1301.38 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 1303.76 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 1301.38 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 10.19 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.57 # Average read queue length over time +system.physmem.busUtil 10.17 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.55 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time system.physmem.readRowHits 358 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 84.63 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 48926.71 # Average gap between requests -system.membus.throughput 1303763635 # Throughput (bytes/s) +system.physmem.avgGap 49014.18 # Average gap between requests +system.membus.throughput 1301382045 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 342 # Transaction distribution system.membus.trans_dist::ReadResp 342 # Transaction distribution system.membus.trans_dist::ReadExReq 81 # Transaction distribution @@ -201,10 +201,10 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 27072 system.membus.tot_pkt_size 27072 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 27072 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 494500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 502000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.4 # Layer utilization (%) -system.membus.respLayer1.occupancy 3936500 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 19.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 3938750 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 18.9 # Layer utilization (%) system.cpu.branchPred.lookups 1636 # Number of BP lookups system.cpu.branchPred.condPredicted 1090 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 897 # Number of conditional branches incorrect @@ -215,7 +215,7 @@ system.cpu.branchPred.BTBHitPct 43.484736 # BT system.cpu.branchPred.usedRAS 67 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 4 # Number of incorrect RAS predictions. system.cpu.workload.num_syscalls 11 # Number of system calls -system.cpu.numCycles 41530 # number of cpu cycles simulated +system.cpu.numCycles 41606 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.branch_predictor.predictedTaken 651 # Number of Branches Predicted As Taken (True). @@ -237,12 +237,12 @@ system.cpu.execution_unit.executions 3957 # Nu system.cpu.mult_div_unit.multiplies 0 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 9717 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 9660 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 483 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 35284 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 6246 # Number of cycles cpu stages are processed. -system.cpu.activity 15.039730 # Percentage of cycles cpu is active +system.cpu.timesIdled 425 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 35361 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 6245 # Number of cycles cpu stages are processed. +system.cpu.activity 15.009854 # Percentage of cycles cpu is active system.cpu.comLoads 715 # Number of Load instructions committed system.cpu.comStores 673 # Number of Store instructions committed system.cpu.comBranches 1115 # Number of Branches instructions committed @@ -254,36 +254,36 @@ system.cpu.committedInsts 5327 # Nu system.cpu.committedOps 5327 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 5327 # Number of Instructions committed (Total) -system.cpu.cpi 7.796133 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 7.810400 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 7.796133 # CPI: Total CPI of All Threads -system.cpu.ipc 0.128269 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 7.810400 # CPI: Total CPI of All Threads +system.cpu.ipc 0.128034 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 0.128269 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 36890 # Number of cycles 0 instructions are processed. +system.cpu.ipc_total 0.128034 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 36966 # Number of cycles 0 instructions are processed. system.cpu.stage0.runCycles 4640 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 11.172646 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 38335 # Number of cycles 0 instructions are processed. +system.cpu.stage0.utilization 11.152238 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 38411 # Number of cycles 0 instructions are processed. system.cpu.stage1.runCycles 3195 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 7.693234 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 38497 # Number of cycles 0 instructions are processed. +system.cpu.stage1.utilization 7.679181 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 38573 # Number of cycles 0 instructions are processed. system.cpu.stage2.runCycles 3033 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 7.303154 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 40555 # Number of cycles 0 instructions are processed. +system.cpu.stage2.utilization 7.289814 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 40631 # Number of cycles 0 instructions are processed. system.cpu.stage3.runCycles 975 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 2.347700 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 38373 # Number of cycles 0 instructions are processed. +system.cpu.stage3.utilization 2.343412 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 38449 # Number of cycles 0 instructions are processed. system.cpu.stage4.runCycles 3157 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 7.601734 # Percentage of cycles stage was utilized (processing insts). -system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 142.226837 # Cycle average of tags in use -system.cpu.icache.total_refs 892 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 291 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 3.065292 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 142.226837 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.069447 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.069447 # Average percentage of cache occupancy +system.cpu.stage4.utilization 7.587848 # Percentage of cycles stage was utilized (processing insts). +system.cpu.icache.tags.replacements 0 # number of replacements +system.cpu.icache.tags.tagsinuse 142.145699 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 892 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 291 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 3.065292 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 142.145699 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.069407 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.069407 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 892 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 892 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 892 # number of demand (read+write) hits @@ -296,12 +296,12 @@ system.cpu.icache.demand_misses::cpu.inst 366 # n system.cpu.icache.demand_misses::total 366 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 366 # number of overall misses system.cpu.icache.overall_misses::total 366 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 25702500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 25702500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 25702500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 25702500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 25702500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 25702500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 25692750 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 25692750 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 25692750 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 25692750 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 25692750 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 25692750 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 1258 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 1258 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 1258 # number of demand (read+write) accesses @@ -314,12 +314,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.290938 system.cpu.icache.demand_miss_rate::total 0.290938 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.290938 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.290938 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 70225.409836 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 70225.409836 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 70225.409836 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 70225.409836 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 70225.409836 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 70225.409836 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 70198.770492 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 70198.770492 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 70198.770492 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 70198.770492 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 70198.770492 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 70198.770492 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -340,26 +340,26 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 291 system.cpu.icache.demand_mshr_misses::total 291 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 291 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 291 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 21114000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 21114000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 21114000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 21114000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 21114000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 21114000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 20948250 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 20948250 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 20948250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 20948250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 20948250 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 20948250 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.231320 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.231320 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.231320 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.231320 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.231320 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.231320 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 72556.701031 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 72556.701031 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 72556.701031 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 72556.701031 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 72556.701031 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 72556.701031 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 71987.113402 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 71987.113402 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 71987.113402 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 71987.113402 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 71987.113402 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 71987.113402 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 1313010186 # Throughput (bytes/s) +system.cpu.toL2Bus.throughput 1310611705 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 345 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 345 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 81 # Transaction distribution @@ -374,21 +374,21 @@ system.cpu.toL2Bus.data_through_bus 27264 # To system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 213000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 436500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 2.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 202500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%) -system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 168.609847 # Cycle average of tags in use -system.cpu.l2cache.total_refs 3 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 342 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.008772 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 141.647687 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 26.962160 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.004323 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.000823 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.005146 # Average percentage of cache occupancy +system.cpu.toL2Bus.respLayer0.occupancy 489750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 2.4 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 219500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 1.1 # Layer utilization (%) +system.cpu.l2cache.tags.replacements 0 # number of replacements +system.cpu.l2cache.tags.tagsinuse 168.511029 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 3 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 342 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.008772 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::cpu.inst 141.570095 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 26.940934 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004320 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.000822 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.005143 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 1 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 3 # number of ReadReq hits @@ -409,17 +409,17 @@ system.cpu.l2cache.demand_misses::total 423 # nu system.cpu.l2cache.overall_misses::cpu.inst 289 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 134 # number of overall misses system.cpu.l2cache.overall_misses::total 423 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 20795500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3765500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 24561000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5904000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 5904000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 20795500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 9669500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 30465000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 20795500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 9669500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 30465000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 20629750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3759250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 24389000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5820750 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 5820750 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 20629750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 9580000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 30209750 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 20629750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 9580000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 30209750 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 291 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 54 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 345 # number of ReadReq accesses(hits+misses) @@ -442,17 +442,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.992958 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993127 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.992593 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.992958 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71956.747405 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 71047.169811 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 71815.789474 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72888.888889 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72888.888889 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71956.747405 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 72160.447761 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 72021.276596 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71956.747405 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 72160.447761 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 72021.276596 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71383.217993 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 70929.245283 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 71312.865497 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 71861.111111 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71861.111111 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71383.217993 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 71492.537313 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 71417.848700 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71383.217993 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 71492.537313 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 71417.848700 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -472,17 +472,17 @@ system.cpu.l2cache.demand_mshr_misses::total 423 system.cpu.l2cache.overall_mshr_misses::cpu.inst 289 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 134 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 423 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 17227750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3116250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 20344000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4915500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4915500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 17227750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8031750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 25259500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 17227750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8031750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 25259500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 17007250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3101250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 20108500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4823250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4823250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 17007250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7924500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 24931750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 17007250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7924500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 24931750 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993127 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.981481 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.991304 # mshr miss rate for ReadReq accesses @@ -494,27 +494,27 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.992958 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993127 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.992593 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.992958 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 59611.591696 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 58797.169811 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59485.380117 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60685.185185 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60685.185185 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59611.591696 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59938.432836 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59715.130024 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59611.591696 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59938.432836 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59715.130024 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58848.615917 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 58514.150943 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58796.783626 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 59546.296296 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 59546.296296 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58848.615917 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59138.059701 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58940.307329 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58848.615917 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59138.059701 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58940.307329 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 84.923213 # Cycle average of tags in use -system.cpu.dcache.total_refs 914 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 135 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 6.770370 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 84.923213 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.020733 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.020733 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 0 # number of replacements +system.cpu.dcache.tags.tagsinuse 84.821490 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 914 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 135 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 6.770370 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 84.821490 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.020708 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.020708 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 654 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 654 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 260 # number of WriteReq hits @@ -531,14 +531,14 @@ system.cpu.dcache.demand_misses::cpu.data 474 # n system.cpu.dcache.demand_misses::total 474 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 474 # number of overall misses system.cpu.dcache.overall_misses::total 474 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 4316000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 4316000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 26761000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 26761000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 31077000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 31077000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 31077000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 31077000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 4325500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 4325500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 26675750 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 26675750 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 31001250 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 31001250 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 31001250 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 31001250 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 715 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 715 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 673 # number of WriteReq accesses(hits+misses) @@ -555,19 +555,19 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.341499 system.cpu.dcache.demand_miss_rate::total 0.341499 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.341499 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.341499 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 70754.098361 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 70754.098361 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64796.610169 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 64796.610169 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 65563.291139 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 65563.291139 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 65563.291139 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 65563.291139 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 781 # number of cycles access was blocked +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 70909.836066 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 70909.836066 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64590.193705 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 64590.193705 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 65403.481013 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 65403.481013 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 65403.481013 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 65403.481013 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 792 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 32 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 31 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 24.406250 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 25.548387 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed @@ -587,14 +587,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 135 system.cpu.dcache.demand_mshr_misses::total 135 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 135 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 135 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3832000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 3832000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5987500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5987500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9819500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 9819500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9819500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 9819500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3825750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 3825750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5904250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5904250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9730000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 9730000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9730000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 9730000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.075524 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.075524 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.120357 # mshr miss rate for WriteReq accesses @@ -603,14 +603,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.097262 system.cpu.dcache.demand_mshr_miss_rate::total 0.097262 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.097262 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.097262 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 70962.962963 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 70962.962963 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73919.753086 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73919.753086 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 72737.037037 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 72737.037037 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 72737.037037 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 72737.037037 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 70847.222222 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 70847.222222 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 72891.975309 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 72891.975309 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 72074.074074 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 72074.074074 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 72074.074074 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 72074.074074 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt index 404dd533e..c4b2117ab 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt @@ -65,15 +65,15 @@ system.cpu.num_idle_cycles 0 # Nu system.cpu.num_busy_cycles 55600 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 117.043638 # Cycle average of tags in use -system.cpu.icache.total_refs 5114 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 257 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 19.898833 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 117.043638 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.057150 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.057150 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 0 # number of replacements +system.cpu.icache.tags.tagsinuse 117.043638 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 5114 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 257 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 19.898833 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 117.043638 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.057150 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.057150 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 5114 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 5114 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 5114 # number of demand (read+write) hits @@ -143,17 +143,17 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 52673.151751 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52673.151751 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 52673.151751 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 142.183999 # Cycle average of tags in use -system.cpu.l2cache.total_refs 3 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 308 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.009740 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 116.519250 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 25.664749 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.003556 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.000783 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.004339 # Average percentage of cache occupancy +system.cpu.l2cache.tags.replacements 0 # number of replacements +system.cpu.l2cache.tags.tagsinuse 142.183999 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 3 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 308 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.009740 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::cpu.inst 116.519250 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 25.664749 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003556 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.000783 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.004339 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 1 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 3 # number of ReadReq hits @@ -271,15 +271,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 82.118455 # Cycle average of tags in use -system.cpu.dcache.total_refs 1253 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 135 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 9.281481 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 82.118455 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.020048 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.020048 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 0 # number of replacements +system.cpu.dcache.tags.tagsinuse 82.118455 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 1253 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 135 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 9.281481 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 82.118455 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.020048 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.020048 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 661 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 661 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 592 # number of WriteReq hits diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt index 43264ddcf..7c9257554 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt @@ -1,50 +1,50 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000020 # Number of seconds simulated -sim_ticks 19589000 # Number of ticks simulated -final_tick 19589000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 19639500 # Number of ticks simulated +final_tick 19639500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1364 # Simulator instruction rate (inst/s) -host_op_rate 2472 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 4967212 # Simulator tick rate (ticks/s) +host_inst_rate 28578 # Simulator instruction rate (inst/s) +host_op_rate 51768 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 104294046 # Simulator tick rate (ticks/s) host_mem_usage 245432 # Number of bytes of host memory used -host_seconds 3.94 # Real time elapsed on the host +host_seconds 0.19 # Real time elapsed on the host sim_insts 5380 # Number of instructions simulated sim_ops 9747 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 17472 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 8960 # Number of bytes read from this memory -system.physmem.bytes_read::total 26432 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 17472 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 17472 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 273 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 140 # Number of read requests responded to by this memory -system.physmem.num_reads::total 413 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 891929144 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 457399561 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1349328705 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 891929144 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 891929144 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 891929144 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 457399561 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1349328705 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 414 # Total number of read requests seen +system.physmem.bytes_read::cpu.inst 17536 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9088 # Number of bytes read from this memory +system.physmem.bytes_read::total 26624 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 17536 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 17536 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 274 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 142 # Number of read requests responded to by this memory +system.physmem.num_reads::total 416 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 892894422 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 462740905 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1355635327 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 892894422 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 892894422 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 892894422 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 462740905 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1355635327 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 417 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen -system.physmem.cpureqs 414 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 26432 # Total number of bytes read from memory +system.physmem.cpureqs 417 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 26624 # Total number of bytes read from memory system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 26432 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedRd 26624 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 33 # Track reads on a per bank basis +system.physmem.perBankRdReqs::0 34 # Track reads on a per bank basis system.physmem.perBankRdReqs::1 1 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 5 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 6 # Track reads on a per bank basis system.physmem.perBankRdReqs::3 8 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 50 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 51 # Track reads on a per bank basis system.physmem.perBankRdReqs::5 44 # Track reads on a per bank basis system.physmem.perBankRdReqs::6 20 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 36 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 22 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 35 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 23 # Track reads on a per bank basis system.physmem.perBankRdReqs::9 73 # Track reads on a per bank basis system.physmem.perBankRdReqs::10 63 # Track reads on a per bank basis system.physmem.perBankRdReqs::11 17 # Track reads on a per bank basis @@ -70,14 +70,14 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 19541000 # Total gap between requests +system.physmem.totGap 19591000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 414 # Categorize read packet sizes +system.physmem.readPktSize::6 417 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes @@ -85,10 +85,10 @@ system.physmem.writePktSize::3 0 # Ca system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes system.physmem.writePktSize::6 0 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 249 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 124 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 38 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 248 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 126 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 37 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 6 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see @@ -149,303 +149,302 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 87 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 216.275862 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 131.153640 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 325.056442 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64 43 49.43% 49.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128 13 14.94% 64.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192 9 10.34% 74.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256 4 4.60% 79.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320 7 8.05% 87.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384 3 3.45% 90.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512 1 1.15% 91.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640 1 1.15% 93.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704 1 1.15% 94.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768 1 1.15% 95.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960 2 2.30% 97.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344 1 1.15% 98.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368 1 1.15% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 87 # Bytes accessed per row activation -system.physmem.totQLat 1394000 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 11081500 # Sum of mem lat for all requests -system.physmem.totBusLat 2070000 # Total cycles spent in databus access -system.physmem.totBankLat 7617500 # Total cycles spent in bank access -system.physmem.avgQLat 3367.15 # Average queueing delay per request -system.physmem.avgBankLat 18399.76 # Average bank access latency per request +system.physmem.bytesPerActivate::samples 88 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 216 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 132.605669 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 322.610045 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64 42 47.73% 47.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128 13 14.77% 62.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192 12 13.64% 76.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256 4 4.55% 80.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320 6 6.82% 87.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384 3 3.41% 90.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512 1 1.14% 92.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640 1 1.14% 93.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704 1 1.14% 94.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768 1 1.14% 95.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960 2 2.27% 97.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344 1 1.14% 98.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368 1 1.14% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 88 # Bytes accessed per row activation +system.physmem.totQLat 1395750 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 11125750 # Sum of mem lat for all requests +system.physmem.totBusLat 2085000 # Total cycles spent in databus access +system.physmem.totBankLat 7645000 # Total cycles spent in bank access +system.physmem.avgQLat 3347.12 # Average queueing delay per request +system.physmem.avgBankLat 18333.33 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 26766.91 # Average memory access latency -system.physmem.avgRdBW 1349.33 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 26680.46 # Average memory access latency +system.physmem.avgRdBW 1355.64 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 1349.33 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 1355.64 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 10.54 # Data bus utilization in percentage +system.physmem.busUtil 10.59 # Data bus utilization in percentage system.physmem.avgRdQLen 0.57 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 327 # Number of row buffer hits during reads +system.physmem.readRowHits 329 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 78.99 # Row buffer hit rate for reads +system.physmem.readRowHitRate 78.90 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 47200.48 # Average gap between requests -system.membus.throughput 1349328705 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 337 # Transaction distribution -system.membus.trans_dist::ReadResp 336 # Transaction distribution +system.physmem.avgGap 46980.82 # Average gap between requests +system.membus.throughput 1355635327 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 340 # Transaction distribution +system.membus.trans_dist::ReadResp 339 # Transaction distribution system.membus.trans_dist::ReadExReq 77 # Transaction distribution system.membus.trans_dist::ReadExResp 77 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 827 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 827 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.physmem.port 827 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 827 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 26432 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 26432 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.physmem.port 26432 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 26432 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 26432 # Total data (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 833 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 833 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.physmem.port 833 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 833 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 26624 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 26624 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.physmem.port 26624 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 26624 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 26624 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 498000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 2.5 # Layer utilization (%) -system.membus.respLayer1.occupancy 3864000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 19.7 # Layer utilization (%) -system.cpu.branchPred.lookups 3089 # Number of BP lookups -system.cpu.branchPred.condPredicted 3089 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 541 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 2286 # Number of BTB lookups -system.cpu.branchPred.BTBHits 726 # Number of BTB hits +system.membus.reqLayer0.occupancy 505500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 2.6 # Layer utilization (%) +system.membus.respLayer1.occupancy 3891500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 19.8 # Layer utilization (%) +system.cpu.branchPred.lookups 3060 # Number of BP lookups +system.cpu.branchPred.condPredicted 3060 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 546 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 2257 # Number of BTB lookups +system.cpu.branchPred.BTBHits 719 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 31.758530 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 207 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 31.856447 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 208 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 72 # Number of incorrect RAS predictions. system.cpu.workload.num_syscalls 11 # Number of system calls -system.cpu.numCycles 39179 # number of cpu cycles simulated +system.cpu.numCycles 39280 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 10273 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 14155 # Number of instructions fetch has processed -system.cpu.fetch.Branches 3089 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 933 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 3944 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 2474 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 5406 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 59 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 375 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 11 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 1981 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 264 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 21925 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.151015 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.666624 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 10420 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 14154 # Number of instructions fetch has processed +system.cpu.fetch.Branches 3060 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 927 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 3932 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 2487 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 5289 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 61 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 384 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 1977 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 258 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 21952 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.145317 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.661061 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 18081 82.47% 82.47% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 213 0.97% 83.44% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 143 0.65% 84.09% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 223 1.02% 85.11% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 185 0.84% 85.95% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 200 0.91% 86.86% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 277 1.26% 88.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 158 0.72% 88.85% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 2445 11.15% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 18121 82.55% 82.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 212 0.97% 83.51% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 149 0.68% 84.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 217 0.99% 85.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 180 0.82% 86.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 202 0.92% 86.92% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 278 1.27% 88.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 161 0.73% 88.92% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 2432 11.08% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 21925 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.078843 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.361290 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 11051 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 5299 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 3578 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 140 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1857 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 24188 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 1857 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 11417 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 3782 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 753 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 3333 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 783 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 22649 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 12 # Number of times rename has blocked due to ROB full +system.cpu.fetch.rateDist::total 21952 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.077902 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.360336 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 11197 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 5173 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 3579 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 137 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1866 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 24141 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 1866 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 11552 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 3842 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 569 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 3343 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 780 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 22717 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 10 # Number of times rename has blocked due to ROB full system.cpu.rename.IQFullEvents 35 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 669 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 25230 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 54980 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 54964 # Number of integer rename lookups +system.cpu.rename.LSQFullEvents 666 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 25267 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 55251 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 55235 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 16 # Number of floating rename lookups system.cpu.rename.CommittedMaps 11063 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 14167 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 32 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 32 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 2073 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2281 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1568 # Number of stores inserted to the mem dependence unit. +system.cpu.rename.UndoneMaps 14204 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 30 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 30 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 2015 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2290 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1582 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 11 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 4 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 20212 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 20306 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 28 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 17024 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 290 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 9720 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 13890 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 17094 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 292 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 9804 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 14093 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 16 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 21925 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.776465 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.650682 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 21952 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.778699 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.655311 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 16429 74.93% 74.93% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1551 7.07% 82.01% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 1089 4.97% 86.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 725 3.31% 90.28% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 705 3.22% 93.50% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 574 2.62% 96.11% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 578 2.64% 98.75% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 230 1.05% 99.80% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 44 0.20% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 16455 74.96% 74.96% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1544 7.03% 81.99% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 1078 4.91% 86.90% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 728 3.32% 90.22% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 707 3.22% 93.44% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 584 2.66% 96.10% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 572 2.61% 98.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 242 1.10% 99.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 42 0.19% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 21925 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 21952 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 139 76.80% 76.80% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 76.80% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 76.80% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 76.80% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 76.80% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 76.80% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 76.80% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 76.80% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 76.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 76.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 76.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 76.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 76.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 76.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 76.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 76.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 76.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 76.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 76.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 76.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 76.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 76.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 76.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 76.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 76.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 76.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 76.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 76.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 76.80% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 27 14.92% 91.71% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 15 8.29% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 143 77.72% 77.72% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 77.72% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 77.72% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 77.72% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 77.72% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 77.72% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 77.72% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 77.72% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 77.72% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 77.72% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 77.72% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 77.72% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 77.72% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 77.72% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 77.72% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 77.72% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 77.72% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 77.72% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 77.72% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 77.72% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 77.72% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 77.72% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 77.72% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 77.72% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 77.72% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 77.72% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 77.72% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 77.72% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 77.72% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 26 14.13% 91.85% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 15 8.15% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 3 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 13662 80.25% 80.27% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 4 0.02% 80.29% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 7 0.04% 80.33% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 80.33% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 80.33% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 80.33% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 80.33% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 80.33% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 80.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 80.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 80.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 80.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 80.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 80.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 80.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 80.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 80.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 80.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 80.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 80.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 80.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 80.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 80.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 80.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 80.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 80.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 80.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 80.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 80.33% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 1972 11.58% 91.92% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1376 8.08% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 13719 80.26% 80.27% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 4 0.02% 80.30% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 7 0.04% 80.34% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 80.34% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 80.34% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 80.34% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 80.34% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 80.34% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 80.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 80.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 80.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 80.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 80.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 80.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 80.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 80.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 80.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 80.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 80.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 80.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 80.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 80.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 80.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 80.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 80.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 80.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 80.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 80.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 80.34% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 1979 11.58% 91.92% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1382 8.08% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 17024 # Type of FU issued -system.cpu.iq.rate 0.434518 # Inst issue rate -system.cpu.iq.fu_busy_cnt 181 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.010632 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 56436 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 29967 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 15651 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 17094 # Type of FU issued +system.cpu.iq.rate 0.435183 # Inst issue rate +system.cpu.iq.fu_busy_cnt 184 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.010764 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 56608 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 30145 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 15699 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 8 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 4 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 4 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 17198 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 17271 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 4 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 173 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 170 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1228 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1237 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 11 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 12 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 633 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 647 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 21 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 12 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1857 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 2975 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 36 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 20240 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 40 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2281 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1568 # Number of dispatched store instructions +system.cpu.iew.iewSquashCycles 1866 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 3033 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 35 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 20334 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 50 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2290 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1582 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 28 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 5 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewIQFullEvents 4 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 12 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 114 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 569 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 683 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 16133 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 1855 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 891 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedTakenIncorrect 113 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 578 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 691 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 16182 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 1848 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 912 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 3133 # number of memory reference insts executed -system.cpu.iew.exec_branches 1621 # Number of branches executed -system.cpu.iew.exec_stores 1278 # Number of stores executed -system.cpu.iew.exec_rate 0.411777 # Inst execution rate -system.cpu.iew.wb_sent 15873 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 15655 # cumulative count of insts written-back -system.cpu.iew.wb_producers 10119 # num instructions producing a value -system.cpu.iew.wb_consumers 15566 # num instructions consuming a value +system.cpu.iew.exec_refs 3125 # number of memory reference insts executed +system.cpu.iew.exec_branches 1615 # Number of branches executed +system.cpu.iew.exec_stores 1277 # Number of stores executed +system.cpu.iew.exec_rate 0.411965 # Inst execution rate +system.cpu.iew.wb_sent 15923 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 15703 # cumulative count of insts written-back +system.cpu.iew.wb_producers 10139 # num instructions producing a value +system.cpu.iew.wb_consumers 15623 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.399576 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.650071 # average fanout of values written-back +system.cpu.iew.wb_rate 0.399771 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.648979 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 10504 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 10598 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 12 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 593 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 20068 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.485699 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.341238 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 599 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 20086 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.485263 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.340827 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 16495 82.20% 82.20% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1364 6.80% 88.99% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 592 2.95% 91.94% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 713 3.55% 95.50% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 16512 82.21% 82.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1365 6.80% 89.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 596 2.97% 91.97% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 708 3.52% 95.49% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::4 362 1.80% 97.30% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::5 137 0.68% 97.98% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::6 121 0.60% 98.58% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 71 0.35% 98.94% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 213 1.06% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 73 0.36% 98.94% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 212 1.06% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 20068 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 20086 # Number of insts commited each cycle system.cpu.commit.committedInsts 5380 # Number of instructions committed system.cpu.commit.committedOps 9747 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -456,138 +455,138 @@ system.cpu.commit.branches 1208 # Nu system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. system.cpu.commit.int_insts 9654 # Number of committed integer instructions. system.cpu.commit.function_calls 106 # Number of function calls committed. -system.cpu.commit.bw_lim_events 213 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 212 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 40106 # The number of ROB reads -system.cpu.rob.rob_writes 42382 # The number of ROB writes -system.cpu.timesIdled 168 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 17254 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 40219 # The number of ROB reads +system.cpu.rob.rob_writes 42582 # The number of ROB writes +system.cpu.timesIdled 167 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 17328 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 5380 # Number of Instructions Simulated system.cpu.committedOps 9747 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 5380 # Number of Instructions Simulated -system.cpu.cpi 7.282342 # CPI: Cycles Per Instruction -system.cpu.cpi_total 7.282342 # CPI: Total CPI of All Threads -system.cpu.ipc 0.137318 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.137318 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 28721 # number of integer regfile reads -system.cpu.int_regfile_writes 17199 # number of integer regfile writes +system.cpu.cpi 7.301115 # CPI: Cycles Per Instruction +system.cpu.cpi_total 7.301115 # CPI: Total CPI of All Threads +system.cpu.ipc 0.136965 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.136965 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 28824 # number of integer regfile reads +system.cpu.int_regfile_writes 17237 # number of integer regfile writes system.cpu.fp_regfile_reads 4 # number of floating regfile reads -system.cpu.misc_regfile_reads 7135 # number of misc regfile reads +system.cpu.misc_regfile_reads 7122 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.toL2Bus.throughput 1355862984 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 339 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 338 # Transaction distribution +system.cpu.toL2Bus.throughput 1362152804 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 342 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 341 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 77 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 77 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 548 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 283 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count 831 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 17536 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 9024 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size 26560 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 26560 # Total data (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 550 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 287 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count 837 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 17600 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 9152 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size 26752 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 26752 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 208000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.occupancy 209500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 411000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 2.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 211500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 1.1 # Layer utilization (%) -system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 130.964375 # Cycle average of tags in use -system.cpu.icache.total_refs 1611 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 274 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 5.879562 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 130.964375 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.063947 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.063947 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 1611 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1611 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1611 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1611 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1611 # number of overall hits -system.cpu.icache.overall_hits::total 1611 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 370 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 370 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 370 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 370 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 370 # number of overall misses -system.cpu.icache.overall_misses::total 370 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 24285500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 24285500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 24285500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 24285500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 24285500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 24285500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1981 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1981 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1981 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1981 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1981 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1981 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.186774 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.186774 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.186774 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.186774 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.186774 # 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miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.993056 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.995227 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68495.437956 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76905.303030 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 70127.941176 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70922.077922 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70922.077922 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68495.437956 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73683.566434 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 70274.580336 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68495.437956 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73683.566434 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 70274.580336 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -660,113 +659,113 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 273 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 64 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 337 # 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mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.985075 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.994152 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996350 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.992958 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.995192 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996350 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.992958 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.995192 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56112.637363 # average ReadReq mshr miss latency +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996364 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.993056 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.995227 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996364 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.993056 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.995227 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55924.270073 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64625 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57729.228487 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58113.636364 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58113.636364 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56112.637363 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61069.148936 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57800.724638 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56112.637363 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61069.148936 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57800.724638 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57613.235294 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58448.051948 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58448.051948 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55924.270073 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61298.951049 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57767.386091 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55924.270073 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61298.951049 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57767.386091 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 81.657362 # Cycle average of tags in use -system.cpu.dcache.total_refs 2334 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 141 # 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miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.082353 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.082353 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.081825 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.081825 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.081825 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.081825 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 71377.862595 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 71377.862595 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73370.129870 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 73370.129870 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 72115.384615 # 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average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed @@ -776,38 +775,38 @@ system.cpu.dcache.demand_mshr_hits::cpu.data 66 system.cpu.dcache.demand_mshr_hits::total 66 # number of demand (read+write) MSHR hits system.cpu.dcache.overall_mshr_hits::cpu.data 66 # number of overall MSHR hits system.cpu.dcache.overall_mshr_hits::total 66 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 65 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 65 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 67 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 67 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 77 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 77 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 142 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 142 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 142 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 142 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4989000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4989000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5495500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5495500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10484500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 10484500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10484500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 10484500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.040448 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.040448 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_misses::cpu.data 144 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 144 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 144 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 144 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5151750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 5151750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5538000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5538000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10689750 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 10689750 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10689750 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 10689750 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.041460 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.041460 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.082353 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.082353 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.055862 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.055862 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.055862 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.055862 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 76753.846154 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 76753.846154 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71370.129870 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71370.129870 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 73834.507042 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 73834.507042 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 73834.507042 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 73834.507042 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.056448 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.056448 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.056448 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.056448 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 76891.791045 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 76891.791045 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71922.077922 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71922.077922 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 74234.375000 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 74234.375000 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74234.375000 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 74234.375000 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt index 7844ef634..f38f31bd7 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt @@ -69,15 +69,15 @@ system.cpu.num_idle_cycles 0 # Nu system.cpu.num_busy_cycles 56716 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 105.550219 # Cycle average of tags in use -system.cpu.icache.total_refs 6637 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 228 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 29.109649 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 105.550219 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.051538 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.051538 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 0 # number of replacements +system.cpu.icache.tags.tagsinuse 105.550219 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 6637 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 228 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 29.109649 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 105.550219 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.051538 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.051538 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 6637 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 6637 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 6637 # number of demand (read+write) hits @@ -147,17 +147,17 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 52815.789474 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52815.789474 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 52815.789474 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 134.034140 # Cycle average of tags in use -system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 282 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.003546 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 105.558330 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 28.475810 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.003221 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.000869 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.004090 # Average percentage of cache occupancy +system.cpu.l2cache.tags.replacements 0 # number of replacements +system.cpu.l2cache.tags.tagsinuse 134.034140 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 282 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.003546 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::cpu.inst 105.558330 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 28.475810 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003221 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.000869 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.004090 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits @@ -272,15 +272,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 80.797237 # Cycle average of tags in use -system.cpu.dcache.total_refs 1854 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 134 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 13.835821 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 80.797237 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.019726 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.019726 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 0 # number of replacements +system.cpu.dcache.tags.tagsinuse 80.797237 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 1854 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 134 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 13.835821 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 80.797237 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.019726 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.019726 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 998 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 998 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 856 # number of WriteReq hits diff --git a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt index 6de850a93..099eda912 100644 --- a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt +++ b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt @@ -1,48 +1,48 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000024 # Number of seconds simulated -sim_ticks 23841000 # Number of ticks simulated -final_tick 23841000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 24404000 # Number of ticks simulated +final_tick 24404000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 85306 # Simulator instruction rate (inst/s) -host_op_rate 85298 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 159545701 # Simulator tick rate (ticks/s) +host_inst_rate 52847 # Simulator instruction rate (inst/s) +host_op_rate 52845 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 101181200 # Simulator tick rate (ticks/s) host_mem_usage 228064 # Number of bytes of host memory used -host_seconds 0.15 # Real time elapsed on the host +host_seconds 0.24 # Real time elapsed on the host sim_insts 12745 # Number of instructions simulated sim_ops 12745 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 40000 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 39936 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 22400 # Number of bytes read from this memory -system.physmem.bytes_read::total 62400 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 40000 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 40000 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 625 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 62336 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 39936 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 39936 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 624 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 350 # Number of read requests responded to by this memory -system.physmem.num_reads::total 975 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1677781972 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 939557904 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2617339877 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1677781972 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1677781972 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1677781972 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 939557904 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2617339877 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 975 # Total number of read requests seen +system.physmem.num_reads::total 974 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1636453040 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 917882314 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2554335355 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1636453040 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1636453040 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1636453040 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 917882314 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2554335355 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 974 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen -system.physmem.cpureqs 975 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 62400 # Total number of bytes read from memory +system.physmem.cpureqs 974 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 62336 # Total number of bytes read from memory system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 62400 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedRd 62336 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed system.physmem.perBankRdReqs::0 83 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 154 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 153 # Track reads on a per bank basis system.physmem.perBankRdReqs::2 77 # Track reads on a per bank basis system.physmem.perBankRdReqs::3 59 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 86 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 87 # Track reads on a per bank basis system.physmem.perBankRdReqs::5 49 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 33 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 32 # Track reads on a per bank basis system.physmem.perBankRdReqs::7 49 # Track reads on a per bank basis system.physmem.perBankRdReqs::8 41 # Track reads on a per bank basis system.physmem.perBankRdReqs::9 39 # Track reads on a per bank basis @@ -70,14 +70,14 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 23399000 # Total gap between requests +system.physmem.totGap 24245500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 975 # Categorize read packet sizes +system.physmem.readPktSize::6 974 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes @@ -85,12 +85,12 @@ system.physmem.writePktSize::3 0 # Ca system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes system.physmem.writePktSize::6 0 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 347 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 345 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 183 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 78 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 14 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 6 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 342 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 347 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 181 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 79 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 19 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 4 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -149,100 +149,101 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 181 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 309.392265 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 160.897114 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 490.133684 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64 75 41.44% 41.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128 28 15.47% 56.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192 19 10.50% 67.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256 20 11.05% 78.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320 2 1.10% 79.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384 4 2.21% 81.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448 4 2.21% 83.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512 3 1.66% 85.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576 2 1.10% 86.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640 4 2.21% 88.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704 2 1.10% 90.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768 1 0.55% 90.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896 1 0.55% 91.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960 2 1.10% 92.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024 2 1.10% 93.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088 2 1.10% 94.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216 1 0.55% 95.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472 1 0.55% 95.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728 1 0.55% 96.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856 1 0.55% 96.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920 2 1.10% 97.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112 1 0.55% 98.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432 1 0.55% 98.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880 2 1.10% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 181 # Bytes accessed per row activation -system.physmem.totQLat 6851500 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 28281500 # Sum of mem lat for all requests -system.physmem.totBusLat 4875000 # Total cycles spent in databus access -system.physmem.totBankLat 16555000 # Total cycles spent in bank access -system.physmem.avgQLat 7027.18 # Average queueing delay per request -system.physmem.avgBankLat 16979.49 # Average bank access latency per request +system.physmem.bytesPerActivate::samples 189 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 295.957672 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 156.277128 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 472.297416 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64 80 42.33% 42.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128 30 15.87% 58.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192 19 10.05% 68.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256 20 10.58% 78.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320 3 1.59% 80.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384 5 2.65% 83.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448 4 2.12% 85.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512 3 1.59% 86.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576 1 0.53% 87.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640 6 3.17% 90.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704 1 0.53% 91.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768 1 0.53% 91.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896 1 0.53% 92.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960 2 1.06% 93.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024 1 0.53% 93.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088 2 1.06% 94.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280 1 0.53% 95.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408 1 0.53% 95.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664 1 0.53% 96.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792 1 0.53% 96.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856 2 1.06% 97.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112 1 0.53% 98.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432 1 0.53% 98.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816 1 0.53% 99.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880 1 0.53% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 189 # Bytes accessed per row activation +system.physmem.totQLat 8948500 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 30593500 # Sum of mem lat for all requests +system.physmem.totBusLat 4870000 # Total cycles spent in databus access +system.physmem.totBankLat 16775000 # Total cycles spent in bank access +system.physmem.avgQLat 9187.37 # Average queueing delay per request +system.physmem.avgBankLat 17222.79 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 29006.67 # Average memory access latency -system.physmem.avgRdBW 2617.34 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 31410.16 # Average memory access latency +system.physmem.avgRdBW 2554.34 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 2617.34 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 2554.34 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 20.45 # Data bus utilization in percentage -system.physmem.avgRdQLen 1.19 # Average read queue length over time +system.physmem.busUtil 19.96 # Data bus utilization in percentage +system.physmem.avgRdQLen 1.25 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 794 # Number of row buffer hits during reads +system.physmem.readRowHits 785 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 81.44 # Row buffer hit rate for reads +system.physmem.readRowHitRate 80.60 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 23998.97 # Average gap between requests -system.membus.throughput 2617339877 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 829 # Transaction distribution -system.membus.trans_dist::ReadResp 829 # Transaction distribution +system.physmem.avgGap 24892.71 # Average gap between requests +system.membus.throughput 2554335355 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 828 # Transaction distribution +system.membus.trans_dist::ReadResp 828 # Transaction distribution system.membus.trans_dist::ReadExReq 146 # Transaction distribution system.membus.trans_dist::ReadExResp 146 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side 1950 # Packet count per connected master and slave (bytes) -system.membus.pkt_count 1950 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 62400 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size 62400 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 62400 # Total data (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side 1948 # Packet count per connected master and slave (bytes) +system.membus.pkt_count 1948 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 62336 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size 62336 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 62336 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1213500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 5.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 9055000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 38.0 # Layer utilization (%) -system.cpu.branchPred.lookups 6923 # Number of BP lookups -system.cpu.branchPred.condPredicted 3910 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1532 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 5090 # Number of BTB lookups -system.cpu.branchPred.BTBHits 950 # Number of BTB hits +system.membus.reqLayer0.occupancy 1227000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 5.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 9049000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 37.1 # Layer utilization (%) +system.cpu.branchPred.lookups 6717 # Number of BP lookups +system.cpu.branchPred.condPredicted 3814 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1469 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 4787 # Number of BTB lookups +system.cpu.branchPred.BTBHits 874 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 18.664047 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 864 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 198 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 18.257781 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 896 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 177 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 4694 # DTB read hits +system.cpu.dtb.read_hits 4630 # DTB read hits system.cpu.dtb.read_misses 109 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 4803 # DTB read accesses -system.cpu.dtb.write_hits 2055 # DTB write hits -system.cpu.dtb.write_misses 93 # DTB write misses +system.cpu.dtb.read_accesses 4739 # DTB read accesses +system.cpu.dtb.write_hits 2007 # DTB write hits +system.cpu.dtb.write_misses 95 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 2148 # DTB write accesses -system.cpu.dtb.data_hits 6749 # DTB hits -system.cpu.dtb.data_misses 202 # DTB misses +system.cpu.dtb.write_accesses 2102 # DTB write accesses +system.cpu.dtb.data_hits 6637 # DTB hits +system.cpu.dtb.data_misses 204 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 6951 # DTB accesses -system.cpu.itb.fetch_hits 5431 # ITB hits -system.cpu.itb.fetch_misses 58 # ITB misses +system.cpu.dtb.data_accesses 6841 # DTB accesses +system.cpu.itb.fetch_hits 5430 # ITB hits +system.cpu.itb.fetch_misses 55 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 5489 # ITB accesses +system.cpu.itb.fetch_accesses 5485 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -257,350 +258,350 @@ system.cpu.itb.data_acv 0 # DT system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload0.num_syscalls 17 # Number of system calls system.cpu.workload1.num_syscalls 17 # Number of system calls -system.cpu.numCycles 47683 # number of cpu cycles simulated +system.cpu.numCycles 48809 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 1647 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 37826 # Number of instructions fetch has processed -system.cpu.fetch.Branches 6923 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 1814 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 6352 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1907 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 435 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.CacheLines 5431 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 913 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 28904 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.308677 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.731944 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 1620 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 37306 # Number of instructions fetch has processed +system.cpu.fetch.Branches 6717 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 1770 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 6254 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1868 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 368 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.CacheLines 5430 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 908 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 28676 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.300949 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.721933 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 22552 78.02% 78.02% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 590 2.04% 80.07% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 356 1.23% 81.30% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 460 1.59% 82.89% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 445 1.54% 84.43% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 430 1.49% 85.92% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 481 1.66% 87.58% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 392 1.36% 88.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 3198 11.06% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 22422 78.19% 78.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 547 1.91% 80.10% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 376 1.31% 81.41% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 432 1.51% 82.92% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 434 1.51% 84.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 433 1.51% 85.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 459 1.60% 87.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 528 1.84% 89.38% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 3045 10.62% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 28904 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.145188 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.793281 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 39785 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 9139 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 5505 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 442 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 2806 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 644 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 419 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 33037 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 796 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 2806 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 40500 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 6036 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 969 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 5106 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 2260 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 30593 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 58 # Number of times rename has blocked due to ROB full -system.cpu.rename.LSQFullEvents 2227 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 22886 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 37694 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 37660 # Number of integer rename lookups +system.cpu.fetch.rateDist::total 28676 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.137618 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.764326 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 39987 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 8556 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 5391 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 467 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 2766 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 575 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 354 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 32748 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 724 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 2766 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 40726 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 5410 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 972 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 5017 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 2276 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 30111 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 60 # Number of times rename has blocked due to ROB full +system.cpu.rename.LSQFullEvents 2293 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 22579 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 37089 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 37055 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 34 # Number of floating rename lookups system.cpu.rename.CommittedMaps 9140 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 13746 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 54 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 42 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 5822 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 3090 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1408 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 13 # Number of conflicting loads. +system.cpu.rename.UndoneMaps 13439 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 57 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 41 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 6273 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 3023 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1356 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 7 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. -system.cpu.memDep1.insertedLoads 3019 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep1.insertedStores 1424 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep1.conflictingLoads 3 # Number of conflicting loads. +system.cpu.memDep1.insertedLoads 3003 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep1.insertedStores 1402 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep1.conflictingLoads 1 # Number of conflicting loads. system.cpu.memDep1.conflictingStores 0 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 26797 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 83 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 22164 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 124 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 13006 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 8107 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 49 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 28904 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.766814 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.345310 # Number of insts issued each cycle +system.cpu.iq.iqInstsAdded 26482 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 81 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 21796 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 122 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 12686 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 8147 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 47 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 28676 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.760078 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.341515 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 19221 66.50% 66.50% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 3610 12.49% 78.99% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 2656 9.19% 88.18% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 1611 5.57% 93.75% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 1014 3.51% 97.26% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 491 1.70% 98.96% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 230 0.80% 99.75% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 50 0.17% 99.93% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 21 0.07% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 19237 67.08% 67.08% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 3397 11.85% 78.93% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 2648 9.23% 88.16% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 1591 5.55% 93.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 1050 3.66% 97.37% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 477 1.66% 99.04% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 210 0.73% 99.77% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 43 0.15% 99.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 23 0.08% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 28904 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 28676 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 5 2.84% 2.84% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 2.84% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 2.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 2.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 2.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 2.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.84% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 106 60.23% 63.07% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 65 36.93% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 7 4.00% 4.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 4.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 4.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 4.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 4.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 4.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 102 58.29% 62.29% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 66 37.71% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 7310 65.49% 65.51% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 1 0.01% 65.52% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 65.53% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 65.53% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 65.53% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 65.53% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 65.53% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 65.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.53% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2686 24.06% 89.60% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1161 10.40% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 7221 65.66% 65.68% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 1 0.01% 65.68% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.68% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 65.70% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 65.70% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 65.70% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 65.70% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 65.70% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 65.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.70% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2635 23.96% 89.66% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1137 10.34% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 11162 # Type of FU issued +system.cpu.iq.FU_type_0::total 10998 # Type of FU issued system.cpu.iq.FU_type_1::No_OpClass 2 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type_1::IntAlu 7255 65.94% 65.96% # Type of FU issued -system.cpu.iq.FU_type_1::IntMult 1 0.01% 65.97% # Type of FU issued -system.cpu.iq.FU_type_1::IntDiv 0 0.00% 65.97% # Type of FU issued -system.cpu.iq.FU_type_1::FloatAdd 2 0.02% 65.99% # Type of FU issued -system.cpu.iq.FU_type_1::FloatCmp 0 0.00% 65.99% # Type of FU issued -system.cpu.iq.FU_type_1::FloatCvt 0 0.00% 65.99% # Type of FU issued -system.cpu.iq.FU_type_1::FloatMult 0 0.00% 65.99% # Type of FU issued -system.cpu.iq.FU_type_1::FloatDiv 0 0.00% 65.99% # Type of FU issued -system.cpu.iq.FU_type_1::FloatSqrt 0 0.00% 65.99% # Type of FU issued -system.cpu.iq.FU_type_1::SimdAdd 0 0.00% 65.99% # Type of FU issued -system.cpu.iq.FU_type_1::SimdAddAcc 0 0.00% 65.99% # Type of FU issued -system.cpu.iq.FU_type_1::SimdAlu 0 0.00% 65.99% # Type of FU issued -system.cpu.iq.FU_type_1::SimdCmp 0 0.00% 65.99% # Type of FU issued -system.cpu.iq.FU_type_1::SimdCvt 0 0.00% 65.99% # Type of FU issued -system.cpu.iq.FU_type_1::SimdMisc 0 0.00% 65.99% # Type of FU issued -system.cpu.iq.FU_type_1::SimdMult 0 0.00% 65.99% # Type of FU issued -system.cpu.iq.FU_type_1::SimdMultAcc 0 0.00% 65.99% # Type of FU issued -system.cpu.iq.FU_type_1::SimdShift 0 0.00% 65.99% # Type of FU issued -system.cpu.iq.FU_type_1::SimdShiftAcc 0 0.00% 65.99% # Type of FU issued -system.cpu.iq.FU_type_1::SimdSqrt 0 0.00% 65.99% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatAdd 0 0.00% 65.99% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatAlu 0 0.00% 65.99% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatCmp 0 0.00% 65.99% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatCvt 0 0.00% 65.99% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatDiv 0 0.00% 65.99% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatMisc 0 0.00% 65.99% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatMult 0 0.00% 65.99% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatMultAcc 0 0.00% 65.99% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatSqrt 0 0.00% 65.99% # Type of FU issued -system.cpu.iq.FU_type_1::MemRead 2595 23.59% 89.57% # Type of FU issued -system.cpu.iq.FU_type_1::MemWrite 1147 10.43% 100.00% # Type of FU issued +system.cpu.iq.FU_type_1::IntAlu 7106 65.81% 65.83% # Type of FU issued +system.cpu.iq.FU_type_1::IntMult 1 0.01% 65.84% # Type of FU issued +system.cpu.iq.FU_type_1::IntDiv 0 0.00% 65.84% # Type of FU issued +system.cpu.iq.FU_type_1::FloatAdd 2 0.02% 65.85% # Type of FU issued +system.cpu.iq.FU_type_1::FloatCmp 0 0.00% 65.85% # Type of FU issued +system.cpu.iq.FU_type_1::FloatCvt 0 0.00% 65.85% # Type of FU issued +system.cpu.iq.FU_type_1::FloatMult 0 0.00% 65.85% # Type of FU issued +system.cpu.iq.FU_type_1::FloatDiv 0 0.00% 65.85% # Type of FU issued +system.cpu.iq.FU_type_1::FloatSqrt 0 0.00% 65.85% # Type of FU issued +system.cpu.iq.FU_type_1::SimdAdd 0 0.00% 65.85% # Type of FU issued +system.cpu.iq.FU_type_1::SimdAddAcc 0 0.00% 65.85% # Type of FU issued +system.cpu.iq.FU_type_1::SimdAlu 0 0.00% 65.85% # Type of FU issued +system.cpu.iq.FU_type_1::SimdCmp 0 0.00% 65.85% # Type of FU issued +system.cpu.iq.FU_type_1::SimdCvt 0 0.00% 65.85% # Type of FU issued +system.cpu.iq.FU_type_1::SimdMisc 0 0.00% 65.85% # Type of FU issued +system.cpu.iq.FU_type_1::SimdMult 0 0.00% 65.85% # Type of FU issued +system.cpu.iq.FU_type_1::SimdMultAcc 0 0.00% 65.85% # Type of FU issued +system.cpu.iq.FU_type_1::SimdShift 0 0.00% 65.85% # Type of FU issued +system.cpu.iq.FU_type_1::SimdShiftAcc 0 0.00% 65.85% # Type of FU issued +system.cpu.iq.FU_type_1::SimdSqrt 0 0.00% 65.85% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatAdd 0 0.00% 65.85% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatAlu 0 0.00% 65.85% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatCmp 0 0.00% 65.85% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatCvt 0 0.00% 65.85% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatDiv 0 0.00% 65.85% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatMisc 0 0.00% 65.85% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatMult 0 0.00% 65.85% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatMultAcc 0 0.00% 65.85% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatSqrt 0 0.00% 65.85% # Type of FU issued +system.cpu.iq.FU_type_1::MemRead 2582 23.91% 89.77% # Type of FU issued +system.cpu.iq.FU_type_1::MemWrite 1105 10.23% 100.00% # Type of FU issued system.cpu.iq.FU_type_1::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_1::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_1::total 11002 # Type of FU issued +system.cpu.iq.FU_type_1::total 10798 # Type of FU issued system.cpu.iq.FU_type::No_OpClass 4 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type::IntAlu 14565 65.71% 65.73% # Type of FU issued -system.cpu.iq.FU_type::IntMult 2 0.01% 65.74% # Type of FU issued -system.cpu.iq.FU_type::IntDiv 0 0.00% 65.74% # Type of FU issued -system.cpu.iq.FU_type::FloatAdd 4 0.02% 65.76% # Type of FU issued -system.cpu.iq.FU_type::FloatCmp 0 0.00% 65.76% # Type of FU issued -system.cpu.iq.FU_type::FloatCvt 0 0.00% 65.76% # Type of FU issued -system.cpu.iq.FU_type::FloatMult 0 0.00% 65.76% # Type of FU issued -system.cpu.iq.FU_type::FloatDiv 0 0.00% 65.76% # Type of FU issued -system.cpu.iq.FU_type::FloatSqrt 0 0.00% 65.76% # Type of FU issued -system.cpu.iq.FU_type::SimdAdd 0 0.00% 65.76% # Type of FU issued -system.cpu.iq.FU_type::SimdAddAcc 0 0.00% 65.76% # Type of FU issued -system.cpu.iq.FU_type::SimdAlu 0 0.00% 65.76% # Type of FU issued -system.cpu.iq.FU_type::SimdCmp 0 0.00% 65.76% # Type of FU issued -system.cpu.iq.FU_type::SimdCvt 0 0.00% 65.76% # Type of FU issued -system.cpu.iq.FU_type::SimdMisc 0 0.00% 65.76% # Type of FU issued -system.cpu.iq.FU_type::SimdMult 0 0.00% 65.76% # Type of FU issued -system.cpu.iq.FU_type::SimdMultAcc 0 0.00% 65.76% # Type of FU issued -system.cpu.iq.FU_type::SimdShift 0 0.00% 65.76% # Type of FU issued -system.cpu.iq.FU_type::SimdShiftAcc 0 0.00% 65.76% # Type of FU issued -system.cpu.iq.FU_type::SimdSqrt 0 0.00% 65.76% # Type of FU issued -system.cpu.iq.FU_type::SimdFloatAdd 0 0.00% 65.76% # Type of FU issued -system.cpu.iq.FU_type::SimdFloatAlu 0 0.00% 65.76% # Type of FU issued -system.cpu.iq.FU_type::SimdFloatCmp 0 0.00% 65.76% # Type of FU issued -system.cpu.iq.FU_type::SimdFloatCvt 0 0.00% 65.76% # Type of FU issued -system.cpu.iq.FU_type::SimdFloatDiv 0 0.00% 65.76% # Type of FU issued -system.cpu.iq.FU_type::SimdFloatMisc 0 0.00% 65.76% # Type of FU issued -system.cpu.iq.FU_type::SimdFloatMult 0 0.00% 65.76% # Type of FU issued -system.cpu.iq.FU_type::SimdFloatMultAcc 0 0.00% 65.76% # Type of FU issued -system.cpu.iq.FU_type::SimdFloatSqrt 0 0.00% 65.76% # Type of FU issued -system.cpu.iq.FU_type::MemRead 5281 23.83% 89.59% # Type of FU issued -system.cpu.iq.FU_type::MemWrite 2308 10.41% 100.00% # Type of FU issued +system.cpu.iq.FU_type::IntAlu 14327 65.73% 65.75% # Type of FU issued +system.cpu.iq.FU_type::IntMult 2 0.01% 65.76% # Type of FU issued +system.cpu.iq.FU_type::IntDiv 0 0.00% 65.76% # Type of FU issued +system.cpu.iq.FU_type::FloatAdd 4 0.02% 65.78% # Type of FU issued +system.cpu.iq.FU_type::FloatCmp 0 0.00% 65.78% # Type of FU issued +system.cpu.iq.FU_type::FloatCvt 0 0.00% 65.78% # Type of FU issued +system.cpu.iq.FU_type::FloatMult 0 0.00% 65.78% # Type of FU issued +system.cpu.iq.FU_type::FloatDiv 0 0.00% 65.78% # Type of FU issued +system.cpu.iq.FU_type::FloatSqrt 0 0.00% 65.78% # Type of FU issued +system.cpu.iq.FU_type::SimdAdd 0 0.00% 65.78% # Type of FU issued +system.cpu.iq.FU_type::SimdAddAcc 0 0.00% 65.78% # Type of FU issued +system.cpu.iq.FU_type::SimdAlu 0 0.00% 65.78% # Type of FU issued +system.cpu.iq.FU_type::SimdCmp 0 0.00% 65.78% # Type of FU issued +system.cpu.iq.FU_type::SimdCvt 0 0.00% 65.78% # Type of FU issued +system.cpu.iq.FU_type::SimdMisc 0 0.00% 65.78% # Type of FU issued +system.cpu.iq.FU_type::SimdMult 0 0.00% 65.78% # Type of FU issued +system.cpu.iq.FU_type::SimdMultAcc 0 0.00% 65.78% # Type of FU issued +system.cpu.iq.FU_type::SimdShift 0 0.00% 65.78% # Type of FU issued +system.cpu.iq.FU_type::SimdShiftAcc 0 0.00% 65.78% # Type of FU issued +system.cpu.iq.FU_type::SimdSqrt 0 0.00% 65.78% # Type of FU issued +system.cpu.iq.FU_type::SimdFloatAdd 0 0.00% 65.78% # Type of FU issued +system.cpu.iq.FU_type::SimdFloatAlu 0 0.00% 65.78% # Type of FU issued +system.cpu.iq.FU_type::SimdFloatCmp 0 0.00% 65.78% # Type of FU issued +system.cpu.iq.FU_type::SimdFloatCvt 0 0.00% 65.78% # Type of FU issued +system.cpu.iq.FU_type::SimdFloatDiv 0 0.00% 65.78% # Type of FU issued +system.cpu.iq.FU_type::SimdFloatMisc 0 0.00% 65.78% # Type of FU issued +system.cpu.iq.FU_type::SimdFloatMult 0 0.00% 65.78% # Type of FU issued +system.cpu.iq.FU_type::SimdFloatMultAcc 0 0.00% 65.78% # Type of FU issued +system.cpu.iq.FU_type::SimdFloatSqrt 0 0.00% 65.78% # Type of FU issued +system.cpu.iq.FU_type::MemRead 5217 23.94% 89.71% # Type of FU issued +system.cpu.iq.FU_type::MemWrite 2242 10.29% 100.00% # Type of FU issued system.cpu.iq.FU_type::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type::total 22164 # Type of FU issued -system.cpu.iq.rate 0.464820 # Inst issue rate -system.cpu.iq.fu_busy_cnt::0 86 # FU busy when requested -system.cpu.iq.fu_busy_cnt::1 90 # FU busy when requested -system.cpu.iq.fu_busy_cnt::total 176 # FU busy when requested -system.cpu.iq.fu_busy_rate::0 0.003880 # FU busy rate (busy events/executed inst) -system.cpu.iq.fu_busy_rate::1 0.004061 # FU busy rate (busy events/executed inst) -system.cpu.iq.fu_busy_rate::total 0.007941 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 73490 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 39895 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 19126 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type::total 21796 # Type of FU issued +system.cpu.iq.rate 0.446557 # Inst issue rate +system.cpu.iq.fu_busy_cnt::0 89 # FU busy when requested +system.cpu.iq.fu_busy_cnt::1 86 # FU busy when requested +system.cpu.iq.fu_busy_cnt::total 175 # FU busy when requested +system.cpu.iq.fu_busy_rate::0 0.004083 # FU busy rate (busy events/executed inst) +system.cpu.iq.fu_busy_rate::1 0.003946 # FU busy rate (busy events/executed inst) +system.cpu.iq.fu_busy_rate::total 0.008029 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 72523 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 39256 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 18760 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 42 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 20 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 20 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 22314 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 21945 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 22 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 66 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 52 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1907 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 15 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 543 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 1840 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 1 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 16 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 491 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 358 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread1.forwLoads 56 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.cacheBlocked 395 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread1.forwLoads 48 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread1.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread1.squashedLoads 1836 # Number of loads squashed -system.cpu.iew.lsq.thread1.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread1.memOrderViolation 16 # Number of memory ordering violations -system.cpu.iew.lsq.thread1.squashedStores 559 # Number of stores squashed +system.cpu.iew.lsq.thread1.squashedLoads 1820 # Number of loads squashed +system.cpu.iew.lsq.thread1.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread1.memOrderViolation 13 # Number of memory ordering violations +system.cpu.iew.lsq.thread1.squashedStores 537 # Number of stores squashed system.cpu.iew.lsq.thread1.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread1.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread1.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread1.cacheBlocked 384 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread1.cacheBlocked 395 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 2806 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 2710 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 46 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 27087 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 546 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 6109 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 2832 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 83 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 23 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 2 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 31 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 255 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 1078 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1333 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 20623 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts::0 2441 # Number of load instructions executed -system.cpu.iew.iewExecLoadInsts::1 2376 # Number of load instructions executed -system.cpu.iew.iewExecLoadInsts::total 4817 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1541 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 2766 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 2054 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 41 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 26762 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 628 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 6026 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 2758 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 81 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 20 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 1 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 29 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 225 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 1067 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1292 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 20286 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts::0 2395 # Number of load instructions executed +system.cpu.iew.iewExecLoadInsts::1 2362 # Number of load instructions executed +system.cpu.iew.iewExecLoadInsts::total 4757 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1510 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp::0 0 # number of swp insts executed system.cpu.iew.exec_swp::1 0 # number of swp insts executed system.cpu.iew.exec_swp::total 0 # number of swp insts executed -system.cpu.iew.exec_nop::0 115 # number of nop insts executed -system.cpu.iew.exec_nop::1 92 # number of nop insts executed -system.cpu.iew.exec_nop::total 207 # number of nop insts executed -system.cpu.iew.exec_refs::0 3520 # number of memory reference insts executed -system.cpu.iew.exec_refs::1 3467 # number of memory reference insts executed -system.cpu.iew.exec_refs::total 6987 # number of memory reference insts executed -system.cpu.iew.exec_branches::0 1642 # Number of branches executed -system.cpu.iew.exec_branches::1 1654 # Number of branches executed -system.cpu.iew.exec_branches::total 3296 # Number of branches executed -system.cpu.iew.exec_stores::0 1079 # Number of stores executed -system.cpu.iew.exec_stores::1 1091 # Number of stores executed -system.cpu.iew.exec_stores::total 2170 # Number of stores executed -system.cpu.iew.exec_rate 0.432502 # Inst execution rate -system.cpu.iew.wb_sent::0 9753 # cumulative count of insts sent to commit -system.cpu.iew.wb_sent::1 9719 # cumulative count of insts sent to commit -system.cpu.iew.wb_sent::total 19472 # cumulative count of insts sent to commit -system.cpu.iew.wb_count::0 9565 # cumulative count of insts written-back -system.cpu.iew.wb_count::1 9581 # cumulative count of insts written-back -system.cpu.iew.wb_count::total 19146 # cumulative count of insts written-back -system.cpu.iew.wb_producers::0 4912 # num instructions producing a value -system.cpu.iew.wb_producers::1 4854 # num instructions producing a value -system.cpu.iew.wb_producers::total 9766 # num instructions producing a value -system.cpu.iew.wb_consumers::0 6410 # num instructions consuming a value -system.cpu.iew.wb_consumers::1 6363 # num instructions consuming a value -system.cpu.iew.wb_consumers::total 12773 # num instructions consuming a value +system.cpu.iew.exec_nop::0 112 # number of nop insts executed +system.cpu.iew.exec_nop::1 87 # number of nop insts executed +system.cpu.iew.exec_nop::total 199 # number of nop insts executed +system.cpu.iew.exec_refs::0 3467 # number of memory reference insts executed +system.cpu.iew.exec_refs::1 3404 # number of memory reference insts executed +system.cpu.iew.exec_refs::total 6871 # number of memory reference insts executed +system.cpu.iew.exec_branches::0 1580 # Number of branches executed +system.cpu.iew.exec_branches::1 1582 # Number of branches executed +system.cpu.iew.exec_branches::total 3162 # Number of branches executed +system.cpu.iew.exec_stores::0 1072 # Number of stores executed +system.cpu.iew.exec_stores::1 1042 # Number of stores executed +system.cpu.iew.exec_stores::total 2114 # Number of stores executed +system.cpu.iew.exec_rate 0.415620 # Inst execution rate +system.cpu.iew.wb_sent::0 9597 # cumulative count of insts sent to commit +system.cpu.iew.wb_sent::1 9491 # cumulative count of insts sent to commit +system.cpu.iew.wb_sent::total 19088 # cumulative count of insts sent to commit +system.cpu.iew.wb_count::0 9418 # cumulative count of insts written-back +system.cpu.iew.wb_count::1 9362 # cumulative count of insts written-back +system.cpu.iew.wb_count::total 18780 # cumulative count of insts written-back +system.cpu.iew.wb_producers::0 4881 # num instructions producing a value +system.cpu.iew.wb_producers::1 4800 # num instructions producing a value +system.cpu.iew.wb_producers::total 9681 # num instructions producing a value +system.cpu.iew.wb_consumers::0 6383 # num instructions consuming a value +system.cpu.iew.wb_consumers::1 6247 # num instructions consuming a value +system.cpu.iew.wb_consumers::total 12630 # num instructions consuming a value system.cpu.iew.wb_penalized::0 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.wb_penalized::1 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.wb_penalized::total 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate::0 0.200596 # insts written-back per cycle -system.cpu.iew.wb_rate::1 0.200931 # insts written-back per cycle -system.cpu.iew.wb_rate::total 0.401527 # insts written-back per cycle -system.cpu.iew.wb_fanout::0 0.766303 # average fanout of values written-back -system.cpu.iew.wb_fanout::1 0.762848 # average fanout of values written-back -system.cpu.iew.wb_fanout::total 0.764582 # average fanout of values written-back +system.cpu.iew.wb_rate::0 0.192956 # insts written-back per cycle +system.cpu.iew.wb_rate::1 0.191809 # insts written-back per cycle +system.cpu.iew.wb_rate::total 0.384765 # insts written-back per cycle +system.cpu.iew.wb_fanout::0 0.764687 # average fanout of values written-back +system.cpu.iew.wb_fanout::1 0.768369 # average fanout of values written-back +system.cpu.iew.wb_fanout::total 0.766508 # average fanout of values written-back system.cpu.iew.wb_penalized_rate::0 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.iew.wb_penalized_rate::1 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.iew.wb_penalized_rate::total 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 14336 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 13991 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 34 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1138 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 28841 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.443084 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.197327 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 1133 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 28610 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.446662 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.213615 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 22992 79.72% 79.72% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 3164 10.97% 90.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 1129 3.91% 94.60% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 501 1.74% 96.34% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 358 1.24% 97.58% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 236 0.82% 98.40% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 188 0.65% 99.05% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 70 0.24% 99.30% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 203 0.70% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 22891 80.01% 80.01% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 3017 10.55% 90.56% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 1097 3.83% 94.39% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 546 1.91% 96.30% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 330 1.15% 97.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 253 0.88% 98.34% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 201 0.70% 99.04% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 61 0.21% 99.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 214 0.75% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 28841 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 28610 # Number of insts commited each cycle system.cpu.commit.committedInsts::0 6390 # Number of instructions committed system.cpu.commit.committedInsts::1 6389 # Number of instructions committed system.cpu.commit.committedInsts::total 12779 # Number of instructions committed @@ -631,210 +632,210 @@ system.cpu.commit.int_insts::total 12614 # Nu system.cpu.commit.function_calls::0 127 # Number of function calls committed. system.cpu.commit.function_calls::1 127 # Number of function calls committed. system.cpu.commit.function_calls::total 254 # Number of function calls committed. -system.cpu.commit.bw_lim_events 203 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 214 # number cycles where commit BW limit reached system.cpu.commit.bw_limited::0 0 # number of insts not committed due to BW limits system.cpu.commit.bw_limited::1 0 # number of insts not committed due to BW limits system.cpu.commit.bw_limited::total 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 132883 # The number of ROB reads -system.cpu.rob.rob_writes 57054 # The number of ROB writes -system.cpu.timesIdled 370 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 18779 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 131690 # The number of ROB reads +system.cpu.rob.rob_writes 56322 # The number of ROB writes +system.cpu.timesIdled 365 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 20133 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts::0 6373 # Number of Instructions Simulated system.cpu.committedInsts::1 6372 # Number of Instructions Simulated system.cpu.committedOps::0 6373 # Number of Ops (including micro ops) Simulated system.cpu.committedOps::1 6372 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 12745 # Number of Instructions Simulated -system.cpu.cpi::0 7.482034 # CPI: Cycles Per Instruction -system.cpu.cpi::1 7.483208 # CPI: Cycles Per Instruction -system.cpu.cpi_total 3.741310 # CPI: Total CPI of All Threads -system.cpu.ipc::0 0.133654 # IPC: Instructions Per Cycle -system.cpu.ipc::1 0.133633 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.267286 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 25857 # number of integer regfile reads -system.cpu.int_regfile_writes 14461 # number of integer regfile writes +system.cpu.cpi::0 7.658716 # CPI: Cycles Per Instruction +system.cpu.cpi::1 7.659918 # CPI: Cycles Per Instruction +system.cpu.cpi_total 3.829659 # CPI: Total CPI of All Threads +system.cpu.ipc::0 0.130570 # IPC: Instructions Per Cycle +system.cpu.ipc::1 0.130550 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.261120 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 25473 # number of integer regfile reads +system.cpu.int_regfile_writes 14213 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads system.cpu.fp_regfile_writes 4 # number of floating regfile writes system.cpu.misc_regfile_reads 2 # number of misc regfile reads system.cpu.misc_regfile_writes 2 # number of misc regfile writes -system.cpu.toL2Bus.throughput 2622708779 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 831 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 831 # Transaction distribution +system.cpu.toL2Bus.throughput 2559580397 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 830 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 830 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 146 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 146 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1254 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1252 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 700 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count 1954 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 40128 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count 1952 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 40064 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 22400 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size 62528 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 62528 # Total data (bytes) +system.cpu.toL2Bus.tot_pkt_size 62464 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 62464 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 488500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.occupancy 488000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 2.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 940500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 3.9 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 525000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 2.2 # Layer utilization (%) -system.cpu.icache.replacements::0 6 # number of replacements -system.cpu.icache.replacements::1 0 # number of replacements -system.cpu.icache.replacements::total 6 # number of replacements -system.cpu.icache.tagsinuse 313.799979 # Cycle average of tags in use -system.cpu.icache.total_refs 4370 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 627 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 6.969697 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 313.799979 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.153223 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.153223 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 4370 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 4370 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 4370 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 4370 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 4370 # number of overall hits -system.cpu.icache.overall_hits::total 4370 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1055 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1055 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1055 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1055 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1055 # number of overall misses -system.cpu.icache.overall_misses::total 1055 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 67889996 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 67889996 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 67889996 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 67889996 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 67889996 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 67889996 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 5425 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 5425 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 5425 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 5425 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 5425 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 5425 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.194470 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.194470 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.194470 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.194470 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.194470 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.194470 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 64350.707109 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 64350.707109 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 64350.707109 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 64350.707109 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 64350.707109 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 64350.707109 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 2740 # number of cycles access was blocked +system.cpu.toL2Bus.respLayer0.occupancy 1029500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 4.2 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 566500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 2.3 # Layer utilization (%) +system.cpu.icache.tags.replacements::0 6 # number of replacements +system.cpu.icache.tags.replacements::1 0 # number of replacements +system.cpu.icache.tags.replacements::total 6 # number of replacements +system.cpu.icache.tags.tagsinuse 309.632563 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 4375 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 626 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 6.988818 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 309.632563 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.151188 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.151188 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 4375 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 4375 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 4375 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 4375 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 4375 # number of overall hits +system.cpu.icache.overall_hits::total 4375 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1049 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1049 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1049 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1049 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1049 # number of overall misses +system.cpu.icache.overall_misses::total 1049 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 69677745 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 69677745 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 69677745 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 69677745 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 69677745 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 69677745 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 5424 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 5424 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 5424 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 5424 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 5424 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 5424 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.193400 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.193400 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.193400 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.193400 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.193400 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.193400 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 66423.017159 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 66423.017159 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 66423.017159 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 66423.017159 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 66423.017159 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 66423.017159 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 2785 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 65 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 57 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 42.153846 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 48.859649 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 428 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 428 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 428 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 428 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 428 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 428 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 627 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 627 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 627 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 627 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 627 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 627 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 45895996 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 45895996 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 45895996 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 45895996 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 45895996 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 45895996 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.115576 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.115576 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.115576 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.115576 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.115576 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.115576 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 73199.355662 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 73199.355662 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 73199.355662 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 73199.355662 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 73199.355662 # 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number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 626 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 46998246 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 46998246 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 46998246 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 46998246 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 46998246 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 46998246 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.115413 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.115413 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.115413 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.115413 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.115413 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.115413 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75077.070288 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75077.070288 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75077.070288 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 75077.070288 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75077.070288 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 75077.070288 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements::0 0 # number of replacements -system.cpu.l2cache.replacements::1 0 # number of replacements -system.cpu.l2cache.replacements::total 0 # number of replacements -system.cpu.l2cache.tagsinuse 433.839977 # Cycle average of tags in use -system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 829 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.002413 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 314.320815 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 119.519162 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.009592 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.003647 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.013240 # Average percentage of cache occupancy +system.cpu.l2cache.tags.replacements::0 0 # number of replacements +system.cpu.l2cache.tags.replacements::1 0 # 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number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.data 350 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 975 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 625 # number of overall misses +system.cpu.l2cache.demand_misses::total 974 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 624 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 350 # number of overall misses -system.cpu.l2cache.overall_misses::total 975 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 45246000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 16414000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 61660000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 10461000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 10461000 # 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number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.083697 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.083697 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.412139 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.412139 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.184711 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.184711 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.184711 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.184711 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 71434.049080 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 71434.049080 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60344.230014 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 60344.230014 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 63823.807507 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 63823.807507 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 63823.807507 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 63823.807507 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 4266 # number of cycles access was blocked +system.cpu.dcache.demand_accesses::cpu.data 5523 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 5523 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 5523 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 5523 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.085421 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.085421 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.408092 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.408092 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.186493 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.186493 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.186493 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.186493 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 70849.537037 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 70849.537037 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 69230.805949 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 69230.805949 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 69739.999029 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 69739.999029 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 69739.999029 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 69739.999029 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 4722 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 128 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 117 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 33.328125 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 40.358974 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 122 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 122 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 567 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 567 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 689 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 689 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 689 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 689 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 120 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 120 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 560 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 560 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 680 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 680 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 680 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 680 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 204 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 204 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 146 # number of WriteReq MSHR misses @@ -971,30 +972,30 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 350 system.cpu.dcache.demand_mshr_misses::total 350 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 350 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 350 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 16628000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 16628000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10609995 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 10609995 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 27237995 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 27237995 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 27237995 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 27237995 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.052375 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.052375 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 16427250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 16427250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12061996 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 12061996 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 28489246 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 28489246 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28489246 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 28489246 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.053783 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.053783 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.062222 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.062222 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.062222 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.062222 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 81509.803922 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 81509.803922 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 72671.198630 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 72671.198630 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 77822.842857 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 77822.842857 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 77822.842857 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 77822.842857 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.063371 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.063371 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.063371 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.063371 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 80525.735294 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 80525.735294 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 82616.410959 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 82616.410959 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 81397.845714 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 81397.845714 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 81397.845714 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 81397.845714 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt index d7ab6a34e..60e6f3a9f 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt +++ b/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000027 # Number of seconds simulated -sim_ticks 27167500 # Number of ticks simulated -final_tick 27167500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 27282000 # Number of ticks simulated +final_tick 27282000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 49297 # Simulator instruction rate (inst/s) -host_op_rate 49293 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 88314525 # Simulator tick rate (ticks/s) -host_mem_usage 232472 # Number of bytes of host memory used -host_seconds 0.31 # Real time elapsed on the host +host_inst_rate 50184 # Simulator instruction rate (inst/s) +host_op_rate 50180 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 90285398 # Simulator tick rate (ticks/s) +host_mem_usage 232468 # Number of bytes of host memory used +host_seconds 0.30 # Real time elapsed on the host sim_insts 15162 # Number of instructions simulated sim_ops 15162 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 19072 # Number of bytes read from this memory @@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 19072 # Nu system.physmem.num_reads::cpu.inst 298 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 138 # Number of read requests responded to by this memory system.physmem.num_reads::total 436 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 702015276 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 325094322 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1027109598 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 702015276 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 702015276 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 702015276 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 325094322 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1027109598 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 699068983 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 323729932 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1022798915 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 699068983 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 699068983 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 699068983 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 323729932 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1022798915 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 436 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen system.physmem.cpureqs 436 # Reqs generatd by CPU via cache - shady @@ -70,7 +70,7 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 27134000 # Total gap between requests +system.physmem.totGap 27248500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes @@ -169,28 +169,28 @@ system.physmem.bytesPerActivate::1856 1 2.04% 95.92% # By system.physmem.bytesPerActivate::1920 1 2.04% 97.96% # Bytes accessed per row activation system.physmem.bytesPerActivate::2048 1 2.04% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 49 # Bytes accessed per row activation -system.physmem.totQLat 1645750 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 10137000 # Sum of mem lat for all requests +system.physmem.totQLat 1525500 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 10030500 # Sum of mem lat for all requests system.physmem.totBusLat 2180000 # Total cycles spent in databus access -system.physmem.totBankLat 6311250 # Total cycles spent in bank access -system.physmem.avgQLat 3774.66 # Average queueing delay per request -system.physmem.avgBankLat 14475.34 # Average bank access latency per request +system.physmem.totBankLat 6325000 # Total cycles spent in bank access +system.physmem.avgQLat 3498.85 # Average queueing delay per request +system.physmem.avgBankLat 14506.88 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 23250.00 # Average memory access latency -system.physmem.avgRdBW 1027.11 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 23005.73 # Average memory access latency +system.physmem.avgRdBW 1022.80 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 1027.11 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 1022.80 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 8.02 # Data bus utilization in percentage +system.physmem.busUtil 7.99 # Data bus utilization in percentage system.physmem.avgRdQLen 0.37 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time system.physmem.readRowHits 387 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 88.76 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 62233.94 # Average gap between requests -system.membus.throughput 1024753842 # Throughput (bytes/s) +system.physmem.avgGap 62496.56 # Average gap between requests +system.membus.throughput 1020453046 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 351 # Transaction distribution system.membus.trans_dist::ReadResp 350 # Transaction distribution system.membus.trans_dist::ReadExReq 85 # Transaction distribution @@ -203,7 +203,7 @@ system.membus.data_through_bus 27840 # To system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.membus.reqLayer0.occupancy 519000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 1.9 # Layer utilization (%) -system.membus.respLayer1.occupancy 4057250 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 4055250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 14.9 # Layer utilization (%) system.cpu.branchPred.lookups 5146 # Number of BP lookups system.cpu.branchPred.condPredicted 3529 # Number of conditional branches predicted @@ -215,7 +215,7 @@ system.cpu.branchPred.BTBHitPct 66.317073 # BT system.cpu.branchPred.usedRAS 174 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 5 # Number of incorrect RAS predictions. system.cpu.workload.num_syscalls 18 # Number of system calls -system.cpu.numCycles 54336 # number of cpu cycles simulated +system.cpu.numCycles 54565 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.branch_predictor.predictedTaken 2893 # Number of Branches Predicted As Taken (True). @@ -237,12 +237,12 @@ system.cpu.execution_unit.executions 11045 # Nu system.cpu.mult_div_unit.multiplies 0 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 21896 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 21826 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 498 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 36768 # Number of cycles cpu's stages were not processed +system.cpu.timesIdled 430 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 36997 # Number of cycles cpu's stages were not processed system.cpu.runCycles 17568 # Number of cycles cpu stages are processed. -system.cpu.activity 32.332155 # Percentage of cycles cpu is active +system.cpu.activity 32.196463 # Percentage of cycles cpu is active system.cpu.comLoads 2225 # Number of Load instructions committed system.cpu.comStores 1448 # Number of Store instructions committed system.cpu.comBranches 3358 # Number of Branches instructions committed @@ -254,36 +254,36 @@ system.cpu.committedInsts 15162 # Nu system.cpu.committedOps 15162 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 15162 # Number of Instructions committed (Total) -system.cpu.cpi 3.583696 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 3.598800 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 3.583696 # CPI: Total CPI of All Threads -system.cpu.ipc 0.279042 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 3.598800 # CPI: Total CPI of All Threads +system.cpu.ipc 0.277870 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 0.279042 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 40910 # Number of cycles 0 instructions are processed. +system.cpu.ipc_total 0.277870 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 41139 # Number of cycles 0 instructions are processed. system.cpu.stage0.runCycles 13426 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 24.709217 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 44983 # Number of cycles 0 instructions are processed. +system.cpu.stage0.utilization 24.605516 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 45212 # Number of cycles 0 instructions are processed. system.cpu.stage1.runCycles 9353 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 17.213266 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 45533 # Number of cycles 0 instructions are processed. +system.cpu.stage1.utilization 17.141024 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 45762 # Number of cycles 0 instructions are processed. system.cpu.stage2.runCycles 8803 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 16.201045 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 51458 # Number of cycles 0 instructions are processed. +system.cpu.stage2.utilization 16.133052 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 51687 # Number of cycles 0 instructions are processed. system.cpu.stage3.runCycles 2878 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 5.296673 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 45027 # Number of cycles 0 instructions are processed. +system.cpu.stage3.utilization 5.274443 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 45256 # Number of cycles 0 instructions are processed. system.cpu.stage4.runCycles 9309 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 17.132288 # Percentage of cycles stage was utilized (processing insts). -system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 168.384950 # Cycle average of tags in use -system.cpu.icache.total_refs 3004 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 299 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 10.046823 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 168.384950 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.082219 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.082219 # Average percentage of cache occupancy +system.cpu.stage4.utilization 17.060387 # Percentage of cycles stage was utilized (processing insts). +system.cpu.icache.tags.replacements 0 # number of replacements +system.cpu.icache.tags.tagsinuse 168.400745 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 3004 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 299 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 10.046823 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 168.400745 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.082227 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.082227 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 3004 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 3004 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 3004 # number of demand (read+write) hits @@ -296,12 +296,12 @@ system.cpu.icache.demand_misses::cpu.inst 381 # n system.cpu.icache.demand_misses::total 381 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 381 # number of overall misses system.cpu.icache.overall_misses::total 381 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 25319500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 25319500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 25319500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 25319500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 25319500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 25319500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 25440250 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 25440250 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 25440250 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 25440250 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 25440250 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 25440250 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 3385 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 3385 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 3385 # number of demand (read+write) accesses @@ -314,12 +314,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.112555 system.cpu.icache.demand_miss_rate::total 0.112555 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.112555 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.112555 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 66455.380577 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 66455.380577 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 66455.380577 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 66455.380577 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 66455.380577 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 66455.380577 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 66772.309711 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 66772.309711 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 66772.309711 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 66772.309711 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 66772.309711 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 66772.309711 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -340,26 +340,26 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 301 system.cpu.icache.demand_mshr_misses::total 301 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 301 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 301 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 20038500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 20038500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 20038500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 20038500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 20038500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 20038500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 19991500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 19991500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 19991500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 19991500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 19991500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 19991500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.088922 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.088922 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.088922 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.088922 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.088922 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.088922 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66573.089701 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66573.089701 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66573.089701 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 66573.089701 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66573.089701 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 66573.089701 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66416.943522 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66416.943522 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66416.943522 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 66416.943522 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66416.943522 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 66416.943522 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 1029465354 # Throughput (bytes/s) +system.cpu.toL2Bus.throughput 1025144784 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 354 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 352 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 85 # Transaction distribution @@ -374,21 +374,21 @@ system.cpu.toL2Bus.data_through_bus 27968 # To system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 219500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.8 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 448500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 1.7 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 207000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 507000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 1.9 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 223250 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) -system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 199.348050 # Cycle average of tags in use -system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 350 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.005714 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 167.722707 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 31.625344 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.005118 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.000965 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.006084 # Average percentage of cache occupancy +system.cpu.l2cache.tags.replacements 0 # number of replacements +system.cpu.l2cache.tags.tagsinuse 199.371038 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 350 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.005714 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::cpu.inst 167.740493 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 31.630545 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005119 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.000965 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.006084 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits @@ -406,17 +406,17 @@ system.cpu.l2cache.demand_misses::total 437 # nu system.cpu.l2cache.overall_misses::cpu.inst 299 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 138 # number of overall misses system.cpu.l2cache.overall_misses::total 437 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 19715000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3728500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 23443500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5878000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 5878000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 19715000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 9606500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 29321500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 19715000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 9606500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 29321500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 19668000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3736000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 23404000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5885250 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 5885250 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 19668000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 9621250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 29289250 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 19668000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 9621250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 29289250 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 301 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 53 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 354 # number of ReadReq accesses(hits+misses) @@ -439,17 +439,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.995444 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993355 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.995444 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 65936.454849 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 70349.056604 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 66600.852273 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 69152.941176 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69152.941176 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 65936.454849 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 69612.318841 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 67097.254005 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 65936.454849 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 69612.318841 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 67097.254005 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 65779.264214 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 70490.566038 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 66488.636364 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 69238.235294 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69238.235294 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 65779.264214 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 69719.202899 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 67023.455378 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 65779.264214 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 69719.202899 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 67023.455378 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -469,17 +469,17 @@ system.cpu.l2cache.demand_mshr_misses::total 437 system.cpu.l2cache.overall_mshr_misses::cpu.inst 299 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 437 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 16042000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3076500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 19118500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 15937500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3076000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 19013500 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4840750 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4840750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 16042000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7917250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 23959250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 16042000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7917250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 23959250 # number of overall MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 15937500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7916750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 23854250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 15937500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7916750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 23854250 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993355 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.994350 # mshr miss rate for ReadReq accesses @@ -491,27 +491,27 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.995444 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993355 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.995444 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 53652.173913 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 58047.169811 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 54313.920455 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 53302.675585 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 58037.735849 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 54015.625000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56950 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56950 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 53652.173913 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57371.376812 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54826.659039 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 53652.173913 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57371.376812 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54826.659039 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 53302.675585 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57367.753623 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54586.384439 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 53302.675585 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57367.753623 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54586.384439 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 98.129274 # Cycle average of tags in use -system.cpu.dcache.total_refs 3193 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 138 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 23.137681 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 98.129274 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.023957 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.023957 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 0 # number of replacements +system.cpu.dcache.tags.tagsinuse 98.106033 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 3193 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 138 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 23.137681 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 98.106033 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.023952 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.023952 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 2167 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 2167 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 1020 # number of WriteReq hits @@ -530,14 +530,14 @@ system.cpu.dcache.demand_misses::cpu.data 480 # n system.cpu.dcache.demand_misses::total 480 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 480 # number of overall misses system.cpu.dcache.overall_misses::total 480 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 4284500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 4284500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 25306500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 25306500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 29591000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 29591000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 29591000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 29591000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 4310500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 4310500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 25385000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 25385000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 29695500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 29695500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 29695500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 29695500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 2225 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 2225 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 1442 # number of WriteReq accesses(hits+misses) @@ -556,19 +556,19 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.130897 system.cpu.dcache.demand_miss_rate::total 0.130897 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.130897 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.130897 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 73870.689655 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 73870.689655 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 59968.009479 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 59968.009479 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 61647.916667 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 61647.916667 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 61647.916667 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 61647.916667 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 1016 # number of cycles access was blocked +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 74318.965517 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 74318.965517 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60154.028436 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 60154.028436 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 61865.625000 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 61865.625000 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 61865.625000 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 61865.625000 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 1022 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 34 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 33 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 29.882353 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 30.969697 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed @@ -588,14 +588,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 138 system.cpu.dcache.demand_mshr_misses::total 138 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 138 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3783000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 3783000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5966000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5966000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9749000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 9749000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9749000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 9749000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3790500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 3790500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5973250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5973250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9763750 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 9763750 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9763750 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 9763750 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.023820 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.023820 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.058946 # mshr miss rate for WriteReq accesses @@ -604,14 +604,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.037633 system.cpu.dcache.demand_mshr_miss_rate::total 0.037633 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.037633 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.037633 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 71377.358491 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 71377.358491 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 70188.235294 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 70188.235294 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 70644.927536 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 70644.927536 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 70644.927536 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 70644.927536 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 71518.867925 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 71518.867925 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 70273.529412 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 70273.529412 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 70751.811594 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 70751.811594 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 70751.811594 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 70751.811594 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt index 3e2a9c814..5128d5dc2 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt +++ b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000026 # Number of seconds simulated -sim_ticks 26399500 # Number of ticks simulated -final_tick 26399500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000027 # Number of seconds simulated +sim_ticks 26524500 # Number of ticks simulated +final_tick 26524500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 93938 # Simulator instruction rate (inst/s) -host_op_rate 93929 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 171756334 # Simulator tick rate (ticks/s) +host_inst_rate 52714 # Simulator instruction rate (inst/s) +host_op_rate 52709 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 96835127 # Simulator tick rate (ticks/s) host_mem_usage 234512 # Number of bytes of host memory used -host_seconds 0.15 # Real time elapsed on the host +host_seconds 0.27 # Real time elapsed on the host sim_insts 14436 # Number of instructions simulated sim_ops 14436 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 21440 # Number of bytes read from this memory @@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 21440 # Nu system.physmem.num_reads::cpu.inst 335 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 147 # Number of read requests responded to by this memory system.physmem.num_reads::total 482 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 812136593 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 356370386 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1168506979 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 812136593 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 812136593 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 812136593 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 356370386 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1168506979 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 808309299 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 354690946 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1163000245 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 808309299 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 808309299 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 808309299 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 354690946 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1163000245 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 482 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen system.physmem.cpureqs 482 # Reqs generatd by CPU via cache - shady @@ -70,7 +70,7 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 26239500 # Total gap between requests +system.physmem.totGap 26363500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes @@ -85,8 +85,8 @@ system.physmem.writePktSize::3 0 # Ca system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes system.physmem.writePktSize::6 0 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 288 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 133 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 287 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 134 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 50 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 7 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see @@ -168,28 +168,28 @@ system.physmem.bytesPerActivate::1856 2 3.85% 96.15% # By system.physmem.bytesPerActivate::2112 1 1.92% 98.08% # Bytes accessed per row activation system.physmem.bytesPerActivate::2176 1 1.92% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 52 # Bytes accessed per row activation -system.physmem.totQLat 1765750 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 10927000 # Sum of mem lat for all requests +system.physmem.totQLat 1755500 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 10930500 # Sum of mem lat for all requests system.physmem.totBusLat 2410000 # Total cycles spent in databus access -system.physmem.totBankLat 6751250 # Total cycles spent in bank access -system.physmem.avgQLat 3663.38 # Average queueing delay per request -system.physmem.avgBankLat 14006.74 # Average bank access latency per request +system.physmem.totBankLat 6765000 # Total cycles spent in bank access +system.physmem.avgQLat 3642.12 # Average queueing delay per request +system.physmem.avgBankLat 14035.27 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 22670.12 # Average memory access latency -system.physmem.avgRdBW 1168.51 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 22677.39 # Average memory access latency +system.physmem.avgRdBW 1163.00 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 1168.51 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 1163.00 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 9.13 # Data bus utilization in percentage +system.physmem.busUtil 9.09 # Data bus utilization in percentage system.physmem.avgRdQLen 0.41 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time system.physmem.readRowHits 430 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 89.21 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 54438.80 # Average gap between requests -system.membus.throughput 1168506979 # Throughput (bytes/s) +system.physmem.avgGap 54696.06 # Average gap between requests +system.membus.throughput 1163000245 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 399 # Transaction distribution system.membus.trans_dist::ReadResp 399 # Transaction distribution system.membus.trans_dist::ReadExReq 83 # Transaction distribution @@ -200,104 +200,104 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 30848 system.membus.tot_pkt_size 30848 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 30848 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 583000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 2.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 4486500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 608000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 2.3 # Layer utilization (%) +system.membus.respLayer1.occupancy 4504750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 17.0 # Layer utilization (%) -system.cpu.branchPred.lookups 6719 # Number of BP lookups -system.cpu.branchPred.condPredicted 4457 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1075 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 5025 # Number of BTB lookups -system.cpu.branchPred.BTBHits 2433 # Number of BTB hits +system.cpu.branchPred.lookups 6716 # Number of BP lookups +system.cpu.branchPred.condPredicted 4456 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1076 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 5022 # Number of BTB lookups +system.cpu.branchPred.BTBHits 2432 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 48.417910 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 48.426922 # BTB Hit Percentage system.cpu.branchPred.usedRAS 444 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 168 # Number of incorrect RAS predictions. system.cpu.workload.num_syscalls 18 # Number of system calls -system.cpu.numCycles 52800 # number of cpu cycles simulated +system.cpu.numCycles 53050 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 12414 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 31130 # Number of instructions fetch has processed -system.cpu.fetch.Branches 6719 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 2877 # Number of branches that fetch has predicted taken +system.cpu.fetch.icacheStallCycles 12402 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 31129 # Number of instructions fetch has processed +system.cpu.fetch.Branches 6716 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 2876 # Number of branches that fetch has predicted taken system.cpu.fetch.Cycles 9133 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 3041 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 8772 # Number of cycles fetch has spent blocked +system.cpu.fetch.SquashCycles 3044 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 8789 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 994 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 5381 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 470 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 33187 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.938018 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.130523 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.PendingTrapStallCycles 999 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 5380 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 469 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 33199 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.937649 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.130205 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 24054 72.48% 72.48% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 4509 13.59% 86.07% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 475 1.43% 87.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 24066 72.49% 72.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 4510 13.58% 86.07% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 474 1.43% 87.50% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::3 392 1.18% 88.68% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::4 680 2.05% 90.73% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::5 706 2.13% 92.86% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 235 0.71% 93.56% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 235 0.71% 93.57% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::7 253 0.76% 94.33% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::8 1883 5.67% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 33187 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.127254 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.589583 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 13016 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 9761 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 8340 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 200 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1870 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 29004 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 1870 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 13656 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 501 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 8734 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 7953 # Number of cycles rename is running +system.cpu.fetch.rateDist::total 33199 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.126598 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.586786 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 13000 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 9785 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 8344 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 198 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1872 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 29016 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 1872 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 13643 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 503 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 8756 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 7952 # Number of cycles rename is running system.cpu.rename.UnblockCycles 473 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 26651 # Number of instructions processed by rename +system.cpu.rename.RenamedInsts 26657 # Number of instructions processed by rename system.cpu.rename.IQFullEvents 2 # Number of times rename has blocked due to IQ full system.cpu.rename.LSQFullEvents 147 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 23943 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 49443 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 49443 # Number of integer rename lookups +system.cpu.rename.RenamedOperands 23951 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 49456 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 49456 # Number of integer rename lookups system.cpu.rename.CommittedMaps 13819 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 10124 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 10132 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 691 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 694 # count of temporary serializing insts renamed system.cpu.rename.skidInsts 2734 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 3527 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 2284 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.insertedLoads 3529 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 2285 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 4 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 22510 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 22518 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 655 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 21113 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 96 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 7896 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 5507 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 21122 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 97 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 7904 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 5498 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 180 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 33187 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.636183 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.261114 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 33199 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.636224 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.261129 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 23946 72.15% 72.15% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 3557 10.72% 82.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 2326 7.01% 89.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 1693 5.10% 94.98% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 889 2.68% 97.66% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 472 1.42% 99.08% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 239 0.72% 99.80% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 23956 72.16% 72.16% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 3556 10.71% 82.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 2322 6.99% 89.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 1703 5.13% 94.99% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 887 2.67% 97.67% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 470 1.42% 99.08% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 240 0.72% 99.80% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 45 0.14% 99.94% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 20 0.06% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 33187 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 33199 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 46 31.29% 31.29% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 31.29% # attempts to use FU when none available @@ -333,113 +333,113 @@ system.cpu.iq.fu_full::MemWrite 75 51.02% 100.00% # at system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 15643 74.09% 74.09% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 74.09% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 74.09% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 74.09% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 74.09% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 74.09% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 74.09% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 74.09% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 74.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 74.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 74.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 74.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 74.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 74.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 74.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 74.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 74.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 74.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 74.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 74.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 74.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 74.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 74.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 74.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 74.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 74.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 74.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 74.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 74.09% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 15651 74.10% 74.10% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 74.10% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 74.10% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 74.10% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 74.10% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 74.10% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 74.10% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 74.10% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 74.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 74.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 74.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 74.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 74.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 74.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 74.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 74.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 74.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 74.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 74.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 74.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 74.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 74.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 74.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 74.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 74.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 74.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 74.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 74.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 74.10% # Type of FU issued system.cpu.iq.FU_type_0::MemRead 3362 15.92% 90.02% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 2108 9.98% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 2109 9.98% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 21113 # Type of FU issued -system.cpu.iq.rate 0.399867 # Inst issue rate +system.cpu.iq.FU_type_0::total 21122 # Type of FU issued +system.cpu.iq.rate 0.398153 # Inst issue rate system.cpu.iq.fu_busy_cnt 147 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.006963 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 75656 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 31087 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 19513 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fu_busy_rate 0.006960 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 75687 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 31103 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 19522 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 21260 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 21269 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 29 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1302 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1304 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 26 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 836 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 837 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 28 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1870 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 357 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 20 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 24299 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 398 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 3527 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 2284 # Number of dispatched store instructions +system.cpu.iew.iewSquashCycles 1872 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 359 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 19 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 24307 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 399 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 3529 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 2285 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 655 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 4 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewIQFullEvents 3 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 26 # Number of memory order violations system.cpu.iew.predictedTakenIncorrect 264 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 945 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1209 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 20068 # Number of executed instructions +system.cpu.iew.predictedNotTakenIncorrect 946 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1210 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 20074 # Number of executed instructions system.cpu.iew.iewExecLoadInsts 3202 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1045 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecSquashedInsts 1048 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 1134 # number of nop insts executed system.cpu.iew.exec_refs 5224 # number of memory reference insts executed -system.cpu.iew.exec_branches 4238 # Number of branches executed +system.cpu.iew.exec_branches 4239 # Number of branches executed system.cpu.iew.exec_stores 2022 # Number of stores executed -system.cpu.iew.exec_rate 0.380076 # Inst execution rate -system.cpu.iew.wb_sent 19741 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 19513 # cumulative count of insts written-back -system.cpu.iew.wb_producers 9111 # num instructions producing a value -system.cpu.iew.wb_consumers 11226 # num instructions consuming a value +system.cpu.iew.exec_rate 0.378398 # Inst execution rate +system.cpu.iew.wb_sent 19749 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 19522 # cumulative count of insts written-back +system.cpu.iew.wb_producers 9120 # num instructions producing a value +system.cpu.iew.wb_consumers 11235 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.369564 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.811598 # average fanout of values written-back +system.cpu.iew.wb_rate 0.367992 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.811749 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 9039 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 9047 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 475 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1075 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 31317 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.484146 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.180879 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 1076 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 31327 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.483991 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.181452 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 23994 76.62% 76.62% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 4076 13.02% 89.63% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 1358 4.34% 93.97% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 763 2.44% 96.40% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 350 1.12% 97.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 272 0.87% 98.39% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 322 1.03% 99.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 24007 76.63% 76.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 4072 13.00% 89.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 1361 4.34% 93.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 763 2.44% 96.41% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 348 1.11% 97.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 270 0.86% 98.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 322 1.03% 99.41% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::7 67 0.21% 99.63% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 115 0.37% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 117 0.37% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 31317 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 31327 # Number of insts commited each cycle system.cpu.commit.committedInsts 15162 # Number of instructions committed system.cpu.commit.committedOps 15162 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -450,24 +450,24 @@ system.cpu.commit.branches 3358 # Nu system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. system.cpu.commit.int_insts 12174 # Number of committed integer instructions. system.cpu.commit.function_calls 187 # Number of function calls committed. -system.cpu.commit.bw_lim_events 115 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 117 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 54580 # The number of ROB reads -system.cpu.rob.rob_writes 50280 # The number of ROB writes -system.cpu.timesIdled 215 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 19613 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 54596 # The number of ROB reads +system.cpu.rob.rob_writes 50298 # The number of ROB writes +system.cpu.timesIdled 214 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 19851 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 14436 # Number of Instructions Simulated system.cpu.committedOps 14436 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 14436 # Number of Instructions Simulated -system.cpu.cpi 3.657523 # CPI: Cycles Per Instruction -system.cpu.cpi_total 3.657523 # CPI: Total CPI of All Threads -system.cpu.ipc 0.273409 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.273409 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 32029 # number of integer regfile reads -system.cpu.int_regfile_writes 17831 # number of integer regfile writes +system.cpu.cpi 3.674841 # CPI: Cycles Per Instruction +system.cpu.cpi_total 3.674841 # CPI: Total CPI of All Threads +system.cpu.ipc 0.272121 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.272121 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 32043 # number of integer regfile reads +system.cpu.int_regfile_writes 17841 # number of integer regfile writes system.cpu.misc_regfile_reads 6919 # number of misc regfile reads system.cpu.misc_regfile_writes 569 # number of misc regfile writes -system.cpu.toL2Bus.throughput 1173355556 # Throughput (bytes/s) +system.cpu.toL2Bus.throughput 1167825972 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 401 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 401 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 83 # Transaction distribution @@ -482,55 +482,55 @@ system.cpu.toL2Bus.data_through_bus 30976 # To system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 242000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.9 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 505500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 1.9 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 220500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) -system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 187.819339 # Cycle average of tags in use -system.cpu.icache.total_refs 4874 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 337 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 14.462908 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 187.819339 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.091709 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.091709 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 4874 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 4874 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 4874 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 4874 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 4874 # number of overall hits -system.cpu.icache.overall_hits::total 4874 # number of overall hits +system.cpu.toL2Bus.respLayer0.occupancy 570000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 2.1 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 235750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) +system.cpu.icache.tags.replacements 0 # number of replacements +system.cpu.icache.tags.tagsinuse 187.665560 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 4873 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 337 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 14.459941 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 187.665560 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.091634 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.091634 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 4873 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 4873 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 4873 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 4873 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 4873 # number of overall hits +system.cpu.icache.overall_hits::total 4873 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 507 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 507 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 507 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 507 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 507 # number of overall misses system.cpu.icache.overall_misses::total 507 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 30807500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 30807500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 30807500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 30807500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 30807500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 30807500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 5381 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 5381 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 5381 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 5381 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 5381 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 5381 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.094220 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.094220 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.094220 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.094220 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.094220 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.094220 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 60764.299803 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 60764.299803 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 60764.299803 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 60764.299803 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 60764.299803 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 60764.299803 # average overall miss latency +system.cpu.icache.ReadReq_miss_latency::cpu.inst 31160500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 31160500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 31160500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 31160500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 31160500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 31160500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 5380 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 5380 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 5380 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 5380 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 5380 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 5380 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.094238 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.094238 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.094238 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.094238 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.094238 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.094238 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61460.552268 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 61460.552268 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 61460.552268 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 61460.552268 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 61460.552268 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 61460.552268 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -551,36 +551,36 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 337 system.cpu.icache.demand_mshr_misses::total 337 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 337 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 337 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22247500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 22247500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22247500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 22247500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22247500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 22247500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.062628 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.062628 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.062628 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.062628 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.062628 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.062628 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66016.320475 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66016.320475 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66016.320475 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 66016.320475 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66016.320475 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 66016.320475 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22334500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 22334500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22334500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 22334500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22334500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 22334500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.062639 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.062639 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.062639 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.062639 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.062639 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.062639 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66274.480712 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66274.480712 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66274.480712 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 66274.480712 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66274.480712 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 66274.480712 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 221.715806 # Cycle average of tags in use -system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 399 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.005013 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 187.205303 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 34.510503 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.005713 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.001053 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.006766 # Average percentage of cache occupancy +system.cpu.l2cache.tags.replacements 0 # number of replacements +system.cpu.l2cache.tags.tagsinuse 221.542392 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 399 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.005013 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::cpu.inst 187.054257 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 34.488135 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005708 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.001052 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.006761 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits @@ -598,17 +598,17 @@ system.cpu.l2cache.demand_misses::total 482 # nu system.cpu.l2cache.overall_misses::cpu.inst 335 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 147 # number of overall misses system.cpu.l2cache.overall_misses::total 482 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 21890500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4591500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 26482000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5706000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 5706000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 21890500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 10297500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 32188000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 21890500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 10297500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 32188000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 21977500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4600000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 26577500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5717750 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 5717750 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 21977500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 10317750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 32295250 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 21977500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 10317750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 32295250 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 337 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 64 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 401 # number of ReadReq accesses(hits+misses) @@ -631,17 +631,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.995868 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.994065 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.995868 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 65344.776119 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 71742.187500 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 66370.927318 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 68746.987952 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68746.987952 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 65344.776119 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70051.020408 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 66780.082988 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 65344.776119 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70051.020408 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 66780.082988 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 65604.477612 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 71875 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 66610.275689 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 68888.554217 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68888.554217 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 65604.477612 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70188.775510 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 67002.593361 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 65604.477612 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70188.775510 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 67002.593361 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -661,17 +661,17 @@ system.cpu.l2cache.demand_mshr_misses::total 482 system.cpu.l2cache.overall_mshr_misses::cpu.inst 335 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 482 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 17748750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3809500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 21558250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4697250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4697250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 17748750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8506750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 26255500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 17748750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8506750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 26255500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 17752000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3813000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 21565000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4699750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4699750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 17752000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8512750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 26264750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 17752000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8512750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 26264750 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.994065 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.995012 # mshr miss rate for ReadReq accesses @@ -683,27 +683,27 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.995868 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.994065 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.995868 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 52981.343284 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 59523.437500 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 54030.701754 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56593.373494 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56593.373494 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 52981.343284 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57869.047619 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54471.991701 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 52981.343284 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57869.047619 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54471.991701 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 52991.044776 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 59578.125000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 54047.619048 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56623.493976 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56623.493976 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 52991.044776 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57909.863946 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54491.182573 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 52991.044776 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57909.863946 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54491.182573 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 98.861742 # Cycle average of tags in use -system.cpu.dcache.total_refs 4001 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 147 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 27.217687 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 98.861742 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.024136 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.024136 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 0 # number of replacements +system.cpu.dcache.tags.tagsinuse 98.809715 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 4001 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 147 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 27.217687 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 98.809715 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.024123 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.024123 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 2962 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 2962 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 1033 # number of WriteReq hits @@ -722,14 +722,14 @@ system.cpu.dcache.demand_misses::cpu.data 535 # n system.cpu.dcache.demand_misses::total 535 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 535 # number of overall misses system.cpu.dcache.overall_misses::total 535 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 7949500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 7949500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 24575974 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 24575974 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 32525474 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 32525474 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 32525474 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 32525474 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 7983250 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 7983250 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 24700974 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 24700974 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 32684224 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 32684224 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 32684224 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 32684224 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 3088 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 3088 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 1442 # number of WriteReq accesses(hits+misses) @@ -748,19 +748,19 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.118102 system.cpu.dcache.demand_miss_rate::total 0.118102 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.118102 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.118102 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63091.269841 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 63091.269841 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60087.955990 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 60087.955990 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 60795.278505 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 60795.278505 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 60795.278505 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 60795.278505 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 749 # number of cycles access was blocked +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63359.126984 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 63359.126984 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60393.579462 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 60393.579462 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 61092.007477 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 61092.007477 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 61092.007477 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 61092.007477 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 729 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 28 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 26.750000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 26.035714 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed @@ -780,14 +780,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 147 system.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4656000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4656000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5790000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5790000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10446000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 10446000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10446000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 10446000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4664500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4664500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5801750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5801750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10466250 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 10466250 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10466250 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 10466250 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.020725 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.020725 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.057559 # mshr miss rate for WriteReq accesses @@ -796,14 +796,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.032450 system.cpu.dcache.demand_mshr_miss_rate::total 0.032450 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.032450 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.032450 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 72750 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 72750 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 69759.036145 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 69759.036145 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 71061.224490 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 71061.224490 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 71061.224490 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 71061.224490 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 72882.812500 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 72882.812500 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 69900.602410 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 69900.602410 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 71198.979592 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 71198.979592 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 71198.979592 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 71198.979592 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt index b595d4238..ac8c29d55 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt @@ -65,15 +65,15 @@ system.cpu.num_idle_cycles 0 # Nu system.cpu.num_busy_cycles 82736 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 153.782734 # Cycle average of tags in use -system.cpu.icache.total_refs 14928 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 280 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 53.314286 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 153.782734 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.075089 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.075089 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 0 # number of replacements +system.cpu.icache.tags.tagsinuse 153.782734 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 14928 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 280 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 53.314286 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 153.782734 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.075089 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.075089 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 14928 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 14928 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 14928 # number of demand (read+write) hits @@ -143,17 +143,17 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 52700 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52700 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 52700 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 184.632038 # Cycle average of tags in use -system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 331 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.006042 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 153.110886 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 31.521152 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.004673 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.000962 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.005635 # Average percentage of cache occupancy +system.cpu.l2cache.tags.replacements 0 # number of replacements +system.cpu.l2cache.tags.tagsinuse 184.632038 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 331 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.006042 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::cpu.inst 153.110886 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 31.521152 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004673 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.000962 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.005635 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits @@ -268,15 +268,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 97.994344 # Cycle average of tags in use -system.cpu.dcache.total_refs 3535 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 138 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 25.615942 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 97.994344 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.023924 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.023924 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 0 # number of replacements +system.cpu.dcache.tags.tagsinuse 97.994344 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 3535 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 138 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 25.615942 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 97.994344 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.023924 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.023924 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 2172 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 2172 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 1357 # number of WriteReq hits diff --git a/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/stats.txt b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/stats.txt index 21486e70f..a1275a141 100644 --- a/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/stats.txt +++ b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/stats.txt @@ -97,15 +97,15 @@ system.cpu.num_idle_cycles 0 # Nu system.cpu.num_busy_cycles 1454144 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 265.013024 # Cycle average of tags in use -system.cpu.icache.total_refs 499617 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 403 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 1239.744417 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 265.013024 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.129401 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.129401 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 0 # number of replacements +system.cpu.icache.tags.tagsinuse 265.013024 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 499617 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 403 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 1239.744417 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 265.013024 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.129401 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.129401 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 499617 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 499617 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 499617 # number of demand (read+write) hits @@ -175,17 +175,17 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 53000 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 481.542013 # Cycle average of tags in use -system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 718 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 265.019675 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 216.522338 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.008088 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.006608 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.014695 # Average percentage of cache occupancy +system.cpu.l2cache.tags.replacements 0 # number of replacements +system.cpu.l2cache.tags.tagsinuse 481.542013 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 0 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 718 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::cpu.inst 265.019675 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 216.522338 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.008088 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.006608 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.014695 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_misses::cpu.inst 403 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.data 315 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::total 718 # number of ReadReq misses @@ -294,15 +294,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 287.259400 # Cycle average of tags in use -system.cpu.dcache.total_refs 180321 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 454 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 397.182819 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 287.259400 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.070132 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.070132 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 0 # number of replacements +system.cpu.dcache.tags.tagsinuse 287.259400 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 180321 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 454 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 397.182819 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 287.259400 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.070132 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.070132 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 124120 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 124120 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 56201 # number of WriteReq hits diff --git a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt index 8803a901a..2e9aa5100 100644 --- a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt +++ b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt @@ -118,15 +118,15 @@ system.cpu0.num_idle_cycles 0 # Nu system.cpu0.num_busy_cycles 500032 # Number of busy cycles system.cpu0.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu0.idle_fraction 0 # Percentage of idle cycles -system.cpu0.icache.replacements 152 # number of replacements -system.cpu0.icache.tagsinuse 218.086151 # Cycle average of tags in use -system.cpu0.icache.total_refs 499556 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 463 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 1078.954644 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 218.086151 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.425950 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.425950 # Average percentage of cache occupancy +system.cpu0.icache.tags.replacements 152 # number of replacements +system.cpu0.icache.tags.tagsinuse 218.086151 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 499556 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 463 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 1078.954644 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 218.086151 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.425950 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.425950 # Average percentage of cache occupancy system.cpu0.icache.ReadReq_hits::cpu0.inst 499556 # number of ReadReq hits system.cpu0.icache.ReadReq_hits::total 499556 # number of ReadReq hits system.cpu0.icache.demand_hits::cpu0.inst 499556 # number of demand (read+write) hits @@ -160,15 +160,15 @@ system.cpu0.icache.avg_blocked_cycles::no_targets nan system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 61 # number of replacements -system.cpu0.dcache.tagsinuse 276.872320 # Cycle average of tags in use -system.cpu0.dcache.total_refs 180312 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 463 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 389.442765 # Average number of references to valid blocks. -system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 276.872320 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.540766 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.540766 # Average percentage of cache occupancy +system.cpu0.dcache.tags.replacements 61 # number of replacements +system.cpu0.dcache.tags.tagsinuse 276.872320 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 180312 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 463 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 389.442765 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 276.872320 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.540766 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.540766 # Average percentage of cache occupancy system.cpu0.dcache.ReadReq_hits::cpu0.data 124111 # number of ReadReq hits system.cpu0.dcache.ReadReq_hits::total 124111 # number of ReadReq hits system.cpu0.dcache.WriteReq_hits::cpu0.data 56201 # number of WriteReq hits @@ -267,15 +267,15 @@ system.cpu1.num_idle_cycles 0 # Nu system.cpu1.num_busy_cycles 500032 # Number of busy cycles system.cpu1.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu1.idle_fraction 0 # Percentage of idle cycles -system.cpu1.icache.replacements 152 # number of replacements -system.cpu1.icache.tagsinuse 218.086151 # Cycle average of tags in use -system.cpu1.icache.total_refs 499556 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 463 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 1078.954644 # Average number of references to valid blocks. -system.cpu1.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 218.086151 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.425950 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.425950 # Average percentage of cache occupancy +system.cpu1.icache.tags.replacements 152 # number of replacements +system.cpu1.icache.tags.tagsinuse 218.086151 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 499556 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 463 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 1078.954644 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 218.086151 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.425950 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.425950 # Average percentage of cache occupancy system.cpu1.icache.ReadReq_hits::cpu1.inst 499556 # number of ReadReq hits system.cpu1.icache.ReadReq_hits::total 499556 # number of ReadReq hits system.cpu1.icache.demand_hits::cpu1.inst 499556 # number of demand (read+write) hits @@ -309,15 +309,15 @@ system.cpu1.icache.avg_blocked_cycles::no_targets nan system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.replacements 61 # number of replacements -system.cpu1.dcache.tagsinuse 276.872320 # Cycle average of tags in use -system.cpu1.dcache.total_refs 180312 # Total number of references to valid blocks. -system.cpu1.dcache.sampled_refs 463 # Sample count of references to valid blocks. -system.cpu1.dcache.avg_refs 389.442765 # Average number of references to valid blocks. -system.cpu1.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::cpu1.data 276.872320 # Average occupied blocks per requestor -system.cpu1.dcache.occ_percent::cpu1.data 0.540766 # Average percentage of cache occupancy -system.cpu1.dcache.occ_percent::total 0.540766 # Average percentage of cache occupancy +system.cpu1.dcache.tags.replacements 61 # number of replacements +system.cpu1.dcache.tags.tagsinuse 276.872320 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 180312 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 463 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 389.442765 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 276.872320 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.540766 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.540766 # Average percentage of cache occupancy system.cpu1.dcache.ReadReq_hits::cpu1.data 124111 # number of ReadReq hits system.cpu1.dcache.ReadReq_hits::total 124111 # number of ReadReq hits system.cpu1.dcache.WriteReq_hits::cpu1.data 56201 # number of WriteReq hits @@ -416,15 +416,15 @@ system.cpu2.num_idle_cycles 0 # Nu system.cpu2.num_busy_cycles 500032 # Number of busy cycles system.cpu2.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu2.idle_fraction 0 # Percentage of idle cycles -system.cpu2.icache.replacements 152 # number of replacements -system.cpu2.icache.tagsinuse 218.086151 # Cycle average of tags in use -system.cpu2.icache.total_refs 499556 # Total number of references to valid blocks. -system.cpu2.icache.sampled_refs 463 # Sample count of references to valid blocks. -system.cpu2.icache.avg_refs 1078.954644 # Average number of references to valid blocks. -system.cpu2.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.icache.occ_blocks::cpu2.inst 218.086151 # Average occupied blocks per requestor -system.cpu2.icache.occ_percent::cpu2.inst 0.425950 # Average percentage of cache occupancy -system.cpu2.icache.occ_percent::total 0.425950 # Average percentage of cache occupancy +system.cpu2.icache.tags.replacements 152 # number of replacements +system.cpu2.icache.tags.tagsinuse 218.086151 # Cycle average of tags in use +system.cpu2.icache.tags.total_refs 499556 # Total number of references to valid blocks. +system.cpu2.icache.tags.sampled_refs 463 # Sample count of references to valid blocks. +system.cpu2.icache.tags.avg_refs 1078.954644 # Average number of references to valid blocks. +system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu2.icache.tags.occ_blocks::cpu2.inst 218.086151 # Average occupied blocks per requestor +system.cpu2.icache.tags.occ_percent::cpu2.inst 0.425950 # Average percentage of cache occupancy +system.cpu2.icache.tags.occ_percent::total 0.425950 # Average percentage of cache occupancy system.cpu2.icache.ReadReq_hits::cpu2.inst 499556 # number of ReadReq hits system.cpu2.icache.ReadReq_hits::total 499556 # number of ReadReq hits system.cpu2.icache.demand_hits::cpu2.inst 499556 # number of demand (read+write) hits @@ -458,15 +458,15 @@ system.cpu2.icache.avg_blocked_cycles::no_targets nan system.cpu2.icache.fast_writes 0 # number of fast writes performed system.cpu2.icache.cache_copies 0 # number of cache copies performed system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.dcache.replacements 61 # number of replacements -system.cpu2.dcache.tagsinuse 276.872320 # Cycle average of tags in use -system.cpu2.dcache.total_refs 180312 # Total number of references to valid blocks. -system.cpu2.dcache.sampled_refs 463 # Sample count of references to valid blocks. -system.cpu2.dcache.avg_refs 389.442765 # Average number of references to valid blocks. -system.cpu2.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.dcache.occ_blocks::cpu2.data 276.872320 # Average occupied blocks per requestor -system.cpu2.dcache.occ_percent::cpu2.data 0.540766 # Average percentage of cache occupancy -system.cpu2.dcache.occ_percent::total 0.540766 # Average percentage of cache occupancy +system.cpu2.dcache.tags.replacements 61 # number of replacements +system.cpu2.dcache.tags.tagsinuse 276.872320 # Cycle average of tags in use +system.cpu2.dcache.tags.total_refs 180312 # Total number of references to valid blocks. +system.cpu2.dcache.tags.sampled_refs 463 # Sample count of references to valid blocks. +system.cpu2.dcache.tags.avg_refs 389.442765 # Average number of references to valid blocks. +system.cpu2.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu2.dcache.tags.occ_blocks::cpu2.data 276.872320 # Average occupied blocks per requestor +system.cpu2.dcache.tags.occ_percent::cpu2.data 0.540766 # Average percentage of cache occupancy +system.cpu2.dcache.tags.occ_percent::total 0.540766 # Average percentage of cache occupancy system.cpu2.dcache.ReadReq_hits::cpu2.data 124111 # number of ReadReq hits system.cpu2.dcache.ReadReq_hits::total 124111 # number of ReadReq hits system.cpu2.dcache.WriteReq_hits::cpu2.data 56201 # number of WriteReq hits @@ -565,15 +565,15 @@ system.cpu3.num_idle_cycles 0 # Nu system.cpu3.num_busy_cycles 500032 # Number of busy cycles system.cpu3.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu3.idle_fraction 0 # Percentage of idle cycles -system.cpu3.icache.replacements 152 # number of replacements -system.cpu3.icache.tagsinuse 218.086151 # Cycle average of tags in use -system.cpu3.icache.total_refs 499556 # Total number of references to valid blocks. -system.cpu3.icache.sampled_refs 463 # Sample count of references to valid blocks. -system.cpu3.icache.avg_refs 1078.954644 # Average number of references to valid blocks. -system.cpu3.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.icache.occ_blocks::cpu3.inst 218.086151 # Average occupied blocks per requestor -system.cpu3.icache.occ_percent::cpu3.inst 0.425950 # Average percentage of cache occupancy -system.cpu3.icache.occ_percent::total 0.425950 # Average percentage of cache occupancy +system.cpu3.icache.tags.replacements 152 # number of replacements +system.cpu3.icache.tags.tagsinuse 218.086151 # Cycle average of tags in use +system.cpu3.icache.tags.total_refs 499556 # Total number of references to valid blocks. +system.cpu3.icache.tags.sampled_refs 463 # Sample count of references to valid blocks. +system.cpu3.icache.tags.avg_refs 1078.954644 # Average number of references to valid blocks. +system.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu3.icache.tags.occ_blocks::cpu3.inst 218.086151 # Average occupied blocks per requestor +system.cpu3.icache.tags.occ_percent::cpu3.inst 0.425950 # Average percentage of cache occupancy +system.cpu3.icache.tags.occ_percent::total 0.425950 # Average percentage of cache occupancy system.cpu3.icache.ReadReq_hits::cpu3.inst 499556 # number of ReadReq hits system.cpu3.icache.ReadReq_hits::total 499556 # number of ReadReq hits system.cpu3.icache.demand_hits::cpu3.inst 499556 # number of demand (read+write) hits @@ -607,15 +607,15 @@ system.cpu3.icache.avg_blocked_cycles::no_targets nan system.cpu3.icache.fast_writes 0 # number of fast writes performed system.cpu3.icache.cache_copies 0 # number of cache copies performed system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.dcache.replacements 61 # number of replacements -system.cpu3.dcache.tagsinuse 276.872320 # Cycle average of tags in use -system.cpu3.dcache.total_refs 180312 # Total number of references to valid blocks. -system.cpu3.dcache.sampled_refs 463 # Sample count of references to valid blocks. -system.cpu3.dcache.avg_refs 389.442765 # Average number of references to valid blocks. -system.cpu3.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.dcache.occ_blocks::cpu3.data 276.872320 # Average occupied blocks per requestor -system.cpu3.dcache.occ_percent::cpu3.data 0.540766 # Average percentage of cache occupancy -system.cpu3.dcache.occ_percent::total 0.540766 # Average percentage of cache occupancy +system.cpu3.dcache.tags.replacements 61 # number of replacements +system.cpu3.dcache.tags.tagsinuse 276.872320 # Cycle average of tags in use +system.cpu3.dcache.tags.total_refs 180312 # Total number of references to valid blocks. +system.cpu3.dcache.tags.sampled_refs 463 # Sample count of references to valid blocks. +system.cpu3.dcache.tags.avg_refs 389.442765 # Average number of references to valid blocks. +system.cpu3.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu3.dcache.tags.occ_blocks::cpu3.data 276.872320 # Average occupied blocks per requestor +system.cpu3.dcache.tags.occ_percent::cpu3.data 0.540766 # Average percentage of cache occupancy +system.cpu3.dcache.tags.occ_percent::total 0.540766 # Average percentage of cache occupancy system.cpu3.dcache.ReadReq_hits::cpu3.data 124111 # number of ReadReq hits system.cpu3.dcache.ReadReq_hits::total 124111 # number of ReadReq hits system.cpu3.dcache.WriteReq_hits::cpu3.data 56201 # number of WriteReq hits @@ -659,31 +659,31 @@ system.cpu3.dcache.cache_copies 0 # nu system.cpu3.dcache.writebacks::writebacks 29 # number of writebacks system.cpu3.dcache.writebacks::total 29 # number of writebacks system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.replacements 0 # number of replacements -system.l2c.tagsinuse 1962.780232 # Cycle average of tags in use -system.l2c.total_refs 332 # Total number of references to valid blocks. -system.l2c.sampled_refs 2932 # Sample count of references to valid blocks. -system.l2c.avg_refs 0.113233 # Average number of references to valid blocks. -system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 17.466765 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 267.152061 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 219.176305 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 267.152061 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 219.176305 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu2.inst 267.152061 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu2.data 219.176305 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu3.inst 267.152061 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu3.data 219.176305 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.000267 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.004076 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.003344 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.004076 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.data 0.003344 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu2.inst 0.004076 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu2.data 0.003344 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu3.inst 0.004076 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu3.data 0.003344 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.029950 # Average percentage of cache occupancy +system.l2c.tags.replacements 0 # number of replacements +system.l2c.tags.tagsinuse 1962.780232 # Cycle average of tags in use +system.l2c.tags.total_refs 332 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 2932 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 0.113233 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 17.466765 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 267.152061 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 219.176305 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 267.152061 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 219.176305 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.inst 267.152061 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.data 219.176305 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3.inst 267.152061 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3.data 219.176305 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.000267 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.004076 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.003344 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.004076 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.003344 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.inst 0.004076 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.data 0.003344 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu3.inst 0.004076 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu3.data 0.003344 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.029950 # Average percentage of cache occupancy system.l2c.ReadReq_hits::cpu0.inst 60 # number of ReadReq hits system.l2c.ReadReq_hits::cpu0.data 9 # number of ReadReq hits system.l2c.ReadReq_hits::cpu1.inst 60 # number of ReadReq hits diff --git a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt index e6052b6f1..d89f8b6a1 100644 --- a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt +++ b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt @@ -171,15 +171,15 @@ system.cpu0.num_idle_cycles 0 # Nu system.cpu0.num_busy_cycles 1458048 # Number of busy cycles system.cpu0.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu0.idle_fraction 0 # Percentage of idle cycles -system.cpu0.icache.replacements 152 # number of replacements -system.cpu0.icache.tagsinuse 216.376897 # Cycle average of tags in use -system.cpu0.icache.total_refs 499557 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 463 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 1078.956803 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 216.376897 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.422611 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.422611 # Average percentage of cache occupancy +system.cpu0.icache.tags.replacements 152 # number of replacements +system.cpu0.icache.tags.tagsinuse 216.376897 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 499557 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 463 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 1078.956803 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 216.376897 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.422611 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.422611 # Average percentage of cache occupancy system.cpu0.icache.ReadReq_hits::cpu0.inst 499557 # number of ReadReq hits system.cpu0.icache.ReadReq_hits::total 499557 # number of ReadReq hits system.cpu0.icache.demand_hits::cpu0.inst 499557 # number of demand (read+write) hits @@ -249,15 +249,15 @@ system.cpu0.icache.demand_avg_mshr_miss_latency::total 47883.369330 system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 47883.369330 # average overall mshr miss latency system.cpu0.icache.overall_avg_mshr_miss_latency::total 47883.369330 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 61 # number of replacements -system.cpu0.dcache.tagsinuse 273.500146 # Cycle average of tags in use -system.cpu0.dcache.total_refs 180312 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 463 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 389.442765 # Average number of references to valid blocks. -system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 273.500146 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.534180 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.534180 # Average percentage of cache occupancy +system.cpu0.dcache.tags.replacements 61 # number of replacements +system.cpu0.dcache.tags.tagsinuse 273.500146 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 180312 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 463 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 389.442765 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 273.500146 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.534180 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.534180 # Average percentage of cache occupancy system.cpu0.dcache.ReadReq_hits::cpu0.data 124111 # number of ReadReq hits system.cpu0.dcache.ReadReq_hits::total 124111 # number of ReadReq hits system.cpu0.dcache.WriteReq_hits::cpu0.data 56201 # number of WriteReq hits @@ -404,15 +404,15 @@ system.cpu1.num_idle_cycles 0 # Nu system.cpu1.num_busy_cycles 1458048 # Number of busy cycles system.cpu1.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu1.idle_fraction 0 # Percentage of idle cycles -system.cpu1.icache.replacements 152 # number of replacements -system.cpu1.icache.tagsinuse 216.373058 # Cycle average of tags in use -system.cpu1.icache.total_refs 499549 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 463 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 1078.939525 # Average number of references to valid blocks. -system.cpu1.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 216.373058 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.422604 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.422604 # Average percentage of cache occupancy +system.cpu1.icache.tags.replacements 152 # number of replacements +system.cpu1.icache.tags.tagsinuse 216.373058 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 499549 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 463 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 1078.939525 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 216.373058 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.422604 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.422604 # Average percentage of cache occupancy system.cpu1.icache.ReadReq_hits::cpu1.inst 499549 # number of ReadReq hits system.cpu1.icache.ReadReq_hits::total 499549 # number of ReadReq hits system.cpu1.icache.demand_hits::cpu1.inst 499549 # number of demand (read+write) hits @@ -482,15 +482,15 @@ system.cpu1.icache.demand_avg_mshr_miss_latency::total 47902.807775 system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 47902.807775 # average overall mshr miss latency system.cpu1.icache.overall_avg_mshr_miss_latency::total 47902.807775 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.replacements 61 # number of replacements -system.cpu1.dcache.tagsinuse 273.495183 # Cycle average of tags in use -system.cpu1.dcache.total_refs 180311 # Total number of references to valid blocks. -system.cpu1.dcache.sampled_refs 463 # Sample count of references to valid blocks. -system.cpu1.dcache.avg_refs 389.440605 # Average number of references to valid blocks. -system.cpu1.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::cpu1.data 273.495183 # Average occupied blocks per requestor -system.cpu1.dcache.occ_percent::cpu1.data 0.534170 # Average percentage of cache occupancy -system.cpu1.dcache.occ_percent::total 0.534170 # Average percentage of cache occupancy +system.cpu1.dcache.tags.replacements 61 # number of replacements +system.cpu1.dcache.tags.tagsinuse 273.495183 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 180311 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 463 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 389.440605 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 273.495183 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.534170 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.534170 # Average percentage of cache occupancy system.cpu1.dcache.ReadReq_hits::cpu1.data 124111 # number of ReadReq hits system.cpu1.dcache.ReadReq_hits::total 124111 # number of ReadReq hits system.cpu1.dcache.WriteReq_hits::cpu1.data 56200 # number of WriteReq hits @@ -637,15 +637,15 @@ system.cpu2.num_idle_cycles 0 # Nu system.cpu2.num_busy_cycles 1458048 # Number of busy cycles system.cpu2.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu2.idle_fraction 0 # Percentage of idle cycles -system.cpu2.icache.replacements 152 # number of replacements -system.cpu2.icache.tagsinuse 216.369218 # Cycle average of tags in use -system.cpu2.icache.total_refs 499542 # Total number of references to valid blocks. -system.cpu2.icache.sampled_refs 463 # Sample count of references to valid blocks. -system.cpu2.icache.avg_refs 1078.924406 # Average number of references to valid blocks. -system.cpu2.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.icache.occ_blocks::cpu2.inst 216.369218 # Average occupied blocks per requestor -system.cpu2.icache.occ_percent::cpu2.inst 0.422596 # Average percentage of cache occupancy -system.cpu2.icache.occ_percent::total 0.422596 # Average percentage of cache occupancy +system.cpu2.icache.tags.replacements 152 # number of replacements +system.cpu2.icache.tags.tagsinuse 216.369218 # Cycle average of tags in use +system.cpu2.icache.tags.total_refs 499542 # Total number of references to valid blocks. +system.cpu2.icache.tags.sampled_refs 463 # Sample count of references to valid blocks. +system.cpu2.icache.tags.avg_refs 1078.924406 # Average number of references to valid blocks. +system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu2.icache.tags.occ_blocks::cpu2.inst 216.369218 # Average occupied blocks per requestor +system.cpu2.icache.tags.occ_percent::cpu2.inst 0.422596 # Average percentage of cache occupancy +system.cpu2.icache.tags.occ_percent::total 0.422596 # Average percentage of cache occupancy system.cpu2.icache.ReadReq_hits::cpu2.inst 499542 # number of ReadReq hits system.cpu2.icache.ReadReq_hits::total 499542 # number of ReadReq hits system.cpu2.icache.demand_hits::cpu2.inst 499542 # number of demand (read+write) hits @@ -715,15 +715,15 @@ system.cpu2.icache.demand_avg_mshr_miss_latency::total 47922.246220 system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 47922.246220 # average overall mshr miss latency system.cpu2.icache.overall_avg_mshr_miss_latency::total 47922.246220 # average overall mshr miss latency system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.dcache.replacements 61 # number of replacements -system.cpu2.dcache.tagsinuse 273.490220 # Cycle average of tags in use -system.cpu2.dcache.total_refs 180309 # Total number of references to valid blocks. -system.cpu2.dcache.sampled_refs 463 # Sample count of references to valid blocks. -system.cpu2.dcache.avg_refs 389.436285 # Average number of references to valid blocks. -system.cpu2.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.dcache.occ_blocks::cpu2.data 273.490220 # Average occupied blocks per requestor -system.cpu2.dcache.occ_percent::cpu2.data 0.534161 # Average percentage of cache occupancy -system.cpu2.dcache.occ_percent::total 0.534161 # Average percentage of cache occupancy +system.cpu2.dcache.tags.replacements 61 # number of replacements +system.cpu2.dcache.tags.tagsinuse 273.490220 # Cycle average of tags in use +system.cpu2.dcache.tags.total_refs 180309 # Total number of references to valid blocks. +system.cpu2.dcache.tags.sampled_refs 463 # Sample count of references to valid blocks. +system.cpu2.dcache.tags.avg_refs 389.436285 # Average number of references to valid blocks. +system.cpu2.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu2.dcache.tags.occ_blocks::cpu2.data 273.490220 # Average occupied blocks per requestor +system.cpu2.dcache.tags.occ_percent::cpu2.data 0.534161 # Average percentage of cache occupancy +system.cpu2.dcache.tags.occ_percent::total 0.534161 # Average percentage of cache occupancy system.cpu2.dcache.ReadReq_hits::cpu2.data 124109 # number of ReadReq hits system.cpu2.dcache.ReadReq_hits::total 124109 # number of ReadReq hits system.cpu2.dcache.WriteReq_hits::cpu2.data 56200 # number of WriteReq hits @@ -870,15 +870,15 @@ system.cpu3.num_idle_cycles 0 # Nu system.cpu3.num_busy_cycles 1458048 # Number of busy cycles system.cpu3.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu3.idle_fraction 0 # Percentage of idle cycles -system.cpu3.icache.replacements 152 # number of replacements -system.cpu3.icache.tagsinuse 216.365379 # Cycle average of tags in use -system.cpu3.icache.total_refs 499535 # Total number of references to valid blocks. -system.cpu3.icache.sampled_refs 463 # Sample count of references to valid blocks. -system.cpu3.icache.avg_refs 1078.909287 # Average number of references to valid blocks. -system.cpu3.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.icache.occ_blocks::cpu3.inst 216.365379 # Average occupied blocks per requestor -system.cpu3.icache.occ_percent::cpu3.inst 0.422589 # Average percentage of cache occupancy -system.cpu3.icache.occ_percent::total 0.422589 # Average percentage of cache occupancy +system.cpu3.icache.tags.replacements 152 # number of replacements +system.cpu3.icache.tags.tagsinuse 216.365379 # Cycle average of tags in use +system.cpu3.icache.tags.total_refs 499535 # Total number of references to valid blocks. +system.cpu3.icache.tags.sampled_refs 463 # Sample count of references to valid blocks. +system.cpu3.icache.tags.avg_refs 1078.909287 # Average number of references to valid blocks. +system.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu3.icache.tags.occ_blocks::cpu3.inst 216.365379 # Average occupied blocks per requestor +system.cpu3.icache.tags.occ_percent::cpu3.inst 0.422589 # Average percentage of cache occupancy +system.cpu3.icache.tags.occ_percent::total 0.422589 # Average percentage of cache occupancy system.cpu3.icache.ReadReq_hits::cpu3.inst 499535 # number of ReadReq hits system.cpu3.icache.ReadReq_hits::total 499535 # number of ReadReq hits system.cpu3.icache.demand_hits::cpu3.inst 499535 # number of demand (read+write) hits @@ -948,15 +948,15 @@ system.cpu3.icache.demand_avg_mshr_miss_latency::total 47941.684665 system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 47941.684665 # average overall mshr miss latency system.cpu3.icache.overall_avg_mshr_miss_latency::total 47941.684665 # average overall mshr miss latency system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.dcache.replacements 61 # number of replacements -system.cpu3.dcache.tagsinuse 273.485257 # Cycle average of tags in use -system.cpu3.dcache.total_refs 180307 # Total number of references to valid blocks. -system.cpu3.dcache.sampled_refs 463 # Sample count of references to valid blocks. -system.cpu3.dcache.avg_refs 389.431965 # Average number of references to valid blocks. -system.cpu3.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.dcache.occ_blocks::cpu3.data 273.485257 # Average occupied blocks per requestor -system.cpu3.dcache.occ_percent::cpu3.data 0.534151 # Average percentage of cache occupancy -system.cpu3.dcache.occ_percent::total 0.534151 # Average percentage of cache occupancy +system.cpu3.dcache.tags.replacements 61 # number of replacements +system.cpu3.dcache.tags.tagsinuse 273.485257 # Cycle average of tags in use +system.cpu3.dcache.tags.total_refs 180307 # Total number of references to valid blocks. +system.cpu3.dcache.tags.sampled_refs 463 # Sample count of references to valid blocks. +system.cpu3.dcache.tags.avg_refs 389.431965 # Average number of references to valid blocks. +system.cpu3.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu3.dcache.tags.occ_blocks::cpu3.data 273.485257 # Average occupied blocks per requestor +system.cpu3.dcache.tags.occ_percent::cpu3.data 0.534151 # Average percentage of cache occupancy +system.cpu3.dcache.tags.occ_percent::total 0.534151 # Average percentage of cache occupancy system.cpu3.dcache.ReadReq_hits::cpu3.data 124107 # number of ReadReq hits system.cpu3.dcache.ReadReq_hits::total 124107 # number of ReadReq hits system.cpu3.dcache.WriteReq_hits::cpu3.data 56200 # number of WriteReq hits @@ -1048,31 +1048,31 @@ system.cpu3.dcache.demand_avg_mshr_miss_latency::total 52306.695464 system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 52306.695464 # average overall mshr miss latency system.cpu3.dcache.overall_avg_mshr_miss_latency::total 52306.695464 # average overall mshr miss latency system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.replacements 0 # number of replacements -system.l2c.tagsinuse 1943.172107 # Cycle average of tags in use -system.l2c.total_refs 332 # Total number of references to valid blocks. -system.l2c.sampled_refs 2932 # Sample count of references to valid blocks. -system.l2c.avg_refs 0.113233 # Average number of references to valid blocks. -system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 17.224555 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 265.011494 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 216.488870 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 265.006320 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 216.484940 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu2.inst 265.001344 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu2.data 216.481052 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu3.inst 264.996369 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu3.data 216.477163 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.000263 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.004044 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.003303 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.004044 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.data 0.003303 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu2.inst 0.004044 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu2.data 0.003303 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu3.inst 0.004044 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu3.data 0.003303 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.029650 # Average percentage of cache occupancy +system.l2c.tags.replacements 0 # number of replacements +system.l2c.tags.tagsinuse 1943.172107 # Cycle average of tags in use +system.l2c.tags.total_refs 332 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 2932 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 0.113233 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 17.224555 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 265.011494 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 216.488870 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 265.006320 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 216.484940 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.inst 265.001344 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.data 216.481052 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3.inst 264.996369 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3.data 216.477163 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.000263 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.004044 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.003303 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.004044 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.003303 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.inst 0.004044 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.data 0.003303 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu3.inst 0.004044 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu3.data 0.003303 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.029650 # Average percentage of cache occupancy system.l2c.ReadReq_hits::cpu0.inst 60 # number of ReadReq hits system.l2c.ReadReq_hits::cpu0.data 9 # number of ReadReq hits system.l2c.ReadReq_hits::cpu1.inst 60 # number of ReadReq hits diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt index 6295c2feb..aa46bcce7 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt @@ -1,71 +1,71 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000110 # Number of seconds simulated -sim_ticks 110344500 # Number of ticks simulated -final_tick 110344500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000111 # Number of seconds simulated +sim_ticks 110804500 # Number of ticks simulated +final_tick 110804500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 97195 # Simulator instruction rate (inst/s) -host_op_rate 97194 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 10306929 # Simulator tick rate (ticks/s) -host_mem_usage 249456 # Number of bytes of host memory used -host_seconds 10.71 # Real time elapsed on the host -sim_insts 1040548 # Number of instructions simulated -sim_ops 1040548 # Number of ops (including micro ops) simulated +host_inst_rate 110530 # Simulator instruction rate (inst/s) +host_op_rate 110530 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 11745373 # Simulator tick rate (ticks/s) +host_mem_usage 249508 # Number of bytes of host memory used +host_seconds 9.43 # Real time elapsed on the host +sim_insts 1042724 # Number of instructions simulated +sim_ops 1042724 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu0.inst 22784 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.data 10752 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 5120 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 1280 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 192 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 832 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 640 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 832 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 4672 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 1280 # Number of bytes read from this memory system.physmem.bytes_read::cpu3.inst 384 # Number of bytes read from this memory system.physmem.bytes_read::cpu3.data 832 # Number of bytes read from this memory system.physmem.bytes_read::total 42176 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu0.inst 22784 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 5120 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 192 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 640 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 4672 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::cpu3.inst 384 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 28480 # Number of instructions bytes read from this memory system.physmem.num_reads::cpu0.inst 356 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.data 168 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 80 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 20 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 3 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 13 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 10 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 13 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 73 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 20 # Number of read requests responded to by this memory system.physmem.num_reads::cpu3.inst 6 # Number of read requests responded to by this memory system.physmem.num_reads::cpu3.data 13 # Number of read requests responded to by this memory system.physmem.num_reads::total 659 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu0.inst 206480613 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 97440289 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 46400138 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 11600034 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 1740005 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 7540022 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.inst 3480010 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.data 7540022 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 382221135 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 206480613 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 46400138 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 1740005 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu3.inst 3480010 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 258100766 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 206480613 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 97440289 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 46400138 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 11600034 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 1740005 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 7540022 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.inst 3480010 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.data 7540022 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 382221135 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 205623418 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 97035770 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 5775939 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 7508720 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 42164353 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 11551877 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.inst 3465563 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.data 7508720 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 380634361 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 205623418 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 5775939 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 42164353 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu3.inst 3465563 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 257029272 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 205623418 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 97035770 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 5775939 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 7508720 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 42164353 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 11551877 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.inst 3465563 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.data 7508720 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 380634361 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 660 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen -system.physmem.cpureqs 735 # Reqs generatd by CPU via cache - shady +system.physmem.cpureqs 736 # Reqs generatd by CPU via cache - shady system.physmem.bytesRead 42176 # Total number of bytes read from memory system.physmem.bytesWritten 0 # Total number of bytes written to memory system.physmem.bytesConsumedRd 42176 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 75 # Reqs where no action is needed +system.physmem.neitherReadNorWrite 76 # Reqs where no action is needed system.physmem.perBankRdReqs::0 115 # Track reads on a per bank basis system.physmem.perBankRdReqs::1 39 # Track reads on a per bank basis system.physmem.perBankRdReqs::2 29 # Track reads on a per bank basis @@ -100,7 +100,7 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 110316500 # Total gap between requests +system.physmem.totGap 110776500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes @@ -115,9 +115,9 @@ system.physmem.writePktSize::3 0 # Ca system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes system.physmem.writePktSize::6 0 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 407 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 192 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 47 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 404 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 193 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 49 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 12 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -180,9 +180,9 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.bytesPerActivate::samples 128 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 282 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 172.796288 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 318.984215 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 281.500000 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 172.723314 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 317.555625 # Bytes accessed per row activation system.physmem.bytesPerActivate::64 51 39.84% 39.84% # Bytes accessed per row activation system.physmem.bytesPerActivate::128 11 8.59% 48.44% # Bytes accessed per row activation system.physmem.bytesPerActivate::192 15 11.72% 60.16% # Bytes accessed per row activation @@ -197,402 +197,402 @@ system.physmem.bytesPerActivate::704 2 1.56% 91.41% # By system.physmem.bytesPerActivate::768 2 1.56% 92.97% # Bytes accessed per row activation system.physmem.bytesPerActivate::832 2 1.56% 94.53% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024 4 3.12% 97.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216 1 0.78% 98.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152 1 0.78% 98.44% # Bytes accessed per row activation system.physmem.bytesPerActivate::1536 1 0.78% 99.22% # Bytes accessed per row activation system.physmem.bytesPerActivate::1984 1 0.78% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 128 # Bytes accessed per row activation -system.physmem.totQLat 3607500 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 17921250 # Sum of mem lat for all requests +system.physmem.totQLat 3818750 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 18118750 # Sum of mem lat for all requests system.physmem.totBusLat 3300000 # Total cycles spent in databus access -system.physmem.totBankLat 11013750 # Total cycles spent in bank access -system.physmem.avgQLat 5465.91 # Average queueing delay per request -system.physmem.avgBankLat 16687.50 # Average bank access latency per request +system.physmem.totBankLat 11000000 # Total cycles spent in bank access +system.physmem.avgQLat 5785.98 # Average queueing delay per request +system.physmem.avgBankLat 16666.67 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 27153.41 # Average memory access latency -system.physmem.avgRdBW 382.22 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 27452.65 # Average memory access latency +system.physmem.avgRdBW 380.63 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 382.22 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 380.63 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 2.99 # Data bus utilization in percentage +system.physmem.busUtil 2.97 # Data bus utilization in percentage system.physmem.avgRdQLen 0.16 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time system.physmem.readRowHits 532 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 80.61 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 167146.21 # Average gap between requests -system.membus.throughput 382221135 # Throughput (bytes/s) +system.physmem.avgGap 167843.18 # Average gap between requests +system.membus.throughput 380634361 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 529 # Transaction distribution system.membus.trans_dist::ReadResp 528 # Transaction distribution -system.membus.trans_dist::UpgradeReq 284 # Transaction distribution -system.membus.trans_dist::UpgradeResp 75 # Transaction distribution -system.membus.trans_dist::ReadExReq 164 # Transaction distribution +system.membus.trans_dist::UpgradeReq 287 # Transaction distribution +system.membus.trans_dist::UpgradeResp 76 # Transaction distribution +system.membus.trans_dist::ReadExReq 163 # Transaction distribution system.membus.trans_dist::ReadExResp 131 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side 1711 # Packet count per connected master and slave (bytes) -system.membus.pkt_count 1711 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side 1714 # Packet count per connected master and slave (bytes) +system.membus.pkt_count 1714 # Packet count per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side 42176 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size 42176 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 42176 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 906000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 929000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.8 # Layer utilization (%) -system.membus.respLayer0.occupancy 6286926 # Layer occupancy (ticks) -system.membus.respLayer0.utilization 5.7 # Layer utilization (%) -system.toL2Bus.throughput 1697085038 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 2531 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2530 # Transaction distribution +system.membus.respLayer1.occupancy 6308925 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 5.7 # Layer utilization (%) +system.toL2Bus.throughput 1691772446 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 2536 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2535 # Transaction distribution system.toL2Bus.trans_dist::Writeback 1 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 287 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 287 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 395 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 395 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 290 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 290 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 393 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 393 # Transaction distribution system.toL2Bus.pkt_count_system.cpu0.icache.mem_side 1175 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side 585 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side 850 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side 363 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu2.icache.mem_side 856 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side 356 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side 586 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side 856 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side 365 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu2.icache.mem_side 850 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side 371 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_count_system.cpu3.icache.mem_side 860 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side 363 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count 5408 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side 352 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count 5415 # Packet count per connected master and slave (bytes) system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side 37568 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side 11136 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side 27200 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side 1600 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu2.icache.mem_side 27392 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu2.dcache.mem_side 1536 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side 27392 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side 1536 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu2.icache.mem_side 27200 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu2.dcache.mem_side 1600 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.tot_pkt_size_system.cpu3.icache.mem_side 27520 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.tot_pkt_size_system.cpu3.dcache.mem_side 1536 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.tot_pkt_size 135488 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.data_through_bus 135488 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 51776 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 1621980 # Layer occupancy (ticks) +system.toL2Bus.snoop_data_through_bus 51968 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 1623982 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 1.5 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 2642498 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 2710248 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 2.4 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 1437498 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 1462515 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 1.3 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 1913498 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 1929494 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 1.7 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 1155972 # Layer occupancy (ticks) -system.toL2Bus.respLayer3.utilization 1.0 # Layer utilization (%) -system.toL2Bus.respLayer4.occupancy 1929492 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 1189495 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.utilization 1.1 # Layer utilization (%) +system.toL2Bus.respLayer4.occupancy 1927246 # Layer occupancy (ticks) system.toL2Bus.respLayer4.utilization 1.7 # Layer utilization (%) -system.toL2Bus.respLayer5.occupancy 1158481 # Layer occupancy (ticks) -system.toL2Bus.respLayer5.utilization 1.0 # Layer utilization (%) -system.toL2Bus.respLayer6.occupancy 1936496 # Layer occupancy (ticks) -system.toL2Bus.respLayer6.utilization 1.8 # Layer utilization (%) -system.toL2Bus.respLayer7.occupancy 1165479 # Layer occupancy (ticks) -system.toL2Bus.respLayer7.utilization 1.1 # Layer utilization (%) -system.cpu0.branchPred.lookups 82851 # Number of BP lookups -system.cpu0.branchPred.condPredicted 80650 # Number of conditional branches predicted +system.toL2Bus.respLayer5.occupancy 1192987 # Layer occupancy (ticks) +system.toL2Bus.respLayer5.utilization 1.1 # Layer utilization (%) +system.toL2Bus.respLayer6.occupancy 1937245 # Layer occupancy (ticks) +system.toL2Bus.respLayer6.utilization 1.7 # Layer utilization (%) +system.toL2Bus.respLayer7.occupancy 1118007 # Layer occupancy (ticks) +system.toL2Bus.respLayer7.utilization 1.0 # Layer utilization (%) +system.cpu0.branchPred.lookups 82992 # Number of BP lookups +system.cpu0.branchPred.condPredicted 80791 # Number of conditional branches predicted system.cpu0.branchPred.condIncorrect 1218 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 80180 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 78131 # Number of BTB hits +system.cpu0.branchPred.BTBLookups 80321 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 78273 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 97.444500 # BTB Hit Percentage +system.cpu0.branchPred.BTBHitPct 97.450231 # BTB Hit Percentage system.cpu0.branchPred.usedRAS 512 # Number of times the RAS was used to get a target. system.cpu0.branchPred.RASInCorrect 132 # Number of incorrect RAS predictions. system.cpu0.workload.num_syscalls 89 # Number of system calls -system.cpu0.numCycles 220690 # number of cpu cycles simulated +system.cpu0.numCycles 221610 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 17257 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 491686 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 82851 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 78643 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 161395 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 3805 # Number of cycles fetch has spent squashing -system.cpu0.fetch.BlockedCycles 13763 # Number of cycles fetch has spent blocked +system.cpu0.fetch.icacheStallCycles 17247 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 492529 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 82992 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 78785 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 161677 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 3808 # Number of cycles fetch has spent squashing +system.cpu0.fetch.BlockedCycles 13819 # Number of cycles fetch has spent blocked system.cpu0.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 1562 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingTrapStallCycles 1570 # Number of stall cycles due to pending traps system.cpu0.fetch.CacheLines 5835 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 494 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.rateDist::samples 196421 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 2.503225 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.215279 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.IcacheSquashes 493 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.rateDist::samples 196760 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 2.503197 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.215126 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 35026 17.83% 17.83% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 79943 40.70% 58.53% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 35083 17.83% 17.83% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 80084 40.70% 58.53% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::2 578 0.29% 58.83% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 973 0.50% 59.32% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 973 0.49% 59.32% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::4 477 0.24% 59.56% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 76047 38.72% 98.28% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 76189 38.72% 98.28% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::6 571 0.29% 98.57% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::7 349 0.18% 98.75% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 2457 1.25% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 2456 1.25% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 196421 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.375418 # Number of branch fetches per cycle -system.cpu0.fetch.rate 2.227949 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 17908 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 15370 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 160419 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 285 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 2439 # Number of cycles decode is squashing -system.cpu0.decode.DecodedInsts 488842 # Number of instructions handled by decode -system.cpu0.rename.SquashCycles 2439 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 18575 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 759 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 14008 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 160070 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 570 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 485981 # Number of instructions processed by rename -system.cpu0.rename.LSQFullEvents 199 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.RenamedOperands 332328 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 969157 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 969157 # Number of integer rename lookups -system.cpu0.rename.CommittedMaps 319407 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 12921 # Number of HB maps that are undone due to squashing +system.cpu0.fetch.rateDist::total 196760 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.374496 # Number of branch fetches per cycle +system.cpu0.fetch.rate 2.222503 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 17898 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 15432 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 160701 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 287 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 2442 # Number of cycles decode is squashing +system.cpu0.decode.DecodedInsts 489694 # Number of instructions handled by decode +system.cpu0.rename.SquashCycles 2442 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 18563 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 848 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 13994 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 160355 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 558 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 486837 # Number of instructions processed by rename +system.cpu0.rename.LSQFullEvents 188 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.RenamedOperands 332900 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 970872 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 970872 # Number of integer rename lookups +system.cpu0.rename.CommittedMaps 319955 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 12945 # Number of HB maps that are undone due to squashing system.cpu0.rename.serializingInsts 867 # count of serializing insts renamed system.cpu0.rename.tempSerializingInsts 888 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 3600 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 155469 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 78571 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 75822 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 75638 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 406410 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.rename.skidInsts 3605 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 155755 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 78714 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 75965 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 75781 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 407125 # Number of instructions added to the IQ (excludes non-spec) system.cpu0.iq.iqNonSpecInstsAdded 911 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 403726 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 135 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 10718 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 9636 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqInstsIssued 404423 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 128 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 10748 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 9686 # Number of squashed operands that are examined and possibly removed from graph system.cpu0.iq.iqSquashedNonSpecRemoved 352 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 196421 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 2.055412 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.097532 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::samples 196760 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 2.055413 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.097364 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 34004 17.31% 17.31% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 4909 2.50% 19.81% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 77804 39.61% 59.42% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 77117 39.26% 98.68% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 1569 0.80% 99.48% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 649 0.33% 99.81% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 264 0.13% 99.95% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 87 0.04% 99.99% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 18 0.01% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 34065 17.31% 17.31% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 4908 2.49% 19.81% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 77935 39.61% 59.42% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 77266 39.27% 98.69% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 1571 0.80% 99.48% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 648 0.33% 99.81% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 262 0.13% 99.95% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 89 0.05% 99.99% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 16 0.01% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 196421 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 196760 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 57 25.68% 25.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 0 0.00% 25.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 25.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 25.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 25.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 25.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 25.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 25.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 25.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 25.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 25.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 25.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 25.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 25.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 25.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 25.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 25.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 25.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 25.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 25.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 25.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 25.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 25.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 25.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 25.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 25.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 25.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 25.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 25.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 53 23.87% 49.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 112 50.45% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 57 25.91% 25.91% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 0 0.00% 25.91% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 25.91% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 25.91% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 25.91% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 25.91% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 25.91% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 25.91% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 25.91% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 25.91% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 25.91% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 25.91% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 25.91% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 25.91% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 25.91% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 25.91% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 25.91% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 25.91% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 25.91% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 25.91% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 25.91% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 25.91% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 25.91% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 25.91% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 25.91% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 25.91% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 25.91% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 25.91% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 25.91% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 51 23.18% 49.09% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 112 50.91% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 170720 42.29% 42.29% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 0 0.00% 42.29% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 42.29% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 42.29% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 42.29% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 42.29% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 42.29% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 42.29% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 42.29% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 42.29% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 42.29% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 42.29% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 42.29% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 42.29% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 42.29% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 42.29% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 42.29% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 42.29% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 42.29% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 42.29% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.29% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.29% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.29% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.29% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.29% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 42.29% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 42.29% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 42.29% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.29% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 155014 38.40% 80.68% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 77992 19.32% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 170994 42.28% 42.28% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 0 0.00% 42.28% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 42.28% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 42.28% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 42.28% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 42.28% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 42.28% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 42.28% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 42.28% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 42.28% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 42.28% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 42.28% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 42.28% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 42.28% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 42.28% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 42.28% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 42.28% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 42.28% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 42.28% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 42.28% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.28% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.28% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.28% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.28% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.28% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 42.28% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 42.28% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 42.28% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.28% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 155300 38.40% 80.68% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 78129 19.32% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 403726 # Type of FU issued -system.cpu0.iq.rate 1.829381 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 222 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.000550 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 1004230 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 418093 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 401910 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.FU_type_0::total 404423 # Type of FU issued +system.cpu0.iq.rate 1.824931 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 220 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.000544 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 1005954 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 418838 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 402603 # Number of integer instruction queue wakeup accesses system.cpu0.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu0.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu0.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 403948 # Number of integer alu accesses +system.cpu0.iq.int_alu_accesses 404643 # Number of integer alu accesses system.cpu0.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 75361 # Number of loads that had data forwarded from stores +system.cpu0.iew.lsq.thread0.forwLoads 75498 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 2176 # Number of loads squashed +system.cpu0.iew.lsq.thread0.squashedLoads 2188 # Number of loads squashed system.cpu0.iew.lsq.thread0.ignoredResponses 4 # Number of memory responses ignored because the instruction is squashed system.cpu0.iew.lsq.thread0.memOrderViolation 54 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 1418 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedStores 1424 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu0.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 20 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.cacheBlocked 19 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 2439 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 333 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 32 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 483693 # Number of instructions dispatched to IQ +system.cpu0.iew.iewSquashCycles 2442 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 391 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 33 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 484551 # Number of instructions dispatched to IQ system.cpu0.iew.iewDispSquashedInsts 313 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 155469 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 78571 # Number of dispatched store instructions +system.cpu0.iew.iewDispLoadInsts 155755 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 78714 # Number of dispatched store instructions system.cpu0.iew.iewDispNonSpecInsts 799 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 37 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewIQFullEvents 38 # Number of times the IQ has become full, causing a stall system.cpu0.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu0.iew.memOrderViolationEvents 54 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 342 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedTakenIncorrect 343 # Number of branches that were predicted taken incorrectly system.cpu0.iew.predictedNotTakenIncorrect 1106 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 1448 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 402662 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 154684 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 1064 # Number of squashed instructions skipped in execute +system.cpu0.iew.branchMispredicts 1449 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 403352 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 154964 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 1071 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 76372 # number of nop insts executed -system.cpu0.iew.exec_refs 232577 # number of memory reference insts executed -system.cpu0.iew.exec_branches 79993 # Number of branches executed -system.cpu0.iew.exec_stores 77893 # Number of stores executed -system.cpu0.iew.exec_rate 1.824559 # Inst execution rate -system.cpu0.iew.wb_sent 402239 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 401910 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 238133 # num instructions producing a value -system.cpu0.iew.wb_consumers 240585 # num instructions consuming a value +system.cpu0.iew.exec_nop 76515 # number of nop insts executed +system.cpu0.iew.exec_refs 232993 # number of memory reference insts executed +system.cpu0.iew.exec_branches 80132 # Number of branches executed +system.cpu0.iew.exec_stores 78029 # Number of stores executed +system.cpu0.iew.exec_rate 1.820098 # Inst execution rate +system.cpu0.iew.wb_sent 402944 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 402603 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 238549 # num instructions producing a value +system.cpu0.iew.wb_consumers 241004 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 1.821152 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.989808 # average fanout of values written-back +system.cpu0.iew.wb_rate 1.816719 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.989813 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 12210 # The number of squashed insts skipped by commit +system.cpu0.commit.commitSquashedInsts 12240 # The number of squashed insts skipped by commit system.cpu0.commit.commitNonSpecStalls 559 # The number of times commit has been forced to stall to communicate backwards system.cpu0.commit.branchMispredicts 1218 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 193982 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 2.430442 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 2.136125 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::samples 194318 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 2.430470 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 2.136197 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 34427 17.75% 17.75% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 79760 41.12% 58.86% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 2402 1.24% 60.10% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 693 0.36% 60.46% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 529 0.27% 60.73% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 75180 38.76% 99.49% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 442 0.23% 99.72% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 241 0.12% 99.84% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 308 0.16% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 34493 17.75% 17.75% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 79895 41.12% 58.87% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 2401 1.24% 60.10% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 689 0.35% 60.46% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 530 0.27% 60.73% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 75316 38.76% 99.49% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 445 0.23% 99.72% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 242 0.12% 99.84% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 307 0.16% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 193982 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 471462 # Number of instructions committed -system.cpu0.commit.committedOps 471462 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 194318 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 472284 # Number of instructions committed +system.cpu0.commit.committedOps 472284 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 230446 # Number of memory references committed -system.cpu0.commit.loads 153293 # Number of loads committed +system.cpu0.commit.refs 230857 # Number of memory references committed +system.cpu0.commit.loads 153567 # Number of loads committed system.cpu0.commit.membars 84 # Number of memory barriers committed -system.cpu0.commit.branches 79040 # Number of branches committed +system.cpu0.commit.branches 79177 # Number of branches committed system.cpu0.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 317738 # Number of committed integer instructions. +system.cpu0.commit.int_insts 318286 # Number of committed integer instructions. system.cpu0.commit.function_calls 223 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 308 # number cycles where commit BW limit reached +system.cpu0.commit.bw_lim_events 307 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 676185 # The number of ROB reads -system.cpu0.rob.rob_writes 969800 # The number of ROB writes +system.cpu0.rob.rob_reads 677374 # The number of ROB reads +system.cpu0.rob.rob_writes 971507 # The number of ROB writes system.cpu0.timesIdled 326 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 24269 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.committedInsts 395606 # Number of Instructions Simulated -system.cpu0.committedOps 395606 # Number of Ops (including micro ops) Simulated -system.cpu0.committedInsts_total 395606 # Number of Instructions Simulated -system.cpu0.cpi 0.557853 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 0.557853 # CPI: Total CPI of All Threads -system.cpu0.ipc 1.792587 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 1.792587 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 720352 # number of integer regfile reads -system.cpu0.int_regfile_writes 324661 # number of integer regfile writes +system.cpu0.idleCycles 24850 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.committedInsts 396291 # Number of Instructions Simulated +system.cpu0.committedOps 396291 # Number of Ops (including micro ops) Simulated +system.cpu0.committedInsts_total 396291 # Number of Instructions Simulated +system.cpu0.cpi 0.559210 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 0.559210 # CPI: Total CPI of All Threads +system.cpu0.ipc 1.788236 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 1.788236 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 721592 # number of integer regfile reads +system.cpu0.int_regfile_writes 325227 # number of integer regfile writes system.cpu0.fp_regfile_reads 192 # number of floating regfile reads -system.cpu0.misc_regfile_reads 234400 # number of misc regfile reads +system.cpu0.misc_regfile_reads 234817 # number of misc regfile reads system.cpu0.misc_regfile_writes 564 # number of misc regfile writes -system.cpu0.icache.replacements 297 # number of replacements -system.cpu0.icache.tagsinuse 241.066229 # Cycle average of tags in use -system.cpu0.icache.total_refs 5081 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 587 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 8.655877 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 241.066229 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.470832 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.470832 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 5081 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 5081 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 5081 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 5081 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 5081 # number of overall hits -system.cpu0.icache.overall_hits::total 5081 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 754 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 754 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 754 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 754 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 754 # number of overall misses -system.cpu0.icache.overall_misses::total 754 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 34643000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 34643000 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 34643000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 34643000 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 34643000 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 34643000 # number of overall miss cycles +system.cpu0.icache.tags.replacements 297 # number of replacements +system.cpu0.icache.tags.tagsinuse 241.148232 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 5079 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 587 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 8.652470 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 241.148232 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.470993 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.470993 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 5079 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 5079 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 5079 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 5079 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 5079 # number of overall hits +system.cpu0.icache.overall_hits::total 5079 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 756 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 756 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 756 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 756 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 756 # number of overall misses +system.cpu0.icache.overall_misses::total 756 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 35147245 # 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average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 45945.623342 # average overall miss latency +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.129563 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.129563 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.129563 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.129563 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.129563 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.129563 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 46491.064815 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 46491.064815 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 46491.064815 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 46491.064815 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 46491.064815 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 46491.064815 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -601,582 +601,583 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 166 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 166 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 166 # 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number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 27250252 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 27250252 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 27250252 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 27250252 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.100771 # mshr miss rate for ReadReq accesses system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.100771 # mshr miss rate for ReadReq accesses system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.100771 # mshr miss rate for demand accesses system.cpu0.icache.demand_mshr_miss_rate::total 0.100771 # mshr miss rate for demand accesses system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.100771 # mshr miss rate for overall accesses system.cpu0.icache.overall_mshr_miss_rate::total 0.100771 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 45925.173469 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 45925.173469 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 45925.173469 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 45925.173469 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 45925.173469 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 45925.173469 # average overall mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 46343.965986 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 46343.965986 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 46343.965986 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 46343.965986 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 46343.965986 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 46343.965986 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 2 # number of replacements -system.cpu0.dcache.tagsinuse 141.846177 # Cycle average of tags in use -system.cpu0.dcache.total_refs 155338 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 170 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 913.752941 # Average number of references to valid blocks. -system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 141.846177 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.277043 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.277043 # 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number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.005163 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.005163 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007055 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.007055 # miss rate for WriteReq accesses system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.500000 # miss rate for SwapReq accesses system.cpu0.dcache.SwapReq_miss_rate::total 0.500000 # miss rate for SwapReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.006082 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.006082 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.006082 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.006082 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 31405.172414 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 31405.172414 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 65129.324771 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 65129.324771 # average WriteReq miss latency -system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 19833.333333 # average SwapReq miss latency -system.cpu0.dcache.SwapReq_avg_miss_latency::total 19833.333333 # average SwapReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 50731.842271 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 50731.842271 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 50731.842271 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 50731.842271 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 499 # number of cycles access was blocked +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.006096 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.006096 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.006096 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.006096 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 32485.865854 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 32485.865854 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 64496.339450 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 64496.339450 # average WriteReq miss latency +system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 19940.476190 # average SwapReq miss latency +system.cpu0.dcache.SwapReq_avg_miss_latency::total 19940.476190 # average SwapReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 50753.623037 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 50753.623037 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 50753.623037 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 50753.623037 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 503 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 21 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 23.761905 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 23.952381 # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed system.cpu0.dcache.writebacks::writebacks 1 # number of writebacks system.cpu0.dcache.writebacks::total 1 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 220 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 220 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 223 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 223 # number of ReadReq MSHR hits system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 370 # number of WriteReq MSHR hits system.cpu0.dcache.WriteReq_mshr_hits::total 370 # number of WriteReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 590 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 590 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 590 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 590 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 186 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 186 # number of ReadReq MSHR misses +system.cpu0.dcache.demand_mshr_hits::cpu0.data 593 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 593 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 593 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 593 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 187 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 187 # number of ReadReq MSHR misses system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 175 # number of WriteReq MSHR misses system.cpu0.dcache.WriteReq_mshr_misses::total 175 # number of WriteReq MSHR misses system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data 21 # number of SwapReq MSHR misses system.cpu0.dcache.SwapReq_mshr_misses::total 21 # number of SwapReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 361 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 361 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 361 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 361 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 6035502 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6035502 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7873000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7873000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 374500 # number of SwapReq MSHR miss cycles -system.cpu0.dcache.SwapReq_mshr_miss_latency::total 374500 # number of SwapReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 13908502 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 13908502 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 13908502 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 13908502 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.002347 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.002347 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.002269 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.002269 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 362 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 362 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 362 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 362 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 6285007 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6285007 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7788228 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7788228 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 375250 # number of SwapReq MSHR miss cycles +system.cpu0.dcache.SwapReq_mshr_miss_latency::total 375250 # number of SwapReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 14073235 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 14073235 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 14073235 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 14073235 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.002355 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.002355 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.002265 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.002265 # mshr miss rate for WriteReq accesses system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.500000 # mshr miss rate for SwapReq accesses system.cpu0.dcache.SwapReq_mshr_miss_rate::total 0.500000 # mshr miss rate for SwapReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.002309 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.002309 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.002309 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.002309 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 32448.935484 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 32448.935484 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 44988.571429 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 44988.571429 # average WriteReq mshr miss latency -system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 17833.333333 # average SwapReq mshr miss latency -system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 17833.333333 # average SwapReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 38527.706371 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 38527.706371 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 38527.706371 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 38527.706371 # average overall mshr miss latency +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.002311 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.002311 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.002311 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.002311 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 33609.663102 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 33609.663102 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 44504.160000 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 44504.160000 # average WriteReq mshr miss latency +system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 17869.047619 # average SwapReq mshr miss latency +system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 17869.047619 # average SwapReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 38876.339779 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 38876.339779 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 38876.339779 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 38876.339779 # average overall mshr miss latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 58259 # Number of BP lookups -system.cpu1.branchPred.condPredicted 55591 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 1274 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 52252 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 51480 # Number of BTB hits +system.cpu1.branchPred.lookups 43495 # Number of BP lookups +system.cpu1.branchPred.condPredicted 40766 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 1279 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 37360 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 36580 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 98.522545 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 650 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.BTBHitPct 97.912206 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 665 # Number of times the RAS was used to get a target. system.cpu1.branchPred.RASInCorrect 232 # Number of incorrect RAS predictions. -system.cpu1.numCycles 176870 # number of cpu cycles simulated +system.cpu1.numCycles 177681 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 24483 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 332703 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 58259 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 52130 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 112942 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 3669 # Number of cycles fetch has spent squashing -system.cpu1.fetch.BlockedCycles 23224 # Number of cycles fetch has spent blocked -system.cpu1.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.NoActiveThreadStallCycles 7326 # Number of stall cycles due to no active thread to fetch from -system.cpu1.fetch.PendingTrapStallCycles 755 # Number of stall cycles due to pending traps -system.cpu1.fetch.CacheLines 15523 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 269 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.rateDist::samples 171052 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 1.945040 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.217476 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 34028 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 233746 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 43495 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 37245 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 88254 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 3762 # Number of cycles fetch has spent squashing +system.cpu1.fetch.BlockedCycles 42089 # Number of cycles fetch has spent blocked +system.cpu1.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.NoActiveThreadStallCycles 7739 # Number of stall cycles due to no active thread to fetch from +system.cpu1.fetch.PendingTrapStallCycles 785 # Number of stall cycles due to pending traps +system.cpu1.fetch.CacheLines 25656 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 258 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.rateDist::samples 175306 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 1.333360 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 1.985884 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 58110 33.97% 33.97% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 56330 32.93% 66.90% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 4061 2.37% 69.28% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 3192 1.87% 71.14% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 642 0.38% 71.52% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 43436 25.39% 96.91% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 1285 0.75% 97.66% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 751 0.44% 98.10% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 3245 1.90% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 87052 49.66% 49.66% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 46435 26.49% 76.15% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 9084 5.18% 81.33% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 3194 1.82% 83.15% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 686 0.39% 83.54% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 23635 13.48% 97.02% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 1173 0.67% 97.69% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 772 0.44% 98.13% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 3275 1.87% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 171052 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.329389 # Number of branch fetches per cycle -system.cpu1.fetch.rate 1.881060 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 27575 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 21737 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 108940 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 3156 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 2318 # Number of cycles decode is squashing -system.cpu1.decode.DecodedInsts 329200 # Number of instructions handled by decode -system.cpu1.rename.SquashCycles 2318 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 28271 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 9057 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 11940 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 106039 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 6101 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 326983 # Number of instructions processed by rename -system.cpu1.rename.LSQFullEvents 23 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.RenamedOperands 231035 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 638817 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 638817 # Number of integer rename lookups -system.cpu1.rename.CommittedMaps 218174 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 12861 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 1086 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 1205 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 8759 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 95375 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 46677 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 44840 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 41648 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 274055 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 4247 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 274319 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 86 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 10569 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 10360 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 496 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 171052 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 1.603717 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.300528 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 175306 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.244793 # Number of branch fetches per cycle +system.cpu1.fetch.rate 1.315537 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 41969 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 35783 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 79597 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 7812 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 2406 # Number of cycles decode is squashing +system.cpu1.decode.DecodedInsts 230200 # Number of instructions handled by decode +system.cpu1.rename.SquashCycles 2406 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 42677 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 23059 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 11946 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 72053 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 15426 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 227940 # Number of instructions processed by rename +system.cpu1.rename.IQFullEvents 4 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LSQFullEvents 19 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.RenamedOperands 156532 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 420697 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 420697 # Number of integer rename lookups +system.cpu1.rename.CommittedMaps 143693 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 12839 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 1114 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 1240 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 18203 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 60713 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 26873 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 30033 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 21821 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 184781 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 9329 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 189617 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 108 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 10957 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 10934 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 690 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 175306 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 1.081634 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.264768 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 55274 32.31% 32.31% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 16462 9.62% 41.94% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 46955 27.45% 69.39% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 47561 27.80% 97.19% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 3274 1.91% 99.11% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 1158 0.68% 99.78% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 257 0.15% 99.94% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 84668 48.30% 48.30% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 30997 17.68% 65.98% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 27119 15.47% 81.45% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 27768 15.84% 97.29% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 3226 1.84% 99.13% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 1160 0.66% 99.79% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 259 0.15% 99.94% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::7 52 0.03% 99.97% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 59 0.03% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 57 0.03% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 171052 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 175306 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 17 6.05% 6.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 0 0.00% 6.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 6.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 6.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 6.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 6.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 6.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 6.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 6.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 6.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 6.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 6.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 6.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 6.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 6.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 6.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 6.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 6.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 6.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 6.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 6.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 6.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 6.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 6.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 6.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 6.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 6.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 6.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 54 19.22% 25.27% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 210 74.73% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 12 4.55% 4.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 0 0.00% 4.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 4.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 4.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 4.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 4.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 4.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 4.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 4.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 4.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 4.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 4.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 4.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 4.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 4.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 4.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 4.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 4.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 4.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 4.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 4.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 4.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 4.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 4.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 4.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 4.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 4.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 4.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 42 15.91% 20.45% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 210 79.55% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 130533 47.58% 47.58% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 0 0.00% 47.58% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 47.58% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 47.58% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 47.58% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 47.58% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 47.58% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 47.58% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 47.58% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 47.58% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 47.58% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 47.58% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 47.58% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 47.58% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 47.58% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 47.58% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 47.58% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 47.58% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 47.58% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 47.58% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.58% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.58% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.58% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.58% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.58% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 47.58% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 47.58% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.58% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.58% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 97787 35.65% 83.23% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 45999 16.77% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 95616 50.43% 50.43% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 0 0.00% 50.43% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 50.43% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 50.43% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 50.43% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 50.43% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 50.43% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 50.43% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 50.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 50.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 50.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 50.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 50.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 50.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 50.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 50.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 50.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 50.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 50.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 50.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 50.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 50.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 50.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 50.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 50.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 50.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 50.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 50.43% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 50.43% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 67820 35.77% 86.19% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 26181 13.81% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 274319 # Type of FU issued -system.cpu1.iq.rate 1.550964 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 281 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.001024 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 720057 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 288914 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 272470 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.FU_type_0::total 189617 # Type of FU issued +system.cpu1.iq.rate 1.067177 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 264 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.001392 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 554912 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 205110 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 187814 # Number of integer instruction queue wakeup accesses system.cpu1.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu1.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu1.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 274600 # Number of integer alu accesses +system.cpu1.iq.int_alu_accesses 189881 # Number of integer alu accesses system.cpu1.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 41423 # Number of loads that had data forwarded from stores +system.cpu1.iew.lsq.thread0.forwLoads 21562 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 2326 # Number of loads squashed +system.cpu1.iew.lsq.thread0.squashedLoads 2474 # Number of loads squashed system.cpu1.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed system.cpu1.iew.lsq.thread0.memOrderViolation 43 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 1418 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedStores 1439 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu1.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu1.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 2318 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 743 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 46 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 324068 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 389 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 95375 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 46677 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 1041 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 46 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewSquashCycles 2406 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 736 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 43 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 225068 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 373 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 60713 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 26873 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 1076 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 42 # Number of times the IQ has become full, causing a stall system.cpu1.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu1.iew.memOrderViolationEvents 43 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 463 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 924 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 1387 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 273134 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 94466 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 1185 # Number of squashed instructions skipped in execute +system.cpu1.iew.predictedTakenIncorrect 453 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 939 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 1392 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 188449 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 59619 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 1168 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 45766 # number of nop insts executed -system.cpu1.iew.exec_refs 140389 # number of memory reference insts executed -system.cpu1.iew.exec_branches 55097 # Number of branches executed -system.cpu1.iew.exec_stores 45923 # Number of stores executed -system.cpu1.iew.exec_rate 1.544264 # Inst execution rate -system.cpu1.iew.wb_sent 272765 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 272470 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 157153 # num instructions producing a value -system.cpu1.iew.wb_consumers 161823 # num instructions consuming a value +system.cpu1.iew.exec_nop 30958 # number of nop insts executed +system.cpu1.iew.exec_refs 85720 # number of memory reference insts executed +system.cpu1.iew.exec_branches 40129 # Number of branches executed +system.cpu1.iew.exec_stores 26101 # Number of stores executed +system.cpu1.iew.exec_rate 1.060603 # Inst execution rate +system.cpu1.iew.wb_sent 188127 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 187814 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 102456 # num instructions producing a value +system.cpu1.iew.wb_consumers 107134 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 1.540510 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.971141 # average fanout of values written-back +system.cpu1.iew.wb_rate 1.057029 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.956335 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 12117 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 3751 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 1274 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 161408 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 1.932674 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 2.096378 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 12618 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 8639 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 1279 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 165161 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 1.286212 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.860966 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 51564 31.95% 31.95% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 53244 32.99% 64.93% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 6086 3.77% 68.70% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 4696 2.91% 71.61% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 1571 0.97% 72.59% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 41954 25.99% 98.58% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 476 0.29% 98.87% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 1001 0.62% 99.49% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 816 0.51% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 85256 51.62% 51.62% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 38272 23.17% 74.79% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 6084 3.68% 78.48% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 9527 5.77% 84.24% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 1571 0.95% 85.20% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 22201 13.44% 98.64% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 436 0.26% 98.90% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 1006 0.61% 99.51% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 808 0.49% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 161408 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 311949 # Number of instructions committed -system.cpu1.commit.committedOps 311949 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 165161 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 212432 # Number of instructions committed +system.cpu1.commit.committedOps 212432 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 138308 # Number of memory references committed -system.cpu1.commit.loads 93049 # Number of loads committed -system.cpu1.commit.membars 3038 # Number of memory barriers committed -system.cpu1.commit.branches 54264 # Number of branches committed +system.cpu1.commit.refs 83673 # Number of memory references committed +system.cpu1.commit.loads 58239 # Number of loads committed +system.cpu1.commit.membars 7917 # Number of memory barriers committed +system.cpu1.commit.branches 39308 # Number of branches committed system.cpu1.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 214693 # Number of committed integer instructions. +system.cpu1.commit.int_insts 145097 # Number of committed integer instructions. system.cpu1.commit.function_calls 322 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 816 # number cycles where commit BW limit reached +system.cpu1.commit.bw_lim_events 808 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 484071 # The number of ROB reads -system.cpu1.rob.rob_writes 650455 # The number of ROB writes -system.cpu1.timesIdled 222 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 5818 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 43818 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 263856 # Number of Instructions Simulated -system.cpu1.committedOps 263856 # Number of Ops (including micro ops) Simulated -system.cpu1.committedInsts_total 263856 # Number of Instructions Simulated -system.cpu1.cpi 0.670328 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 0.670328 # CPI: Total CPI of All Threads -system.cpu1.ipc 1.491808 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 1.491808 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 479823 # number of integer regfile reads -system.cpu1.int_regfile_writes 223101 # number of integer regfile writes +system.cpu1.rob.rob_reads 388816 # The number of ROB reads +system.cpu1.rob.rob_writes 452512 # The number of ROB writes +system.cpu1.timesIdled 218 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 2375 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 43927 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 174425 # Number of Instructions Simulated +system.cpu1.committedOps 174425 # Number of Ops (including micro ops) Simulated +system.cpu1.committedInsts_total 174425 # Number of Instructions Simulated +system.cpu1.cpi 1.018667 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 1.018667 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.981675 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.981675 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 315718 # number of integer regfile reads +system.cpu1.int_regfile_writes 148477 # number of integer regfile writes system.cpu1.fp_regfile_writes 64 # number of floating regfile writes -system.cpu1.misc_regfile_reads 141972 # number of misc regfile reads +system.cpu1.misc_regfile_reads 87269 # number of misc regfile reads system.cpu1.misc_regfile_writes 648 # number of misc regfile writes -system.cpu1.icache.replacements 317 # number of replacements -system.cpu1.icache.tagsinuse 82.334562 # Cycle average of tags in use -system.cpu1.icache.total_refs 15036 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 425 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 35.378824 # Average number of references to valid blocks. -system.cpu1.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 82.334562 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.160810 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.160810 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 15036 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 15036 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 15036 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 15036 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 15036 # number of overall hits -system.cpu1.icache.overall_hits::total 15036 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 487 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 487 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 487 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 487 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 487 # number of overall misses -system.cpu1.icache.overall_misses::total 487 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 12109000 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 12109000 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 12109000 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 12109000 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 12109000 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 12109000 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 15523 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 15523 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 15523 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 15523 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 15523 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 15523 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.031373 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.031373 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.031373 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.031373 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.031373 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.031373 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 24864.476386 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 24864.476386 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 24864.476386 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 24864.476386 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 24864.476386 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 24864.476386 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 84 # number of cycles access was blocked +system.cpu1.icache.tags.replacements 318 # number of replacements +system.cpu1.icache.tags.tagsinuse 79.958659 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 25178 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 428 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 58.827103 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 79.958659 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.156169 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.156169 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 25178 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 25178 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 25178 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 25178 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 25178 # number of overall hits +system.cpu1.icache.overall_hits::total 25178 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 478 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 478 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 478 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 478 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 478 # number of overall misses +system.cpu1.icache.overall_misses::total 478 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7224243 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 7224243 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 7224243 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 7224243 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 7224243 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 7224243 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 25656 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 25656 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 25656 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 25656 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 25656 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 25656 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.018631 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.018631 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.018631 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.018631 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.018631 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.018631 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 15113.479079 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 15113.479079 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 15113.479079 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 15113.479079 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 15113.479079 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 15113.479079 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 26 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 1 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 2 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 84 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 13 # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 62 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 62 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 62 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 62 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 62 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 62 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 425 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 425 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 425 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 425 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 425 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 425 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 9721502 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 9721502 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 9721502 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 9721502 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 9721502 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 9721502 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.027379 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.027379 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.027379 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.027379 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.027379 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.027379 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 22874.122353 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 22874.122353 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 22874.122353 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 22874.122353 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 22874.122353 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 22874.122353 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 50 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 50 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 50 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 50 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 50 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 50 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 428 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 428 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 428 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 428 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 428 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 428 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5769006 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 5769006 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5769006 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 5769006 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5769006 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 5769006 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.016682 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.016682 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.016682 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.016682 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.016682 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.016682 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13478.985981 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 13478.985981 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13478.985981 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 13478.985981 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13478.985981 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 13478.985981 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.replacements 0 # number of replacements -system.cpu1.dcache.tagsinuse 26.168894 # Cycle average of tags in use -system.cpu1.dcache.total_refs 51272 # Total number of references to valid blocks. -system.cpu1.dcache.sampled_refs 28 # Sample count of references to valid blocks. -system.cpu1.dcache.avg_refs 1831.142857 # Average number of references to valid blocks. -system.cpu1.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::cpu1.data 26.168894 # Average occupied blocks per requestor -system.cpu1.dcache.occ_percent::cpu1.data 0.051111 # Average percentage of cache occupancy -system.cpu1.dcache.occ_percent::total 0.051111 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::cpu1.data 52686 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 52686 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 45050 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 45050 # number of WriteReq hits -system.cpu1.dcache.SwapReq_hits::cpu1.data 11 # number of SwapReq hits -system.cpu1.dcache.SwapReq_hits::total 11 # number of SwapReq hits -system.cpu1.dcache.demand_hits::cpu1.data 97736 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 97736 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 97736 # number of overall hits -system.cpu1.dcache.overall_hits::total 97736 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 340 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 340 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 142 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 142 # number of WriteReq misses -system.cpu1.dcache.SwapReq_misses::cpu1.data 56 # number of SwapReq misses -system.cpu1.dcache.SwapReq_misses::total 56 # number of SwapReq misses -system.cpu1.dcache.demand_misses::cpu1.data 482 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 482 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 482 # number of overall misses -system.cpu1.dcache.overall_misses::total 482 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 5254500 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 5254500 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 3040000 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 3040000 # number of WriteReq miss cycles -system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 532000 # number of SwapReq miss cycles -system.cpu1.dcache.SwapReq_miss_latency::total 532000 # number of SwapReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 8294500 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 8294500 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 8294500 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 8294500 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 53026 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 53026 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 45192 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 45192 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SwapReq_accesses::cpu1.data 67 # number of SwapReq accesses(hits+misses) -system.cpu1.dcache.SwapReq_accesses::total 67 # number of SwapReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 98218 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 98218 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 98218 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 98218 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.006412 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.006412 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.003142 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.003142 # miss rate for WriteReq accesses -system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.835821 # miss rate for SwapReq accesses -system.cpu1.dcache.SwapReq_miss_rate::total 0.835821 # miss rate for SwapReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.004907 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.004907 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.004907 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.004907 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15454.411765 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 15454.411765 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 21408.450704 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 21408.450704 # average WriteReq miss latency -system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 9500 # average SwapReq miss latency -system.cpu1.dcache.SwapReq_avg_miss_latency::total 9500 # average SwapReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 17208.506224 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 17208.506224 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 17208.506224 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 17208.506224 # average overall miss latency +system.cpu1.dcache.tags.replacements 0 # number of replacements +system.cpu1.dcache.tags.tagsinuse 24.742100 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 31558 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 1088.206897 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 24.742100 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.048324 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.048324 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::cpu1.data 37722 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 37722 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 25226 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 25226 # number of WriteReq hits +system.cpu1.dcache.SwapReq_hits::cpu1.data 16 # number of SwapReq hits +system.cpu1.dcache.SwapReq_hits::total 16 # number of SwapReq hits +system.cpu1.dcache.demand_hits::cpu1.data 62948 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 62948 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 62948 # number of overall hits +system.cpu1.dcache.overall_hits::total 62948 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 319 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 319 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 132 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 132 # number of WriteReq misses +system.cpu1.dcache.SwapReq_misses::cpu1.data 60 # number of SwapReq misses +system.cpu1.dcache.SwapReq_misses::total 60 # number of SwapReq misses +system.cpu1.dcache.demand_misses::cpu1.data 451 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 451 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 451 # number of overall misses +system.cpu1.dcache.overall_misses::total 451 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 3919891 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 3919891 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2617261 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 2617261 # number of WriteReq miss cycles +system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 548504 # number of SwapReq miss cycles +system.cpu1.dcache.SwapReq_miss_latency::total 548504 # number of SwapReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 6537152 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 6537152 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 6537152 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 6537152 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 38041 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 38041 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 25358 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 25358 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SwapReq_accesses::cpu1.data 76 # number of SwapReq accesses(hits+misses) +system.cpu1.dcache.SwapReq_accesses::total 76 # number of SwapReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 63399 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 63399 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 63399 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 63399 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.008386 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.008386 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.005205 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.005205 # miss rate for WriteReq accesses +system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.789474 # miss rate for SwapReq accesses +system.cpu1.dcache.SwapReq_miss_rate::total 0.789474 # miss rate for SwapReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.007114 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.007114 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.007114 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.007114 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12288.059561 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 12288.059561 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 19827.734848 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 19827.734848 # average WriteReq miss latency +system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 9141.733333 # average SwapReq miss latency +system.cpu1.dcache.SwapReq_avg_miss_latency::total 9141.733333 # average SwapReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 14494.793792 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 14494.793792 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14494.793792 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 14494.793792 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1185,473 +1186,473 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 185 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 185 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 34 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 34 # number of WriteReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 219 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 219 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 219 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 219 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 155 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 155 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 108 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 108 # number of WriteReq MSHR misses -system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 56 # number of SwapReq MSHR misses -system.cpu1.dcache.SwapReq_mshr_misses::total 56 # number of SwapReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 263 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 263 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 263 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 263 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1346027 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1346027 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1452501 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1452501 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 420000 # number of SwapReq MSHR miss cycles -system.cpu1.dcache.SwapReq_mshr_miss_latency::total 420000 # number of SwapReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2798528 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 2798528 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2798528 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 2798528 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.002923 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.002923 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.002390 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.002390 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.835821 # mshr miss rate for SwapReq accesses -system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.835821 # mshr miss rate for SwapReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.002678 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.002678 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.002678 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.002678 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 8684.045161 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 8684.045161 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 13449.083333 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 13449.083333 # average WriteReq mshr miss latency -system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 7500 # average SwapReq mshr miss latency -system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 7500 # average SwapReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 10640.790875 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 10640.790875 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 10640.790875 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 10640.790875 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 154 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 154 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 32 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 32 # number of WriteReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 186 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 186 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 186 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 186 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 165 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 165 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 100 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 100 # number of WriteReq MSHR misses +system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 60 # number of SwapReq MSHR misses +system.cpu1.dcache.SwapReq_mshr_misses::total 60 # number of SwapReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 265 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 265 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 265 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 265 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1138770 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1138770 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1290739 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1290739 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 428496 # number of SwapReq MSHR miss cycles +system.cpu1.dcache.SwapReq_mshr_miss_latency::total 428496 # number of SwapReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2429509 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 2429509 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2429509 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 2429509 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.004337 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.004337 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.003944 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.003944 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.789474 # mshr miss rate for SwapReq accesses +system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.789474 # mshr miss rate for SwapReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.004180 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.004180 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.004180 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.004180 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 6901.636364 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 6901.636364 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 12907.390000 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 12907.390000 # average WriteReq mshr miss latency +system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 7141.600000 # average SwapReq mshr miss latency +system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 7141.600000 # average SwapReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 9167.958491 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 9167.958491 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 9167.958491 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 9167.958491 # average overall mshr miss latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.branchPred.lookups 40256 # Number of BP lookups -system.cpu2.branchPred.condPredicted 37554 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 1244 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 34216 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 33404 # Number of BTB hits +system.cpu2.branchPred.lookups 51236 # Number of BP lookups +system.cpu2.branchPred.condPredicted 48519 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 1308 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 45052 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 44357 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 97.626841 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 656 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.BTBHitPct 98.457338 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 684 # Number of times the RAS was used to get a target. system.cpu2.branchPred.RASInCorrect 232 # Number of incorrect RAS predictions. -system.cpu2.numCycles 176505 # number of cpu cycles simulated +system.cpu2.numCycles 177316 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 35945 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 212693 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 40256 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 34060 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 82824 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 3666 # Number of cycles fetch has spent squashing -system.cpu2.fetch.BlockedCycles 45362 # Number of cycles fetch has spent blocked -system.cpu2.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu2.fetch.NoActiveThreadStallCycles 7326 # Number of stall cycles due to no active thread to fetch from -system.cpu2.fetch.PendingTrapStallCycles 778 # Number of stall cycles due to pending traps -system.cpu2.fetch.CacheLines 27473 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 251 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.rateDist::samples 174585 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.218278 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 1.916616 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.icacheStallCycles 28846 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 286216 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 51236 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 45041 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 100902 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 3805 # Number of cycles fetch has spent squashing +system.cpu2.fetch.BlockedCycles 31210 # Number of cycles fetch has spent blocked +system.cpu2.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu2.fetch.NoActiveThreadStallCycles 7739 # Number of stall cycles due to no active thread to fetch from +system.cpu2.fetch.PendingTrapStallCycles 775 # Number of stall cycles due to pending traps +system.cpu2.fetch.CacheLines 19767 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 276 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.rateDist::samples 171898 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.665034 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 2.139289 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 91761 52.56% 52.56% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 44191 25.31% 77.87% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 10007 5.73% 83.60% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 3161 1.81% 85.41% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 734 0.42% 85.83% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 19642 11.25% 97.09% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 1038 0.59% 97.68% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 777 0.45% 98.12% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 3274 1.88% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 70996 41.30% 41.30% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 51338 29.87% 71.17% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 6125 3.56% 74.73% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 3190 1.86% 76.59% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 695 0.40% 76.99% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 34353 19.98% 96.97% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 1162 0.68% 97.65% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 771 0.45% 98.10% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 3268 1.90% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 174585 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.228073 # Number of branch fetches per cycle -system.cpu2.fetch.rate 1.205025 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 44684 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 38236 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 73287 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 8707 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 2345 # Number of cycles decode is squashing -system.cpu2.decode.DecodedInsts 209159 # Number of instructions handled by decode -system.cpu2.rename.SquashCycles 2345 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 45347 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 25711 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 11752 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 64880 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 17224 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 207132 # Number of instructions processed by rename -system.cpu2.rename.IQFullEvents 1 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LSQFullEvents 18 # Number of times rename has blocked due to LSQ full -system.cpu2.rename.RenamedOperands 141115 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 375802 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 375802 # Number of integer rename lookups -system.cpu2.rename.CommittedMaps 128666 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 12449 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 1089 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 1217 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 19740 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 53610 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 22854 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 26965 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 17848 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 166370 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 10183 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 172186 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 129 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 10670 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 10572 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 668 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 174585 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 0.986259 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 1.235789 # Number of insts issued each cycle +system.cpu2.fetch.rateDist::total 171898 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.288953 # Number of branch fetches per cycle +system.cpu2.fetch.rate 1.614158 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 33770 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 27924 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 94988 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 5055 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 2422 # Number of cycles decode is squashing +system.cpu2.decode.DecodedInsts 282690 # Number of instructions handled by decode +system.cpu2.rename.SquashCycles 2422 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 34480 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 14885 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 12280 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 90190 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 9902 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 280450 # Number of instructions processed by rename +system.cpu2.rename.IQFullEvents 4 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LSQFullEvents 24 # Number of times rename has blocked due to LSQ full +system.cpu2.rename.RenamedOperands 196553 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 537620 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 537620 # Number of integer rename lookups +system.cpu2.rename.CommittedMaps 183508 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 13045 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 1112 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 1237 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 12513 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 79191 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 37564 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 37796 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 32512 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 232563 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 6341 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 234561 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 83 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 11040 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 10888 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 602 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 171898 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 1.364536 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 1.313534 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 89355 51.18% 51.18% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 33684 19.29% 70.48% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 23026 13.19% 83.66% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 23727 13.59% 97.25% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 3246 1.86% 99.11% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 1164 0.67% 99.78% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 273 0.16% 99.94% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 53 0.03% 99.97% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 68441 39.81% 39.81% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 22472 13.07% 52.89% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 37788 21.98% 74.87% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 38389 22.33% 97.20% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 3254 1.89% 99.10% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 1164 0.68% 99.77% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 277 0.16% 99.93% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 56 0.03% 99.97% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::8 57 0.03% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 174585 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 171898 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 12 4.35% 4.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 0 0.00% 4.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 0 0.00% 4.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 4.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 4.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 4.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 4.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 4.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 4.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 4.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 4.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 4.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 4.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 4.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 4.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 4.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 4.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 4.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 4.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 4.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 4.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 4.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 4.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 4.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 4.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 4.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 4.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 4.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 54 19.57% 23.91% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 210 76.09% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 17 6.14% 6.14% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 0 0.00% 6.14% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 0 0.00% 6.14% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 6.14% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 6.14% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 6.14% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 6.14% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 6.14% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 6.14% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 6.14% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 6.14% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 6.14% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 6.14% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 6.14% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 6.14% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 6.14% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 6.14% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 6.14% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 6.14% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 6.14% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 6.14% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 6.14% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 6.14% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 6.14% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 6.14% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 6.14% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 6.14% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.14% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 6.14% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 50 18.05% 24.19% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 210 75.81% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 88373 51.32% 51.32% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 0 0.00% 51.32% # Type of FU issued -system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 51.32% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 51.32% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 51.32% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 51.32% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 51.32% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 51.32% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 51.32% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 51.32% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 51.32% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 51.32% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 51.32% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 51.32% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 51.32% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 51.32% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 51.32% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 51.32% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 51.32% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 51.32% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 51.32% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 51.32% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 51.32% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 51.32% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 51.32% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 51.32% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 51.32% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 51.32% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 51.32% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 61586 35.77% 87.09% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 22227 12.91% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 114217 48.69% 48.69% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 0 0.00% 48.69% # Type of FU issued +system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 48.69% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 48.69% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 48.69% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 48.69% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 48.69% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 48.69% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 48.69% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 48.69% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 48.69% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 48.69% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 48.69% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 48.69% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 48.69% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 48.69% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 48.69% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 48.69% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.69% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 48.69% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 48.69% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.69% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 48.69% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 48.69% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 48.69% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.69% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 48.69% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.69% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.69% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 83468 35.58% 84.28% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 36876 15.72% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 172186 # Type of FU issued -system.cpu2.iq.rate 0.975530 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 276 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.001603 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 519362 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 187269 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 170462 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.FU_type_0::total 234561 # Type of FU issued +system.cpu2.iq.rate 1.322842 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 277 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.001181 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 641380 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 249989 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 232740 # Number of integer instruction queue wakeup accesses system.cpu2.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu2.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu2.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 172462 # Number of integer alu accesses +system.cpu2.iq.int_alu_accesses 234838 # Number of integer alu accesses system.cpu2.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 17592 # Number of loads that had data forwarded from stores +system.cpu2.iew.lsq.thread0.forwLoads 32248 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 2439 # Number of loads squashed +system.cpu2.iew.lsq.thread0.squashedLoads 2484 # Number of loads squashed system.cpu2.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 46 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 1401 # Number of stores squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 45 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 1465 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu2.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu2.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 2345 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 684 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 40 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 204373 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 344 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 53610 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 22854 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 1055 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 40 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewSquashCycles 2422 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 851 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 46 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 277610 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 365 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 79191 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 37564 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 1068 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 46 # Number of times the IQ has become full, causing a stall system.cpu2.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 46 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 451 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 900 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 1351 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 171090 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 52536 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 1096 # Number of squashed instructions skipped in execute +system.cpu2.iew.memOrderViolationEvents 45 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 466 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 970 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 1436 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 233403 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 78158 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 1158 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed -system.cpu2.iew.exec_nop 27820 # number of nop insts executed -system.cpu2.iew.exec_refs 74679 # number of memory reference insts executed -system.cpu2.iew.exec_branches 36982 # Number of branches executed -system.cpu2.iew.exec_stores 22143 # Number of stores executed -system.cpu2.iew.exec_rate 0.969321 # Inst execution rate -system.cpu2.iew.wb_sent 170734 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 170462 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 91387 # num instructions producing a value -system.cpu2.iew.wb_consumers 96059 # num instructions consuming a value +system.cpu2.iew.exec_nop 38706 # number of nop insts executed +system.cpu2.iew.exec_refs 114950 # number of memory reference insts executed +system.cpu2.iew.exec_branches 47927 # Number of branches executed +system.cpu2.iew.exec_stores 36792 # Number of stores executed +system.cpu2.iew.exec_rate 1.316311 # Inst execution rate +system.cpu2.iew.wb_sent 233070 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 232740 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 131730 # num instructions producing a value +system.cpu2.iew.wb_consumers 136434 # num instructions consuming a value system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_rate 0.965763 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.951363 # average fanout of values written-back +system.cpu2.iew.wb_rate 1.312572 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.965522 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.commit.commitSquashedInsts 12267 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 9515 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 1244 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 164914 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 1.164777 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 1.788510 # Number of insts commited each cycle +system.cpu2.commit.commitSquashedInsts 12692 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 5739 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 1308 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 161737 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 1.637943 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 2.020354 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 91274 55.35% 55.35% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 35097 21.28% 76.63% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 6075 3.68% 80.31% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 10441 6.33% 86.64% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 1560 0.95% 87.59% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 18154 11.01% 98.60% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 495 0.30% 98.90% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 1006 0.61% 99.51% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 812 0.49% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 66243 40.96% 40.96% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 46082 28.49% 69.45% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 6100 3.77% 73.22% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 6659 4.12% 77.34% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 1556 0.96% 78.30% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 32794 20.28% 98.58% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 480 0.30% 98.87% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 1001 0.62% 99.49% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 822 0.51% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 164914 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 192088 # Number of instructions committed -system.cpu2.commit.committedOps 192088 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 161737 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 264916 # Number of instructions committed +system.cpu2.commit.committedOps 264916 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 72624 # Number of memory references committed -system.cpu2.commit.loads 51171 # Number of loads committed -system.cpu2.commit.membars 8798 # Number of memory barriers committed -system.cpu2.commit.branches 36206 # Number of branches committed +system.cpu2.commit.refs 112806 # Number of memory references committed +system.cpu2.commit.loads 76707 # Number of loads committed +system.cpu2.commit.membars 5024 # Number of memory barriers committed +system.cpu2.commit.branches 47088 # Number of branches committed system.cpu2.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 130952 # Number of committed integer instructions. +system.cpu2.commit.int_insts 182014 # Number of committed integer instructions. system.cpu2.commit.function_calls 322 # Number of function calls committed. -system.cpu2.commit.bw_lim_events 812 # number cycles where commit BW limit reached +system.cpu2.commit.bw_lim_events 822 # number cycles where commit BW limit reached system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu2.rob.rob_reads 367870 # The number of ROB reads -system.cpu2.rob.rob_writes 411061 # The number of ROB writes -system.cpu2.timesIdled 219 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 1920 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 44183 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 156297 # Number of Instructions Simulated -system.cpu2.committedOps 156297 # Number of Ops (including micro ops) Simulated -system.cpu2.committedInsts_total 156297 # Number of Instructions Simulated -system.cpu2.cpi 1.129292 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 1.129292 # CPI: Total CPI of All Threads -system.cpu2.ipc 0.885510 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 0.885510 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 282509 # number of integer regfile reads -system.cpu2.int_regfile_writes 133289 # number of integer regfile writes +system.cpu2.rob.rob_reads 437936 # The number of ROB reads +system.cpu2.rob.rob_writes 557643 # The number of ROB writes +system.cpu2.timesIdled 224 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 5418 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 44292 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 222015 # Number of Instructions Simulated +system.cpu2.committedOps 222015 # Number of Ops (including micro ops) Simulated +system.cpu2.committedInsts_total 222015 # Number of Instructions Simulated +system.cpu2.cpi 0.798667 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 0.798667 # CPI: Total CPI of All Threads +system.cpu2.ipc 1.252087 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 1.252087 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 403571 # number of integer regfile reads +system.cpu2.int_regfile_writes 188531 # number of integer regfile writes system.cpu2.fp_regfile_writes 64 # number of floating regfile writes -system.cpu2.misc_regfile_reads 76201 # number of misc regfile reads +system.cpu2.misc_regfile_reads 116514 # number of misc regfile reads system.cpu2.misc_regfile_writes 648 # number of misc regfile writes -system.cpu2.icache.replacements 318 # number of replacements -system.cpu2.icache.tagsinuse 76.657940 # Cycle average of tags in use -system.cpu2.icache.total_refs 26999 # Total number of references to valid blocks. -system.cpu2.icache.sampled_refs 428 # Sample count of references to valid blocks. -system.cpu2.icache.avg_refs 63.081776 # Average number of references to valid blocks. -system.cpu2.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.icache.occ_blocks::cpu2.inst 76.657940 # Average occupied blocks per requestor -system.cpu2.icache.occ_percent::cpu2.inst 0.149723 # Average percentage of cache occupancy -system.cpu2.icache.occ_percent::total 0.149723 # Average percentage of cache occupancy -system.cpu2.icache.ReadReq_hits::cpu2.inst 26999 # number of ReadReq hits -system.cpu2.icache.ReadReq_hits::total 26999 # number of ReadReq hits -system.cpu2.icache.demand_hits::cpu2.inst 26999 # number of demand (read+write) hits -system.cpu2.icache.demand_hits::total 26999 # number of demand (read+write) hits -system.cpu2.icache.overall_hits::cpu2.inst 26999 # number of overall hits -system.cpu2.icache.overall_hits::total 26999 # number of overall hits -system.cpu2.icache.ReadReq_misses::cpu2.inst 474 # number of ReadReq misses -system.cpu2.icache.ReadReq_misses::total 474 # number of ReadReq misses -system.cpu2.icache.demand_misses::cpu2.inst 474 # number of demand (read+write) misses -system.cpu2.icache.demand_misses::total 474 # number of demand (read+write) misses -system.cpu2.icache.overall_misses::cpu2.inst 474 # number of overall misses -system.cpu2.icache.overall_misses::total 474 # number of overall misses -system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 6632500 # number of ReadReq miss cycles -system.cpu2.icache.ReadReq_miss_latency::total 6632500 # number of ReadReq miss cycles -system.cpu2.icache.demand_miss_latency::cpu2.inst 6632500 # number of demand (read+write) miss cycles -system.cpu2.icache.demand_miss_latency::total 6632500 # number of demand (read+write) miss cycles -system.cpu2.icache.overall_miss_latency::cpu2.inst 6632500 # number of overall miss cycles -system.cpu2.icache.overall_miss_latency::total 6632500 # number of overall miss cycles -system.cpu2.icache.ReadReq_accesses::cpu2.inst 27473 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.ReadReq_accesses::total 27473 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.demand_accesses::cpu2.inst 27473 # number of demand (read+write) accesses -system.cpu2.icache.demand_accesses::total 27473 # number of demand (read+write) accesses -system.cpu2.icache.overall_accesses::cpu2.inst 27473 # number of overall (read+write) accesses -system.cpu2.icache.overall_accesses::total 27473 # number of overall (read+write) accesses -system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.017253 # miss rate for ReadReq accesses -system.cpu2.icache.ReadReq_miss_rate::total 0.017253 # miss rate for ReadReq accesses -system.cpu2.icache.demand_miss_rate::cpu2.inst 0.017253 # miss rate for demand accesses -system.cpu2.icache.demand_miss_rate::total 0.017253 # miss rate for demand accesses -system.cpu2.icache.overall_miss_rate::cpu2.inst 0.017253 # miss rate for overall accesses -system.cpu2.icache.overall_miss_rate::total 0.017253 # miss rate for overall accesses -system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 13992.616034 # average ReadReq miss latency -system.cpu2.icache.ReadReq_avg_miss_latency::total 13992.616034 # average ReadReq miss latency -system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 13992.616034 # average overall miss latency -system.cpu2.icache.demand_avg_miss_latency::total 13992.616034 # average overall miss latency -system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 13992.616034 # average overall miss latency -system.cpu2.icache.overall_avg_miss_latency::total 13992.616034 # average overall miss latency -system.cpu2.icache.blocked_cycles::no_mshrs 26 # number of cycles access was blocked +system.cpu2.icache.tags.replacements 317 # number of replacements +system.cpu2.icache.tags.tagsinuse 82.351710 # Cycle average of tags in use +system.cpu2.icache.tags.total_refs 19274 # Total number of references to valid blocks. +system.cpu2.icache.tags.sampled_refs 425 # Sample count of references to valid blocks. +system.cpu2.icache.tags.avg_refs 45.350588 # Average number of references to valid blocks. +system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu2.icache.tags.occ_blocks::cpu2.inst 82.351710 # Average occupied blocks per requestor +system.cpu2.icache.tags.occ_percent::cpu2.inst 0.160843 # Average percentage of cache occupancy +system.cpu2.icache.tags.occ_percent::total 0.160843 # Average percentage of cache occupancy +system.cpu2.icache.ReadReq_hits::cpu2.inst 19274 # number of ReadReq hits +system.cpu2.icache.ReadReq_hits::total 19274 # number of ReadReq hits +system.cpu2.icache.demand_hits::cpu2.inst 19274 # number of demand (read+write) hits +system.cpu2.icache.demand_hits::total 19274 # number of demand (read+write) hits +system.cpu2.icache.overall_hits::cpu2.inst 19274 # number of overall hits +system.cpu2.icache.overall_hits::total 19274 # number of overall hits +system.cpu2.icache.ReadReq_misses::cpu2.inst 493 # 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miss rate for WriteReq accesses +system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.826087 # miss rate for SwapReq accesses +system.cpu2.dcache.SwapReq_miss_rate::total 0.826087 # miss rate for SwapReq accesses +system.cpu2.dcache.demand_miss_rate::cpu2.data 0.005945 # miss rate for demand accesses +system.cpu2.dcache.demand_miss_rate::total 0.005945 # miss rate for demand accesses +system.cpu2.dcache.overall_miss_rate::cpu2.data 0.005945 # miss rate for overall accesses +system.cpu2.dcache.overall_miss_rate::total 0.005945 # miss rate for overall accesses +system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 16278.494186 # average ReadReq miss latency +system.cpu2.dcache.ReadReq_avg_miss_latency::total 16278.494186 # average ReadReq miss latency +system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 21715.104895 # average WriteReq miss latency +system.cpu2.dcache.WriteReq_avg_miss_latency::total 21715.104895 # average WriteReq miss latency +system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 10087.842105 # average SwapReq miss latency +system.cpu2.dcache.SwapReq_avg_miss_latency::total 10087.842105 # average SwapReq miss latency +system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 17874.870637 # average overall miss latency +system.cpu2.dcache.demand_avg_miss_latency::total 17874.870637 # average overall miss latency +system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 17874.870637 # average overall miss latency +system.cpu2.dcache.overall_avg_miss_latency::total 17874.870637 # average overall miss latency system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1660,365 +1661,365 @@ system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu2.dcache.fast_writes 0 # number of fast writes performed system.cpu2.dcache.cache_copies 0 # number of cache copies performed -system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data 156 # number of ReadReq MSHR hits -system.cpu2.dcache.ReadReq_mshr_hits::total 156 # number of ReadReq MSHR hits -system.cpu2.dcache.WriteReq_mshr_hits::cpu2.data 33 # number of WriteReq MSHR hits -system.cpu2.dcache.WriteReq_mshr_hits::total 33 # number of WriteReq MSHR hits -system.cpu2.dcache.demand_mshr_hits::cpu2.data 189 # number of demand (read+write) MSHR hits -system.cpu2.dcache.demand_mshr_hits::total 189 # number of demand (read+write) MSHR hits -system.cpu2.dcache.overall_mshr_hits::cpu2.data 189 # number of overall MSHR hits -system.cpu2.dcache.overall_mshr_hits::total 189 # number of overall MSHR hits -system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 161 # number of ReadReq MSHR misses -system.cpu2.dcache.ReadReq_mshr_misses::total 161 # number of ReadReq MSHR misses -system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 101 # number of WriteReq MSHR misses -system.cpu2.dcache.WriteReq_mshr_misses::total 101 # number of WriteReq MSHR misses -system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 54 # number of SwapReq MSHR misses -system.cpu2.dcache.SwapReq_mshr_misses::total 54 # number of SwapReq MSHR misses -system.cpu2.dcache.demand_mshr_misses::cpu2.data 262 # number of demand (read+write) MSHR misses -system.cpu2.dcache.demand_mshr_misses::total 262 # number of demand (read+write) MSHR misses -system.cpu2.dcache.overall_mshr_misses::cpu2.data 262 # number of overall MSHR misses -system.cpu2.dcache.overall_mshr_misses::total 262 # number of overall MSHR misses -system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 1142519 # number of ReadReq MSHR miss cycles -system.cpu2.dcache.ReadReq_mshr_miss_latency::total 1142519 # number of ReadReq MSHR miss cycles -system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1333500 # number of WriteReq MSHR miss cycles -system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1333500 # number of WriteReq MSHR miss cycles -system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 425000 # number of SwapReq MSHR miss cycles -system.cpu2.dcache.SwapReq_mshr_miss_latency::total 425000 # number of SwapReq MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 2476019 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_latency::total 2476019 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 2476019 # number of overall MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_latency::total 2476019 # number of overall MSHR miss cycles -system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.004609 # mshr miss rate for ReadReq accesses -system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.004609 # mshr miss rate for ReadReq accesses -system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.004724 # mshr miss rate for WriteReq accesses -system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.004724 # mshr miss rate for WriteReq accesses -system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.760563 # mshr miss rate for SwapReq accesses -system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.760563 # mshr miss rate for SwapReq accesses -system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.004653 # mshr miss rate for demand accesses -system.cpu2.dcache.demand_mshr_miss_rate::total 0.004653 # mshr miss rate for demand accesses -system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.004653 # mshr miss rate for overall accesses -system.cpu2.dcache.overall_mshr_miss_rate::total 0.004653 # mshr miss rate for overall accesses -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 7096.391304 # average ReadReq mshr miss latency -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 7096.391304 # average ReadReq mshr miss latency -system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 13202.970297 # average WriteReq mshr miss latency -system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 13202.970297 # average WriteReq mshr miss latency -system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 7870.370370 # average SwapReq mshr miss latency -system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 7870.370370 # average SwapReq mshr miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 9450.454198 # average overall mshr miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency::total 9450.454198 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 9450.454198 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency::total 9450.454198 # average overall mshr miss latency +system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data 182 # number of ReadReq MSHR hits +system.cpu2.dcache.ReadReq_mshr_hits::total 182 # number of ReadReq MSHR hits +system.cpu2.dcache.WriteReq_mshr_hits::cpu2.data 34 # number of WriteReq MSHR hits +system.cpu2.dcache.WriteReq_mshr_hits::total 34 # number of WriteReq MSHR hits +system.cpu2.dcache.demand_mshr_hits::cpu2.data 216 # number of demand (read+write) MSHR hits +system.cpu2.dcache.demand_mshr_hits::total 216 # number of demand (read+write) MSHR hits +system.cpu2.dcache.overall_mshr_hits::cpu2.data 216 # number of overall MSHR hits +system.cpu2.dcache.overall_mshr_hits::total 216 # number of overall MSHR hits +system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 162 # number of ReadReq MSHR misses +system.cpu2.dcache.ReadReq_mshr_misses::total 162 # number of ReadReq MSHR misses +system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 109 # number of WriteReq MSHR misses +system.cpu2.dcache.WriteReq_mshr_misses::total 109 # number of WriteReq MSHR misses +system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 57 # number of SwapReq MSHR misses +system.cpu2.dcache.SwapReq_mshr_misses::total 57 # number of SwapReq MSHR misses +system.cpu2.dcache.demand_mshr_misses::cpu2.data 271 # number of demand (read+write) MSHR misses +system.cpu2.dcache.demand_mshr_misses::total 271 # number of demand (read+write) MSHR misses +system.cpu2.dcache.overall_mshr_misses::cpu2.data 271 # number of overall MSHR misses +system.cpu2.dcache.overall_mshr_misses::total 271 # number of overall MSHR misses +system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 1526780 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_latency::total 1526780 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1514240 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1514240 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 460993 # number of SwapReq MSHR miss cycles +system.cpu2.dcache.SwapReq_mshr_miss_latency::total 460993 # number of SwapReq MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 3041020 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_latency::total 3041020 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 3041020 # number of overall MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_latency::total 3041020 # number of overall MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003530 # mshr miss rate for ReadReq accesses +system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003530 # mshr miss rate for ReadReq accesses +system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.003025 # mshr miss rate for WriteReq accesses +system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.003025 # mshr miss rate for WriteReq accesses +system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.826087 # mshr miss rate for SwapReq accesses +system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.826087 # mshr miss rate for SwapReq accesses +system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.003308 # mshr miss rate for demand accesses +system.cpu2.dcache.demand_mshr_miss_rate::total 0.003308 # mshr miss rate for demand accesses +system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.003308 # mshr miss rate for overall accesses +system.cpu2.dcache.overall_mshr_miss_rate::total 0.003308 # mshr miss rate for overall accesses +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 9424.567901 # average ReadReq mshr miss latency +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 9424.567901 # average ReadReq mshr miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 13892.110092 # average WriteReq mshr miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 13892.110092 # average WriteReq mshr miss latency +system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 8087.596491 # average SwapReq mshr miss latency +system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 8087.596491 # average SwapReq mshr miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 11221.476015 # average overall mshr miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency::total 11221.476015 # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 11221.476015 # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency::total 11221.476015 # average overall mshr miss latency system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.branchPred.lookups 52069 # Number of BP lookups -system.cpu3.branchPred.condPredicted 49356 # Number of conditional branches predicted -system.cpu3.branchPred.condIncorrect 1283 # Number of conditional branches incorrect -system.cpu3.branchPred.BTBLookups 46005 # Number of BTB lookups -system.cpu3.branchPred.BTBHits 45233 # Number of BTB hits +system.cpu3.branchPred.lookups 56317 # Number of BP lookups +system.cpu3.branchPred.condPredicted 53592 # Number of conditional branches predicted +system.cpu3.branchPred.condIncorrect 1257 # Number of conditional branches incorrect +system.cpu3.branchPred.BTBLookups 50318 # Number of BTB lookups +system.cpu3.branchPred.BTBHits 49441 # Number of BTB hits system.cpu3.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu3.branchPred.BTBHitPct 98.321922 # BTB Hit Percentage -system.cpu3.branchPred.usedRAS 642 # Number of times the RAS was used to get a target. +system.cpu3.branchPred.BTBHitPct 98.257085 # BTB Hit Percentage +system.cpu3.branchPred.usedRAS 649 # Number of times the RAS was used to get a target. system.cpu3.branchPred.RASInCorrect 232 # Number of incorrect RAS predictions. -system.cpu3.numCycles 176161 # number of cpu cycles simulated +system.cpu3.numCycles 176970 # number of cpu cycles simulated system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu3.fetch.icacheStallCycles 28821 # Number of cycles fetch is stalled on an Icache miss -system.cpu3.fetch.Insts 290359 # Number of instructions fetch has processed -system.cpu3.fetch.Branches 52069 # Number of branches that fetch encountered -system.cpu3.fetch.predictedBranches 45875 # Number of branches that fetch has predicted taken -system.cpu3.fetch.Cycles 102938 # Number of cycles fetch has run and was not squashing or blocked -system.cpu3.fetch.SquashCycles 3745 # Number of cycles fetch has spent squashing -system.cpu3.fetch.BlockedCycles 32453 # Number of cycles fetch has spent blocked +system.cpu3.fetch.icacheStallCycles 26467 # Number of cycles fetch is stalled on an Icache miss +system.cpu3.fetch.Insts 318235 # Number of instructions fetch has processed +system.cpu3.fetch.Branches 56317 # Number of branches that fetch encountered +system.cpu3.fetch.predictedBranches 50090 # Number of branches that fetch has predicted taken +system.cpu3.fetch.Cycles 110248 # Number of cycles fetch has run and was not squashing or blocked +system.cpu3.fetch.SquashCycles 3629 # Number of cycles fetch has spent squashing +system.cpu3.fetch.BlockedCycles 28039 # Number of cycles fetch has spent blocked system.cpu3.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu3.fetch.NoActiveThreadStallCycles 7327 # Number of stall cycles due to no active thread to fetch from -system.cpu3.fetch.PendingTrapStallCycles 785 # Number of stall cycles due to pending traps -system.cpu3.fetch.CacheLines 20536 # Number of cache lines fetched -system.cpu3.fetch.IcacheSquashes 262 # Number of outstanding Icache misses that were squashed -system.cpu3.fetch.rateDist::samples 174715 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::mean 1.661901 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::stdev 2.131946 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.NoActiveThreadStallCycles 7739 # Number of stall cycles due to no active thread to fetch from +system.cpu3.fetch.PendingTrapStallCycles 790 # Number of stall cycles due to pending traps +system.cpu3.fetch.CacheLines 18199 # Number of cache lines fetched +system.cpu3.fetch.IcacheSquashes 258 # Number of outstanding Icache misses that were squashed +system.cpu3.fetch.rateDist::samples 175582 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::mean 1.812458 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::stdev 2.180606 # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::0 71777 41.08% 41.08% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::1 52540 30.07% 71.15% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::2 6531 3.74% 74.89% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::3 3210 1.84% 76.73% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::4 677 0.39% 77.12% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::5 34730 19.88% 97.00% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::6 1243 0.71% 97.71% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::7 745 0.43% 98.13% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::8 3262 1.87% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::0 65334 37.21% 37.21% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::1 55610 31.67% 68.88% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::2 5389 3.07% 71.95% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::3 3177 1.81% 73.76% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::4 669 0.38% 74.14% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::5 40119 22.85% 96.99% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::6 1237 0.70% 97.70% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::7 753 0.43% 98.12% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::8 3294 1.88% 100.00% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::total 174715 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.branchRate 0.295576 # Number of branch fetches per cycle -system.cpu3.fetch.rate 1.648259 # Number of inst fetches per cycle -system.cpu3.decode.IdleCycles 34404 # Number of cycles decode is idle -system.cpu3.decode.BlockedCycles 28518 # Number of cycles decode is blocked -system.cpu3.decode.RunCycles 96588 # Number of cycles decode is running -system.cpu3.decode.UnblockCycles 5492 # Number of cycles decode is unblocking -system.cpu3.decode.SquashCycles 2386 # Number of cycles decode is squashing -system.cpu3.decode.DecodedInsts 286754 # Number of instructions handled by decode -system.cpu3.rename.SquashCycles 2386 # Number of cycles rename is squashing -system.cpu3.rename.IdleCycles 35116 # Number of cycles rename is idle -system.cpu3.rename.BlockCycles 15951 # Number of cycles rename is blocking -system.cpu3.rename.serializeStallCycles 11812 # count of cycles rename stalled for serializing inst -system.cpu3.rename.RunCycles 91334 # Number of cycles rename is running -system.cpu3.rename.UnblockCycles 10789 # Number of cycles rename is unblocking -system.cpu3.rename.RenamedInsts 284513 # Number of instructions processed by rename -system.cpu3.rename.IQFullEvents 8 # Number of times rename has blocked due to IQ full +system.cpu3.fetch.rateDist::total 175582 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.branchRate 0.318229 # Number of branch fetches per cycle +system.cpu3.fetch.rate 1.798243 # Number of inst fetches per cycle +system.cpu3.decode.IdleCycles 31057 # Number of cycles decode is idle +system.cpu3.decode.BlockedCycles 25106 # Number of cycles decode is blocked +system.cpu3.decode.RunCycles 104911 # Number of cycles decode is running +system.cpu3.decode.UnblockCycles 4475 # Number of cycles decode is unblocking +system.cpu3.decode.SquashCycles 2294 # Number of cycles decode is squashing +system.cpu3.decode.DecodedInsts 314540 # Number of instructions handled by decode +system.cpu3.rename.SquashCycles 2294 # Number of cycles rename is squashing +system.cpu3.rename.IdleCycles 31713 # Number of cycles rename is idle +system.cpu3.rename.BlockCycles 12844 # Number of cycles rename is blocking +system.cpu3.rename.serializeStallCycles 11527 # count of cycles rename stalled for serializing inst +system.cpu3.rename.RunCycles 100723 # Number of cycles rename is running +system.cpu3.rename.UnblockCycles 8742 # Number of cycles rename is unblocking +system.cpu3.rename.RenamedInsts 312369 # Number of instructions processed by rename +system.cpu3.rename.IQFullEvents 1 # Number of times rename has blocked due to IQ full system.cpu3.rename.LSQFullEvents 22 # Number of times rename has blocked due to LSQ full -system.cpu3.rename.RenamedOperands 198512 # Number of destination operands rename has renamed -system.cpu3.rename.RenameLookups 543834 # Number of register rename lookups that rename has made -system.cpu3.rename.int_rename_lookups 543834 # Number of integer rename lookups -system.cpu3.rename.CommittedMaps 185460 # Number of HB maps that are committed -system.cpu3.rename.UndoneMaps 13052 # Number of HB maps that are undone due to squashing -system.cpu3.rename.serializingInsts 1098 # count of serializing insts renamed -system.cpu3.rename.tempSerializingInsts 1218 # count of temporary serializing insts renamed -system.cpu3.rename.skidInsts 13448 # count of insts added to the skid buffer -system.cpu3.memDep0.insertedLoads 80352 # Number of loads inserted to the mem dependence unit. -system.cpu3.memDep0.insertedStores 37945 # Number of stores inserted to the mem dependence unit. -system.cpu3.memDep0.conflictingLoads 38583 # Number of conflicting loads. -system.cpu3.memDep0.conflictingStores 32886 # Number of conflicting stores. -system.cpu3.iq.iqInstsAdded 235223 # Number of instructions added to the IQ (excludes non-spec) -system.cpu3.iq.iqNonSpecInstsAdded 6760 # Number of non-speculative instructions added to the IQ -system.cpu3.iq.iqInstsIssued 237671 # Number of instructions issued -system.cpu3.iq.iqSquashedInstsIssued 118 # Number of squashed instructions issued -system.cpu3.iq.iqSquashedInstsExamined 10910 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu3.iq.iqSquashedOperandsExamined 10900 # Number of squashed operands that are examined and possibly removed from graph -system.cpu3.iq.iqSquashedNonSpecRemoved 576 # Number of squashed non-spec instructions that were removed -system.cpu3.iq.issued_per_cycle::samples 174715 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::mean 1.360335 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::stdev 1.308190 # Number of insts issued each cycle +system.cpu3.rename.RenamedOperands 219058 # Number of destination operands rename has renamed +system.cpu3.rename.RenameLookups 604346 # Number of register rename lookups that rename has made +system.cpu3.rename.int_rename_lookups 604346 # Number of integer rename lookups +system.cpu3.rename.CommittedMaps 206290 # Number of HB maps that are committed +system.cpu3.rename.UndoneMaps 12768 # Number of HB maps that are undone due to squashing +system.cpu3.rename.serializingInsts 1082 # count of serializing insts renamed +system.cpu3.rename.tempSerializingInsts 1202 # count of temporary serializing insts renamed +system.cpu3.rename.skidInsts 11332 # count of insts added to the skid buffer +system.cpu3.memDep0.insertedLoads 90084 # Number of loads inserted to the mem dependence unit. +system.cpu3.memDep0.insertedStores 43367 # Number of stores inserted to the mem dependence unit. +system.cpu3.memDep0.conflictingLoads 42837 # Number of conflicting loads. +system.cpu3.memDep0.conflictingStores 38342 # Number of conflicting stores. +system.cpu3.iq.iqInstsAdded 260031 # Number of instructions added to the IQ (excludes non-spec) +system.cpu3.iq.iqNonSpecInstsAdded 5573 # Number of non-speculative instructions added to the IQ +system.cpu3.iq.iqInstsIssued 261645 # Number of instructions issued +system.cpu3.iq.iqSquashedInstsIssued 62 # Number of squashed instructions issued +system.cpu3.iq.iqSquashedInstsExamined 10424 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu3.iq.iqSquashedOperandsExamined 10297 # Number of squashed operands that are examined and possibly removed from graph +system.cpu3.iq.iqSquashedNonSpecRemoved 498 # Number of squashed non-spec instructions that were removed +system.cpu3.iq.issued_per_cycle::samples 175582 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::mean 1.490158 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::stdev 1.307816 # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::0 69245 39.63% 39.63% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::1 23718 13.58% 53.21% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::2 38151 21.84% 75.04% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::3 38808 22.21% 97.26% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::4 3275 1.87% 99.13% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::5 1152 0.66% 99.79% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::6 254 0.15% 99.94% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::7 53 0.03% 99.97% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::0 62519 35.61% 35.61% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::1 20435 11.64% 47.25% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::2 43580 24.82% 72.07% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::3 44218 25.18% 97.25% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::4 3288 1.87% 99.12% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::5 1176 0.67% 99.79% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::6 257 0.15% 99.94% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::7 50 0.03% 99.97% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::8 59 0.03% 100.00% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::total 174715 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::total 175582 # Number of insts issued each cycle system.cpu3.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntAlu 17 5.94% 5.94% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntMult 0 0.00% 5.94% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntDiv 0 0.00% 5.94% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatAdd 0 0.00% 5.94% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatCmp 0 0.00% 5.94% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatCvt 0 0.00% 5.94% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatMult 0 0.00% 5.94% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatDiv 0 0.00% 5.94% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 5.94% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAdd 0 0.00% 5.94% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 5.94% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAlu 0 0.00% 5.94% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdCmp 0 0.00% 5.94% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdCvt 0 0.00% 5.94% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMisc 0 0.00% 5.94% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMult 0 0.00% 5.94% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 5.94% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdShift 0 0.00% 5.94% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 5.94% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 5.94% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 5.94% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 5.94% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 5.94% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 5.94% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 5.94% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 5.94% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 5.94% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.94% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 5.94% # attempts to use FU when none available -system.cpu3.iq.fu_full::MemRead 59 20.63% 26.57% # attempts to use FU when none available -system.cpu3.iq.fu_full::MemWrite 210 73.43% 100.00% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntAlu 17 6.25% 6.25% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntMult 0 0.00% 6.25% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntDiv 0 0.00% 6.25% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatAdd 0 0.00% 6.25% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatCmp 0 0.00% 6.25% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatCvt 0 0.00% 6.25% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatMult 0 0.00% 6.25% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatDiv 0 0.00% 6.25% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 6.25% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAdd 0 0.00% 6.25% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 6.25% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAlu 0 0.00% 6.25% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdCmp 0 0.00% 6.25% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdCvt 0 0.00% 6.25% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMisc 0 0.00% 6.25% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMult 0 0.00% 6.25% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 6.25% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdShift 0 0.00% 6.25% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 6.25% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 6.25% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 6.25% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 6.25% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 6.25% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 6.25% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 6.25% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 6.25% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 6.25% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.25% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 6.25% # attempts to use FU when none available +system.cpu3.iq.fu_full::MemRead 45 16.54% 22.79% # attempts to use FU when none available +system.cpu3.iq.fu_full::MemWrite 210 77.21% 100.00% # attempts to use FU when none available system.cpu3.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu3.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu3.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu3.iq.FU_type_0::IntAlu 115348 48.53% 48.53% # Type of FU issued -system.cpu3.iq.FU_type_0::IntMult 0 0.00% 48.53% # Type of FU issued -system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 48.53% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 48.53% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 48.53% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 48.53% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 48.53% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 48.53% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 48.53% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 48.53% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 48.53% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 48.53% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 48.53% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 48.53% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 48.53% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 48.53% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 48.53% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 48.53% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.53% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 48.53% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 48.53% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.53% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 48.53% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 48.53% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 48.53% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.53% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 48.53% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.53% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.53% # Type of FU issued -system.cpu3.iq.FU_type_0::MemRead 85085 35.80% 84.33% # Type of FU issued -system.cpu3.iq.FU_type_0::MemWrite 37238 15.67% 100.00% # Type of FU issued +system.cpu3.iq.FU_type_0::IntAlu 125105 47.81% 47.81% # Type of FU issued +system.cpu3.iq.FU_type_0::IntMult 0 0.00% 47.81% # Type of FU issued +system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 47.81% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 47.81% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 47.81% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 47.81% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 47.81% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 47.81% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 47.81% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 47.81% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 47.81% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 47.81% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 47.81% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 47.81% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 47.81% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 47.81% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 47.81% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 47.81% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 47.81% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 47.81% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.81% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.81% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.81% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.81% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.81% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMisc 0 0.00% 47.81% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 47.81% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.81% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.81% # Type of FU issued +system.cpu3.iq.FU_type_0::MemRead 93850 35.87% 83.68% # Type of FU issued +system.cpu3.iq.FU_type_0::MemWrite 42690 16.32% 100.00% # Type of FU issued system.cpu3.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu3.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu3.iq.FU_type_0::total 237671 # Type of FU issued -system.cpu3.iq.rate 1.349169 # Inst issue rate -system.cpu3.iq.fu_busy_cnt 286 # FU busy when requested -system.cpu3.iq.fu_busy_rate 0.001203 # FU busy rate (busy events/executed inst) -system.cpu3.iq.int_inst_queue_reads 650461 # Number of integer instruction queue reads -system.cpu3.iq.int_inst_queue_writes 252939 # Number of integer instruction queue writes -system.cpu3.iq.int_inst_queue_wakeup_accesses 235820 # Number of integer instruction queue wakeup accesses +system.cpu3.iq.FU_type_0::total 261645 # Type of FU issued +system.cpu3.iq.rate 1.478471 # Inst issue rate +system.cpu3.iq.fu_busy_cnt 272 # FU busy when requested +system.cpu3.iq.fu_busy_rate 0.001040 # FU busy rate (busy events/executed inst) +system.cpu3.iq.int_inst_queue_reads 699206 # Number of integer instruction queue reads +system.cpu3.iq.int_inst_queue_writes 276071 # Number of integer instruction queue writes +system.cpu3.iq.int_inst_queue_wakeup_accesses 259793 # Number of integer instruction queue wakeup accesses system.cpu3.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu3.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu3.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu3.iq.int_alu_accesses 237957 # Number of integer alu accesses +system.cpu3.iq.int_alu_accesses 261917 # Number of integer alu accesses system.cpu3.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu3.iew.lsq.thread0.forwLoads 32638 # Number of loads that had data forwarded from stores +system.cpu3.iew.lsq.thread0.forwLoads 38112 # Number of loads that had data forwarded from stores system.cpu3.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu3.iew.lsq.thread0.squashedLoads 2448 # Number of loads squashed +system.cpu3.iew.lsq.thread0.squashedLoads 2309 # Number of loads squashed system.cpu3.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed -system.cpu3.iew.lsq.thread0.memOrderViolation 46 # Number of memory ordering violations -system.cpu3.iew.lsq.thread0.squashedStores 1468 # Number of stores squashed +system.cpu3.iew.lsq.thread0.memOrderViolation 43 # Number of memory ordering violations +system.cpu3.iew.lsq.thread0.squashedStores 1414 # Number of stores squashed system.cpu3.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu3.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu3.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu3.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu3.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu3.iew.iewSquashCycles 2386 # Number of cycles IEW is squashing -system.cpu3.iew.iewBlockCycles 609 # Number of cycles IEW is blocking -system.cpu3.iew.iewUnblockCycles 39 # Number of cycles IEW is unblocking -system.cpu3.iew.iewDispatchedInsts 281506 # Number of instructions dispatched to IQ -system.cpu3.iew.iewDispSquashedInsts 366 # Number of squashed instructions skipped by dispatch -system.cpu3.iew.iewDispLoadInsts 80352 # Number of dispatched load instructions -system.cpu3.iew.iewDispStoreInsts 37945 # Number of dispatched store instructions -system.cpu3.iew.iewDispNonSpecInsts 1055 # Number of dispatched non-speculative instructions -system.cpu3.iew.iewIQFullEvents 38 # Number of times the IQ has become full, causing a stall +system.cpu3.iew.iewSquashCycles 2294 # Number of cycles IEW is squashing +system.cpu3.iew.iewBlockCycles 580 # Number of cycles IEW is blocking +system.cpu3.iew.iewUnblockCycles 36 # Number of cycles IEW is unblocking +system.cpu3.iew.iewDispatchedInsts 309373 # Number of instructions dispatched to IQ +system.cpu3.iew.iewDispSquashedInsts 369 # Number of squashed instructions skipped by dispatch +system.cpu3.iew.iewDispLoadInsts 90084 # Number of dispatched load instructions +system.cpu3.iew.iewDispStoreInsts 43367 # Number of dispatched store instructions +system.cpu3.iew.iewDispNonSpecInsts 1034 # Number of dispatched non-speculative instructions +system.cpu3.iew.iewIQFullEvents 36 # Number of times the IQ has become full, causing a stall system.cpu3.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu3.iew.memOrderViolationEvents 46 # Number of memory order violations -system.cpu3.iew.predictedTakenIncorrect 470 # Number of branches that were predicted taken incorrectly -system.cpu3.iew.predictedNotTakenIncorrect 925 # Number of branches that were predicted not taken incorrectly -system.cpu3.iew.branchMispredicts 1395 # Number of branch mispredicts detected at execute -system.cpu3.iew.iewExecutedInsts 236476 # Number of executed instructions -system.cpu3.iew.iewExecLoadInsts 79331 # Number of load instructions executed -system.cpu3.iew.iewExecSquashedInsts 1195 # Number of squashed instructions skipped in execute +system.cpu3.iew.memOrderViolationEvents 43 # Number of memory order violations +system.cpu3.iew.predictedTakenIncorrect 465 # Number of branches that were predicted taken incorrectly +system.cpu3.iew.predictedNotTakenIncorrect 904 # Number of branches that were predicted not taken incorrectly +system.cpu3.iew.branchMispredicts 1369 # Number of branch mispredicts detected at execute +system.cpu3.iew.iewExecutedInsts 260458 # Number of executed instructions +system.cpu3.iew.iewExecLoadInsts 89199 # Number of load instructions executed +system.cpu3.iew.iewExecSquashedInsts 1187 # Number of squashed instructions skipped in execute system.cpu3.iew.exec_swp 0 # number of swp insts executed -system.cpu3.iew.exec_nop 39523 # number of nop insts executed -system.cpu3.iew.exec_refs 116486 # number of memory reference insts executed -system.cpu3.iew.exec_branches 48746 # Number of branches executed -system.cpu3.iew.exec_stores 37155 # Number of stores executed -system.cpu3.iew.exec_rate 1.342386 # Inst execution rate -system.cpu3.iew.wb_sent 236114 # cumulative count of insts sent to commit -system.cpu3.iew.wb_count 235820 # cumulative count of insts written-back -system.cpu3.iew.wb_producers 133214 # num instructions producing a value -system.cpu3.iew.wb_consumers 137877 # num instructions consuming a value +system.cpu3.iew.exec_nop 43769 # number of nop insts executed +system.cpu3.iew.exec_refs 131812 # number of memory reference insts executed +system.cpu3.iew.exec_branches 53091 # Number of branches executed +system.cpu3.iew.exec_stores 42613 # Number of stores executed +system.cpu3.iew.exec_rate 1.471764 # Inst execution rate +system.cpu3.iew.wb_sent 260118 # cumulative count of insts sent to commit +system.cpu3.iew.wb_count 259793 # cumulative count of insts written-back +system.cpu3.iew.wb_producers 148532 # num instructions producing a value +system.cpu3.iew.wb_consumers 153197 # num instructions consuming a value system.cpu3.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu3.iew.wb_rate 1.338662 # insts written-back per cycle -system.cpu3.iew.wb_fanout 0.966180 # average fanout of values written-back +system.cpu3.iew.wb_rate 1.468006 # insts written-back per cycle +system.cpu3.iew.wb_fanout 0.969549 # average fanout of values written-back system.cpu3.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu3.commit.commitSquashedInsts 12531 # The number of squashed insts skipped by commit -system.cpu3.commit.commitNonSpecStalls 6184 # The number of times commit has been forced to stall to communicate backwards -system.cpu3.commit.branchMispredicts 1283 # The number of times a branch was mispredicted -system.cpu3.commit.committed_per_cycle::samples 165002 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::mean 1.630011 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::stdev 2.014402 # Number of insts commited each cycle +system.cpu3.commit.commitSquashedInsts 11915 # The number of squashed insts skipped by commit +system.cpu3.commit.commitNonSpecStalls 5075 # The number of times commit has been forced to stall to communicate backwards +system.cpu3.commit.branchMispredicts 1257 # The number of times a branch was mispredicted +system.cpu3.commit.committed_per_cycle::samples 165549 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::mean 1.796677 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::stdev 2.064793 # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::0 67849 41.12% 41.12% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::1 46915 28.43% 69.55% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::2 6084 3.69% 73.24% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::3 7112 4.31% 77.55% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::4 1576 0.96% 78.51% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::5 33196 20.12% 98.62% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::6 454 0.28% 98.90% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::7 1000 0.61% 99.51% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::8 816 0.49% 100.00% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::0 59727 36.08% 36.08% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::1 51190 30.92% 67.00% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::2 6085 3.68% 70.68% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::3 6030 3.64% 74.32% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::4 1572 0.95% 75.27% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::5 38600 23.32% 98.58% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::6 530 0.32% 98.90% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::7 1000 0.60% 99.51% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::8 815 0.49% 100.00% # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::total 165002 # Number of insts commited each cycle -system.cpu3.commit.committedInsts 268955 # Number of instructions committed -system.cpu3.commit.committedOps 268955 # Number of ops (including micro ops) committed +system.cpu3.commit.committed_per_cycle::total 165549 # Number of insts commited each cycle +system.cpu3.commit.committedInsts 297438 # Number of instructions committed +system.cpu3.commit.committedOps 297438 # Number of ops (including micro ops) committed system.cpu3.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu3.commit.refs 114381 # Number of memory references committed -system.cpu3.commit.loads 77904 # Number of loads committed -system.cpu3.commit.membars 5468 # Number of memory barriers committed -system.cpu3.commit.branches 47910 # Number of branches committed +system.cpu3.commit.refs 129728 # Number of memory references committed +system.cpu3.commit.loads 87775 # Number of loads committed +system.cpu3.commit.membars 4366 # Number of memory barriers committed +system.cpu3.commit.branches 52284 # Number of branches committed system.cpu3.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu3.commit.int_insts 184410 # Number of committed integer instructions. +system.cpu3.commit.int_insts 204138 # Number of committed integer instructions. system.cpu3.commit.function_calls 322 # Number of function calls committed. -system.cpu3.commit.bw_lim_events 816 # number cycles where commit BW limit reached +system.cpu3.commit.bw_lim_events 815 # number cycles where commit BW limit reached system.cpu3.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu3.rob.rob_reads 445085 # The number of ROB reads -system.cpu3.rob.rob_writes 565364 # The number of ROB writes -system.cpu3.timesIdled 211 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu3.idleCycles 1446 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu3.quiesceCycles 44527 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu3.committedInsts 224789 # Number of Instructions Simulated -system.cpu3.committedOps 224789 # Number of Ops (including micro ops) Simulated -system.cpu3.committedInsts_total 224789 # Number of Instructions Simulated -system.cpu3.cpi 0.783673 # CPI: Cycles Per Instruction -system.cpu3.cpi_total 0.783673 # CPI: Total CPI of All Threads -system.cpu3.ipc 1.276043 # IPC: Instructions Per Cycle -system.cpu3.ipc_total 1.276043 # IPC: Total IPC of All Threads -system.cpu3.int_regfile_reads 408025 # number of integer regfile reads -system.cpu3.int_regfile_writes 190344 # number of integer regfile writes +system.cpu3.rob.rob_reads 473500 # The number of ROB reads +system.cpu3.rob.rob_writes 621006 # The number of ROB writes +system.cpu3.timesIdled 209 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu3.idleCycles 1388 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu3.quiesceCycles 44638 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu3.committedInsts 249993 # Number of Instructions Simulated +system.cpu3.committedOps 249993 # Number of Ops (including micro ops) Simulated +system.cpu3.committedInsts_total 249993 # Number of Instructions Simulated +system.cpu3.cpi 0.707900 # CPI: Cycles Per Instruction +system.cpu3.cpi_total 0.707900 # CPI: Total CPI of All Threads +system.cpu3.ipc 1.412629 # IPC: Instructions Per Cycle +system.cpu3.ipc_total 1.412629 # IPC: Total IPC of All Threads +system.cpu3.int_regfile_reads 453881 # number of integer regfile reads +system.cpu3.int_regfile_writes 211087 # number of integer regfile writes system.cpu3.fp_regfile_writes 64 # number of floating regfile writes -system.cpu3.misc_regfile_reads 118055 # number of misc regfile reads +system.cpu3.misc_regfile_reads 133368 # number of misc regfile reads system.cpu3.misc_regfile_writes 648 # number of misc regfile writes -system.cpu3.icache.replacements 319 # number of replacements -system.cpu3.icache.tagsinuse 80.505037 # Cycle average of tags in use -system.cpu3.icache.total_refs 20059 # Total number of references to valid blocks. -system.cpu3.icache.sampled_refs 430 # Sample count of references to valid blocks. -system.cpu3.icache.avg_refs 46.648837 # Average number of references to valid blocks. -system.cpu3.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.icache.occ_blocks::cpu3.inst 80.505037 # Average occupied blocks per requestor -system.cpu3.icache.occ_percent::cpu3.inst 0.157236 # Average percentage of cache occupancy -system.cpu3.icache.occ_percent::total 0.157236 # Average percentage of cache occupancy -system.cpu3.icache.ReadReq_hits::cpu3.inst 20059 # number of ReadReq hits -system.cpu3.icache.ReadReq_hits::total 20059 # number of ReadReq hits -system.cpu3.icache.demand_hits::cpu3.inst 20059 # number of demand (read+write) hits -system.cpu3.icache.demand_hits::total 20059 # number of demand (read+write) hits -system.cpu3.icache.overall_hits::cpu3.inst 20059 # number of overall hits -system.cpu3.icache.overall_hits::total 20059 # number of overall hits -system.cpu3.icache.ReadReq_misses::cpu3.inst 477 # number of ReadReq misses -system.cpu3.icache.ReadReq_misses::total 477 # number of ReadReq misses -system.cpu3.icache.demand_misses::cpu3.inst 477 # number of demand (read+write) misses -system.cpu3.icache.demand_misses::total 477 # number of demand (read+write) misses -system.cpu3.icache.overall_misses::cpu3.inst 477 # number of overall misses -system.cpu3.icache.overall_misses::total 477 # number of overall misses -system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 6428500 # number of ReadReq miss cycles -system.cpu3.icache.ReadReq_miss_latency::total 6428500 # number of ReadReq miss cycles -system.cpu3.icache.demand_miss_latency::cpu3.inst 6428500 # number of demand (read+write) miss cycles -system.cpu3.icache.demand_miss_latency::total 6428500 # number of demand (read+write) miss cycles -system.cpu3.icache.overall_miss_latency::cpu3.inst 6428500 # number of overall miss cycles -system.cpu3.icache.overall_miss_latency::total 6428500 # number of overall miss cycles -system.cpu3.icache.ReadReq_accesses::cpu3.inst 20536 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.ReadReq_accesses::total 20536 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.demand_accesses::cpu3.inst 20536 # number of demand (read+write) accesses -system.cpu3.icache.demand_accesses::total 20536 # number of demand (read+write) accesses -system.cpu3.icache.overall_accesses::cpu3.inst 20536 # number of overall (read+write) accesses -system.cpu3.icache.overall_accesses::total 20536 # number of overall (read+write) accesses -system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.023228 # miss rate for ReadReq accesses -system.cpu3.icache.ReadReq_miss_rate::total 0.023228 # miss rate for ReadReq accesses -system.cpu3.icache.demand_miss_rate::cpu3.inst 0.023228 # miss rate for demand accesses -system.cpu3.icache.demand_miss_rate::total 0.023228 # miss rate for demand accesses -system.cpu3.icache.overall_miss_rate::cpu3.inst 0.023228 # miss rate for overall accesses -system.cpu3.icache.overall_miss_rate::total 0.023228 # miss rate for overall accesses -system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 13476.939203 # average ReadReq miss latency -system.cpu3.icache.ReadReq_avg_miss_latency::total 13476.939203 # average ReadReq miss latency -system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 13476.939203 # average overall miss latency -system.cpu3.icache.demand_avg_miss_latency::total 13476.939203 # average overall miss latency -system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 13476.939203 # average overall miss latency -system.cpu3.icache.overall_avg_miss_latency::total 13476.939203 # average overall miss latency +system.cpu3.icache.tags.replacements 319 # number of replacements +system.cpu3.icache.tags.tagsinuse 77.348761 # Cycle average of tags in use +system.cpu3.icache.tags.total_refs 17724 # Total number of references to valid blocks. +system.cpu3.icache.tags.sampled_refs 430 # Sample count of references to valid blocks. +system.cpu3.icache.tags.avg_refs 41.218605 # Average number of references to valid blocks. +system.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu3.icache.tags.occ_blocks::cpu3.inst 77.348761 # Average occupied blocks per requestor +system.cpu3.icache.tags.occ_percent::cpu3.inst 0.151072 # Average percentage of cache occupancy +system.cpu3.icache.tags.occ_percent::total 0.151072 # Average percentage of cache occupancy +system.cpu3.icache.ReadReq_hits::cpu3.inst 17724 # number of ReadReq hits +system.cpu3.icache.ReadReq_hits::total 17724 # number of ReadReq hits +system.cpu3.icache.demand_hits::cpu3.inst 17724 # number of demand (read+write) hits +system.cpu3.icache.demand_hits::total 17724 # number of demand (read+write) hits +system.cpu3.icache.overall_hits::cpu3.inst 17724 # number of overall hits +system.cpu3.icache.overall_hits::total 17724 # number of overall hits +system.cpu3.icache.ReadReq_misses::cpu3.inst 475 # number of ReadReq misses +system.cpu3.icache.ReadReq_misses::total 475 # number of ReadReq misses +system.cpu3.icache.demand_misses::cpu3.inst 475 # number of demand (read+write) misses +system.cpu3.icache.demand_misses::total 475 # number of demand (read+write) misses +system.cpu3.icache.overall_misses::cpu3.inst 475 # number of overall misses +system.cpu3.icache.overall_misses::total 475 # number of overall misses +system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 6467995 # number of ReadReq miss cycles +system.cpu3.icache.ReadReq_miss_latency::total 6467995 # number of ReadReq miss cycles +system.cpu3.icache.demand_miss_latency::cpu3.inst 6467995 # number of demand (read+write) miss cycles +system.cpu3.icache.demand_miss_latency::total 6467995 # number of demand (read+write) miss cycles +system.cpu3.icache.overall_miss_latency::cpu3.inst 6467995 # number of overall miss cycles +system.cpu3.icache.overall_miss_latency::total 6467995 # number of overall miss cycles +system.cpu3.icache.ReadReq_accesses::cpu3.inst 18199 # number of ReadReq accesses(hits+misses) +system.cpu3.icache.ReadReq_accesses::total 18199 # number of ReadReq accesses(hits+misses) +system.cpu3.icache.demand_accesses::cpu3.inst 18199 # number of demand (read+write) accesses +system.cpu3.icache.demand_accesses::total 18199 # number of demand (read+write) accesses +system.cpu3.icache.overall_accesses::cpu3.inst 18199 # number of overall (read+write) accesses +system.cpu3.icache.overall_accesses::total 18199 # number of overall (read+write) accesses +system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.026100 # miss rate for ReadReq accesses +system.cpu3.icache.ReadReq_miss_rate::total 0.026100 # miss rate for ReadReq accesses +system.cpu3.icache.demand_miss_rate::cpu3.inst 0.026100 # miss rate for demand accesses +system.cpu3.icache.demand_miss_rate::total 0.026100 # miss rate for demand accesses +system.cpu3.icache.overall_miss_rate::cpu3.inst 0.026100 # miss rate for overall accesses +system.cpu3.icache.overall_miss_rate::total 0.026100 # miss rate for overall accesses +system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 13616.831579 # average ReadReq miss latency +system.cpu3.icache.ReadReq_avg_miss_latency::total 13616.831579 # average ReadReq miss latency +system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 13616.831579 # average overall miss latency +system.cpu3.icache.demand_avg_miss_latency::total 13616.831579 # average overall miss latency +system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 13616.831579 # average overall miss latency +system.cpu3.icache.overall_avg_miss_latency::total 13616.831579 # average overall miss latency system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -2027,106 +2028,106 @@ system.cpu3.icache.avg_blocked_cycles::no_mshrs nan system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu3.icache.fast_writes 0 # number of fast writes performed system.cpu3.icache.cache_copies 0 # number of cache copies performed -system.cpu3.icache.ReadReq_mshr_hits::cpu3.inst 47 # number of ReadReq MSHR hits -system.cpu3.icache.ReadReq_mshr_hits::total 47 # number of ReadReq MSHR hits -system.cpu3.icache.demand_mshr_hits::cpu3.inst 47 # number of demand (read+write) MSHR hits -system.cpu3.icache.demand_mshr_hits::total 47 # number of demand (read+write) MSHR hits -system.cpu3.icache.overall_mshr_hits::cpu3.inst 47 # number of overall MSHR hits -system.cpu3.icache.overall_mshr_hits::total 47 # number of overall MSHR hits +system.cpu3.icache.ReadReq_mshr_hits::cpu3.inst 45 # number of ReadReq MSHR hits +system.cpu3.icache.ReadReq_mshr_hits::total 45 # number of ReadReq MSHR hits +system.cpu3.icache.demand_mshr_hits::cpu3.inst 45 # number of demand (read+write) MSHR hits +system.cpu3.icache.demand_mshr_hits::total 45 # number of demand (read+write) MSHR hits +system.cpu3.icache.overall_mshr_hits::cpu3.inst 45 # number of overall MSHR hits +system.cpu3.icache.overall_mshr_hits::total 45 # number of overall MSHR hits system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst 430 # number of ReadReq MSHR misses system.cpu3.icache.ReadReq_mshr_misses::total 430 # number of ReadReq MSHR misses system.cpu3.icache.demand_mshr_misses::cpu3.inst 430 # number of demand (read+write) MSHR misses system.cpu3.icache.demand_mshr_misses::total 430 # number of demand (read+write) MSHR misses system.cpu3.icache.overall_mshr_misses::cpu3.inst 430 # number of overall MSHR misses system.cpu3.icache.overall_mshr_misses::total 430 # number of overall MSHR misses -system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 5181004 # number of ReadReq MSHR miss cycles -system.cpu3.icache.ReadReq_mshr_miss_latency::total 5181004 # number of ReadReq MSHR miss cycles -system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 5181004 # number of demand (read+write) MSHR miss cycles -system.cpu3.icache.demand_mshr_miss_latency::total 5181004 # number of demand (read+write) MSHR miss cycles -system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 5181004 # number of overall MSHR miss cycles -system.cpu3.icache.overall_mshr_miss_latency::total 5181004 # number of overall MSHR miss cycles -system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.020939 # mshr miss rate for ReadReq accesses -system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.020939 # mshr miss rate for ReadReq accesses -system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.020939 # mshr miss rate for demand accesses -system.cpu3.icache.demand_mshr_miss_rate::total 0.020939 # mshr miss rate for demand accesses -system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.020939 # mshr miss rate for overall accesses -system.cpu3.icache.overall_mshr_miss_rate::total 0.020939 # mshr miss rate for overall accesses -system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12048.846512 # average ReadReq mshr miss latency -system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 12048.846512 # average ReadReq mshr miss latency -system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 12048.846512 # average overall mshr miss latency -system.cpu3.icache.demand_avg_mshr_miss_latency::total 12048.846512 # average overall mshr miss latency -system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 12048.846512 # average overall mshr miss latency -system.cpu3.icache.overall_avg_mshr_miss_latency::total 12048.846512 # average overall mshr miss latency +system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 5219755 # number of ReadReq MSHR miss cycles +system.cpu3.icache.ReadReq_mshr_miss_latency::total 5219755 # number of ReadReq MSHR miss cycles +system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 5219755 # number of demand (read+write) MSHR miss cycles +system.cpu3.icache.demand_mshr_miss_latency::total 5219755 # number of demand (read+write) MSHR miss cycles +system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 5219755 # number of overall MSHR miss cycles +system.cpu3.icache.overall_mshr_miss_latency::total 5219755 # number of overall MSHR miss cycles +system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.023628 # mshr miss rate for ReadReq accesses +system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.023628 # mshr miss rate for ReadReq accesses +system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.023628 # mshr miss rate for demand accesses +system.cpu3.icache.demand_mshr_miss_rate::total 0.023628 # mshr miss rate for demand accesses +system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.023628 # mshr miss rate for overall accesses +system.cpu3.icache.overall_mshr_miss_rate::total 0.023628 # mshr miss rate for overall accesses +system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12138.965116 # average ReadReq mshr miss latency +system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 12138.965116 # average ReadReq mshr miss latency +system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 12138.965116 # average overall mshr miss latency +system.cpu3.icache.demand_avg_mshr_miss_latency::total 12138.965116 # average overall mshr miss latency +system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 12138.965116 # average overall mshr miss latency +system.cpu3.icache.overall_avg_mshr_miss_latency::total 12138.965116 # average overall mshr miss latency system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.dcache.replacements 0 # number of replacements -system.cpu3.dcache.tagsinuse 24.780818 # Cycle average of tags in use -system.cpu3.dcache.total_refs 42491 # Total number of references to valid blocks. -system.cpu3.dcache.sampled_refs 28 # Sample count of references to valid blocks. -system.cpu3.dcache.avg_refs 1517.535714 # Average number of references to valid blocks. -system.cpu3.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.dcache.occ_blocks::cpu3.data 24.780818 # Average occupied blocks per requestor -system.cpu3.dcache.occ_percent::cpu3.data 0.048400 # Average percentage of cache occupancy -system.cpu3.dcache.occ_percent::total 0.048400 # Average percentage of cache occupancy -system.cpu3.dcache.ReadReq_hits::cpu3.data 46335 # number of ReadReq hits -system.cpu3.dcache.ReadReq_hits::total 46335 # number of ReadReq hits -system.cpu3.dcache.WriteReq_hits::cpu3.data 36269 # number of WriteReq hits -system.cpu3.dcache.WriteReq_hits::total 36269 # number of WriteReq hits +system.cpu3.dcache.tags.replacements 0 # number of replacements +system.cpu3.dcache.tags.tagsinuse 23.659946 # Cycle average of tags in use +system.cpu3.dcache.tags.total_refs 47957 # Total number of references to valid blocks. +system.cpu3.dcache.tags.sampled_refs 28 # Sample count of references to valid blocks. +system.cpu3.dcache.tags.avg_refs 1712.750000 # Average number of references to valid blocks. +system.cpu3.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu3.dcache.tags.occ_blocks::cpu3.data 23.659946 # Average occupied blocks per requestor +system.cpu3.dcache.tags.occ_percent::cpu3.data 0.046211 # Average percentage of cache occupancy +system.cpu3.dcache.tags.occ_percent::total 0.046211 # Average percentage of cache occupancy +system.cpu3.dcache.ReadReq_hits::cpu3.data 50723 # number of ReadReq hits +system.cpu3.dcache.ReadReq_hits::total 50723 # number of ReadReq hits +system.cpu3.dcache.WriteReq_hits::cpu3.data 41752 # number of WriteReq hits +system.cpu3.dcache.WriteReq_hits::total 41752 # number of WriteReq hits system.cpu3.dcache.SwapReq_hits::cpu3.data 12 # number of SwapReq hits system.cpu3.dcache.SwapReq_hits::total 12 # number of SwapReq hits -system.cpu3.dcache.demand_hits::cpu3.data 82604 # number of demand (read+write) hits -system.cpu3.dcache.demand_hits::total 82604 # number of demand (read+write) hits -system.cpu3.dcache.overall_hits::cpu3.data 82604 # number of overall hits -system.cpu3.dcache.overall_hits::total 82604 # number of overall hits -system.cpu3.dcache.ReadReq_misses::cpu3.data 340 # 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miss rate for ReadReq accesses -system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.003790 # miss rate for WriteReq accesses -system.cpu3.dcache.WriteReq_miss_rate::total 0.003790 # miss rate for WriteReq accesses -system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.828571 # miss rate for SwapReq accesses -system.cpu3.dcache.SwapReq_miss_rate::total 0.828571 # miss rate for SwapReq accesses -system.cpu3.dcache.demand_miss_rate::cpu3.data 0.005753 # miss rate for demand accesses -system.cpu3.dcache.demand_miss_rate::total 0.005753 # miss rate for demand accesses -system.cpu3.dcache.overall_miss_rate::cpu3.data 0.005753 # miss rate for overall accesses -system.cpu3.dcache.overall_miss_rate::total 0.005753 # miss rate for overall accesses -system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 12491.176471 # average ReadReq miss latency -system.cpu3.dcache.ReadReq_avg_miss_latency::total 12491.176471 # average ReadReq miss latency -system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 19630.434783 # average WriteReq miss latency -system.cpu3.dcache.WriteReq_avg_miss_latency::total 19630.434783 # average WriteReq miss latency -system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 9456.896552 # average SwapReq miss latency -system.cpu3.dcache.SwapReq_avg_miss_latency::total 9456.896552 # average SwapReq miss latency -system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 14552.301255 # average overall miss latency -system.cpu3.dcache.demand_avg_miss_latency::total 14552.301255 # average overall miss latency -system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 14552.301255 # average overall miss latency -system.cpu3.dcache.overall_avg_miss_latency::total 14552.301255 # average overall miss latency +system.cpu3.dcache.SwapReq_misses::cpu3.data 51 # number of SwapReq misses +system.cpu3.dcache.SwapReq_misses::total 51 # number of SwapReq misses +system.cpu3.dcache.demand_misses::cpu3.data 484 # number of demand (read+write) misses +system.cpu3.dcache.demand_misses::total 484 # number of demand (read+write) misses +system.cpu3.dcache.overall_misses::cpu3.data 484 # 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number of ReadReq accesses(hits+misses) +system.cpu3.dcache.ReadReq_accesses::total 51069 # number of ReadReq accesses(hits+misses) +system.cpu3.dcache.WriteReq_accesses::cpu3.data 41890 # number of WriteReq accesses(hits+misses) +system.cpu3.dcache.WriteReq_accesses::total 41890 # number of WriteReq accesses(hits+misses) +system.cpu3.dcache.SwapReq_accesses::cpu3.data 63 # number of SwapReq accesses(hits+misses) +system.cpu3.dcache.SwapReq_accesses::total 63 # number of SwapReq accesses(hits+misses) +system.cpu3.dcache.demand_accesses::cpu3.data 92959 # number of demand (read+write) accesses +system.cpu3.dcache.demand_accesses::total 92959 # number of demand (read+write) accesses +system.cpu3.dcache.overall_accesses::cpu3.data 92959 # number of overall (read+write) accesses +system.cpu3.dcache.overall_accesses::total 92959 # number of overall (read+write) accesses +system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.006775 # miss rate for ReadReq accesses +system.cpu3.dcache.ReadReq_miss_rate::total 0.006775 # miss rate for ReadReq accesses +system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.003294 # miss rate for WriteReq accesses +system.cpu3.dcache.WriteReq_miss_rate::total 0.003294 # miss rate for WriteReq accesses +system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.809524 # miss rate for SwapReq accesses +system.cpu3.dcache.SwapReq_miss_rate::total 0.809524 # miss rate for SwapReq accesses +system.cpu3.dcache.demand_miss_rate::cpu3.data 0.005207 # miss rate for demand accesses +system.cpu3.dcache.demand_miss_rate::total 0.005207 # miss rate for demand accesses +system.cpu3.dcache.overall_miss_rate::cpu3.data 0.005207 # miss rate for overall accesses +system.cpu3.dcache.overall_miss_rate::total 0.005207 # miss rate for overall accesses +system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 12859.592486 # average ReadReq miss latency +system.cpu3.dcache.ReadReq_avg_miss_latency::total 12859.592486 # average ReadReq miss latency +system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 20862.398551 # average WriteReq miss latency +system.cpu3.dcache.WriteReq_avg_miss_latency::total 20862.398551 # average WriteReq miss latency +system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 9382.529412 # average SwapReq miss latency +system.cpu3.dcache.SwapReq_avg_miss_latency::total 9382.529412 # average SwapReq miss latency +system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 15141.384298 # average overall miss latency +system.cpu3.dcache.demand_avg_miss_latency::total 15141.384298 # average overall miss latency +system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 15141.384298 # average overall miss latency +system.cpu3.dcache.overall_avg_miss_latency::total 15141.384298 # average overall miss latency system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -2135,87 +2136,87 @@ system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu3.dcache.fast_writes 0 # number of fast writes performed system.cpu3.dcache.cache_copies 0 # number of cache copies performed -system.cpu3.dcache.ReadReq_mshr_hits::cpu3.data 182 # number of ReadReq MSHR hits -system.cpu3.dcache.ReadReq_mshr_hits::total 182 # number of ReadReq MSHR hits -system.cpu3.dcache.WriteReq_mshr_hits::cpu3.data 33 # number of WriteReq MSHR hits -system.cpu3.dcache.WriteReq_mshr_hits::total 33 # number of WriteReq MSHR hits -system.cpu3.dcache.demand_mshr_hits::cpu3.data 215 # number of demand (read+write) MSHR hits -system.cpu3.dcache.demand_mshr_hits::total 215 # number of demand (read+write) MSHR hits -system.cpu3.dcache.overall_mshr_hits::cpu3.data 215 # number of overall MSHR hits -system.cpu3.dcache.overall_mshr_hits::total 215 # number of overall MSHR hits -system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 158 # number of ReadReq MSHR misses -system.cpu3.dcache.ReadReq_mshr_misses::total 158 # number of ReadReq MSHR misses -system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 105 # number of WriteReq MSHR misses -system.cpu3.dcache.WriteReq_mshr_misses::total 105 # number of WriteReq MSHR misses -system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 58 # number of SwapReq MSHR misses -system.cpu3.dcache.SwapReq_mshr_misses::total 58 # number of SwapReq MSHR misses -system.cpu3.dcache.demand_mshr_misses::cpu3.data 263 # number of demand (read+write) MSHR misses -system.cpu3.dcache.demand_mshr_misses::total 263 # number of demand (read+write) MSHR misses -system.cpu3.dcache.overall_mshr_misses::cpu3.data 263 # number of overall MSHR misses -system.cpu3.dcache.overall_mshr_misses::total 263 # number of overall MSHR misses -system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 1065020 # number of ReadReq MSHR miss cycles -system.cpu3.dcache.ReadReq_mshr_miss_latency::total 1065020 # number of ReadReq MSHR miss cycles -system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1284501 # number of WriteReq MSHR miss cycles -system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1284501 # number of WriteReq MSHR miss cycles -system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 432500 # number of SwapReq MSHR miss cycles -system.cpu3.dcache.SwapReq_mshr_miss_latency::total 432500 # number of SwapReq MSHR miss cycles -system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 2349521 # number of demand (read+write) MSHR miss cycles -system.cpu3.dcache.demand_mshr_miss_latency::total 2349521 # number of demand (read+write) MSHR miss cycles -system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 2349521 # number of overall MSHR miss cycles -system.cpu3.dcache.overall_mshr_miss_latency::total 2349521 # number of overall MSHR miss cycles -system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.003385 # mshr miss rate for ReadReq accesses -system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.003385 # mshr miss rate for ReadReq accesses -system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.002884 # mshr miss rate for WriteReq accesses -system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.002884 # mshr miss rate for WriteReq accesses -system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.828571 # mshr miss rate for SwapReq accesses -system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.828571 # mshr miss rate for SwapReq accesses -system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.003166 # mshr miss rate for demand accesses -system.cpu3.dcache.demand_mshr_miss_rate::total 0.003166 # mshr miss rate for demand accesses -system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.003166 # mshr miss rate for overall accesses -system.cpu3.dcache.overall_mshr_miss_rate::total 0.003166 # mshr miss rate for overall accesses -system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 6740.632911 # average ReadReq mshr miss latency -system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 6740.632911 # average ReadReq mshr miss latency -system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 12233.342857 # average WriteReq mshr miss latency -system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 12233.342857 # average WriteReq mshr miss latency -system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 7456.896552 # average SwapReq mshr miss latency -system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 7456.896552 # average SwapReq mshr miss latency -system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 8933.539924 # average overall mshr miss latency -system.cpu3.dcache.demand_avg_mshr_miss_latency::total 8933.539924 # average overall mshr miss latency -system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 8933.539924 # average overall mshr miss latency -system.cpu3.dcache.overall_avg_mshr_miss_latency::total 8933.539924 # average overall mshr miss latency +system.cpu3.dcache.ReadReq_mshr_hits::cpu3.data 195 # number of ReadReq MSHR hits +system.cpu3.dcache.ReadReq_mshr_hits::total 195 # number of ReadReq MSHR hits +system.cpu3.dcache.WriteReq_mshr_hits::cpu3.data 32 # number of WriteReq MSHR hits +system.cpu3.dcache.WriteReq_mshr_hits::total 32 # number of WriteReq MSHR hits +system.cpu3.dcache.demand_mshr_hits::cpu3.data 227 # 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number of overall MSHR miss cycles +system.cpu3.dcache.overall_mshr_miss_latency::total 2326002 # number of overall MSHR miss cycles +system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.002957 # mshr miss rate for ReadReq accesses +system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.002957 # mshr miss rate for ReadReq accesses +system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.002530 # mshr miss rate for WriteReq accesses +system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.002530 # mshr miss rate for WriteReq accesses +system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.809524 # mshr miss rate for SwapReq accesses +system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.809524 # mshr miss rate for SwapReq accesses +system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.002765 # mshr miss rate for demand accesses +system.cpu3.dcache.demand_mshr_miss_rate::total 0.002765 # mshr miss rate for demand accesses +system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.002765 # mshr miss rate for overall accesses +system.cpu3.dcache.overall_mshr_miss_rate::total 0.002765 # mshr miss rate for overall accesses +system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 6647.437086 # average ReadReq mshr miss latency +system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 6647.437086 # average ReadReq mshr miss latency +system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 12473.952830 # average WriteReq mshr miss latency +system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 12473.952830 # average WriteReq mshr miss latency +system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 7382.176471 # average SwapReq mshr miss latency +system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 7382.176471 # average SwapReq mshr miss latency +system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 9050.591440 # average overall mshr miss latency +system.cpu3.dcache.demand_avg_mshr_miss_latency::total 9050.591440 # average overall mshr miss latency +system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 9050.591440 # average overall mshr miss latency +system.cpu3.dcache.overall_avg_mshr_miss_latency::total 9050.591440 # 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Average occupied blocks per requestor -system.l2c.occ_blocks::cpu3.inst 3.476542 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu3.data 0.732205 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.000012 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.004346 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.000891 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.000919 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.data 0.000083 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu2.inst 0.000036 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu2.data 0.000011 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu3.inst 0.000053 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu3.data 0.000011 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.006361 # 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Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3.inst 2.743977 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3.data 0.695773 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.000012 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.004347 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.000891 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.000119 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.000011 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.inst 0.000847 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.data 0.000083 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu3.inst 0.000042 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu3.data 0.000011 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.006363 # 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number of demand (read+write) hits system.l2c.demand_hits::total 1443 # number of demand (read+write) hits system.l2c.overall_hits::cpu0.inst 229 # number of overall hits system.l2c.overall_hits::cpu0.data 5 # number of overall hits -system.l2c.overall_hits::cpu1.inst 343 # number of overall hits -system.l2c.overall_hits::cpu1.data 5 # number of overall hits -system.l2c.overall_hits::cpu2.inst 417 # number of overall hits -system.l2c.overall_hits::cpu2.data 11 # number of overall hits -system.l2c.overall_hits::cpu3.inst 422 # number of overall hits +system.l2c.overall_hits::cpu1.inst 412 # number of overall hits +system.l2c.overall_hits::cpu1.data 11 # number of overall hits +system.l2c.overall_hits::cpu2.inst 349 # number of overall hits +system.l2c.overall_hits::cpu2.data 5 # number of overall hits +system.l2c.overall_hits::cpu3.inst 421 # number of overall hits system.l2c.overall_hits::cpu3.data 11 # number of overall hits system.l2c.overall_hits::total 1443 # number of overall hits system.l2c.ReadReq_misses::cpu0.inst 359 # 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number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu2.data 16 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu3.data 18 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 75 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 16 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu2.data 18 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu3.data 20 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 76 # number of UpgradeReq misses system.l2c.ReadExReq_misses::cpu0.data 94 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 13 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu2.data 12 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 12 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu2.data 13 # number of ReadExReq misses system.l2c.ReadExReq_misses::cpu3.data 12 # number of ReadExReq misses system.l2c.ReadExReq_misses::total 131 # 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number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 912500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.inst 5263750 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.data 1590999 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu3.inst 570250 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu3.data 971000 # number of overall miss cycles +system.l2c.overall_miss_latency::total 47873999 # number of overall miss cycles system.l2c.ReadReq_accesses::cpu0.inst 588 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu0.data 79 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 425 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 428 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu1.data 12 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.inst 428 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2.inst 425 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu2.data 12 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu3.inst 430 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu3.data 12 # number of ReadReq accesses(hits+misses) @@ -2321,47 +2322,47 @@ system.l2c.ReadReq_accesses::total 1986 # nu system.l2c.Writeback_accesses::writebacks 1 # number of Writeback accesses(hits+misses) system.l2c.Writeback_accesses::total 1 # number of Writeback accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu0.data 25 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 19 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu2.data 16 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu3.data 18 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 78 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 16 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu2.data 18 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu3.data 20 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 79 # number of UpgradeReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu0.data 94 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 13 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu2.data 12 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 12 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu2.data 13 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu3.data 12 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::total 131 # number of ReadExReq accesses(hits+misses) system.l2c.demand_accesses::cpu0.inst 588 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu0.data 173 # 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number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 425 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 25 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.inst 428 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.data 24 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 428 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 24 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.inst 425 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.data 25 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu3.inst 430 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu3.data 24 # number of overall (read+write) accesses system.l2c.overall_accesses::total 2117 # number of overall (read+write) accesses system.l2c.ReadReq_miss_rate::cpu0.inst 0.610544 # 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mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.583333 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.007009 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.083333 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.023364 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.083333 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.171765 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.583333 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu3.inst 0.013953 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu3.data 0.083333 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::total 0.266365 # mshr miss rate for ReadReq accesses @@ -2527,7 +2528,7 @@ system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.880000 system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.961538 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.962025 # mshr miss rate for UpgradeReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for ReadExReq accesses @@ -2535,59 +2536,59 @@ system.l2c.ReadExReq_mshr_miss_rate::cpu3.data 1 system.l2c.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.l2c.demand_mshr_miss_rate::cpu0.inst 0.607143 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu0.data 0.971098 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.188235 # 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average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 76250 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 57260.273973 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 62321.428571 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst 54583.333333 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.data 76250 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 56749.527410 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 57357.750473 # average ReadReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10001 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10563.437500 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 11094.687500 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10001 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 10001 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10120.986667 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 66630.319149 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 65711.538462 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 62937.500000 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 58604.166667 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 65465.648855 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 54942.577031 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 64392.857143 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 58906.250000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 64500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 60583.333333 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.data 63961.538462 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 61458.333333 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3.data 59961.538462 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 58479.545455 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 54942.577031 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 64392.857143 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 58906.250000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 64500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 60583.333333 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.data 63961.538462 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 61458.333333 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3.data 59961.538462 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 58479.545455 # average overall mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10231.250000 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 65409.574468 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 56020.833333 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 69788.384615 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 60937.500000 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 64574.419847 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 55433.473389 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 64934.523810 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 69575 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 57576.923077 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 57260.273973 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 67174.950000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 54583.333333 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.data 62115.384615 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 58790.150000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 55433.473389 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 64934.523810 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 69575 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 57576.923077 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 57260.273973 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 67174.950000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 54583.333333 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.data 62115.384615 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 58790.150000 # average overall mshr miss latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt index 3469c3943..42fbfc6a4 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt @@ -86,15 +86,15 @@ system.cpu0.num_idle_cycles 0 # Nu system.cpu0.num_busy_cycles 175415 # Number of busy cycles system.cpu0.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu0.idle_fraction 0 # Percentage of idle cycles -system.cpu0.icache.replacements 215 # number of replacements -system.cpu0.icache.tagsinuse 222.772698 # Cycle average of tags in use -system.cpu0.icache.total_refs 174921 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 467 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 374.563169 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 222.772698 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.435103 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.435103 # Average percentage of cache occupancy +system.cpu0.icache.tags.replacements 215 # number of replacements +system.cpu0.icache.tags.tagsinuse 222.772698 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 174921 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 467 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 374.563169 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 222.772698 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.435103 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.435103 # Average percentage of cache occupancy system.cpu0.icache.ReadReq_hits::cpu0.inst 174921 # number of ReadReq hits system.cpu0.icache.ReadReq_hits::total 174921 # number of ReadReq hits system.cpu0.icache.demand_hits::cpu0.inst 174921 # number of demand (read+write) hits @@ -128,15 +128,15 @@ system.cpu0.icache.avg_blocked_cycles::no_targets nan system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 2 # number of replacements -system.cpu0.dcache.tagsinuse 150.745494 # Cycle average of tags in use -system.cpu0.dcache.total_refs 81883 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 167 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 490.317365 # Average number of references to valid blocks. -system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 150.745494 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.294425 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.294425 # Average percentage of cache occupancy +system.cpu0.dcache.tags.replacements 2 # number of replacements +system.cpu0.dcache.tags.tagsinuse 150.745494 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 81883 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 167 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 490.317365 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 150.745494 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.294425 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.294425 # Average percentage of cache occupancy system.cpu0.dcache.ReadReq_hits::cpu0.data 54430 # number of ReadReq hits system.cpu0.dcache.ReadReq_hits::total 54430 # number of ReadReq hits system.cpu0.dcache.WriteReq_hits::cpu0.data 27578 # number of WriteReq hits @@ -210,15 +210,15 @@ system.cpu1.num_idle_cycles 7873.724337 # Nu system.cpu1.num_busy_cycles 165421.275663 # Number of busy cycles system.cpu1.not_idle_fraction 0.954565 # Percentage of non-idle cycles system.cpu1.idle_fraction 0.045435 # Percentage of idle cycles -system.cpu1.icache.replacements 278 # number of replacements -system.cpu1.icache.tagsinuse 76.751702 # Cycle average of tags in use -system.cpu1.icache.total_refs 167072 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 358 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 466.681564 # Average number of references to valid blocks. -system.cpu1.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 76.751702 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.149906 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.149906 # Average percentage of cache occupancy +system.cpu1.icache.tags.replacements 278 # number of replacements +system.cpu1.icache.tags.tagsinuse 76.751702 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 167072 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 358 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 466.681564 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 76.751702 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.149906 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.149906 # Average percentage of cache occupancy system.cpu1.icache.ReadReq_hits::cpu1.inst 167072 # number of ReadReq hits system.cpu1.icache.ReadReq_hits::total 167072 # number of ReadReq hits system.cpu1.icache.demand_hits::cpu1.inst 167072 # number of demand (read+write) hits @@ -252,15 +252,15 @@ system.cpu1.icache.avg_blocked_cycles::no_targets nan system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.replacements 0 # number of replacements -system.cpu1.dcache.tagsinuse 30.316999 # Cycle average of tags in use -system.cpu1.dcache.total_refs 26731 # Total number of references to valid blocks. -system.cpu1.dcache.sampled_refs 26 # Sample count of references to valid blocks. -system.cpu1.dcache.avg_refs 1028.115385 # Average number of references to valid blocks. -system.cpu1.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::cpu1.data 30.316999 # Average occupied blocks per requestor -system.cpu1.dcache.occ_percent::cpu1.data 0.059213 # Average percentage of cache occupancy -system.cpu1.dcache.occ_percent::total 0.059213 # Average percentage of cache occupancy +system.cpu1.dcache.tags.replacements 0 # number of replacements +system.cpu1.dcache.tags.tagsinuse 30.316999 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 26731 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 26 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 1028.115385 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 30.316999 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.059213 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.059213 # Average percentage of cache occupancy system.cpu1.dcache.ReadReq_hits::cpu1.data 40470 # number of ReadReq hits system.cpu1.dcache.ReadReq_hits::total 40470 # number of ReadReq hits system.cpu1.dcache.WriteReq_hits::cpu1.data 12563 # number of WriteReq hits @@ -332,15 +332,15 @@ system.cpu2.num_idle_cycles 7936.951217 # Nu system.cpu2.num_busy_cycles 165358.048783 # Number of busy cycles system.cpu2.not_idle_fraction 0.954200 # Percentage of non-idle cycles system.cpu2.idle_fraction 0.045800 # Percentage of idle cycles -system.cpu2.icache.replacements 278 # number of replacements -system.cpu2.icache.tagsinuse 74.781015 # Cycle average of tags in use -system.cpu2.icache.total_refs 167008 # Total number of references to valid blocks. -system.cpu2.icache.sampled_refs 358 # Sample count of references to valid blocks. -system.cpu2.icache.avg_refs 466.502793 # Average number of references to valid blocks. -system.cpu2.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.icache.occ_blocks::cpu2.inst 74.781015 # Average occupied blocks per requestor -system.cpu2.icache.occ_percent::cpu2.inst 0.146057 # Average percentage of cache occupancy -system.cpu2.icache.occ_percent::total 0.146057 # Average percentage of cache occupancy +system.cpu2.icache.tags.replacements 278 # number of replacements +system.cpu2.icache.tags.tagsinuse 74.781015 # Cycle average of tags in use +system.cpu2.icache.tags.total_refs 167008 # Total number of references to valid blocks. +system.cpu2.icache.tags.sampled_refs 358 # Sample count of references to valid blocks. +system.cpu2.icache.tags.avg_refs 466.502793 # Average number of references to valid blocks. +system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu2.icache.tags.occ_blocks::cpu2.inst 74.781015 # Average occupied blocks per requestor +system.cpu2.icache.tags.occ_percent::cpu2.inst 0.146057 # Average percentage of cache occupancy +system.cpu2.icache.tags.occ_percent::total 0.146057 # Average percentage of cache occupancy system.cpu2.icache.ReadReq_hits::cpu2.inst 167008 # number of ReadReq hits system.cpu2.icache.ReadReq_hits::total 167008 # number of ReadReq hits system.cpu2.icache.demand_hits::cpu2.inst 167008 # number of demand (read+write) hits @@ -374,15 +374,15 @@ system.cpu2.icache.avg_blocked_cycles::no_targets nan system.cpu2.icache.fast_writes 0 # number of fast writes performed system.cpu2.icache.cache_copies 0 # number of cache copies performed system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.dcache.replacements 0 # number of replacements -system.cpu2.dcache.tagsinuse 29.605505 # Cycle average of tags in use -system.cpu2.dcache.total_refs 33613 # Total number of references to valid blocks. -system.cpu2.dcache.sampled_refs 26 # Sample count of references to valid blocks. -system.cpu2.dcache.avg_refs 1292.807692 # Average number of references to valid blocks. -system.cpu2.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.dcache.occ_blocks::cpu2.data 29.605505 # Average occupied blocks per requestor -system.cpu2.dcache.occ_percent::cpu2.data 0.057823 # Average percentage of cache occupancy -system.cpu2.dcache.occ_percent::total 0.057823 # Average percentage of cache occupancy +system.cpu2.dcache.tags.replacements 0 # number of replacements +system.cpu2.dcache.tags.tagsinuse 29.605505 # Cycle average of tags in use +system.cpu2.dcache.tags.total_refs 33613 # Total number of references to valid blocks. +system.cpu2.dcache.tags.sampled_refs 26 # Sample count of references to valid blocks. +system.cpu2.dcache.tags.avg_refs 1292.807692 # Average number of references to valid blocks. +system.cpu2.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu2.dcache.tags.occ_blocks::cpu2.data 29.605505 # Average occupied blocks per requestor +system.cpu2.dcache.tags.occ_percent::cpu2.data 0.057823 # Average percentage of cache occupancy +system.cpu2.dcache.tags.occ_percent::total 0.057823 # Average percentage of cache occupancy system.cpu2.dcache.ReadReq_hits::cpu2.data 42194 # number of ReadReq hits system.cpu2.dcache.ReadReq_hits::total 42194 # number of ReadReq hits system.cpu2.dcache.WriteReq_hits::cpu2.data 15998 # number of WriteReq hits @@ -454,15 +454,15 @@ system.cpu3.num_idle_cycles 8001.119846 # Nu system.cpu3.num_busy_cycles 165292.880154 # Number of busy cycles system.cpu3.not_idle_fraction 0.953829 # Percentage of non-idle cycles system.cpu3.idle_fraction 0.046171 # Percentage of idle cycles -system.cpu3.icache.replacements 279 # number of replacements -system.cpu3.icache.tagsinuse 72.874497 # Cycle average of tags in use -system.cpu3.icache.total_refs 166942 # Total number of references to valid blocks. -system.cpu3.icache.sampled_refs 359 # Sample count of references to valid blocks. -system.cpu3.icache.avg_refs 465.019499 # Average number of references to valid blocks. -system.cpu3.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.icache.occ_blocks::cpu3.inst 72.874497 # Average occupied blocks per requestor -system.cpu3.icache.occ_percent::cpu3.inst 0.142333 # Average percentage of cache occupancy -system.cpu3.icache.occ_percent::total 0.142333 # Average percentage of cache occupancy +system.cpu3.icache.tags.replacements 279 # number of replacements +system.cpu3.icache.tags.tagsinuse 72.874497 # Cycle average of tags in use +system.cpu3.icache.tags.total_refs 166942 # Total number of references to valid blocks. +system.cpu3.icache.tags.sampled_refs 359 # Sample count of references to valid blocks. +system.cpu3.icache.tags.avg_refs 465.019499 # Average number of references to valid blocks. +system.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu3.icache.tags.occ_blocks::cpu3.inst 72.874497 # Average occupied blocks per requestor +system.cpu3.icache.tags.occ_percent::cpu3.inst 0.142333 # Average percentage of cache occupancy +system.cpu3.icache.tags.occ_percent::total 0.142333 # Average percentage of cache occupancy system.cpu3.icache.ReadReq_hits::cpu3.inst 166942 # number of ReadReq hits system.cpu3.icache.ReadReq_hits::total 166942 # number of ReadReq hits system.cpu3.icache.demand_hits::cpu3.inst 166942 # number of demand (read+write) hits @@ -496,15 +496,15 @@ system.cpu3.icache.avg_blocked_cycles::no_targets nan system.cpu3.icache.fast_writes 0 # number of fast writes performed system.cpu3.icache.cache_copies 0 # number of cache copies performed system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.dcache.replacements 0 # number of replacements -system.cpu3.dcache.tagsinuse 28.795404 # Cycle average of tags in use -system.cpu3.dcache.total_refs 30236 # Total number of references to valid blocks. -system.cpu3.dcache.sampled_refs 27 # Sample count of references to valid blocks. -system.cpu3.dcache.avg_refs 1119.851852 # Average number of references to valid blocks. -system.cpu3.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.dcache.occ_blocks::cpu3.data 28.795404 # Average occupied blocks per requestor -system.cpu3.dcache.occ_percent::cpu3.data 0.056241 # Average percentage of cache occupancy -system.cpu3.dcache.occ_percent::total 0.056241 # Average percentage of cache occupancy +system.cpu3.dcache.tags.replacements 0 # number of replacements +system.cpu3.dcache.tags.tagsinuse 28.795404 # Cycle average of tags in use +system.cpu3.dcache.tags.total_refs 30236 # Total number of references to valid blocks. +system.cpu3.dcache.tags.sampled_refs 27 # Sample count of references to valid blocks. +system.cpu3.dcache.tags.avg_refs 1119.851852 # Average number of references to valid blocks. +system.cpu3.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu3.dcache.tags.occ_blocks::cpu3.data 28.795404 # Average occupied blocks per requestor +system.cpu3.dcache.tags.occ_percent::cpu3.data 0.056241 # Average percentage of cache occupancy +system.cpu3.dcache.tags.occ_percent::total 0.056241 # Average percentage of cache occupancy system.cpu3.dcache.ReadReq_hits::cpu3.data 41301 # number of ReadReq hits system.cpu3.dcache.ReadReq_hits::total 41301 # number of ReadReq hits system.cpu3.dcache.WriteReq_hits::cpu3.data 14260 # number of WriteReq hits @@ -554,31 +554,31 @@ system.cpu3.dcache.avg_blocked_cycles::no_targets nan system.cpu3.dcache.fast_writes 0 # number of fast writes performed system.cpu3.dcache.cache_copies 0 # number of cache copies performed system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.replacements 0 # number of replacements -system.l2c.tagsinuse 366.582542 # Cycle average of tags in use -system.l2c.total_refs 1220 # Total number of references to valid blocks. -system.l2c.sampled_refs 421 # Sample count of references to valid blocks. -system.l2c.avg_refs 2.897862 # Average number of references to valid blocks. -system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 0.966439 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 239.426226 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 55.207595 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 59.511852 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 6.721145 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu2.inst 1.930661 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu2.data 0.935410 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu3.inst 0.977573 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu3.data 0.905640 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.000015 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.003653 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.000842 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.000908 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.data 0.000103 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu2.inst 0.000029 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu2.data 0.000014 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu3.inst 0.000015 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu3.data 0.000014 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.005594 # Average percentage of cache occupancy +system.l2c.tags.replacements 0 # number of replacements +system.l2c.tags.tagsinuse 366.582542 # Cycle average of tags in use +system.l2c.tags.total_refs 1220 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 421 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 2.897862 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 0.966439 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 239.426226 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 55.207595 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 59.511852 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 6.721145 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.inst 1.930661 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.data 0.935410 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3.inst 0.977573 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3.data 0.905640 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.000015 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.003653 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.000842 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.000908 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.000103 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.inst 0.000029 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.data 0.000014 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu3.inst 0.000015 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu3.data 0.000014 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.005594 # Average percentage of cache occupancy system.l2c.ReadReq_hits::cpu0.inst 185 # number of ReadReq hits system.l2c.ReadReq_hits::cpu0.data 5 # number of ReadReq hits system.l2c.ReadReq_hits::cpu1.inst 296 # number of ReadReq hits diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt index a78d037d9..4a2827ac8 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt @@ -1,16 +1,16 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000263 # Number of seconds simulated -sim_ticks 262793500 # Number of ticks simulated -final_tick 262793500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 262794500 # Number of ticks simulated +final_tick 262794500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1490059 # Simulator instruction rate (inst/s) -host_op_rate 1490014 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 590046557 # Simulator tick rate (ticks/s) -host_mem_usage 244196 # Number of bytes of host memory used -host_seconds 0.45 # Real time elapsed on the host -sim_insts 663601 # Number of instructions simulated -sim_ops 663601 # Number of ops (including micro ops) simulated +host_inst_rate 146225 # Simulator instruction rate (inst/s) +host_op_rate 146224 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 57909206 # Simulator tick rate (ticks/s) +host_mem_usage 244388 # Number of bytes of host memory used +host_seconds 4.54 # Real time elapsed on the host +sim_insts 663567 # Number of instructions simulated +sim_ops 663567 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu0.inst 18240 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.data 10560 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.inst 3776 # Number of bytes read from this memory @@ -34,30 +34,30 @@ system.physmem.num_reads::cpu2.data 15 # Nu system.physmem.num_reads::cpu3.inst 8 # Number of read requests responded to by this memory system.physmem.num_reads::cpu3.data 16 # Number of read requests responded to by this memory system.physmem.num_reads::total 572 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu0.inst 69408109 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 40183642 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 14368696 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 5357819 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 487074 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 3653058 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.inst 1948298 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.data 3896596 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 139303293 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 69408109 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 14368696 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 487074 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu3.inst 1948298 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 86212178 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 69408109 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 40183642 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 14368696 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 5357819 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 487074 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 3653058 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.inst 1948298 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.data 3896596 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 139303293 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 139303293 # Throughput (bytes/s) +system.physmem.bw_read::cpu0.inst 69407845 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 40183489 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 14368642 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 5357799 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 487073 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 3653044 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.inst 1948290 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.data 3896581 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 139302763 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 69407845 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 14368642 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 487073 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu3.inst 1948290 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 86211850 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 69407845 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 40183489 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 14368642 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 5357799 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 487073 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 3653044 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.inst 1948290 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.data 3896581 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 139302763 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 139302763 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 430 # Transaction distribution system.membus.trans_dist::ReadResp 430 # Transaction distribution system.membus.trans_dist::UpgradeReq 272 # Transaction distribution @@ -70,11 +70,11 @@ system.membus.tot_pkt_size_system.l2c.mem_side 36608 system.membus.tot_pkt_size 36608 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 36608 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 855296 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 852296 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.3 # Layer utilization (%) -system.membus.respLayer0.occupancy 5423500 # Layer occupancy (ticks) -system.membus.respLayer0.utilization 2.1 # Layer utilization (%) -system.toL2Bus.throughput 646591335 # Throughput (bytes/s) +system.membus.respLayer1.occupancy 5420500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 2.1 # Layer utilization (%) +system.toL2Bus.throughput 646588875 # Throughput (bytes/s) system.toL2Bus.trans_dist::ReadReq 2225 # Transaction distribution system.toL2Bus.trans_dist::ReadResp 2225 # Transaction distribution system.toL2Bus.trans_dist::Writeback 1 # Transaction distribution @@ -85,11 +85,11 @@ system.toL2Bus.trans_dist::ReadExResp 429 # Tr system.toL2Bus.pkt_count_system.cpu0.icache.mem_side 934 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side 580 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_count_system.cpu1.icache.mem_side 732 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side 388 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side 355 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_count_system.cpu2.icache.mem_side 732 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side 359 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side 352 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_count_system.cpu3.icache.mem_side 734 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side 361 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side 401 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_count 4820 # Packet count per connected master and slave (bytes) system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side 29888 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side 10944 # Cumulative packet size per connected master and slave (bytes) @@ -102,26 +102,26 @@ system.toL2Bus.tot_pkt_size_system.cpu3.dcache.mem_side 1600 system.toL2Bus.tot_pkt_size 116032 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.data_through_bus 116032 # Total data (bytes) system.toL2Bus.snoop_data_through_bus 53888 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 1474488 # Layer occupancy (ticks) +system.toL2Bus.reqLayer0.occupancy 1473490 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%) system.toL2Bus.respLayer0.occupancy 2101500 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.8 # Layer utilization (%) system.toL2Bus.respLayer1.occupancy 1430481 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 1650489 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 1650488 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.6 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 1281961 # Layer occupancy (ticks) -system.toL2Bus.respLayer3.utilization 0.5 # Layer utilization (%) -system.toL2Bus.respLayer4.occupancy 1651987 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 1157483 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.utilization 0.4 # Layer utilization (%) +system.toL2Bus.respLayer4.occupancy 1651988 # Layer occupancy (ticks) system.toL2Bus.respLayer4.utilization 0.6 # Layer utilization (%) -system.toL2Bus.respLayer5.occupancy 1173486 # Layer occupancy (ticks) +system.toL2Bus.respLayer5.occupancy 1147981 # Layer occupancy (ticks) system.toL2Bus.respLayer5.utilization 0.4 # Layer utilization (%) system.toL2Bus.respLayer6.occupancy 1651999 # Layer occupancy (ticks) system.toL2Bus.respLayer6.utilization 0.6 # Layer utilization (%) -system.toL2Bus.respLayer7.occupancy 1177490 # Layer occupancy (ticks) -system.toL2Bus.respLayer7.utilization 0.4 # Layer utilization (%) +system.toL2Bus.respLayer7.occupancy 1327473 # Layer occupancy (ticks) +system.toL2Bus.respLayer7.utilization 0.5 # Layer utilization (%) system.cpu0.workload.num_syscalls 89 # Number of system calls -system.cpu0.numCycles 525587 # number of cpu cycles simulated +system.cpu0.numCycles 525589 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu0.committedInsts 158574 # Number of instructions committed @@ -140,18 +140,18 @@ system.cpu0.num_mem_refs 74021 # nu system.cpu0.num_load_insts 49007 # Number of load instructions system.cpu0.num_store_insts 25014 # Number of store instructions system.cpu0.num_idle_cycles 0 # Number of idle cycles -system.cpu0.num_busy_cycles 525587 # Number of busy cycles +system.cpu0.num_busy_cycles 525589 # Number of busy cycles system.cpu0.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu0.idle_fraction 0 # Percentage of idle cycles -system.cpu0.icache.replacements 215 # number of replacements -system.cpu0.icache.tagsinuse 212.401760 # Cycle average of tags in use -system.cpu0.icache.total_refs 158170 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 467 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 338.693790 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 212.401760 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.414847 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.414847 # Average percentage of cache occupancy +system.cpu0.icache.tags.replacements 215 # number of replacements +system.cpu0.icache.tags.tagsinuse 212.401822 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 158170 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 467 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 338.693790 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 212.401822 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.414847 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.414847 # Average percentage of cache occupancy system.cpu0.icache.ReadReq_hits::cpu0.inst 158170 # number of ReadReq hits system.cpu0.icache.ReadReq_hits::total 158170 # number of ReadReq hits system.cpu0.icache.demand_hits::cpu0.inst 158170 # number of demand (read+write) hits @@ -164,12 +164,12 @@ system.cpu0.icache.demand_misses::cpu0.inst 467 # system.cpu0.icache.demand_misses::total 467 # number of demand (read+write) misses system.cpu0.icache.overall_misses::cpu0.inst 467 # number of overall misses system.cpu0.icache.overall_misses::total 467 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 18147500 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 18147500 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 18147500 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 18147500 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 18147500 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 18147500 # number of overall miss cycles +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 18148000 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 18148000 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 18148000 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 18148000 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 18148000 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 18148000 # number of overall miss cycles system.cpu0.icache.ReadReq_accesses::cpu0.inst 158637 # number of ReadReq accesses(hits+misses) system.cpu0.icache.ReadReq_accesses::total 158637 # number of ReadReq accesses(hits+misses) system.cpu0.icache.demand_accesses::cpu0.inst 158637 # number of demand (read+write) accesses @@ -182,12 +182,12 @@ system.cpu0.icache.demand_miss_rate::cpu0.inst 0.002944 system.cpu0.icache.demand_miss_rate::total 0.002944 # miss rate for demand accesses system.cpu0.icache.overall_miss_rate::cpu0.inst 0.002944 # miss rate for overall accesses system.cpu0.icache.overall_miss_rate::total 0.002944 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 38859.743041 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 38859.743041 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 38859.743041 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 38859.743041 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 38859.743041 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 38859.743041 # average overall miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 38860.813704 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 38860.813704 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 38860.813704 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 38860.813704 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 38860.813704 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 38860.813704 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -202,34 +202,34 @@ system.cpu0.icache.demand_mshr_misses::cpu0.inst 467 system.cpu0.icache.demand_mshr_misses::total 467 # number of demand (read+write) MSHR misses system.cpu0.icache.overall_mshr_misses::cpu0.inst 467 # number of overall MSHR misses system.cpu0.icache.overall_mshr_misses::total 467 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 17213500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 17213500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 17213500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 17213500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 17213500 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 17213500 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 17214000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 17214000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 17214000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 17214000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 17214000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 17214000 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.002944 # mshr miss rate for ReadReq accesses system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.002944 # mshr miss rate for ReadReq accesses system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.002944 # mshr miss rate for demand accesses system.cpu0.icache.demand_mshr_miss_rate::total 0.002944 # mshr miss rate for demand accesses system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.002944 # mshr miss rate for overall accesses system.cpu0.icache.overall_mshr_miss_rate::total 0.002944 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 36859.743041 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 36859.743041 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 36859.743041 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 36859.743041 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 36859.743041 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 36859.743041 # average overall mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 36860.813704 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 36860.813704 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 36860.813704 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 36860.813704 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 36860.813704 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 36860.813704 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 2 # number of replacements -system.cpu0.dcache.tagsinuse 145.572033 # Cycle average of tags in use -system.cpu0.dcache.total_refs 73489 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 167 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 440.053892 # Average number of references to valid blocks. -system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 145.572033 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.284320 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.284320 # Average percentage of cache occupancy +system.cpu0.dcache.tags.replacements 2 # number of replacements +system.cpu0.dcache.tags.tagsinuse 145.571924 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 73489 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 167 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 440.053892 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 145.571924 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.284320 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.284320 # Average percentage of cache occupancy system.cpu0.dcache.ReadReq_hits::cpu0.data 48827 # number of ReadReq hits system.cpu0.dcache.ReadReq_hits::total 48827 # number of ReadReq hits system.cpu0.dcache.WriteReq_hits::cpu0.data 24780 # number of WriteReq hits @@ -250,16 +250,16 @@ system.cpu0.dcache.demand_misses::cpu0.data 353 # system.cpu0.dcache.demand_misses::total 353 # number of demand (read+write) misses system.cpu0.dcache.overall_misses::cpu0.data 353 # number of overall misses system.cpu0.dcache.overall_misses::total 353 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 4582500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 4582500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 6978000 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 6978000 # number of WriteReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 4586981 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 4586981 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 6974000 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 6974000 # number of WriteReq miss cycles system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 360500 # number of SwapReq miss cycles system.cpu0.dcache.SwapReq_miss_latency::total 360500 # number of SwapReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 11560500 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 11560500 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 11560500 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 11560500 # number of overall miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 11560981 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 11560981 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 11560981 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 11560981 # number of overall miss cycles system.cpu0.dcache.ReadReq_accesses::cpu0.data 48997 # number of ReadReq accesses(hits+misses) system.cpu0.dcache.ReadReq_accesses::total 48997 # number of ReadReq accesses(hits+misses) system.cpu0.dcache.WriteReq_accesses::cpu0.data 24963 # number of WriteReq accesses(hits+misses) @@ -280,16 +280,16 @@ system.cpu0.dcache.demand_miss_rate::cpu0.data 0.004773 system.cpu0.dcache.demand_miss_rate::total 0.004773 # miss rate for demand accesses system.cpu0.dcache.overall_miss_rate::cpu0.data 0.004773 # miss rate for overall accesses system.cpu0.dcache.overall_miss_rate::total 0.004773 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 26955.882353 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 26955.882353 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38131.147541 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 38131.147541 # average WriteReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 26982.241176 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 26982.241176 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38109.289617 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 38109.289617 # average WriteReq miss latency system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 13865.384615 # average SwapReq miss latency system.cpu0.dcache.SwapReq_avg_miss_latency::total 13865.384615 # average SwapReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 32749.291785 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 32749.291785 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 32749.291785 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 32749.291785 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 32750.654391 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 32750.654391 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 32750.654391 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 32750.654391 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -310,16 +310,16 @@ system.cpu0.dcache.demand_mshr_misses::cpu0.data 353 system.cpu0.dcache.demand_mshr_misses::total 353 # number of demand (read+write) MSHR misses system.cpu0.dcache.overall_mshr_misses::cpu0.data 353 # number of overall MSHR misses system.cpu0.dcache.overall_mshr_misses::total 353 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4237519 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4237519 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6612000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6612000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4237019 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4237019 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6608000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6608000 # number of WriteReq MSHR miss cycles system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 308500 # number of SwapReq MSHR miss cycles system.cpu0.dcache.SwapReq_mshr_miss_latency::total 308500 # number of SwapReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 10849519 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 10849519 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10849519 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 10849519 # number of overall MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 10845019 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 10845019 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10845019 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 10845019 # number of overall MSHR miss cycles system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.003470 # mshr miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.003470 # mshr miss rate for ReadReq accesses system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.007331 # mshr miss rate for WriteReq accesses @@ -330,84 +330,84 @@ system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.004773 system.cpu0.dcache.demand_mshr_miss_rate::total 0.004773 # mshr miss rate for demand accesses system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.004773 # mshr miss rate for overall accesses system.cpu0.dcache.overall_mshr_miss_rate::total 0.004773 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 24926.582353 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 24926.582353 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 36131.147541 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 36131.147541 # average WriteReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 24923.641176 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 24923.641176 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 36109.289617 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 36109.289617 # average WriteReq mshr miss latency system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 11865.384615 # average SwapReq mshr miss latency system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 11865.384615 # average SwapReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 30735.181303 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 30735.181303 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 30735.181303 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 30735.181303 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 30722.433428 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 30722.433428 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 30722.433428 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 30722.433428 # average overall mshr miss latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.numCycles 525587 # number of cpu cycles simulated +system.cpu1.numCycles 525588 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 173389 # Number of instructions committed -system.cpu1.committedOps 173389 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 107707 # Number of integer alu accesses +system.cpu1.committedInsts 163471 # Number of instructions committed +system.cpu1.committedOps 163471 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 111731 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu1.num_func_calls 637 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 36848 # number of instructions that are conditional controls -system.cpu1.num_int_insts 107707 # number of integer instructions +system.cpu1.num_conditional_control_insts 29880 # number of instructions that are conditional controls +system.cpu1.num_int_insts 111731 # number of integer instructions system.cpu1.num_fp_insts 0 # number of float instructions -system.cpu1.num_int_register_reads 245634 # number of times the integer registers were read -system.cpu1.num_int_register_writes 91167 # number of times the integer registers were written +system.cpu1.num_int_register_reads 289610 # number of times the integer registers were read +system.cpu1.num_int_register_writes 111151 # number of times the integer registers were written system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu1.num_mem_refs 47028 # number of memory refs -system.cpu1.num_load_insts 39502 # Number of load instructions -system.cpu1.num_store_insts 7526 # Number of store instructions -system.cpu1.num_idle_cycles 69346.001736 # Number of idle cycles -system.cpu1.num_busy_cycles 456240.998264 # Number of busy cycles -system.cpu1.not_idle_fraction 0.868060 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.131940 # Percentage of idle cycles -system.cpu1.icache.replacements 280 # number of replacements -system.cpu1.icache.tagsinuse 70.017443 # Cycle average of tags in use -system.cpu1.icache.total_refs 173056 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 366 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 472.830601 # Average number of references to valid blocks. -system.cpu1.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 70.017443 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.136753 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.136753 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 173056 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 173056 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 173056 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 173056 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 173056 # number of overall hits -system.cpu1.icache.overall_hits::total 173056 # number of overall hits +system.cpu1.num_mem_refs 58020 # number of memory refs +system.cpu1.num_load_insts 41540 # Number of load instructions +system.cpu1.num_store_insts 16480 # Number of store instructions +system.cpu1.num_idle_cycles 69347.869793 # Number of idle cycles +system.cpu1.num_busy_cycles 456240.130207 # Number of busy cycles +system.cpu1.not_idle_fraction 0.868057 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.131943 # Percentage of idle cycles +system.cpu1.icache.tags.replacements 280 # number of replacements +system.cpu1.icache.tags.tagsinuse 70.017506 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 163138 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 366 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 445.732240 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 70.017506 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.136753 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.136753 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 163138 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 163138 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 163138 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 163138 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 163138 # number of overall hits +system.cpu1.icache.overall_hits::total 163138 # number of overall hits system.cpu1.icache.ReadReq_misses::cpu1.inst 366 # number of ReadReq misses system.cpu1.icache.ReadReq_misses::total 366 # number of ReadReq misses system.cpu1.icache.demand_misses::cpu1.inst 366 # number of demand (read+write) misses system.cpu1.icache.demand_misses::total 366 # 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number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 173422 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 173422 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.002110 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.002110 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.002110 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.002110 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.002110 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.002110 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 20606.557377 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 20606.557377 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 20606.557377 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 20606.557377 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 20606.557377 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 20606.557377 # average overall miss latency +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7546988 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 7546988 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 7546988 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 7546988 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 7546988 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 7546988 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 163504 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 163504 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 163504 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 163504 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 163504 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 163504 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.002238 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.002238 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.002238 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.002238 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.002238 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.002238 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 20620.185792 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 20620.185792 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 20620.185792 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 20620.185792 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 20620.185792 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 20620.185792 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -422,94 +422,94 @@ system.cpu1.icache.demand_mshr_misses::cpu1.inst 366 system.cpu1.icache.demand_mshr_misses::total 366 # number of demand (read+write) MSHR misses system.cpu1.icache.overall_mshr_misses::cpu1.inst 366 # number of overall MSHR misses system.cpu1.icache.overall_mshr_misses::total 366 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 6806511 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 6806511 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 6806511 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 6806511 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 6806511 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 6806511 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.002110 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.002110 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.002110 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.002110 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.002110 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.002110 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 18597.024590 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 18597.024590 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 18597.024590 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 18597.024590 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 18597.024590 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 18597.024590 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 6808012 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 6808012 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 6808012 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 6808012 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 6808012 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 6808012 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.002238 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.002238 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.002238 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.002238 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.002238 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.002238 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 18601.125683 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 18601.125683 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 18601.125683 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 18601.125683 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 18601.125683 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 18601.125683 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.replacements 0 # number of replacements -system.cpu1.dcache.tagsinuse 27.692937 # Cycle average of tags in use -system.cpu1.dcache.total_refs 17380 # Total number of references to valid blocks. -system.cpu1.dcache.sampled_refs 30 # Sample count of references to valid blocks. -system.cpu1.dcache.avg_refs 579.333333 # Average number of references to valid blocks. -system.cpu1.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::cpu1.data 27.692937 # Average occupied blocks per requestor -system.cpu1.dcache.occ_percent::cpu1.data 0.054088 # Average percentage of cache occupancy -system.cpu1.dcache.occ_percent::total 0.054088 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::cpu1.data 39322 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 39322 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 7334 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 7334 # number of WriteReq hits -system.cpu1.dcache.SwapReq_hits::cpu1.data 19 # number of SwapReq hits -system.cpu1.dcache.SwapReq_hits::total 19 # number of SwapReq hits -system.cpu1.dcache.demand_hits::cpu1.data 46656 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 46656 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 46656 # number of overall hits -system.cpu1.dcache.overall_hits::total 46656 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 172 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 172 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 106 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 106 # number of WriteReq misses -system.cpu1.dcache.SwapReq_misses::cpu1.data 65 # number of SwapReq misses -system.cpu1.dcache.SwapReq_misses::total 65 # number of SwapReq misses -system.cpu1.dcache.demand_misses::cpu1.data 278 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 278 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 278 # number of overall misses -system.cpu1.dcache.overall_misses::total 278 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 3331000 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 3331000 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2174000 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 2174000 # number of WriteReq miss cycles -system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 282000 # number of SwapReq miss cycles -system.cpu1.dcache.SwapReq_miss_latency::total 282000 # number of SwapReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 5505000 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 5505000 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 5505000 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 5505000 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 39494 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 39494 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 7440 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 7440 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SwapReq_accesses::cpu1.data 84 # number of SwapReq accesses(hits+misses) -system.cpu1.dcache.SwapReq_accesses::total 84 # number of SwapReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 46934 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 46934 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 46934 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 46934 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.004355 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.004355 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.014247 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.014247 # miss rate for WriteReq accesses -system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.773810 # miss rate for SwapReq accesses -system.cpu1.dcache.SwapReq_miss_rate::total 0.773810 # miss rate for SwapReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.005923 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.005923 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.005923 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.005923 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 19366.279070 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 19366.279070 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 20509.433962 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 20509.433962 # average WriteReq miss latency -system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 4338.461538 # average SwapReq miss latency -system.cpu1.dcache.SwapReq_avg_miss_latency::total 4338.461538 # average SwapReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 19802.158273 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 19802.158273 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 19802.158273 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 19802.158273 # average overall miss latency +system.cpu1.dcache.tags.replacements 0 # number of replacements +system.cpu1.dcache.tags.tagsinuse 27.720196 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 35348 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 30 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 1178.266667 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 27.720196 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.054141 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.054141 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::cpu1.data 41378 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 41378 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 16307 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 16307 # number of WriteReq hits +system.cpu1.dcache.SwapReq_hits::cpu1.data 11 # number of SwapReq hits +system.cpu1.dcache.SwapReq_hits::total 11 # number of SwapReq hits +system.cpu1.dcache.demand_hits::cpu1.data 57685 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 57685 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 57685 # number of overall hits +system.cpu1.dcache.overall_hits::total 57685 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 154 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 154 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 109 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 109 # number of WriteReq misses +system.cpu1.dcache.SwapReq_misses::cpu1.data 51 # number of SwapReq misses +system.cpu1.dcache.SwapReq_misses::total 51 # number of SwapReq misses +system.cpu1.dcache.demand_misses::cpu1.data 263 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 263 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 263 # number of overall misses +system.cpu1.dcache.overall_misses::total 263 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2495483 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 2495483 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 1980000 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 1980000 # number of WriteReq miss cycles +system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 209500 # number of SwapReq miss cycles +system.cpu1.dcache.SwapReq_miss_latency::total 209500 # number of SwapReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 4475483 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 4475483 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 4475483 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 4475483 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 41532 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 41532 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 16416 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 16416 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SwapReq_accesses::cpu1.data 62 # number of SwapReq accesses(hits+misses) +system.cpu1.dcache.SwapReq_accesses::total 62 # number of SwapReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 57948 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 57948 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 57948 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 57948 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.003708 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.003708 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.006640 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.006640 # miss rate for WriteReq accesses +system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.822581 # miss rate for SwapReq accesses +system.cpu1.dcache.SwapReq_miss_rate::total 0.822581 # miss rate for SwapReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.004539 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.004539 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.004539 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.004539 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 16204.435065 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 16204.435065 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18165.137615 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 18165.137615 # average WriteReq miss latency +system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 4107.843137 # average SwapReq miss latency +system.cpu1.dcache.SwapReq_avg_miss_latency::total 4107.843137 # average SwapReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 17017.045627 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 17017.045627 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 17017.045627 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 17017.045627 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -518,114 +518,114 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 172 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 172 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 106 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 106 # number of WriteReq MSHR misses -system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 65 # number of SwapReq MSHR misses -system.cpu1.dcache.SwapReq_mshr_misses::total 65 # number of SwapReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 278 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 278 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 278 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 278 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2972539 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2972539 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1962000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1962000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 152000 # number of SwapReq MSHR miss cycles -system.cpu1.dcache.SwapReq_mshr_miss_latency::total 152000 # number of SwapReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4934539 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 4934539 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4934539 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 4934539 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.004355 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.004355 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.014247 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.014247 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.773810 # mshr miss rate for SwapReq accesses -system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.773810 # mshr miss rate for SwapReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.005923 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.005923 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.005923 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.005923 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 17282.203488 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 17282.203488 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 18509.433962 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 18509.433962 # average WriteReq mshr miss latency -system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 2338.461538 # average SwapReq mshr miss latency -system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 2338.461538 # average SwapReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17750.140288 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17750.140288 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17750.140288 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17750.140288 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 154 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 154 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 109 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 109 # number of WriteReq MSHR misses +system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 51 # number of SwapReq MSHR misses +system.cpu1.dcache.SwapReq_mshr_misses::total 51 # number of SwapReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 263 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 263 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 263 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 263 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2170517 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2170517 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1762000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1762000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 107500 # number of SwapReq MSHR miss cycles +system.cpu1.dcache.SwapReq_mshr_miss_latency::total 107500 # number of SwapReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3932517 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 3932517 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 3932517 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 3932517 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.003708 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.003708 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.006640 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.006640 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.822581 # mshr miss rate for SwapReq accesses +system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.822581 # mshr miss rate for SwapReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.004539 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.004539 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.004539 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.004539 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14094.266234 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14094.266234 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16165.137615 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16165.137615 # average WriteReq mshr miss latency +system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 2107.843137 # average SwapReq mshr miss latency +system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 2107.843137 # average SwapReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 14952.536122 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 14952.536122 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 14952.536122 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 14952.536122 # average overall mshr miss latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.numCycles 525587 # number of cpu cycles simulated +system.cpu2.numCycles 525588 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.committedInsts 164870 # Number of instructions committed -system.cpu2.committedOps 164870 # Number of ops (including micro ops) committed -system.cpu2.num_int_alu_accesses 112982 # Number of integer alu accesses +system.cpu2.committedInsts 164866 # Number of instructions committed +system.cpu2.committedOps 164866 # Number of ops (including micro ops) committed +system.cpu2.num_int_alu_accesses 112988 # Number of integer alu accesses system.cpu2.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu2.num_func_calls 637 # number of times a function call or return occured -system.cpu2.num_conditional_control_insts 29953 # number of instructions that are conditional controls -system.cpu2.num_int_insts 112982 # number of integer instructions +system.cpu2.num_conditional_control_insts 29949 # number of instructions that are conditional controls +system.cpu2.num_int_insts 112988 # number of integer instructions system.cpu2.num_fp_insts 0 # number of float instructions -system.cpu2.num_int_register_reads 294323 # number of times the integer registers were read -system.cpu2.num_int_register_writes 112883 # number of times the integer registers were written +system.cpu2.num_int_register_reads 294363 # number of times the integer registers were read +system.cpu2.num_int_register_writes 112900 # number of times the integer registers were written system.cpu2.num_fp_register_reads 0 # number of times the floating registers were read system.cpu2.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu2.num_mem_refs 59198 # number of memory refs -system.cpu2.num_load_insts 42166 # Number of load instructions -system.cpu2.num_store_insts 17032 # Number of store instructions -system.cpu2.num_idle_cycles 69603.001735 # Number of idle cycles -system.cpu2.num_busy_cycles 455983.998265 # Number of busy cycles -system.cpu2.not_idle_fraction 0.867571 # Percentage of non-idle cycles -system.cpu2.idle_fraction 0.132429 # Percentage of idle cycles -system.cpu2.icache.replacements 280 # number of replacements -system.cpu2.icache.tagsinuse 67.624903 # Cycle average of tags in use -system.cpu2.icache.total_refs 164537 # Total number of references to valid blocks. -system.cpu2.icache.sampled_refs 366 # Sample count of references to valid blocks. -system.cpu2.icache.avg_refs 449.554645 # Average number of references to valid blocks. -system.cpu2.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.icache.occ_blocks::cpu2.inst 67.624903 # Average occupied blocks per requestor -system.cpu2.icache.occ_percent::cpu2.inst 0.132080 # Average percentage of cache occupancy -system.cpu2.icache.occ_percent::total 0.132080 # Average percentage of cache occupancy -system.cpu2.icache.ReadReq_hits::cpu2.inst 164537 # number of ReadReq hits -system.cpu2.icache.ReadReq_hits::total 164537 # number of ReadReq hits -system.cpu2.icache.demand_hits::cpu2.inst 164537 # number of demand (read+write) hits -system.cpu2.icache.demand_hits::total 164537 # number of demand (read+write) hits -system.cpu2.icache.overall_hits::cpu2.inst 164537 # number of overall hits -system.cpu2.icache.overall_hits::total 164537 # number of overall hits +system.cpu2.num_mem_refs 59208 # number of memory refs +system.cpu2.num_load_insts 42171 # Number of load instructions +system.cpu2.num_store_insts 17037 # Number of store instructions +system.cpu2.num_idle_cycles 69604.869303 # Number of idle cycles +system.cpu2.num_busy_cycles 455983.130697 # Number of busy cycles +system.cpu2.not_idle_fraction 0.867568 # Percentage of non-idle cycles +system.cpu2.idle_fraction 0.132432 # Percentage of idle cycles +system.cpu2.icache.tags.replacements 280 # number of replacements +system.cpu2.icache.tags.tagsinuse 67.624969 # Cycle average of tags in use +system.cpu2.icache.tags.total_refs 164533 # Total number of references to valid blocks. +system.cpu2.icache.tags.sampled_refs 366 # Sample count of references to valid blocks. +system.cpu2.icache.tags.avg_refs 449.543716 # Average number of references to valid blocks. +system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu2.icache.tags.occ_blocks::cpu2.inst 67.624969 # Average occupied blocks per requestor +system.cpu2.icache.tags.occ_percent::cpu2.inst 0.132080 # Average percentage of cache occupancy +system.cpu2.icache.tags.occ_percent::total 0.132080 # Average percentage of cache occupancy +system.cpu2.icache.ReadReq_hits::cpu2.inst 164533 # number of ReadReq hits +system.cpu2.icache.ReadReq_hits::total 164533 # number of ReadReq hits +system.cpu2.icache.demand_hits::cpu2.inst 164533 # number of demand (read+write) hits +system.cpu2.icache.demand_hits::total 164533 # number of demand (read+write) hits +system.cpu2.icache.overall_hits::cpu2.inst 164533 # number of overall hits +system.cpu2.icache.overall_hits::total 164533 # number of overall hits system.cpu2.icache.ReadReq_misses::cpu2.inst 366 # number of ReadReq misses system.cpu2.icache.ReadReq_misses::total 366 # number of ReadReq misses system.cpu2.icache.demand_misses::cpu2.inst 366 # number of demand (read+write) misses system.cpu2.icache.demand_misses::total 366 # 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average overall miss latency system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -736,114 +736,114 @@ system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu2.dcache.fast_writes 0 # number of fast writes performed system.cpu2.dcache.cache_copies 0 # number of cache copies performed -system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 158 # number of ReadReq MSHR misses -system.cpu2.dcache.ReadReq_mshr_misses::total 158 # number of ReadReq MSHR misses -system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 109 # number of WriteReq MSHR misses -system.cpu2.dcache.WriteReq_mshr_misses::total 109 # number of WriteReq MSHR misses -system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 52 # number of SwapReq MSHR misses -system.cpu2.dcache.SwapReq_mshr_misses::total 52 # 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number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_latency::total 3522514 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 3522514 # number of overall MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_latency::total 3522514 # number of overall MSHR miss cycles -system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003748 # mshr miss rate for ReadReq accesses -system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003748 # mshr miss rate for ReadReq accesses -system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.006424 # mshr miss rate for WriteReq accesses -system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.006424 # mshr miss rate for WriteReq accesses -system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.838710 # mshr miss rate for SwapReq accesses -system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.838710 # mshr miss rate for SwapReq accesses -system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.004516 # mshr miss rate for demand accesses -system.cpu2.dcache.demand_mshr_miss_rate::total 0.004516 # mshr miss rate for demand accesses -system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.004516 # mshr miss rate for overall accesses -system.cpu2.dcache.overall_mshr_miss_rate::total 0.004516 # mshr miss rate for overall accesses -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 11481.101266 # average ReadReq mshr miss latency -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 11481.101266 # average ReadReq mshr miss latency -system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 15674.311927 # average WriteReq mshr miss latency -system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 15674.311927 # average WriteReq mshr miss latency -system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 2115.384615 # average SwapReq mshr miss latency -system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 2115.384615 # average SwapReq mshr miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 13192.936330 # average overall mshr miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency::total 13192.936330 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 13192.936330 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency::total 13192.936330 # average overall mshr miss latency +system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 152 # number of ReadReq MSHR misses +system.cpu2.dcache.ReadReq_mshr_misses::total 152 # number of ReadReq MSHR misses +system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 110 # number of WriteReq MSHR misses +system.cpu2.dcache.WriteReq_mshr_misses::total 110 # number of WriteReq MSHR misses +system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 50 # number of SwapReq MSHR misses +system.cpu2.dcache.SwapReq_mshr_misses::total 50 # number of SwapReq MSHR misses +system.cpu2.dcache.demand_mshr_misses::cpu2.data 262 # number of demand (read+write) MSHR misses +system.cpu2.dcache.demand_mshr_misses::total 262 # number of demand (read+write) MSHR misses +system.cpu2.dcache.overall_mshr_misses::cpu2.data 262 # number of overall MSHR misses +system.cpu2.dcache.overall_mshr_misses::total 262 # number of overall MSHR misses +system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 1809519 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_latency::total 1809519 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1710500 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1710500 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 104500 # number of SwapReq MSHR miss cycles +system.cpu2.dcache.SwapReq_mshr_miss_latency::total 104500 # number of SwapReq MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 3520019 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_latency::total 3520019 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 3520019 # number of overall MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_latency::total 3520019 # number of overall MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003605 # mshr miss rate for ReadReq accesses +system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003605 # mshr miss rate for ReadReq accesses +system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.006480 # mshr miss rate for WriteReq accesses +system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.006480 # mshr miss rate for WriteReq accesses +system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.833333 # mshr miss rate for SwapReq accesses +system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.833333 # mshr miss rate for SwapReq accesses +system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.004430 # mshr miss rate for demand accesses +system.cpu2.dcache.demand_mshr_miss_rate::total 0.004430 # mshr miss rate for demand accesses +system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.004430 # mshr miss rate for overall accesses +system.cpu2.dcache.overall_mshr_miss_rate::total 0.004430 # mshr miss rate for overall accesses +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 11904.730263 # average ReadReq mshr miss latency +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 11904.730263 # average ReadReq mshr miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 15550 # average WriteReq mshr miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 15550 # average WriteReq mshr miss latency +system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 2090 # average SwapReq mshr miss latency +system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 2090 # average SwapReq mshr miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 13435.187023 # average overall mshr miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency::total 13435.187023 # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 13435.187023 # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency::total 13435.187023 # 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number of instructions that are conditional controls -system.cpu3.num_int_insts 112266 # number of integer instructions +system.cpu3.num_conditional_control_insts 38223 # number of instructions that are conditional controls +system.cpu3.num_int_insts 108218 # number of integer instructions system.cpu3.num_fp_insts 0 # number of float instructions -system.cpu3.num_int_register_reads 286233 # number of times the integer registers were read -system.cpu3.num_int_register_writes 109194 # number of times the integer registers were written +system.cpu3.num_int_register_reads 242179 # number of times the integer registers were read +system.cpu3.num_int_register_writes 89182 # number of times the integer registers were written system.cpu3.num_fp_register_reads 0 # number of times the floating registers were read system.cpu3.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu3.num_mem_refs 57176 # number of memory refs -system.cpu3.num_load_insts 41805 # Number of load instructions -system.cpu3.num_store_insts 15371 # Number of store instructions -system.cpu3.num_idle_cycles 69867.868801 # Number of idle cycles -system.cpu3.num_busy_cycles 455718.131199 # Number of busy cycles -system.cpu3.not_idle_fraction 0.867067 # Percentage of non-idle cycles -system.cpu3.idle_fraction 0.132933 # Percentage of idle cycles -system.cpu3.icache.replacements 281 # number of replacements -system.cpu3.icache.tagsinuse 65.598360 # Cycle average of tags in use -system.cpu3.icache.total_refs 166434 # Total number of references to valid blocks. -system.cpu3.icache.sampled_refs 367 # Sample count of references to valid blocks. -system.cpu3.icache.avg_refs 453.498638 # Average number of references to valid blocks. -system.cpu3.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.icache.occ_blocks::cpu3.inst 65.598360 # Average occupied blocks per requestor -system.cpu3.icache.occ_percent::cpu3.inst 0.128122 # Average percentage of cache occupancy -system.cpu3.icache.occ_percent::total 0.128122 # Average percentage of cache occupancy -system.cpu3.icache.ReadReq_hits::cpu3.inst 166434 # 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Total number of references to valid blocks. +system.cpu3.icache.tags.sampled_refs 367 # Sample count of references to valid blocks. +system.cpu3.icache.tags.avg_refs 480.441417 # Average number of references to valid blocks. +system.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu3.icache.tags.occ_blocks::cpu3.inst 65.598437 # Average occupied blocks per requestor +system.cpu3.icache.tags.occ_percent::cpu3.inst 0.128122 # Average percentage of cache occupancy +system.cpu3.icache.tags.occ_percent::total 0.128122 # Average percentage of cache occupancy +system.cpu3.icache.ReadReq_hits::cpu3.inst 176322 # number of ReadReq hits +system.cpu3.icache.ReadReq_hits::total 176322 # number of ReadReq hits +system.cpu3.icache.demand_hits::cpu3.inst 176322 # number of demand (read+write) hits +system.cpu3.icache.demand_hits::total 176322 # number of demand (read+write) hits +system.cpu3.icache.overall_hits::cpu3.inst 176322 # number of overall hits +system.cpu3.icache.overall_hits::total 176322 # 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number of overall miss cycles -system.cpu3.icache.ReadReq_accesses::cpu3.inst 166801 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.ReadReq_accesses::total 166801 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.demand_accesses::cpu3.inst 166801 # number of demand (read+write) accesses -system.cpu3.icache.demand_accesses::total 166801 # number of demand (read+write) accesses -system.cpu3.icache.overall_accesses::cpu3.inst 166801 # number of overall (read+write) accesses -system.cpu3.icache.overall_accesses::total 166801 # number of overall (read+write) accesses -system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.002200 # miss rate for ReadReq accesses -system.cpu3.icache.ReadReq_miss_rate::total 0.002200 # miss rate for ReadReq accesses -system.cpu3.icache.demand_miss_rate::cpu3.inst 0.002200 # miss rate for demand accesses -system.cpu3.icache.demand_miss_rate::total 0.002200 # miss rate for demand accesses -system.cpu3.icache.overall_miss_rate::cpu3.inst 0.002200 # miss rate for overall accesses -system.cpu3.icache.overall_miss_rate::total 0.002200 # miss rate for overall accesses -system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 14029.972752 # average ReadReq miss latency -system.cpu3.icache.ReadReq_avg_miss_latency::total 14029.972752 # average ReadReq miss latency -system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 14029.972752 # average overall miss latency -system.cpu3.icache.demand_avg_miss_latency::total 14029.972752 # average overall miss latency -system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 14029.972752 # average overall miss latency -system.cpu3.icache.overall_avg_miss_latency::total 14029.972752 # average overall miss latency +system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 5147499 # number of ReadReq miss cycles +system.cpu3.icache.ReadReq_miss_latency::total 5147499 # number of ReadReq miss cycles +system.cpu3.icache.demand_miss_latency::cpu3.inst 5147499 # number of demand (read+write) miss cycles +system.cpu3.icache.demand_miss_latency::total 5147499 # number of demand (read+write) miss cycles +system.cpu3.icache.overall_miss_latency::cpu3.inst 5147499 # number of overall miss cycles +system.cpu3.icache.overall_miss_latency::total 5147499 # number of overall miss cycles +system.cpu3.icache.ReadReq_accesses::cpu3.inst 176689 # number of ReadReq accesses(hits+misses) +system.cpu3.icache.ReadReq_accesses::total 176689 # number of ReadReq accesses(hits+misses) +system.cpu3.icache.demand_accesses::cpu3.inst 176689 # number of demand (read+write) accesses +system.cpu3.icache.demand_accesses::total 176689 # number of demand (read+write) accesses +system.cpu3.icache.overall_accesses::cpu3.inst 176689 # number of overall (read+write) accesses +system.cpu3.icache.overall_accesses::total 176689 # number of overall (read+write) accesses +system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.002077 # miss rate for ReadReq accesses +system.cpu3.icache.ReadReq_miss_rate::total 0.002077 # miss rate for ReadReq accesses +system.cpu3.icache.demand_miss_rate::cpu3.inst 0.002077 # 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number of cycles access was blocked system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -858,94 +858,94 @@ system.cpu3.icache.demand_mshr_misses::cpu3.inst 367 system.cpu3.icache.demand_mshr_misses::total 367 # number of demand (read+write) MSHR misses system.cpu3.icache.overall_mshr_misses::cpu3.inst 367 # number of overall MSHR misses system.cpu3.icache.overall_mshr_misses::total 367 # number of overall MSHR misses -system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 4414501 # number of ReadReq MSHR miss cycles -system.cpu3.icache.ReadReq_mshr_miss_latency::total 4414501 # number of ReadReq MSHR miss cycles -system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 4414501 # number of demand (read+write) MSHR miss cycles -system.cpu3.icache.demand_mshr_miss_latency::total 4414501 # number of demand (read+write) MSHR miss cycles -system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 4414501 # number of overall MSHR miss cycles -system.cpu3.icache.overall_mshr_miss_latency::total 4414501 # number of overall MSHR miss cycles -system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.002200 # mshr miss rate for ReadReq accesses -system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.002200 # mshr miss rate for ReadReq accesses -system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.002200 # mshr miss rate for demand accesses -system.cpu3.icache.demand_mshr_miss_rate::total 0.002200 # mshr miss rate for demand accesses -system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.002200 # mshr miss rate for overall accesses -system.cpu3.icache.overall_mshr_miss_rate::total 0.002200 # mshr miss rate for overall accesses -system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12028.613079 # average ReadReq mshr miss latency -system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 12028.613079 # average ReadReq mshr miss latency -system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 12028.613079 # average overall mshr miss latency -system.cpu3.icache.demand_avg_mshr_miss_latency::total 12028.613079 # average overall mshr miss latency -system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 12028.613079 # average overall mshr miss latency -system.cpu3.icache.overall_avg_mshr_miss_latency::total 12028.613079 # average overall mshr miss latency +system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 4412501 # number of ReadReq MSHR miss cycles +system.cpu3.icache.ReadReq_mshr_miss_latency::total 4412501 # number of ReadReq MSHR miss cycles +system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 4412501 # number of demand (read+write) MSHR miss cycles +system.cpu3.icache.demand_mshr_miss_latency::total 4412501 # number of demand (read+write) MSHR miss cycles +system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 4412501 # number of overall MSHR miss cycles +system.cpu3.icache.overall_mshr_miss_latency::total 4412501 # number of overall MSHR miss cycles +system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.002077 # mshr miss rate for ReadReq accesses +system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.002077 # mshr miss rate for ReadReq accesses +system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.002077 # mshr miss rate for demand accesses +system.cpu3.icache.demand_mshr_miss_rate::total 0.002077 # mshr miss rate for demand accesses +system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.002077 # mshr miss rate for overall accesses +system.cpu3.icache.overall_mshr_miss_rate::total 0.002077 # mshr miss rate for overall accesses +system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12023.163488 # average ReadReq mshr miss latency +system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 12023.163488 # average ReadReq mshr miss latency +system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 12023.163488 # average overall mshr miss latency +system.cpu3.icache.demand_avg_mshr_miss_latency::total 12023.163488 # average overall mshr miss latency +system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 12023.163488 # average overall mshr miss latency +system.cpu3.icache.overall_avg_mshr_miss_latency::total 12023.163488 # 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number of WriteReq hits -system.cpu3.dcache.WriteReq_hits::total 15196 # number of WriteReq hits -system.cpu3.dcache.SwapReq_hits::cpu3.data 11 # number of SwapReq hits -system.cpu3.dcache.SwapReq_hits::total 11 # number of SwapReq hits -system.cpu3.dcache.demand_hits::cpu3.data 56834 # number of demand (read+write) hits -system.cpu3.dcache.demand_hits::total 56834 # number of demand (read+write) hits -system.cpu3.dcache.overall_hits::cpu3.data 56834 # number of overall hits -system.cpu3.dcache.overall_hits::total 56834 # number of overall hits -system.cpu3.dcache.ReadReq_misses::cpu3.data 159 # number of ReadReq misses -system.cpu3.dcache.ReadReq_misses::total 159 # number of ReadReq misses -system.cpu3.dcache.WriteReq_misses::cpu3.data 109 # number of WriteReq misses -system.cpu3.dcache.WriteReq_misses::total 109 # number of WriteReq misses -system.cpu3.dcache.SwapReq_misses::cpu3.data 53 # number of SwapReq misses -system.cpu3.dcache.SwapReq_misses::total 53 # number of SwapReq misses -system.cpu3.dcache.demand_misses::cpu3.data 268 # number of demand (read+write) misses -system.cpu3.dcache.demand_misses::total 268 # number of demand (read+write) misses -system.cpu3.dcache.overall_misses::cpu3.data 268 # number of overall misses -system.cpu3.dcache.overall_misses::total 268 # number of overall misses -system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 2247500 # number of ReadReq miss cycles -system.cpu3.dcache.ReadReq_miss_latency::total 2247500 # number of ReadReq miss cycles -system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 1908500 # number of WriteReq miss cycles -system.cpu3.dcache.WriteReq_miss_latency::total 1908500 # number of WriteReq miss cycles -system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 217500 # number of SwapReq miss cycles -system.cpu3.dcache.SwapReq_miss_latency::total 217500 # number of SwapReq miss cycles -system.cpu3.dcache.demand_miss_latency::cpu3.data 4156000 # number of demand (read+write) miss cycles -system.cpu3.dcache.demand_miss_latency::total 4156000 # number of demand (read+write) miss cycles -system.cpu3.dcache.overall_miss_latency::cpu3.data 4156000 # number of overall miss cycles -system.cpu3.dcache.overall_miss_latency::total 4156000 # number of overall miss cycles -system.cpu3.dcache.ReadReq_accesses::cpu3.data 41797 # number of ReadReq accesses(hits+misses) -system.cpu3.dcache.ReadReq_accesses::total 41797 # number of ReadReq accesses(hits+misses) -system.cpu3.dcache.WriteReq_accesses::cpu3.data 15305 # number of WriteReq accesses(hits+misses) -system.cpu3.dcache.WriteReq_accesses::total 15305 # number of WriteReq accesses(hits+misses) -system.cpu3.dcache.SwapReq_accesses::cpu3.data 64 # number of SwapReq accesses(hits+misses) -system.cpu3.dcache.SwapReq_accesses::total 64 # number of SwapReq accesses(hits+misses) -system.cpu3.dcache.demand_accesses::cpu3.data 57102 # number of demand (read+write) accesses -system.cpu3.dcache.demand_accesses::total 57102 # number of demand (read+write) accesses -system.cpu3.dcache.overall_accesses::cpu3.data 57102 # number of overall (read+write) accesses -system.cpu3.dcache.overall_accesses::total 57102 # number of overall (read+write) accesses -system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.003804 # miss rate for ReadReq accesses -system.cpu3.dcache.ReadReq_miss_rate::total 0.003804 # miss rate for ReadReq accesses -system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.007122 # miss rate for WriteReq accesses -system.cpu3.dcache.WriteReq_miss_rate::total 0.007122 # miss rate for WriteReq accesses -system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.828125 # miss rate for SwapReq accesses -system.cpu3.dcache.SwapReq_miss_rate::total 0.828125 # miss rate for SwapReq accesses -system.cpu3.dcache.demand_miss_rate::cpu3.data 0.004693 # miss rate for demand accesses -system.cpu3.dcache.demand_miss_rate::total 0.004693 # miss rate for demand accesses -system.cpu3.dcache.overall_miss_rate::cpu3.data 0.004693 # miss rate for overall accesses -system.cpu3.dcache.overall_miss_rate::total 0.004693 # miss rate for overall accesses -system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 14135.220126 # average ReadReq miss latency -system.cpu3.dcache.ReadReq_avg_miss_latency::total 14135.220126 # average ReadReq miss latency -system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 17509.174312 # average WriteReq miss latency -system.cpu3.dcache.WriteReq_avg_miss_latency::total 17509.174312 # average WriteReq miss latency -system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 4103.773585 # average SwapReq miss latency -system.cpu3.dcache.SwapReq_avg_miss_latency::total 4103.773585 # average SwapReq miss latency -system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 15507.462687 # average overall miss latency -system.cpu3.dcache.demand_avg_miss_latency::total 15507.462687 # average overall miss latency -system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 15507.462687 # average overall miss latency -system.cpu3.dcache.overall_avg_miss_latency::total 15507.462687 # average overall miss latency +system.cpu3.dcache.tags.replacements 0 # number of replacements +system.cpu3.dcache.tags.tagsinuse 25.915086 # Cycle average of tags in use +system.cpu3.dcache.tags.total_refs 15020 # Total number of references to valid blocks. +system.cpu3.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks. +system.cpu3.dcache.tags.avg_refs 517.931034 # Average number of references to valid blocks. +system.cpu3.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu3.dcache.tags.occ_blocks::cpu3.data 25.915086 # Average occupied blocks per requestor +system.cpu3.dcache.tags.occ_percent::cpu3.data 0.050615 # Average percentage of cache occupancy +system.cpu3.dcache.tags.occ_percent::total 0.050615 # Average percentage of cache occupancy +system.cpu3.dcache.ReadReq_hits::cpu3.data 39563 # number of ReadReq hits +system.cpu3.dcache.ReadReq_hits::total 39563 # number of ReadReq hits +system.cpu3.dcache.WriteReq_hits::cpu3.data 6216 # number of WriteReq hits +system.cpu3.dcache.WriteReq_hits::total 6216 # number of WriteReq hits +system.cpu3.dcache.SwapReq_hits::cpu3.data 19 # number of SwapReq hits +system.cpu3.dcache.SwapReq_hits::total 19 # number of SwapReq hits +system.cpu3.dcache.demand_hits::cpu3.data 45779 # number of demand (read+write) hits +system.cpu3.dcache.demand_hits::total 45779 # number of demand (read+write) hits +system.cpu3.dcache.overall_hits::cpu3.data 45779 # number of overall hits +system.cpu3.dcache.overall_hits::total 45779 # number of overall hits +system.cpu3.dcache.ReadReq_misses::cpu3.data 183 # number of ReadReq misses +system.cpu3.dcache.ReadReq_misses::total 183 # number of ReadReq misses +system.cpu3.dcache.WriteReq_misses::cpu3.data 105 # number of WriteReq misses +system.cpu3.dcache.WriteReq_misses::total 105 # number of WriteReq misses +system.cpu3.dcache.SwapReq_misses::cpu3.data 69 # number of SwapReq misses +system.cpu3.dcache.SwapReq_misses::total 69 # number of SwapReq misses +system.cpu3.dcache.demand_misses::cpu3.data 288 # number of demand (read+write) misses +system.cpu3.dcache.demand_misses::total 288 # number of demand (read+write) misses +system.cpu3.dcache.overall_misses::cpu3.data 288 # number of overall misses +system.cpu3.dcache.overall_misses::total 288 # number of overall misses +system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 3156473 # number of ReadReq miss cycles +system.cpu3.dcache.ReadReq_miss_latency::total 3156473 # number of ReadReq miss cycles +system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 2098500 # number of WriteReq miss cycles +system.cpu3.dcache.WriteReq_miss_latency::total 2098500 # number of WriteReq miss cycles +system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 280000 # number of SwapReq miss cycles +system.cpu3.dcache.SwapReq_miss_latency::total 280000 # number of SwapReq miss cycles +system.cpu3.dcache.demand_miss_latency::cpu3.data 5254973 # number of demand (read+write) miss cycles +system.cpu3.dcache.demand_miss_latency::total 5254973 # number of demand (read+write) miss cycles +system.cpu3.dcache.overall_miss_latency::cpu3.data 5254973 # number of overall miss cycles +system.cpu3.dcache.overall_miss_latency::total 5254973 # number of overall miss cycles +system.cpu3.dcache.ReadReq_accesses::cpu3.data 39746 # number of ReadReq accesses(hits+misses) +system.cpu3.dcache.ReadReq_accesses::total 39746 # number of ReadReq accesses(hits+misses) +system.cpu3.dcache.WriteReq_accesses::cpu3.data 6321 # number of WriteReq accesses(hits+misses) +system.cpu3.dcache.WriteReq_accesses::total 6321 # number of WriteReq accesses(hits+misses) +system.cpu3.dcache.SwapReq_accesses::cpu3.data 88 # number of SwapReq accesses(hits+misses) +system.cpu3.dcache.SwapReq_accesses::total 88 # number of SwapReq accesses(hits+misses) +system.cpu3.dcache.demand_accesses::cpu3.data 46067 # number of demand (read+write) accesses +system.cpu3.dcache.demand_accesses::total 46067 # number of demand (read+write) accesses +system.cpu3.dcache.overall_accesses::cpu3.data 46067 # number of overall (read+write) accesses +system.cpu3.dcache.overall_accesses::total 46067 # number of overall (read+write) accesses +system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.004604 # miss rate for ReadReq accesses +system.cpu3.dcache.ReadReq_miss_rate::total 0.004604 # miss rate for ReadReq accesses +system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.016611 # miss rate for WriteReq accesses +system.cpu3.dcache.WriteReq_miss_rate::total 0.016611 # miss rate for WriteReq accesses +system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.784091 # miss rate for SwapReq accesses +system.cpu3.dcache.SwapReq_miss_rate::total 0.784091 # miss rate for SwapReq accesses +system.cpu3.dcache.demand_miss_rate::cpu3.data 0.006252 # miss rate for demand accesses +system.cpu3.dcache.demand_miss_rate::total 0.006252 # miss rate for demand accesses +system.cpu3.dcache.overall_miss_rate::cpu3.data 0.006252 # miss rate for overall accesses +system.cpu3.dcache.overall_miss_rate::total 0.006252 # miss rate for overall accesses +system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 17248.486339 # average ReadReq miss latency +system.cpu3.dcache.ReadReq_avg_miss_latency::total 17248.486339 # average ReadReq miss latency +system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 19985.714286 # average WriteReq miss latency +system.cpu3.dcache.WriteReq_avg_miss_latency::total 19985.714286 # average WriteReq miss latency +system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 4057.971014 # average SwapReq miss latency +system.cpu3.dcache.SwapReq_avg_miss_latency::total 4057.971014 # average SwapReq miss latency +system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 18246.434028 # average overall miss latency +system.cpu3.dcache.demand_avg_miss_latency::total 18246.434028 # average overall miss latency +system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 18246.434028 # average overall miss latency +system.cpu3.dcache.overall_avg_miss_latency::total 18246.434028 # average overall miss latency system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -954,72 +954,72 @@ system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu3.dcache.fast_writes 0 # number of fast writes performed system.cpu3.dcache.cache_copies 0 # number of cache copies performed -system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 159 # number of ReadReq MSHR misses -system.cpu3.dcache.ReadReq_mshr_misses::total 159 # number of ReadReq MSHR misses -system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 109 # number of WriteReq MSHR misses -system.cpu3.dcache.WriteReq_mshr_misses::total 109 # number of WriteReq MSHR misses -system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 53 # number of SwapReq MSHR misses -system.cpu3.dcache.SwapReq_mshr_misses::total 53 # number of SwapReq MSHR misses -system.cpu3.dcache.demand_mshr_misses::cpu3.data 268 # number of demand (read+write) MSHR misses -system.cpu3.dcache.demand_mshr_misses::total 268 # number of demand (read+write) MSHR misses -system.cpu3.dcache.overall_mshr_misses::cpu3.data 268 # number of overall MSHR misses -system.cpu3.dcache.overall_mshr_misses::total 268 # number of overall MSHR misses -system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 1924510 # number of ReadReq MSHR miss cycles -system.cpu3.dcache.ReadReq_mshr_miss_latency::total 1924510 # number of ReadReq MSHR miss cycles -system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1690500 # number of WriteReq MSHR miss cycles -system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1690500 # number of WriteReq MSHR miss cycles -system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 111500 # number of SwapReq MSHR miss cycles -system.cpu3.dcache.SwapReq_mshr_miss_latency::total 111500 # number of SwapReq MSHR miss cycles -system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 3615010 # number of demand (read+write) MSHR miss cycles -system.cpu3.dcache.demand_mshr_miss_latency::total 3615010 # number of demand (read+write) MSHR miss cycles -system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 3615010 # number of overall MSHR miss cycles -system.cpu3.dcache.overall_mshr_miss_latency::total 3615010 # number of overall MSHR miss cycles -system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.003804 # mshr miss rate for ReadReq accesses -system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.003804 # mshr miss rate for ReadReq accesses -system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.007122 # mshr miss rate for WriteReq accesses -system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.007122 # mshr miss rate for WriteReq accesses -system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.828125 # mshr miss rate for SwapReq accesses -system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.828125 # mshr miss rate for SwapReq accesses -system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.004693 # mshr miss rate for demand accesses -system.cpu3.dcache.demand_mshr_miss_rate::total 0.004693 # mshr miss rate for demand accesses -system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.004693 # mshr miss rate for overall accesses -system.cpu3.dcache.overall_mshr_miss_rate::total 0.004693 # mshr miss rate for overall accesses -system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 12103.836478 # average ReadReq mshr miss latency -system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 12103.836478 # average ReadReq mshr miss latency -system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 15509.174312 # average WriteReq mshr miss latency -system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 15509.174312 # average WriteReq mshr miss latency -system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 2103.773585 # average SwapReq mshr miss latency -system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 2103.773585 # average SwapReq mshr miss latency -system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 13488.843284 # average overall mshr miss latency -system.cpu3.dcache.demand_avg_mshr_miss_latency::total 13488.843284 # average overall mshr miss latency -system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 13488.843284 # average overall mshr miss latency -system.cpu3.dcache.overall_avg_mshr_miss_latency::total 13488.843284 # average overall mshr miss latency +system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 183 # number of ReadReq MSHR misses +system.cpu3.dcache.ReadReq_mshr_misses::total 183 # number of ReadReq MSHR misses +system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 105 # number of WriteReq MSHR misses +system.cpu3.dcache.WriteReq_mshr_misses::total 105 # number of WriteReq MSHR misses +system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 69 # number of SwapReq MSHR misses +system.cpu3.dcache.SwapReq_mshr_misses::total 69 # number of SwapReq MSHR misses +system.cpu3.dcache.demand_mshr_misses::cpu3.data 288 # number of demand (read+write) MSHR misses +system.cpu3.dcache.demand_mshr_misses::total 288 # number of demand (read+write) MSHR misses +system.cpu3.dcache.overall_mshr_misses::cpu3.data 288 # number of overall MSHR misses +system.cpu3.dcache.overall_mshr_misses::total 288 # number of overall MSHR misses +system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 2772527 # number of ReadReq MSHR miss cycles +system.cpu3.dcache.ReadReq_mshr_miss_latency::total 2772527 # number of ReadReq MSHR miss cycles +system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1888500 # number of WriteReq MSHR miss cycles +system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1888500 # number of WriteReq MSHR miss cycles +system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 142000 # number of SwapReq MSHR miss cycles +system.cpu3.dcache.SwapReq_mshr_miss_latency::total 142000 # number of SwapReq MSHR miss cycles +system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 4661027 # number of demand (read+write) MSHR miss cycles +system.cpu3.dcache.demand_mshr_miss_latency::total 4661027 # number of demand (read+write) MSHR miss cycles +system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 4661027 # number of overall MSHR miss cycles +system.cpu3.dcache.overall_mshr_miss_latency::total 4661027 # number of overall MSHR miss cycles +system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.004604 # mshr miss rate for ReadReq accesses +system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.004604 # mshr miss rate for ReadReq accesses +system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.016611 # mshr miss rate for WriteReq accesses +system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.016611 # mshr miss rate for WriteReq accesses +system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.784091 # mshr miss rate for SwapReq accesses +system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.784091 # mshr miss rate for SwapReq accesses +system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.006252 # mshr miss rate for demand accesses +system.cpu3.dcache.demand_mshr_miss_rate::total 0.006252 # mshr miss rate for demand accesses +system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.006252 # mshr miss rate for overall accesses +system.cpu3.dcache.overall_mshr_miss_rate::total 0.006252 # mshr miss rate for overall accesses +system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 15150.420765 # average ReadReq mshr miss latency +system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 15150.420765 # average ReadReq mshr miss latency +system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 17985.714286 # average WriteReq mshr miss latency +system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 17985.714286 # average WriteReq mshr miss latency +system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 2057.971014 # average SwapReq mshr miss latency +system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 2057.971014 # average SwapReq mshr miss latency +system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 16184.121528 # average overall mshr miss latency +system.cpu3.dcache.demand_avg_mshr_miss_latency::total 16184.121528 # average overall mshr miss latency +system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 16184.121528 # average overall mshr miss latency +system.cpu3.dcache.overall_avg_mshr_miss_latency::total 16184.121528 # average overall mshr miss latency system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.replacements 0 # number of replacements -system.l2c.tagsinuse 349.045938 # Cycle average of tags in use -system.l2c.total_refs 1220 # Total number of references to valid blocks. -system.l2c.sampled_refs 429 # Sample count of references to valid blocks. -system.l2c.avg_refs 2.843823 # Average number of references to valid blocks. -system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 0.889004 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 231.790377 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 54.207937 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 51.556644 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 6.123911 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu2.inst 1.773020 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu2.data 0.843759 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu3.inst 1.030265 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu3.data 0.831019 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.000014 # 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Sample count of references to valid blocks. +system.l2c.tags.avg_refs 2.843823 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 0.889005 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 231.790437 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 54.207948 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 51.556673 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 6.123914 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.inst 1.773020 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.data 0.843760 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3.inst 1.030292 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3.data 0.831024 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.000014 # 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number of ReadReq hits @@ -1061,9 +1061,9 @@ system.l2c.ReadReq_misses::cpu3.inst 9 # nu system.l2c.ReadReq_misses::cpu3.data 2 # number of ReadReq misses system.l2c.ReadReq_misses::total 450 # number of ReadReq misses system.l2c.UpgradeReq_misses::cpu0.data 28 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 19 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 15 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::cpu2.data 15 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu3.data 15 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu3.data 19 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::total 77 # number of UpgradeReq misses system.l2c.ReadExReq_misses::cpu0.data 99 # number of ReadExReq misses system.l2c.ReadExReq_misses::cpu1.data 15 # number of ReadExReq misses @@ -1088,38 +1088,38 @@ system.l2c.overall_misses::cpu2.data 16 # nu system.l2c.overall_misses::cpu3.inst 9 # number of overall misses system.l2c.overall_misses::cpu3.data 16 # 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number of Writeback accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu0.data 30 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 19 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 15 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu2.data 15 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu3.data 15 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu3.data 19 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::total 79 # number of UpgradeReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu0.data 99 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu1.data 15 # number of ReadExReq accesses(hits+misses) @@ -1196,38 +1196,38 @@ system.l2c.overall_miss_rate::cpu2.data 0.640000 # mi system.l2c.overall_miss_rate::cpu3.inst 0.024523 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu3.data 0.640000 # miss rate for overall accesses system.l2c.overall_miss_rate::total 0.326711 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52373.684211 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52375.438596 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu0.data 52295.454545 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 52083.333333 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 52250 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2.inst 49833.333333 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2.data 52000 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 52068.181818 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 52312.500000 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2.inst 49791.666667 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2.data 51750 # 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n system.l2c.ReadReq_mshr_misses::cpu3.data 2 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::total 430 # number of ReadReq MSHR misses system.l2c.UpgradeReq_mshr_misses::cpu0.data 28 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 19 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 15 # number of UpgradeReq MSHR misses system.l2c.UpgradeReq_mshr_misses::cpu2.data 15 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu3.data 15 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu3.data 19 # number of UpgradeReq MSHR misses system.l2c.UpgradeReq_mshr_misses::total 77 # number of UpgradeReq MSHR misses system.l2c.ReadExReq_mshr_misses::cpu0.data 99 # number of ReadExReq MSHR misses system.l2c.ReadExReq_mshr_misses::cpu1.data 15 # number of ReadExReq MSHR misses @@ -1301,15 +1301,15 @@ system.l2c.ReadReq_mshr_miss_latency::cpu3.inst 320000 system.l2c.ReadReq_mshr_miss_latency::cpu3.data 80000 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::total 17223000 # number of ReadReq MSHR miss cycles system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 1120000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 764491 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 600499 # number of UpgradeReq MSHR miss cycles system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 600000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data 600000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data 763992 # number of UpgradeReq MSHR miss cycles system.l2c.UpgradeReq_mshr_miss_latency::total 3084491 # number of UpgradeReq MSHR miss cycles system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 3964000 # number of ReadExReq MSHR miss cycles system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 617500 # number of ReadExReq MSHR miss cycles system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 577500 # 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average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40236.368421 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40033.266667 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 40000 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 40000 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 40210.105263 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40058.324675 # average UpgradeReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40040.404040 # average ReadExReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 41166.666667 # average ReadExReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 41250 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 40035.642857 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 40278.161972 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 40000 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 40274.647887 # average ReadExReq mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40050.877193 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40024.242424 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40144.067797 # average overall mshr miss latency @@ -1391,8 +1391,8 @@ system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40795.454545 system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 40000 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu2.data 41166.666667 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 40000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3.data 40031.187500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 40109.263986 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.data 40000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40108.391608 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40050.877193 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40024.242424 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40144.067797 # average overall mshr miss latency @@ -1400,8 +1400,8 @@ system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40795.454545 system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 40000 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu2.data 41166.666667 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 40000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3.data 40031.187500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 40109.263986 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.data 40000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40108.391608 # average overall mshr miss latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest/stats.txt b/tests/quick/se/50.memtest/ref/alpha/linux/memtest/stats.txt index e56d497e2..0a30250cf 100644 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest/stats.txt +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest/stats.txt @@ -1,656 +1,654 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000650 # Number of seconds simulated -sim_ticks 649827000 # Number of ticks simulated -final_tick 649827000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000653 # Number of seconds simulated +sim_ticks 652606500 # Number of ticks simulated +final_tick 652606500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_tick_rate 87337651 # Simulator tick rate (ticks/s) -host_mem_usage 355516 # Number of bytes of host memory used -host_seconds 7.44 # Real time elapsed on the host -system.physmem.bytes_read::cpu0 81682 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1 82403 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2 82634 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3 80397 # Number of bytes read from this memory -system.physmem.bytes_read::cpu4 83903 # Number of bytes read from this memory -system.physmem.bytes_read::cpu5 81493 # Number of bytes read from this memory -system.physmem.bytes_read::cpu6 81053 # Number of bytes read from this memory -system.physmem.bytes_read::cpu7 80348 # Number of bytes read from this memory -system.physmem.bytes_read::total 653913 # Number of bytes read from this memory -system.physmem.bytes_written::writebacks 411392 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0 5392 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1 5164 # Number of bytes written to this memory -system.physmem.bytes_written::cpu2 5249 # Number of bytes written to this memory -system.physmem.bytes_written::cpu3 5478 # Number of bytes written to this memory -system.physmem.bytes_written::cpu4 5343 # Number of bytes written to this memory -system.physmem.bytes_written::cpu5 5429 # Number of bytes written to this memory -system.physmem.bytes_written::cpu6 5380 # Number of bytes written to this memory -system.physmem.bytes_written::cpu7 5399 # Number of bytes written to this memory -system.physmem.bytes_written::total 454226 # Number of bytes written to this memory -system.physmem.num_reads::cpu0 10933 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1 11024 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2 11066 # Number of read requests responded to by this memory +host_tick_rate 176079756 # Simulator tick rate (ticks/s) +host_mem_usage 355636 # Number of bytes of host memory used +host_seconds 3.71 # Real time elapsed on the host +system.physmem.bytes_read::cpu0 80014 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1 82049 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2 81047 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3 79011 # Number of bytes read from this memory +system.physmem.bytes_read::cpu4 80501 # Number of bytes read from this memory +system.physmem.bytes_read::cpu5 83900 # Number of bytes read from this memory +system.physmem.bytes_read::cpu6 78451 # Number of bytes read from this memory +system.physmem.bytes_read::cpu7 80299 # Number of bytes read from this memory +system.physmem.bytes_read::total 645272 # Number of bytes read from this memory +system.physmem.bytes_written::writebacks 398848 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0 5221 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1 5261 # Number of bytes written to this memory +system.physmem.bytes_written::cpu2 5379 # Number of bytes written to this memory +system.physmem.bytes_written::cpu3 5376 # Number of bytes written to this memory +system.physmem.bytes_written::cpu4 5284 # Number of bytes written to this memory +system.physmem.bytes_written::cpu5 5253 # Number of bytes written to this memory +system.physmem.bytes_written::cpu6 5355 # Number of bytes written to this memory +system.physmem.bytes_written::cpu7 5238 # Number of bytes written to this memory +system.physmem.bytes_written::total 441215 # Number of bytes written to this memory +system.physmem.num_reads::cpu0 10966 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1 11048 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2 10991 # Number of read requests responded to by this memory system.physmem.num_reads::cpu3 11034 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu4 11012 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu5 10870 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu6 10997 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu7 10859 # Number of read requests responded to by this memory -system.physmem.num_reads::total 87795 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 6428 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0 5392 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1 5164 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu2 5249 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu3 5478 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu4 5343 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu5 5429 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu6 5380 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu7 5399 # Number of write requests responded to by this memory -system.physmem.num_writes::total 49262 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0 125698070 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1 126807596 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2 127163076 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3 123720621 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu4 129115903 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu5 125407224 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu6 124730120 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu7 123645216 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1006287827 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 633079266 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0 8297593 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1 7946730 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu2 8077534 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu3 8429936 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu4 8222188 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu5 8354531 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu6 8279127 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu7 8308365 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 698995271 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 633079266 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0 133995663 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1 134754327 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2 135240610 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3 132150557 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu4 137338092 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu5 133761755 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu6 133009247 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu7 131953581 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1705283098 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 1705280021 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 84626 # Transaction distribution -system.membus.trans_dist::ReadResp 84624 # Transaction distribution -system.membus.trans_dist::WriteReq 42834 # Transaction distribution -system.membus.trans_dist::WriteResp 42832 # Transaction distribution -system.membus.trans_dist::Writeback 6428 # Transaction distribution -system.membus.trans_dist::UpgradeReq 56782 # Transaction distribution -system.membus.trans_dist::UpgradeResp 46322 # Transaction distribution -system.membus.trans_dist::ReadExReq 48493 # Transaction distribution -system.membus.trans_dist::ReadExResp 3169 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side 416110 # Packet count per connected master and slave (bytes) -system.membus.pkt_count 416110 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side 1108137 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size 1108137 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 1108137 # Total data (bytes) +system.physmem.num_reads::cpu4 11075 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu5 11072 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu6 10915 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu7 11125 # Number of read requests responded to by this memory +system.physmem.num_reads::total 88226 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 6232 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0 5221 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1 5261 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu2 5379 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu3 5376 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu4 5284 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu5 5253 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu6 5355 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu7 5238 # Number of write requests responded to by this memory +system.physmem.num_writes::total 48599 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0 122606808 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1 125725073 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2 124189692 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3 121069894 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu4 123353047 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu5 128561392 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu6 120211797 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu7 123043519 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 988761221 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 611161550 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0 8000227 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1 8061519 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu2 8242333 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu3 8237736 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu4 8096763 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu5 8049261 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu6 8205557 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu7 8026276 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 676081222 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 611161550 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0 130607035 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1 133786593 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2 132432025 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3 129307630 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu4 131449809 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu5 136610653 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu6 128417354 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu7 131069795 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1664842443 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 1664833249 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 85134 # Transaction distribution +system.membus.trans_dist::ReadResp 85128 # Transaction distribution +system.membus.trans_dist::WriteReq 42367 # Transaction distribution +system.membus.trans_dist::WriteResp 42365 # Transaction distribution +system.membus.trans_dist::Writeback 6232 # Transaction distribution +system.membus.trans_dist::UpgradeReq 57414 # Transaction distribution +system.membus.trans_dist::UpgradeResp 46744 # Transaction distribution +system.membus.trans_dist::ReadExReq 48586 # Transaction distribution +system.membus.trans_dist::ReadExResp 3092 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side 417062 # Packet count per connected master and slave (bytes) +system.membus.pkt_count 417062 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side 1086481 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size 1086481 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 1086481 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 287607668 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 44.3 # Layer utilization (%) -system.membus.respLayer0.occupancy 310731500 # Layer occupancy (ticks) -system.membus.respLayer0.utilization 47.8 # Layer utilization (%) -system.l2c.replacements 13443 # number of replacements -system.l2c.tagsinuse 785.847638 # Cycle average of tags in use -system.l2c.total_refs 148477 # Total number of references to valid blocks. -system.l2c.sampled_refs 14254 # Sample count of references to valid blocks. -system.l2c.avg_refs 10.416515 # Average number of references to valid blocks. -system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 727.764026 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0 7.053915 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1 7.581472 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu2 7.416719 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu3 7.244884 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu4 7.857651 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu5 7.082573 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu6 6.903381 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu7 6.943017 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.710707 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0 0.006889 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1 0.007404 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu2 0.007243 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu3 0.007075 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu4 0.007673 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu5 0.006917 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu6 0.006742 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu7 0.006780 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.767429 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0 10664 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1 10479 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2 10841 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu3 10758 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu4 10614 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu5 10530 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu6 10691 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu7 10867 # number of ReadReq hits -system.l2c.ReadReq_hits::total 85444 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 73993 # number of Writeback hits -system.l2c.Writeback_hits::total 73993 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0 363 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1 337 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu2 327 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu3 310 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu4 313 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu5 326 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu6 344 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu7 344 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 2664 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu0 1821 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1 1874 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu2 1837 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu3 1846 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu4 1900 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu5 1886 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu6 1867 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu7 1842 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 14873 # number of ReadExReq hits -system.l2c.demand_hits::cpu0 12485 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1 12353 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2 12678 # number of demand (read+write) hits -system.l2c.demand_hits::cpu3 12604 # number of demand (read+write) hits -system.l2c.demand_hits::cpu4 12514 # number of demand (read+write) hits -system.l2c.demand_hits::cpu5 12416 # number of demand (read+write) hits -system.l2c.demand_hits::cpu6 12558 # number of demand (read+write) hits -system.l2c.demand_hits::cpu7 12709 # number of demand (read+write) hits -system.l2c.demand_hits::total 100317 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0 12485 # number of overall hits -system.l2c.overall_hits::cpu1 12353 # number of overall hits -system.l2c.overall_hits::cpu2 12678 # number of overall hits -system.l2c.overall_hits::cpu3 12604 # number of overall hits -system.l2c.overall_hits::cpu4 12514 # number of overall hits -system.l2c.overall_hits::cpu5 12416 # number of overall hits -system.l2c.overall_hits::cpu6 12558 # number of overall hits -system.l2c.overall_hits::cpu7 12709 # number of overall hits -system.l2c.overall_hits::total 100317 # number of overall hits -system.l2c.ReadReq_misses::cpu0 745 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1 740 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2 751 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu3 714 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu4 782 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu5 720 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu6 737 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu7 688 # number of ReadReq misses -system.l2c.ReadReq_misses::total 5877 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0 1987 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1 1883 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu2 1865 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu3 1791 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu4 1907 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu5 1910 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu6 1895 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu7 1890 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 15128 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::cpu0 4230 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1 4311 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu2 4330 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu3 4249 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu4 4286 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu5 4380 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu6 4201 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu7 4403 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 34390 # number of ReadExReq misses -system.l2c.demand_misses::cpu0 4975 # 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number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu4 2220 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu5 2236 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu6 2239 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu7 2234 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 17792 # number of UpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0 6051 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1 6185 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu2 6167 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu3 6095 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu4 6186 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu5 6266 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu6 6068 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu7 6245 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 49263 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0 17460 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1 17404 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2 17759 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu3 17567 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu4 17582 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu5 17516 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu6 17496 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu7 17800 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 140584 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0 17460 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1 17404 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2 17759 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu3 17567 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu4 17582 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu5 17516 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu6 17496 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu7 17800 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 140584 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0 0.065299 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1 0.065960 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2 0.064786 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu3 0.062238 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu4 0.068621 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu5 0.064000 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu6 0.064491 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu7 0.059541 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.064355 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0 0.845532 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1 0.848198 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu2 0.850821 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu3 0.852451 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu4 0.859009 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu5 0.854204 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu6 0.846360 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu7 0.846016 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.850270 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0 0.699058 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1 0.697009 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu2 0.702124 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu3 0.697129 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu4 0.692855 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu5 0.699011 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu6 0.692320 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu7 0.705044 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.698090 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0 0.284937 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1 0.290221 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2 0.286108 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu3 0.282518 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu4 0.288249 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu5 0.291162 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu6 0.282236 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu7 0.286011 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.286427 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0 0.284937 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1 0.290221 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2 0.286108 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu3 0.282518 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu4 0.288249 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu5 0.291162 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu6 0.282236 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu7 0.286011 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.286427 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0 62204.697987 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1 61800 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2 62104.527297 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu3 61950.278711 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu4 61886.828645 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu5 61015.277778 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu6 61084.124830 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu7 61997.819767 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 61757.273949 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0 29049.068948 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1 28979.553903 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu2 30054.155496 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu3 28684.254606 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu4 29557.420031 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu5 28797.905759 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu6 29426.912929 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu7 28887.830688 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 29180.691433 # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0 53780.969031 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1 53878.334493 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu2 53936.489607 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu3 54008.590021 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu4 53944.587028 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu5 54063.242009 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu6 53966.436563 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu7 53933.794913 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 53939.444519 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0 55042.411859 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1 55038.903187 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2 55143.770911 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu3 55151.117872 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu4 55170.086819 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu5 55044.705882 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu6 55028.756582 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu7 55023.570811 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 55080.462811 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0 55042.411859 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1 55038.903187 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2 55143.770911 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu3 55151.117872 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu4 55170.086819 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu5 55044.705882 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu6 55028.756582 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu7 55023.570811 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 55080.462811 # average overall miss latency -system.l2c.blocked_cycles::no_mshrs 13397 # number of cycles access was blocked +system.membus.reqLayer0.occupancy 286485584 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 43.9 # Layer utilization (%) +system.membus.respLayer0.occupancy 311361500 # Layer occupancy (ticks) +system.membus.respLayer0.utilization 47.7 # Layer utilization (%) +system.l2c.tags.replacements 13254 # number of replacements +system.l2c.tags.tagsinuse 783.820018 # Cycle average of tags in use +system.l2c.tags.total_refs 149317 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 14065 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 10.616210 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 726.472153 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0 7.679894 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1 7.566050 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2 7.311161 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3 6.856177 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu4 7.195523 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu5 6.988954 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu6 6.739476 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu7 7.010629 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.709445 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0 0.007500 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1 0.007389 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2 0.007140 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu3 0.006695 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu4 0.007027 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu5 0.006825 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu6 0.006582 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu7 0.006846 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.765449 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0 10635 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1 10552 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2 10744 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu3 10808 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu4 10723 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu5 10748 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu6 10725 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu7 10838 # number of ReadReq hits +system.l2c.ReadReq_hits::total 85773 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 74336 # number of Writeback hits +system.l2c.Writeback_hits::total 74336 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0 332 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1 322 # 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number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu5 237965000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu6 227719000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu7 232651999 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 1863605497 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu0 279010999 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1 280419000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2 281173500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu3 271778498 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu4 280353500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu5 282697500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu6 271323500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu7 275793999 # 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number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu4 2162 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu5 2240 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu6 2270 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu7 2341 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 18051 # number of UpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0 6251 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1 6213 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu2 6226 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu3 6083 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu4 6232 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu5 6213 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu6 6177 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu7 6175 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 49570 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0 17637 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1 17507 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2 17714 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu3 17587 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu4 17682 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu5 17696 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu6 17610 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu7 17711 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 141144 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0 17637 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1 17507 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2 17714 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu3 17587 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu4 17682 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu5 17696 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu6 17610 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu7 17711 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 141144 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0 0.065958 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1 0.065699 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2 0.064763 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu3 0.060501 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu4 0.063493 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu5 0.064008 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu6 0.061926 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu7 0.060506 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.063348 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0 0.855401 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1 0.856952 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu2 0.850687 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu3 0.841540 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu4 0.846438 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu5 0.842411 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu6 0.846256 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu7 0.838531 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.847266 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0 0.691249 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1 0.700628 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu2 0.699968 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu3 0.695874 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu4 0.699775 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu5 0.708836 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu6 0.683827 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu7 0.699109 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.697418 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0 0.287577 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1 0.291026 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2 0.288021 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu3 0.280264 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu4 0.287750 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu5 0.290405 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu6 0.280068 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu7 0.283157 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.286034 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0 0.287577 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1 0.291026 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2 0.288021 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu3 0.280264 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu4 0.287750 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu5 0.290405 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu6 0.280068 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu7 0.283157 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.286034 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu0 62125.832224 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1 61843.665768 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2 62116.263441 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu3 62106.320402 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu4 62559.834938 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu5 60860.544218 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu6 61588.276836 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu7 61808.022923 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 61876.400448 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu0 27740.325866 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1 29086.314152 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu2 28488.541667 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu3 29653.723404 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu4 28261.475410 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu5 29585.585586 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu6 28866.475794 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu7 29855.068772 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 28942.134170 # average UpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0 53773.316131 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1 53878.015162 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu2 53914.410280 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu3 53993.030711 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu4 53857.486815 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu5 54033.832879 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu6 53910.748106 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu7 53892.054436 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 53906.612392 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu0 55010.055008 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1 55038.076546 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2 55110.446884 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu3 55138.668695 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu4 55100.923742 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu5 55010.215995 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu6 55012.875101 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu7 54993.818345 # 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number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu5 1910 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu6 1894 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu7 1889 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 15124 # number of UpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0 4226 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1 4305 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu2 4324 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu3 4247 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu4 4284 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu5 4378 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu6 4198 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu7 4400 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 34362 # 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number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu3 213447998 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu4 218017000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu5 218634500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu6 211504500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu7 218219499 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 1728084496 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0 406261500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1 408851000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu2 410764500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu3 410830500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu4 407460500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu5 403658000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu6 409230500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu7 404004500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 3261061000 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0 227401000 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1 218592500 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu2 221548500 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu3 231869500 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu4 226934000 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu5 230334000 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu6 226902000 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu7 228628000 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 1812209500 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0 633662500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1 627443500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu2 632313000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu3 642700000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu4 634394500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu5 633992000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu6 636132500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu7 632632500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 5073270500 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0 0.064773 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1 0.065425 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2 0.064268 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu3 0.061890 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu4 0.068006 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu5 0.063378 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu6 0.063616 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu7 0.059109 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.063797 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0 0.845106 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1 0.847748 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu2 0.850821 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu3 0.852451 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu4 0.859009 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu5 0.854204 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu6 0.845913 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu7 0.845568 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.850045 # mshr miss rate for UpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0 0.698397 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1 0.696039 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu2 0.701151 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu3 0.696801 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu4 0.692532 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu5 0.698691 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu6 0.691826 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu7 0.704564 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.697521 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0 0.284364 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1 0.289531 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2 0.285433 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu3 0.282177 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu4 0.287737 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu5 0.290649 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu6 0.281493 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu7 0.285562 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.285865 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0 0.284364 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1 0.289531 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2 0.285433 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu3 0.282177 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu4 0.287737 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu5 0.290649 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu6 0.281493 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu7 0.285562 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.285865 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0 50359.945873 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1 49936.648501 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2 50069.127517 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu3 50016.195775 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu4 49982.580645 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu5 48983.169705 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu6 49182.943604 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu7 49942.166911 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 49812.993306 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0 41052.870091 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1 41030.286929 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2 41033.512064 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3 41078.447795 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu4 41054.798112 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu5 41092.931937 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu6 41129.619852 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu7 41088.141874 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 41070.021158 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0 41702.082111 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1 41773.635308 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2 41864.361702 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3 41896.985872 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu4 41848.856209 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu5 41961.968936 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu6 41864.816579 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu7 41842.954318 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 41844.886706 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0 42990.734945 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1 42962.691010 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2 43070.230815 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3 43059.914868 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu4 43094.880411 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu5 42945.295620 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu6 42945.076142 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu7 42931.241196 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 43000.012342 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0 42990.734945 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1 42962.691010 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2 43070.230815 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3 43059.914868 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu4 43094.880411 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu5 42945.295620 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu6 42945.076142 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu7 42931.241196 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 43000.012342 # average overall mshr miss latency +system.l2c.ReadReq_mshr_misses::cpu2 736 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu3 693 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu4 721 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu5 731 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu6 703 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu7 693 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 5756 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0 1963 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1 1929 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu2 1920 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu3 1879 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu4 1830 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu5 1887 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu6 1921 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu7 1963 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 15292 # number of UpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0 4318 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1 4350 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu2 4355 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu3 4230 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu4 4356 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu5 4398 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu6 4220 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu7 4314 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 34541 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu0 5063 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1 5084 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2 5091 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu3 4923 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu4 5077 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu5 5129 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu6 4923 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu7 5007 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 40297 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0 5063 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1 5084 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2 5091 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu3 4923 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu4 5077 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu5 5129 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu6 4923 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu7 5007 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 40297 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu0 37430000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1 36700000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2 36861500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu3 34765499 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu4 36517000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu5 35579500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu6 34789500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu7 34507000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 287149999 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0 80503500 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1 79250000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu2 78828500 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu3 77220000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu4 75116000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu5 77478500 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu6 78872500 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu7 80473500 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 627742500 # number of UpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0 179980999 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1 181689000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu2 182122000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu3 177202499 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu4 181963000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu5 184511000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu6 176480500 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu7 180371999 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 1444320997 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0 217410999 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1 218389000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2 218983500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu3 211967998 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu4 218480000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu5 220090500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu6 211270000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu7 214878999 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 1731470996 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0 217410999 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1 218389000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2 218983500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu3 211967998 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu4 218480000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu5 220090500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu6 211270000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu7 214878999 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 1731470996 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0 408599000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1 409928000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu2 408199000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu3 411446500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu4 412339500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu5 409840000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu6 407063000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu7 414602500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 3282017500 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0 219448000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1 222166000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu2 226500000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu3 227574000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu4 224253000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu5 222853000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu6 225951500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu7 221581000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 1790326500 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0 628047000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1 632094000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu2 634699000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu3 639020500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu4 636592500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu5 632693000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu6 633014500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu7 636183500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 5072344000 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0 0.065431 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1 0.064990 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2 0.064067 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu3 0.060240 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu4 0.062969 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu5 0.063659 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu6 0.061489 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu7 0.060073 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.062856 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0 0.854965 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1 0.856952 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu2 0.850687 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu3 0.841092 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu4 0.846438 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu5 0.842411 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu6 0.846256 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu7 0.838531 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.847155 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0 0.690769 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1 0.700145 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu2 0.699486 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu3 0.695381 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu4 0.698973 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu5 0.707871 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu6 0.683180 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu7 0.698623 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.696813 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0 0.287067 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1 0.290398 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2 0.287400 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3 0.279923 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu4 0.287128 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu5 0.289840 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu6 0.279557 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu7 0.282706 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.285503 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0 0.287067 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1 0.290398 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2 0.287400 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3 0.279923 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu4 0.287128 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu5 0.289840 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu6 0.279557 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu7 0.282706 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.285503 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0 50241.610738 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1 50000 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2 50083.559783 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu3 50166.665224 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu4 50647.711512 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu5 48672.366621 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu6 49487.197724 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu7 49793.650794 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 49887.074183 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0 41010.443199 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1 41083.462934 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2 41056.510417 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3 41096.327834 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu4 41046.994536 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu5 41059.088500 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu6 41058.042686 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu7 40995.160469 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 41050.385823 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0 41681.565308 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1 41767.586207 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2 41819.058553 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3 41891.843735 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu4 41772.956841 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu5 41953.387904 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu6 41820.023697 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu7 41810.848169 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 41814.683912 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0 42941.141418 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1 42956.136900 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2 43013.847967 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3 43056.672354 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu4 43033.287374 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu5 42910.996296 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu6 42914.889295 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu7 42915.717795 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 42967.739435 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0 42941.141418 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1 42956.136900 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2 43013.847967 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3 43056.672354 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu4 43033.287374 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu5 42910.996296 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu6 42914.889295 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu7 42915.717795 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 42967.739435 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0 inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1 inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2 inf # average ReadReq mshr uncacheable latency @@ -681,163 +679,163 @@ system.l2c.overall_avg_mshr_uncacheable_latency::total inf system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.funcbus.throughput 0 # Throughput (bytes/s) system.funcbus.data_through_bus 0 # Total data (bytes) -system.toL2Bus.throughput 51050793519 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 365486 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 365476 # Transaction distribution -system.toL2Bus.trans_dist::ReadRespWithInvalidate 2 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 42834 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 42830 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 73993 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 28250 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 28248 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 155786 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 155781 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l1c.mem_side 118183 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l1c.mem_side 117760 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu2.l1c.mem_side 118671 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu3.l1c.mem_side 118343 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu4.l1c.mem_side 117990 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu5.l1c.mem_side 118322 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu6.l1c.mem_side 118461 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu7.l1c.mem_side 118625 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count 946355 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.l1c.mem_side 1725217 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.l1c.mem_side 1723022 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu2.l1c.mem_side 1747851 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu3.l1c.mem_side 1725043 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu4.l1c.mem_side 1729886 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu5.l1c.mem_side 1731401 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu6.l1c.mem_side 1727521 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu7.l1c.mem_side 1744371 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size 13854312 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 13854312 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 19319872 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 649780490 # Layer occupancy (ticks) +system.toL2Bus.throughput 51078499831 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 368070 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 368059 # Transaction distribution +system.toL2Bus.trans_dist::ReadRespWithInvalidate 1 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 42367 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 42365 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 74336 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 28719 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 28718 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 155928 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 155926 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l1c.mem_side 118285 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l1c.mem_side 118639 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu2.l1c.mem_side 118896 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu3.l1c.mem_side 119078 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu4.l1c.mem_side 118813 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu5.l1c.mem_side 118602 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu6.l1c.mem_side 118904 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu7.l1c.mem_side 119137 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count 950354 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.l1c.mem_side 1731443 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.l1c.mem_side 1726092 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu2.l1c.mem_side 1741657 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu3.l1c.mem_side 1748194 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu4.l1c.mem_side 1742487 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu5.l1c.mem_side 1735937 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu6.l1c.mem_side 1741406 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu7.l1c.mem_side 1745057 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size 13912273 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 13912273 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 19421888 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 652560490 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 100.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 156586979 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 157373515 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 24.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 156968437 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 158243013 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 24.2 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 157751073 # Layer occupancy (ticks) -system.toL2Bus.respLayer2.utilization 24.3 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 157263428 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 157858027 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.utilization 24.2 # Layer utilization (%) +system.toL2Bus.respLayer3.occupancy 157862988 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 24.2 # Layer utilization (%) -system.toL2Bus.respLayer4.occupancy 156564098 # Layer occupancy (ticks) -system.toL2Bus.respLayer4.utilization 24.1 # Layer utilization (%) -system.toL2Bus.respLayer5.occupancy 157250041 # Layer occupancy (ticks) +system.toL2Bus.respLayer4.occupancy 158148657 # Layer occupancy (ticks) +system.toL2Bus.respLayer4.utilization 24.2 # Layer utilization (%) +system.toL2Bus.respLayer5.occupancy 157838676 # Layer occupancy (ticks) system.toL2Bus.respLayer5.utilization 24.2 # Layer utilization (%) -system.toL2Bus.respLayer6.occupancy 157464901 # Layer occupancy (ticks) +system.toL2Bus.respLayer6.occupancy 158178516 # Layer occupancy (ticks) system.toL2Bus.respLayer6.utilization 24.2 # Layer utilization (%) -system.toL2Bus.respLayer7.occupancy 157629539 # Layer occupancy (ticks) -system.toL2Bus.respLayer7.utilization 24.3 # Layer utilization (%) -system.cpu0.num_reads 98049 # number of read accesses completed -system.cpu0.num_writes 53278 # number of write accesses completed +system.toL2Bus.respLayer7.occupancy 157763244 # Layer occupancy (ticks) +system.toL2Bus.respLayer7.utilization 24.2 # Layer utilization (%) +system.cpu0.num_reads 98977 # number of read accesses completed +system.cpu0.num_writes 53590 # number of write accesses completed system.cpu0.num_copies 0 # number of copy accesses completed -system.cpu0.l1c.replacements 21910 # number of replacements -system.cpu0.l1c.tagsinuse 394.044184 # Cycle average of tags in use -system.cpu0.l1c.total_refs 13156 # Total number of references to valid blocks. -system.cpu0.l1c.sampled_refs 22301 # Sample count of references to valid blocks. -system.cpu0.l1c.avg_refs 0.589929 # Average number of references to valid blocks. -system.cpu0.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.l1c.occ_blocks::cpu0 394.044184 # Average occupied blocks per requestor -system.cpu0.l1c.occ_percent::cpu0 0.769618 # Average percentage of cache occupancy -system.cpu0.l1c.occ_percent::total 0.769618 # Average percentage of cache occupancy -system.cpu0.l1c.ReadReq_hits::cpu0 8471 # number of ReadReq hits -system.cpu0.l1c.ReadReq_hits::total 8471 # number of ReadReq hits -system.cpu0.l1c.WriteReq_hits::cpu0 1074 # number of WriteReq hits -system.cpu0.l1c.WriteReq_hits::total 1074 # number of WriteReq hits -system.cpu0.l1c.demand_hits::cpu0 9545 # number of demand (read+write) hits -system.cpu0.l1c.demand_hits::total 9545 # number of demand (read+write) hits -system.cpu0.l1c.overall_hits::cpu0 9545 # number of overall hits -system.cpu0.l1c.overall_hits::total 9545 # number of overall hits -system.cpu0.l1c.ReadReq_misses::cpu0 35640 # number of ReadReq misses -system.cpu0.l1c.ReadReq_misses::total 35640 # number of ReadReq misses -system.cpu0.l1c.WriteReq_misses::cpu0 23074 # number of WriteReq misses -system.cpu0.l1c.WriteReq_misses::total 23074 # number of WriteReq misses -system.cpu0.l1c.demand_misses::cpu0 58714 # number of demand (read+write) misses -system.cpu0.l1c.demand_misses::total 58714 # number of demand (read+write) misses -system.cpu0.l1c.overall_misses::cpu0 58714 # number of overall misses -system.cpu0.l1c.overall_misses::total 58714 # number of overall misses -system.cpu0.l1c.ReadReq_miss_latency::cpu0 933901812 # number of ReadReq miss cycles -system.cpu0.l1c.ReadReq_miss_latency::total 933901812 # number of ReadReq miss cycles -system.cpu0.l1c.WriteReq_miss_latency::cpu0 856280361 # number of WriteReq miss cycles -system.cpu0.l1c.WriteReq_miss_latency::total 856280361 # number of WriteReq miss cycles -system.cpu0.l1c.demand_miss_latency::cpu0 1790182173 # number of demand (read+write) miss cycles -system.cpu0.l1c.demand_miss_latency::total 1790182173 # number of demand (read+write) miss cycles -system.cpu0.l1c.overall_miss_latency::cpu0 1790182173 # number of overall miss cycles -system.cpu0.l1c.overall_miss_latency::total 1790182173 # number of overall miss cycles -system.cpu0.l1c.ReadReq_accesses::cpu0 44111 # number of ReadReq accesses(hits+misses) -system.cpu0.l1c.ReadReq_accesses::total 44111 # number of ReadReq accesses(hits+misses) -system.cpu0.l1c.WriteReq_accesses::cpu0 24148 # number of WriteReq accesses(hits+misses) -system.cpu0.l1c.WriteReq_accesses::total 24148 # number of WriteReq accesses(hits+misses) -system.cpu0.l1c.demand_accesses::cpu0 68259 # number of demand (read+write) accesses -system.cpu0.l1c.demand_accesses::total 68259 # number of demand (read+write) accesses -system.cpu0.l1c.overall_accesses::cpu0 68259 # number of overall (read+write) accesses -system.cpu0.l1c.overall_accesses::total 68259 # number of overall (read+write) accesses -system.cpu0.l1c.ReadReq_miss_rate::cpu0 0.807962 # miss rate for ReadReq accesses -system.cpu0.l1c.ReadReq_miss_rate::total 0.807962 # miss rate for ReadReq accesses -system.cpu0.l1c.WriteReq_miss_rate::cpu0 0.955524 # miss rate for WriteReq accesses -system.cpu0.l1c.WriteReq_miss_rate::total 0.955524 # miss rate for WriteReq accesses -system.cpu0.l1c.demand_miss_rate::cpu0 0.860165 # miss rate for demand accesses -system.cpu0.l1c.demand_miss_rate::total 0.860165 # miss rate for demand accesses -system.cpu0.l1c.overall_miss_rate::cpu0 0.860165 # miss rate for overall accesses -system.cpu0.l1c.overall_miss_rate::total 0.860165 # miss rate for overall accesses -system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 26203.754545 # average ReadReq miss latency -system.cpu0.l1c.ReadReq_avg_miss_latency::total 26203.754545 # average ReadReq miss latency -system.cpu0.l1c.WriteReq_avg_miss_latency::cpu0 37110.182933 # average WriteReq miss latency -system.cpu0.l1c.WriteReq_avg_miss_latency::total 37110.182933 # average WriteReq miss latency -system.cpu0.l1c.demand_avg_miss_latency::cpu0 30489.869077 # average overall miss latency -system.cpu0.l1c.demand_avg_miss_latency::total 30489.869077 # average overall miss latency -system.cpu0.l1c.overall_avg_miss_latency::cpu0 30489.869077 # average overall miss latency -system.cpu0.l1c.overall_avg_miss_latency::total 30489.869077 # average overall miss latency -system.cpu0.l1c.blocked_cycles::no_mshrs 1011011 # number of cycles access was blocked +system.cpu0.l1c.tags.replacements 21970 # number of replacements +system.cpu0.l1c.tags.tagsinuse 393.709596 # Cycle average of tags in use +system.cpu0.l1c.tags.total_refs 13350 # Total number of references to valid blocks. +system.cpu0.l1c.tags.sampled_refs 22370 # Sample count of references to valid blocks. +system.cpu0.l1c.tags.avg_refs 0.596781 # Average number of references to valid blocks. +system.cpu0.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu0.l1c.tags.occ_blocks::cpu0 393.709596 # Average occupied blocks per requestor +system.cpu0.l1c.tags.occ_percent::cpu0 0.768964 # Average percentage of cache occupancy +system.cpu0.l1c.tags.occ_percent::total 0.768964 # Average percentage of cache occupancy +system.cpu0.l1c.ReadReq_hits::cpu0 8685 # number of ReadReq hits +system.cpu0.l1c.ReadReq_hits::total 8685 # number of ReadReq hits +system.cpu0.l1c.WriteReq_hits::cpu0 1118 # number of WriteReq hits +system.cpu0.l1c.WriteReq_hits::total 1118 # number of WriteReq hits +system.cpu0.l1c.demand_hits::cpu0 9803 # number of demand (read+write) hits +system.cpu0.l1c.demand_hits::total 9803 # number of demand (read+write) hits +system.cpu0.l1c.overall_hits::cpu0 9803 # number of overall hits +system.cpu0.l1c.overall_hits::total 9803 # number of overall hits +system.cpu0.l1c.ReadReq_misses::cpu0 35704 # number of ReadReq misses +system.cpu0.l1c.ReadReq_misses::total 35704 # number of ReadReq misses +system.cpu0.l1c.WriteReq_misses::cpu0 23289 # number of WriteReq misses +system.cpu0.l1c.WriteReq_misses::total 23289 # number of WriteReq misses +system.cpu0.l1c.demand_misses::cpu0 58993 # number of demand (read+write) misses +system.cpu0.l1c.demand_misses::total 58993 # number of demand (read+write) misses +system.cpu0.l1c.overall_misses::cpu0 58993 # number of overall misses +system.cpu0.l1c.overall_misses::total 58993 # number of overall misses +system.cpu0.l1c.ReadReq_miss_latency::cpu0 937059642 # number of ReadReq miss cycles +system.cpu0.l1c.ReadReq_miss_latency::total 937059642 # number of ReadReq miss cycles +system.cpu0.l1c.WriteReq_miss_latency::cpu0 866806760 # number of WriteReq miss cycles +system.cpu0.l1c.WriteReq_miss_latency::total 866806760 # number of WriteReq miss cycles +system.cpu0.l1c.demand_miss_latency::cpu0 1803866402 # number of demand (read+write) miss cycles +system.cpu0.l1c.demand_miss_latency::total 1803866402 # number of demand (read+write) miss cycles +system.cpu0.l1c.overall_miss_latency::cpu0 1803866402 # number of overall miss cycles +system.cpu0.l1c.overall_miss_latency::total 1803866402 # number of overall miss cycles +system.cpu0.l1c.ReadReq_accesses::cpu0 44389 # number of ReadReq accesses(hits+misses) +system.cpu0.l1c.ReadReq_accesses::total 44389 # number of ReadReq accesses(hits+misses) +system.cpu0.l1c.WriteReq_accesses::cpu0 24407 # number of WriteReq accesses(hits+misses) +system.cpu0.l1c.WriteReq_accesses::total 24407 # number of WriteReq accesses(hits+misses) +system.cpu0.l1c.demand_accesses::cpu0 68796 # number of demand (read+write) accesses +system.cpu0.l1c.demand_accesses::total 68796 # number of demand (read+write) accesses +system.cpu0.l1c.overall_accesses::cpu0 68796 # number of overall (read+write) accesses +system.cpu0.l1c.overall_accesses::total 68796 # number of overall (read+write) accesses +system.cpu0.l1c.ReadReq_miss_rate::cpu0 0.804343 # miss rate for ReadReq accesses +system.cpu0.l1c.ReadReq_miss_rate::total 0.804343 # miss rate for ReadReq accesses +system.cpu0.l1c.WriteReq_miss_rate::cpu0 0.954193 # miss rate for WriteReq accesses +system.cpu0.l1c.WriteReq_miss_rate::total 0.954193 # miss rate for WriteReq accesses +system.cpu0.l1c.demand_miss_rate::cpu0 0.857506 # miss rate for demand accesses +system.cpu0.l1c.demand_miss_rate::total 0.857506 # miss rate for demand accesses +system.cpu0.l1c.overall_miss_rate::cpu0 0.857506 # miss rate for overall accesses +system.cpu0.l1c.overall_miss_rate::total 0.857506 # miss rate for overall accesses +system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 26245.228602 # average ReadReq miss latency +system.cpu0.l1c.ReadReq_avg_miss_latency::total 26245.228602 # average ReadReq miss latency +system.cpu0.l1c.WriteReq_avg_miss_latency::cpu0 37219.578342 # average WriteReq miss latency +system.cpu0.l1c.WriteReq_avg_miss_latency::total 37219.578342 # average WriteReq miss latency +system.cpu0.l1c.demand_avg_miss_latency::cpu0 30577.634669 # average overall miss latency +system.cpu0.l1c.demand_avg_miss_latency::total 30577.634669 # average overall miss latency +system.cpu0.l1c.overall_avg_miss_latency::cpu0 30577.634669 # average overall miss latency +system.cpu0.l1c.overall_avg_miss_latency::total 30577.634669 # average overall miss latency +system.cpu0.l1c.blocked_cycles::no_mshrs 1018391 # number of cycles access was blocked system.cpu0.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.l1c.blocked::no_mshrs 61585 # number of cycles access was blocked +system.cpu0.l1c.blocked::no_mshrs 62068 # number of cycles access was blocked system.cpu0.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.l1c.avg_blocked_cycles::no_mshrs 16.416514 # average number of cycles each access was blocked +system.cpu0.l1c.avg_blocked_cycles::no_mshrs 16.407666 # average number of cycles each access was blocked system.cpu0.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.l1c.fast_writes 0 # number of fast writes performed system.cpu0.l1c.cache_copies 0 # number of cache copies performed -system.cpu0.l1c.writebacks::writebacks 9569 # number of writebacks -system.cpu0.l1c.writebacks::total 9569 # number of writebacks -system.cpu0.l1c.ReadReq_mshr_misses::cpu0 35640 # number of ReadReq MSHR misses -system.cpu0.l1c.ReadReq_mshr_misses::total 35640 # number of ReadReq MSHR misses -system.cpu0.l1c.WriteReq_mshr_misses::cpu0 23074 # number of WriteReq MSHR misses -system.cpu0.l1c.WriteReq_mshr_misses::total 23074 # number of WriteReq MSHR misses -system.cpu0.l1c.demand_mshr_misses::cpu0 58714 # number of demand (read+write) MSHR misses -system.cpu0.l1c.demand_mshr_misses::total 58714 # number of demand (read+write) MSHR misses -system.cpu0.l1c.overall_mshr_misses::cpu0 58714 # number of overall MSHR misses -system.cpu0.l1c.overall_mshr_misses::total 58714 # number of overall MSHR misses -system.cpu0.l1c.ReadReq_mshr_miss_latency::cpu0 860177811 # number of ReadReq MSHR miss cycles -system.cpu0.l1c.ReadReq_mshr_miss_latency::total 860177811 # number of ReadReq MSHR miss cycles -system.cpu0.l1c.WriteReq_mshr_miss_latency::cpu0 808764395 # number of WriteReq MSHR miss cycles -system.cpu0.l1c.WriteReq_mshr_miss_latency::total 808764395 # number of WriteReq MSHR miss cycles -system.cpu0.l1c.demand_mshr_miss_latency::cpu0 1668942206 # number of demand (read+write) MSHR miss cycles -system.cpu0.l1c.demand_mshr_miss_latency::total 1668942206 # number of demand (read+write) MSHR miss cycles -system.cpu0.l1c.overall_mshr_miss_latency::cpu0 1668942206 # number of overall MSHR miss cycles -system.cpu0.l1c.overall_mshr_miss_latency::total 1668942206 # number of overall MSHR miss cycles -system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::cpu0 696207485 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::total 696207485 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::cpu0 1651009618 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::total 1651009618 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l1c.overall_mshr_uncacheable_latency::cpu0 2347217103 # number of overall MSHR uncacheable cycles -system.cpu0.l1c.overall_mshr_uncacheable_latency::total 2347217103 # number of overall MSHR uncacheable cycles -system.cpu0.l1c.ReadReq_mshr_miss_rate::cpu0 0.807962 # mshr miss rate for ReadReq accesses -system.cpu0.l1c.ReadReq_mshr_miss_rate::total 0.807962 # mshr miss rate for ReadReq accesses -system.cpu0.l1c.WriteReq_mshr_miss_rate::cpu0 0.955524 # mshr miss rate for WriteReq accesses -system.cpu0.l1c.WriteReq_mshr_miss_rate::total 0.955524 # mshr miss rate for WriteReq accesses -system.cpu0.l1c.demand_mshr_miss_rate::cpu0 0.860165 # mshr miss rate for demand accesses -system.cpu0.l1c.demand_mshr_miss_rate::total 0.860165 # mshr miss rate for demand accesses -system.cpu0.l1c.overall_mshr_miss_rate::cpu0 0.860165 # mshr miss rate for overall accesses -system.cpu0.l1c.overall_mshr_miss_rate::total 0.860165 # mshr miss rate for overall accesses -system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::cpu0 24135.179882 # average ReadReq mshr miss latency -system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::total 24135.179882 # average ReadReq mshr miss latency -system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::cpu0 35050.896897 # average WriteReq mshr miss latency -system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::total 35050.896897 # average WriteReq mshr miss latency -system.cpu0.l1c.demand_avg_mshr_miss_latency::cpu0 28424.944749 # average overall mshr miss latency -system.cpu0.l1c.demand_avg_mshr_miss_latency::total 28424.944749 # average overall mshr miss latency -system.cpu0.l1c.overall_avg_mshr_miss_latency::cpu0 28424.944749 # average overall mshr miss latency -system.cpu0.l1c.overall_avg_mshr_miss_latency::total 28424.944749 # average overall mshr miss latency +system.cpu0.l1c.writebacks::writebacks 9494 # number of writebacks +system.cpu0.l1c.writebacks::total 9494 # number of writebacks +system.cpu0.l1c.ReadReq_mshr_misses::cpu0 35704 # number of ReadReq MSHR misses +system.cpu0.l1c.ReadReq_mshr_misses::total 35704 # number of ReadReq MSHR misses +system.cpu0.l1c.WriteReq_mshr_misses::cpu0 23289 # number of WriteReq MSHR misses +system.cpu0.l1c.WriteReq_mshr_misses::total 23289 # number of WriteReq MSHR misses +system.cpu0.l1c.demand_mshr_misses::cpu0 58993 # number of demand (read+write) MSHR misses +system.cpu0.l1c.demand_mshr_misses::total 58993 # number of demand (read+write) MSHR misses +system.cpu0.l1c.overall_mshr_misses::cpu0 58993 # number of overall MSHR misses +system.cpu0.l1c.overall_mshr_misses::total 58993 # number of overall MSHR misses +system.cpu0.l1c.ReadReq_mshr_miss_latency::cpu0 860700776 # number of ReadReq MSHR miss cycles +system.cpu0.l1c.ReadReq_mshr_miss_latency::total 860700776 # number of ReadReq MSHR miss cycles +system.cpu0.l1c.WriteReq_mshr_miss_latency::cpu0 817560778 # number of WriteReq MSHR miss cycles +system.cpu0.l1c.WriteReq_mshr_miss_latency::total 817560778 # number of WriteReq MSHR miss cycles +system.cpu0.l1c.demand_mshr_miss_latency::cpu0 1678261554 # number of demand (read+write) MSHR miss cycles +system.cpu0.l1c.demand_mshr_miss_latency::total 1678261554 # number of demand (read+write) MSHR miss cycles +system.cpu0.l1c.overall_mshr_miss_latency::cpu0 1678261554 # number of overall MSHR miss cycles +system.cpu0.l1c.overall_mshr_miss_latency::total 1678261554 # number of overall MSHR miss cycles +system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::cpu0 703193894 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::total 703193894 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::cpu0 1636775658 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::total 1636775658 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l1c.overall_mshr_uncacheable_latency::cpu0 2339969552 # number of overall MSHR uncacheable cycles +system.cpu0.l1c.overall_mshr_uncacheable_latency::total 2339969552 # number of overall MSHR uncacheable cycles +system.cpu0.l1c.ReadReq_mshr_miss_rate::cpu0 0.804343 # mshr miss rate for ReadReq accesses +system.cpu0.l1c.ReadReq_mshr_miss_rate::total 0.804343 # mshr miss rate for ReadReq accesses +system.cpu0.l1c.WriteReq_mshr_miss_rate::cpu0 0.954193 # mshr miss rate for WriteReq accesses +system.cpu0.l1c.WriteReq_mshr_miss_rate::total 0.954193 # mshr miss rate for WriteReq accesses +system.cpu0.l1c.demand_mshr_miss_rate::cpu0 0.857506 # mshr miss rate for demand accesses +system.cpu0.l1c.demand_mshr_miss_rate::total 0.857506 # mshr miss rate for demand accesses +system.cpu0.l1c.overall_mshr_miss_rate::cpu0 0.857506 # mshr miss rate for overall accesses +system.cpu0.l1c.overall_mshr_miss_rate::total 0.857506 # mshr miss rate for overall accesses +system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::cpu0 24106.564419 # average ReadReq mshr miss latency +system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::total 24106.564419 # average ReadReq mshr miss latency +system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::cpu0 35105.018592 # average WriteReq mshr miss latency +system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::total 35105.018592 # average WriteReq mshr miss latency +system.cpu0.l1c.demand_avg_mshr_miss_latency::cpu0 28448.486329 # average overall mshr miss latency +system.cpu0.l1c.demand_avg_mshr_miss_latency::total 28448.486329 # average overall mshr miss latency +system.cpu0.l1c.overall_avg_mshr_miss_latency::cpu0 28448.486329 # average overall mshr miss latency +system.cpu0.l1c.overall_avg_mshr_miss_latency::total 28448.486329 # average overall mshr miss latency system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu0 inf # average ReadReq mshr uncacheable latency system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu0 inf # average WriteReq mshr uncacheable latency @@ -845,114 +843,114 @@ system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::cpu0 inf # average overall mshr uncacheable latency system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.num_reads 98391 # number of read accesses completed -system.cpu1.num_writes 53060 # number of write accesses completed +system.cpu1.num_reads 99824 # number of read accesses completed +system.cpu1.num_writes 53636 # number of write accesses completed system.cpu1.num_copies 0 # number of copy accesses completed -system.cpu1.l1c.replacements 21908 # number of replacements -system.cpu1.l1c.tagsinuse 394.826417 # Cycle average of tags in use -system.cpu1.l1c.total_refs 13138 # Total number of references to valid blocks. -system.cpu1.l1c.sampled_refs 22318 # Sample count of references to valid blocks. -system.cpu1.l1c.avg_refs 0.588673 # Average number of references to valid blocks. -system.cpu1.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.l1c.occ_blocks::cpu1 394.826417 # Average occupied blocks per requestor -system.cpu1.l1c.occ_percent::cpu1 0.771145 # Average percentage of cache occupancy -system.cpu1.l1c.occ_percent::total 0.771145 # Average percentage of cache occupancy -system.cpu1.l1c.ReadReq_hits::cpu1 8563 # number of ReadReq hits -system.cpu1.l1c.ReadReq_hits::total 8563 # number of ReadReq hits -system.cpu1.l1c.WriteReq_hits::cpu1 1113 # number of WriteReq hits -system.cpu1.l1c.WriteReq_hits::total 1113 # number of WriteReq hits -system.cpu1.l1c.demand_hits::cpu1 9676 # number of demand (read+write) hits -system.cpu1.l1c.demand_hits::total 9676 # number of demand (read+write) hits -system.cpu1.l1c.overall_hits::cpu1 9676 # number of overall hits -system.cpu1.l1c.overall_hits::total 9676 # number of overall hits -system.cpu1.l1c.ReadReq_misses::cpu1 35632 # number of ReadReq misses -system.cpu1.l1c.ReadReq_misses::total 35632 # number of ReadReq misses -system.cpu1.l1c.WriteReq_misses::cpu1 23114 # number of WriteReq misses -system.cpu1.l1c.WriteReq_misses::total 23114 # number of WriteReq misses -system.cpu1.l1c.demand_misses::cpu1 58746 # number of demand (read+write) misses -system.cpu1.l1c.demand_misses::total 58746 # number of demand (read+write) misses -system.cpu1.l1c.overall_misses::cpu1 58746 # number of overall misses -system.cpu1.l1c.overall_misses::total 58746 # number of overall misses -system.cpu1.l1c.ReadReq_miss_latency::cpu1 934157803 # number of ReadReq miss cycles -system.cpu1.l1c.ReadReq_miss_latency::total 934157803 # number of ReadReq miss cycles -system.cpu1.l1c.WriteReq_miss_latency::cpu1 854823705 # number of WriteReq miss cycles -system.cpu1.l1c.WriteReq_miss_latency::total 854823705 # number of WriteReq miss cycles -system.cpu1.l1c.demand_miss_latency::cpu1 1788981508 # number of demand (read+write) miss cycles -system.cpu1.l1c.demand_miss_latency::total 1788981508 # number of demand (read+write) miss cycles -system.cpu1.l1c.overall_miss_latency::cpu1 1788981508 # number of overall miss cycles -system.cpu1.l1c.overall_miss_latency::total 1788981508 # number of overall miss cycles -system.cpu1.l1c.ReadReq_accesses::cpu1 44195 # number of ReadReq accesses(hits+misses) -system.cpu1.l1c.ReadReq_accesses::total 44195 # number of ReadReq accesses(hits+misses) -system.cpu1.l1c.WriteReq_accesses::cpu1 24227 # number of WriteReq accesses(hits+misses) -system.cpu1.l1c.WriteReq_accesses::total 24227 # number of WriteReq accesses(hits+misses) -system.cpu1.l1c.demand_accesses::cpu1 68422 # number of demand (read+write) accesses -system.cpu1.l1c.demand_accesses::total 68422 # number of demand (read+write) accesses -system.cpu1.l1c.overall_accesses::cpu1 68422 # number of overall (read+write) accesses -system.cpu1.l1c.overall_accesses::total 68422 # number of overall (read+write) accesses -system.cpu1.l1c.ReadReq_miss_rate::cpu1 0.806245 # miss rate for ReadReq accesses -system.cpu1.l1c.ReadReq_miss_rate::total 0.806245 # miss rate for ReadReq accesses -system.cpu1.l1c.WriteReq_miss_rate::cpu1 0.954060 # miss rate for WriteReq accesses -system.cpu1.l1c.WriteReq_miss_rate::total 0.954060 # miss rate for WriteReq accesses -system.cpu1.l1c.demand_miss_rate::cpu1 0.858583 # miss rate for demand accesses -system.cpu1.l1c.demand_miss_rate::total 0.858583 # miss rate for demand accesses -system.cpu1.l1c.overall_miss_rate::cpu1 0.858583 # miss rate for overall accesses -system.cpu1.l1c.overall_miss_rate::total 0.858583 # miss rate for overall accesses -system.cpu1.l1c.ReadReq_avg_miss_latency::cpu1 26216.822042 # average ReadReq miss latency -system.cpu1.l1c.ReadReq_avg_miss_latency::total 26216.822042 # average ReadReq miss latency -system.cpu1.l1c.WriteReq_avg_miss_latency::cpu1 36982.941291 # average WriteReq miss latency -system.cpu1.l1c.WriteReq_avg_miss_latency::total 36982.941291 # average WriteReq miss latency -system.cpu1.l1c.demand_avg_miss_latency::cpu1 30452.822456 # average overall miss latency -system.cpu1.l1c.demand_avg_miss_latency::total 30452.822456 # average overall miss latency -system.cpu1.l1c.overall_avg_miss_latency::cpu1 30452.822456 # average overall miss latency -system.cpu1.l1c.overall_avg_miss_latency::total 30452.822456 # average overall miss latency -system.cpu1.l1c.blocked_cycles::no_mshrs 1014678 # number of cycles access was blocked +system.cpu1.l1c.tags.replacements 22223 # number of replacements +system.cpu1.l1c.tags.tagsinuse 395.298418 # Cycle average of tags in use +system.cpu1.l1c.tags.total_refs 13436 # Total number of references to valid blocks. +system.cpu1.l1c.tags.sampled_refs 22630 # Sample count of references to valid blocks. +system.cpu1.l1c.tags.avg_refs 0.593725 # Average number of references to valid blocks. +system.cpu1.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu1.l1c.tags.occ_blocks::cpu1 395.298418 # Average occupied blocks per requestor +system.cpu1.l1c.tags.occ_percent::cpu1 0.772067 # Average percentage of cache occupancy +system.cpu1.l1c.tags.occ_percent::total 0.772067 # Average percentage of cache occupancy +system.cpu1.l1c.ReadReq_hits::cpu1 8757 # number of ReadReq hits +system.cpu1.l1c.ReadReq_hits::total 8757 # number of ReadReq hits +system.cpu1.l1c.WriteReq_hits::cpu1 1135 # number of WriteReq hits +system.cpu1.l1c.WriteReq_hits::total 1135 # number of WriteReq hits +system.cpu1.l1c.demand_hits::cpu1 9892 # number of demand (read+write) hits +system.cpu1.l1c.demand_hits::total 9892 # number of demand (read+write) hits +system.cpu1.l1c.overall_hits::cpu1 9892 # number of overall hits +system.cpu1.l1c.overall_hits::total 9892 # number of overall hits +system.cpu1.l1c.ReadReq_misses::cpu1 36260 # number of ReadReq misses +system.cpu1.l1c.ReadReq_misses::total 36260 # number of ReadReq misses +system.cpu1.l1c.WriteReq_misses::cpu1 23033 # number of WriteReq misses +system.cpu1.l1c.WriteReq_misses::total 23033 # number of WriteReq misses +system.cpu1.l1c.demand_misses::cpu1 59293 # number of demand (read+write) misses +system.cpu1.l1c.demand_misses::total 59293 # number of demand (read+write) misses +system.cpu1.l1c.overall_misses::cpu1 59293 # number of overall misses +system.cpu1.l1c.overall_misses::total 59293 # number of overall misses +system.cpu1.l1c.ReadReq_miss_latency::cpu1 947629716 # number of ReadReq miss cycles +system.cpu1.l1c.ReadReq_miss_latency::total 947629716 # number of ReadReq miss cycles +system.cpu1.l1c.WriteReq_miss_latency::cpu1 858813201 # number of WriteReq miss cycles +system.cpu1.l1c.WriteReq_miss_latency::total 858813201 # number of WriteReq miss cycles +system.cpu1.l1c.demand_miss_latency::cpu1 1806442917 # number of demand (read+write) miss cycles +system.cpu1.l1c.demand_miss_latency::total 1806442917 # number of demand (read+write) miss cycles +system.cpu1.l1c.overall_miss_latency::cpu1 1806442917 # number of overall miss cycles +system.cpu1.l1c.overall_miss_latency::total 1806442917 # number of overall miss cycles +system.cpu1.l1c.ReadReq_accesses::cpu1 45017 # number of ReadReq accesses(hits+misses) +system.cpu1.l1c.ReadReq_accesses::total 45017 # number of ReadReq accesses(hits+misses) +system.cpu1.l1c.WriteReq_accesses::cpu1 24168 # number of WriteReq accesses(hits+misses) +system.cpu1.l1c.WriteReq_accesses::total 24168 # number of WriteReq accesses(hits+misses) +system.cpu1.l1c.demand_accesses::cpu1 69185 # number of demand (read+write) accesses +system.cpu1.l1c.demand_accesses::total 69185 # number of demand (read+write) accesses +system.cpu1.l1c.overall_accesses::cpu1 69185 # number of overall (read+write) accesses +system.cpu1.l1c.overall_accesses::total 69185 # number of overall (read+write) accesses +system.cpu1.l1c.ReadReq_miss_rate::cpu1 0.805473 # miss rate for ReadReq accesses +system.cpu1.l1c.ReadReq_miss_rate::total 0.805473 # miss rate for ReadReq accesses +system.cpu1.l1c.WriteReq_miss_rate::cpu1 0.953037 # miss rate for WriteReq accesses +system.cpu1.l1c.WriteReq_miss_rate::total 0.953037 # miss rate for WriteReq accesses +system.cpu1.l1c.demand_miss_rate::cpu1 0.857021 # miss rate for demand accesses +system.cpu1.l1c.demand_miss_rate::total 0.857021 # miss rate for demand accesses +system.cpu1.l1c.overall_miss_rate::cpu1 0.857021 # miss rate for overall accesses +system.cpu1.l1c.overall_miss_rate::total 0.857021 # miss rate for overall accesses +system.cpu1.l1c.ReadReq_avg_miss_latency::cpu1 26134.299945 # average ReadReq miss latency +system.cpu1.l1c.ReadReq_avg_miss_latency::total 26134.299945 # average ReadReq miss latency +system.cpu1.l1c.WriteReq_avg_miss_latency::cpu1 37286.206790 # average WriteReq miss latency +system.cpu1.l1c.WriteReq_avg_miss_latency::total 37286.206790 # average WriteReq miss latency +system.cpu1.l1c.demand_avg_miss_latency::cpu1 30466.377431 # average overall miss latency +system.cpu1.l1c.demand_avg_miss_latency::total 30466.377431 # average overall miss latency +system.cpu1.l1c.overall_avg_miss_latency::cpu1 30466.377431 # average overall miss latency +system.cpu1.l1c.overall_avg_miss_latency::total 30466.377431 # average overall miss latency +system.cpu1.l1c.blocked_cycles::no_mshrs 1020302 # number of cycles access was blocked system.cpu1.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.l1c.blocked::no_mshrs 61858 # number of cycles access was blocked +system.cpu1.l1c.blocked::no_mshrs 62395 # number of cycles access was blocked system.cpu1.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.l1c.avg_blocked_cycles::no_mshrs 16.403343 # average number of cycles each access was blocked +system.cpu1.l1c.avg_blocked_cycles::no_mshrs 16.352304 # average number of cycles each access was blocked system.cpu1.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.l1c.fast_writes 0 # number of fast writes performed system.cpu1.l1c.cache_copies 0 # number of cache copies performed -system.cpu1.l1c.writebacks::writebacks 9599 # number of writebacks -system.cpu1.l1c.writebacks::total 9599 # number of writebacks -system.cpu1.l1c.ReadReq_mshr_misses::cpu1 35632 # number of ReadReq MSHR misses -system.cpu1.l1c.ReadReq_mshr_misses::total 35632 # number of ReadReq MSHR misses -system.cpu1.l1c.WriteReq_mshr_misses::cpu1 23114 # number of WriteReq MSHR misses -system.cpu1.l1c.WriteReq_mshr_misses::total 23114 # number of WriteReq MSHR misses -system.cpu1.l1c.demand_mshr_misses::cpu1 58746 # number of demand (read+write) MSHR misses -system.cpu1.l1c.demand_mshr_misses::total 58746 # number of demand (read+write) MSHR misses -system.cpu1.l1c.overall_mshr_misses::cpu1 58746 # number of overall MSHR misses -system.cpu1.l1c.overall_mshr_misses::total 58746 # number of overall MSHR misses -system.cpu1.l1c.ReadReq_mshr_miss_latency::cpu1 860390916 # number of ReadReq MSHR miss cycles -system.cpu1.l1c.ReadReq_mshr_miss_latency::total 860390916 # number of ReadReq MSHR miss cycles -system.cpu1.l1c.WriteReq_mshr_miss_latency::cpu1 807278180 # number of WriteReq MSHR miss cycles -system.cpu1.l1c.WriteReq_mshr_miss_latency::total 807278180 # number of WriteReq MSHR miss cycles -system.cpu1.l1c.demand_mshr_miss_latency::cpu1 1667669096 # number of demand (read+write) MSHR miss cycles -system.cpu1.l1c.demand_mshr_miss_latency::total 1667669096 # number of demand (read+write) MSHR miss cycles -system.cpu1.l1c.overall_mshr_miss_latency::cpu1 1667669096 # number of overall MSHR miss cycles -system.cpu1.l1c.overall_mshr_miss_latency::total 1667669096 # number of overall MSHR miss cycles -system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::cpu1 703500956 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::total 703500956 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::cpu1 1594898180 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::total 1594898180 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l1c.overall_mshr_uncacheable_latency::cpu1 2298399136 # number of overall MSHR uncacheable cycles -system.cpu1.l1c.overall_mshr_uncacheable_latency::total 2298399136 # number of overall MSHR uncacheable cycles -system.cpu1.l1c.ReadReq_mshr_miss_rate::cpu1 0.806245 # mshr miss rate for ReadReq accesses -system.cpu1.l1c.ReadReq_mshr_miss_rate::total 0.806245 # mshr miss rate for ReadReq accesses -system.cpu1.l1c.WriteReq_mshr_miss_rate::cpu1 0.954060 # mshr miss rate for WriteReq accesses -system.cpu1.l1c.WriteReq_mshr_miss_rate::total 0.954060 # mshr miss rate for WriteReq accesses -system.cpu1.l1c.demand_mshr_miss_rate::cpu1 0.858583 # mshr miss rate for demand accesses -system.cpu1.l1c.demand_mshr_miss_rate::total 0.858583 # mshr miss rate for demand accesses -system.cpu1.l1c.overall_mshr_miss_rate::cpu1 0.858583 # mshr miss rate for overall accesses -system.cpu1.l1c.overall_mshr_miss_rate::total 0.858583 # mshr miss rate for overall accesses -system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 24146.579367 # average ReadReq mshr miss latency -system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::total 24146.579367 # average ReadReq mshr miss latency -system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 34925.940123 # average WriteReq mshr miss latency -system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::total 34925.940123 # average WriteReq mshr miss latency -system.cpu1.l1c.demand_avg_mshr_miss_latency::cpu1 28387.789739 # average overall mshr miss latency -system.cpu1.l1c.demand_avg_mshr_miss_latency::total 28387.789739 # average overall mshr miss latency -system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 28387.789739 # average overall mshr miss latency -system.cpu1.l1c.overall_avg_mshr_miss_latency::total 28387.789739 # average overall mshr miss latency +system.cpu1.l1c.writebacks::writebacks 9512 # number of writebacks +system.cpu1.l1c.writebacks::total 9512 # number of writebacks +system.cpu1.l1c.ReadReq_mshr_misses::cpu1 36260 # number of ReadReq MSHR misses +system.cpu1.l1c.ReadReq_mshr_misses::total 36260 # number of ReadReq MSHR misses +system.cpu1.l1c.WriteReq_mshr_misses::cpu1 23033 # number of WriteReq MSHR misses +system.cpu1.l1c.WriteReq_mshr_misses::total 23033 # number of WriteReq MSHR misses +system.cpu1.l1c.demand_mshr_misses::cpu1 59293 # number of demand (read+write) MSHR misses +system.cpu1.l1c.demand_mshr_misses::total 59293 # number of demand (read+write) MSHR misses +system.cpu1.l1c.overall_mshr_misses::cpu1 59293 # number of overall MSHR misses +system.cpu1.l1c.overall_mshr_misses::total 59293 # number of overall MSHR misses +system.cpu1.l1c.ReadReq_mshr_miss_latency::cpu1 870111848 # number of ReadReq MSHR miss cycles +system.cpu1.l1c.ReadReq_mshr_miss_latency::total 870111848 # number of ReadReq MSHR miss cycles +system.cpu1.l1c.WriteReq_mshr_miss_latency::cpu1 810087173 # number of WriteReq MSHR miss cycles +system.cpu1.l1c.WriteReq_mshr_miss_latency::total 810087173 # number of WriteReq MSHR miss cycles +system.cpu1.l1c.demand_mshr_miss_latency::cpu1 1680199021 # number of demand (read+write) MSHR miss cycles +system.cpu1.l1c.demand_mshr_miss_latency::total 1680199021 # number of demand (read+write) MSHR miss cycles +system.cpu1.l1c.overall_mshr_miss_latency::cpu1 1680199021 # number of overall MSHR miss cycles +system.cpu1.l1c.overall_mshr_miss_latency::total 1680199021 # number of overall MSHR miss cycles +system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::cpu1 702431869 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::total 702431869 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::cpu1 1631991143 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::total 1631991143 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l1c.overall_mshr_uncacheable_latency::cpu1 2334423012 # number of overall MSHR uncacheable cycles +system.cpu1.l1c.overall_mshr_uncacheable_latency::total 2334423012 # number of overall MSHR uncacheable cycles +system.cpu1.l1c.ReadReq_mshr_miss_rate::cpu1 0.805473 # mshr miss rate for ReadReq accesses +system.cpu1.l1c.ReadReq_mshr_miss_rate::total 0.805473 # mshr miss rate for ReadReq accesses +system.cpu1.l1c.WriteReq_mshr_miss_rate::cpu1 0.953037 # mshr miss rate for WriteReq accesses +system.cpu1.l1c.WriteReq_mshr_miss_rate::total 0.953037 # mshr miss rate for WriteReq accesses +system.cpu1.l1c.demand_mshr_miss_rate::cpu1 0.857021 # mshr miss rate for demand accesses +system.cpu1.l1c.demand_mshr_miss_rate::total 0.857021 # mshr miss rate for demand accesses +system.cpu1.l1c.overall_mshr_miss_rate::cpu1 0.857021 # mshr miss rate for overall accesses +system.cpu1.l1c.overall_mshr_miss_rate::total 0.857021 # mshr miss rate for overall accesses +system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 23996.465747 # average ReadReq mshr miss latency +system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::total 23996.465747 # average ReadReq mshr miss latency +system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 35170.719099 # average WriteReq mshr miss latency +system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::total 35170.719099 # average WriteReq mshr miss latency +system.cpu1.l1c.demand_avg_mshr_miss_latency::cpu1 28337.223972 # average overall mshr miss latency +system.cpu1.l1c.demand_avg_mshr_miss_latency::total 28337.223972 # average overall mshr miss latency +system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 28337.223972 # average overall mshr miss latency +system.cpu1.l1c.overall_avg_mshr_miss_latency::total 28337.223972 # average overall mshr miss latency system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu1 inf # average ReadReq mshr uncacheable latency system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu1 inf # average WriteReq mshr uncacheable latency @@ -960,114 +958,114 @@ system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::cpu1 inf # average overall mshr uncacheable latency system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.num_reads 100000 # number of read accesses completed -system.cpu2.num_writes 53426 # number of write accesses completed +system.cpu2.num_reads 99336 # number of read accesses completed +system.cpu2.num_writes 53403 # number of write accesses completed system.cpu2.num_copies 0 # number of copy accesses completed -system.cpu2.l1c.replacements 22360 # number of replacements -system.cpu2.l1c.tagsinuse 394.888678 # Cycle average of tags in use -system.cpu2.l1c.total_refs 13327 # Total number of references to valid blocks. -system.cpu2.l1c.sampled_refs 22756 # Sample count of references to valid blocks. -system.cpu2.l1c.avg_refs 0.585648 # Average number of references to valid blocks. -system.cpu2.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.l1c.occ_blocks::cpu2 394.888678 # Average occupied blocks per requestor -system.cpu2.l1c.occ_percent::cpu2 0.771267 # Average percentage of cache occupancy -system.cpu2.l1c.occ_percent::total 0.771267 # Average percentage of cache occupancy -system.cpu2.l1c.ReadReq_hits::cpu2 8771 # number of ReadReq hits -system.cpu2.l1c.ReadReq_hits::total 8771 # number of ReadReq hits -system.cpu2.l1c.WriteReq_hits::cpu2 1101 # number of WriteReq hits -system.cpu2.l1c.WriteReq_hits::total 1101 # number of WriteReq hits -system.cpu2.l1c.demand_hits::cpu2 9872 # number of demand (read+write) hits -system.cpu2.l1c.demand_hits::total 9872 # number of demand (read+write) hits -system.cpu2.l1c.overall_hits::cpu2 9872 # number of overall hits -system.cpu2.l1c.overall_hits::total 9872 # number of overall hits -system.cpu2.l1c.ReadReq_misses::cpu2 36112 # number of ReadReq misses -system.cpu2.l1c.ReadReq_misses::total 36112 # number of ReadReq misses -system.cpu2.l1c.WriteReq_misses::cpu2 22938 # number of WriteReq misses -system.cpu2.l1c.WriteReq_misses::total 22938 # number of WriteReq misses -system.cpu2.l1c.demand_misses::cpu2 59050 # number of demand (read+write) misses -system.cpu2.l1c.demand_misses::total 59050 # number of demand (read+write) misses -system.cpu2.l1c.overall_misses::cpu2 59050 # number of overall misses -system.cpu2.l1c.overall_misses::total 59050 # number of overall misses -system.cpu2.l1c.ReadReq_miss_latency::cpu2 945591370 # number of ReadReq miss cycles -system.cpu2.l1c.ReadReq_miss_latency::total 945591370 # number of ReadReq miss cycles -system.cpu2.l1c.WriteReq_miss_latency::cpu2 849320343 # number of WriteReq miss cycles -system.cpu2.l1c.WriteReq_miss_latency::total 849320343 # number of WriteReq miss cycles -system.cpu2.l1c.demand_miss_latency::cpu2 1794911713 # number of demand (read+write) miss cycles -system.cpu2.l1c.demand_miss_latency::total 1794911713 # number of demand (read+write) miss cycles -system.cpu2.l1c.overall_miss_latency::cpu2 1794911713 # number of overall miss cycles -system.cpu2.l1c.overall_miss_latency::total 1794911713 # number of overall miss cycles -system.cpu2.l1c.ReadReq_accesses::cpu2 44883 # number of ReadReq accesses(hits+misses) -system.cpu2.l1c.ReadReq_accesses::total 44883 # number of ReadReq accesses(hits+misses) -system.cpu2.l1c.WriteReq_accesses::cpu2 24039 # number of WriteReq accesses(hits+misses) -system.cpu2.l1c.WriteReq_accesses::total 24039 # number of WriteReq accesses(hits+misses) -system.cpu2.l1c.demand_accesses::cpu2 68922 # number of demand (read+write) accesses -system.cpu2.l1c.demand_accesses::total 68922 # number of demand (read+write) accesses -system.cpu2.l1c.overall_accesses::cpu2 68922 # number of overall (read+write) accesses -system.cpu2.l1c.overall_accesses::total 68922 # number of overall (read+write) accesses -system.cpu2.l1c.ReadReq_miss_rate::cpu2 0.804581 # miss rate for ReadReq accesses -system.cpu2.l1c.ReadReq_miss_rate::total 0.804581 # miss rate for ReadReq accesses -system.cpu2.l1c.WriteReq_miss_rate::cpu2 0.954199 # miss rate for WriteReq accesses -system.cpu2.l1c.WriteReq_miss_rate::total 0.954199 # miss rate for WriteReq accesses -system.cpu2.l1c.demand_miss_rate::cpu2 0.856766 # miss rate for demand accesses -system.cpu2.l1c.demand_miss_rate::total 0.856766 # miss rate for demand accesses -system.cpu2.l1c.overall_miss_rate::cpu2 0.856766 # miss rate for overall accesses -system.cpu2.l1c.overall_miss_rate::total 0.856766 # miss rate for overall accesses -system.cpu2.l1c.ReadReq_avg_miss_latency::cpu2 26184.962616 # average ReadReq miss latency -system.cpu2.l1c.ReadReq_avg_miss_latency::total 26184.962616 # average ReadReq miss latency -system.cpu2.l1c.WriteReq_avg_miss_latency::cpu2 37026.782762 # average WriteReq miss latency -system.cpu2.l1c.WriteReq_avg_miss_latency::total 37026.782762 # average WriteReq miss latency -system.cpu2.l1c.demand_avg_miss_latency::cpu2 30396.472701 # average overall miss latency -system.cpu2.l1c.demand_avg_miss_latency::total 30396.472701 # average overall miss latency -system.cpu2.l1c.overall_avg_miss_latency::cpu2 30396.472701 # average overall miss latency -system.cpu2.l1c.overall_avg_miss_latency::total 30396.472701 # average overall miss latency -system.cpu2.l1c.blocked_cycles::no_mshrs 1018235 # number of cycles access was blocked +system.cpu2.l1c.tags.replacements 22214 # number of replacements +system.cpu2.l1c.tags.tagsinuse 394.859577 # Cycle average of tags in use +system.cpu2.l1c.tags.total_refs 13307 # Total number of references to valid blocks. +system.cpu2.l1c.tags.sampled_refs 22614 # Sample count of references to valid blocks. +system.cpu2.l1c.tags.avg_refs 0.588441 # Average number of references to valid blocks. +system.cpu2.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu2.l1c.tags.occ_blocks::cpu2 394.859577 # Average occupied blocks per requestor +system.cpu2.l1c.tags.occ_percent::cpu2 0.771210 # Average percentage of cache occupancy +system.cpu2.l1c.tags.occ_percent::total 0.771210 # Average percentage of cache occupancy +system.cpu2.l1c.ReadReq_hits::cpu2 8708 # number of ReadReq hits +system.cpu2.l1c.ReadReq_hits::total 8708 # number of ReadReq hits +system.cpu2.l1c.WriteReq_hits::cpu2 1070 # number of WriteReq hits +system.cpu2.l1c.WriteReq_hits::total 1070 # number of WriteReq hits +system.cpu2.l1c.demand_hits::cpu2 9778 # number of demand (read+write) hits +system.cpu2.l1c.demand_hits::total 9778 # number of demand (read+write) hits +system.cpu2.l1c.overall_hits::cpu2 9778 # number of overall hits +system.cpu2.l1c.overall_hits::total 9778 # number of overall hits +system.cpu2.l1c.ReadReq_misses::cpu2 36160 # number of ReadReq misses +system.cpu2.l1c.ReadReq_misses::total 36160 # number of ReadReq misses +system.cpu2.l1c.WriteReq_misses::cpu2 22990 # number of WriteReq misses +system.cpu2.l1c.WriteReq_misses::total 22990 # number of WriteReq misses +system.cpu2.l1c.demand_misses::cpu2 59150 # number of demand (read+write) misses +system.cpu2.l1c.demand_misses::total 59150 # number of demand (read+write) misses +system.cpu2.l1c.overall_misses::cpu2 59150 # number of overall misses +system.cpu2.l1c.overall_misses::total 59150 # number of overall misses +system.cpu2.l1c.ReadReq_miss_latency::cpu2 947354858 # number of ReadReq miss cycles +system.cpu2.l1c.ReadReq_miss_latency::total 947354858 # number of ReadReq miss cycles +system.cpu2.l1c.WriteReq_miss_latency::cpu2 856510547 # number of WriteReq miss cycles +system.cpu2.l1c.WriteReq_miss_latency::total 856510547 # number of WriteReq miss cycles +system.cpu2.l1c.demand_miss_latency::cpu2 1803865405 # number of demand (read+write) miss cycles +system.cpu2.l1c.demand_miss_latency::total 1803865405 # number of demand (read+write) miss cycles +system.cpu2.l1c.overall_miss_latency::cpu2 1803865405 # number of overall miss cycles +system.cpu2.l1c.overall_miss_latency::total 1803865405 # number of overall miss cycles +system.cpu2.l1c.ReadReq_accesses::cpu2 44868 # number of ReadReq accesses(hits+misses) +system.cpu2.l1c.ReadReq_accesses::total 44868 # number of ReadReq accesses(hits+misses) +system.cpu2.l1c.WriteReq_accesses::cpu2 24060 # number of WriteReq accesses(hits+misses) +system.cpu2.l1c.WriteReq_accesses::total 24060 # number of WriteReq accesses(hits+misses) +system.cpu2.l1c.demand_accesses::cpu2 68928 # number of demand (read+write) accesses +system.cpu2.l1c.demand_accesses::total 68928 # number of demand (read+write) accesses +system.cpu2.l1c.overall_accesses::cpu2 68928 # number of overall (read+write) accesses +system.cpu2.l1c.overall_accesses::total 68928 # number of overall (read+write) accesses +system.cpu2.l1c.ReadReq_miss_rate::cpu2 0.805920 # miss rate for ReadReq accesses +system.cpu2.l1c.ReadReq_miss_rate::total 0.805920 # miss rate for ReadReq accesses +system.cpu2.l1c.WriteReq_miss_rate::cpu2 0.955528 # miss rate for WriteReq accesses +system.cpu2.l1c.WriteReq_miss_rate::total 0.955528 # miss rate for WriteReq accesses +system.cpu2.l1c.demand_miss_rate::cpu2 0.858142 # miss rate for demand accesses +system.cpu2.l1c.demand_miss_rate::total 0.858142 # miss rate for demand accesses +system.cpu2.l1c.overall_miss_rate::cpu2 0.858142 # miss rate for overall accesses +system.cpu2.l1c.overall_miss_rate::total 0.858142 # miss rate for overall accesses +system.cpu2.l1c.ReadReq_avg_miss_latency::cpu2 26198.972843 # average ReadReq miss latency +system.cpu2.l1c.ReadReq_avg_miss_latency::total 26198.972843 # average ReadReq miss latency +system.cpu2.l1c.WriteReq_avg_miss_latency::cpu2 37255.787168 # average WriteReq miss latency +system.cpu2.l1c.WriteReq_avg_miss_latency::total 37255.787168 # average WriteReq miss latency +system.cpu2.l1c.demand_avg_miss_latency::cpu2 30496.456551 # average overall miss latency +system.cpu2.l1c.demand_avg_miss_latency::total 30496.456551 # average overall miss latency +system.cpu2.l1c.overall_avg_miss_latency::cpu2 30496.456551 # average overall miss latency +system.cpu2.l1c.overall_avg_miss_latency::total 30496.456551 # average overall miss latency +system.cpu2.l1c.blocked_cycles::no_mshrs 1016435 # number of cycles access was blocked system.cpu2.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu2.l1c.blocked::no_mshrs 62319 # number of cycles access was blocked +system.cpu2.l1c.blocked::no_mshrs 62092 # number of cycles access was blocked system.cpu2.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu2.l1c.avg_blocked_cycles::no_mshrs 16.339078 # average number of cycles each access was blocked +system.cpu2.l1c.avg_blocked_cycles::no_mshrs 16.369822 # average number of cycles each access was blocked system.cpu2.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu2.l1c.fast_writes 0 # number of fast writes performed system.cpu2.l1c.cache_copies 0 # number of cache copies performed -system.cpu2.l1c.writebacks::writebacks 9616 # number of writebacks -system.cpu2.l1c.writebacks::total 9616 # number of writebacks -system.cpu2.l1c.ReadReq_mshr_misses::cpu2 36112 # number of ReadReq MSHR misses -system.cpu2.l1c.ReadReq_mshr_misses::total 36112 # number of ReadReq MSHR misses -system.cpu2.l1c.WriteReq_mshr_misses::cpu2 22938 # number of WriteReq MSHR misses -system.cpu2.l1c.WriteReq_mshr_misses::total 22938 # number of WriteReq MSHR misses -system.cpu2.l1c.demand_mshr_misses::cpu2 59050 # number of demand (read+write) MSHR misses -system.cpu2.l1c.demand_mshr_misses::total 59050 # number of demand (read+write) MSHR misses -system.cpu2.l1c.overall_mshr_misses::cpu2 59050 # number of overall MSHR misses -system.cpu2.l1c.overall_mshr_misses::total 59050 # number of overall MSHR misses -system.cpu2.l1c.ReadReq_mshr_miss_latency::cpu2 870903925 # number of ReadReq MSHR miss cycles -system.cpu2.l1c.ReadReq_mshr_miss_latency::total 870903925 # number of ReadReq MSHR miss cycles -system.cpu2.l1c.WriteReq_mshr_miss_latency::cpu2 802151745 # number of WriteReq MSHR miss cycles -system.cpu2.l1c.WriteReq_mshr_miss_latency::total 802151745 # number of WriteReq MSHR miss cycles -system.cpu2.l1c.demand_mshr_miss_latency::cpu2 1673055670 # number of demand (read+write) MSHR miss cycles -system.cpu2.l1c.demand_mshr_miss_latency::total 1673055670 # number of demand (read+write) MSHR miss cycles -system.cpu2.l1c.overall_mshr_miss_latency::cpu2 1673055670 # number of overall MSHR miss cycles -system.cpu2.l1c.overall_mshr_miss_latency::total 1673055670 # number of overall MSHR miss cycles -system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::cpu2 702585995 # number of ReadReq MSHR uncacheable cycles -system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::total 702585995 # number of ReadReq MSHR uncacheable cycles -system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::cpu2 1602698265 # number of WriteReq MSHR uncacheable cycles -system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::total 1602698265 # number of WriteReq MSHR uncacheable cycles -system.cpu2.l1c.overall_mshr_uncacheable_latency::cpu2 2305284260 # number of overall MSHR uncacheable cycles -system.cpu2.l1c.overall_mshr_uncacheable_latency::total 2305284260 # number of overall MSHR uncacheable cycles -system.cpu2.l1c.ReadReq_mshr_miss_rate::cpu2 0.804581 # mshr miss rate for ReadReq accesses -system.cpu2.l1c.ReadReq_mshr_miss_rate::total 0.804581 # mshr miss rate for ReadReq accesses -system.cpu2.l1c.WriteReq_mshr_miss_rate::cpu2 0.954199 # mshr miss rate for WriteReq accesses -system.cpu2.l1c.WriteReq_mshr_miss_rate::total 0.954199 # mshr miss rate for WriteReq accesses -system.cpu2.l1c.demand_mshr_miss_rate::cpu2 0.856766 # mshr miss rate for demand accesses -system.cpu2.l1c.demand_mshr_miss_rate::total 0.856766 # mshr miss rate for demand accesses -system.cpu2.l1c.overall_mshr_miss_rate::cpu2 0.856766 # mshr miss rate for overall accesses -system.cpu2.l1c.overall_mshr_miss_rate::total 0.856766 # mshr miss rate for overall accesses -system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::cpu2 24116.745819 # average ReadReq mshr miss latency -system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::total 24116.745819 # average ReadReq mshr miss latency -system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::cpu2 34970.430944 # average WriteReq mshr miss latency -system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::total 34970.430944 # average WriteReq mshr miss latency -system.cpu2.l1c.demand_avg_mshr_miss_latency::cpu2 28332.864860 # average overall mshr miss latency -system.cpu2.l1c.demand_avg_mshr_miss_latency::total 28332.864860 # average overall mshr miss latency -system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 28332.864860 # average overall mshr miss latency -system.cpu2.l1c.overall_avg_mshr_miss_latency::total 28332.864860 # average overall mshr miss latency +system.cpu2.l1c.writebacks::writebacks 9582 # number of writebacks +system.cpu2.l1c.writebacks::total 9582 # number of writebacks +system.cpu2.l1c.ReadReq_mshr_misses::cpu2 36160 # number of ReadReq MSHR misses +system.cpu2.l1c.ReadReq_mshr_misses::total 36160 # number of ReadReq MSHR misses +system.cpu2.l1c.WriteReq_mshr_misses::cpu2 22990 # number of WriteReq MSHR misses +system.cpu2.l1c.WriteReq_mshr_misses::total 22990 # number of WriteReq MSHR misses +system.cpu2.l1c.demand_mshr_misses::cpu2 59150 # number of demand (read+write) MSHR misses +system.cpu2.l1c.demand_mshr_misses::total 59150 # number of demand (read+write) MSHR misses +system.cpu2.l1c.overall_mshr_misses::cpu2 59150 # number of overall MSHR misses +system.cpu2.l1c.overall_mshr_misses::total 59150 # number of overall MSHR misses +system.cpu2.l1c.ReadReq_mshr_miss_latency::cpu2 870067956 # number of ReadReq MSHR miss cycles +system.cpu2.l1c.ReadReq_mshr_miss_latency::total 870067956 # number of ReadReq MSHR miss cycles +system.cpu2.l1c.WriteReq_mshr_miss_latency::cpu2 807866531 # number of WriteReq MSHR miss cycles +system.cpu2.l1c.WriteReq_mshr_miss_latency::total 807866531 # number of WriteReq MSHR miss cycles +system.cpu2.l1c.demand_mshr_miss_latency::cpu2 1677934487 # number of demand (read+write) MSHR miss cycles +system.cpu2.l1c.demand_mshr_miss_latency::total 1677934487 # number of demand (read+write) MSHR miss cycles +system.cpu2.l1c.overall_mshr_miss_latency::cpu2 1677934487 # number of overall MSHR miss cycles +system.cpu2.l1c.overall_mshr_miss_latency::total 1677934487 # number of overall MSHR miss cycles +system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::cpu2 699720514 # number of ReadReq MSHR uncacheable cycles +system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::total 699720514 # number of ReadReq MSHR uncacheable cycles +system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::cpu2 1649553128 # number of WriteReq MSHR uncacheable cycles +system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::total 1649553128 # number of WriteReq MSHR uncacheable cycles +system.cpu2.l1c.overall_mshr_uncacheable_latency::cpu2 2349273642 # number of overall MSHR uncacheable cycles +system.cpu2.l1c.overall_mshr_uncacheable_latency::total 2349273642 # number of overall MSHR uncacheable cycles +system.cpu2.l1c.ReadReq_mshr_miss_rate::cpu2 0.805920 # mshr miss rate for ReadReq accesses +system.cpu2.l1c.ReadReq_mshr_miss_rate::total 0.805920 # mshr miss rate for ReadReq accesses +system.cpu2.l1c.WriteReq_mshr_miss_rate::cpu2 0.955528 # mshr miss rate for WriteReq accesses +system.cpu2.l1c.WriteReq_mshr_miss_rate::total 0.955528 # mshr miss rate for WriteReq accesses +system.cpu2.l1c.demand_mshr_miss_rate::cpu2 0.858142 # mshr miss rate for demand accesses +system.cpu2.l1c.demand_mshr_miss_rate::total 0.858142 # mshr miss rate for demand accesses +system.cpu2.l1c.overall_mshr_miss_rate::cpu2 0.858142 # mshr miss rate for overall accesses +system.cpu2.l1c.overall_mshr_miss_rate::total 0.858142 # mshr miss rate for overall accesses +system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::cpu2 24061.613827 # average ReadReq mshr miss latency +system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::total 24061.613827 # average ReadReq mshr miss latency +system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::cpu2 35139.910004 # average WriteReq mshr miss latency +system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::total 35139.910004 # average WriteReq mshr miss latency +system.cpu2.l1c.demand_avg_mshr_miss_latency::cpu2 28367.446948 # average overall mshr miss latency +system.cpu2.l1c.demand_avg_mshr_miss_latency::total 28367.446948 # average overall mshr miss latency +system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 28367.446948 # average overall mshr miss latency +system.cpu2.l1c.overall_avg_mshr_miss_latency::total 28367.446948 # average overall mshr miss latency system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu2 inf # average ReadReq mshr uncacheable latency system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu2 inf # average WriteReq mshr uncacheable latency @@ -1075,114 +1073,114 @@ system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::cpu2 inf # average overall mshr uncacheable latency system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu2.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.num_reads 98539 # number of read accesses completed -system.cpu3.num_writes 53510 # number of write accesses completed +system.cpu3.num_reads 100000 # number of read accesses completed +system.cpu3.num_writes 53536 # number of write accesses completed system.cpu3.num_copies 0 # number of copy accesses completed -system.cpu3.l1c.replacements 21926 # number of replacements -system.cpu3.l1c.tagsinuse 394.806744 # Cycle average of tags in use -system.cpu3.l1c.total_refs 12847 # Total number of references to valid blocks. -system.cpu3.l1c.sampled_refs 22328 # Sample count of references to valid blocks. -system.cpu3.l1c.avg_refs 0.575376 # Average number of references to valid blocks. -system.cpu3.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.l1c.occ_blocks::cpu3 394.806744 # Average occupied blocks per requestor -system.cpu3.l1c.occ_percent::cpu3 0.771107 # Average percentage of cache occupancy -system.cpu3.l1c.occ_percent::total 0.771107 # Average percentage of cache occupancy -system.cpu3.l1c.ReadReq_hits::cpu3 8426 # number of ReadReq hits -system.cpu3.l1c.ReadReq_hits::total 8426 # number of ReadReq hits -system.cpu3.l1c.WriteReq_hits::cpu3 1071 # number of WriteReq hits -system.cpu3.l1c.WriteReq_hits::total 1071 # number of WriteReq hits -system.cpu3.l1c.demand_hits::cpu3 9497 # number of demand (read+write) hits -system.cpu3.l1c.demand_hits::total 9497 # number of demand (read+write) hits -system.cpu3.l1c.overall_hits::cpu3 9497 # number of overall hits -system.cpu3.l1c.overall_hits::total 9497 # number of overall hits -system.cpu3.l1c.ReadReq_misses::cpu3 35942 # number of ReadReq misses -system.cpu3.l1c.ReadReq_misses::total 35942 # number of ReadReq misses -system.cpu3.l1c.WriteReq_misses::cpu3 22767 # number of WriteReq misses -system.cpu3.l1c.WriteReq_misses::total 22767 # number of WriteReq misses -system.cpu3.l1c.demand_misses::cpu3 58709 # number of demand (read+write) misses -system.cpu3.l1c.demand_misses::total 58709 # number of demand (read+write) misses -system.cpu3.l1c.overall_misses::cpu3 58709 # number of overall misses -system.cpu3.l1c.overall_misses::total 58709 # number of overall misses -system.cpu3.l1c.ReadReq_miss_latency::cpu3 940164359 # number of ReadReq miss cycles -system.cpu3.l1c.ReadReq_miss_latency::total 940164359 # number of ReadReq miss cycles -system.cpu3.l1c.WriteReq_miss_latency::cpu3 841530610 # number of WriteReq miss cycles -system.cpu3.l1c.WriteReq_miss_latency::total 841530610 # number of WriteReq miss cycles -system.cpu3.l1c.demand_miss_latency::cpu3 1781694969 # number of demand (read+write) miss cycles -system.cpu3.l1c.demand_miss_latency::total 1781694969 # number of demand (read+write) miss cycles -system.cpu3.l1c.overall_miss_latency::cpu3 1781694969 # number of overall miss cycles -system.cpu3.l1c.overall_miss_latency::total 1781694969 # number of overall miss cycles -system.cpu3.l1c.ReadReq_accesses::cpu3 44368 # number of ReadReq accesses(hits+misses) -system.cpu3.l1c.ReadReq_accesses::total 44368 # number of ReadReq accesses(hits+misses) -system.cpu3.l1c.WriteReq_accesses::cpu3 23838 # number of WriteReq accesses(hits+misses) -system.cpu3.l1c.WriteReq_accesses::total 23838 # number of WriteReq accesses(hits+misses) -system.cpu3.l1c.demand_accesses::cpu3 68206 # number of demand (read+write) accesses -system.cpu3.l1c.demand_accesses::total 68206 # number of demand (read+write) accesses -system.cpu3.l1c.overall_accesses::cpu3 68206 # number of overall (read+write) accesses -system.cpu3.l1c.overall_accesses::total 68206 # number of overall (read+write) accesses -system.cpu3.l1c.ReadReq_miss_rate::cpu3 0.810088 # miss rate for ReadReq accesses -system.cpu3.l1c.ReadReq_miss_rate::total 0.810088 # miss rate for ReadReq accesses -system.cpu3.l1c.WriteReq_miss_rate::cpu3 0.955072 # miss rate for WriteReq accesses -system.cpu3.l1c.WriteReq_miss_rate::total 0.955072 # miss rate for WriteReq accesses -system.cpu3.l1c.demand_miss_rate::cpu3 0.860760 # miss rate for demand accesses -system.cpu3.l1c.demand_miss_rate::total 0.860760 # miss rate for demand accesses -system.cpu3.l1c.overall_miss_rate::cpu3 0.860760 # miss rate for overall accesses -system.cpu3.l1c.overall_miss_rate::total 0.860760 # miss rate for overall accesses -system.cpu3.l1c.ReadReq_avg_miss_latency::cpu3 26157.819793 # average ReadReq miss latency -system.cpu3.l1c.ReadReq_avg_miss_latency::total 26157.819793 # average ReadReq miss latency -system.cpu3.l1c.WriteReq_avg_miss_latency::cpu3 36962.735978 # average WriteReq miss latency -system.cpu3.l1c.WriteReq_avg_miss_latency::total 36962.735978 # average WriteReq miss latency -system.cpu3.l1c.demand_avg_miss_latency::cpu3 30347.901838 # average overall miss latency -system.cpu3.l1c.demand_avg_miss_latency::total 30347.901838 # average overall miss latency -system.cpu3.l1c.overall_avg_miss_latency::cpu3 30347.901838 # average overall miss latency -system.cpu3.l1c.overall_avg_miss_latency::total 30347.901838 # average overall miss latency -system.cpu3.l1c.blocked_cycles::no_mshrs 1011201 # number of cycles access was blocked +system.cpu3.l1c.tags.replacements 22464 # number of replacements +system.cpu3.l1c.tags.tagsinuse 397.838914 # Cycle average of tags in use +system.cpu3.l1c.tags.total_refs 13424 # Total number of references to valid blocks. +system.cpu3.l1c.tags.sampled_refs 22862 # Sample count of references to valid blocks. +system.cpu3.l1c.tags.avg_refs 0.587175 # Average number of references to valid blocks. +system.cpu3.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu3.l1c.tags.occ_blocks::cpu3 397.838914 # Average occupied blocks per requestor +system.cpu3.l1c.tags.occ_percent::cpu3 0.777029 # Average percentage of cache occupancy +system.cpu3.l1c.tags.occ_percent::total 0.777029 # Average percentage of cache occupancy +system.cpu3.l1c.ReadReq_hits::cpu3 8781 # number of ReadReq hits +system.cpu3.l1c.ReadReq_hits::total 8781 # number of ReadReq hits +system.cpu3.l1c.WriteReq_hits::cpu3 1109 # number of WriteReq hits +system.cpu3.l1c.WriteReq_hits::total 1109 # number of WriteReq hits +system.cpu3.l1c.demand_hits::cpu3 9890 # number of demand (read+write) hits +system.cpu3.l1c.demand_hits::total 9890 # number of demand (read+write) hits +system.cpu3.l1c.overall_hits::cpu3 9890 # number of overall hits +system.cpu3.l1c.overall_hits::total 9890 # number of overall hits +system.cpu3.l1c.ReadReq_misses::cpu3 36107 # number of ReadReq misses +system.cpu3.l1c.ReadReq_misses::total 36107 # number of ReadReq misses +system.cpu3.l1c.WriteReq_misses::cpu3 23001 # number of WriteReq misses +system.cpu3.l1c.WriteReq_misses::total 23001 # number of WriteReq misses +system.cpu3.l1c.demand_misses::cpu3 59108 # number of demand (read+write) misses +system.cpu3.l1c.demand_misses::total 59108 # number of demand (read+write) misses +system.cpu3.l1c.overall_misses::cpu3 59108 # number of overall misses +system.cpu3.l1c.overall_misses::total 59108 # number of overall misses +system.cpu3.l1c.ReadReq_miss_latency::cpu3 940989779 # number of ReadReq miss cycles +system.cpu3.l1c.ReadReq_miss_latency::total 940989779 # number of ReadReq miss cycles +system.cpu3.l1c.WriteReq_miss_latency::cpu3 850325185 # number of WriteReq miss cycles +system.cpu3.l1c.WriteReq_miss_latency::total 850325185 # number of WriteReq miss cycles +system.cpu3.l1c.demand_miss_latency::cpu3 1791314964 # number of demand (read+write) miss cycles +system.cpu3.l1c.demand_miss_latency::total 1791314964 # number of demand (read+write) miss cycles +system.cpu3.l1c.overall_miss_latency::cpu3 1791314964 # number of overall miss cycles +system.cpu3.l1c.overall_miss_latency::total 1791314964 # number of overall miss cycles +system.cpu3.l1c.ReadReq_accesses::cpu3 44888 # number of ReadReq accesses(hits+misses) +system.cpu3.l1c.ReadReq_accesses::total 44888 # number of ReadReq accesses(hits+misses) +system.cpu3.l1c.WriteReq_accesses::cpu3 24110 # number of WriteReq accesses(hits+misses) +system.cpu3.l1c.WriteReq_accesses::total 24110 # number of WriteReq accesses(hits+misses) +system.cpu3.l1c.demand_accesses::cpu3 68998 # number of demand (read+write) accesses +system.cpu3.l1c.demand_accesses::total 68998 # number of demand (read+write) accesses +system.cpu3.l1c.overall_accesses::cpu3 68998 # number of overall (read+write) accesses +system.cpu3.l1c.overall_accesses::total 68998 # number of overall (read+write) accesses +system.cpu3.l1c.ReadReq_miss_rate::cpu3 0.804380 # miss rate for ReadReq accesses +system.cpu3.l1c.ReadReq_miss_rate::total 0.804380 # miss rate for ReadReq accesses +system.cpu3.l1c.WriteReq_miss_rate::cpu3 0.954002 # miss rate for WriteReq accesses +system.cpu3.l1c.WriteReq_miss_rate::total 0.954002 # miss rate for WriteReq accesses +system.cpu3.l1c.demand_miss_rate::cpu3 0.856663 # miss rate for demand accesses +system.cpu3.l1c.demand_miss_rate::total 0.856663 # miss rate for demand accesses +system.cpu3.l1c.overall_miss_rate::cpu3 0.856663 # miss rate for overall accesses +system.cpu3.l1c.overall_miss_rate::total 0.856663 # miss rate for overall accesses +system.cpu3.l1c.ReadReq_avg_miss_latency::cpu3 26061.145457 # average ReadReq miss latency +system.cpu3.l1c.ReadReq_avg_miss_latency::total 26061.145457 # average ReadReq miss latency +system.cpu3.l1c.WriteReq_avg_miss_latency::cpu3 36969.052867 # average WriteReq miss latency +system.cpu3.l1c.WriteReq_avg_miss_latency::total 36969.052867 # average WriteReq miss latency +system.cpu3.l1c.demand_avg_miss_latency::cpu3 30305.795561 # average overall miss latency +system.cpu3.l1c.demand_avg_miss_latency::total 30305.795561 # average overall miss latency +system.cpu3.l1c.overall_avg_miss_latency::cpu3 30305.795561 # average overall miss latency +system.cpu3.l1c.overall_avg_miss_latency::total 30305.795561 # average overall miss latency +system.cpu3.l1c.blocked_cycles::no_mshrs 1013074 # number of cycles access was blocked system.cpu3.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu3.l1c.blocked::no_mshrs 61773 # number of cycles access was blocked +system.cpu3.l1c.blocked::no_mshrs 62000 # number of cycles access was blocked system.cpu3.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu3.l1c.avg_blocked_cycles::no_mshrs 16.369628 # average number of cycles each access was blocked +system.cpu3.l1c.avg_blocked_cycles::no_mshrs 16.339903 # average number of cycles each access was blocked system.cpu3.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu3.l1c.fast_writes 0 # number of fast writes performed system.cpu3.l1c.cache_copies 0 # number of cache copies performed -system.cpu3.l1c.writebacks::writebacks 9447 # number of writebacks -system.cpu3.l1c.writebacks::total 9447 # number of writebacks -system.cpu3.l1c.ReadReq_mshr_misses::cpu3 35942 # number of ReadReq MSHR misses -system.cpu3.l1c.ReadReq_mshr_misses::total 35942 # number of ReadReq MSHR misses -system.cpu3.l1c.WriteReq_mshr_misses::cpu3 22767 # number of WriteReq MSHR misses -system.cpu3.l1c.WriteReq_mshr_misses::total 22767 # number of WriteReq MSHR misses -system.cpu3.l1c.demand_mshr_misses::cpu3 58709 # number of demand (read+write) MSHR misses -system.cpu3.l1c.demand_mshr_misses::total 58709 # number of demand (read+write) MSHR misses -system.cpu3.l1c.overall_mshr_misses::cpu3 58709 # number of overall MSHR misses -system.cpu3.l1c.overall_mshr_misses::total 58709 # number of overall MSHR misses -system.cpu3.l1c.ReadReq_mshr_miss_latency::cpu3 865819865 # number of ReadReq MSHR miss cycles -system.cpu3.l1c.ReadReq_mshr_miss_latency::total 865819865 # number of ReadReq MSHR miss cycles -system.cpu3.l1c.WriteReq_mshr_miss_latency::cpu3 794633661 # number of WriteReq MSHR miss cycles -system.cpu3.l1c.WriteReq_mshr_miss_latency::total 794633661 # number of WriteReq MSHR miss cycles -system.cpu3.l1c.demand_mshr_miss_latency::cpu3 1660453526 # number of demand (read+write) MSHR miss cycles -system.cpu3.l1c.demand_mshr_miss_latency::total 1660453526 # number of demand (read+write) MSHR miss cycles -system.cpu3.l1c.overall_mshr_miss_latency::cpu3 1660453526 # number of overall MSHR miss cycles -system.cpu3.l1c.overall_mshr_miss_latency::total 1660453526 # number of overall MSHR miss cycles -system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::cpu3 705869404 # number of ReadReq MSHR uncacheable cycles -system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::total 705869404 # number of ReadReq MSHR uncacheable cycles -system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::cpu3 1670668640 # number of WriteReq MSHR uncacheable cycles -system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::total 1670668640 # number of WriteReq MSHR uncacheable cycles -system.cpu3.l1c.overall_mshr_uncacheable_latency::cpu3 2376538044 # number of overall MSHR uncacheable cycles -system.cpu3.l1c.overall_mshr_uncacheable_latency::total 2376538044 # number of overall MSHR uncacheable cycles -system.cpu3.l1c.ReadReq_mshr_miss_rate::cpu3 0.810088 # mshr miss rate for ReadReq accesses -system.cpu3.l1c.ReadReq_mshr_miss_rate::total 0.810088 # mshr miss rate for ReadReq accesses -system.cpu3.l1c.WriteReq_mshr_miss_rate::cpu3 0.955072 # mshr miss rate for WriteReq accesses -system.cpu3.l1c.WriteReq_mshr_miss_rate::total 0.955072 # mshr miss rate for WriteReq accesses -system.cpu3.l1c.demand_mshr_miss_rate::cpu3 0.860760 # mshr miss rate for demand accesses -system.cpu3.l1c.demand_mshr_miss_rate::total 0.860760 # mshr miss rate for demand accesses -system.cpu3.l1c.overall_mshr_miss_rate::cpu3 0.860760 # mshr miss rate for overall accesses -system.cpu3.l1c.overall_mshr_miss_rate::total 0.860760 # mshr miss rate for overall accesses -system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::cpu3 24089.362445 # average ReadReq mshr miss latency -system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::total 24089.362445 # average ReadReq mshr miss latency -system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::cpu3 34902.870866 # average WriteReq mshr miss latency -system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::total 34902.870866 # average WriteReq mshr miss latency -system.cpu3.l1c.demand_avg_mshr_miss_latency::cpu3 28282.776508 # average overall mshr miss latency -system.cpu3.l1c.demand_avg_mshr_miss_latency::total 28282.776508 # average overall mshr miss latency -system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 28282.776508 # average overall mshr miss latency -system.cpu3.l1c.overall_avg_mshr_miss_latency::total 28282.776508 # average overall mshr miss latency +system.cpu3.l1c.writebacks::writebacks 9786 # number of writebacks +system.cpu3.l1c.writebacks::total 9786 # number of writebacks +system.cpu3.l1c.ReadReq_mshr_misses::cpu3 36107 # number of ReadReq MSHR misses +system.cpu3.l1c.ReadReq_mshr_misses::total 36107 # number of ReadReq MSHR misses +system.cpu3.l1c.WriteReq_mshr_misses::cpu3 23001 # number of WriteReq MSHR misses +system.cpu3.l1c.WriteReq_mshr_misses::total 23001 # number of WriteReq MSHR misses +system.cpu3.l1c.demand_mshr_misses::cpu3 59108 # number of demand (read+write) MSHR misses +system.cpu3.l1c.demand_mshr_misses::total 59108 # number of demand (read+write) MSHR misses +system.cpu3.l1c.overall_mshr_misses::cpu3 59108 # number of overall MSHR misses +system.cpu3.l1c.overall_mshr_misses::total 59108 # number of overall MSHR misses +system.cpu3.l1c.ReadReq_mshr_miss_latency::cpu3 863727177 # number of ReadReq MSHR miss cycles +system.cpu3.l1c.ReadReq_mshr_miss_latency::total 863727177 # number of ReadReq MSHR miss cycles +system.cpu3.l1c.WriteReq_mshr_miss_latency::cpu3 801703041 # number of WriteReq MSHR miss cycles +system.cpu3.l1c.WriteReq_mshr_miss_latency::total 801703041 # number of WriteReq MSHR miss cycles +system.cpu3.l1c.demand_mshr_miss_latency::cpu3 1665430218 # number of demand (read+write) MSHR miss cycles +system.cpu3.l1c.demand_mshr_miss_latency::total 1665430218 # number of demand (read+write) MSHR miss cycles +system.cpu3.l1c.overall_mshr_miss_latency::cpu3 1665430218 # number of overall MSHR miss cycles +system.cpu3.l1c.overall_mshr_miss_latency::total 1665430218 # number of overall MSHR miss cycles +system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::cpu3 709371346 # number of ReadReq MSHR uncacheable cycles +system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::total 709371346 # number of ReadReq MSHR uncacheable cycles +system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::cpu3 1619504156 # number of WriteReq MSHR uncacheable cycles +system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::total 1619504156 # number of WriteReq MSHR uncacheable cycles +system.cpu3.l1c.overall_mshr_uncacheable_latency::cpu3 2328875502 # number of overall MSHR uncacheable cycles +system.cpu3.l1c.overall_mshr_uncacheable_latency::total 2328875502 # number of overall MSHR uncacheable cycles +system.cpu3.l1c.ReadReq_mshr_miss_rate::cpu3 0.804380 # mshr miss rate for ReadReq accesses +system.cpu3.l1c.ReadReq_mshr_miss_rate::total 0.804380 # mshr miss rate for ReadReq accesses +system.cpu3.l1c.WriteReq_mshr_miss_rate::cpu3 0.954002 # mshr miss rate for WriteReq accesses +system.cpu3.l1c.WriteReq_mshr_miss_rate::total 0.954002 # mshr miss rate for WriteReq accesses +system.cpu3.l1c.demand_mshr_miss_rate::cpu3 0.856663 # mshr miss rate for demand accesses +system.cpu3.l1c.demand_mshr_miss_rate::total 0.856663 # mshr miss rate for demand accesses +system.cpu3.l1c.overall_mshr_miss_rate::cpu3 0.856663 # mshr miss rate for overall accesses +system.cpu3.l1c.overall_mshr_miss_rate::total 0.856663 # mshr miss rate for overall accesses +system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::cpu3 23921.322098 # average ReadReq mshr miss latency +system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::total 23921.322098 # average ReadReq mshr miss latency +system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::cpu3 34855.138516 # average WriteReq mshr miss latency +system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::total 34855.138516 # average WriteReq mshr miss latency +system.cpu3.l1c.demand_avg_mshr_miss_latency::cpu3 28176.054307 # average overall mshr miss latency +system.cpu3.l1c.demand_avg_mshr_miss_latency::total 28176.054307 # average overall mshr miss latency +system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 28176.054307 # average overall mshr miss latency +system.cpu3.l1c.overall_avg_mshr_miss_latency::total 28176.054307 # average overall mshr miss latency system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu3 inf # average ReadReq mshr uncacheable latency system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu3 inf # average WriteReq mshr uncacheable latency @@ -1190,114 +1188,114 @@ system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::cpu3 inf # average overall mshr uncacheable latency system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu3.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu4.num_reads 98567 # number of read accesses completed -system.cpu4.num_writes 53142 # number of write accesses completed +system.cpu4.num_reads 99830 # number of read accesses completed +system.cpu4.num_writes 54064 # number of write accesses completed system.cpu4.num_copies 0 # number of copy accesses completed -system.cpu4.l1c.replacements 21884 # number of replacements -system.cpu4.l1c.tagsinuse 394.848687 # Cycle average of tags in use -system.cpu4.l1c.total_refs 13028 # Total number of references to valid blocks. -system.cpu4.l1c.sampled_refs 22289 # Sample count of references to valid blocks. -system.cpu4.l1c.avg_refs 0.584504 # Average number of references to valid blocks. -system.cpu4.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu4.l1c.occ_blocks::cpu4 394.848687 # Average occupied blocks per requestor -system.cpu4.l1c.occ_percent::cpu4 0.771189 # Average percentage of cache occupancy -system.cpu4.l1c.occ_percent::total 0.771189 # Average percentage of cache occupancy -system.cpu4.l1c.ReadReq_hits::cpu4 8503 # number of ReadReq hits -system.cpu4.l1c.ReadReq_hits::total 8503 # number of ReadReq hits -system.cpu4.l1c.WriteReq_hits::cpu4 1105 # number of WriteReq hits -system.cpu4.l1c.WriteReq_hits::total 1105 # number of WriteReq hits -system.cpu4.l1c.demand_hits::cpu4 9608 # number of demand (read+write) hits -system.cpu4.l1c.demand_hits::total 9608 # number of demand (read+write) hits -system.cpu4.l1c.overall_hits::cpu4 9608 # number of overall hits -system.cpu4.l1c.overall_hits::total 9608 # number of overall hits -system.cpu4.l1c.ReadReq_misses::cpu4 35561 # number of ReadReq misses -system.cpu4.l1c.ReadReq_misses::total 35561 # number of ReadReq misses -system.cpu4.l1c.WriteReq_misses::cpu4 23022 # number of WriteReq misses -system.cpu4.l1c.WriteReq_misses::total 23022 # number of WriteReq misses -system.cpu4.l1c.demand_misses::cpu4 58583 # number of demand (read+write) misses -system.cpu4.l1c.demand_misses::total 58583 # number of demand (read+write) misses -system.cpu4.l1c.overall_misses::cpu4 58583 # number of overall misses -system.cpu4.l1c.overall_misses::total 58583 # number of overall misses -system.cpu4.l1c.ReadReq_miss_latency::cpu4 936314772 # number of ReadReq miss cycles -system.cpu4.l1c.ReadReq_miss_latency::total 936314772 # number of ReadReq miss cycles -system.cpu4.l1c.WriteReq_miss_latency::cpu4 859386922 # number of WriteReq miss cycles -system.cpu4.l1c.WriteReq_miss_latency::total 859386922 # number of WriteReq miss cycles -system.cpu4.l1c.demand_miss_latency::cpu4 1795701694 # number of demand (read+write) miss cycles -system.cpu4.l1c.demand_miss_latency::total 1795701694 # number of demand (read+write) miss cycles -system.cpu4.l1c.overall_miss_latency::cpu4 1795701694 # number of overall miss cycles -system.cpu4.l1c.overall_miss_latency::total 1795701694 # number of overall miss cycles -system.cpu4.l1c.ReadReq_accesses::cpu4 44064 # number of ReadReq accesses(hits+misses) -system.cpu4.l1c.ReadReq_accesses::total 44064 # number of ReadReq accesses(hits+misses) -system.cpu4.l1c.WriteReq_accesses::cpu4 24127 # number of WriteReq accesses(hits+misses) -system.cpu4.l1c.WriteReq_accesses::total 24127 # number of WriteReq accesses(hits+misses) -system.cpu4.l1c.demand_accesses::cpu4 68191 # number of demand (read+write) accesses -system.cpu4.l1c.demand_accesses::total 68191 # number of demand (read+write) accesses -system.cpu4.l1c.overall_accesses::cpu4 68191 # number of overall (read+write) accesses -system.cpu4.l1c.overall_accesses::total 68191 # number of overall (read+write) accesses -system.cpu4.l1c.ReadReq_miss_rate::cpu4 0.807031 # miss rate for ReadReq accesses -system.cpu4.l1c.ReadReq_miss_rate::total 0.807031 # miss rate for ReadReq accesses -system.cpu4.l1c.WriteReq_miss_rate::cpu4 0.954201 # miss rate for WriteReq accesses -system.cpu4.l1c.WriteReq_miss_rate::total 0.954201 # miss rate for WriteReq accesses -system.cpu4.l1c.demand_miss_rate::cpu4 0.859102 # miss rate for demand accesses -system.cpu4.l1c.demand_miss_rate::total 0.859102 # miss rate for demand accesses -system.cpu4.l1c.overall_miss_rate::cpu4 0.859102 # miss rate for overall accesses -system.cpu4.l1c.overall_miss_rate::total 0.859102 # miss rate for overall accesses -system.cpu4.l1c.ReadReq_avg_miss_latency::cpu4 26329.821209 # average ReadReq miss latency -system.cpu4.l1c.ReadReq_avg_miss_latency::total 26329.821209 # average ReadReq miss latency -system.cpu4.l1c.WriteReq_avg_miss_latency::cpu4 37328.942837 # average WriteReq miss latency -system.cpu4.l1c.WriteReq_avg_miss_latency::total 37328.942837 # average WriteReq miss latency -system.cpu4.l1c.demand_avg_miss_latency::cpu4 30652.265913 # average overall miss latency -system.cpu4.l1c.demand_avg_miss_latency::total 30652.265913 # average overall miss latency -system.cpu4.l1c.overall_avg_miss_latency::cpu4 30652.265913 # average overall miss latency -system.cpu4.l1c.overall_avg_miss_latency::total 30652.265913 # average overall miss latency -system.cpu4.l1c.blocked_cycles::no_mshrs 1016374 # number of cycles access was blocked +system.cpu4.l1c.tags.replacements 22082 # number of replacements +system.cpu4.l1c.tags.tagsinuse 393.544066 # Cycle average of tags in use +system.cpu4.l1c.tags.total_refs 13201 # Total number of references to valid blocks. +system.cpu4.l1c.tags.sampled_refs 22486 # Sample count of references to valid blocks. +system.cpu4.l1c.tags.avg_refs 0.587076 # Average number of references to valid blocks. +system.cpu4.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu4.l1c.tags.occ_blocks::cpu4 393.544066 # Average occupied blocks per requestor +system.cpu4.l1c.tags.occ_percent::cpu4 0.768641 # Average percentage of cache occupancy +system.cpu4.l1c.tags.occ_percent::total 0.768641 # Average percentage of cache occupancy +system.cpu4.l1c.ReadReq_hits::cpu4 8712 # number of ReadReq hits +system.cpu4.l1c.ReadReq_hits::total 8712 # number of ReadReq hits +system.cpu4.l1c.WriteReq_hits::cpu4 1102 # number of WriteReq hits +system.cpu4.l1c.WriteReq_hits::total 1102 # number of WriteReq hits +system.cpu4.l1c.demand_hits::cpu4 9814 # number of demand (read+write) hits +system.cpu4.l1c.demand_hits::total 9814 # number of demand (read+write) hits +system.cpu4.l1c.overall_hits::cpu4 9814 # number of overall hits +system.cpu4.l1c.overall_hits::total 9814 # number of overall hits +system.cpu4.l1c.ReadReq_misses::cpu4 35977 # number of ReadReq misses +system.cpu4.l1c.ReadReq_misses::total 35977 # number of ReadReq misses +system.cpu4.l1c.WriteReq_misses::cpu4 23176 # number of WriteReq misses +system.cpu4.l1c.WriteReq_misses::total 23176 # number of WriteReq misses +system.cpu4.l1c.demand_misses::cpu4 59153 # number of demand (read+write) misses +system.cpu4.l1c.demand_misses::total 59153 # number of demand (read+write) misses +system.cpu4.l1c.overall_misses::cpu4 59153 # number of overall misses +system.cpu4.l1c.overall_misses::total 59153 # number of overall misses +system.cpu4.l1c.ReadReq_miss_latency::cpu4 943945635 # number of ReadReq miss cycles +system.cpu4.l1c.ReadReq_miss_latency::total 943945635 # number of ReadReq miss cycles +system.cpu4.l1c.WriteReq_miss_latency::cpu4 856485364 # number of WriteReq miss cycles +system.cpu4.l1c.WriteReq_miss_latency::total 856485364 # number of WriteReq miss cycles +system.cpu4.l1c.demand_miss_latency::cpu4 1800430999 # number of demand (read+write) miss cycles +system.cpu4.l1c.demand_miss_latency::total 1800430999 # number of demand (read+write) miss cycles +system.cpu4.l1c.overall_miss_latency::cpu4 1800430999 # number of overall miss cycles +system.cpu4.l1c.overall_miss_latency::total 1800430999 # number of overall miss cycles +system.cpu4.l1c.ReadReq_accesses::cpu4 44689 # number of ReadReq accesses(hits+misses) +system.cpu4.l1c.ReadReq_accesses::total 44689 # number of ReadReq accesses(hits+misses) +system.cpu4.l1c.WriteReq_accesses::cpu4 24278 # number of WriteReq accesses(hits+misses) +system.cpu4.l1c.WriteReq_accesses::total 24278 # number of WriteReq accesses(hits+misses) +system.cpu4.l1c.demand_accesses::cpu4 68967 # number of demand (read+write) accesses +system.cpu4.l1c.demand_accesses::total 68967 # number of demand (read+write) accesses +system.cpu4.l1c.overall_accesses::cpu4 68967 # number of overall (read+write) accesses +system.cpu4.l1c.overall_accesses::total 68967 # number of overall (read+write) accesses +system.cpu4.l1c.ReadReq_miss_rate::cpu4 0.805053 # miss rate for ReadReq accesses +system.cpu4.l1c.ReadReq_miss_rate::total 0.805053 # miss rate for ReadReq accesses +system.cpu4.l1c.WriteReq_miss_rate::cpu4 0.954609 # miss rate for WriteReq accesses +system.cpu4.l1c.WriteReq_miss_rate::total 0.954609 # miss rate for WriteReq accesses +system.cpu4.l1c.demand_miss_rate::cpu4 0.857700 # miss rate for demand accesses +system.cpu4.l1c.demand_miss_rate::total 0.857700 # miss rate for demand accesses +system.cpu4.l1c.overall_miss_rate::cpu4 0.857700 # miss rate for overall accesses +system.cpu4.l1c.overall_miss_rate::total 0.857700 # miss rate for overall accesses +system.cpu4.l1c.ReadReq_avg_miss_latency::cpu4 26237.474915 # average ReadReq miss latency +system.cpu4.l1c.ReadReq_avg_miss_latency::total 26237.474915 # average ReadReq miss latency +system.cpu4.l1c.WriteReq_avg_miss_latency::cpu4 36955.702623 # average WriteReq miss latency +system.cpu4.l1c.WriteReq_avg_miss_latency::total 36955.702623 # average WriteReq miss latency +system.cpu4.l1c.demand_avg_miss_latency::cpu4 30436.850185 # average overall miss latency +system.cpu4.l1c.demand_avg_miss_latency::total 30436.850185 # average overall miss latency +system.cpu4.l1c.overall_avg_miss_latency::cpu4 30436.850185 # average overall miss latency +system.cpu4.l1c.overall_avg_miss_latency::total 30436.850185 # average overall miss latency +system.cpu4.l1c.blocked_cycles::no_mshrs 1017670 # number of cycles access was blocked system.cpu4.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu4.l1c.blocked::no_mshrs 61728 # number of cycles access was blocked +system.cpu4.l1c.blocked::no_mshrs 62294 # number of cycles access was blocked system.cpu4.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu4.l1c.avg_blocked_cycles::no_mshrs 16.465364 # average number of cycles each access was blocked +system.cpu4.l1c.avg_blocked_cycles::no_mshrs 16.336565 # average number of cycles each access was blocked system.cpu4.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu4.l1c.fast_writes 0 # number of fast writes performed system.cpu4.l1c.cache_copies 0 # number of cache copies performed -system.cpu4.l1c.writebacks::writebacks 9520 # number of writebacks -system.cpu4.l1c.writebacks::total 9520 # number of writebacks -system.cpu4.l1c.ReadReq_mshr_misses::cpu4 35561 # number of ReadReq MSHR misses -system.cpu4.l1c.ReadReq_mshr_misses::total 35561 # number of ReadReq MSHR misses -system.cpu4.l1c.WriteReq_mshr_misses::cpu4 23022 # number of WriteReq MSHR misses -system.cpu4.l1c.WriteReq_mshr_misses::total 23022 # number of WriteReq MSHR misses -system.cpu4.l1c.demand_mshr_misses::cpu4 58583 # number of demand (read+write) MSHR misses -system.cpu4.l1c.demand_mshr_misses::total 58583 # number of demand (read+write) MSHR misses -system.cpu4.l1c.overall_mshr_misses::cpu4 58583 # number of overall MSHR misses -system.cpu4.l1c.overall_mshr_misses::total 58583 # number of overall MSHR misses -system.cpu4.l1c.ReadReq_mshr_miss_latency::cpu4 862769237 # number of ReadReq MSHR miss cycles -system.cpu4.l1c.ReadReq_mshr_miss_latency::total 862769237 # number of ReadReq MSHR miss cycles -system.cpu4.l1c.WriteReq_mshr_miss_latency::cpu4 812030378 # number of WriteReq MSHR miss cycles -system.cpu4.l1c.WriteReq_mshr_miss_latency::total 812030378 # number of WriteReq MSHR miss cycles -system.cpu4.l1c.demand_mshr_miss_latency::cpu4 1674799615 # number of demand (read+write) MSHR miss cycles -system.cpu4.l1c.demand_mshr_miss_latency::total 1674799615 # number of demand (read+write) MSHR miss cycles -system.cpu4.l1c.overall_mshr_miss_latency::cpu4 1674799615 # number of overall MSHR miss cycles -system.cpu4.l1c.overall_mshr_miss_latency::total 1674799615 # number of overall MSHR miss cycles -system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::cpu4 700729623 # number of ReadReq MSHR uncacheable cycles -system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::total 700729623 # number of ReadReq MSHR uncacheable cycles -system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::cpu4 1644067080 # number of WriteReq MSHR uncacheable cycles -system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::total 1644067080 # number of WriteReq MSHR uncacheable cycles -system.cpu4.l1c.overall_mshr_uncacheable_latency::cpu4 2344796703 # number of overall MSHR uncacheable cycles -system.cpu4.l1c.overall_mshr_uncacheable_latency::total 2344796703 # number of overall MSHR uncacheable cycles -system.cpu4.l1c.ReadReq_mshr_miss_rate::cpu4 0.807031 # mshr miss rate for ReadReq accesses -system.cpu4.l1c.ReadReq_mshr_miss_rate::total 0.807031 # mshr miss rate for ReadReq accesses -system.cpu4.l1c.WriteReq_mshr_miss_rate::cpu4 0.954201 # mshr miss rate for WriteReq accesses -system.cpu4.l1c.WriteReq_mshr_miss_rate::total 0.954201 # mshr miss rate for WriteReq accesses -system.cpu4.l1c.demand_mshr_miss_rate::cpu4 0.859102 # mshr miss rate for demand accesses -system.cpu4.l1c.demand_mshr_miss_rate::total 0.859102 # mshr miss rate for demand accesses -system.cpu4.l1c.overall_mshr_miss_rate::cpu4 0.859102 # mshr miss rate for overall accesses -system.cpu4.l1c.overall_mshr_miss_rate::total 0.859102 # mshr miss rate for overall accesses -system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::cpu4 24261.669722 # average ReadReq mshr miss latency -system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::total 24261.669722 # average ReadReq mshr miss latency -system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::cpu4 35271.930241 # average WriteReq mshr miss latency -system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::total 35271.930241 # average WriteReq mshr miss latency -system.cpu4.l1c.demand_avg_mshr_miss_latency::cpu4 28588.491798 # average overall mshr miss latency -system.cpu4.l1c.demand_avg_mshr_miss_latency::total 28588.491798 # average overall mshr miss latency -system.cpu4.l1c.overall_avg_mshr_miss_latency::cpu4 28588.491798 # average overall mshr miss latency -system.cpu4.l1c.overall_avg_mshr_miss_latency::total 28588.491798 # average overall mshr miss latency +system.cpu4.l1c.writebacks::writebacks 9622 # number of writebacks +system.cpu4.l1c.writebacks::total 9622 # number of writebacks +system.cpu4.l1c.ReadReq_mshr_misses::cpu4 35977 # number of ReadReq MSHR misses +system.cpu4.l1c.ReadReq_mshr_misses::total 35977 # number of ReadReq MSHR misses +system.cpu4.l1c.WriteReq_mshr_misses::cpu4 23176 # number of WriteReq MSHR misses +system.cpu4.l1c.WriteReq_mshr_misses::total 23176 # number of WriteReq MSHR misses +system.cpu4.l1c.demand_mshr_misses::cpu4 59153 # number of demand (read+write) MSHR misses +system.cpu4.l1c.demand_mshr_misses::total 59153 # number of demand (read+write) MSHR misses +system.cpu4.l1c.overall_mshr_misses::cpu4 59153 # number of overall MSHR misses +system.cpu4.l1c.overall_mshr_misses::total 59153 # number of overall MSHR misses +system.cpu4.l1c.ReadReq_mshr_miss_latency::cpu4 867154515 # number of ReadReq MSHR miss cycles +system.cpu4.l1c.ReadReq_mshr_miss_latency::total 867154515 # number of ReadReq MSHR miss cycles +system.cpu4.l1c.WriteReq_mshr_miss_latency::cpu4 807437346 # number of WriteReq MSHR miss cycles +system.cpu4.l1c.WriteReq_mshr_miss_latency::total 807437346 # number of WriteReq MSHR miss cycles +system.cpu4.l1c.demand_mshr_miss_latency::cpu4 1674591861 # number of demand (read+write) MSHR miss cycles +system.cpu4.l1c.demand_mshr_miss_latency::total 1674591861 # number of demand (read+write) MSHR miss cycles +system.cpu4.l1c.overall_mshr_miss_latency::cpu4 1674591861 # number of overall MSHR miss cycles +system.cpu4.l1c.overall_mshr_miss_latency::total 1674591861 # number of overall MSHR miss cycles +system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::cpu4 707224870 # number of ReadReq MSHR uncacheable cycles +system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::total 707224870 # number of ReadReq MSHR uncacheable cycles +system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::cpu4 1620907679 # number of WriteReq MSHR uncacheable cycles +system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::total 1620907679 # number of WriteReq MSHR uncacheable cycles +system.cpu4.l1c.overall_mshr_uncacheable_latency::cpu4 2328132549 # number of overall MSHR uncacheable cycles +system.cpu4.l1c.overall_mshr_uncacheable_latency::total 2328132549 # number of overall MSHR uncacheable cycles +system.cpu4.l1c.ReadReq_mshr_miss_rate::cpu4 0.805053 # mshr miss rate for ReadReq accesses +system.cpu4.l1c.ReadReq_mshr_miss_rate::total 0.805053 # mshr miss rate for ReadReq accesses +system.cpu4.l1c.WriteReq_mshr_miss_rate::cpu4 0.954609 # mshr miss rate for WriteReq accesses +system.cpu4.l1c.WriteReq_mshr_miss_rate::total 0.954609 # mshr miss rate for WriteReq accesses +system.cpu4.l1c.demand_mshr_miss_rate::cpu4 0.857700 # mshr miss rate for demand accesses +system.cpu4.l1c.demand_mshr_miss_rate::total 0.857700 # mshr miss rate for demand accesses +system.cpu4.l1c.overall_mshr_miss_rate::cpu4 0.857700 # mshr miss rate for overall accesses +system.cpu4.l1c.overall_mshr_miss_rate::total 0.857700 # mshr miss rate for overall accesses +system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::cpu4 24103.024571 # average ReadReq mshr miss latency +system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::total 24103.024571 # average ReadReq mshr miss latency +system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::cpu4 34839.374612 # average WriteReq mshr miss latency +system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::total 34839.374612 # average WriteReq mshr miss latency +system.cpu4.l1c.demand_avg_mshr_miss_latency::cpu4 28309.500127 # average overall mshr miss latency +system.cpu4.l1c.demand_avg_mshr_miss_latency::total 28309.500127 # average overall mshr miss latency +system.cpu4.l1c.overall_avg_mshr_miss_latency::cpu4 28309.500127 # average overall mshr miss latency +system.cpu4.l1c.overall_avg_mshr_miss_latency::total 28309.500127 # average overall mshr miss latency system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu4 inf # average ReadReq mshr uncacheable latency system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu4 inf # average WriteReq mshr uncacheable latency @@ -1305,114 +1303,114 @@ system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::cpu4 inf # average overall mshr uncacheable latency system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu4.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu5.num_reads 98869 # number of read accesses completed -system.cpu5.num_writes 53477 # number of write accesses completed +system.cpu5.num_reads 99630 # number of read accesses completed +system.cpu5.num_writes 53500 # number of write accesses completed system.cpu5.num_copies 0 # number of copy accesses completed -system.cpu5.l1c.replacements 22131 # number of replacements -system.cpu5.l1c.tagsinuse 394.954130 # Cycle average of tags in use -system.cpu5.l1c.total_refs 13197 # Total number of references to valid blocks. -system.cpu5.l1c.sampled_refs 22529 # Sample count of references to valid blocks. -system.cpu5.l1c.avg_refs 0.585778 # Average number of references to valid blocks. -system.cpu5.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu5.l1c.occ_blocks::cpu5 394.954130 # Average occupied blocks per requestor -system.cpu5.l1c.occ_percent::cpu5 0.771395 # Average percentage of cache occupancy -system.cpu5.l1c.occ_percent::total 0.771395 # Average percentage of cache occupancy -system.cpu5.l1c.ReadReq_hits::cpu5 8594 # number of ReadReq hits -system.cpu5.l1c.ReadReq_hits::total 8594 # number of ReadReq hits -system.cpu5.l1c.WriteReq_hits::cpu5 1100 # number of WriteReq hits -system.cpu5.l1c.WriteReq_hits::total 1100 # number of WriteReq hits -system.cpu5.l1c.demand_hits::cpu5 9694 # number of demand (read+write) hits -system.cpu5.l1c.demand_hits::total 9694 # number of demand (read+write) hits -system.cpu5.l1c.overall_hits::cpu5 9694 # number of overall hits -system.cpu5.l1c.overall_hits::total 9694 # number of overall hits -system.cpu5.l1c.ReadReq_misses::cpu5 35827 # number of ReadReq misses -system.cpu5.l1c.ReadReq_misses::total 35827 # number of ReadReq misses -system.cpu5.l1c.WriteReq_misses::cpu5 23090 # number of WriteReq misses -system.cpu5.l1c.WriteReq_misses::total 23090 # number of WriteReq misses -system.cpu5.l1c.demand_misses::cpu5 58917 # number of demand (read+write) misses -system.cpu5.l1c.demand_misses::total 58917 # number of demand (read+write) misses -system.cpu5.l1c.overall_misses::cpu5 58917 # number of overall misses -system.cpu5.l1c.overall_misses::total 58917 # number of overall misses -system.cpu5.l1c.ReadReq_miss_latency::cpu5 936035832 # number of ReadReq miss cycles -system.cpu5.l1c.ReadReq_miss_latency::total 936035832 # number of ReadReq miss cycles -system.cpu5.l1c.WriteReq_miss_latency::cpu5 858178388 # number of WriteReq miss cycles -system.cpu5.l1c.WriteReq_miss_latency::total 858178388 # number of WriteReq miss cycles -system.cpu5.l1c.demand_miss_latency::cpu5 1794214220 # number of demand (read+write) miss cycles -system.cpu5.l1c.demand_miss_latency::total 1794214220 # number of demand (read+write) miss cycles -system.cpu5.l1c.overall_miss_latency::cpu5 1794214220 # number of overall miss cycles -system.cpu5.l1c.overall_miss_latency::total 1794214220 # number of overall miss cycles -system.cpu5.l1c.ReadReq_accesses::cpu5 44421 # number of ReadReq accesses(hits+misses) -system.cpu5.l1c.ReadReq_accesses::total 44421 # number of ReadReq accesses(hits+misses) -system.cpu5.l1c.WriteReq_accesses::cpu5 24190 # number of WriteReq accesses(hits+misses) -system.cpu5.l1c.WriteReq_accesses::total 24190 # number of WriteReq accesses(hits+misses) -system.cpu5.l1c.demand_accesses::cpu5 68611 # number of demand (read+write) accesses -system.cpu5.l1c.demand_accesses::total 68611 # number of demand (read+write) accesses -system.cpu5.l1c.overall_accesses::cpu5 68611 # number of overall (read+write) accesses -system.cpu5.l1c.overall_accesses::total 68611 # number of overall (read+write) accesses -system.cpu5.l1c.ReadReq_miss_rate::cpu5 0.806533 # miss rate for ReadReq accesses -system.cpu5.l1c.ReadReq_miss_rate::total 0.806533 # miss rate for ReadReq accesses -system.cpu5.l1c.WriteReq_miss_rate::cpu5 0.954527 # miss rate for WriteReq accesses -system.cpu5.l1c.WriteReq_miss_rate::total 0.954527 # miss rate for WriteReq accesses -system.cpu5.l1c.demand_miss_rate::cpu5 0.858711 # miss rate for demand accesses -system.cpu5.l1c.demand_miss_rate::total 0.858711 # miss rate for demand accesses -system.cpu5.l1c.overall_miss_rate::cpu5 0.858711 # miss rate for overall accesses -system.cpu5.l1c.overall_miss_rate::total 0.858711 # miss rate for overall accesses -system.cpu5.l1c.ReadReq_avg_miss_latency::cpu5 26126.547911 # average ReadReq miss latency -system.cpu5.l1c.ReadReq_avg_miss_latency::total 26126.547911 # average ReadReq miss latency -system.cpu5.l1c.WriteReq_avg_miss_latency::cpu5 37166.669034 # average WriteReq miss latency -system.cpu5.l1c.WriteReq_avg_miss_latency::total 37166.669034 # average WriteReq miss latency -system.cpu5.l1c.demand_avg_miss_latency::cpu5 30453.251523 # average overall miss latency -system.cpu5.l1c.demand_avg_miss_latency::total 30453.251523 # average overall miss latency -system.cpu5.l1c.overall_avg_miss_latency::cpu5 30453.251523 # average overall miss latency -system.cpu5.l1c.overall_avg_miss_latency::total 30453.251523 # average overall miss latency -system.cpu5.l1c.blocked_cycles::no_mshrs 1010232 # number of cycles access was blocked +system.cpu5.l1c.tags.replacements 22051 # number of replacements +system.cpu5.l1c.tags.tagsinuse 395.592742 # Cycle average of tags in use +system.cpu5.l1c.tags.total_refs 13484 # Total number of references to valid blocks. +system.cpu5.l1c.tags.sampled_refs 22450 # Sample count of references to valid blocks. +system.cpu5.l1c.tags.avg_refs 0.600624 # Average number of references to valid blocks. +system.cpu5.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu5.l1c.tags.occ_blocks::cpu5 395.592742 # Average occupied blocks per requestor +system.cpu5.l1c.tags.occ_percent::cpu5 0.772642 # Average percentage of cache occupancy +system.cpu5.l1c.tags.occ_percent::total 0.772642 # Average percentage of cache occupancy +system.cpu5.l1c.ReadReq_hits::cpu5 8824 # number of ReadReq hits +system.cpu5.l1c.ReadReq_hits::total 8824 # number of ReadReq hits +system.cpu5.l1c.WriteReq_hits::cpu5 1160 # number of WriteReq hits +system.cpu5.l1c.WriteReq_hits::total 1160 # number of WriteReq hits +system.cpu5.l1c.demand_hits::cpu5 9984 # number of demand (read+write) hits +system.cpu5.l1c.demand_hits::total 9984 # number of demand (read+write) hits +system.cpu5.l1c.overall_hits::cpu5 9984 # number of overall hits +system.cpu5.l1c.overall_hits::total 9984 # number of overall hits +system.cpu5.l1c.ReadReq_misses::cpu5 36108 # number of ReadReq misses +system.cpu5.l1c.ReadReq_misses::total 36108 # number of ReadReq misses +system.cpu5.l1c.WriteReq_misses::cpu5 23031 # number of WriteReq misses +system.cpu5.l1c.WriteReq_misses::total 23031 # number of WriteReq misses +system.cpu5.l1c.demand_misses::cpu5 59139 # number of demand (read+write) misses +system.cpu5.l1c.demand_misses::total 59139 # number of demand (read+write) misses +system.cpu5.l1c.overall_misses::cpu5 59139 # number of overall misses +system.cpu5.l1c.overall_misses::total 59139 # number of overall misses +system.cpu5.l1c.ReadReq_miss_latency::cpu5 948980493 # number of ReadReq miss cycles +system.cpu5.l1c.ReadReq_miss_latency::total 948980493 # number of ReadReq miss cycles +system.cpu5.l1c.WriteReq_miss_latency::cpu5 861190152 # number of WriteReq miss cycles +system.cpu5.l1c.WriteReq_miss_latency::total 861190152 # number of WriteReq miss cycles +system.cpu5.l1c.demand_miss_latency::cpu5 1810170645 # number of demand (read+write) miss cycles +system.cpu5.l1c.demand_miss_latency::total 1810170645 # number of demand (read+write) miss cycles +system.cpu5.l1c.overall_miss_latency::cpu5 1810170645 # number of overall miss cycles +system.cpu5.l1c.overall_miss_latency::total 1810170645 # number of overall miss cycles +system.cpu5.l1c.ReadReq_accesses::cpu5 44932 # number of ReadReq accesses(hits+misses) +system.cpu5.l1c.ReadReq_accesses::total 44932 # number of ReadReq accesses(hits+misses) +system.cpu5.l1c.WriteReq_accesses::cpu5 24191 # number of WriteReq accesses(hits+misses) +system.cpu5.l1c.WriteReq_accesses::total 24191 # number of WriteReq accesses(hits+misses) +system.cpu5.l1c.demand_accesses::cpu5 69123 # number of demand (read+write) accesses +system.cpu5.l1c.demand_accesses::total 69123 # number of demand (read+write) accesses +system.cpu5.l1c.overall_accesses::cpu5 69123 # number of overall (read+write) accesses +system.cpu5.l1c.overall_accesses::total 69123 # number of overall (read+write) accesses +system.cpu5.l1c.ReadReq_miss_rate::cpu5 0.803614 # miss rate for ReadReq accesses +system.cpu5.l1c.ReadReq_miss_rate::total 0.803614 # miss rate for ReadReq accesses +system.cpu5.l1c.WriteReq_miss_rate::cpu5 0.952048 # miss rate for WriteReq accesses +system.cpu5.l1c.WriteReq_miss_rate::total 0.952048 # miss rate for WriteReq accesses +system.cpu5.l1c.demand_miss_rate::cpu5 0.855562 # miss rate for demand accesses +system.cpu5.l1c.demand_miss_rate::total 0.855562 # miss rate for demand accesses +system.cpu5.l1c.overall_miss_rate::cpu5 0.855562 # miss rate for overall accesses +system.cpu5.l1c.overall_miss_rate::total 0.855562 # miss rate for overall accesses +system.cpu5.l1c.ReadReq_avg_miss_latency::cpu5 26281.724078 # average ReadReq miss latency +system.cpu5.l1c.ReadReq_avg_miss_latency::total 26281.724078 # average ReadReq miss latency +system.cpu5.l1c.WriteReq_avg_miss_latency::cpu5 37392.651296 # average WriteReq miss latency +system.cpu5.l1c.WriteReq_avg_miss_latency::total 37392.651296 # average WriteReq miss latency +system.cpu5.l1c.demand_avg_miss_latency::cpu5 30608.746259 # average overall miss latency +system.cpu5.l1c.demand_avg_miss_latency::total 30608.746259 # average overall miss latency +system.cpu5.l1c.overall_avg_miss_latency::cpu5 30608.746259 # average overall miss latency +system.cpu5.l1c.overall_avg_miss_latency::total 30608.746259 # average overall miss latency +system.cpu5.l1c.blocked_cycles::no_mshrs 1024769 # number of cycles access was blocked system.cpu5.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu5.l1c.blocked::no_mshrs 61688 # number of cycles access was blocked +system.cpu5.l1c.blocked::no_mshrs 62427 # number of cycles access was blocked system.cpu5.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu5.l1c.avg_blocked_cycles::no_mshrs 16.376475 # average number of cycles each access was blocked +system.cpu5.l1c.avg_blocked_cycles::no_mshrs 16.415477 # average number of cycles each access was blocked system.cpu5.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu5.l1c.fast_writes 0 # number of fast writes performed system.cpu5.l1c.cache_copies 0 # number of cache copies performed -system.cpu5.l1c.writebacks::writebacks 9611 # number of writebacks -system.cpu5.l1c.writebacks::total 9611 # number of writebacks -system.cpu5.l1c.ReadReq_mshr_misses::cpu5 35827 # number of ReadReq MSHR misses -system.cpu5.l1c.ReadReq_mshr_misses::total 35827 # number of ReadReq MSHR misses -system.cpu5.l1c.WriteReq_mshr_misses::cpu5 23090 # number of WriteReq MSHR misses -system.cpu5.l1c.WriteReq_mshr_misses::total 23090 # number of WriteReq MSHR misses -system.cpu5.l1c.demand_mshr_misses::cpu5 58917 # number of demand (read+write) MSHR misses -system.cpu5.l1c.demand_mshr_misses::total 58917 # number of demand (read+write) MSHR misses -system.cpu5.l1c.overall_mshr_misses::cpu5 58917 # number of overall MSHR misses -system.cpu5.l1c.overall_mshr_misses::total 58917 # number of overall MSHR misses -system.cpu5.l1c.ReadReq_mshr_miss_latency::cpu5 861924856 # number of ReadReq MSHR miss cycles -system.cpu5.l1c.ReadReq_mshr_miss_latency::total 861924856 # number of ReadReq MSHR miss cycles -system.cpu5.l1c.WriteReq_mshr_miss_latency::cpu5 810652413 # number of WriteReq MSHR miss cycles -system.cpu5.l1c.WriteReq_mshr_miss_latency::total 810652413 # number of WriteReq MSHR miss cycles -system.cpu5.l1c.demand_mshr_miss_latency::cpu5 1672577269 # number of demand (read+write) MSHR miss cycles -system.cpu5.l1c.demand_mshr_miss_latency::total 1672577269 # number of demand (read+write) MSHR miss cycles -system.cpu5.l1c.overall_mshr_miss_latency::cpu5 1672577269 # number of overall MSHR miss cycles -system.cpu5.l1c.overall_mshr_miss_latency::total 1672577269 # number of overall MSHR miss cycles -system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::cpu5 694440055 # number of ReadReq MSHR uncacheable cycles -system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::total 694440055 # number of ReadReq MSHR uncacheable cycles -system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::cpu5 1653385505 # number of WriteReq MSHR uncacheable cycles -system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::total 1653385505 # number of WriteReq MSHR uncacheable cycles -system.cpu5.l1c.overall_mshr_uncacheable_latency::cpu5 2347825560 # number of overall MSHR uncacheable cycles -system.cpu5.l1c.overall_mshr_uncacheable_latency::total 2347825560 # number of overall MSHR uncacheable cycles -system.cpu5.l1c.ReadReq_mshr_miss_rate::cpu5 0.806533 # mshr miss rate for ReadReq accesses -system.cpu5.l1c.ReadReq_mshr_miss_rate::total 0.806533 # mshr miss rate for ReadReq accesses -system.cpu5.l1c.WriteReq_mshr_miss_rate::cpu5 0.954527 # mshr miss rate for WriteReq accesses -system.cpu5.l1c.WriteReq_mshr_miss_rate::total 0.954527 # mshr miss rate for WriteReq accesses -system.cpu5.l1c.demand_mshr_miss_rate::cpu5 0.858711 # mshr miss rate for demand accesses -system.cpu5.l1c.demand_mshr_miss_rate::total 0.858711 # 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average ReadReq mshr miss latency +system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::total 24145.633904 # average ReadReq mshr miss latency +system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::cpu5 35278.884981 # average WriteReq mshr miss latency +system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::total 35278.884981 # average WriteReq mshr miss latency +system.cpu5.l1c.demand_avg_mshr_miss_latency::cpu5 28481.349854 # average overall mshr miss latency +system.cpu5.l1c.demand_avg_mshr_miss_latency::total 28481.349854 # average overall mshr miss latency +system.cpu5.l1c.overall_avg_mshr_miss_latency::cpu5 28481.349854 # average overall mshr miss latency +system.cpu5.l1c.overall_avg_mshr_miss_latency::total 28481.349854 # average overall mshr miss latency system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu5 inf # average ReadReq mshr uncacheable latency system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu5 inf # average WriteReq mshr uncacheable latency @@ -1420,114 +1418,114 @@ system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::cpu5 inf # average overall mshr uncacheable latency system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu5.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu6.num_reads 99583 # number of read accesses completed -system.cpu6.num_writes 53438 # number of write accesses completed +system.cpu6.num_reads 99897 # number of read accesses completed +system.cpu6.num_writes 53584 # number of write accesses completed system.cpu6.num_copies 0 # number of copy accesses completed -system.cpu6.l1c.replacements 21939 # number of replacements -system.cpu6.l1c.tagsinuse 394.903585 # Cycle average of tags in use -system.cpu6.l1c.total_refs 13339 # Total number of references to valid blocks. -system.cpu6.l1c.sampled_refs 22346 # Sample count of references to valid blocks. -system.cpu6.l1c.avg_refs 0.596930 # Average number of references to valid blocks. -system.cpu6.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu6.l1c.occ_blocks::cpu6 394.903585 # Average occupied blocks per requestor -system.cpu6.l1c.occ_percent::cpu6 0.771296 # Average percentage of cache occupancy -system.cpu6.l1c.occ_percent::total 0.771296 # Average percentage of cache occupancy -system.cpu6.l1c.ReadReq_hits::cpu6 8764 # number of ReadReq hits -system.cpu6.l1c.ReadReq_hits::total 8764 # number of ReadReq hits -system.cpu6.l1c.WriteReq_hits::cpu6 1067 # number of WriteReq hits -system.cpu6.l1c.WriteReq_hits::total 1067 # number of WriteReq hits -system.cpu6.l1c.demand_hits::cpu6 9831 # number of demand (read+write) hits -system.cpu6.l1c.demand_hits::total 9831 # number of demand (read+write) hits -system.cpu6.l1c.overall_hits::cpu6 9831 # number of overall hits -system.cpu6.l1c.overall_hits::total 9831 # number of overall hits -system.cpu6.l1c.ReadReq_misses::cpu6 36046 # number of ReadReq misses -system.cpu6.l1c.ReadReq_misses::total 36046 # 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number of overall miss cycles -system.cpu6.l1c.overall_miss_latency::total 1784076243 # number of overall miss cycles -system.cpu6.l1c.ReadReq_accesses::cpu6 44810 # number of ReadReq accesses(hits+misses) -system.cpu6.l1c.ReadReq_accesses::total 44810 # number of ReadReq accesses(hits+misses) -system.cpu6.l1c.WriteReq_accesses::cpu6 23962 # number of WriteReq accesses(hits+misses) -system.cpu6.l1c.WriteReq_accesses::total 23962 # number of WriteReq accesses(hits+misses) -system.cpu6.l1c.demand_accesses::cpu6 68772 # number of demand (read+write) accesses -system.cpu6.l1c.demand_accesses::total 68772 # number of demand (read+write) accesses -system.cpu6.l1c.overall_accesses::cpu6 68772 # number of overall (read+write) accesses -system.cpu6.l1c.overall_accesses::total 68772 # number of overall (read+write) accesses -system.cpu6.l1c.ReadReq_miss_rate::cpu6 0.804419 # miss rate for ReadReq accesses -system.cpu6.l1c.ReadReq_miss_rate::total 0.804419 # miss rate for ReadReq accesses -system.cpu6.l1c.WriteReq_miss_rate::cpu6 0.955471 # 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average overall miss latency -system.cpu6.l1c.overall_avg_miss_latency::total 30268.849239 # average overall miss latency -system.cpu6.l1c.blocked_cycles::no_mshrs 1009249 # number of cycles access was blocked +system.cpu6.l1c.tags.replacements 22385 # number of replacements +system.cpu6.l1c.tags.tagsinuse 395.582005 # Cycle average of tags in use +system.cpu6.l1c.tags.total_refs 13337 # Total number of references to valid blocks. +system.cpu6.l1c.tags.sampled_refs 22793 # Sample count of references to valid blocks. +system.cpu6.l1c.tags.avg_refs 0.585136 # Average number of references to valid blocks. +system.cpu6.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu6.l1c.tags.occ_blocks::cpu6 395.582005 # Average occupied blocks per requestor +system.cpu6.l1c.tags.occ_percent::cpu6 0.772621 # Average percentage of cache occupancy +system.cpu6.l1c.tags.occ_percent::total 0.772621 # Average percentage of cache occupancy +system.cpu6.l1c.ReadReq_hits::cpu6 8715 # number of ReadReq hits +system.cpu6.l1c.ReadReq_hits::total 8715 # number of ReadReq hits +system.cpu6.l1c.WriteReq_hits::cpu6 1094 # number of WriteReq hits +system.cpu6.l1c.WriteReq_hits::total 1094 # number of WriteReq hits +system.cpu6.l1c.demand_hits::cpu6 9809 # number of demand (read+write) hits +system.cpu6.l1c.demand_hits::total 9809 # number of demand (read+write) hits +system.cpu6.l1c.overall_hits::cpu6 9809 # number of overall hits +system.cpu6.l1c.overall_hits::total 9809 # number of overall hits +system.cpu6.l1c.ReadReq_misses::cpu6 36235 # number of ReadReq misses +system.cpu6.l1c.ReadReq_misses::total 36235 # number of ReadReq misses +system.cpu6.l1c.WriteReq_misses::cpu6 23035 # number of WriteReq misses +system.cpu6.l1c.WriteReq_misses::total 23035 # number of WriteReq misses +system.cpu6.l1c.demand_misses::cpu6 59270 # number of demand (read+write) misses +system.cpu6.l1c.demand_misses::total 59270 # number of demand (read+write) misses +system.cpu6.l1c.overall_misses::cpu6 59270 # number of overall misses +system.cpu6.l1c.overall_misses::total 59270 # number of overall misses +system.cpu6.l1c.ReadReq_miss_latency::cpu6 950668375 # number of ReadReq miss cycles +system.cpu6.l1c.ReadReq_miss_latency::total 950668375 # number of ReadReq miss cycles +system.cpu6.l1c.WriteReq_miss_latency::cpu6 850880053 # number of WriteReq miss cycles +system.cpu6.l1c.WriteReq_miss_latency::total 850880053 # number of WriteReq miss cycles +system.cpu6.l1c.demand_miss_latency::cpu6 1801548428 # number of demand (read+write) miss cycles +system.cpu6.l1c.demand_miss_latency::total 1801548428 # number of demand (read+write) miss cycles +system.cpu6.l1c.overall_miss_latency::cpu6 1801548428 # number of overall miss cycles +system.cpu6.l1c.overall_miss_latency::total 1801548428 # number of overall miss cycles +system.cpu6.l1c.ReadReq_accesses::cpu6 44950 # number of ReadReq accesses(hits+misses) +system.cpu6.l1c.ReadReq_accesses::total 44950 # number of ReadReq accesses(hits+misses) +system.cpu6.l1c.WriteReq_accesses::cpu6 24129 # number of WriteReq accesses(hits+misses) +system.cpu6.l1c.WriteReq_accesses::total 24129 # number of WriteReq accesses(hits+misses) +system.cpu6.l1c.demand_accesses::cpu6 69079 # number of demand (read+write) accesses +system.cpu6.l1c.demand_accesses::total 69079 # number of demand (read+write) accesses +system.cpu6.l1c.overall_accesses::cpu6 69079 # number of overall (read+write) accesses +system.cpu6.l1c.overall_accesses::total 69079 # number of overall (read+write) accesses +system.cpu6.l1c.ReadReq_miss_rate::cpu6 0.806118 # miss rate for ReadReq accesses +system.cpu6.l1c.ReadReq_miss_rate::total 0.806118 # miss rate for ReadReq accesses +system.cpu6.l1c.WriteReq_miss_rate::cpu6 0.954660 # miss rate for WriteReq accesses +system.cpu6.l1c.WriteReq_miss_rate::total 0.954660 # miss rate for WriteReq accesses +system.cpu6.l1c.demand_miss_rate::cpu6 0.858003 # miss rate for demand accesses +system.cpu6.l1c.demand_miss_rate::total 0.858003 # miss rate for demand accesses +system.cpu6.l1c.overall_miss_rate::cpu6 0.858003 # miss rate for overall accesses +system.cpu6.l1c.overall_miss_rate::total 0.858003 # miss rate for overall accesses +system.cpu6.l1c.ReadReq_avg_miss_latency::cpu6 26236.190838 # average ReadReq miss latency +system.cpu6.l1c.ReadReq_avg_miss_latency::total 26236.190838 # average ReadReq miss latency +system.cpu6.l1c.WriteReq_avg_miss_latency::cpu6 36938.574040 # average WriteReq miss latency +system.cpu6.l1c.WriteReq_avg_miss_latency::total 36938.574040 # average WriteReq miss latency +system.cpu6.l1c.demand_avg_miss_latency::cpu6 30395.620516 # average overall miss latency +system.cpu6.l1c.demand_avg_miss_latency::total 30395.620516 # average overall miss latency +system.cpu6.l1c.overall_avg_miss_latency::cpu6 30395.620516 # average overall miss latency +system.cpu6.l1c.overall_avg_miss_latency::total 30395.620516 # average overall miss latency +system.cpu6.l1c.blocked_cycles::no_mshrs 1011987 # number of cycles access was blocked system.cpu6.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu6.l1c.blocked::no_mshrs 61784 # number of cycles access was blocked +system.cpu6.l1c.blocked::no_mshrs 61933 # number of cycles access was blocked system.cpu6.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu6.l1c.avg_blocked_cycles::no_mshrs 16.335119 # average number of cycles each access was blocked +system.cpu6.l1c.avg_blocked_cycles::no_mshrs 16.340029 # average number of cycles each access was blocked system.cpu6.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu6.l1c.fast_writes 0 # number of fast writes performed system.cpu6.l1c.cache_copies 0 # number of cache copies performed -system.cpu6.l1c.writebacks::writebacks 9560 # number of writebacks -system.cpu6.l1c.writebacks::total 9560 # number of writebacks -system.cpu6.l1c.ReadReq_mshr_misses::cpu6 36046 # number of ReadReq MSHR misses -system.cpu6.l1c.ReadReq_mshr_misses::total 36046 # number of ReadReq MSHR misses -system.cpu6.l1c.WriteReq_mshr_misses::cpu6 22895 # number of WriteReq MSHR misses -system.cpu6.l1c.WriteReq_mshr_misses::total 22895 # number of WriteReq MSHR misses -system.cpu6.l1c.demand_mshr_misses::cpu6 58941 # number of demand (read+write) MSHR misses -system.cpu6.l1c.demand_mshr_misses::total 58941 # number of demand (read+write) MSHR misses -system.cpu6.l1c.overall_mshr_misses::cpu6 58941 # number of overall MSHR misses -system.cpu6.l1c.overall_mshr_misses::total 58941 # number of overall MSHR misses -system.cpu6.l1c.ReadReq_mshr_miss_latency::cpu6 863686811 # number of ReadReq MSHR miss cycles -system.cpu6.l1c.ReadReq_mshr_miss_latency::total 863686811 # number of ReadReq MSHR miss cycles -system.cpu6.l1c.WriteReq_mshr_miss_latency::cpu6 798668072 # number of WriteReq MSHR miss cycles -system.cpu6.l1c.WriteReq_mshr_miss_latency::total 798668072 # number of WriteReq MSHR miss cycles -system.cpu6.l1c.demand_mshr_miss_latency::cpu6 1662354883 # number of demand (read+write) MSHR miss cycles -system.cpu6.l1c.demand_mshr_miss_latency::total 1662354883 # number of demand (read+write) MSHR miss cycles -system.cpu6.l1c.overall_mshr_miss_latency::cpu6 1662354883 # number of overall MSHR miss cycles -system.cpu6.l1c.overall_mshr_miss_latency::total 1662354883 # number of overall MSHR miss cycles -system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::cpu6 702782954 # number of ReadReq MSHR uncacheable cycles -system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::total 702782954 # number of ReadReq MSHR uncacheable cycles -system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::cpu6 1637437633 # number of WriteReq MSHR uncacheable cycles -system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::total 1637437633 # number of WriteReq MSHR uncacheable cycles -system.cpu6.l1c.overall_mshr_uncacheable_latency::cpu6 2340220587 # number of overall MSHR uncacheable cycles -system.cpu6.l1c.overall_mshr_uncacheable_latency::total 2340220587 # number of overall MSHR uncacheable cycles -system.cpu6.l1c.ReadReq_mshr_miss_rate::cpu6 0.804419 # mshr miss rate for ReadReq accesses -system.cpu6.l1c.ReadReq_mshr_miss_rate::total 0.804419 # mshr miss rate for ReadReq accesses -system.cpu6.l1c.WriteReq_mshr_miss_rate::cpu6 0.955471 # mshr miss rate for WriteReq accesses -system.cpu6.l1c.WriteReq_mshr_miss_rate::total 0.955471 # mshr miss rate for WriteReq accesses -system.cpu6.l1c.demand_mshr_miss_rate::cpu6 0.857049 # mshr miss rate for demand accesses -system.cpu6.l1c.demand_mshr_miss_rate::total 0.857049 # mshr miss rate for demand accesses -system.cpu6.l1c.overall_mshr_miss_rate::cpu6 0.857049 # mshr miss rate for overall accesses -system.cpu6.l1c.overall_mshr_miss_rate::total 0.857049 # mshr miss rate for overall accesses -system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::cpu6 23960.683876 # average ReadReq mshr miss latency -system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::total 23960.683876 # average ReadReq mshr miss latency -system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::cpu6 34883.951605 # average WriteReq mshr miss latency -system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::total 34883.951605 # average WriteReq mshr miss latency -system.cpu6.l1c.demand_avg_mshr_miss_latency::cpu6 28203.710202 # average overall mshr miss latency -system.cpu6.l1c.demand_avg_mshr_miss_latency::total 28203.710202 # average overall mshr miss latency -system.cpu6.l1c.overall_avg_mshr_miss_latency::cpu6 28203.710202 # average overall mshr miss latency -system.cpu6.l1c.overall_avg_mshr_miss_latency::total 28203.710202 # average overall mshr miss latency +system.cpu6.l1c.writebacks::writebacks 9690 # number of writebacks +system.cpu6.l1c.writebacks::total 9690 # number of writebacks +system.cpu6.l1c.ReadReq_mshr_misses::cpu6 36235 # number of ReadReq MSHR misses +system.cpu6.l1c.ReadReq_mshr_misses::total 36235 # number of ReadReq MSHR misses +system.cpu6.l1c.WriteReq_mshr_misses::cpu6 23035 # number of WriteReq MSHR misses +system.cpu6.l1c.WriteReq_mshr_misses::total 23035 # number of WriteReq MSHR misses +system.cpu6.l1c.demand_mshr_misses::cpu6 59270 # number of demand (read+write) MSHR misses +system.cpu6.l1c.demand_mshr_misses::total 59270 # number of demand (read+write) MSHR misses +system.cpu6.l1c.overall_mshr_misses::cpu6 59270 # number of overall MSHR misses +system.cpu6.l1c.overall_mshr_misses::total 59270 # number of overall MSHR misses +system.cpu6.l1c.ReadReq_mshr_miss_latency::cpu6 873220563 # number of ReadReq MSHR miss cycles +system.cpu6.l1c.ReadReq_mshr_miss_latency::total 873220563 # number of ReadReq MSHR miss cycles +system.cpu6.l1c.WriteReq_mshr_miss_latency::cpu6 802141037 # number of WriteReq MSHR miss cycles +system.cpu6.l1c.WriteReq_mshr_miss_latency::total 802141037 # number of WriteReq MSHR miss cycles +system.cpu6.l1c.demand_mshr_miss_latency::cpu6 1675361600 # number of demand (read+write) MSHR miss cycles +system.cpu6.l1c.demand_mshr_miss_latency::total 1675361600 # number of demand (read+write) MSHR miss cycles +system.cpu6.l1c.overall_mshr_miss_latency::cpu6 1675361600 # number of overall MSHR miss cycles +system.cpu6.l1c.overall_mshr_miss_latency::total 1675361600 # number of overall MSHR miss cycles +system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::cpu6 697661939 # number of ReadReq MSHR uncacheable cycles +system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::total 697661939 # number of ReadReq MSHR uncacheable cycles +system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::cpu6 1639994129 # number of WriteReq MSHR uncacheable cycles +system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::total 1639994129 # number of WriteReq MSHR uncacheable cycles +system.cpu6.l1c.overall_mshr_uncacheable_latency::cpu6 2337656068 # number of overall MSHR uncacheable cycles +system.cpu6.l1c.overall_mshr_uncacheable_latency::total 2337656068 # number of overall MSHR uncacheable cycles +system.cpu6.l1c.ReadReq_mshr_miss_rate::cpu6 0.806118 # mshr miss rate for ReadReq accesses +system.cpu6.l1c.ReadReq_mshr_miss_rate::total 0.806118 # mshr miss rate for ReadReq accesses +system.cpu6.l1c.WriteReq_mshr_miss_rate::cpu6 0.954660 # mshr miss rate for WriteReq accesses +system.cpu6.l1c.WriteReq_mshr_miss_rate::total 0.954660 # mshr miss rate for WriteReq accesses +system.cpu6.l1c.demand_mshr_miss_rate::cpu6 0.858003 # mshr miss rate for demand accesses +system.cpu6.l1c.demand_mshr_miss_rate::total 0.858003 # mshr miss rate for demand accesses +system.cpu6.l1c.overall_mshr_miss_rate::cpu6 0.858003 # mshr miss rate for overall accesses +system.cpu6.l1c.overall_mshr_miss_rate::total 0.858003 # mshr miss rate for overall accesses +system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::cpu6 24098.815041 # average ReadReq mshr miss latency +system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::total 24098.815041 # average ReadReq mshr miss latency +system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::cpu6 34822.706186 # average WriteReq mshr miss latency +system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::total 34822.706186 # average WriteReq mshr miss latency +system.cpu6.l1c.demand_avg_mshr_miss_latency::cpu6 28266.603678 # average overall mshr miss latency +system.cpu6.l1c.demand_avg_mshr_miss_latency::total 28266.603678 # average overall mshr miss latency +system.cpu6.l1c.overall_avg_mshr_miss_latency::cpu6 28266.603678 # average overall mshr miss latency +system.cpu6.l1c.overall_avg_mshr_miss_latency::total 28266.603678 # average overall mshr miss latency system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu6 inf # average ReadReq mshr uncacheable latency system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu6 inf # average WriteReq mshr uncacheable latency @@ -1535,114 +1533,114 @@ system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::cpu6 inf # average overall mshr uncacheable latency system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu6.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu7.num_reads 99199 # number of read accesses completed -system.cpu7.num_writes 53517 # number of write accesses completed +system.cpu7.num_reads 99207 # number of read accesses completed +system.cpu7.num_writes 53401 # number of write accesses completed system.cpu7.num_copies 0 # number of copy accesses completed -system.cpu7.l1c.replacements 22063 # number of replacements -system.cpu7.l1c.tagsinuse 393.496696 # Cycle average of tags in use -system.cpu7.l1c.total_refs 13289 # Total number of references to valid blocks. -system.cpu7.l1c.sampled_refs 22472 # Sample count of references to valid blocks. -system.cpu7.l1c.avg_refs 0.591358 # Average number of references to valid blocks. -system.cpu7.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu7.l1c.occ_blocks::cpu7 393.496696 # Average occupied blocks per requestor -system.cpu7.l1c.occ_percent::cpu7 0.768548 # Average percentage of cache occupancy -system.cpu7.l1c.occ_percent::total 0.768548 # Average percentage of cache occupancy -system.cpu7.l1c.ReadReq_hits::cpu7 8670 # number of ReadReq hits -system.cpu7.l1c.ReadReq_hits::total 8670 # number of ReadReq hits -system.cpu7.l1c.WriteReq_hits::cpu7 1128 # number of WriteReq hits -system.cpu7.l1c.WriteReq_hits::total 1128 # number of WriteReq hits -system.cpu7.l1c.demand_hits::cpu7 9798 # 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number of WriteReq miss cycles -system.cpu7.l1c.WriteReq_miss_latency::total 860844547 # number of WriteReq miss cycles -system.cpu7.l1c.demand_miss_latency::cpu7 1794181629 # number of demand (read+write) miss cycles -system.cpu7.l1c.demand_miss_latency::total 1794181629 # number of demand (read+write) miss cycles -system.cpu7.l1c.overall_miss_latency::cpu7 1794181629 # number of overall miss cycles -system.cpu7.l1c.overall_miss_latency::total 1794181629 # number of overall miss cycles -system.cpu7.l1c.ReadReq_accesses::cpu7 44596 # number of ReadReq accesses(hits+misses) -system.cpu7.l1c.ReadReq_accesses::total 44596 # number of ReadReq accesses(hits+misses) -system.cpu7.l1c.WriteReq_accesses::cpu7 24267 # number of WriteReq accesses(hits+misses) -system.cpu7.l1c.WriteReq_accesses::total 24267 # number of WriteReq accesses(hits+misses) -system.cpu7.l1c.demand_accesses::cpu7 68863 # number of demand (read+write) accesses -system.cpu7.l1c.demand_accesses::total 68863 # number of demand (read+write) accesses -system.cpu7.l1c.overall_accesses::cpu7 68863 # number of overall (read+write) accesses -system.cpu7.l1c.overall_accesses::total 68863 # number of overall (read+write) accesses -system.cpu7.l1c.ReadReq_miss_rate::cpu7 0.805588 # miss rate for ReadReq accesses -system.cpu7.l1c.ReadReq_miss_rate::total 0.805588 # miss rate for ReadReq accesses -system.cpu7.l1c.WriteReq_miss_rate::cpu7 0.953517 # miss rate for WriteReq accesses -system.cpu7.l1c.WriteReq_miss_rate::total 0.953517 # miss rate for WriteReq accesses -system.cpu7.l1c.demand_miss_rate::cpu7 0.857717 # miss rate for demand accesses -system.cpu7.l1c.demand_miss_rate::total 0.857717 # miss rate for demand accesses -system.cpu7.l1c.overall_miss_rate::cpu7 0.857717 # miss rate for overall accesses -system.cpu7.l1c.overall_miss_rate::total 0.857717 # miss rate for overall accesses -system.cpu7.l1c.ReadReq_avg_miss_latency::cpu7 25979.432222 # average ReadReq miss latency -system.cpu7.l1c.ReadReq_avg_miss_latency::total 25979.432222 # average ReadReq miss latency -system.cpu7.l1c.WriteReq_avg_miss_latency::cpu7 37203.187130 # average WriteReq miss latency -system.cpu7.l1c.WriteReq_avg_miss_latency::total 37203.187130 # average WriteReq miss latency -system.cpu7.l1c.demand_avg_miss_latency::cpu7 30376.392601 # average overall miss latency -system.cpu7.l1c.demand_avg_miss_latency::total 30376.392601 # average overall miss latency -system.cpu7.l1c.overall_avg_miss_latency::cpu7 30376.392601 # average overall miss latency -system.cpu7.l1c.overall_avg_miss_latency::total 30376.392601 # average overall miss latency -system.cpu7.l1c.blocked_cycles::no_mshrs 1011426 # number of cycles access was blocked +system.cpu7.l1c.tags.replacements 22143 # number of replacements +system.cpu7.l1c.tags.tagsinuse 394.587693 # Cycle average of tags in use +system.cpu7.l1c.tags.total_refs 13403 # Total number of references to valid blocks. +system.cpu7.l1c.tags.sampled_refs 22544 # Sample count of references to valid blocks. +system.cpu7.l1c.tags.avg_refs 0.594526 # Average number of references to valid blocks. +system.cpu7.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu7.l1c.tags.occ_blocks::cpu7 394.587693 # Average occupied blocks per requestor +system.cpu7.l1c.tags.occ_percent::cpu7 0.770679 # Average percentage of cache occupancy +system.cpu7.l1c.tags.occ_percent::total 0.770679 # Average percentage of cache occupancy +system.cpu7.l1c.ReadReq_hits::cpu7 8635 # number of ReadReq hits +system.cpu7.l1c.ReadReq_hits::total 8635 # number of ReadReq hits +system.cpu7.l1c.WriteReq_hits::cpu7 1078 # number of WriteReq hits +system.cpu7.l1c.WriteReq_hits::total 1078 # number of WriteReq hits +system.cpu7.l1c.demand_hits::cpu7 9713 # number of demand (read+write) hits +system.cpu7.l1c.demand_hits::total 9713 # number of demand (read+write) hits +system.cpu7.l1c.overall_hits::cpu7 9713 # number of overall hits +system.cpu7.l1c.overall_hits::total 9713 # number of overall hits +system.cpu7.l1c.ReadReq_misses::cpu7 36141 # number of ReadReq misses +system.cpu7.l1c.ReadReq_misses::total 36141 # number of ReadReq misses +system.cpu7.l1c.WriteReq_misses::cpu7 23098 # number of WriteReq misses +system.cpu7.l1c.WriteReq_misses::total 23098 # number of WriteReq misses +system.cpu7.l1c.demand_misses::cpu7 59239 # number of demand (read+write) misses +system.cpu7.l1c.demand_misses::total 59239 # number of demand (read+write) misses +system.cpu7.l1c.overall_misses::cpu7 59239 # number of overall misses +system.cpu7.l1c.overall_misses::total 59239 # number of overall misses +system.cpu7.l1c.ReadReq_miss_latency::cpu7 942615817 # number of ReadReq miss cycles +system.cpu7.l1c.ReadReq_miss_latency::total 942615817 # number of ReadReq miss cycles +system.cpu7.l1c.WriteReq_miss_latency::cpu7 859348059 # number of WriteReq miss cycles +system.cpu7.l1c.WriteReq_miss_latency::total 859348059 # number of WriteReq miss cycles +system.cpu7.l1c.demand_miss_latency::cpu7 1801963876 # number of demand (read+write) miss cycles +system.cpu7.l1c.demand_miss_latency::total 1801963876 # number of demand (read+write) miss cycles +system.cpu7.l1c.overall_miss_latency::cpu7 1801963876 # number of overall miss cycles +system.cpu7.l1c.overall_miss_latency::total 1801963876 # number of overall miss cycles +system.cpu7.l1c.ReadReq_accesses::cpu7 44776 # number of ReadReq accesses(hits+misses) +system.cpu7.l1c.ReadReq_accesses::total 44776 # number of ReadReq accesses(hits+misses) +system.cpu7.l1c.WriteReq_accesses::cpu7 24176 # number of WriteReq accesses(hits+misses) +system.cpu7.l1c.WriteReq_accesses::total 24176 # number of WriteReq accesses(hits+misses) +system.cpu7.l1c.demand_accesses::cpu7 68952 # number of demand (read+write) accesses +system.cpu7.l1c.demand_accesses::total 68952 # number of demand (read+write) accesses +system.cpu7.l1c.overall_accesses::cpu7 68952 # number of overall (read+write) accesses +system.cpu7.l1c.overall_accesses::total 68952 # number of overall (read+write) accesses +system.cpu7.l1c.ReadReq_miss_rate::cpu7 0.807151 # miss rate for ReadReq accesses +system.cpu7.l1c.ReadReq_miss_rate::total 0.807151 # miss rate for ReadReq accesses +system.cpu7.l1c.WriteReq_miss_rate::cpu7 0.955410 # miss rate for WriteReq accesses +system.cpu7.l1c.WriteReq_miss_rate::total 0.955410 # miss rate for WriteReq accesses +system.cpu7.l1c.demand_miss_rate::cpu7 0.859134 # miss rate for demand accesses +system.cpu7.l1c.demand_miss_rate::total 0.859134 # miss rate for demand accesses +system.cpu7.l1c.overall_miss_rate::cpu7 0.859134 # miss rate for overall accesses +system.cpu7.l1c.overall_miss_rate::total 0.859134 # miss rate for overall accesses +system.cpu7.l1c.ReadReq_avg_miss_latency::cpu7 26081.619684 # average ReadReq miss latency +system.cpu7.l1c.ReadReq_avg_miss_latency::total 26081.619684 # average ReadReq miss latency +system.cpu7.l1c.WriteReq_avg_miss_latency::cpu7 37204.435839 # average WriteReq miss latency +system.cpu7.l1c.WriteReq_avg_miss_latency::total 37204.435839 # average WriteReq miss latency +system.cpu7.l1c.demand_avg_miss_latency::cpu7 30418.539746 # average overall miss latency +system.cpu7.l1c.demand_avg_miss_latency::total 30418.539746 # average overall miss latency +system.cpu7.l1c.overall_avg_miss_latency::cpu7 30418.539746 # average overall miss latency +system.cpu7.l1c.overall_avg_miss_latency::total 30418.539746 # average overall miss latency +system.cpu7.l1c.blocked_cycles::no_mshrs 1024987 # number of cycles access was blocked system.cpu7.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu7.l1c.blocked::no_mshrs 62031 # number of cycles access was blocked +system.cpu7.l1c.blocked::no_mshrs 62690 # number of cycles access was blocked system.cpu7.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu7.l1c.avg_blocked_cycles::no_mshrs 16.305170 # average number of cycles each access was blocked +system.cpu7.l1c.avg_blocked_cycles::no_mshrs 16.350088 # average number of cycles each access was blocked system.cpu7.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu7.l1c.fast_writes 0 # number of fast writes performed system.cpu7.l1c.cache_copies 0 # number of cache copies performed -system.cpu7.l1c.writebacks::writebacks 9494 # number of writebacks -system.cpu7.l1c.writebacks::total 9494 # number of writebacks -system.cpu7.l1c.ReadReq_mshr_misses::cpu7 35926 # number of ReadReq MSHR misses -system.cpu7.l1c.ReadReq_mshr_misses::total 35926 # number of ReadReq MSHR misses -system.cpu7.l1c.WriteReq_mshr_misses::cpu7 23139 # number of WriteReq MSHR misses -system.cpu7.l1c.WriteReq_mshr_misses::total 23139 # number of WriteReq MSHR misses -system.cpu7.l1c.demand_mshr_misses::cpu7 59065 # number of demand (read+write) MSHR misses -system.cpu7.l1c.demand_mshr_misses::total 59065 # number of demand (read+write) MSHR misses -system.cpu7.l1c.overall_mshr_misses::cpu7 59065 # number of overall MSHR misses -system.cpu7.l1c.overall_mshr_misses::total 59065 # number of overall MSHR misses -system.cpu7.l1c.ReadReq_mshr_miss_latency::cpu7 859043599 # number of ReadReq MSHR miss cycles -system.cpu7.l1c.ReadReq_mshr_miss_latency::total 859043599 # number of ReadReq MSHR miss cycles -system.cpu7.l1c.WriteReq_mshr_miss_latency::cpu7 813252475 # number of WriteReq MSHR miss cycles -system.cpu7.l1c.WriteReq_mshr_miss_latency::total 813252475 # number of WriteReq MSHR miss cycles -system.cpu7.l1c.demand_mshr_miss_latency::cpu7 1672296074 # number of demand (read+write) MSHR miss cycles -system.cpu7.l1c.demand_mshr_miss_latency::total 1672296074 # number of demand (read+write) MSHR miss cycles -system.cpu7.l1c.overall_mshr_miss_latency::cpu7 1672296074 # number of overall MSHR miss cycles -system.cpu7.l1c.overall_mshr_miss_latency::total 1672296074 # number of overall MSHR miss cycles -system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::cpu7 693959592 # number of ReadReq MSHR uncacheable cycles -system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::total 693959592 # number of ReadReq MSHR uncacheable cycles -system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::cpu7 1654672592 # number of WriteReq MSHR uncacheable cycles -system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::total 1654672592 # number of WriteReq MSHR uncacheable cycles -system.cpu7.l1c.overall_mshr_uncacheable_latency::cpu7 2348632184 # number of overall MSHR uncacheable cycles -system.cpu7.l1c.overall_mshr_uncacheable_latency::total 2348632184 # number of overall MSHR uncacheable cycles -system.cpu7.l1c.ReadReq_mshr_miss_rate::cpu7 0.805588 # mshr miss rate for ReadReq accesses -system.cpu7.l1c.ReadReq_mshr_miss_rate::total 0.805588 # mshr miss rate for ReadReq accesses -system.cpu7.l1c.WriteReq_mshr_miss_rate::cpu7 0.953517 # mshr miss rate for WriteReq accesses -system.cpu7.l1c.WriteReq_mshr_miss_rate::total 0.953517 # mshr miss rate for WriteReq accesses -system.cpu7.l1c.demand_mshr_miss_rate::cpu7 0.857717 # mshr miss rate for demand accesses -system.cpu7.l1c.demand_mshr_miss_rate::total 0.857717 # mshr miss rate for demand accesses -system.cpu7.l1c.overall_mshr_miss_rate::cpu7 0.857717 # mshr miss rate for overall accesses -system.cpu7.l1c.overall_mshr_miss_rate::total 0.857717 # mshr miss rate for overall accesses -system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::cpu7 23911.473557 # average ReadReq mshr miss latency -system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::total 23911.473557 # average ReadReq mshr miss latency -system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::cpu7 35146.396776 # average WriteReq mshr miss latency -system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::total 35146.396776 # average WriteReq mshr miss latency -system.cpu7.l1c.demand_avg_mshr_miss_latency::cpu7 28312.809176 # average overall mshr miss latency -system.cpu7.l1c.demand_avg_mshr_miss_latency::total 28312.809176 # average overall mshr miss latency -system.cpu7.l1c.overall_avg_mshr_miss_latency::cpu7 28312.809176 # average overall mshr miss latency -system.cpu7.l1c.overall_avg_mshr_miss_latency::total 28312.809176 # average overall mshr miss latency +system.cpu7.l1c.writebacks::writebacks 9629 # number of writebacks +system.cpu7.l1c.writebacks::total 9629 # number of writebacks +system.cpu7.l1c.ReadReq_mshr_misses::cpu7 36141 # number of ReadReq MSHR misses +system.cpu7.l1c.ReadReq_mshr_misses::total 36141 # number of ReadReq MSHR misses +system.cpu7.l1c.WriteReq_mshr_misses::cpu7 23098 # number of WriteReq MSHR misses +system.cpu7.l1c.WriteReq_mshr_misses::total 23098 # number of WriteReq MSHR misses +system.cpu7.l1c.demand_mshr_misses::cpu7 59239 # number of demand (read+write) MSHR misses +system.cpu7.l1c.demand_mshr_misses::total 59239 # number of demand (read+write) MSHR misses +system.cpu7.l1c.overall_mshr_misses::cpu7 59239 # number of overall MSHR misses +system.cpu7.l1c.overall_mshr_misses::total 59239 # number of overall MSHR misses +system.cpu7.l1c.ReadReq_mshr_miss_latency::cpu7 865505701 # number of ReadReq MSHR miss cycles +system.cpu7.l1c.ReadReq_mshr_miss_latency::total 865505701 # number of ReadReq MSHR miss cycles +system.cpu7.l1c.WriteReq_mshr_miss_latency::cpu7 810567819 # number of WriteReq MSHR miss cycles +system.cpu7.l1c.WriteReq_mshr_miss_latency::total 810567819 # number of WriteReq MSHR miss cycles +system.cpu7.l1c.demand_mshr_miss_latency::cpu7 1676073520 # number of demand (read+write) MSHR miss cycles +system.cpu7.l1c.demand_mshr_miss_latency::total 1676073520 # number of demand (read+write) MSHR miss cycles +system.cpu7.l1c.overall_mshr_miss_latency::cpu7 1676073520 # number of overall MSHR miss cycles +system.cpu7.l1c.overall_mshr_miss_latency::total 1676073520 # number of overall MSHR miss cycles +system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::cpu7 711693302 # number of ReadReq MSHR uncacheable cycles +system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::total 711693302 # number of ReadReq MSHR uncacheable cycles +system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::cpu7 1603062205 # number of WriteReq MSHR uncacheable cycles +system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::total 1603062205 # number of WriteReq MSHR uncacheable cycles +system.cpu7.l1c.overall_mshr_uncacheable_latency::cpu7 2314755507 # number of overall MSHR uncacheable cycles +system.cpu7.l1c.overall_mshr_uncacheable_latency::total 2314755507 # number of overall MSHR uncacheable cycles +system.cpu7.l1c.ReadReq_mshr_miss_rate::cpu7 0.807151 # mshr miss rate for ReadReq accesses +system.cpu7.l1c.ReadReq_mshr_miss_rate::total 0.807151 # mshr miss rate for ReadReq accesses +system.cpu7.l1c.WriteReq_mshr_miss_rate::cpu7 0.955410 # mshr miss rate for WriteReq accesses +system.cpu7.l1c.WriteReq_mshr_miss_rate::total 0.955410 # mshr miss rate for WriteReq accesses +system.cpu7.l1c.demand_mshr_miss_rate::cpu7 0.859134 # mshr miss rate for demand accesses +system.cpu7.l1c.demand_mshr_miss_rate::total 0.859134 # mshr miss rate for demand accesses +system.cpu7.l1c.overall_mshr_miss_rate::cpu7 0.859134 # mshr miss rate for overall accesses +system.cpu7.l1c.overall_mshr_miss_rate::total 0.859134 # mshr miss rate for overall accesses +system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::cpu7 23948.028582 # average ReadReq mshr miss latency +system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::total 23948.028582 # average ReadReq mshr miss latency +system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::cpu7 35092.554290 # average WriteReq mshr miss latency +system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::total 35092.554290 # average WriteReq mshr miss latency +system.cpu7.l1c.demand_avg_mshr_miss_latency::cpu7 28293.413461 # average overall mshr miss latency +system.cpu7.l1c.demand_avg_mshr_miss_latency::total 28293.413461 # average overall mshr miss latency +system.cpu7.l1c.overall_avg_mshr_miss_latency::cpu7 28293.413461 # average overall mshr miss latency +system.cpu7.l1c.overall_avg_mshr_miss_latency::total 28293.413461 # average overall mshr miss latency system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu7 inf # average ReadReq mshr uncacheable latency system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu7 inf # average WriteReq mshr uncacheable latency diff --git a/tests/quick/se/70.tgen/ref/arm/linux/tgen-simple-dram/stats.txt b/tests/quick/se/70.tgen/ref/arm/linux/tgen-simple-dram/stats.txt index 39565381c..ff9167bb3 100644 --- a/tests/quick/se/70.tgen/ref/arm/linux/tgen-simple-dram/stats.txt +++ b/tests/quick/se/70.tgen/ref/arm/linux/tgen-simple-dram/stats.txt @@ -4,9 +4,9 @@ sim_seconds 0.100000 # Nu sim_ticks 100000000000 # Number of ticks simulated final_tick 100000000000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_tick_rate 12296459257 # Simulator tick rate (ticks/s) -host_mem_usage 231220 # Number of bytes of host memory used -host_seconds 8.13 # Real time elapsed on the host +host_tick_rate 29067628326 # Simulator tick rate (ticks/s) +host_mem_usage 231288 # Number of bytes of host memory used +host_seconds 3.44 # Real time elapsed on the host system.physmem.bytes_read::cpu 213331136 # Number of bytes read from this memory system.physmem.bytes_read::total 213331136 # Number of bytes read from this memory system.physmem.num_reads::cpu 3333299 # Number of read requests responded to by this memory @@ -519,7 +519,5 @@ system.monitor.writeTransHist::17 0 0.00% 100.00% # Hi system.monitor.writeTransHist::18 0 0.00% 100.00% # Histogram of read transactions per sample period system.monitor.writeTransHist::19 0 0.00% 100.00% # Histogram of read transactions per sample period system.monitor.writeTransHist::total 100 # Histogram of read transactions per sample period -system.monitor.readAddrDist::total 16 # Read address distribution -system.monitor.writeAddrDist::total 16 # Write address distribution ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/70.tgen/ref/arm/linux/tgen-simple-mem/stats.txt b/tests/quick/se/70.tgen/ref/arm/linux/tgen-simple-mem/stats.txt index d0c130b6b..4db87dea6 100644 --- a/tests/quick/se/70.tgen/ref/arm/linux/tgen-simple-mem/stats.txt +++ b/tests/quick/se/70.tgen/ref/arm/linux/tgen-simple-mem/stats.txt @@ -4,9 +4,9 @@ sim_seconds 0.100000 # Nu sim_ticks 100000000000 # Number of ticks simulated final_tick 100000000000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_tick_rate 7576487056 # Simulator tick rate (ticks/s) -host_mem_usage 230980 # Number of bytes of host memory used -host_seconds 13.20 # Real time elapsed on the host +host_tick_rate 14083896029 # Simulator tick rate (ticks/s) +host_mem_usage 231304 # Number of bytes of host memory used +host_seconds 7.10 # Real time elapsed on the host system.physmem.bytes_read::cpu 64 # Number of bytes read from this memory system.physmem.bytes_read::total 64 # Number of bytes read from this memory system.physmem.bytes_written::cpu 213329152 # Number of bytes written to this memory @@ -376,7 +376,5 @@ system.monitor.writeTransHist::34816-36863 0 0.00% 100.00% # system.monitor.writeTransHist::36864-38911 0 0.00% 100.00% # Histogram of read transactions per sample period system.monitor.writeTransHist::38912-40959 0 0.00% 100.00% # Histogram of read transactions per sample period system.monitor.writeTransHist::total 100 # Histogram of read transactions per sample period -system.monitor.readAddrDist::total 16 # Read address distribution -system.monitor.writeAddrDist::total 16 # Write address distribution ---------- End Simulation Statistics ---------- |